Unnamed: 0
int64 1
143k
| directory
stringlengths 39
203
| repo_id
float64 143k
552M
| file_name
stringlengths 3
107
| extension
stringclasses 6
values | no_lines
int64 5
304k
| max_line_len
int64 15
21.6k
| generation_keywords
stringclasses 3
values | license_whitelist_keywords
stringclasses 16
values | license_blacklist_keywords
stringclasses 4
values | icarus_module_spans
stringlengths 8
6.16k
⌀ | icarus_exception
stringlengths 12
124
⌀ | verilator_xml_output_path
stringlengths 60
60
⌀ | verilator_exception
stringlengths 33
1.53M
⌀ | file_index
int64 0
315k
| snippet_type
stringclasses 2
values | snippet
stringlengths 21
9.27M
| snippet_def
stringlengths 9
30.3k
| snippet_body
stringlengths 10
9.27M
| gh_stars
int64 0
1.61k
|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
6,165 | data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/pc.v | 115,487,336 | pc.v | v | 58 | 83 | [] | [] | [] | [(21, 57)] | null | data/verilator_xmls/1c8c90c4-3b12-4549-ba21-7eee5169f30b.xml | null | 6,929 | module | module pc(
input clk,
input rst_n,
input muxer,
input [31:0] addr,
output [31:0] now_addr
);
assign now_addr=nowaddr;
reg [31:0] nowaddr;
reg [31:0] nextaddr;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
nowaddr<=32'hFFFF_FFFB;
end
else
begin
if(nextaddr==32'hFFFF_FFFF)
nowaddr<=0;
else
nowaddr<= ( muxer ? addr : nextaddr);
end
end
always@(*)
begin
nextaddr=nowaddr+32'h4;
end
endmodule | module pc(
input clk,
input rst_n,
input muxer,
input [31:0] addr,
output [31:0] now_addr
); |
assign now_addr=nowaddr;
reg [31:0] nowaddr;
reg [31:0] nextaddr;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
nowaddr<=32'hFFFF_FFFB;
end
else
begin
if(nextaddr==32'hFFFF_FFFF)
nowaddr<=0;
else
nowaddr<= ( muxer ? addr : nextaddr);
end
end
always@(*)
begin
nextaddr=nowaddr+32'h4;
end
endmodule | 0 |
6,166 | data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/REG_MUXER.v | 115,487,336 | REG_MUXER.v | v | 59 | 83 | [] | [] | [] | [(21, 58)] | null | data/verilator_xmls/c94e0a0a-7f04-4165-8e96-7cbf2cc23254.xml | null | 6,931 | module | module REG_MUXER(
input [4:0] reg1,
input [4:0] reg2,
input [4:0] reg3,
input Wr,
input [1:0] optype,
output reg [4:0] regaddr1,
output reg [4:0] regaddr2,
output reg [4:0] regaddr3
);
always@(*)
begin
if(optype==2'h0)
begin
regaddr1=reg1;
regaddr2=reg2;
regaddr3=reg3;
end
else if(optype==2'h1)
begin
if(Wr)
begin
regaddr1=reg1;
regaddr2=reg2;
end
else
begin
regaddr1=reg1;
regaddr3=reg2;
end
end
end
endmodule | module REG_MUXER(
input [4:0] reg1,
input [4:0] reg2,
input [4:0] reg3,
input Wr,
input [1:0] optype,
output reg [4:0] regaddr1,
output reg [4:0] regaddr2,
output reg [4:0] regaddr3
); |
always@(*)
begin
if(optype==2'h0)
begin
regaddr1=reg1;
regaddr2=reg2;
regaddr3=reg3;
end
else if(optype==2'h1)
begin
if(Wr)
begin
regaddr1=reg1;
regaddr2=reg2;
end
else
begin
regaddr1=reg1;
regaddr3=reg2;
end
end
end
endmodule | 0 |
6,167 | data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/top.v | 115,487,336 | top.v | v | 179 | 83 | [] | [] | [] | [(21, 178)] | null | null | 1: b"%Error: data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/top.v:35: Cannot find file containing module: 'pc'\npc u_pc(\n^~\n ... Looked in:\n data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips,data/full_repos/permissive/115487336/pc\n data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips,data/full_repos/permissive/115487336/pc.v\n data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips,data/full_repos/permissive/115487336/pc.sv\n pc\n pc.v\n pc.sv\n obj_dir/pc\n obj_dir/pc.v\n obj_dir/pc.sv\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/top.v:44: Cannot find file containing module: 'ir'\nir u_ir(\n^~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/top.v:60: Cannot find file containing module: 'control'\ncontrol u_control(\n^~~~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/top.v:100: Cannot find file containing module: 'REG_MUXER'\nREG_MUXER u_REG_MUXER(\n^~~~~~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/top.v:112: Cannot find file containing module: 'REG_FILE'\nREG_FILE u_REG_FILE(\n^~~~~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/top.v:139: Cannot find file containing module: 'ALU_MUXER'\nALU_MUXER u_ALU_MUXER(\n^~~~~~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/top.v:149: Cannot find file containing module: 'ALU'\nALU u_ALU(\n^~~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/top.v:160: Cannot find file containing module: 'mem'\nmem u_mem(\n^~~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/top.v:168: Cannot find file containing module: 'branch'\nbranch u_branch(\n^~~~~~\n%Error: Exiting due to 9 error(s)\n" | 6,932 | module | module top(
input clk,
input rst_n
);
wire muxer;
wire [31:0] addr;
wire [31:0] now_addr;
wire [31:0] ir_addr;
assign ir_addr=now_addr>>2;
pc u_pc(
clk,
rst_n,
muxer,
addr,
now_addr
);
wire [31:0] instruction;
ir u_ir(
ir_addr,
instruction
);
wire [4:0] aluop;
wire [1:0] optype;
wire reg_AOM;
wire regwe;
wire memwe;
wire Wr;
wire br;
wire j_or_b;
control u_control(
clk,
rst_n,
instruction,
optype,
aluop,
reg_AOM,
regwe,
Wr,
memwe,
br,
j_or_b
);
wire [4:0] regip1;
assign regip1=instruction[25:21];
wire [4:0] regip2;
assign regip2=instruction[20:16];
wire [4:0] regip3;
assign regip3=instruction[15:11];
wire [31:0] reg_ipdata;
wire [31:0] aluout;
wire [31:0] dout;
assign reg_ipdata=(reg_AOM ? aluout : dout);
wire [31:0] regop1;
wire [31:0] regop2;
wire [4:0] regaddr1;
wire [4:0] regaddr2;
wire [4:0] regaddr3;
REG_MUXER u_REG_MUXER(
regip1,
regip2,
regip3,
Wr,
optype,
regaddr1,
regaddr2,
regaddr3
);
REG_FILE u_REG_FILE(
clk,
rst_n,
regaddr1,
regaddr2,
regaddr3,
reg_ipdata,
regwe,
regop1,
regop2
);
wire [31:0] memipdata;
assign memipdata=regop2;
wire [31:0] aluip1;
wire [31:0] aluip2;
wire nzp;
wire [15:0] imm;
assign imm=instruction[15:0];
wire [25:0] jtypeImm;
assign jtypeImm=instruction[25:0];
ALU_MUXER u_ALU_MUXER(
regop1,
regop2,
imm,
jtypeImm,
optype,
aluip1,
aluip2
);
ALU u_ALU(
aluip1,
aluip2,
aluop,
aluout,
nzp
);
wire [31:0] memaddr;
assign memaddr=aluout>>2;
mem u_mem(
memaddr,
memipdata,
clk,
memwe,
dout
);
branch u_branch(
now_addr,
br,
j_or_b,
nzp,
aluip2,
muxer,
addr
);
endmodule | module top(
input clk,
input rst_n
); |
wire muxer;
wire [31:0] addr;
wire [31:0] now_addr;
wire [31:0] ir_addr;
assign ir_addr=now_addr>>2;
pc u_pc(
clk,
rst_n,
muxer,
addr,
now_addr
);
wire [31:0] instruction;
ir u_ir(
ir_addr,
instruction
);
wire [4:0] aluop;
wire [1:0] optype;
wire reg_AOM;
wire regwe;
wire memwe;
wire Wr;
wire br;
wire j_or_b;
control u_control(
clk,
rst_n,
instruction,
optype,
aluop,
reg_AOM,
regwe,
Wr,
memwe,
br,
j_or_b
);
wire [4:0] regip1;
assign regip1=instruction[25:21];
wire [4:0] regip2;
assign regip2=instruction[20:16];
wire [4:0] regip3;
assign regip3=instruction[15:11];
wire [31:0] reg_ipdata;
wire [31:0] aluout;
wire [31:0] dout;
assign reg_ipdata=(reg_AOM ? aluout : dout);
wire [31:0] regop1;
wire [31:0] regop2;
wire [4:0] regaddr1;
wire [4:0] regaddr2;
wire [4:0] regaddr3;
REG_MUXER u_REG_MUXER(
regip1,
regip2,
regip3,
Wr,
optype,
regaddr1,
regaddr2,
regaddr3
);
REG_FILE u_REG_FILE(
clk,
rst_n,
regaddr1,
regaddr2,
regaddr3,
reg_ipdata,
regwe,
regop1,
regop2
);
wire [31:0] memipdata;
assign memipdata=regop2;
wire [31:0] aluip1;
wire [31:0] aluip2;
wire nzp;
wire [15:0] imm;
assign imm=instruction[15:0];
wire [25:0] jtypeImm;
assign jtypeImm=instruction[25:0];
ALU_MUXER u_ALU_MUXER(
regop1,
regop2,
imm,
jtypeImm,
optype,
aluip1,
aluip2
);
ALU u_ALU(
aluip1,
aluip2,
aluop,
aluout,
nzp
);
wire [31:0] memaddr;
assign memaddr=aluout>>2;
mem u_mem(
memaddr,
memipdata,
clk,
memwe,
dout
);
branch u_branch(
now_addr,
br,
j_or_b,
nzp,
aluip2,
muxer,
addr
);
endmodule | 0 |
6,168 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/ALU.v | 115,487,336 | ALU.v | v | 66 | 83 | [] | [] | [] | [(21, 65)] | null | data/verilator_xmls/0f4a93a3-a816-49f2-ae77-3dcf2652f9ef.xml | null | 6,935 | module | module ALU(
input signed [31:0] alu_a,
input signed [31:0] alu_b,
input [4:0] alu_op,
output [31:0] alu_out,
output reg flag
);
assign alu_out = alu_out2;
reg [31:0] alu_out2;
always @(*)
begin
case(alu_op)
5'h0:
alu_out2=32'b0;
5'h1:
alu_out2=alu_a+alu_b;
5'h2:
alu_out2=alu_a-alu_b;
5'h3:
alu_out2=alu_a&alu_b;
5'h4:
alu_out2=alu_a|alu_b;
5'h5:
alu_out2=alu_a^alu_b;
5'h6:
alu_out2=~(alu_a|alu_b);
5'h7:
begin
if(alu_a[31]==0 && (!(alu_a==32'b0)))
flag=1;
else
flag=0;
end
default:
alu_out2=32'hcccccccc;
endcase
end
endmodule | module ALU(
input signed [31:0] alu_a,
input signed [31:0] alu_b,
input [4:0] alu_op,
output [31:0] alu_out,
output reg flag
); |
assign alu_out = alu_out2;
reg [31:0] alu_out2;
always @(*)
begin
case(alu_op)
5'h0:
alu_out2=32'b0;
5'h1:
alu_out2=alu_a+alu_b;
5'h2:
alu_out2=alu_a-alu_b;
5'h3:
alu_out2=alu_a&alu_b;
5'h4:
alu_out2=alu_a|alu_b;
5'h5:
alu_out2=alu_a^alu_b;
5'h6:
alu_out2=~(alu_a|alu_b);
5'h7:
begin
if(alu_a[31]==0 && (!(alu_a==32'b0)))
flag=1;
else
flag=0;
end
default:
alu_out2=32'hcccccccc;
endcase
end
endmodule | 0 |
6,169 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/ALUmodule.v | 115,487,336 | ALUmodule.v | v | 90 | 83 | [] | [] | [] | [(21, 89)] | null | null | 1: b"%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/ALUmodule.v:59: Cannot find file containing module: 'ALU'\nALU u_ALU(\n^~~\n ... Looked in:\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/ALU\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/ALU.v\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/ALU.sv\n ALU\n ALU.v\n ALU.sv\n obj_dir/ALU\n obj_dir/ALU.v\n obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s)\n" | 6,936 | module | module ALUmodule(
input clk,
input rst_n,
input [31:0] rego1,
input [31:0] PC,
input ALUSrcA,
input [31:0] rego2,
input [15:0] imm,
input [1:0] ALUSrcB,
input [4:0] alu_op,
input ALURegWe,
output [31:0] alu_out,
output reg [31:0] alu_lock_next,
output flag
);
wire [31:0] alu_a;
assign alu_a= ALUSrcA ? rego1 : PC;
wire [31:0] SignExtend;
assign SignExtend[15:0]=imm;
assign SignExtend[31:16]= imm[15]==1 ? 16'hFFFF : 16'h0;
wire [31:0] alu_b;
assign alu_b= ALUSrcB==2'h0 ? rego2 : (
ALUSrcB==2'h2 ? SignExtend : (
ALUSrcB==2'h3 ? SignExtend << 2 : 32'h4
));
ALU u_ALU(
alu_a,
alu_b,
alu_op,
alu_out,
flag
);
reg [31:0] alu_lock_now;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
alu_lock_now<=32'hCCCC_CCCC;
end
else
begin
alu_lock_now<=alu_lock_next;
end
end
always@(*)
begin
if(ALURegWe)
alu_lock_next=alu_out;
else
alu_lock_next=alu_lock_now;
end
endmodule | module ALUmodule(
input clk,
input rst_n,
input [31:0] rego1,
input [31:0] PC,
input ALUSrcA,
input [31:0] rego2,
input [15:0] imm,
input [1:0] ALUSrcB,
input [4:0] alu_op,
input ALURegWe,
output [31:0] alu_out,
output reg [31:0] alu_lock_next,
output flag
); |
wire [31:0] alu_a;
assign alu_a= ALUSrcA ? rego1 : PC;
wire [31:0] SignExtend;
assign SignExtend[15:0]=imm;
assign SignExtend[31:16]= imm[15]==1 ? 16'hFFFF : 16'h0;
wire [31:0] alu_b;
assign alu_b= ALUSrcB==2'h0 ? rego2 : (
ALUSrcB==2'h2 ? SignExtend : (
ALUSrcB==2'h3 ? SignExtend << 2 : 32'h4
));
ALU u_ALU(
alu_a,
alu_b,
alu_op,
alu_out,
flag
);
reg [31:0] alu_lock_now;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
alu_lock_now<=32'hCCCC_CCCC;
end
else
begin
alu_lock_now<=alu_lock_next;
end
end
always@(*)
begin
if(ALURegWe)
alu_lock_next=alu_out;
else
alu_lock_next=alu_lock_now;
end
endmodule | 0 |
6,170 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/branch.v | 115,487,336 | branch.v | v | 76 | 83 | [] | [] | [] | [(21, 75)] | null | data/verilator_xmls/9c1fe17b-0e07-430c-800c-ccd488db3700.xml | null | 6,937 | module | module branch(
input need_jmp,
input b_or_j,
input branch_flag,
input [31:0] pc,
input [15:0] imm,
input [25:0] jimm,
output reg pcmux,
output reg [31:0] new_pc
);
reg [31:0] Imm;
reg [31:0] JImm;
always@(*)
begin
Imm[1:0]=2'b0;
JImm[1:0]=2'b0;
Imm[17:2]=imm;
JImm[27:2]=jimm;
if(imm[15])
Imm[31:18]=14'b1111111_1111111;
else
Imm[31:18]=14'h0;
if(jimm[25])
JImm[31:28]=4'hF;
else
JImm[31:28]=4'b0;
end
always@(*)
begin
pcmux=0;
if(need_jmp)
begin
if(b_or_j)
begin
if(branch_flag)
begin
new_pc=Imm+32'h4;
pcmux=1;
end
else
pcmux=0;
end
else
begin
new_pc=JImm+32'h4;
pcmux=1;
end
end
end
endmodule | module branch(
input need_jmp,
input b_or_j,
input branch_flag,
input [31:0] pc,
input [15:0] imm,
input [25:0] jimm,
output reg pcmux,
output reg [31:0] new_pc
); |
reg [31:0] Imm;
reg [31:0] JImm;
always@(*)
begin
Imm[1:0]=2'b0;
JImm[1:0]=2'b0;
Imm[17:2]=imm;
JImm[27:2]=jimm;
if(imm[15])
Imm[31:18]=14'b1111111_1111111;
else
Imm[31:18]=14'h0;
if(jimm[25])
JImm[31:28]=4'hF;
else
JImm[31:28]=4'b0;
end
always@(*)
begin
pcmux=0;
if(need_jmp)
begin
if(b_or_j)
begin
if(branch_flag)
begin
new_pc=Imm+32'h4;
pcmux=1;
end
else
pcmux=0;
end
else
begin
new_pc=JImm+32'h4;
pcmux=1;
end
end
end
endmodule | 0 |
6,171 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/FSM.v | 115,487,336 | FSM.v | v | 266 | 83 | [] | [] | [] | [(21, 265)] | null | data/verilator_xmls/c984b046-d243-4a9f-9625-1150230ae6aa.xml | null | 6,938 | module | module FSM(
input clk,
input rst_n,
input [31:0] ir,
output reg RegDst,
output reg MemtoReg,
output reg IorD,
output reg MemWrite,
output reg IRWrite,
output reg pcen,
output reg Branch,
output reg PCSrc,
output reg [4:0] ALUControl,
output reg [1:0] ALUSrcB,
output reg ALUSrcA,
output reg RegWrite,
output reg ALURegWe,
output reg NeedJmp,
output reg BorJ
);
reg [7:0] nowstate;
reg [7:0] nextstate;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
nowstate<=8'h0;
end
else
nowstate<=nextstate;
end
always@(*)
begin
case(nowstate)
8'h0:
nextstate=8'h1;
8'h1:
nextstate=8'h2;
8'h2:
begin
case(ir[31:26])
6'h0:
nextstate=8'h10;
6'h8:
nextstate=8'h20;
6'h23:
nextstate=8'h30;
6'h2B:
nextstate=8'h40;
6'h2:
nextstate=8'h50;
6'h7:
nextstate=8'h60;
default:
nextstate=8'h0;
endcase
end
8'h10:
nextstate=8'h11;
8'h20:
nextstate=8'h21;
8'h30:
nextstate=8'h31;
8'h31:
nextstate=8'h32;
8'h40:
nextstate=8'h41;
8'h50:
nextstate=8'h51;
8'h60:
nextstate=8'h61;
default:
nextstate=8'h1;
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
pcen<=1;
MemWrite<=0;
RegWrite<=0;
IorD<=0;
IRWrite<=0;
Branch<=0;
PCSrc<=0;
ALUControl<=5'b0;
ALUSrcB<=2'b0;
ALUSrcA<=0;
RegWrite<=0;
ALURegWe<=0;
NeedJmp<=0;
BorJ<=0;
end
else
begin
case(nextstate)
8'h1:
begin
pcen<=0;
IRWrite<=1;
end
8'h2:
begin
IRWrite<=0;
end
8'h10:
begin
RegDst<=1;
RegWrite<=1;
ALUSrcA<=1;
ALUSrcB<=2'b00;
ALURegWe<=1;
ALUControl<=5'h1;
MemtoReg<=0;
end
8'h11:
begin
RegDst<=0;
RegWrite<=0;
ALUSrcA<=0;
ALUControl<=5'h0;
pcen<=1;
ALURegWe<=0;
end
8'h20:
begin
RegDst<=0;
RegWrite<=1;
ALUSrcA<=1;
ALUSrcB<=2'b10;
ALUControl<=5'h1;
MemtoReg<=0;
ALURegWe<=1;
end
8'h21:
begin
RegDst<=0;
RegWrite<=0;
ALUSrcA<=0;
ALUSrcB<=2'b0;
ALUControl<=5'h0;
pcen<=1;
ALURegWe<=0;
end
8'h30:
begin
ALUSrcA<=1;
ALUSrcB<=2'b11;
ALUControl<=5'h1;
IorD<=1;
ALURegWe<=1;
end
8'h31:
begin
ALURegWe<=0;
IorD<=0;
ALUControl<=5'h0;
ALUSrcA<=0;
ALUSrcB<=2'b0;
RegDst<=0;
RegWrite<=1;
end
8'h32:
begin
RegWrite<=0;
pcen<=1;
end
8'h40:
begin
ALUSrcA<=1;
ALUSrcB<=2'b11;
ALUControl<=5'h1;
IorD<=1;
ALURegWe<=1;
MemWrite<=1;
end
8'h41:
begin
MemWrite<=0;
ALURegWe<=0;
IorD<=0;
ALUSrcA<=0;
ALUSrcB<=2'b0;
ALUControl<=5'h0;
pcen<=1;
end
8'h50:
begin
ALUSrcA<=1;
ALUControl<=5'h7;
NeedJmp<=1;
BorJ<=1;
end
8'h51:
begin
NeedJmp<=0;
BorJ<=0;
pcen<=1;
end
8'h60:
begin
NeedJmp<=1;
BorJ<=0;
end
8'h61:
begin
NeedJmp<=0;
pcen<=1;
end
endcase
end
end
endmodule | module FSM(
input clk,
input rst_n,
input [31:0] ir,
output reg RegDst,
output reg MemtoReg,
output reg IorD,
output reg MemWrite,
output reg IRWrite,
output reg pcen,
output reg Branch,
output reg PCSrc,
output reg [4:0] ALUControl,
output reg [1:0] ALUSrcB,
output reg ALUSrcA,
output reg RegWrite,
output reg ALURegWe,
output reg NeedJmp,
output reg BorJ
); |
reg [7:0] nowstate;
reg [7:0] nextstate;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
nowstate<=8'h0;
end
else
nowstate<=nextstate;
end
always@(*)
begin
case(nowstate)
8'h0:
nextstate=8'h1;
8'h1:
nextstate=8'h2;
8'h2:
begin
case(ir[31:26])
6'h0:
nextstate=8'h10;
6'h8:
nextstate=8'h20;
6'h23:
nextstate=8'h30;
6'h2B:
nextstate=8'h40;
6'h2:
nextstate=8'h50;
6'h7:
nextstate=8'h60;
default:
nextstate=8'h0;
endcase
end
8'h10:
nextstate=8'h11;
8'h20:
nextstate=8'h21;
8'h30:
nextstate=8'h31;
8'h31:
nextstate=8'h32;
8'h40:
nextstate=8'h41;
8'h50:
nextstate=8'h51;
8'h60:
nextstate=8'h61;
default:
nextstate=8'h1;
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
pcen<=1;
MemWrite<=0;
RegWrite<=0;
IorD<=0;
IRWrite<=0;
Branch<=0;
PCSrc<=0;
ALUControl<=5'b0;
ALUSrcB<=2'b0;
ALUSrcA<=0;
RegWrite<=0;
ALURegWe<=0;
NeedJmp<=0;
BorJ<=0;
end
else
begin
case(nextstate)
8'h1:
begin
pcen<=0;
IRWrite<=1;
end
8'h2:
begin
IRWrite<=0;
end
8'h10:
begin
RegDst<=1;
RegWrite<=1;
ALUSrcA<=1;
ALUSrcB<=2'b00;
ALURegWe<=1;
ALUControl<=5'h1;
MemtoReg<=0;
end
8'h11:
begin
RegDst<=0;
RegWrite<=0;
ALUSrcA<=0;
ALUControl<=5'h0;
pcen<=1;
ALURegWe<=0;
end
8'h20:
begin
RegDst<=0;
RegWrite<=1;
ALUSrcA<=1;
ALUSrcB<=2'b10;
ALUControl<=5'h1;
MemtoReg<=0;
ALURegWe<=1;
end
8'h21:
begin
RegDst<=0;
RegWrite<=0;
ALUSrcA<=0;
ALUSrcB<=2'b0;
ALUControl<=5'h0;
pcen<=1;
ALURegWe<=0;
end
8'h30:
begin
ALUSrcA<=1;
ALUSrcB<=2'b11;
ALUControl<=5'h1;
IorD<=1;
ALURegWe<=1;
end
8'h31:
begin
ALURegWe<=0;
IorD<=0;
ALUControl<=5'h0;
ALUSrcA<=0;
ALUSrcB<=2'b0;
RegDst<=0;
RegWrite<=1;
end
8'h32:
begin
RegWrite<=0;
pcen<=1;
end
8'h40:
begin
ALUSrcA<=1;
ALUSrcB<=2'b11;
ALUControl<=5'h1;
IorD<=1;
ALURegWe<=1;
MemWrite<=1;
end
8'h41:
begin
MemWrite<=0;
ALURegWe<=0;
IorD<=0;
ALUSrcA<=0;
ALUSrcB<=2'b0;
ALUControl<=5'h0;
pcen<=1;
end
8'h50:
begin
ALUSrcA<=1;
ALUControl<=5'h7;
NeedJmp<=1;
BorJ<=1;
end
8'h51:
begin
NeedJmp<=0;
BorJ<=0;
pcen<=1;
end
8'h60:
begin
NeedJmp<=1;
BorJ<=0;
end
8'h61:
begin
NeedJmp<=0;
pcen<=1;
end
endcase
end
end
endmodule | 0 |
6,172 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/MEMmodule.v | 115,487,336 | MEMmodule.v | v | 72 | 83 | [] | [] | [] | [(21, 71)] | null | null | 1: b"%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/MEMmodule.v:40: Cannot find file containing module: 'MEM'\nMEM u_MEM(\n^~~\n ... Looked in:\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/MEM\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/MEM.v\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/MEM.sv\n MEM\n MEM.v\n MEM.sv\n obj_dir/MEM\n obj_dir/MEM.v\n obj_dir/MEM.sv\n%Error: Exiting due to 1 error(s)\n" | 6,939 | module | module MEMmodule(
input clk,
input rst_n,
input [31:0] pc,
input [31:0] data_addr,
input IorD,
input [31:0] mem_wd,
input WE,
input IRWrite,
output reg [31:0] now_Instr
);
wire [31:0] real_addr;
assign real_addr[31:30] = 2'b0;
assign real_addr[29:0] = IorD ? data_addr[31:2] : pc[31:2];
wire [31:0] memout;
MEM u_MEM(
clk,
WE,
real_addr,
mem_wd,
memout
);
reg [31:0] next_Instr;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
now_Instr<=32'hCCCC_CCCC;
end
else
begin
now_Instr<=next_Instr;
end
end
always@(*)
begin
if(IRWrite)
next_Instr=memout;
else
next_Instr=now_Instr;
end
endmodule | module MEMmodule(
input clk,
input rst_n,
input [31:0] pc,
input [31:0] data_addr,
input IorD,
input [31:0] mem_wd,
input WE,
input IRWrite,
output reg [31:0] now_Instr
); |
wire [31:0] real_addr;
assign real_addr[31:30] = 2'b0;
assign real_addr[29:0] = IorD ? data_addr[31:2] : pc[31:2];
wire [31:0] memout;
MEM u_MEM(
clk,
WE,
real_addr,
mem_wd,
memout
);
reg [31:0] next_Instr;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
now_Instr<=32'hCCCC_CCCC;
end
else
begin
now_Instr<=next_Instr;
end
end
always@(*)
begin
if(IRWrite)
next_Instr=memout;
else
next_Instr=now_Instr;
end
endmodule | 0 |
6,173 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/PC.v | 115,487,336 | PC.v | v | 62 | 83 | [] | [] | [] | [(21, 61)] | null | data/verilator_xmls/b6c89a7b-17d6-424a-82d5-0f7b30b401c8.xml | null | 6,940 | module | module PC(
input clk,
input rst_n,
input pcen,
input [31:0] addr,
input en,
output [31:0] now_addr
);
assign now_addr=nextaddr;
reg [31:0] nowaddr;
reg [31:0] nextaddr;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
nowaddr<=32'hFFFF_FFFC;
end
else if(pcen)
begin
nowaddr<= nextaddr;
end
end
always@(*)
begin
if(en)
nextaddr=addr;
else
nextaddr=nowaddr+32'h4;
end
endmodule | module PC(
input clk,
input rst_n,
input pcen,
input [31:0] addr,
input en,
output [31:0] now_addr
); |
assign now_addr=nextaddr;
reg [31:0] nowaddr;
reg [31:0] nextaddr;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
nowaddr<=32'hFFFF_FFFC;
end
else if(pcen)
begin
nowaddr<= nextaddr;
end
end
always@(*)
begin
if(en)
nextaddr=addr;
else
nextaddr=nowaddr+32'h4;
end
endmodule | 0 |
6,174 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/REG_FILEmodule.v | 115,487,336 | REG_FILEmodule.v | v | 76 | 83 | [] | [] | [] | [(21, 75)] | null | null | 1: b"%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/REG_FILEmodule.v:50: Cannot find file containing module: 'REG_FILE'\nREG_FILE u_RegFile(\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/REG_FILE\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/REG_FILE.v\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/REG_FILE.sv\n REG_FILE\n REG_FILE.v\n REG_FILE.sv\n obj_dir/REG_FILE\n obj_dir/REG_FILE.v\n obj_dir/REG_FILE.sv\n%Error: Exiting due to 1 error(s)\n" | 6,942 | module | module REG_FILEmodule(
input clk,
input rst_n,
input [31:0] ir,
input [31:0] aluans,
input RegDst,
input MemToReg,
input RegWrite,
output reg [31:0] rego1,
output reg [31:0] rego2
);
wire [31:0] regot1;
wire [31:0] regot2;
wire [4:0] regaddr1;
wire [4:0] regaddr2;
wire [4:0] regaddr3;
assign regaddr1=ir[25:21];
assign regaddr2=ir[20:16];
assign regaddr3= RegDst ? ir[15:11] : ir[20:16] ;
wire [31:0] wd;
assign wd = MemToReg ? ir : aluans;
REG_FILE u_RegFile(
clk,
rst_n,
regaddr1,
regaddr2,
regaddr3,
wd,
RegWrite,
regot1,
regot2
);
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
rego1<=32'hcccccccc;
rego2<=32'hcccccccc;
end
else
begin
rego1<=regot1;
rego2<=regot2;
end
end
endmodule | module REG_FILEmodule(
input clk,
input rst_n,
input [31:0] ir,
input [31:0] aluans,
input RegDst,
input MemToReg,
input RegWrite,
output reg [31:0] rego1,
output reg [31:0] rego2
); |
wire [31:0] regot1;
wire [31:0] regot2;
wire [4:0] regaddr1;
wire [4:0] regaddr2;
wire [4:0] regaddr3;
assign regaddr1=ir[25:21];
assign regaddr2=ir[20:16];
assign regaddr3= RegDst ? ir[15:11] : ir[20:16] ;
wire [31:0] wd;
assign wd = MemToReg ? ir : aluans;
REG_FILE u_RegFile(
clk,
rst_n,
regaddr1,
regaddr2,
regaddr3,
wd,
RegWrite,
regot1,
regot2
);
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
rego1<=32'hcccccccc;
rego2<=32'hcccccccc;
end
else
begin
rego1<=regot1;
rego2<=regot2;
end
end
endmodule | 0 |
6,175 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/top.v | 115,487,336 | top.v | v | 135 | 83 | [] | [] | [] | [(21, 134)] | null | null | 1: b"%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/top.v:54: Cannot find file containing module: 'PC'\nPC u_PC(\n^~\n ... Looked in:\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/PC\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/PC.v\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/PC.sv\n PC\n PC.v\n PC.sv\n obj_dir/PC\n obj_dir/PC.v\n obj_dir/PC.sv\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/top.v:63: Cannot find file containing module: 'MEMmodule'\nMEMmodule u_MEMmodule(\n^~~~~~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/top.v:75: Cannot find file containing module: 'REG_FILEmodule'\nREG_FILEmodule u_REGFILEmodule(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/top.v:87: Cannot find file containing module: 'ALUmodule'\nALUmodule u_ALUmodule(\n^~~~~~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/top.v:103: Cannot find file containing module: 'branch'\nbranch u_branch(\n^~~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/top.v:114: Cannot find file containing module: 'FSM'\nFSM u_FSM(\n^~~\n%Error: Exiting due to 6 error(s)\n" | 6,943 | module | module top(
input clk,
input rst_n
);
wire [31:0] j_z_nextpc;
wire PCWrite;
wire [31:0] now_addr;
wire MEMWrite;
wire IorD;
wire [31:0] mem_out;
wire RegDst;
wire MemToReg;
wire RegWrite;
wire IRWrite;
wire ALUSrcA;
wire [1:0] ALUSrcB;
wire ALURegWe;
wire [31:0] rego1;
wire [31:0] rego2;
wire [4:0] ALUControl;
wire [31:0] aluout;
wire flag;
wire NeedJmp;
wire BorJ;
wire pcen;
PC u_PC(
clk,
rst_n,
pcen,
j_z_nextpc,
PCWrite,
now_addr
);
MEMmodule u_MEMmodule(
clk,
rst_n,
now_addr,
aluout,
IorD,
rego2,
MEMWrite,
IRWrite,
mem_out
);
REG_FILEmodule u_REGFILEmodule(
clk,
rst_n,
mem_out,
mem_out,
RegDst,
MemToReg,
RegWrite,
rego1,
rego2
);
ALUmodule u_ALUmodule(
clk,
rst_n,
rego1,
now_addr,
ALUSrcA,
rego2,
mem_out[15:0],
ALUSrcB,
ALUControl,
ALURegWE,
aluout,
alu_lock,
flag
);
branch u_branch(
NeedJmp,
BorJ,
flag,
now_addr,
mem_out[15:0],
mem_out[25:0],
PCWrite,
j_z_nextpc
);
FSM u_FSM(
clk,
rst_n,
mem_out,
RegDst,
MemtoReg,
IorD,
MEMWrite,
IRWrite,
pcen,
Branch,
PCSrc,
ALUControl,
ALUSrcB,
ALUSrcA,
RegWrite,
ALURegWe,
NeedJmp,
BorJ
);
endmodule | module top(
input clk,
input rst_n
); |
wire [31:0] j_z_nextpc;
wire PCWrite;
wire [31:0] now_addr;
wire MEMWrite;
wire IorD;
wire [31:0] mem_out;
wire RegDst;
wire MemToReg;
wire RegWrite;
wire IRWrite;
wire ALUSrcA;
wire [1:0] ALUSrcB;
wire ALURegWe;
wire [31:0] rego1;
wire [31:0] rego2;
wire [4:0] ALUControl;
wire [31:0] aluout;
wire flag;
wire NeedJmp;
wire BorJ;
wire pcen;
PC u_PC(
clk,
rst_n,
pcen,
j_z_nextpc,
PCWrite,
now_addr
);
MEMmodule u_MEMmodule(
clk,
rst_n,
now_addr,
aluout,
IorD,
rego2,
MEMWrite,
IRWrite,
mem_out
);
REG_FILEmodule u_REGFILEmodule(
clk,
rst_n,
mem_out,
mem_out,
RegDst,
MemToReg,
RegWrite,
rego1,
rego2
);
ALUmodule u_ALUmodule(
clk,
rst_n,
rego1,
now_addr,
ALUSrcA,
rego2,
mem_out[15:0],
ALUSrcB,
ALUControl,
ALURegWE,
aluout,
alu_lock,
flag
);
branch u_branch(
NeedJmp,
BorJ,
flag,
now_addr,
mem_out[15:0],
mem_out[25:0],
PCWrite,
j_z_nextpc
);
FSM u_FSM(
clk,
rst_n,
mem_out,
RegDst,
MemtoReg,
IorD,
MEMWrite,
IRWrite,
pcen,
Branch,
PCSrc,
ALUControl,
ALUSrcB,
ALUSrcA,
RegWrite,
ALURegWe,
NeedJmp,
BorJ
);
endmodule | 0 |
6,176 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALU.v | 115,487,336 | ALU.v | v | 287 | 83 | [] | [] | [] | [(21, 286)] | null | data/verilator_xmls/e937d75b-7a3f-408c-b2df-f883cc0e8818.xml | null | 6,945 | module | module ALU(
input signed [31:0] alu_a,
input signed [31:0] alu_b,
input [4:0] alu_op,
output [31:0] alu_out,
output reg flag
);
assign alu_out = alu_out2;
reg [31:0] alu_out2;
reg [31:0] alutp;
always @(*)
begin
flag=0;
case(alu_op)
5'h0:
alu_out2=32'b0;
5'h1:
alu_out2=alu_a+alu_b;
5'h2:
alu_out2=alu_a-alu_b;
5'h3:
alu_out2=alu_a&alu_b;
5'h4:
alu_out2=alu_a|alu_b;
5'h5:
alu_out2=alu_a^alu_b;
5'h6:
alu_out2=~(alu_a|alu_b);
5'h7:
begin
if(alu_a[31]==0 && (!(alu_a==32'b0)))
flag=1;
else
flag=0;
end
5'h8:
begin
if(alu_a[31]==0)
flag=1;
else
flag=0;
end
5'h9:
begin
if(alu_a[31]==1)
flag=1;
else
flag=0;
end
5'hA:
begin
if(alu_a[31]==1 || (alu_a==32'b0))
flag=1;
else
flag=0;
end
5'hB:
begin
if(alu_a==alu_b)
flag=1;
else
flag=0;
end
5'hC:
begin
if(alu_a==alu_b)
flag=0;
else
flag=1;
end
5'hD:
alu_out2=alu_a << alu_b;
5'hE:
alu_out2=alu_a>>alu_b;
5'hF:
alu_out2=alu_a>>>alu_b;
5'h1E:
begin
alutp=~(alu_a);
if(alutp[31:0]==32'b0)
alu_out2=32'd32;
else if(alutp[31:1]==31'b0)
alu_out2=32'd31;
else if(alutp[31:2]==30'b0)
alu_out2=32'd30;
else if(alutp[31:3]==29'b0)
alu_out2=32'd29;
else if(alutp[31:4]==28'b0)
alu_out2=32'd28;
else if(alutp[31:5]==27'b0)
alu_out2=32'd27;
else if(alutp[31:6]==26'b0)
alu_out2=32'd26;
else if(alutp[31:7]==25'b0)
alu_out2=32'd25;
else if(alutp[31:8]==24'b0)
alu_out2=32'd24;
else if(alutp[31:9]==23'b0)
alu_out2=32'd23;
else if(alutp[31:10]==22'b0)
alu_out2=32'd22;
else if(alutp[31:11]==21'b0)
alu_out2=32'd21;
else if(alutp[31:12]==20'b0)
alu_out2=32'd20;
else if(alutp[31:13]==19'b0)
alu_out2=32'd19;
else if(alutp[31:14]==18'b0)
alu_out2=32'd18;
else if(alutp[31:15]==17'b0)
alu_out2=32'd17;
else if(alutp[31:16]==16'b0)
alu_out2=32'd16;
else if(alutp[31:17]==15'b0)
alu_out2=32'd15;
else if(alutp[31:18]==14'b0)
alu_out2=32'd14;
else if(alutp[31:19]==13'b0)
alu_out2=32'd13;
else if(alutp[31:20]==12'b0)
alu_out2=32'd12;
else if(alutp[31:21]==11'b0)
alu_out2=32'd11;
else if(alutp[31:22]==10'b0)
alu_out2=32'd10;
else if(alutp[31:23]==9'b0)
alu_out2=32'd9;
else if(alutp[31:24]==8'b0)
alu_out2=32'd8;
else if(alutp[31:25]==7'b0)
alu_out2=32'd7;
else if(alutp[31:26]==6'b0)
alu_out2=32'd6;
else if(alutp[31:27]==5'b0)
alu_out2=32'd5;
else if(alutp[31:28]==4'b0)
alu_out2=32'd4;
else if(alutp[31:29]==3'b0)
alu_out2=32'd3;
else if(alutp[31:30]==2'b0)
alu_out2=32'd2;
else if(alutp[31]==1'b0)
alu_out2=32'd1;
else
alu_out2=32'd0;
end
5'h1F:
begin
alutp=alu_a;
if(alutp[31:0]==32'b0)
alu_out2=32'd32;
else if(alutp[31:1]==31'b0)
alu_out2=32'd31;
else if(alutp[31:2]==30'b0)
alu_out2=32'd30;
else if(alutp[31:3]==29'b0)
alu_out2=32'd29;
else if(alutp[31:4]==28'b0)
alu_out2=32'd28;
else if(alutp[31:5]==27'b0)
alu_out2=32'd27;
else if(alutp[31:6]==26'b0)
alu_out2=32'd26;
else if(alutp[31:7]==25'b0)
alu_out2=32'd25;
else if(alutp[31:8]==24'b0)
alu_out2=32'd24;
else if(alutp[31:9]==23'b0)
alu_out2=32'd23;
else if(alutp[31:10]==22'b0)
alu_out2=32'd22;
else if(alutp[31:11]==21'b0)
alu_out2=32'd21;
else if(alutp[31:12]==20'b0)
alu_out2=32'd20;
else if(alutp[31:13]==19'b0)
alu_out2=32'd19;
else if(alutp[31:14]==18'b0)
alu_out2=32'd18;
else if(alutp[31:15]==17'b0)
alu_out2=32'd17;
else if(alutp[31:16]==16'b0)
alu_out2=32'd16;
else if(alutp[31:17]==15'b0)
alu_out2=32'd15;
else if(alutp[31:18]==14'b0)
alu_out2=32'd14;
else if(alutp[31:19]==13'b0)
alu_out2=32'd13;
else if(alutp[31:20]==12'b0)
alu_out2=32'd12;
else if(alutp[31:21]==11'b0)
alu_out2=32'd11;
else if(alutp[31:22]==10'b0)
alu_out2=32'd10;
else if(alutp[31:23]==9'b0)
alu_out2=32'd9;
else if(alutp[31:24]==8'b0)
alu_out2=32'd8;
else if(alutp[31:25]==7'b0)
alu_out2=32'd7;
else if(alutp[31:26]==6'b0)
alu_out2=32'd6;
else if(alutp[31:27]==5'b0)
alu_out2=32'd5;
else if(alutp[31:28]==4'b0)
alu_out2=32'd4;
else if(alutp[31:29]==3'b0)
alu_out2=32'd3;
else if(alutp[31:30]==2'b0)
alu_out2=32'd2;
else if(alutp[31]==1'b0)
alu_out2=32'd1;
else
alu_out2=32'd0;
end
5'h10:
begin
alu_out2[31:16]=alu_b[15:0];
alu_out2[15:0]=alu_a[15:0];
end
5'h11:
begin
alu_out2[31:16]=alu_a[31:16];
alu_out2[15:0]=alu_b[15:0];
end
5'h12:
alu_out2=alu_a;
5'h13:
alu_out2=alu_b;
default:
alu_out2=32'hcccccccc;
endcase
end
endmodule | module ALU(
input signed [31:0] alu_a,
input signed [31:0] alu_b,
input [4:0] alu_op,
output [31:0] alu_out,
output reg flag
); |
assign alu_out = alu_out2;
reg [31:0] alu_out2;
reg [31:0] alutp;
always @(*)
begin
flag=0;
case(alu_op)
5'h0:
alu_out2=32'b0;
5'h1:
alu_out2=alu_a+alu_b;
5'h2:
alu_out2=alu_a-alu_b;
5'h3:
alu_out2=alu_a&alu_b;
5'h4:
alu_out2=alu_a|alu_b;
5'h5:
alu_out2=alu_a^alu_b;
5'h6:
alu_out2=~(alu_a|alu_b);
5'h7:
begin
if(alu_a[31]==0 && (!(alu_a==32'b0)))
flag=1;
else
flag=0;
end
5'h8:
begin
if(alu_a[31]==0)
flag=1;
else
flag=0;
end
5'h9:
begin
if(alu_a[31]==1)
flag=1;
else
flag=0;
end
5'hA:
begin
if(alu_a[31]==1 || (alu_a==32'b0))
flag=1;
else
flag=0;
end
5'hB:
begin
if(alu_a==alu_b)
flag=1;
else
flag=0;
end
5'hC:
begin
if(alu_a==alu_b)
flag=0;
else
flag=1;
end
5'hD:
alu_out2=alu_a << alu_b;
5'hE:
alu_out2=alu_a>>alu_b;
5'hF:
alu_out2=alu_a>>>alu_b;
5'h1E:
begin
alutp=~(alu_a);
if(alutp[31:0]==32'b0)
alu_out2=32'd32;
else if(alutp[31:1]==31'b0)
alu_out2=32'd31;
else if(alutp[31:2]==30'b0)
alu_out2=32'd30;
else if(alutp[31:3]==29'b0)
alu_out2=32'd29;
else if(alutp[31:4]==28'b0)
alu_out2=32'd28;
else if(alutp[31:5]==27'b0)
alu_out2=32'd27;
else if(alutp[31:6]==26'b0)
alu_out2=32'd26;
else if(alutp[31:7]==25'b0)
alu_out2=32'd25;
else if(alutp[31:8]==24'b0)
alu_out2=32'd24;
else if(alutp[31:9]==23'b0)
alu_out2=32'd23;
else if(alutp[31:10]==22'b0)
alu_out2=32'd22;
else if(alutp[31:11]==21'b0)
alu_out2=32'd21;
else if(alutp[31:12]==20'b0)
alu_out2=32'd20;
else if(alutp[31:13]==19'b0)
alu_out2=32'd19;
else if(alutp[31:14]==18'b0)
alu_out2=32'd18;
else if(alutp[31:15]==17'b0)
alu_out2=32'd17;
else if(alutp[31:16]==16'b0)
alu_out2=32'd16;
else if(alutp[31:17]==15'b0)
alu_out2=32'd15;
else if(alutp[31:18]==14'b0)
alu_out2=32'd14;
else if(alutp[31:19]==13'b0)
alu_out2=32'd13;
else if(alutp[31:20]==12'b0)
alu_out2=32'd12;
else if(alutp[31:21]==11'b0)
alu_out2=32'd11;
else if(alutp[31:22]==10'b0)
alu_out2=32'd10;
else if(alutp[31:23]==9'b0)
alu_out2=32'd9;
else if(alutp[31:24]==8'b0)
alu_out2=32'd8;
else if(alutp[31:25]==7'b0)
alu_out2=32'd7;
else if(alutp[31:26]==6'b0)
alu_out2=32'd6;
else if(alutp[31:27]==5'b0)
alu_out2=32'd5;
else if(alutp[31:28]==4'b0)
alu_out2=32'd4;
else if(alutp[31:29]==3'b0)
alu_out2=32'd3;
else if(alutp[31:30]==2'b0)
alu_out2=32'd2;
else if(alutp[31]==1'b0)
alu_out2=32'd1;
else
alu_out2=32'd0;
end
5'h1F:
begin
alutp=alu_a;
if(alutp[31:0]==32'b0)
alu_out2=32'd32;
else if(alutp[31:1]==31'b0)
alu_out2=32'd31;
else if(alutp[31:2]==30'b0)
alu_out2=32'd30;
else if(alutp[31:3]==29'b0)
alu_out2=32'd29;
else if(alutp[31:4]==28'b0)
alu_out2=32'd28;
else if(alutp[31:5]==27'b0)
alu_out2=32'd27;
else if(alutp[31:6]==26'b0)
alu_out2=32'd26;
else if(alutp[31:7]==25'b0)
alu_out2=32'd25;
else if(alutp[31:8]==24'b0)
alu_out2=32'd24;
else if(alutp[31:9]==23'b0)
alu_out2=32'd23;
else if(alutp[31:10]==22'b0)
alu_out2=32'd22;
else if(alutp[31:11]==21'b0)
alu_out2=32'd21;
else if(alutp[31:12]==20'b0)
alu_out2=32'd20;
else if(alutp[31:13]==19'b0)
alu_out2=32'd19;
else if(alutp[31:14]==18'b0)
alu_out2=32'd18;
else if(alutp[31:15]==17'b0)
alu_out2=32'd17;
else if(alutp[31:16]==16'b0)
alu_out2=32'd16;
else if(alutp[31:17]==15'b0)
alu_out2=32'd15;
else if(alutp[31:18]==14'b0)
alu_out2=32'd14;
else if(alutp[31:19]==13'b0)
alu_out2=32'd13;
else if(alutp[31:20]==12'b0)
alu_out2=32'd12;
else if(alutp[31:21]==11'b0)
alu_out2=32'd11;
else if(alutp[31:22]==10'b0)
alu_out2=32'd10;
else if(alutp[31:23]==9'b0)
alu_out2=32'd9;
else if(alutp[31:24]==8'b0)
alu_out2=32'd8;
else if(alutp[31:25]==7'b0)
alu_out2=32'd7;
else if(alutp[31:26]==6'b0)
alu_out2=32'd6;
else if(alutp[31:27]==5'b0)
alu_out2=32'd5;
else if(alutp[31:28]==4'b0)
alu_out2=32'd4;
else if(alutp[31:29]==3'b0)
alu_out2=32'd3;
else if(alutp[31:30]==2'b0)
alu_out2=32'd2;
else if(alutp[31]==1'b0)
alu_out2=32'd1;
else
alu_out2=32'd0;
end
5'h10:
begin
alu_out2[31:16]=alu_b[15:0];
alu_out2[15:0]=alu_a[15:0];
end
5'h11:
begin
alu_out2[31:16]=alu_a[31:16];
alu_out2[15:0]=alu_b[15:0];
end
5'h12:
alu_out2=alu_a;
5'h13:
alu_out2=alu_b;
default:
alu_out2=32'hcccccccc;
endcase
end
endmodule | 0 |
6,177 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v | 115,487,336 | ALUmodule.v | v | 227 | 95 | [] | [] | [] | [(21, 226)] | null | null | 1: b'%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:143: Cannot find file containing module: \'ALU\'\nALU u_ALU(\n^~~\n ... Looked in:\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/ALU\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/ALU.v\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/ALU.sv\n ALU\n ALU.v\n ALU.sv\n obj_dir/ALU\n obj_dir/ALU.v\n obj_dir/ALU.sv\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:176: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'to_optype\' generates 6 bits.\n : ... In instance ALUmodule\n local_optype=to_optype;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:180: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h3f\' generates 6 bits.\n : ... In instance ALUmodule\n local_optype=6\'h3F;\n ^\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:185: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'optype\' generates 6 bits.\n : ... In instance ALUmodule\n local_optype=optype;\n ^\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:203: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'local_optype\' generates 32 bits.\n : ... In instance ALUmodule\n to_optype<=local_optype;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:217: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance ALUmodule\n if(local_optype==6\'h00 || local_optype==6\'h01 || local_optype==6\'h02\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:217: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1\' generates 6 bits.\n : ... In instance ALUmodule\n if(local_optype==6\'h00 || local_optype==6\'h01 || local_optype==6\'h02\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:217: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n : ... In instance ALUmodule\n if(local_optype==6\'h00 || local_optype==6\'h01 || local_optype==6\'h02\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:218: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n : ... In instance ALUmodule\n || local_optype==6\'h04 || local_optype==6\'h05 || local_optype==6\'h06 || local_optype==6\'h13)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:218: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'6\'h5\' generates 6 bits.\n : ... In instance ALUmodule\n || local_optype==6\'h04 || local_optype==6\'h05 || local_optype==6\'h06 || local_optype==6\'h13)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:218: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n : ... In instance ALUmodule\n || local_optype==6\'h04 || local_optype==6\'h05 || local_optype==6\'h06 || local_optype==6\'h13)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:218: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'6\'h13\' generates 6 bits.\n : ... In instance ALUmodule\n || local_optype==6\'h04 || local_optype==6\'h05 || local_optype==6\'h06 || local_optype==6\'h13)\n ^~\n%Error: Exiting due to 1 error(s), 11 warning(s)\n' | 6,946 | module | module ALUmodule(
input clk,
input rst_n,
input alu_stall,
input alu_bubble,
input [31:0] pc,
input [31:0] ir,
input [4:0] regaddr1,
input [4:0] regaddr2,
input [4:0] regaddr3,
input [31:0] alu_a,
input [31:0] alu_b,
input [4:0] op,
input [5:0] optype,
input [31:0] swdata,
input [4:0] a_bwregaddr,
input [31:0] a_bw_data,
input a_valid,
input [4:0] b_bwregaddr,
input [31:0] b_bw_data,
input b_valid,
output [31:0] walu_out,
output wflag,
output reg to_valid,
output reg [4:0] to_regaddr3,
output reg [31:0] alu_out,
output reg flag,
output reg [31:0] to_swdata,
output reg [31:0] to_pc,
output reg [31:0] to_ir,
output reg [5:0] to_optype
);
reg [31:0] local_d1;
reg [31:0] local_d2;
always@(*)
begin
local_d1=alu_a;
local_d2=alu_b;
if(optype==6'h00 || optype==6'h12)
begin
if(a_bwregaddr==regaddr1 && a_valid)
begin
local_d1=a_bw_data;
end
else if(b_bwregaddr==regaddr1 && b_valid)
begin
local_d1=b_bw_data;
end
else
begin
local_d1=alu_a;
end
if(a_bwregaddr==regaddr2 && a_valid)
begin
local_d2=a_bw_data;
end
else if(b_bwregaddr==regaddr2 && b_valid)
begin
local_d2=b_bw_data;
end
else
begin
local_d2=alu_b;
end
end
else if(optype==6'h01 || optype==6'h02 || optype==6'h04 || optype==6'h05
|| optype==6'h10 || optype==6'h13 || optype==6'h14)
begin
if(a_bwregaddr==regaddr1 && a_valid)
begin
local_d1=a_bw_data;
end
else if(b_bwregaddr==regaddr1 && b_valid)
begin
local_d1=b_bw_data;
end
else
begin
local_d1=alu_a;
end
if(a_bwregaddr==regaddr2 && a_valid)
begin
local_swdata=a_bw_data;
end
else if(b_bwregaddr==regaddr2 && b_valid)
begin
local_swdata=b_bw_data;
end
else
begin
local_swdata=swdata;
end
end
else
begin
end
end
ALU u_ALU(
.alu_a(local_d1),
.alu_b(local_d2),
.alu_op(op),
.alu_out(walu_out),
.flag(wflag)
);
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
alu_out<=32'hCCCC_CCCC;
flag<=0;
end
else
begin
alu_out<=walu_out;
flag<=wflag;
end
end
reg [31:0] local_pc;
reg [31:0] local_ir;
reg [31:0] local_optype;
reg [31:0] local_swdata;
always@(*)
begin
if(alu_stall)
begin
local_pc=to_pc;
local_ir=to_ir;
local_optype=to_optype;
end
else if(alu_bubble)
begin
local_optype=6'h3F;
end
begin
local_pc=pc;
local_ir=ir;
local_optype=optype;
end
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
to_pc<=32'h0;
to_ir<=32'h0;
to_optype<=6'h3F;
to_regaddr3<=5'h0;
to_valid<=0;
end
else if(alu_stall)
begin
to_pc<=local_pc;
to_ir<=local_ir;
to_optype<=local_optype;
to_swdata<=local_swdata;
end
else
begin
to_pc<=pc;
to_ir<=ir;
to_optype<=optype;
to_swdata<=local_swdata;
to_regaddr3<=regaddr3;
if(local_optype==6'h00 || local_optype==6'h01 || local_optype==6'h02
|| local_optype==6'h04 || local_optype==6'h05 || local_optype==6'h06 || local_optype==6'h13)
to_valid<=1;
else
to_valid<=0;
end
end
endmodule | module ALUmodule(
input clk,
input rst_n,
input alu_stall,
input alu_bubble,
input [31:0] pc,
input [31:0] ir,
input [4:0] regaddr1,
input [4:0] regaddr2,
input [4:0] regaddr3,
input [31:0] alu_a,
input [31:0] alu_b,
input [4:0] op,
input [5:0] optype,
input [31:0] swdata,
input [4:0] a_bwregaddr,
input [31:0] a_bw_data,
input a_valid,
input [4:0] b_bwregaddr,
input [31:0] b_bw_data,
input b_valid,
output [31:0] walu_out,
output wflag,
output reg to_valid,
output reg [4:0] to_regaddr3,
output reg [31:0] alu_out,
output reg flag,
output reg [31:0] to_swdata,
output reg [31:0] to_pc,
output reg [31:0] to_ir,
output reg [5:0] to_optype
); |
reg [31:0] local_d1;
reg [31:0] local_d2;
always@(*)
begin
local_d1=alu_a;
local_d2=alu_b;
if(optype==6'h00 || optype==6'h12)
begin
if(a_bwregaddr==regaddr1 && a_valid)
begin
local_d1=a_bw_data;
end
else if(b_bwregaddr==regaddr1 && b_valid)
begin
local_d1=b_bw_data;
end
else
begin
local_d1=alu_a;
end
if(a_bwregaddr==regaddr2 && a_valid)
begin
local_d2=a_bw_data;
end
else if(b_bwregaddr==regaddr2 && b_valid)
begin
local_d2=b_bw_data;
end
else
begin
local_d2=alu_b;
end
end
else if(optype==6'h01 || optype==6'h02 || optype==6'h04 || optype==6'h05
|| optype==6'h10 || optype==6'h13 || optype==6'h14)
begin
if(a_bwregaddr==regaddr1 && a_valid)
begin
local_d1=a_bw_data;
end
else if(b_bwregaddr==regaddr1 && b_valid)
begin
local_d1=b_bw_data;
end
else
begin
local_d1=alu_a;
end
if(a_bwregaddr==regaddr2 && a_valid)
begin
local_swdata=a_bw_data;
end
else if(b_bwregaddr==regaddr2 && b_valid)
begin
local_swdata=b_bw_data;
end
else
begin
local_swdata=swdata;
end
end
else
begin
end
end
ALU u_ALU(
.alu_a(local_d1),
.alu_b(local_d2),
.alu_op(op),
.alu_out(walu_out),
.flag(wflag)
);
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
alu_out<=32'hCCCC_CCCC;
flag<=0;
end
else
begin
alu_out<=walu_out;
flag<=wflag;
end
end
reg [31:0] local_pc;
reg [31:0] local_ir;
reg [31:0] local_optype;
reg [31:0] local_swdata;
always@(*)
begin
if(alu_stall)
begin
local_pc=to_pc;
local_ir=to_ir;
local_optype=to_optype;
end
else if(alu_bubble)
begin
local_optype=6'h3F;
end
begin
local_pc=pc;
local_ir=ir;
local_optype=optype;
end
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
to_pc<=32'h0;
to_ir<=32'h0;
to_optype<=6'h3F;
to_regaddr3<=5'h0;
to_valid<=0;
end
else if(alu_stall)
begin
to_pc<=local_pc;
to_ir<=local_ir;
to_optype<=local_optype;
to_swdata<=local_swdata;
end
else
begin
to_pc<=pc;
to_ir<=ir;
to_optype<=optype;
to_swdata<=local_swdata;
to_regaddr3<=regaddr3;
if(local_optype==6'h00 || local_optype==6'h01 || local_optype==6'h02
|| local_optype==6'h04 || local_optype==6'h05 || local_optype==6'h06 || local_optype==6'h13)
to_valid<=1;
else
to_valid<=0;
end
end
endmodule | 0 |
6,178 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/branch.v | 115,487,336 | branch.v | v | 100 | 83 | [] | [] | [] | [(21, 99)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/branch.v:41: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 18 bits.\n : ... In instance branch\nassign tempdd = {$signed(ir[15:0]),2\'h0};\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 6,947 | module | module branch(
input clk,
input rst_n,
input [5:0] optype,
input [31:0] pc,
input [31:0] ir,
input [31:0] walu_out,
input wflag,
output reg pcjump,
output reg [31:0] real_pc,
output reg ir_bubble
);
wire [31:0] tempdd;
assign tempdd = {$signed(ir[15:0]),2'h0};
reg ir_bubble_two;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
ir_bubble_two<=0;
end
else
begin
if(!ir_bubble_two && ir_bubble==1)
ir_bubble_two<=1;
else
ir_bubble_two<=0;
end
end
always@(*)
begin
if(optype==6'h12 && wflag)
begin
ir_bubble=1;
real_pc = pc+tempdd+32'h4;
end
else if(optype==6'h10 || optype==6'h11)
begin
real_pc = walu_out;
ir_bubble=1;
end
else if(optype==6'h21)
begin
ir_bubble=1;
end
else
begin
if(!ir_bubble_two)
ir_bubble=0;
else
ir_bubble=1;
end
end
always@(*)
begin
if((optype==6'h12 && wflag) || optype==6'h10 || optype==6'h11)
begin
pcjump=1;
end
else
pcjump=0;
end
endmodule | module branch(
input clk,
input rst_n,
input [5:0] optype,
input [31:0] pc,
input [31:0] ir,
input [31:0] walu_out,
input wflag,
output reg pcjump,
output reg [31:0] real_pc,
output reg ir_bubble
); |
wire [31:0] tempdd;
assign tempdd = {$signed(ir[15:0]),2'h0};
reg ir_bubble_two;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
ir_bubble_two<=0;
end
else
begin
if(!ir_bubble_two && ir_bubble==1)
ir_bubble_two<=1;
else
ir_bubble_two<=0;
end
end
always@(*)
begin
if(optype==6'h12 && wflag)
begin
ir_bubble=1;
real_pc = pc+tempdd+32'h4;
end
else if(optype==6'h10 || optype==6'h11)
begin
real_pc = walu_out;
ir_bubble=1;
end
else if(optype==6'h21)
begin
ir_bubble=1;
end
else
begin
if(!ir_bubble_two)
ir_bubble=0;
else
ir_bubble=1;
end
end
always@(*)
begin
if((optype==6'h12 && wflag) || optype==6'h10 || optype==6'h11)
begin
pcjump=1;
end
else
pcjump=0;
end
endmodule | 0 |
6,179 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/butt.v | 115,487,336 | butt.v | v | 78 | 83 | [] | [] | [] | [(21, 77)] | null | data/verilator_xmls/377b2d4d-c8c3-4cfa-9f58-4b54d7248e7a.xml | null | 6,948 | module | module butt(
input clk,
input rst_n,
input buttonpress,
output button
);
assign button = buttonpress;
reg [31:0] cycle_count;
reg valid;
reg sgcycle;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
valid<=0;
cycle_count<=0;
sgcycle<=0;
end
else
begin
if(buttonpress)
begin
if(cycle_count==32'd999)
begin
if(!sgcycle)
begin
valid<=1;
sgcycle<=1;
end
else
begin
valid<=0;
end
end
else
begin
cycle_count<=cycle_count+32'h1;
end
end
else
begin
cycle_count<=32'h0;
valid<=0;
sgcycle<=0;
end
end
end
endmodule | module butt(
input clk,
input rst_n,
input buttonpress,
output button
); |
assign button = buttonpress;
reg [31:0] cycle_count;
reg valid;
reg sgcycle;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
valid<=0;
cycle_count<=0;
sgcycle<=0;
end
else
begin
if(buttonpress)
begin
if(cycle_count==32'd999)
begin
if(!sgcycle)
begin
valid<=1;
sgcycle<=1;
end
else
begin
valid<=0;
end
end
else
begin
cycle_count<=cycle_count+32'h1;
end
end
else
begin
cycle_count<=32'h0;
valid<=0;
sgcycle<=0;
end
end
end
endmodule | 0 |
6,180 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/DMemModule.v | 115,487,336 | DMemModule.v | v | 229 | 127 | [] | [] | [] | [(21, 228)] | null | null | 1: b'%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/DMemModule.v:58: Cannot find file containing module: \'DMem\'\nDMem u_DMem(\n^~~~\n ... Looked in:\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/DMem\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/DMem.v\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/DMem.sv\n DMem\n DMem.v\n DMem.sv\n obj_dir/DMem\n obj_dir/DMem.v\n obj_dir/DMem.sv\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/DMemModule.v:181: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s UNSIGNED generates 7 bits.\n : ... In instance DMemModule\nassign outdata = which==2\'h1 ? $unsigned(local_sw) : (which==2\'h2 ? douta : local_alu_ans);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 6,949 | module | module DMemModule(
input clk,
input rst_n,
input dmem_stall,
input dmem_bubble,
input [31:0] pc,
input [31:0] ir,
input [4:0] regaddr3,
input [31:0] alu_ans,
input [31:0] swdata,
input [5:0] optype,
input [6:0] sw,
output reg [5:0] to_optype,
output reg [4:0] to_regaddr3,
output [31:0] outdata,
output reg [31:0] smg,
output reg [7:0] led
);
wire we;
wire [31:0] douta;
assign we = optype==6'h14 ? 1 : 0;
DMem u_DMem(
clk,
we,
alu_ans[6:2],
swdata,
douta
);
reg [6:0] local_sw;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
smg<=32'h0;
led<=8'hFD;
local_sw<=7'h0;
end
else
begin
local_sw<=sw;
if(we && alu_ans==32'h78 )
begin
smg<=swdata;
end
else if(we && alu_ans==32'h7C )
begin
led<=swdata[7:0];
end
else
begin
end
end
end
reg [31:0] temp_aluans;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
temp_aluans<=32'hCCCC_CCCC;
else if(!dmem_stall)
temp_aluans<=alu_ans;
else
begin
end
end
reg [31:0] local_alu_ans;
reg [5:0] local_optype;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
local_alu_ans<=32'h0;
local_optype<=6'h3f;
end
else
begin
local_alu_ans<=alu_ans;
local_optype<=optype;
end
end
reg [1:0] which;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
which<=2'h0;
else
if(optype==6'h13 && alu_ans==32'h74)
which<=2'h1;
else if(optype==6'h13)
which<=2'h2;
else
which<=2'h3;
end
assign outdata = which==2'h1 ? $unsigned(local_sw) : (which==2'h2 ? douta : local_alu_ans);
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
to_optype<=6'h3F;
to_regaddr3<=5'h0;
end
else if(dmem_bubble)
begin
to_optype<=6'h3F;
end
else if(!dmem_stall)
begin
to_optype<=optype;
to_regaddr3<=regaddr3;
end
else
begin
end
end
endmodule | module DMemModule(
input clk,
input rst_n,
input dmem_stall,
input dmem_bubble,
input [31:0] pc,
input [31:0] ir,
input [4:0] regaddr3,
input [31:0] alu_ans,
input [31:0] swdata,
input [5:0] optype,
input [6:0] sw,
output reg [5:0] to_optype,
output reg [4:0] to_regaddr3,
output [31:0] outdata,
output reg [31:0] smg,
output reg [7:0] led
); |
wire we;
wire [31:0] douta;
assign we = optype==6'h14 ? 1 : 0;
DMem u_DMem(
clk,
we,
alu_ans[6:2],
swdata,
douta
);
reg [6:0] local_sw;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
smg<=32'h0;
led<=8'hFD;
local_sw<=7'h0;
end
else
begin
local_sw<=sw;
if(we && alu_ans==32'h78 )
begin
smg<=swdata;
end
else if(we && alu_ans==32'h7C )
begin
led<=swdata[7:0];
end
else
begin
end
end
end
reg [31:0] temp_aluans;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
temp_aluans<=32'hCCCC_CCCC;
else if(!dmem_stall)
temp_aluans<=alu_ans;
else
begin
end
end
reg [31:0] local_alu_ans;
reg [5:0] local_optype;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
local_alu_ans<=32'h0;
local_optype<=6'h3f;
end
else
begin
local_alu_ans<=alu_ans;
local_optype<=optype;
end
end
reg [1:0] which;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
which<=2'h0;
else
if(optype==6'h13 && alu_ans==32'h74)
which<=2'h1;
else if(optype==6'h13)
which<=2'h2;
else
which<=2'h3;
end
assign outdata = which==2'h1 ? $unsigned(local_sw) : (which==2'h2 ? douta : local_alu_ans);
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
to_optype<=6'h3F;
to_regaddr3<=5'h0;
end
else if(dmem_bubble)
begin
to_optype<=6'h3F;
end
else if(!dmem_stall)
begin
to_optype<=optype;
to_regaddr3<=regaddr3;
end
else
begin
end
end
endmodule | 0 |
6,181 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/IMemModule.v | 115,487,336 | IMemModule.v | v | 45 | 83 | [] | [] | [] | [(21, 44)] | null | null | 1: b"%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/IMemModule.v:30: Cannot find file containing module: 'IMem'\nIMem u_IMem(\n^~~~\n ... Looked in:\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/IMem\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/IMem.v\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/IMem.sv\n IMem\n IMem.v\n IMem.sv\n obj_dir/IMem\n obj_dir/IMem.v\n obj_dir/IMem.sv\n%Error: Exiting due to 1 error(s)\n" | 6,950 | module | module IMemModule(
input clk,
input rst_n,
input [31:0] addr,
output reg [31:0] pc,
output [31:0] ir
);
IMem u_IMem(
clk,
addr[8:2],
ir
);
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
pc<=32'h0;
else
pc<=addr;
end
endmodule | module IMemModule(
input clk,
input rst_n,
input [31:0] addr,
output reg [31:0] pc,
output [31:0] ir
); |
IMem u_IMem(
clk,
addr[8:2],
ir
);
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
pc<=32'h0;
else
pc<=addr;
end
endmodule | 0 |
6,182 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/interface.v | 115,487,336 | interface.v | v | 149 | 83 | [] | [] | [] | [(21, 148)] | null | null | 1: b"%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/interface.v:21: syntax error, unexpected interface, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule interface(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/interface.v:32: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n output reg [3:0] sel\n ^~~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/interface.v:33: syntax error, unexpected ')', expecting ',' or ';'\n );\n ^\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/interface.v:42: syntax error, unexpected always\nalways@(posedge clk or negedge rst_n)\n^~~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/interface.v:82: syntax error, unexpected always\nalways@(*)\n^~~~~~\n%Error: Exiting due to 5 error(s)\n" | 6,951 | module | module interface(
input clk,
input rst_n,
input button,
input [6:0] sw,
input [31:0] data,
output reg [7:0] smg,
output reg [3:0] sel
);
reg [1:0] tr;
reg [31:0] sw_count;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
sw_count<=32'd0;
tr<=2'b00;
end
else
begin
if(sw_count==32'd9)
begin
sw_count<=32'd0;
tr<=tr+2'h1;
end
else
begin
sw_count<=sw_count+32'd1;
end
end
end
always@(*)
begin
case(tr)
2'h0:
sel=4'b1110;
2'h1:
sel=4'b1101;
2'h2:
sel=4'b1011;
2'h3:
sel=4'b0111;
default:
sel=4'b1111;
endcase
end
reg [3:0] sgnum;
always@(*)
begin
if(sw[6])
begin
if(tr==2'h0)
sgnum=data[19:16];
else if(tr==2'h1)
sgnum=data[23:20];
else if(tr==2'h2)
sgnum=data[27:24];
else if(tr==2'h3)
sgnum=data[31:28];
else
begin
end
end
else
begin
if(tr==2'h0)
sgnum=data[3:0];
else if(tr==2'h1)
sgnum=data[7:4];
else if(tr==2'h2)
sgnum=data[11:8];
else if(tr==2'h3)
sgnum=data[15:12];
else
begin
end
end
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
smg<=8'h0;
end
else
begin
case(sgnum)
4'h0: smg <= 8'b0000_0011;
4'h1: smg <= 8'b1001_1111;
4'h2: smg <= 8'b0010_0101;
4'h3: smg <= 8'b0000_1101;
4'h4: smg <= 8'b1001_1001;
4'h5: smg <= 8'b0100_1001;
4'h6: smg <= 8'b0100_0001;
4'h7: smg <= 8'b0001_1111;
4'h8: smg <= 8'b0000_0001;
4'h9: smg <= 8'b0000_1001;
4'hA: smg <= 8'b0001_0001;
4'hb: smg <= 8'b1100_0001;
4'hC: smg <= 8'b0110_0011;
4'hd: smg <= 8'b1000_0101;
4'hE: smg <= 8'b0110_0001;
4'hF: smg <= 8'b0111_0001;
default:
smg<=8'b0;
endcase
end
end
endmodule | module interface(
input clk,
input rst_n,
input button,
input [6:0] sw,
input [31:0] data,
output reg [7:0] smg,
output reg [3:0] sel
); |
reg [1:0] tr;
reg [31:0] sw_count;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
sw_count<=32'd0;
tr<=2'b00;
end
else
begin
if(sw_count==32'd9)
begin
sw_count<=32'd0;
tr<=tr+2'h1;
end
else
begin
sw_count<=sw_count+32'd1;
end
end
end
always@(*)
begin
case(tr)
2'h0:
sel=4'b1110;
2'h1:
sel=4'b1101;
2'h2:
sel=4'b1011;
2'h3:
sel=4'b0111;
default:
sel=4'b1111;
endcase
end
reg [3:0] sgnum;
always@(*)
begin
if(sw[6])
begin
if(tr==2'h0)
sgnum=data[19:16];
else if(tr==2'h1)
sgnum=data[23:20];
else if(tr==2'h2)
sgnum=data[27:24];
else if(tr==2'h3)
sgnum=data[31:28];
else
begin
end
end
else
begin
if(tr==2'h0)
sgnum=data[3:0];
else if(tr==2'h1)
sgnum=data[7:4];
else if(tr==2'h2)
sgnum=data[11:8];
else if(tr==2'h3)
sgnum=data[15:12];
else
begin
end
end
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
smg<=8'h0;
end
else
begin
case(sgnum)
4'h0: smg <= 8'b0000_0011;
4'h1: smg <= 8'b1001_1111;
4'h2: smg <= 8'b0010_0101;
4'h3: smg <= 8'b0000_1101;
4'h4: smg <= 8'b1001_1001;
4'h5: smg <= 8'b0100_1001;
4'h6: smg <= 8'b0100_0001;
4'h7: smg <= 8'b0001_1111;
4'h8: smg <= 8'b0000_0001;
4'h9: smg <= 8'b0000_1001;
4'hA: smg <= 8'b0001_0001;
4'hb: smg <= 8'b1100_0001;
4'hC: smg <= 8'b0110_0011;
4'hd: smg <= 8'b1000_0101;
4'hE: smg <= 8'b0110_0001;
4'hF: smg <= 8'b0111_0001;
default:
smg<=8'b0;
endcase
end
end
endmodule | 0 |
6,183 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/interrupt.v | 115,487,336 | interrupt.v | v | 131 | 83 | [] | [] | [] | [(21, 130)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/interrupt.v:65: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n : ... In instance interrupt\n count<=15\'h0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/interrupt.v:73: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n : ... In instance interrupt\n count<=15\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/interrupt.v:70: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'15\'h1f4\' generates 15 bits.\n : ... In instance interrupt\n if(count==15\'d500)\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 6,952 | module | module interrupt(
input clk,
input rst_n,
input buttonint,
input syscall,
input RTI,
output reg to_syscall,
output reg to_button,
output reg start_int,
output reg [31:0] int_id
);
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
to_syscall<=0;
to_button<=0;
end
else
begin
to_syscall<=syscall;
to_button<=buttonint;
end
end
reg has_int;
reg citai;
reg [15:0] count;
reg resetflag;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
count<=15'h0;
resetflag<=0;
end
else if(has_int)
begin
if(count==15'd500)
begin
resetflag<=1;
count<=15'd0;
end
else
begin
resetflag<=0;
count<=count+15'h1;
end
end
else
begin
end
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
has_int<=0;
start_int<=0;
int_id<=0;
end
else if(!citai)
begin
if(buttonint)
begin
int_id<=32'h4;
has_int<=1;
start_int<=1;
end
else if(syscall)
begin
int_id<=32'h0;
has_int<=1;
start_int<=1;
end
else
begin
end
end
else
begin
if(RTI)
has_int<=0;
else if(resetflag)
has_int<=0;
else
has_int<=citai;
start_int<=0;
end
end
always@(*)
begin
citai=has_int;
end
endmodule | module interrupt(
input clk,
input rst_n,
input buttonint,
input syscall,
input RTI,
output reg to_syscall,
output reg to_button,
output reg start_int,
output reg [31:0] int_id
); |
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
to_syscall<=0;
to_button<=0;
end
else
begin
to_syscall<=syscall;
to_button<=buttonint;
end
end
reg has_int;
reg citai;
reg [15:0] count;
reg resetflag;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
count<=15'h0;
resetflag<=0;
end
else if(has_int)
begin
if(count==15'd500)
begin
resetflag<=1;
count<=15'd0;
end
else
begin
resetflag<=0;
count<=count+15'h1;
end
end
else
begin
end
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
has_int<=0;
start_int<=0;
int_id<=0;
end
else if(!citai)
begin
if(buttonint)
begin
int_id<=32'h4;
has_int<=1;
start_int<=1;
end
else if(syscall)
begin
int_id<=32'h0;
has_int<=1;
start_int<=1;
end
else
begin
end
end
else
begin
if(RTI)
has_int<=0;
else if(resetflag)
has_int<=0;
else
has_int<=citai;
start_int<=0;
end
end
always@(*)
begin
citai=has_int;
end
endmodule | 0 |
6,184 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/IR_reg.v | 115,487,336 | IR_reg.v | v | 609 | 110 | [] | [] | [] | [(21, 608)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/IR_reg.v:323: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 5 bits.\n : ... In instance IR_reg\n tpimm<=$unsigned(ir[10:6]);\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/IR_reg.v:325: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n : ... In instance IR_reg\n tpimm<=$signed(ir[15:0]);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/IR_reg.v:327: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 16 bits.\n : ... In instance IR_reg\n tpimm<=$unsigned(ir[15:0]);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/IR_reg.v:329: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 28 bits.\n : ... In instance IR_reg\n tpimm<={$unsigned(ir[25:0]),2\'h0};\n ^~\n%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/IR_reg.v:595: Cannot find file containing module: \'REG_FILE\'\nREG_FILE u_REG_FILE(\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/REG_FILE\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/REG_FILE.v\n data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/REG_FILE.sv\n REG_FILE\n REG_FILE.v\n REG_FILE.sv\n obj_dir/REG_FILE\n obj_dir/REG_FILE.v\n obj_dir/REG_FILE.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n' | 6,953 | module | module IR_reg(
input clk,
input rst_n,
input [31:0] pc,
input [31:0] ir,
input is_int,
input ir_stall,
input ir_bubble,
input preg_we,
input [4:0] pregaddr3,
input [31:0] pregvalue3,
output reg [31:0] next_pc,
output reg [31:0] next_ir,
output reg [4:0] regaddr1,
output reg [4:0] regaddr2,
output reg [4:0] regaddr3,
output [31:0] alu_a,
output [31:0] alu_b,
output [31:0] swdata,
output reg [4:0] op,
output reg [5:0] optype,
output reg RTI,
output syscall
);
assign syscall = ir==32'h0000_000C ? 1 : 0;
wire [31:0] regout1;
wire [31:0] regout2;
assign swdata = regout2;
reg [31:0] next_temppc;
reg [31:0] local_swdata;
reg [4:0] ir_local_regaddr1;
reg [4:0] ir_local_regaddr2;
reg [4:0] ir_local_regaddr3;
reg [5:0] ir_local_optype;
reg [4:0] ir_local_op;
always@(*)
begin
if(ir_stall)
begin
ir_local_op=op;
ir_local_optype=optype;
next_temppc=next_pc;
end
else if(ir_bubble || is_int)
begin
ir_local_op=5'h0;
ir_local_optype=6'h3F;
end
else if(ir==32'h0)
begin
ir_local_op=5'h0;
ir_local_optype=6'h3F;
end
else if(ir==32'h4200_0018)
begin
ir_local_optype=6'h20;
end
else if(ir==32'h0000_000C)
begin
ir_local_op=5'h12;
ir_local_optype=6'h21;
end
else
begin
next_temppc=pc;
case(ir[31:26])
6'h0:
begin
if(ir[5:0]==6'b001000)
begin
ir_local_optype=6'h10;
ir_local_op=5'h12;
end
else if(ir[5:0] == 6'b000000)
begin
ir_local_op=5'hD;
ir_local_optype=6'h01;
end
else if(ir[5:0] == 6'b000010)
begin
ir_local_op=5'hE;
ir_local_optype=6'h01;
end
else if(ir[5:0] == 6'b000011)
begin
ir_local_op=5'hF;
ir_local_optype=6'h01;
end
else
begin
ir_local_optype=6'h00;
if(ir[5:0]==6'b10_0000)
begin
ir_local_op=5'h01;
end
else if(ir[5:0]==6'b10_0001)
begin
ir_local_op=5'h01;
end
else if(ir[5:0]==6'b10_0010)
begin
ir_local_op=5'h02;
end
else if(ir[5:0]==6'b10_0011)
begin
ir_local_op=5'h02;
end
else if(ir[5:0]==6'b10_0100)
begin
ir_local_op=5'h03;
end
else if(ir[5:0]==6'b10_0101)
begin
ir_local_op=5'h04;
end
else if(ir[5:0]==6'b10_0110)
begin
ir_local_op=5'h05;
end
else if(ir[5:0]==6'b10_0111)
begin
ir_local_op=5'h06;
end
else if(ir[5:0]==6'b00_0100)
begin
ir_local_op=5'h0D;
end
else if(ir[5:0]==6'b00_0110)
begin
ir_local_op=5'h0E;
end
else if(ir[5:0]==6'b00_0111)
begin
ir_local_op=5'h0F;
end
else
begin
end
end
end
6'b01_1100:
begin
if(ir[5:0]==6'b10_0001)
begin
ir_local_optype=6'h02;
ir_local_op=5'h1E;
end
else if(ir[5:0]==6'b10_0000)
begin
ir_local_optype=6'h02;
ir_local_op=5'h1F;
end
else
begin
end
end
6'b00_1000:
begin
ir_local_optype=6'h04;
ir_local_op=5'h01;
end
6'b00_1100:
begin
ir_local_optype=6'h05;
ir_local_op=5'h03;
end
6'b00_1101:
begin
ir_local_optype=6'h05;
ir_local_op=5'h04;
end
6'b00_1110:
begin
ir_local_optype=6'h05;
ir_local_op=5'h05;
end
6'b00_1111:
begin
ir_local_optype=6'h06;
ir_local_op=5'h10;
end
6'b00_1001:
begin
ir_local_optype=6'h06;
ir_local_op=5'h11;
end
6'b00_0010:
begin
ir_local_optype=6'h11;
ir_local_op=5'h13;
end
6'b00_0100:
begin
ir_local_optype=6'h12;
ir_local_op=5'h0B;
end
6'b00_0101:
begin
ir_local_optype=6'h12;
ir_local_op=5'h0C;
end
6'b00_0111:
begin
ir_local_optype=6'h12;
ir_local_op=5'h07;
end
6'b00_0110:
begin
ir_local_optype=6'h12;
ir_local_op=5'h0A;
end
6'b00_0001:
begin
if(ir[16])
begin
ir_local_optype=6'h12;
ir_local_op=5'h08;
end
else
begin
ir_local_optype=6'h12;
ir_local_op=5'h09;
end
end
6'b10_0011:
begin
ir_local_optype=6'h13;
ir_local_op=5'h01;
end
6'b101011:
begin
ir_local_optype=6'h14;
ir_local_op=5'h01;
end
default:
begin
end
endcase
end
end
reg [31:0] tpimm;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
tpimm<=32'h0;
end
else
begin
if(ir_local_optype==6'h01)
tpimm<=$unsigned(ir[10:6]);
else if(ir_local_optype==6'h04 || ir_local_optype==6'h13 || ir_local_optype==6'h14)
tpimm<=$signed(ir[15:0]);
else if(ir_local_optype==6'h05 || ir_local_optype==6'h06)
tpimm<=$unsigned(ir[15:0]);
else if(ir_local_optype==6'h11)
tpimm<={$unsigned(ir[25:0]),2'h0};
else
begin
end
end
end
reg is_reg_or_imm;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
is_reg_or_imm<=0;
end
else
begin
if(ir_local_optype==6'h01 || ir_local_optype==6'h04 || ir_local_optype==6'h05
|| ir_local_optype==6'h06 || ir_local_optype==6'h13 || ir_local_optype==6'h14 || ir_local_optype==6'h11)
begin
is_reg_or_imm<=1;
end
else
is_reg_or_imm<=0;
end
end
reg is_shamt;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
is_shamt<=0;
else
begin
if(ir_local_optype==6'h01)
is_shamt<=1;
else
is_shamt<=0;
end
end
assign alu_a = is_shamt? regout2 : regout1;
assign alu_b = is_reg_or_imm ? tpimm : regout2;
always@(*)
begin
RTI=0;
if(ir_stall)
begin
ir_local_regaddr1=regaddr1;
ir_local_regaddr2=regaddr2;
ir_local_regaddr3=regaddr3;
end
else if(ir_local_optype==6'h3F)
begin
ir_local_regaddr1=5'h0;
ir_local_regaddr2=5'h0;
ir_local_regaddr3=5'h0;
end
else if(ir_local_optype==6'h00)
begin
ir_local_regaddr1=ir[25:21];
ir_local_regaddr2=ir[20:16];
ir_local_regaddr3=ir[15:11];
end
else if(ir_local_optype==6'h01)
begin
ir_local_regaddr1=ir[20:16];
ir_local_regaddr3=ir[15:11];
end
else if(ir_local_optype==6'h02)
begin
ir_local_regaddr1=ir[25:21];
ir_local_regaddr3=ir[15:11];
end
else if(ir_local_optype==6'h04)
begin
ir_local_regaddr1=ir[25:21];
ir_local_regaddr3=ir[20:16];
end
else if(ir_local_optype==6'h05)
begin
ir_local_regaddr1=ir[25:21];
ir_local_regaddr3=ir[20:16];
end
else if(ir_local_optype==6'h06)
begin
ir_local_regaddr3=ir[20:16];
end
else if(ir_local_optype==6'h10)
begin
ir_local_regaddr1=ir[25:21];
end
else if(ir_local_optype==6'h11)
begin
end
else if(ir_local_optype==6'h12)
begin
ir_local_regaddr1=ir[25:21];
ir_local_regaddr2=ir[20:16];
end
else if(ir_local_optype==6'h13)
begin
ir_local_regaddr1=ir[25:21];
ir_local_regaddr3=ir[20:16];
end
else if(ir_local_optype==6'h14)
begin
ir_local_regaddr1=ir[25:21];
ir_local_regaddr2=ir[20:16];
end
else if(ir_local_optype==6'h20)
begin
RTI=1;
end
else if(ir_local_optype==6'h21)
begin
ir_local_regaddr1=5'h2;
end
else
begin
end
end
reg two_bubble;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
optype<=6'h3F;
op<=5'h0;
regaddr1<=5'h0;
regaddr2<=5'h0;
regaddr3<=5'h0;
next_pc<=32'h0;
next_ir<=32'h0;
two_bubble<=1;
end
else
begin
next_pc<=next_temppc;
next_ir<=ir;
if(two_bubble)
begin
two_bubble<=0;
optype<=6'h3F;
end
else
begin
optype<=ir_local_optype;
end
op<=ir_local_op;
regaddr1<=ir_local_regaddr1;
regaddr2<=ir_local_regaddr2;
regaddr3<=ir_local_regaddr3;
end
end
REG_FILE u_REG_FILE(
.clk(clk),
.rst_n(rst_n),
.r1_addr(ir_local_regaddr1),
.r2_addr(ir_local_regaddr2),
.r3_addr(pregaddr3),
.r3_din(pregvalue3),
.r3_wr(preg_we),
.r1_dout(regout1),
.r2_dout(regout2)
);
endmodule | module IR_reg(
input clk,
input rst_n,
input [31:0] pc,
input [31:0] ir,
input is_int,
input ir_stall,
input ir_bubble,
input preg_we,
input [4:0] pregaddr3,
input [31:0] pregvalue3,
output reg [31:0] next_pc,
output reg [31:0] next_ir,
output reg [4:0] regaddr1,
output reg [4:0] regaddr2,
output reg [4:0] regaddr3,
output [31:0] alu_a,
output [31:0] alu_b,
output [31:0] swdata,
output reg [4:0] op,
output reg [5:0] optype,
output reg RTI,
output syscall
); |
assign syscall = ir==32'h0000_000C ? 1 : 0;
wire [31:0] regout1;
wire [31:0] regout2;
assign swdata = regout2;
reg [31:0] next_temppc;
reg [31:0] local_swdata;
reg [4:0] ir_local_regaddr1;
reg [4:0] ir_local_regaddr2;
reg [4:0] ir_local_regaddr3;
reg [5:0] ir_local_optype;
reg [4:0] ir_local_op;
always@(*)
begin
if(ir_stall)
begin
ir_local_op=op;
ir_local_optype=optype;
next_temppc=next_pc;
end
else if(ir_bubble || is_int)
begin
ir_local_op=5'h0;
ir_local_optype=6'h3F;
end
else if(ir==32'h0)
begin
ir_local_op=5'h0;
ir_local_optype=6'h3F;
end
else if(ir==32'h4200_0018)
begin
ir_local_optype=6'h20;
end
else if(ir==32'h0000_000C)
begin
ir_local_op=5'h12;
ir_local_optype=6'h21;
end
else
begin
next_temppc=pc;
case(ir[31:26])
6'h0:
begin
if(ir[5:0]==6'b001000)
begin
ir_local_optype=6'h10;
ir_local_op=5'h12;
end
else if(ir[5:0] == 6'b000000)
begin
ir_local_op=5'hD;
ir_local_optype=6'h01;
end
else if(ir[5:0] == 6'b000010)
begin
ir_local_op=5'hE;
ir_local_optype=6'h01;
end
else if(ir[5:0] == 6'b000011)
begin
ir_local_op=5'hF;
ir_local_optype=6'h01;
end
else
begin
ir_local_optype=6'h00;
if(ir[5:0]==6'b10_0000)
begin
ir_local_op=5'h01;
end
else if(ir[5:0]==6'b10_0001)
begin
ir_local_op=5'h01;
end
else if(ir[5:0]==6'b10_0010)
begin
ir_local_op=5'h02;
end
else if(ir[5:0]==6'b10_0011)
begin
ir_local_op=5'h02;
end
else if(ir[5:0]==6'b10_0100)
begin
ir_local_op=5'h03;
end
else if(ir[5:0]==6'b10_0101)
begin
ir_local_op=5'h04;
end
else if(ir[5:0]==6'b10_0110)
begin
ir_local_op=5'h05;
end
else if(ir[5:0]==6'b10_0111)
begin
ir_local_op=5'h06;
end
else if(ir[5:0]==6'b00_0100)
begin
ir_local_op=5'h0D;
end
else if(ir[5:0]==6'b00_0110)
begin
ir_local_op=5'h0E;
end
else if(ir[5:0]==6'b00_0111)
begin
ir_local_op=5'h0F;
end
else
begin
end
end
end
6'b01_1100:
begin
if(ir[5:0]==6'b10_0001)
begin
ir_local_optype=6'h02;
ir_local_op=5'h1E;
end
else if(ir[5:0]==6'b10_0000)
begin
ir_local_optype=6'h02;
ir_local_op=5'h1F;
end
else
begin
end
end
6'b00_1000:
begin
ir_local_optype=6'h04;
ir_local_op=5'h01;
end
6'b00_1100:
begin
ir_local_optype=6'h05;
ir_local_op=5'h03;
end
6'b00_1101:
begin
ir_local_optype=6'h05;
ir_local_op=5'h04;
end
6'b00_1110:
begin
ir_local_optype=6'h05;
ir_local_op=5'h05;
end
6'b00_1111:
begin
ir_local_optype=6'h06;
ir_local_op=5'h10;
end
6'b00_1001:
begin
ir_local_optype=6'h06;
ir_local_op=5'h11;
end
6'b00_0010:
begin
ir_local_optype=6'h11;
ir_local_op=5'h13;
end
6'b00_0100:
begin
ir_local_optype=6'h12;
ir_local_op=5'h0B;
end
6'b00_0101:
begin
ir_local_optype=6'h12;
ir_local_op=5'h0C;
end
6'b00_0111:
begin
ir_local_optype=6'h12;
ir_local_op=5'h07;
end
6'b00_0110:
begin
ir_local_optype=6'h12;
ir_local_op=5'h0A;
end
6'b00_0001:
begin
if(ir[16])
begin
ir_local_optype=6'h12;
ir_local_op=5'h08;
end
else
begin
ir_local_optype=6'h12;
ir_local_op=5'h09;
end
end
6'b10_0011:
begin
ir_local_optype=6'h13;
ir_local_op=5'h01;
end
6'b101011:
begin
ir_local_optype=6'h14;
ir_local_op=5'h01;
end
default:
begin
end
endcase
end
end
reg [31:0] tpimm;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
tpimm<=32'h0;
end
else
begin
if(ir_local_optype==6'h01)
tpimm<=$unsigned(ir[10:6]);
else if(ir_local_optype==6'h04 || ir_local_optype==6'h13 || ir_local_optype==6'h14)
tpimm<=$signed(ir[15:0]);
else if(ir_local_optype==6'h05 || ir_local_optype==6'h06)
tpimm<=$unsigned(ir[15:0]);
else if(ir_local_optype==6'h11)
tpimm<={$unsigned(ir[25:0]),2'h0};
else
begin
end
end
end
reg is_reg_or_imm;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
is_reg_or_imm<=0;
end
else
begin
if(ir_local_optype==6'h01 || ir_local_optype==6'h04 || ir_local_optype==6'h05
|| ir_local_optype==6'h06 || ir_local_optype==6'h13 || ir_local_optype==6'h14 || ir_local_optype==6'h11)
begin
is_reg_or_imm<=1;
end
else
is_reg_or_imm<=0;
end
end
reg is_shamt;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
is_shamt<=0;
else
begin
if(ir_local_optype==6'h01)
is_shamt<=1;
else
is_shamt<=0;
end
end
assign alu_a = is_shamt? regout2 : regout1;
assign alu_b = is_reg_or_imm ? tpimm : regout2;
always@(*)
begin
RTI=0;
if(ir_stall)
begin
ir_local_regaddr1=regaddr1;
ir_local_regaddr2=regaddr2;
ir_local_regaddr3=regaddr3;
end
else if(ir_local_optype==6'h3F)
begin
ir_local_regaddr1=5'h0;
ir_local_regaddr2=5'h0;
ir_local_regaddr3=5'h0;
end
else if(ir_local_optype==6'h00)
begin
ir_local_regaddr1=ir[25:21];
ir_local_regaddr2=ir[20:16];
ir_local_regaddr3=ir[15:11];
end
else if(ir_local_optype==6'h01)
begin
ir_local_regaddr1=ir[20:16];
ir_local_regaddr3=ir[15:11];
end
else if(ir_local_optype==6'h02)
begin
ir_local_regaddr1=ir[25:21];
ir_local_regaddr3=ir[15:11];
end
else if(ir_local_optype==6'h04)
begin
ir_local_regaddr1=ir[25:21];
ir_local_regaddr3=ir[20:16];
end
else if(ir_local_optype==6'h05)
begin
ir_local_regaddr1=ir[25:21];
ir_local_regaddr3=ir[20:16];
end
else if(ir_local_optype==6'h06)
begin
ir_local_regaddr3=ir[20:16];
end
else if(ir_local_optype==6'h10)
begin
ir_local_regaddr1=ir[25:21];
end
else if(ir_local_optype==6'h11)
begin
end
else if(ir_local_optype==6'h12)
begin
ir_local_regaddr1=ir[25:21];
ir_local_regaddr2=ir[20:16];
end
else if(ir_local_optype==6'h13)
begin
ir_local_regaddr1=ir[25:21];
ir_local_regaddr3=ir[20:16];
end
else if(ir_local_optype==6'h14)
begin
ir_local_regaddr1=ir[25:21];
ir_local_regaddr2=ir[20:16];
end
else if(ir_local_optype==6'h20)
begin
RTI=1;
end
else if(ir_local_optype==6'h21)
begin
ir_local_regaddr1=5'h2;
end
else
begin
end
end
reg two_bubble;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
optype<=6'h3F;
op<=5'h0;
regaddr1<=5'h0;
regaddr2<=5'h0;
regaddr3<=5'h0;
next_pc<=32'h0;
next_ir<=32'h0;
two_bubble<=1;
end
else
begin
next_pc<=next_temppc;
next_ir<=ir;
if(two_bubble)
begin
two_bubble<=0;
optype<=6'h3F;
end
else
begin
optype<=ir_local_optype;
end
op<=ir_local_op;
regaddr1<=ir_local_regaddr1;
regaddr2<=ir_local_regaddr2;
regaddr3<=ir_local_regaddr3;
end
end
REG_FILE u_REG_FILE(
.clk(clk),
.rst_n(rst_n),
.r1_addr(ir_local_regaddr1),
.r2_addr(ir_local_regaddr2),
.r3_addr(pregaddr3),
.r3_din(pregvalue3),
.r3_wr(preg_we),
.r1_dout(regout1),
.r2_dout(regout2)
);
endmodule | 0 |
6,185 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/pc.v | 115,487,336 | pc.v | v | 123 | 83 | [] | [] | [] | [(21, 122)] | null | data/verilator_xmls/d1423282-32ae-4b4b-b7a9-cd9a28da72bd.xml | null | 6,954 | module | module pc(
input clk,
input rst_n,
input syscall,
input button,
input [31:0] target,
input [31:0] int_id,
input start_int,
input RTI,
input pc_stall,
input pc_jump,
output [31:0] pc
);
assign pc=now_pc;
reg [31:0] now_pc;
reg [31:0] next_pc;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
now_pc<=32'b0;
else
now_pc<=next_pc;
end
reg [31:0] int_pc;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
int_pc<=32'b0;
else if(start_int && syscall)
int_pc<=now_pc-32'h4;
else if(start_int && button)
int_pc<=now_pc-32'h8;
else
begin
end
end
reg flg;
reg [2:0] ct;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
flg<=0;
ct<=3'h0;
end
else
begin
if(start_int && button)
flg<=1;
else
begin
end
if(ct!=3'h3 && flg)
begin
ct<=ct+3'h1;
end
else
begin
ct<=3'h0;
flg<=0;
end
end
end
wire [31:0] base;
assign base = 32'h40;
always@(*)
begin
if(RTI)
next_pc=int_pc;
else if(start_int)
next_pc=(base+int_id)<<2;
else if(pc_stall)
next_pc=now_pc;
else if(pc_jump)
next_pc=target;
else
next_pc=now_pc+32'h4;
end
endmodule | module pc(
input clk,
input rst_n,
input syscall,
input button,
input [31:0] target,
input [31:0] int_id,
input start_int,
input RTI,
input pc_stall,
input pc_jump,
output [31:0] pc
); |
assign pc=now_pc;
reg [31:0] now_pc;
reg [31:0] next_pc;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
now_pc<=32'b0;
else
now_pc<=next_pc;
end
reg [31:0] int_pc;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
int_pc<=32'b0;
else if(start_int && syscall)
int_pc<=now_pc-32'h4;
else if(start_int && button)
int_pc<=now_pc-32'h8;
else
begin
end
end
reg flg;
reg [2:0] ct;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
flg<=0;
ct<=3'h0;
end
else
begin
if(start_int && button)
flg<=1;
else
begin
end
if(ct!=3'h3 && flg)
begin
ct<=ct+3'h1;
end
else
begin
ct<=3'h0;
flg<=0;
end
end
end
wire [31:0] base;
assign base = 32'h40;
always@(*)
begin
if(RTI)
next_pc=int_pc;
else if(start_int)
next_pc=(base+int_id)<<2;
else if(pc_stall)
next_pc=now_pc;
else if(pc_jump)
next_pc=target;
else
next_pc=now_pc+32'h4;
end
endmodule | 0 |
6,186 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/REG_FILE.v | 115,487,336 | REG_FILE.v | v | 184 | 98 | [] | [] | [] | [(21, 183)] | null | data/verilator_xmls/137d29cc-8e0d-4c2a-b3bc-aef916d7f8e8.xml | null | 6,955 | module | module REG_FILE(
input clk,
input rst_n,
input [4:0] r1_addr,
input [4:0] r2_addr,
input [4:0] r3_addr,
input [31:0] r3_din,
input r3_wr,
output [31:0] r1_dout,
output [31:0] r2_dout
);
reg [31:0] now_regs[31:0];
reg [31:0] next_regs[31:0];
reg [4:0] local_r1_addr;
reg [4:0] local_r2_addr;
assign r1_dout= (r3_wr == 1 && local_r1_addr==r3_addr) ? r3_din : now_regs[local_r1_addr][31:0];
assign r2_dout= (r3_wr == 1 && local_r2_addr==r3_addr) ? r3_din : now_regs[local_r2_addr][31:0];
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
local_r1_addr<=5'h0;
local_r2_addr<=5'h0;
end
else
begin
local_r1_addr<=r1_addr;
local_r2_addr<=r2_addr;
end
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
now_regs[0]<=32'b0;
now_regs[1]<=32'b0;
now_regs[2]<=32'b0;
now_regs[3]<=32'b0;
now_regs[4]<=32'b0;
now_regs[5]<=32'b0;
now_regs[6]<=32'b0;
now_regs[7]<=32'b0;
now_regs[8]<=32'b0;
now_regs[9]<=32'b0;
now_regs[10]<=32'b0;
now_regs[11]<=32'b0;
now_regs[12]<=32'b0;
now_regs[13]<=32'b0;
now_regs[14]<=32'b0;
now_regs[15]<=32'b0;
now_regs[16]<=32'b0;
now_regs[17]<=32'b0;
now_regs[18]<=32'b0;
now_regs[19]<=32'b0;
now_regs[20]<=32'b0;
now_regs[21]<=32'b0;
now_regs[22]<=32'b0;
now_regs[23]<=32'b0;
now_regs[24]<=32'b0;
now_regs[25]<=32'b0;
now_regs[26]<=32'b0;
now_regs[27]<=32'b0;
now_regs[28]<=32'b0;
now_regs[29]<=32'b0;
now_regs[30]<=32'b0;
now_regs[31]<=32'b0;
end
else
begin
now_regs[0]<=next_regs[0];
now_regs[1]<=next_regs[1];
now_regs[2]<=next_regs[2];
now_regs[3]<=next_regs[3];
now_regs[4]<=next_regs[4];
now_regs[5]<=next_regs[5];
now_regs[6]<=next_regs[6];
now_regs[7]<=next_regs[7];
now_regs[8]<=next_regs[8];
now_regs[9]<=next_regs[9];
now_regs[10]<=next_regs[10];
now_regs[11]<=next_regs[11];
now_regs[12]<=next_regs[12];
now_regs[13]<=next_regs[13];
now_regs[14]<=next_regs[14];
now_regs[15]<=next_regs[15];
now_regs[16]<=next_regs[16];
now_regs[17]<=next_regs[17];
now_regs[18]<=next_regs[18];
now_regs[19]<=next_regs[19];
now_regs[20]<=next_regs[20];
now_regs[21]<=next_regs[21];
now_regs[22]<=next_regs[22];
now_regs[23]<=next_regs[23];
now_regs[24]<=next_regs[24];
now_regs[25]<=next_regs[25];
now_regs[26]<=next_regs[26];
now_regs[27]<=next_regs[27];
now_regs[28]<=next_regs[28];
now_regs[29]<=next_regs[29];
now_regs[30]<=next_regs[30];
now_regs[31]<=next_regs[31];
end
if(r3_wr)
now_regs[r3_addr]<=r3_din;
else
begin
end
end
always@(*)
begin
next_regs[0]=now_regs[0];
next_regs[1]=now_regs[1];
next_regs[2]=now_regs[2];
next_regs[3]=now_regs[3];
next_regs[4]=now_regs[4];
next_regs[5]=now_regs[5];
next_regs[6]=now_regs[6];
next_regs[7]=now_regs[7];
next_regs[8]=now_regs[8];
next_regs[9]=now_regs[9];
next_regs[10]=now_regs[10];
next_regs[11]=now_regs[11];
next_regs[12]=now_regs[12];
next_regs[13]=now_regs[13];
next_regs[14]=now_regs[14];
next_regs[15]=now_regs[15];
next_regs[16]=now_regs[16];
next_regs[17]=now_regs[17];
next_regs[18]=now_regs[18];
next_regs[19]=now_regs[19];
next_regs[20]=now_regs[20];
next_regs[21]=now_regs[21];
next_regs[22]=now_regs[22];
next_regs[23]=now_regs[23];
next_regs[24]=now_regs[24];
next_regs[25]=now_regs[25];
next_regs[26]=now_regs[26];
next_regs[27]=now_regs[27];
next_regs[28]=now_regs[28];
next_regs[29]=now_regs[29];
next_regs[30]=now_regs[30];
next_regs[31]=now_regs[31];
end
endmodule | module REG_FILE(
input clk,
input rst_n,
input [4:0] r1_addr,
input [4:0] r2_addr,
input [4:0] r3_addr,
input [31:0] r3_din,
input r3_wr,
output [31:0] r1_dout,
output [31:0] r2_dout
); |
reg [31:0] now_regs[31:0];
reg [31:0] next_regs[31:0];
reg [4:0] local_r1_addr;
reg [4:0] local_r2_addr;
assign r1_dout= (r3_wr == 1 && local_r1_addr==r3_addr) ? r3_din : now_regs[local_r1_addr][31:0];
assign r2_dout= (r3_wr == 1 && local_r2_addr==r3_addr) ? r3_din : now_regs[local_r2_addr][31:0];
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
local_r1_addr<=5'h0;
local_r2_addr<=5'h0;
end
else
begin
local_r1_addr<=r1_addr;
local_r2_addr<=r2_addr;
end
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
now_regs[0]<=32'b0;
now_regs[1]<=32'b0;
now_regs[2]<=32'b0;
now_regs[3]<=32'b0;
now_regs[4]<=32'b0;
now_regs[5]<=32'b0;
now_regs[6]<=32'b0;
now_regs[7]<=32'b0;
now_regs[8]<=32'b0;
now_regs[9]<=32'b0;
now_regs[10]<=32'b0;
now_regs[11]<=32'b0;
now_regs[12]<=32'b0;
now_regs[13]<=32'b0;
now_regs[14]<=32'b0;
now_regs[15]<=32'b0;
now_regs[16]<=32'b0;
now_regs[17]<=32'b0;
now_regs[18]<=32'b0;
now_regs[19]<=32'b0;
now_regs[20]<=32'b0;
now_regs[21]<=32'b0;
now_regs[22]<=32'b0;
now_regs[23]<=32'b0;
now_regs[24]<=32'b0;
now_regs[25]<=32'b0;
now_regs[26]<=32'b0;
now_regs[27]<=32'b0;
now_regs[28]<=32'b0;
now_regs[29]<=32'b0;
now_regs[30]<=32'b0;
now_regs[31]<=32'b0;
end
else
begin
now_regs[0]<=next_regs[0];
now_regs[1]<=next_regs[1];
now_regs[2]<=next_regs[2];
now_regs[3]<=next_regs[3];
now_regs[4]<=next_regs[4];
now_regs[5]<=next_regs[5];
now_regs[6]<=next_regs[6];
now_regs[7]<=next_regs[7];
now_regs[8]<=next_regs[8];
now_regs[9]<=next_regs[9];
now_regs[10]<=next_regs[10];
now_regs[11]<=next_regs[11];
now_regs[12]<=next_regs[12];
now_regs[13]<=next_regs[13];
now_regs[14]<=next_regs[14];
now_regs[15]<=next_regs[15];
now_regs[16]<=next_regs[16];
now_regs[17]<=next_regs[17];
now_regs[18]<=next_regs[18];
now_regs[19]<=next_regs[19];
now_regs[20]<=next_regs[20];
now_regs[21]<=next_regs[21];
now_regs[22]<=next_regs[22];
now_regs[23]<=next_regs[23];
now_regs[24]<=next_regs[24];
now_regs[25]<=next_regs[25];
now_regs[26]<=next_regs[26];
now_regs[27]<=next_regs[27];
now_regs[28]<=next_regs[28];
now_regs[29]<=next_regs[29];
now_regs[30]<=next_regs[30];
now_regs[31]<=next_regs[31];
end
if(r3_wr)
now_regs[r3_addr]<=r3_din;
else
begin
end
end
always@(*)
begin
next_regs[0]=now_regs[0];
next_regs[1]=now_regs[1];
next_regs[2]=now_regs[2];
next_regs[3]=now_regs[3];
next_regs[4]=now_regs[4];
next_regs[5]=now_regs[5];
next_regs[6]=now_regs[6];
next_regs[7]=now_regs[7];
next_regs[8]=now_regs[8];
next_regs[9]=now_regs[9];
next_regs[10]=now_regs[10];
next_regs[11]=now_regs[11];
next_regs[12]=now_regs[12];
next_regs[13]=now_regs[13];
next_regs[14]=now_regs[14];
next_regs[15]=now_regs[15];
next_regs[16]=now_regs[16];
next_regs[17]=now_regs[17];
next_regs[18]=now_regs[18];
next_regs[19]=now_regs[19];
next_regs[20]=now_regs[20];
next_regs[21]=now_regs[21];
next_regs[22]=now_regs[22];
next_regs[23]=now_regs[23];
next_regs[24]=now_regs[24];
next_regs[25]=now_regs[25];
next_regs[26]=now_regs[26];
next_regs[27]=now_regs[27];
next_regs[28]=now_regs[28];
next_regs[29]=now_regs[29];
next_regs[30]=now_regs[30];
next_regs[31]=now_regs[31];
end
endmodule | 0 |
6,187 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/top.v | 115,487,336 | top.v | v | 352 | 94 | [] | [] | [] | [(21, 351)] | null | null | 1: b"%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/top.v:50: syntax error, unexpected '.', expecting '['\n .clk(clk),\n ^\n%Error: Internal Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/top.v:21: ../V3ParseSym.h:114: Symbols suggest ending IFACE 'u_interface' but parser thinks ending MODULE 'top'\nmodule top(\n ^~~\n" | 6,956 | module | module top(
input clk,
input rst_n,
input [6:0] sw,
input buttonpress,
output [7:0] smg,
output [3:0] sel,
output [7:0] led
);
wire button;
butt u_butt(
.clk(clk),
.rst_n(rst_n),
.buttonpress(buttonpress),
.button(button)
);
wire [31:0] smgdata;
interface u_interface(
.clk(clk),
.rst_n(rst_n),
.button(button),
.sw(sw),
.data(smgdata),
.smg(smg),
.sel(sel)
);
wire ir_to_int_syscall;
wire imem_to_int_RTI;
wire int_to_pc_start_int;
wire [31:0] int_to_pc_int_id;
wire int_to_pc_syscall;
wire int_to_pc_button;
wire [4:0] dmem_to_wb_regaddr3;
wire [4:0] wb_to_reg_regaddr3;
wire [31:0] wb_to_reg_delay_regdata;
wire wb_to_reg_reg_we;
interrupt u_interrupt(
.clk(clk),
.rst_n(rst_n),
.buttonint(button),
.syscall(ir_to_int_syscall),
.RTI(imem_to_int_RTI),
.to_syscall(int_to_pc_syscall),
.to_button(int_to_pc_button),
.start_int(int_to_pc_start_int),
.int_id(int_to_pc_int_id)
);
wire [31:0] branch_to_pc_target;
wire pc_stall;
wire pc_jump;
wire [31:0] pc_to_imem_pc;
pc u_pc(
.clk(clk),
.rst_n(rst_n),
.syscall(int_to_pc_syscall),
.button(int_to_pc_button),
.target(branch_to_pc_target),
.int_id(int_to_pc_int_id),
.start_int(int_to_pc_start_int),
.RTI(imem_to_int_RTI),
.pc_stall(pc_stall),
.pc_jump(pc_jump),
.pc(pc_to_imem_pc)
);
wire [31:0] imem_to_reg_pc;
wire [31:0] imem_to_reg_ir;
IMemModule u_IMemModule(
.clk(clk),
.rst_n(rst_n),
.addr(pc_to_imem_pc),
.pc(imem_to_reg_pc),
.ir(imem_to_reg_ir)
);
wire ir_stall;
assign ir_stall = 0;
wire ir_bubble;
wire [31:0] reg_to_alu_pc;
wire [31:0] reg_to_alu_ir;
wire [4:0] reg_to_alu_regaddr1;
wire [4:0] reg_to_alu_regaddr2;
wire [4:0] reg_to_alu_regaddr3;
wire [31:0] reg_to_alu_alu_a;
wire [31:0] reg_to_alu_alu_b;
wire [31:0] reg_to_alu_swdata;
wire [4:0] reg_to_alu_op;
wire [5:0] reg_to_alu_optype;
IR_reg u_IR_reg(
.clk(clk),
.rst_n(rst_n),
.pc(imem_to_reg_pc),
.ir(imem_to_reg_ir),
.is_int( buttonpress ),
.ir_stall(ir_stall),
.ir_bubble(ir_bubble),
.preg_we(wb_to_reg_reg_we),
.pregaddr3(wb_to_reg_regaddr3),
.pregvalue3(wb_to_reg_delay_regdata),
.next_pc(reg_to_alu_pc),
.next_ir(reg_to_alu_ir),
.regaddr1(reg_to_alu_regaddr1),
.regaddr2(reg_to_alu_regaddr2),
.regaddr3(reg_to_alu_regaddr3),
.alu_a(reg_to_alu_alu_a),
.alu_b(reg_to_alu_alu_b),
.swdata(reg_to_alu_swdata),
.op(reg_to_alu_op),
.optype(reg_to_alu_optype),
.RTI(imem_to_int_RTI),
.syscall(ir_to_int_syscall)
);
wire alu_stall;
assign alu_stall=0;
wire alu_bubble;
assign alu_bubble=0;
wire [31:0] walu_out;
wire wflag;
wire [4:0] alu_to_dmem_regaddr3;
wire [31:0] alu_to_dmem_alu_out;
wire alu_to_branch_flag;
wire [31:0] alu_to_dmem_swdata;
wire [31:0] alu_to_dmem_pc;
wire [31:0] alu_to_dmem_ir;
wire [5:0] alu_to_dmem_optype;
wire [4:0] alu_to_alu_bwregaddr;
wire [31:0] alu_to_alu_bwdata;
wire [4:0] bw_to_alu_bwregaddr;
wire [31:0] bw_to_alu_bwdata;
assign alu_to_alu_bwregaddr = alu_to_dmem_regaddr3;
assign alu_to_alu_bwdata = alu_to_dmem_alu_out;
assign bw_to_alu_bwregaddr = wb_to_reg_regaddr3;
assign bw_to_alu_bwdata = wb_to_reg_regdata;
wire alu_to_alu_valid;
wire dmem_to_alu_valid;
ALUmodule u_ALUmodule(
.clk(clk),
.rst_n(rst_n),
.alu_stall(alu_stall),
.alu_bubble(alu_bubble),
.pc(reg_to_alu_pc),
.ir(reg_to_alu_ir),
.regaddr1(reg_to_alu_regaddr1),
.regaddr2(reg_to_alu_regaddr2),
.regaddr3(reg_to_alu_regaddr3),
.alu_a(reg_to_alu_alu_a),
.alu_b(reg_to_alu_alu_b),
.op(reg_to_alu_op),
.optype(reg_to_alu_optype),
.swdata(reg_to_alu_swdata),
.a_valid(alu_to_alu_valid),
.a_bwregaddr(alu_to_alu_bwregaddr),
.a_bw_data(alu_to_alu_bwdata),
.b_valid(dmem_to_alu_valid),
.b_bwregaddr(dmem_to_wb_regaddr3),
.b_bw_data(bw_to_alu_bwdata),
.walu_out(walu_out),
.wflag(wflag),
.to_regaddr3(alu_to_dmem_regaddr3),
.alu_out(alu_to_dmem_alu_out),
.flag(alu_to_branch_flag),
.to_swdata(alu_to_dmem_swdata),
.to_valid(alu_to_alu_valid),
.to_pc(alu_to_dmem_pc),
.to_ir(alu_to_dmem_ir),
.to_optype(alu_to_dmem_optype)
);
wire dmem_stall;
wire dmem_bubble;
wire [5:0] dmem_to_wb_optype;
wire [31:0] dmem_to_wb_outdata;
assign dmem_stall = 0;
assign dmem_bubble = 0;
DMemModule u_DMemModule(
.clk(clk),
.rst_n(rst_n),
.dmem_stall(dmem_stall),
.dmem_bubble(dmem_bubble),
.pc(alu_to_dmem_pc),
.ir(alu_to_dmem_ir),
.regaddr3(alu_to_dmem_regaddr3),
.alu_ans(alu_to_dmem_alu_out),
.swdata(alu_to_dmem_swdata),
.optype(alu_to_dmem_optype),
.sw(sw),
.to_optype(dmem_to_wb_optype),
.to_regaddr3(dmem_to_wb_regaddr3),
.outdata(dmem_to_wb_outdata),
.smg(smgdata),
.led(led)
);
wire [31:0] wb_to_reg_regdata;
WriteBack u_WriteBack(
.clk(clk),
.rst_n(rst_n),
.ipvalid(alu_to_alu_valid),
.regaddr3(dmem_to_wb_regaddr3),
.regdata(dmem_to_wb_outdata),
.optype(dmem_to_wb_optype),
.to_valid(dmem_to_alu_valid),
.to_regaddr3(wb_to_reg_regaddr3),
.to_regdata(wb_to_reg_regdata),
.delay_regdata(wb_to_reg_delay_regdata),
.reg_we(wb_to_reg_reg_we)
);
branch u_branch(
.clk(clk),
.rst_n(rst_n),
.optype(reg_to_alu_optype),
.pc(reg_to_alu_pc),
.ir(reg_to_alu_ir),
.walu_out(walu_out),
.wflag(wflag),
.pcjump(pc_jump),
.real_pc(branch_to_pc_target),
.ir_bubble(ir_bubble)
);
endmodule | module top(
input clk,
input rst_n,
input [6:0] sw,
input buttonpress,
output [7:0] smg,
output [3:0] sel,
output [7:0] led
); |
wire button;
butt u_butt(
.clk(clk),
.rst_n(rst_n),
.buttonpress(buttonpress),
.button(button)
);
wire [31:0] smgdata;
interface u_interface(
.clk(clk),
.rst_n(rst_n),
.button(button),
.sw(sw),
.data(smgdata),
.smg(smg),
.sel(sel)
);
wire ir_to_int_syscall;
wire imem_to_int_RTI;
wire int_to_pc_start_int;
wire [31:0] int_to_pc_int_id;
wire int_to_pc_syscall;
wire int_to_pc_button;
wire [4:0] dmem_to_wb_regaddr3;
wire [4:0] wb_to_reg_regaddr3;
wire [31:0] wb_to_reg_delay_regdata;
wire wb_to_reg_reg_we;
interrupt u_interrupt(
.clk(clk),
.rst_n(rst_n),
.buttonint(button),
.syscall(ir_to_int_syscall),
.RTI(imem_to_int_RTI),
.to_syscall(int_to_pc_syscall),
.to_button(int_to_pc_button),
.start_int(int_to_pc_start_int),
.int_id(int_to_pc_int_id)
);
wire [31:0] branch_to_pc_target;
wire pc_stall;
wire pc_jump;
wire [31:0] pc_to_imem_pc;
pc u_pc(
.clk(clk),
.rst_n(rst_n),
.syscall(int_to_pc_syscall),
.button(int_to_pc_button),
.target(branch_to_pc_target),
.int_id(int_to_pc_int_id),
.start_int(int_to_pc_start_int),
.RTI(imem_to_int_RTI),
.pc_stall(pc_stall),
.pc_jump(pc_jump),
.pc(pc_to_imem_pc)
);
wire [31:0] imem_to_reg_pc;
wire [31:0] imem_to_reg_ir;
IMemModule u_IMemModule(
.clk(clk),
.rst_n(rst_n),
.addr(pc_to_imem_pc),
.pc(imem_to_reg_pc),
.ir(imem_to_reg_ir)
);
wire ir_stall;
assign ir_stall = 0;
wire ir_bubble;
wire [31:0] reg_to_alu_pc;
wire [31:0] reg_to_alu_ir;
wire [4:0] reg_to_alu_regaddr1;
wire [4:0] reg_to_alu_regaddr2;
wire [4:0] reg_to_alu_regaddr3;
wire [31:0] reg_to_alu_alu_a;
wire [31:0] reg_to_alu_alu_b;
wire [31:0] reg_to_alu_swdata;
wire [4:0] reg_to_alu_op;
wire [5:0] reg_to_alu_optype;
IR_reg u_IR_reg(
.clk(clk),
.rst_n(rst_n),
.pc(imem_to_reg_pc),
.ir(imem_to_reg_ir),
.is_int( buttonpress ),
.ir_stall(ir_stall),
.ir_bubble(ir_bubble),
.preg_we(wb_to_reg_reg_we),
.pregaddr3(wb_to_reg_regaddr3),
.pregvalue3(wb_to_reg_delay_regdata),
.next_pc(reg_to_alu_pc),
.next_ir(reg_to_alu_ir),
.regaddr1(reg_to_alu_regaddr1),
.regaddr2(reg_to_alu_regaddr2),
.regaddr3(reg_to_alu_regaddr3),
.alu_a(reg_to_alu_alu_a),
.alu_b(reg_to_alu_alu_b),
.swdata(reg_to_alu_swdata),
.op(reg_to_alu_op),
.optype(reg_to_alu_optype),
.RTI(imem_to_int_RTI),
.syscall(ir_to_int_syscall)
);
wire alu_stall;
assign alu_stall=0;
wire alu_bubble;
assign alu_bubble=0;
wire [31:0] walu_out;
wire wflag;
wire [4:0] alu_to_dmem_regaddr3;
wire [31:0] alu_to_dmem_alu_out;
wire alu_to_branch_flag;
wire [31:0] alu_to_dmem_swdata;
wire [31:0] alu_to_dmem_pc;
wire [31:0] alu_to_dmem_ir;
wire [5:0] alu_to_dmem_optype;
wire [4:0] alu_to_alu_bwregaddr;
wire [31:0] alu_to_alu_bwdata;
wire [4:0] bw_to_alu_bwregaddr;
wire [31:0] bw_to_alu_bwdata;
assign alu_to_alu_bwregaddr = alu_to_dmem_regaddr3;
assign alu_to_alu_bwdata = alu_to_dmem_alu_out;
assign bw_to_alu_bwregaddr = wb_to_reg_regaddr3;
assign bw_to_alu_bwdata = wb_to_reg_regdata;
wire alu_to_alu_valid;
wire dmem_to_alu_valid;
ALUmodule u_ALUmodule(
.clk(clk),
.rst_n(rst_n),
.alu_stall(alu_stall),
.alu_bubble(alu_bubble),
.pc(reg_to_alu_pc),
.ir(reg_to_alu_ir),
.regaddr1(reg_to_alu_regaddr1),
.regaddr2(reg_to_alu_regaddr2),
.regaddr3(reg_to_alu_regaddr3),
.alu_a(reg_to_alu_alu_a),
.alu_b(reg_to_alu_alu_b),
.op(reg_to_alu_op),
.optype(reg_to_alu_optype),
.swdata(reg_to_alu_swdata),
.a_valid(alu_to_alu_valid),
.a_bwregaddr(alu_to_alu_bwregaddr),
.a_bw_data(alu_to_alu_bwdata),
.b_valid(dmem_to_alu_valid),
.b_bwregaddr(dmem_to_wb_regaddr3),
.b_bw_data(bw_to_alu_bwdata),
.walu_out(walu_out),
.wflag(wflag),
.to_regaddr3(alu_to_dmem_regaddr3),
.alu_out(alu_to_dmem_alu_out),
.flag(alu_to_branch_flag),
.to_swdata(alu_to_dmem_swdata),
.to_valid(alu_to_alu_valid),
.to_pc(alu_to_dmem_pc),
.to_ir(alu_to_dmem_ir),
.to_optype(alu_to_dmem_optype)
);
wire dmem_stall;
wire dmem_bubble;
wire [5:0] dmem_to_wb_optype;
wire [31:0] dmem_to_wb_outdata;
assign dmem_stall = 0;
assign dmem_bubble = 0;
DMemModule u_DMemModule(
.clk(clk),
.rst_n(rst_n),
.dmem_stall(dmem_stall),
.dmem_bubble(dmem_bubble),
.pc(alu_to_dmem_pc),
.ir(alu_to_dmem_ir),
.regaddr3(alu_to_dmem_regaddr3),
.alu_ans(alu_to_dmem_alu_out),
.swdata(alu_to_dmem_swdata),
.optype(alu_to_dmem_optype),
.sw(sw),
.to_optype(dmem_to_wb_optype),
.to_regaddr3(dmem_to_wb_regaddr3),
.outdata(dmem_to_wb_outdata),
.smg(smgdata),
.led(led)
);
wire [31:0] wb_to_reg_regdata;
WriteBack u_WriteBack(
.clk(clk),
.rst_n(rst_n),
.ipvalid(alu_to_alu_valid),
.regaddr3(dmem_to_wb_regaddr3),
.regdata(dmem_to_wb_outdata),
.optype(dmem_to_wb_optype),
.to_valid(dmem_to_alu_valid),
.to_regaddr3(wb_to_reg_regaddr3),
.to_regdata(wb_to_reg_regdata),
.delay_regdata(wb_to_reg_delay_regdata),
.reg_we(wb_to_reg_reg_we)
);
branch u_branch(
.clk(clk),
.rst_n(rst_n),
.optype(reg_to_alu_optype),
.pc(reg_to_alu_pc),
.ir(reg_to_alu_ir),
.walu_out(walu_out),
.wflag(wflag),
.pcjump(pc_jump),
.real_pc(branch_to_pc_target),
.ir_bubble(ir_bubble)
);
endmodule | 0 |
6,188 | data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/WriteBack.v | 115,487,336 | WriteBack.v | v | 82 | 85 | [] | [] | [] | [(21, 81)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/WriteBack.v:45: Signal definition not found, creating implicitly: \'local_reg_we\'\nassign local_reg_we = ( optype==6\'h0 || optype==6\'h1 || optype==6\'h2 || optype==6\'h4\n ^~~~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 6,957 | module | module WriteBack(
input clk,
input rst_n,
input ipvalid,
input [4:0] regaddr3,
input [31:0] regdata,
input [5:0] optype,
output reg to_valid,
output reg [4:0] to_regaddr3,
output [31:0] to_regdata,
output reg [31:0] delay_regdata,
output reg reg_we
);
assign to_regdata=regdata;
assign local_reg_we = ( optype==6'h0 || optype==6'h1 || optype==6'h2 || optype==6'h4
|| optype==6'h5 || optype==6'h6 || optype==6'h13) ? 1 : 0;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
delay_regdata<=32'hCCCC_CCCC;
else
delay_regdata<=regdata;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
to_valid<=0;
else
to_valid<=ipvalid;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
reg_we<=0;
else
reg_we<=local_reg_we;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
to_regaddr3<=5'h0;
else
to_regaddr3<=regaddr3;
end
endmodule | module WriteBack(
input clk,
input rst_n,
input ipvalid,
input [4:0] regaddr3,
input [31:0] regdata,
input [5:0] optype,
output reg to_valid,
output reg [4:0] to_regaddr3,
output [31:0] to_regdata,
output reg [31:0] delay_regdata,
output reg reg_we
); |
assign to_regdata=regdata;
assign local_reg_we = ( optype==6'h0 || optype==6'h1 || optype==6'h2 || optype==6'h4
|| optype==6'h5 || optype==6'h6 || optype==6'h13) ? 1 : 0;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
delay_regdata<=32'hCCCC_CCCC;
else
delay_regdata<=regdata;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
to_valid<=0;
else
to_valid<=ipvalid;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
reg_we<=0;
else
reg_we<=local_reg_we;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
to_regaddr3<=5'h0;
else
to_regaddr3<=regaddr3;
end
endmodule | 0 |
6,189 | data/full_repos/permissive/115487336/mycode/Whac-A-Mole/button.v | 115,487,336 | button.v | v | 72 | 83 | [] | [] | [] | [(21, 71)] | null | data/verilator_xmls/5fe0e31a-1736-4693-9b9c-fadf813a7387.xml | null | 6,960 | module | module button(
input clk,
input rst_n,
input button,
output reg buttonpress
);
reg [19:0] count;
reg en;
reg update;
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
begin
count <= 20'h0;
en<=1'b0;
update <= 1'b0;
buttonpress <= 1'b0;
end
else
begin
buttonpress <= 1'b0;
if(button)
begin
if(count == 20'd9_99999)
begin
en <= 1'b1;
end
else
begin
count <= count + 20'h1;
en <= 1'b0;
end
end
else
begin
count <= 20'h0;
en <= 1'b0;
update <= 1'b0;
end
if(en && !update)
begin
buttonpress <= 1'b1;
update <= 1'b1;
end
end
end
endmodule | module button(
input clk,
input rst_n,
input button,
output reg buttonpress
); |
reg [19:0] count;
reg en;
reg update;
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
begin
count <= 20'h0;
en<=1'b0;
update <= 1'b0;
buttonpress <= 1'b0;
end
else
begin
buttonpress <= 1'b0;
if(button)
begin
if(count == 20'd9_99999)
begin
en <= 1'b1;
end
else
begin
count <= count + 20'h1;
en <= 1'b0;
end
end
else
begin
count <= 20'h0;
en <= 1'b0;
update <= 1'b0;
end
if(en && !update)
begin
buttonpress <= 1'b1;
update <= 1'b1;
end
end
end
endmodule | 0 |
6,190 | data/full_repos/permissive/115487336/mycode/Whac-A-Mole/code.v | 115,487,336 | code.v | v | 117 | 83 | [] | [] | [] | [(21, 116)] | null | data/verilator_xmls/440c5014-c046-4b0b-9b89-0f2ef264f282.xml | null | 6,961 | module | module code(
input clk,
input rst_n,
input [15:0] data,
output reg [7:0] smg,
output [3:0] sel
);
reg [3:0] isel;
reg [19:0] selcount;
reg selen;
reg [1:0] temp;
reg [3:0] num;
assign sel = isel;
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
begin
selcount <= 20'd0;
selen <= 0;
end
else if(selcount == 20'd99_999)
begin
selcount <= 20'd0;
selen <= 1;
end
else
begin
selcount <= selcount + 20'h1;
selen <= 0;
end
end
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
begin
isel <= 4'b1111;
smg <= 8'b1111_1111;
temp <= 2'b00;
end
else
begin
if(selen)
begin
case(temp)
2'h0:
begin
isel<=4'b1110;
num<=data[3:0];
end
2'h1:
begin
isel<=4'b1101;
num<=data[7:4];
end
2'h2:
begin
isel<=4'b1011;
num<=data[11:8];
end
2'h3:
begin
isel<=4'b0111;
num<=data[15:12];
end
default:
begin
isel<=4'b1111;
num<=4'hF;
end
endcase
temp <= temp+1;
end
case(num)
4'h0: smg = 8'b0000_0011;
4'h1: smg = 8'b1001_1111;
4'h2: smg = 8'b0010_0101;
4'h3: smg = 8'b0000_1101;
4'h4: smg = 8'b1001_1001;
4'h5: smg = 8'b0100_1001;
4'h6: smg = 8'b0100_0001;
4'h7: smg = 8'b0001_1111;
4'h8: smg = 8'b0000_0001;
4'h9: smg = 8'b0000_1001;
4'hA: smg = 8'b0011_1001;
default: smg = 8'b1111_1111;
endcase
end
end
endmodule | module code(
input clk,
input rst_n,
input [15:0] data,
output reg [7:0] smg,
output [3:0] sel
); |
reg [3:0] isel;
reg [19:0] selcount;
reg selen;
reg [1:0] temp;
reg [3:0] num;
assign sel = isel;
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
begin
selcount <= 20'd0;
selen <= 0;
end
else if(selcount == 20'd99_999)
begin
selcount <= 20'd0;
selen <= 1;
end
else
begin
selcount <= selcount + 20'h1;
selen <= 0;
end
end
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
begin
isel <= 4'b1111;
smg <= 8'b1111_1111;
temp <= 2'b00;
end
else
begin
if(selen)
begin
case(temp)
2'h0:
begin
isel<=4'b1110;
num<=data[3:0];
end
2'h1:
begin
isel<=4'b1101;
num<=data[7:4];
end
2'h2:
begin
isel<=4'b1011;
num<=data[11:8];
end
2'h3:
begin
isel<=4'b0111;
num<=data[15:12];
end
default:
begin
isel<=4'b1111;
num<=4'hF;
end
endcase
temp <= temp+1;
end
case(num)
4'h0: smg = 8'b0000_0011;
4'h1: smg = 8'b1001_1111;
4'h2: smg = 8'b0010_0101;
4'h3: smg = 8'b0000_1101;
4'h4: smg = 8'b1001_1001;
4'h5: smg = 8'b0100_1001;
4'h6: smg = 8'b0100_0001;
4'h7: smg = 8'b0001_1111;
4'h8: smg = 8'b0000_0001;
4'h9: smg = 8'b0000_1001;
4'hA: smg = 8'b0011_1001;
default: smg = 8'b1111_1111;
endcase
end
end
endmodule | 0 |
6,191 | data/full_repos/permissive/115487336/mycode/Whac-A-Mole/delay.v | 115,487,336 | delay.v | v | 62 | 83 | [] | [] | [] | [(21, 61)] | null | data/verilator_xmls/6dcd7cb6-b52c-4355-8f4f-d04bdde14604.xml | null | 6,962 | module | module delay(
input clk,
input rst_n,
input [4:0] state,
output reg [15:0] data,
output delayover
);
reg [31:0] delaycount;
reg idelayover;
assign delayover=idelayover;
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
begin
delaycount <= 32'b0;
idelayover <= 0;
data <= 16'hFFFF;
end
else
begin
if(delaycount == 32'd0)
data <= 16'h3FFF;
else if(delaycount == 32'd1_0000_0000)
data <= 16'h2FFF;
else if(delaycount == 32'd2_0000_0000)
data <= 16'h1FFF;
else if(delaycount == 32'd3_0000_0000)
data <= 16'h9AFF;
else if(delaycount == 32'd4_0000_0000)
idelayover <= 1;
else
begin
end
if(~idelayover)
delaycount <= delaycount + 32'h1;
end
end
endmodule | module delay(
input clk,
input rst_n,
input [4:0] state,
output reg [15:0] data,
output delayover
); |
reg [31:0] delaycount;
reg idelayover;
assign delayover=idelayover;
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
begin
delaycount <= 32'b0;
idelayover <= 0;
data <= 16'hFFFF;
end
else
begin
if(delaycount == 32'd0)
data <= 16'h3FFF;
else if(delaycount == 32'd1_0000_0000)
data <= 16'h2FFF;
else if(delaycount == 32'd2_0000_0000)
data <= 16'h1FFF;
else if(delaycount == 32'd3_0000_0000)
data <= 16'h9AFF;
else if(delaycount == 32'd4_0000_0000)
idelayover <= 1;
else
begin
end
if(~idelayover)
delaycount <= delaycount + 32'h1;
end
end
endmodule | 0 |
6,192 | data/full_repos/permissive/115487336/mycode/Whac-A-Mole/hex_8421BCD.v | 115,487,336 | hex_8421BCD.v | v | 83 | 83 | [] | [] | [] | [(21, 82)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/hex_8421BCD.v:55: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'hex_\' generates 4 bits.\n : ... In instance hex_8421BCD\nassign ystemp = hex_ + linshi;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/hex_8421BCD.v:55: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'linshi\' generates 4 bits.\n : ... In instance hex_8421BCD\nassign ystemp = hex_ + linshi;\n ^\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/hex_8421BCD.v:61: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'hex_\' generates 4 bits.\n : ... In instance hex_8421BCD\nassign yunsuantemp = hex_ + linshi - 8\'d10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/hex_8421BCD.v:61: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'linshi\' generates 4 bits.\n : ... In instance hex_8421BCD\nassign yunsuantemp = hex_ + linshi - 8\'d10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/hex_8421BCD.v:79: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'jw1\' generates 1 bits.\n : ... In instance hex_8421BCD\n) + jw1 + jw2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/hex_8421BCD.v:79: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'jw2\' generates 1 bits.\n : ... In instance hex_8421BCD\n) + jw1 + jw2;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 6,963 | module | module hex_8421BCD(
input [7:0] hex,
output [7:0] BCD
);
wire [3:0] gw;
wire [3:0] bw;
wire [3:0] linshi;
wire jw1;
wire jw2;
wire [3:0] hex_;
wire [3:0] _hex;
assign linshi = (
hex[7:4] == 4'h1 ? 4'd6 :(
hex[7:4] == 4'h2 ? 4'd2 : (
hex[7:4] == 4'h3 ? 4'd8 : (
hex[7:4] == 4'h4 ? 4'd4 : (
hex[7:4] == 4'h5 ? 4'd0 : (
hex[7:4] == 4'h6 ? 4'd6 : 4'd0
)
)
)
)
)
);
assign jw1 = hex[3:0] > 4'd9 ? 1 : 0;
assign hex_ = (jw1 == 1 ? hex[3:0] - 4'd10 : hex[3:0]);
wire [7:0] ystemp;
assign ystemp = hex_ + linshi;
assign jw2 = ystemp > 8'd9 ? 1 : 0;
wire [7:0] yunsuantemp;
assign yunsuantemp = hex_ + linshi - 8'd10;
assign BCD[3:0] = (jw2 == 1 ? yunsuantemp[3:0] : hex_ + linshi);
assign _hex = (
hex[7:4] == 4'h0 ? 4'd0 : (
hex[7:4] == 4'h1 ? 4'd1 : (
hex[7:4] == 4'h2 ? 4'd3 : (
hex[7:4] == 4'h3 ? 4'd4: (
hex[7:4] == 4'h4 ? 4'd6 : (
hex[7:4] == 4'h5 ? 4'd8 : (
hex[7:4] == 4'h6 ? 4'd9 : 4'd0
)
)
)
)
)
)
) + jw1 + jw2;
assign BCD[7:4] = _hex;
endmodule | module hex_8421BCD(
input [7:0] hex,
output [7:0] BCD
); |
wire [3:0] gw;
wire [3:0] bw;
wire [3:0] linshi;
wire jw1;
wire jw2;
wire [3:0] hex_;
wire [3:0] _hex;
assign linshi = (
hex[7:4] == 4'h1 ? 4'd6 :(
hex[7:4] == 4'h2 ? 4'd2 : (
hex[7:4] == 4'h3 ? 4'd8 : (
hex[7:4] == 4'h4 ? 4'd4 : (
hex[7:4] == 4'h5 ? 4'd0 : (
hex[7:4] == 4'h6 ? 4'd6 : 4'd0
)
)
)
)
)
);
assign jw1 = hex[3:0] > 4'd9 ? 1 : 0;
assign hex_ = (jw1 == 1 ? hex[3:0] - 4'd10 : hex[3:0]);
wire [7:0] ystemp;
assign ystemp = hex_ + linshi;
assign jw2 = ystemp > 8'd9 ? 1 : 0;
wire [7:0] yunsuantemp;
assign yunsuantemp = hex_ + linshi - 8'd10;
assign BCD[3:0] = (jw2 == 1 ? yunsuantemp[3:0] : hex_ + linshi);
assign _hex = (
hex[7:4] == 4'h0 ? 4'd0 : (
hex[7:4] == 4'h1 ? 4'd1 : (
hex[7:4] == 4'h2 ? 4'd3 : (
hex[7:4] == 4'h3 ? 4'd4: (
hex[7:4] == 4'h4 ? 4'd6 : (
hex[7:4] == 4'h5 ? 4'd8 : (
hex[7:4] == 4'h6 ? 4'd9 : 4'd0
)
)
)
)
)
)
) + jw1 + jw2;
assign BCD[7:4] = _hex;
endmodule | 0 |
6,193 | data/full_repos/permissive/115487336/mycode/Whac-A-Mole/logic.v | 115,487,336 | logic.v | v | 196 | 83 | [] | [] | [] | [(21, 195)] | null | null | 1: b"%Error: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/logic.v:41: syntax error, unexpected rand, expecting IDENTIFIER or do or final\nwire [2:0] rand;\n ^~~~\n%Error: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/logic.v:46: syntax error, unexpected rand, expecting TYPE-IDENTIFIER\nassign rand = a[2:0];\n ^~~~\n%Error: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/logic.v:53: Too many digits for 16 bit number: 16'h7FFFF\n a <= (a*_A+_B)>>16 & 16'h7FFFF;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/logic.v:74: syntax error, unexpected rand, expecting TYPE-IDENTIFIER\n target_sw[ rand ] <= !target_sw[ rand ];\n ^~~~\n%Error: Exiting due to 4 error(s)\n" | 6,964 | module | module gamelogic(
input clk,
input rst_n,
input [4:0] state,
input [7:0] sw,
output reg scorezero,
output [8:0] score,
output [7:0] led
);
reg [7:0] target_sw;
reg [7:0] iscore;
assign score = iscore;
assign led = target_sw;
reg [31:0] a;
wire [2:0] rand;
wire [31:0] _A;
wire [31:0] _B;
assign _A = 32'd214013;
assign _B = 32'd2531011;
assign rand = a[2:0];
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
a <= sw;
else
a <= (a*_A+_B)>>16 & 16'h7FFFF;
end
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
begin
target_sw <= sw;
dishu_en <= 1;
scorecount_en <= 0;
end
else
begin
if(state == 5'd1)
begin
target_sw <= sw;
end
if(next_dishu && state == 5'd3)
begin
target_sw[ rand ] <= !target_sw[ rand ];
dishu_en <= 0;
scorecount_en <= 1;
end
else if(next && state == 5'd3)
begin
dishu_en <= 1;
scorecount_en <= 0;
end
end
end
reg dishu_en;
reg [31:0] rdcount;
reg next_dishu;
always@(posedge clk or posedge rst_n)
begin
if(rst_n || !dishu_en)
begin
rdcount <= 32'b0;
next_dishu <= 0;
end
else
begin
if(rdcount == 32'd3999_9999)
begin
rdcount <= 32'b0;
next_dishu <= 1;
end
else
begin
rdcount <= rdcount + 32'd1;
next_dishu <= 0;
end
end
end
reg scorecount_en;
reg [63:0] scorecount;
reg next;
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
begin
scorecount <= 64'b0;
iscore <= 8'd50;
next <= 0;
scorezero <= 0;
end
else if(!scorecount_en)
begin
scorecount <= 64'b0;
next <= 0;
end
else if(state == 5'd3)
begin
if(sw == target_sw)
begin
if(scorecount < 64'd1500_0000)
iscore <= (iscore > 8'd96 ? 8'd99 : iscore + 8'd2);
else if(scorecount < 64'd5000_0000)
iscore <= (iscore > 8'd97 ? 8'd99 : iscore + 8'd1);
else if(scorecount < 64'd15000_0000)
begin
if(iscore < 8'd3)
begin
iscore <= 0;
scorezero <= 1;
end
else
iscore <= iscore - 8'd3;
end
else if(scorecount < 64'd19000_0000)
begin
if(iscore < 8'd5)
begin
iscore <= 0;
scorezero <= 1;
end
else
iscore <= iscore - 8'd5;
end
else
begin
end
next <= 1;
scorecount <= 64'b0;
end
else
begin
if(scorecount > 64'd19000_0000)
begin
if(iscore < 8'd4)
begin
iscore <= 0;
scorezero <= 1;
end
else
begin
scorecount <= 64'd14000_0000;
iscore <= iscore - 8'd3;
end
end
else
begin
scorecount <= scorecount + 64'b1;
end
next <= 0;
end
end
else
begin
end
end
endmodule | module gamelogic(
input clk,
input rst_n,
input [4:0] state,
input [7:0] sw,
output reg scorezero,
output [8:0] score,
output [7:0] led
); |
reg [7:0] target_sw;
reg [7:0] iscore;
assign score = iscore;
assign led = target_sw;
reg [31:0] a;
wire [2:0] rand;
wire [31:0] _A;
wire [31:0] _B;
assign _A = 32'd214013;
assign _B = 32'd2531011;
assign rand = a[2:0];
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
a <= sw;
else
a <= (a*_A+_B)>>16 & 16'h7FFFF;
end
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
begin
target_sw <= sw;
dishu_en <= 1;
scorecount_en <= 0;
end
else
begin
if(state == 5'd1)
begin
target_sw <= sw;
end
if(next_dishu && state == 5'd3)
begin
target_sw[ rand ] <= !target_sw[ rand ];
dishu_en <= 0;
scorecount_en <= 1;
end
else if(next && state == 5'd3)
begin
dishu_en <= 1;
scorecount_en <= 0;
end
end
end
reg dishu_en;
reg [31:0] rdcount;
reg next_dishu;
always@(posedge clk or posedge rst_n)
begin
if(rst_n || !dishu_en)
begin
rdcount <= 32'b0;
next_dishu <= 0;
end
else
begin
if(rdcount == 32'd3999_9999)
begin
rdcount <= 32'b0;
next_dishu <= 1;
end
else
begin
rdcount <= rdcount + 32'd1;
next_dishu <= 0;
end
end
end
reg scorecount_en;
reg [63:0] scorecount;
reg next;
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
begin
scorecount <= 64'b0;
iscore <= 8'd50;
next <= 0;
scorezero <= 0;
end
else if(!scorecount_en)
begin
scorecount <= 64'b0;
next <= 0;
end
else if(state == 5'd3)
begin
if(sw == target_sw)
begin
if(scorecount < 64'd1500_0000)
iscore <= (iscore > 8'd96 ? 8'd99 : iscore + 8'd2);
else if(scorecount < 64'd5000_0000)
iscore <= (iscore > 8'd97 ? 8'd99 : iscore + 8'd1);
else if(scorecount < 64'd15000_0000)
begin
if(iscore < 8'd3)
begin
iscore <= 0;
scorezero <= 1;
end
else
iscore <= iscore - 8'd3;
end
else if(scorecount < 64'd19000_0000)
begin
if(iscore < 8'd5)
begin
iscore <= 0;
scorezero <= 1;
end
else
iscore <= iscore - 8'd5;
end
else
begin
end
next <= 1;
scorecount <= 64'b0;
end
else
begin
if(scorecount > 64'd19000_0000)
begin
if(iscore < 8'd4)
begin
iscore <= 0;
scorezero <= 1;
end
else
begin
scorecount <= 64'd14000_0000;
iscore <= iscore - 8'd3;
end
end
else
begin
scorecount <= scorecount + 64'b1;
end
next <= 0;
end
end
else
begin
end
end
endmodule | 0 |
6,194 | data/full_repos/permissive/115487336/mycode/Whac-A-Mole/muxer.v | 115,487,336 | muxer.v | v | 44 | 83 | [] | [] | [] | [(21, 43)] | null | data/verilator_xmls/55a7eec7-ee4e-41c6-9cf2-6a55777d2618.xml | null | 6,965 | module | module muxer(
input [4:0] state,
input [15:0] delay,
input [7:0] resttime,
input [7:0] score,
input timeover,
input scorezero,
output [15:0] data
);
wire [15:0] temp;
wire [15:0] halt;
assign temp[15:8] = scorezero == 1 ? 8'b0 : score[7:0];
assign temp[7:0] = timeover == 1 ? 8'b0 : resttime;
assign data = (state==5'd2 ? delay: temp );
endmodule | module muxer(
input [4:0] state,
input [15:0] delay,
input [7:0] resttime,
input [7:0] score,
input timeover,
input scorezero,
output [15:0] data
); |
wire [15:0] temp;
wire [15:0] halt;
assign temp[15:8] = scorezero == 1 ? 8'b0 : score[7:0];
assign temp[7:0] = timeover == 1 ? 8'b0 : resttime;
assign data = (state==5'd2 ? delay: temp );
endmodule | 0 |
6,195 | data/full_repos/permissive/115487336/mycode/Whac-A-Mole/state.v | 115,487,336 | state.v | v | 81 | 83 | [] | [] | [] | [(21, 80)] | null | data/verilator_xmls/e1766e4d-4ea6-4b3c-b3c4-008801510262.xml | null | 6,966 | module | module state(
input clk,
input rst_n,
input buttonpress,
input delayover,
input timeover,
input scorezero,
output [4:0] state
);
reg [4:0] curr_state;
reg [4:0] next_state;
assign state = curr_state;
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
curr_state <= 5'b0;
else
curr_state <= next_state;
end
always@(*)
begin
if(curr_state == 5'd0)
next_state = 5'd1;
else if(curr_state == 5'd1)
begin
if(buttonpress)
next_state=5'd2;
else
next_state=5'd1;
end
else if(curr_state == 5'd2)
begin
if(delayover)
next_state=5'd3;
else
next_state=5'd2;
end
else if(curr_state == 5'd3)
begin
if(timeover||scorezero)
next_state=5'd4;
else
next_state=5'd3;
end
else
next_state=5'd4;
end
endmodule | module state(
input clk,
input rst_n,
input buttonpress,
input delayover,
input timeover,
input scorezero,
output [4:0] state
); |
reg [4:0] curr_state;
reg [4:0] next_state;
assign state = curr_state;
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
curr_state <= 5'b0;
else
curr_state <= next_state;
end
always@(*)
begin
if(curr_state == 5'd0)
next_state = 5'd1;
else if(curr_state == 5'd1)
begin
if(buttonpress)
next_state=5'd2;
else
next_state=5'd1;
end
else if(curr_state == 5'd2)
begin
if(delayover)
next_state=5'd3;
else
next_state=5'd2;
end
else if(curr_state == 5'd3)
begin
if(timeover||scorezero)
next_state=5'd4;
else
next_state=5'd3;
end
else
next_state=5'd4;
end
endmodule | 0 |
6,196 | data/full_repos/permissive/115487336/mycode/Whac-A-Mole/timer.v | 115,487,336 | timer.v | v | 91 | 83 | [] | [] | [] | [(21, 90)] | null | data/verilator_xmls/5b52991d-6776-4167-b480-9a6e56902dde.xml | null | 6,967 | module | module timer(
input clk,
input rst_n,
input [7:0] sw,
input [4:0] state,
output timeover,
output [7:0] resttime
);
reg [7:0] iresttime;
assign resttime=iresttime;
assign timeover = iresttime == 8'b0 ? 1 : 0;
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
iresttime <= 8'b0;
else
begin
if(state == 5'd1)
iresttime <= sw;
else if(state == 5'd3 && decen)
begin
if(iresttime[3:0] == 4'b0)
begin
if(iresttime[7:4]==4'b0)
begin
end
else
begin
iresttime[7:4] <= iresttime[7:4] - 4'd1;
iresttime[3:0] <= 4'd9;
end
end
else
iresttime[3:0] <= iresttime[3:0] - 4'd1;
end
else
begin
end
end
end
reg [31:0] deccount;
reg decen;
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
begin
deccount <= 32'b0;
decen <= 0;
end
else
begin
if(deccount == 32'd9999_9999)
begin
decen <= 1;
deccount <= 32'b0;
end
else
begin
deccount <= deccount + 32'b1;
decen <= 0;
end
end
end
endmodule | module timer(
input clk,
input rst_n,
input [7:0] sw,
input [4:0] state,
output timeover,
output [7:0] resttime
); |
reg [7:0] iresttime;
assign resttime=iresttime;
assign timeover = iresttime == 8'b0 ? 1 : 0;
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
iresttime <= 8'b0;
else
begin
if(state == 5'd1)
iresttime <= sw;
else if(state == 5'd3 && decen)
begin
if(iresttime[3:0] == 4'b0)
begin
if(iresttime[7:4]==4'b0)
begin
end
else
begin
iresttime[7:4] <= iresttime[7:4] - 4'd1;
iresttime[3:0] <= 4'd9;
end
end
else
iresttime[3:0] <= iresttime[3:0] - 4'd1;
end
else
begin
end
end
end
reg [31:0] deccount;
reg decen;
always@(posedge clk or posedge rst_n)
begin
if(rst_n)
begin
deccount <= 32'b0;
decen <= 0;
end
else
begin
if(deccount == 32'd9999_9999)
begin
decen <= 1;
deccount <= 32'b0;
end
else
begin
deccount <= deccount + 32'b1;
decen <= 0;
end
end
end
endmodule | 0 |
6,197 | data/full_repos/permissive/115487336/mycode/Whac-A-Mole/top.v | 115,487,336 | top.v | v | 119 | 83 | [] | [] | [] | [(21, 118)] | null | null | 1: b"%Error: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/top.v:50: Cannot find file containing module: 'button'\nbutton u_button(\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/115487336/mycode/Whac-A-Mole,data/full_repos/permissive/115487336/button\n data/full_repos/permissive/115487336/mycode/Whac-A-Mole,data/full_repos/permissive/115487336/button.v\n data/full_repos/permissive/115487336/mycode/Whac-A-Mole,data/full_repos/permissive/115487336/button.sv\n button\n button.v\n button.sv\n obj_dir/button\n obj_dir/button.v\n obj_dir/button.sv\n%Error: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/top.v:57: Cannot find file containing module: 'state'\nstate u_state(\n^~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/top.v:67: Cannot find file containing module: 'gamelogic'\ngamelogic u_gamelogic(\n^~~~~~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/top.v:77: Cannot find file containing module: 'delay'\ndelay u_delay(\n^~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/top.v:85: Cannot find file containing module: 'timer'\ntimer u_timer(\n^~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/top.v:94: Cannot find file containing module: 'hex_8421BCD'\nhex_8421BCD u_hex_8421BCD(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/top.v:100: Cannot find file containing module: 'muxer'\nmuxer u_muxer(\n^~~~~\n%Error: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/top.v:110: Cannot find file containing module: 'code'\ncode u_code(\n^~~~\n%Error: Exiting due to 8 error(s)\n" | 6,968 | module | module top(
input clk,
input rst_n,
input [7:0] sw,
input buttonset,
output [7:0] led,
output [7:0] smg,
output [3:0] sel
);
wire buttonpress;
wire [15:0] data;
wire [4:0] state;
wire [15:0] delay;
wire delayover;
wire [7:0] resttime;
wire [7:0] score;
wire [7:0] scoreBCD;
wire timeover;
wire scorezero;
button u_button(
.clk(clk),
.rst_n(rst_n),
.button(buttonset),
.buttonpress(buttonpress)
);
state u_state(
.clk(clk),
.rst_n(rst_n),
.buttonpress(buttonpress),
.delayover(delayover),
.timeover(timeover),
.scorezero(scorezero),
.state(state)
);
gamelogic u_gamelogic(
.clk(clk),
.rst_n(rst_n),
.state(state),
.sw(sw),
.score(score),
.scorezero(scorezero),
.led(led)
);
delay u_delay(
.clk(clk),
.rst_n(rst_n),
.state(state),
.data(delay),
.delayover(delayover)
);
timer u_timer(
.clk(clk),
.rst_n(rst_n),
.sw(sw),
.state(state),
.timeover(timeover),
.resttime(resttime)
);
hex_8421BCD u_hex_8421BCD(
.hex(score),
.BCD(scoreBCD)
);
muxer u_muxer(
.state(state),
.delay(delay),
.resttime(resttime),
.score(scoreBCD),
.timeover(timeover),
.scorezero(scorezero),
.data(data)
);
code u_code(
.clk(clk),
.rst_n(rst_n),
.data(data),
.smg(smg),
.sel(sel)
);
endmodule | module top(
input clk,
input rst_n,
input [7:0] sw,
input buttonset,
output [7:0] led,
output [7:0] smg,
output [3:0] sel
); |
wire buttonpress;
wire [15:0] data;
wire [4:0] state;
wire [15:0] delay;
wire delayover;
wire [7:0] resttime;
wire [7:0] score;
wire [7:0] scoreBCD;
wire timeover;
wire scorezero;
button u_button(
.clk(clk),
.rst_n(rst_n),
.button(buttonset),
.buttonpress(buttonpress)
);
state u_state(
.clk(clk),
.rst_n(rst_n),
.buttonpress(buttonpress),
.delayover(delayover),
.timeover(timeover),
.scorezero(scorezero),
.state(state)
);
gamelogic u_gamelogic(
.clk(clk),
.rst_n(rst_n),
.state(state),
.sw(sw),
.score(score),
.scorezero(scorezero),
.led(led)
);
delay u_delay(
.clk(clk),
.rst_n(rst_n),
.state(state),
.data(delay),
.delayover(delayover)
);
timer u_timer(
.clk(clk),
.rst_n(rst_n),
.sw(sw),
.state(state),
.timeover(timeover),
.resttime(resttime)
);
hex_8421BCD u_hex_8421BCD(
.hex(score),
.BCD(scoreBCD)
);
muxer u_muxer(
.state(state),
.delay(delay),
.resttime(resttime),
.score(scoreBCD),
.timeover(timeover),
.scorezero(scorezero),
.data(data)
);
code u_code(
.clk(clk),
.rst_n(rst_n),
.data(data),
.smg(smg),
.sel(sel)
);
endmodule | 0 |
6,198 | data/full_repos/permissive/115632823/code/Stream Multi-processor/SM.srcs/sim_1/new/test.v | 115,632,823 | test.v | v | 33 | 55 | [] | [] | [] | [(3, 18)] | null | null | 1: b'%Error: Cannot find file containing module: Multi-processor/SM.srcs/sim_1/new,data/full_repos/permissive/115632823\n ... Looked in:\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sim_1/new,data/full_repos/permissive/115632823\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sim_1/new,data/full_repos/permissive/115632823.v\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sim_1/new,data/full_repos/permissive/115632823.sv\n Multi-processor/SM.srcs/sim_1/new,data/full_repos/permissive/115632823\n Multi-processor/SM.srcs/sim_1/new,data/full_repos/permissive/115632823.v\n Multi-processor/SM.srcs/sim_1/new,data/full_repos/permissive/115632823.sv\n obj_dir/Multi-processor/SM.srcs/sim_1/new,data/full_repos/permissive/115632823\n obj_dir/Multi-processor/SM.srcs/sim_1/new,data/full_repos/permissive/115632823.v\n obj_dir/Multi-processor/SM.srcs/sim_1/new,data/full_repos/permissive/115632823.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/115632823/code/Stream\n%Error: Cannot find file containing module: Multi-processor/SM.srcs/sim_1/new/test.v\n%Error: Exiting due to 3 error(s)\n' | 6,970 | module | module test();
reg clk;
initial begin
clk = 1;
end
StreamingMultiprocesser SM(.CLK(clk));
always begin
#100 clk = ~clk;
end
endmodule | module test(); |
reg clk;
initial begin
clk = 1;
end
StreamingMultiprocesser SM(.CLK(clk));
always begin
#100 clk = ~clk;
end
endmodule | 1 |
6,202 | data/full_repos/permissive/115632823/code/Stream Multi-processor/SM.srcs/sources_1/new/FpMultiplier.v | 115,632,823 | FpMultiplier.v | v | 65 | 142 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa3 in position 178: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n ... Looked in:\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/115632823/code/Stream\n%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new/FpMultiplier.v\n%Error: Exiting due to 3 error(s)\n' | 6,974 | module | module FpMultiplier(
input wire [31:0] A,
input wire [31:0] B,
output reg [31:0] Result
);
reg [1:0] overflow;
reg signA, signB, signR;
reg [7:0] expA, expB, expR;
reg [22:0] manA, manB, manR;
reg normalRight;
reg [7:0] tempExpA, tempExpB;
reg [8:0] tempExpR;
reg [23:0] tempMan;
reg [45:0] tempProduct;
reg [23:0] tempSum;
reg [1:0] intPart;
always@(A or B) begin
signA = A[31];
expA = A[30:23];
manA = A[22:0];
signB = B[31];
expB = B[30:23];
manB = B[22:0];
tempProduct = manA * manB;
tempSum = manA + manB;
tempMan = tempProduct[45:23] + tempSum[22:0];
intPart = 1 + tempMan[23] + tempSum[23];
if(intPart[1] == 1) begin
normalRight = 1'b1;
manR = {intPart[0], tempMan[22:1]};
end
else begin
normalRight = 1'b0;
manR = tempMan;
end
tempExpR = tempExpA + tempExpB - 127 + normalRight;
case(tempExpR[8:7])
2'b10: overflow = 2'b10;
2'b01: overflow = 2'b01;
endcase
expR = tempExpR[7:0];
signR = signA ^ signB;
Result = {signR, expR, manR};
end
endmodule | module FpMultiplier(
input wire [31:0] A,
input wire [31:0] B,
output reg [31:0] Result
); |
reg [1:0] overflow;
reg signA, signB, signR;
reg [7:0] expA, expB, expR;
reg [22:0] manA, manB, manR;
reg normalRight;
reg [7:0] tempExpA, tempExpB;
reg [8:0] tempExpR;
reg [23:0] tempMan;
reg [45:0] tempProduct;
reg [23:0] tempSum;
reg [1:0] intPart;
always@(A or B) begin
signA = A[31];
expA = A[30:23];
manA = A[22:0];
signB = B[31];
expB = B[30:23];
manB = B[22:0];
tempProduct = manA * manB;
tempSum = manA + manB;
tempMan = tempProduct[45:23] + tempSum[22:0];
intPart = 1 + tempMan[23] + tempSum[23];
if(intPart[1] == 1) begin
normalRight = 1'b1;
manR = {intPart[0], tempMan[22:1]};
end
else begin
normalRight = 1'b0;
manR = tempMan;
end
tempExpR = tempExpA + tempExpB - 127 + normalRight;
case(tempExpR[8:7])
2'b10: overflow = 2'b10;
2'b01: overflow = 2'b01;
endcase
expR = tempExpR[7:0];
signR = signA ^ signB;
Result = {signR, expR, manR};
end
endmodule | 1 |
6,203 | data/full_repos/permissive/115632823/code/Stream Multi-processor/SM.srcs/sources_1/new/Instruction_Cache.v | 115,632,823 | Instruction_Cache.v | v | 142 | 170 | [] | [] | [] | [(1, 141)] | null | null | 1: b'%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n ... Looked in:\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/115632823/code/Stream\n%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new/Instruction_Cache.v\n%Error: Exiting due to 3 error(s)\n' | 6,975 | module | module Instruction_Cache(
input wire [7:0] validVector,
output reg [64*8-1:0] Ins
);
reg [3:0] BarrierNum;
reg [7:0] InsMem[0:1023];
reg [63:0] InsReal[7:0];
integer i, j, t, InsPtr;
initial begin
$readmemb("../../../Ins.txt", InsMem);
InsPtr = 0;
end
always @(validVector) begin
for(j = 0; j < 8; j = j + 1) begin
for(t = 0; t < 64; t = t + 1) begin
Ins[j*64+t] <= InsReal[j][t];
end
end
end
always @(validVector) begin
BarrierNum = 8;
for(i = 0; i < 8; i=i + 1) begin
if(validVector[i] == 0 && i < BarrierNum) begin
InsReal[i] = {InsMem[InsPtr], InsMem[InsPtr+1], InsMem[InsPtr+2], InsMem[InsPtr+3], InsMem[InsPtr+4], InsMem[InsPtr+5], InsMem[InsPtr+6], InsMem[InsPtr+7]};
if(InsReal[i][63:54] == 10'b1111_1111_10) begin
BarrierNum = i;
InsReal[i] = 64'hFFFF_FFFF;
end
InsPtr = InsPtr + 8;
end
else begin
InsReal[i] = 64'hFFFF_FFFF;
end
end
end
endmodule | module Instruction_Cache(
input wire [7:0] validVector,
output reg [64*8-1:0] Ins
); |
reg [3:0] BarrierNum;
reg [7:0] InsMem[0:1023];
reg [63:0] InsReal[7:0];
integer i, j, t, InsPtr;
initial begin
$readmemb("../../../Ins.txt", InsMem);
InsPtr = 0;
end
always @(validVector) begin
for(j = 0; j < 8; j = j + 1) begin
for(t = 0; t < 64; t = t + 1) begin
Ins[j*64+t] <= InsReal[j][t];
end
end
end
always @(validVector) begin
BarrierNum = 8;
for(i = 0; i < 8; i=i + 1) begin
if(validVector[i] == 0 && i < BarrierNum) begin
InsReal[i] = {InsMem[InsPtr], InsMem[InsPtr+1], InsMem[InsPtr+2], InsMem[InsPtr+3], InsMem[InsPtr+4], InsMem[InsPtr+5], InsMem[InsPtr+6], InsMem[InsPtr+7]};
if(InsReal[i][63:54] == 10'b1111_1111_10) begin
BarrierNum = i;
InsReal[i] = 64'hFFFF_FFFF;
end
InsPtr = InsPtr + 8;
end
else begin
InsReal[i] = 64'hFFFF_FFFF;
end
end
end
endmodule | 1 |
6,204 | data/full_repos/permissive/115632823/code/Stream Multi-processor/SM.srcs/sources_1/new/MulticastNetwork.v | 115,632,823 | MulticastNetwork.v | v | 46 | 61 | [] | [] | [] | [(1, 46)] | null | null | 1: b'%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n ... Looked in:\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/115632823/code/Stream\n%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new/MulticastNetwork.v\n%Error: Exiting due to 3 error(s)\n' | 6,976 | module | module MulticastNetwork(
input wire [32*16-1:0] DataIn,
input wire [8*16-1:0] RequestVector,
input wire [7:0] ReturnIn,
output reg [32*8-1:0] DataOut,
output wire [7:0] ReturnOut
);
integer i;
integer j;
assign ReturnOut = ReturnIn;
reg [31:0]DataInReal[15:0];
reg [7:0] RequestVectorReal[15:0];
reg [31:0] DataOutReal[7:0];
always@(DataIn or RequestVector or ReturnIn) begin
for(i = 0; i < 16; i = i + 1) begin
for(j = 0; j < 32; j = j + 1) begin
DataInReal[i][j] <= DataIn[i*32+j];
end
end
for(i = 0; i < 8; i = i + 1) begin
for(j = 0; j < 16; j = j + 1) begin
RequestVectorReal[i][j] <= RequestVector[i*8+j];
end
end
for(i = 0; i < 16; i = i + 1) begin
for(j = 0; j < 8; j = j + 1) begin
if(RequestVectorReal[j] == 1) begin
DataOutReal[j] <= DataInReal[i];
end
end
end
for(i = 0; i < 8; i = i + 1) begin
for(j = 0; j < 32; j = j + 1) begin
DataOut[i*8+j] <= DataOutReal[i][j];
end
end
end
endmodule | module MulticastNetwork(
input wire [32*16-1:0] DataIn,
input wire [8*16-1:0] RequestVector,
input wire [7:0] ReturnIn,
output reg [32*8-1:0] DataOut,
output wire [7:0] ReturnOut
); |
integer i;
integer j;
assign ReturnOut = ReturnIn;
reg [31:0]DataInReal[15:0];
reg [7:0] RequestVectorReal[15:0];
reg [31:0] DataOutReal[7:0];
always@(DataIn or RequestVector or ReturnIn) begin
for(i = 0; i < 16; i = i + 1) begin
for(j = 0; j < 32; j = j + 1) begin
DataInReal[i][j] <= DataIn[i*32+j];
end
end
for(i = 0; i < 8; i = i + 1) begin
for(j = 0; j < 16; j = j + 1) begin
RequestVectorReal[i][j] <= RequestVector[i*8+j];
end
end
for(i = 0; i < 16; i = i + 1) begin
for(j = 0; j < 8; j = j + 1) begin
if(RequestVectorReal[j] == 1) begin
DataOutReal[j] <= DataInReal[i];
end
end
end
for(i = 0; i < 8; i = i + 1) begin
for(j = 0; j < 32; j = j + 1) begin
DataOut[i*8+j] <= DataOutReal[i][j];
end
end
end
endmodule | 1 |
6,205 | data/full_repos/permissive/115632823/code/Stream Multi-processor/SM.srcs/sources_1/new/MultithreadedInstructionUnit.v | 115,632,823 | MultithreadedInstructionUnit.v | v | 22 | 42 | [] | [] | [] | [(1, 22)] | null | null | 1: b'%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n ... Looked in:\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/115632823/code/Stream\n%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new/MultithreadedInstructionUnit.v\n%Error: Exiting due to 3 error(s)\n' | 6,977 | module | module MultithreadInstructionUnit(
input wire clk,
input wire [7:0] validVectorOri,
input wire [64*8-1:0] Ins,
output reg [64*8-1:0] instructions,
output reg [7:0] validVectorTo
);
integer i;
always @(posedge clk) begin
for(i = 0; i < 64*8; i = i + 1) begin
instructions[i] <= Ins[i];
end
end
always @(negedge clk) begin
validVectorTo = validVectorOri;
end
endmodule | module MultithreadInstructionUnit(
input wire clk,
input wire [7:0] validVectorOri,
input wire [64*8-1:0] Ins,
output reg [64*8-1:0] instructions,
output reg [7:0] validVectorTo
); |
integer i;
always @(posedge clk) begin
for(i = 0; i < 64*8; i = i + 1) begin
instructions[i] <= Ins[i];
end
end
always @(negedge clk) begin
validVectorTo = validVectorOri;
end
endmodule | 1 |
6,206 | data/full_repos/permissive/115632823/code/Stream Multi-processor/SM.srcs/sources_1/new/RegFile.v | 115,632,823 | RegFile.v | v | 28 | 62 | [] | [] | [] | [(3, 27)] | null | null | 1: b'%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n ... Looked in:\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/115632823/code/Stream\n%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new/RegFile.v\n%Error: Exiting due to 3 error(s)\n' | 6,978 | module | module RegFile(
input clk,
input RegWre,
input [9:0] ReadReg1,ReadReg2,WriteReg,
input [31:0] WriteData,
input [31:0] ReadData1,ReadData2
);
reg [31:0] regFile [1:1023];
integer i;
assign ReadData1 = (ReadReg1 == 0)? 0: regFile[ReadReg1];
assign ReadData2 = (ReadReg2 == 0)? 0: regFile[ReadReg2];
always@(posedge clk)
begin
if(RegWre == 1 && WriteReg != 0)
regFile[WriteReg] <= WriteData;
end
endmodule | module RegFile(
input clk,
input RegWre,
input [9:0] ReadReg1,ReadReg2,WriteReg,
input [31:0] WriteData,
input [31:0] ReadData1,ReadData2
); |
reg [31:0] regFile [1:1023];
integer i;
assign ReadData1 = (ReadReg1 == 0)? 0: regFile[ReadReg1];
assign ReadData2 = (ReadReg2 == 0)? 0: regFile[ReadReg2];
always@(posedge clk)
begin
if(RegWre == 1 && WriteReg != 0)
regFile[WriteReg] <= WriteData;
end
endmodule | 1 |
6,207 | data/full_repos/permissive/115632823/code/Stream Multi-processor/SM.srcs/sources_1/new/SharedMemory.v | 115,632,823 | SharedMemory.v | v | 196 | 472 | [] | [] | [] | null | line:10: before: "[" | null | 1: b'%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n ... Looked in:\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/115632823/code/Stream\n%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new/SharedMemory.v\n%Error: Exiting due to 3 error(s)\n' | 6,979 | module | module ShareMemory(
input wire clk,
input wire [7:0] MemoryWrite,
input wire [7:0] MemoryRead,
input wire [31:0][7:0] WriteData,
input wire [31:0][7:0] Address,
output reg [7:0] Return,
output reg [7:0][15:0] RequestVector,
output reg [31:0][15:0] Data
);
reg [31:0]WriteDataReal[7:0];
reg [31:0]AddressReal[7:0];
reg [7:0]RequestVectorReal[15:0];
reg [31:0]DataReal[15:0];
integer i, j, t, z;
always@(Address or WriteData) begin
for(i = 0; i < 8; i = i + 1) begin
AddressReal[i] = Address[i];
WriteDataReal[i] = WriteData[i];
end
end
reg [7:0] banks[64*`K-1:0];
reg [3:0] targetBank[7:0];
reg [3:0] firstReq[7:0];
reg [2:0] conflicts[7:0];
integer head, tail;
initial begin
head = 0;
tail = -1;
end
always@(posedge clk) begin
for(i = 0; i < 8; i = i + 1) begin
firstReq[i] = 8;
end
for(i = 0; i < 8; i = i + 1) begin
if(AddressReal[i]/4 % 16 == 0) begin
targetBank[i] <= 0;
RequestVectorReal[0][i]<=1;
end
else if(AddressReal[i]/4 % 16 == 1) begin
RequestVectorReal[0][i] <= 0;
targetBank[i] <= 1;
RequestVectorReal[1][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 2) begin
RequestVectorReal[1][i] <= 0;
targetBank[i] <= 2;
RequestVectorReal[2][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 3) begin
RequestVectorReal[2][i] <= 0;
targetBank[i] <= 3;
RequestVectorReal[3][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 4) begin
RequestVectorReal[3][i] <= 0;
targetBank[i] <= 4;
RequestVectorReal[4][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 5) begin
RequestVectorReal[4][i] <= 0;
targetBank[i] <= 5;
RequestVectorReal[5][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 6) begin
RequestVectorReal[5][i] <= 0;
targetBank[i] <= 6;
RequestVectorReal[6][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 7) begin
RequestVectorReal[6][i] <= 0;
targetBank[i] <= 7;
RequestVectorReal[7][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 8) begin
RequestVectorReal[7][i] <= 0;
targetBank[i] <= 8;
RequestVectorReal[7][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 9) begin
RequestVectorReal[8][i] <= 0;
targetBank[i] <= 9;
RequestVectorReal[9][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 10) begin
RequestVectorReal[9][i] <= 0;
targetBank[i] <= 10;
RequestVectorReal[10][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 11) begin
RequestVectorReal[10][i] <= 0;
targetBank[i] <= 11;
RequestVectorReal[11][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 12) begin
RequestVectorReal[11][i] <= 0;
targetBank[i] <= 12;
RequestVectorReal[12][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 13) begin
RequestVectorReal[12][i] <= 0;
targetBank[i] <= 13;
RequestVectorReal[13][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 14) begin
RequestVectorReal[13][i] <= 0;
targetBank[i] <= 14;
RequestVectorReal[14][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 15) begin
RequestVectorReal[14][i] <= 0;
targetBank[i] <= 15;
RequestVectorReal[15][i] <= 1;
end
else begin
RequestVectorReal[15][i] <= 0;
end
if(firstReq[targetBank[i]] != 8) begin
if(AddressReal[i] != AddressReal[firstReq[targetBank[i]]] && MemoryRead[i] == 1) begin
RequestVectorReal[targetBank[i]][i] <= 0;
tail <= (tail+1)%`MAX;
conflicts[tail] <= i;
Return[i] <= 0;
end
else begin
if(MemoryRead[i] == 1) begin
Return[i] <= 1;
end
end
end
else begin
if(MemoryRead[i] == 1) begin
firstReq[targetBank[i]] <= i;
DataReal[targetBank[i]] <= {banks[AddressReal[i]], banks[AddressReal[i]+1] , banks[AddressReal[i]+2], banks[AddressReal[i]+3]};
Return[i] <= 1;
end
end
end
if((tail+1)%`MAX != head) begin
DataReal[targetBank[conflicts[head]]] <= {banks[AddressReal[conflicts[head]]], banks[AddressReal[conflicts[head]]+1], banks[AddressReal[conflicts[head]]+2], banks[AddressReal[conflicts[head]]+3]};
for(j = 0; j < 8; j = j + 1) begin
if(j == conflicts[head]) begin
RequestVectorReal[j] <= 1;
end
else begin
RequestVectorReal[j] <= 0;
end
end
Return[conflicts[head]] <= 1;
head <= (head+1)%`MAX;
end
end
always@(posedge clk) begin
for(t = 0; t < 8; t = t + 1) begin
if(MemoryWrite[t] == 1) begin
{banks[AddressReal[t]], banks[AddressReal[t]+1], banks[AddressReal[t]+2], banks[AddressReal[t]+3]} <= WriteDataReal[t];
end
end
end
always@(*) begin
for(z = 0; z < 16; z = z + 1) begin
RequestVector[z] = RequestVectorReal[z];
Data[z] = DataReal[z];
end
end
endmodule | module ShareMemory(
input wire clk,
input wire [7:0] MemoryWrite,
input wire [7:0] MemoryRead,
input wire [31:0][7:0] WriteData,
input wire [31:0][7:0] Address,
output reg [7:0] Return,
output reg [7:0][15:0] RequestVector,
output reg [31:0][15:0] Data
); |
reg [31:0]WriteDataReal[7:0];
reg [31:0]AddressReal[7:0];
reg [7:0]RequestVectorReal[15:0];
reg [31:0]DataReal[15:0];
integer i, j, t, z;
always@(Address or WriteData) begin
for(i = 0; i < 8; i = i + 1) begin
AddressReal[i] = Address[i];
WriteDataReal[i] = WriteData[i];
end
end
reg [7:0] banks[64*`K-1:0];
reg [3:0] targetBank[7:0];
reg [3:0] firstReq[7:0];
reg [2:0] conflicts[7:0];
integer head, tail;
initial begin
head = 0;
tail = -1;
end
always@(posedge clk) begin
for(i = 0; i < 8; i = i + 1) begin
firstReq[i] = 8;
end
for(i = 0; i < 8; i = i + 1) begin
if(AddressReal[i]/4 % 16 == 0) begin
targetBank[i] <= 0;
RequestVectorReal[0][i]<=1;
end
else if(AddressReal[i]/4 % 16 == 1) begin
RequestVectorReal[0][i] <= 0;
targetBank[i] <= 1;
RequestVectorReal[1][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 2) begin
RequestVectorReal[1][i] <= 0;
targetBank[i] <= 2;
RequestVectorReal[2][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 3) begin
RequestVectorReal[2][i] <= 0;
targetBank[i] <= 3;
RequestVectorReal[3][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 4) begin
RequestVectorReal[3][i] <= 0;
targetBank[i] <= 4;
RequestVectorReal[4][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 5) begin
RequestVectorReal[4][i] <= 0;
targetBank[i] <= 5;
RequestVectorReal[5][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 6) begin
RequestVectorReal[5][i] <= 0;
targetBank[i] <= 6;
RequestVectorReal[6][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 7) begin
RequestVectorReal[6][i] <= 0;
targetBank[i] <= 7;
RequestVectorReal[7][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 8) begin
RequestVectorReal[7][i] <= 0;
targetBank[i] <= 8;
RequestVectorReal[7][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 9) begin
RequestVectorReal[8][i] <= 0;
targetBank[i] <= 9;
RequestVectorReal[9][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 10) begin
RequestVectorReal[9][i] <= 0;
targetBank[i] <= 10;
RequestVectorReal[10][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 11) begin
RequestVectorReal[10][i] <= 0;
targetBank[i] <= 11;
RequestVectorReal[11][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 12) begin
RequestVectorReal[11][i] <= 0;
targetBank[i] <= 12;
RequestVectorReal[12][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 13) begin
RequestVectorReal[12][i] <= 0;
targetBank[i] <= 13;
RequestVectorReal[13][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 14) begin
RequestVectorReal[13][i] <= 0;
targetBank[i] <= 14;
RequestVectorReal[14][i] <= 1;
end
else if(AddressReal[i]/4 % 16 == 15) begin
RequestVectorReal[14][i] <= 0;
targetBank[i] <= 15;
RequestVectorReal[15][i] <= 1;
end
else begin
RequestVectorReal[15][i] <= 0;
end
if(firstReq[targetBank[i]] != 8) begin
if(AddressReal[i] != AddressReal[firstReq[targetBank[i]]] && MemoryRead[i] == 1) begin
RequestVectorReal[targetBank[i]][i] <= 0;
tail <= (tail+1)%`MAX;
conflicts[tail] <= i;
Return[i] <= 0;
end
else begin
if(MemoryRead[i] == 1) begin
Return[i] <= 1;
end
end
end
else begin
if(MemoryRead[i] == 1) begin
firstReq[targetBank[i]] <= i;
DataReal[targetBank[i]] <= {banks[AddressReal[i]], banks[AddressReal[i]+1] , banks[AddressReal[i]+2], banks[AddressReal[i]+3]};
Return[i] <= 1;
end
end
end
if((tail+1)%`MAX != head) begin
DataReal[targetBank[conflicts[head]]] <= {banks[AddressReal[conflicts[head]]], banks[AddressReal[conflicts[head]]+1], banks[AddressReal[conflicts[head]]+2], banks[AddressReal[conflicts[head]]+3]};
for(j = 0; j < 8; j = j + 1) begin
if(j == conflicts[head]) begin
RequestVectorReal[j] <= 1;
end
else begin
RequestVectorReal[j] <= 0;
end
end
Return[conflicts[head]] <= 1;
head <= (head+1)%`MAX;
end
end
always@(posedge clk) begin
for(t = 0; t < 8; t = t + 1) begin
if(MemoryWrite[t] == 1) begin
{banks[AddressReal[t]], banks[AddressReal[t]+1], banks[AddressReal[t]+2], banks[AddressReal[t]+3]} <= WriteDataReal[t];
end
end
end
always@(*) begin
for(z = 0; z < 16; z = z + 1) begin
RequestVector[z] = RequestVectorReal[z];
Data[z] = DataReal[z];
end
end
endmodule | 1 |
6,208 | data/full_repos/permissive/115632823/code/Stream Multi-processor/SM.srcs/sources_1/new/StreamingMultiprocesser.v | 115,632,823 | StreamingMultiprocesser.v | v | 60 | 125 | [] | [] | [] | [(2, 59)] | null | null | 1: b'%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n ... Looked in:\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/115632823/code/Stream\n%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new/StreamingMultiprocesser.v\n%Error: Exiting due to 3 error(s)\n' | 6,980 | module | module StreamingMultiprocesser(
input wire CLK
);
wire [64*8-1:0] Ins;
wire [64*8-1:0] InsOutOfMulInsUnit;
wire [7:0] ValidVector;
Instruction_Cache InsCache(
.validVector(ValidVector), .Ins(Ins)
);
wire [7:0] ValidVectorFromSP;
MultithreadInstructionUnit MulInsUnit(
.clk(CLK), .validVectorOri(ValidVectorFromSP), .Ins(Ins), .instructions(InsOutOfMulInsUnit), .validVectorTo(ValidVector)
);
wire [7:0] ReturnFMulNet;
wire [7:0] ReturnFShared;
wire [32*8-1:0] DataFMulNet;
wire [32*16-1:0] DataFShared;
wire [8*16-1:0] RequestVector;
wire [32*8-1:0] MemoryAddress;
wire [32*8-1:0] MemoryWriteData;
wire [7:0] MemoryRead;
wire [7:0] MemoryWrite;
genvar gv_i;
generate
for(gv_i = 0; gv_i < 8; gv_i = gv_i + 1) begin : SP
StreamProcessor _SP(
.clk(CLK), .instruction(InsOutOfMulInsUnit[(gv_i+1)*64-1:gv_i*64]),
.Return(ReturnFMulNet[gv_i]), .MemoryReadData(DataFMulNet[(gv_i+1)*32-1:gv_i*32]),
.Occupied(ValidVectorFromSP[gv_i]), .MemoryAddress(MemoryAddress[(gv_i+1)*32-1:gv_i*32]),
.MemoryWriteData(MemoryWriteData[(gv_i+1)*32-1:gv_i*32]), .MemoryRead(MemoryRead[gv_i]),
.MemoryWrite(MemoryWrite[gv_i])
);
end
endgenerate
MulticastNetwork MulNet(
.DataIn(DataFShared), .RequestVector(RequestVector), .ReturnIn(ReturnFShared),
.DataOut(DataFMulNet), .ReturnOut(ReturnFMulNet)
);
ShareMemory SharedMem(
.clk(CLK), .MemoryWrite(MemoryWrite), .MemoryRead(MemoryRead), .WriteData(MemoryWriteData), .Address(MemoryAddress),
.Return(ReturnFShared), .RequestVector(RequestVector), .Data(DataFShared)
);
endmodule | module StreamingMultiprocesser(
input wire CLK
); |
wire [64*8-1:0] Ins;
wire [64*8-1:0] InsOutOfMulInsUnit;
wire [7:0] ValidVector;
Instruction_Cache InsCache(
.validVector(ValidVector), .Ins(Ins)
);
wire [7:0] ValidVectorFromSP;
MultithreadInstructionUnit MulInsUnit(
.clk(CLK), .validVectorOri(ValidVectorFromSP), .Ins(Ins), .instructions(InsOutOfMulInsUnit), .validVectorTo(ValidVector)
);
wire [7:0] ReturnFMulNet;
wire [7:0] ReturnFShared;
wire [32*8-1:0] DataFMulNet;
wire [32*16-1:0] DataFShared;
wire [8*16-1:0] RequestVector;
wire [32*8-1:0] MemoryAddress;
wire [32*8-1:0] MemoryWriteData;
wire [7:0] MemoryRead;
wire [7:0] MemoryWrite;
genvar gv_i;
generate
for(gv_i = 0; gv_i < 8; gv_i = gv_i + 1) begin : SP
StreamProcessor _SP(
.clk(CLK), .instruction(InsOutOfMulInsUnit[(gv_i+1)*64-1:gv_i*64]),
.Return(ReturnFMulNet[gv_i]), .MemoryReadData(DataFMulNet[(gv_i+1)*32-1:gv_i*32]),
.Occupied(ValidVectorFromSP[gv_i]), .MemoryAddress(MemoryAddress[(gv_i+1)*32-1:gv_i*32]),
.MemoryWriteData(MemoryWriteData[(gv_i+1)*32-1:gv_i*32]), .MemoryRead(MemoryRead[gv_i]),
.MemoryWrite(MemoryWrite[gv_i])
);
end
endgenerate
MulticastNetwork MulNet(
.DataIn(DataFShared), .RequestVector(RequestVector), .ReturnIn(ReturnFShared),
.DataOut(DataFMulNet), .ReturnOut(ReturnFMulNet)
);
ShareMemory SharedMem(
.clk(CLK), .MemoryWrite(MemoryWrite), .MemoryRead(MemoryRead), .WriteData(MemoryWriteData), .Address(MemoryAddress),
.Return(ReturnFShared), .RequestVector(RequestVector), .Data(DataFShared)
);
endmodule | 1 |
6,210 | data/full_repos/permissive/11571685/verilog/display_data.v | 11,571,685 | display_data.v | v | 192 | 74 | [] | [] | [] | [(3, 191)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/11571685/verilog/display_data.v:39: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n : ... In instance display_data\n dig3 <= decimal_nybble[15:12];\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/11571685/verilog/display_data.v:40: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n : ... In instance display_data\n dig2 <= decimal_nybble[11:8];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/11571685/verilog/display_data.v:41: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n : ... In instance display_data\n dig1 <= decimal_nybble[7:4];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/11571685/verilog/display_data.v:42: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n : ... In instance display_data\n dig0 <= decimal_nybble[3:0];\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 6,982 | module | module display_data(
input clk,
input [15:0] decimal_nybble,
output reg [3:0] seg_an_reg,
output reg [7:0] seg_cat_reg
);
integer slowdown;
reg [1:0] state;
integer ID;
integer digit;
integer dig0;
integer dig1;
integer dig2;
integer dig3;
integer temp0;
integer temp1;
initial begin
slowdown = 0;
state = 0;
digit = 0;
dig0 = 0;
dig1 = 0;
dig2 = 0;
dig3 = 0;
ID = 0;
seg_an_reg = 4'b0000;
seg_cat_reg = 8'b00000000;
end
always @(decimal_nybble) begin
dig3 <= decimal_nybble[15:12];
dig2 <= decimal_nybble[11:8];
dig1 <= decimal_nybble[7:4];
dig0 <= decimal_nybble[3:0];
end
always @(posedge clk) begin
if(slowdown==200000) begin
case(state)
2'd0: begin
digit = dig0;
seg_an_reg[0] <= 0;
seg_an_reg[1] <= 1;
seg_an_reg[2] <= 1;
seg_an_reg[3] <= 1;
end
2'd1: begin
digit = dig1;
seg_an_reg[0] <= 1;
seg_an_reg[1] <= 0;
seg_an_reg[2] <= 1;
seg_an_reg[3] <= 1;
end
2'd2: begin
digit = dig2;
seg_an_reg[0] <= 1;
seg_an_reg[1] <= 1;
seg_an_reg[2] <= 0;
seg_an_reg[3] <= 1;
end
2'd3: begin
digit = dig3;
seg_an_reg[0] <= 1;
seg_an_reg[1] <= 1;
seg_an_reg[2] <= 1;
seg_an_reg[3] <= 0;
end
endcase
case(digit)
'd0: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 0;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 1;
seg_cat_reg[7] = 1;
end
'd1: begin
seg_cat_reg[0] = 1;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 1;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 1;
seg_cat_reg[6] = 1;
seg_cat_reg[7] = 1;
end
'd2: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 1;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 0;
seg_cat_reg[5] = 1;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd3: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 1;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd4: begin
seg_cat_reg[0] = 1;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 1;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd5: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 1;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd6: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 1;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 0;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd7: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 1;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 1;
seg_cat_reg[6] = 1;
seg_cat_reg[7] = 1;
end
'd8: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 0;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd9: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
endcase
case(state)
2'd3: state <= 0;
default: state <= state + 1;
endcase
slowdown <= 0;
end else slowdown <= slowdown + 1;
end
endmodule | module display_data(
input clk,
input [15:0] decimal_nybble,
output reg [3:0] seg_an_reg,
output reg [7:0] seg_cat_reg
); |
integer slowdown;
reg [1:0] state;
integer ID;
integer digit;
integer dig0;
integer dig1;
integer dig2;
integer dig3;
integer temp0;
integer temp1;
initial begin
slowdown = 0;
state = 0;
digit = 0;
dig0 = 0;
dig1 = 0;
dig2 = 0;
dig3 = 0;
ID = 0;
seg_an_reg = 4'b0000;
seg_cat_reg = 8'b00000000;
end
always @(decimal_nybble) begin
dig3 <= decimal_nybble[15:12];
dig2 <= decimal_nybble[11:8];
dig1 <= decimal_nybble[7:4];
dig0 <= decimal_nybble[3:0];
end
always @(posedge clk) begin
if(slowdown==200000) begin
case(state)
2'd0: begin
digit = dig0;
seg_an_reg[0] <= 0;
seg_an_reg[1] <= 1;
seg_an_reg[2] <= 1;
seg_an_reg[3] <= 1;
end
2'd1: begin
digit = dig1;
seg_an_reg[0] <= 1;
seg_an_reg[1] <= 0;
seg_an_reg[2] <= 1;
seg_an_reg[3] <= 1;
end
2'd2: begin
digit = dig2;
seg_an_reg[0] <= 1;
seg_an_reg[1] <= 1;
seg_an_reg[2] <= 0;
seg_an_reg[3] <= 1;
end
2'd3: begin
digit = dig3;
seg_an_reg[0] <= 1;
seg_an_reg[1] <= 1;
seg_an_reg[2] <= 1;
seg_an_reg[3] <= 0;
end
endcase
case(digit)
'd0: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 0;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 1;
seg_cat_reg[7] = 1;
end
'd1: begin
seg_cat_reg[0] = 1;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 1;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 1;
seg_cat_reg[6] = 1;
seg_cat_reg[7] = 1;
end
'd2: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 1;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 0;
seg_cat_reg[5] = 1;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd3: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 1;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd4: begin
seg_cat_reg[0] = 1;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 1;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd5: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 1;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd6: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 1;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 0;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd7: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 1;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 1;
seg_cat_reg[6] = 1;
seg_cat_reg[7] = 1;
end
'd8: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 0;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd9: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
endcase
case(state)
2'd3: state <= 0;
default: state <= state + 1;
endcase
slowdown <= 0;
end else slowdown <= slowdown + 1;
end
endmodule | 0 |
6,211 | data/full_repos/permissive/11571685/verilog/freq_decode.v | 11,571,685 | freq_decode.v | v | 38 | 41 | [] | [] | [] | [(3, 37)] | null | data/verilator_xmls/b36ac6fe-25e6-41ea-9248-81efe3c88424.xml | null | 6,983 | module | module freq_decode(
input clk,
input sq_wv,
input data_in,
input manual,
output reg data_out
);
integer pulse_count;
reg last_sq;
reg last_data;
initial begin
pulse_count = 0;
last_sq = 0;
last_data = 0;
data_out = 0;
end
always @(posedge sq_wv) begin
pulse_count = pulse_count + 1;
if (manual == 1) data_out <= 0;
if(last_data<data_in) begin
if(pulse_count==8) data_out<=0;
else if(pulse_count==10) data_out<=1;
else data_out<=data_out;
pulse_count = 0;
end
last_data <= data_in;
end
endmodule | module freq_decode(
input clk,
input sq_wv,
input data_in,
input manual,
output reg data_out
); |
integer pulse_count;
reg last_sq;
reg last_data;
initial begin
pulse_count = 0;
last_sq = 0;
last_data = 0;
data_out = 0;
end
always @(posedge sq_wv) begin
pulse_count = pulse_count + 1;
if (manual == 1) data_out <= 0;
if(last_data<data_in) begin
if(pulse_count==8) data_out<=0;
else if(pulse_count==10) data_out<=1;
else data_out<=data_out;
pulse_count = 0;
end
last_data <= data_in;
end
endmodule | 0 |
6,212 | data/full_repos/permissive/11571685/verilog/fsk_iface_mchester.v | 11,571,685 | fsk_iface_mchester.v | v | 151 | 83 | [] | [] | [] | [(21, 150)] | null | data/verilator_xmls/5d2bee53-d570-4922-af69-f798531abffa.xml | null | 6,984 | module | module fsk_iface_mchester(
input sqwv,
input fsk_in,
input manual,
output reg fsk_out,
output reg fsk_out_trigger,
output reg done
);
integer count_0s, count_0secs, count_1s, count_all;
reg [2:0] occurence;
reg ready_or_not;
reg [1:0] ready_preamble_stage;
initial begin
ready_or_not = 0;
ready_preamble_stage = 0;
count_0s = 0;
count_1s = 0;
count_all = 0;
fsk_out_trigger = 0;
fsk_out = 0;
occurence = 0;
done = 0;
end
always @(posedge sqwv) begin
if (manual == 1) begin
ready_or_not <= 0;
ready_preamble_stage <= 0;
count_0s <= 0;
count_1s <= 0;
count_all <= 0;
fsk_out <= 0;
fsk_out_trigger <= 0;
occurence <= 0;
done <= 0;
end
else if (ready_or_not == 0) begin
if (ready_preamble_stage == 0 && fsk_in == 1) begin
count_1s <= count_1s + 1;
ready_preamble_stage <= 1;
end
else if (ready_preamble_stage == 1) begin
if (fsk_in == 1) begin
count_1s <= count_1s + 1;
if (count_1s == 150) begin
count_0s <= 0;
ready_preamble_stage <= 2;
end
end
else begin
count_1s <= 0;
ready_preamble_stage <= 0;
end
end
else if (ready_preamble_stage == 2) begin
if (fsk_in == 0) begin
count_0s <= count_0s + 1;
if (count_0s == 152) begin
count_1s <= 0;
ready_preamble_stage <= 3;
end
end
else begin
count_0s <= 0;
ready_preamble_stage <= 2;
end
end
else if (ready_preamble_stage == 3) begin
if (fsk_in == 1) begin
count_1s <= count_1s + 1;
if (count_1s == 150) begin
count_1s <= 0; count_0s <= 0; count_all <= 0;
ready_preamble_stage <= 0; ready_or_not <= 1;
end
end
else if (fsk_in == 0 && count_1s == 0);
else begin
count_1s <= 0;
ready_preamble_stage <= 0;
end
end
end
else if (ready_or_not == 1 && count_0secs == 152) begin
ready_or_not <= 0;
ready_preamble_stage <= 0;
count_1s <= 0;
count_0s <= 0;
count_0secs <= 0;
count_all <= 0;
done <= 1;
end
else begin
if (fsk_in == 1) begin
count_1s <= count_1s + 1;
count_0secs <= 0;
count_all <= count_all + 1;
end
else begin
count_0s <= count_0s + 1;
count_0secs <= count_0secs + 1;
count_all <= count_all + 1;
end
if (((count_all == 48-1) && (count_0s > count_1s) && (occurence % 4 != 1)) ||
((count_all == 56-1) && (count_0s > count_1s) && (occurence % 4 == 1))) begin
occurence <= (occurence + 1) % 4;
fsk_out <= 0;
fsk_out_trigger <= ~fsk_out_trigger;
count_0s <= 0;
count_1s <= 0;
count_all <= 0;
end
else if ((count_all == 50-1) && (count_1s > count_0s)) begin
fsk_out <= 1;
fsk_out_trigger <= ~fsk_out_trigger;
count_0s <= 0;
count_1s <= 0;
count_all <= 0;
end
end
end
endmodule | module fsk_iface_mchester(
input sqwv,
input fsk_in,
input manual,
output reg fsk_out,
output reg fsk_out_trigger,
output reg done
); |
integer count_0s, count_0secs, count_1s, count_all;
reg [2:0] occurence;
reg ready_or_not;
reg [1:0] ready_preamble_stage;
initial begin
ready_or_not = 0;
ready_preamble_stage = 0;
count_0s = 0;
count_1s = 0;
count_all = 0;
fsk_out_trigger = 0;
fsk_out = 0;
occurence = 0;
done = 0;
end
always @(posedge sqwv) begin
if (manual == 1) begin
ready_or_not <= 0;
ready_preamble_stage <= 0;
count_0s <= 0;
count_1s <= 0;
count_all <= 0;
fsk_out <= 0;
fsk_out_trigger <= 0;
occurence <= 0;
done <= 0;
end
else if (ready_or_not == 0) begin
if (ready_preamble_stage == 0 && fsk_in == 1) begin
count_1s <= count_1s + 1;
ready_preamble_stage <= 1;
end
else if (ready_preamble_stage == 1) begin
if (fsk_in == 1) begin
count_1s <= count_1s + 1;
if (count_1s == 150) begin
count_0s <= 0;
ready_preamble_stage <= 2;
end
end
else begin
count_1s <= 0;
ready_preamble_stage <= 0;
end
end
else if (ready_preamble_stage == 2) begin
if (fsk_in == 0) begin
count_0s <= count_0s + 1;
if (count_0s == 152) begin
count_1s <= 0;
ready_preamble_stage <= 3;
end
end
else begin
count_0s <= 0;
ready_preamble_stage <= 2;
end
end
else if (ready_preamble_stage == 3) begin
if (fsk_in == 1) begin
count_1s <= count_1s + 1;
if (count_1s == 150) begin
count_1s <= 0; count_0s <= 0; count_all <= 0;
ready_preamble_stage <= 0; ready_or_not <= 1;
end
end
else if (fsk_in == 0 && count_1s == 0);
else begin
count_1s <= 0;
ready_preamble_stage <= 0;
end
end
end
else if (ready_or_not == 1 && count_0secs == 152) begin
ready_or_not <= 0;
ready_preamble_stage <= 0;
count_1s <= 0;
count_0s <= 0;
count_0secs <= 0;
count_all <= 0;
done <= 1;
end
else begin
if (fsk_in == 1) begin
count_1s <= count_1s + 1;
count_0secs <= 0;
count_all <= count_all + 1;
end
else begin
count_0s <= count_0s + 1;
count_0secs <= count_0secs + 1;
count_all <= count_all + 1;
end
if (((count_all == 48-1) && (count_0s > count_1s) && (occurence % 4 != 1)) ||
((count_all == 56-1) && (count_0s > count_1s) && (occurence % 4 == 1))) begin
occurence <= (occurence + 1) % 4;
fsk_out <= 0;
fsk_out_trigger <= ~fsk_out_trigger;
count_0s <= 0;
count_1s <= 0;
count_all <= 0;
end
else if ((count_all == 50-1) && (count_1s > count_0s)) begin
fsk_out <= 1;
fsk_out_trigger <= ~fsk_out_trigger;
count_0s <= 0;
count_1s <= 0;
count_all <= 0;
end
end
end
endmodule | 0 |
6,213 | data/full_repos/permissive/11571685/verilog/getID_4digits.v | 11,571,685 | getID_4digits.v | v | 71 | 83 | [] | [] | [] | [(21, 71)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/11571685/verilog/getID_4digits.v:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n : ... In instance getID_4digits\n ID = digits45[16:1];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/11571685/verilog/getID_4digits.v:67: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n : ... In instance getID_4digits\n iddecimal4[3:0] = temp1-(iddecimal4[7:4]*10);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 6,985 | module | module getID_4digits(
input enable,
input [44:0] digits45,
output reg [15:0] iddecimal4
);
integer ID;
integer temp0, temp1;
always @(posedge enable) begin
ID = digits45[16:1];
if(ID>=9000) iddecimal4[15:12] = 9;
else if(ID>=8000) iddecimal4[15:12] = 8;
else if(ID>=7000) iddecimal4[15:12] = 7;
else if(ID>=6000) iddecimal4[15:12] = 6;
else if(ID>=5000) iddecimal4[15:12] = 5;
else if(ID>=4000) iddecimal4[15:12] = 4;
else if(ID>=3000) iddecimal4[15:12] = 3;
else if(ID>=2000) iddecimal4[15:12] = 2;
else if(ID>=1000) iddecimal4[15:12] = 1;
else iddecimal4[15:12] = 0;
temp0 = ID-(iddecimal4[15:12]*1000);
if(temp0>=900) iddecimal4[11:8] = 9;
else if(temp0>=800) iddecimal4[11:8] = 8;
else if(temp0>=700) iddecimal4[11:8] = 7;
else if(temp0>=600) iddecimal4[11:8] = 6;
else if(temp0>=500) iddecimal4[11:8] = 5;
else if(temp0>=400) iddecimal4[11:8] = 4;
else if(temp0>=300) iddecimal4[11:8] = 3;
else if(temp0>=200) iddecimal4[11:8] = 2;
else if(temp0>=100) iddecimal4[11:8] = 1;
else iddecimal4[11:8] = 0;
temp1 = temp0-(iddecimal4[11:8]*100);
if(temp1>=90) iddecimal4[7:4] = 9;
else if(temp1>=80) iddecimal4[7:4] = 8;
else if(temp1>=70) iddecimal4[7:4] = 7;
else if(temp1>=60) iddecimal4[7:4] = 6;
else if(temp1>=50) iddecimal4[7:4] = 5;
else if(temp1>=40) iddecimal4[7:4] = 4;
else if(temp1>=30) iddecimal4[7:4] = 3;
else if(temp1>=20) iddecimal4[7:4] = 2;
else if(temp1>=10) iddecimal4[7:4] = 1;
else iddecimal4[7:4] = 0;
iddecimal4[3:0] = temp1-(iddecimal4[7:4]*10);
end
endmodule | module getID_4digits(
input enable,
input [44:0] digits45,
output reg [15:0] iddecimal4
); |
integer ID;
integer temp0, temp1;
always @(posedge enable) begin
ID = digits45[16:1];
if(ID>=9000) iddecimal4[15:12] = 9;
else if(ID>=8000) iddecimal4[15:12] = 8;
else if(ID>=7000) iddecimal4[15:12] = 7;
else if(ID>=6000) iddecimal4[15:12] = 6;
else if(ID>=5000) iddecimal4[15:12] = 5;
else if(ID>=4000) iddecimal4[15:12] = 4;
else if(ID>=3000) iddecimal4[15:12] = 3;
else if(ID>=2000) iddecimal4[15:12] = 2;
else if(ID>=1000) iddecimal4[15:12] = 1;
else iddecimal4[15:12] = 0;
temp0 = ID-(iddecimal4[15:12]*1000);
if(temp0>=900) iddecimal4[11:8] = 9;
else if(temp0>=800) iddecimal4[11:8] = 8;
else if(temp0>=700) iddecimal4[11:8] = 7;
else if(temp0>=600) iddecimal4[11:8] = 6;
else if(temp0>=500) iddecimal4[11:8] = 5;
else if(temp0>=400) iddecimal4[11:8] = 4;
else if(temp0>=300) iddecimal4[11:8] = 3;
else if(temp0>=200) iddecimal4[11:8] = 2;
else if(temp0>=100) iddecimal4[11:8] = 1;
else iddecimal4[11:8] = 0;
temp1 = temp0-(iddecimal4[11:8]*100);
if(temp1>=90) iddecimal4[7:4] = 9;
else if(temp1>=80) iddecimal4[7:4] = 8;
else if(temp1>=70) iddecimal4[7:4] = 7;
else if(temp1>=60) iddecimal4[7:4] = 6;
else if(temp1>=50) iddecimal4[7:4] = 5;
else if(temp1>=40) iddecimal4[7:4] = 4;
else if(temp1>=30) iddecimal4[7:4] = 3;
else if(temp1>=20) iddecimal4[7:4] = 2;
else if(temp1>=10) iddecimal4[7:4] = 1;
else iddecimal4[7:4] = 0;
iddecimal4[3:0] = temp1-(iddecimal4[7:4]*10);
end
endmodule | 0 |
6,214 | data/full_repos/permissive/11571685/verilog/mchester_decode.v | 11,571,685 | mchester_decode.v | v | 73 | 83 | [] | [] | [] | [(21, 72)] | null | data/verilator_xmls/0a83df87-7ffb-4017-b787-53e0c13c3103.xml | null | 6,986 | module | module mchester_decode(
input sqwv,
input fsk_out_trigger,
input fsk_out,
input manual,
output reg [44:0] decoded,
output reg done
);
reg prev_trig;
integer bits_rcvd;
integer bits_left;
reg odd_bit, even_bit;
initial begin
bits_rcvd = 0;
bits_left = 44;
decoded = 0;
done = 0;
end
always @(posedge sqwv) begin
if (manual == 1) begin
bits_rcvd <= 0;
bits_left <= 44;
decoded <= 0;
done <= 0;
end
else if (fsk_out_trigger != prev_trig) begin
if (bits_left >= 0) begin
if (bits_rcvd % 2 == 0) begin
even_bit <= fsk_out;
end
else begin
decoded[bits_left] <= even_bit;
bits_left <= bits_left - 1;
end
bits_rcvd <= bits_rcvd + 1;
end
else done <= 1;
prev_trig <= fsk_out_trigger;
end
end
endmodule | module mchester_decode(
input sqwv,
input fsk_out_trigger,
input fsk_out,
input manual,
output reg [44:0] decoded,
output reg done
); |
reg prev_trig;
integer bits_rcvd;
integer bits_left;
reg odd_bit, even_bit;
initial begin
bits_rcvd = 0;
bits_left = 44;
decoded = 0;
done = 0;
end
always @(posedge sqwv) begin
if (manual == 1) begin
bits_rcvd <= 0;
bits_left <= 44;
decoded <= 0;
done <= 0;
end
else if (fsk_out_trigger != prev_trig) begin
if (bits_left >= 0) begin
if (bits_rcvd % 2 == 0) begin
even_bit <= fsk_out;
end
else begin
decoded[bits_left] <= even_bit;
bits_left <= bits_left - 1;
end
bits_rcvd <= bits_rcvd + 1;
end
else done <= 1;
prev_trig <= fsk_out_trigger;
end
end
endmodule | 0 |
6,215 | data/full_repos/permissive/11571685/verilog/rfid.v | 11,571,685 | rfid.v | v | 35 | 103 | [] | [] | [] | [(3, 34)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/11571685/verilog/rfid.v:21: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'iface_done\' generates 1 bits.\n : ... In instance rfid\n led[7:4] = iface_done;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/11571685/verilog/rfid.v:22: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'mchester_done\' generates 1 bits.\n : ... In instance rfid\n led[3:0] = mchester_done;\n ^\n%Error: data/full_repos/permissive/11571685/verilog/rfid.v:25: Cannot find file containing module: \'freq_decode\'\n freq_decode F_DECODE(clk,square_wave,dataIn,manual,freqOut);\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11571685/verilog,data/full_repos/permissive/11571685/freq_decode\n data/full_repos/permissive/11571685/verilog,data/full_repos/permissive/11571685/freq_decode.v\n data/full_repos/permissive/11571685/verilog,data/full_repos/permissive/11571685/freq_decode.sv\n freq_decode\n freq_decode.v\n freq_decode.sv\n obj_dir/freq_decode\n obj_dir/freq_decode.v\n obj_dir/freq_decode.sv\n%Error: data/full_repos/permissive/11571685/verilog/rfid.v:26: Cannot find file containing module: \'fsk_iface_mchester\'\n fsk_iface_mchester FSK_IFACE_MCHESTER(square_wave,freqOut,manual,fsk_out,fsk_out_trigger,iface_done);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11571685/verilog/rfid.v:27: Cannot find file containing module: \'mchester_decode\'\n mchester_decode MCHESTER_DECODE(square_wave,fsk_out_trigger,fsk_out,manual,decoded,mchester_done);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11571685/verilog/rfid.v:28: Cannot find file containing module: \'getID_4digits\'\n getID_4digits GETID_4DIGITS(square_wave,decoded,iddecimal4);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11571685/verilog/rfid.v:30: Cannot find file containing module: \'square_wave\'\n square_wave SQ_WV(clk,square_wave);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/11571685/verilog/rfid.v:32: Cannot find file containing module: \'display_data\'\n display_data DISP_DATA(clk,iddecimal4,seg_an_main,seg_cat_main);\n ^~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 2 warning(s)\n' | 6,987 | module | module rfid(
input clk,
input dataIn,
input manual,
output square_wave,
output freqOut,
output [3:0] seg_an_main,
output [7:0] seg_cat_main,
output reg [7:0] led,
output fsk_out,
output fsk_out_trigger
);
wire iface_done;
wire mchester_done;
wire [44:0] decoded;
wire [15:0] iddecimal4;
always @(posedge square_wave) begin
led[7:4] = iface_done;
led[3:0] = mchester_done;
end
freq_decode F_DECODE(clk,square_wave,dataIn,manual,freqOut);
fsk_iface_mchester FSK_IFACE_MCHESTER(square_wave,freqOut,manual,fsk_out,fsk_out_trigger,iface_done);
mchester_decode MCHESTER_DECODE(square_wave,fsk_out_trigger,fsk_out,manual,decoded,mchester_done);
getID_4digits GETID_4DIGITS(square_wave,decoded,iddecimal4);
square_wave SQ_WV(clk,square_wave);
display_data DISP_DATA(clk,iddecimal4,seg_an_main,seg_cat_main);
endmodule | module rfid(
input clk,
input dataIn,
input manual,
output square_wave,
output freqOut,
output [3:0] seg_an_main,
output [7:0] seg_cat_main,
output reg [7:0] led,
output fsk_out,
output fsk_out_trigger
); |
wire iface_done;
wire mchester_done;
wire [44:0] decoded;
wire [15:0] iddecimal4;
always @(posedge square_wave) begin
led[7:4] = iface_done;
led[3:0] = mchester_done;
end
freq_decode F_DECODE(clk,square_wave,dataIn,manual,freqOut);
fsk_iface_mchester FSK_IFACE_MCHESTER(square_wave,freqOut,manual,fsk_out,fsk_out_trigger,iface_done);
mchester_decode MCHESTER_DECODE(square_wave,fsk_out_trigger,fsk_out,manual,decoded,mchester_done);
getID_4digits GETID_4DIGITS(square_wave,decoded,iddecimal4);
square_wave SQ_WV(clk,square_wave);
display_data DISP_DATA(clk,iddecimal4,seg_an_main,seg_cat_main);
endmodule | 0 |
6,216 | data/full_repos/permissive/11571685/verilog/square_wave.v | 11,571,685 | square_wave.v | v | 21 | 29 | [] | [] | [] | [(3, 20)] | null | data/verilator_xmls/0c22a973-1878-4bfb-ad72-96dfbfb9d243.xml | null | 6,988 | module | module square_wave(
input clk,
output reg sqwv_out
);
integer counter;
initial counter=0;
initial sqwv_out=0;
always @(posedge clk) begin
if(counter==399) begin
sqwv_out<=~sqwv_out;
counter <= 0;
end else begin
counter<=counter+1;
end
end
endmodule | module square_wave(
input clk,
output reg sqwv_out
); |
integer counter;
initial counter=0;
initial sqwv_out=0;
always @(posedge clk) begin
if(counter==399) begin
sqwv_out<=~sqwv_out;
counter <= 0;
end else begin
counter<=counter+1;
end
end
endmodule | 0 |
6,217 | data/full_repos/permissive/11575011/frontier/synthesis/submodules/basic_FuncLED.v | 11,575,011 | basic_FuncLED.v | v | 84 | 83 | [] | [] | [] | [(1, 83)] | null | data/verilator_xmls/2451b2a6-7036-4ad0-9928-21b99935c833.xml | null | 7,002 | module | module basic_FuncLED(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
input [23:0] asi_ledf_data,
input asi_ledf_valid,
output coe_LED_R,
output coe_LED_G,
output coe_LED_B
);
assign avs_ctrl_readdata = {led_asi_en, 7'b0, led_r_data, led_g_data, led_b_data};
assign avs_ctrl_waitrequest = 1'b0;
reg [7:0] led_r_data, led_g_data, led_b_data;
reg [7:0] led_r_cnt, led_g_cnt, led_b_cnt;
reg led_r, led_g, led_b;
reg led_asi_en;
assign coe_LED_R = led_r;
assign coe_LED_G = led_g;
assign coe_LED_B = led_b;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
led_r_data <= 0;
led_g_data <= 0;
led_b_data <= 0;
led_asi_en <= 0;
end
else begin
if(avs_ctrl_write) begin
if(avs_ctrl_byteenable[3]) led_asi_en <= avs_ctrl_writedata[31];
end
if(led_asi_en) begin
if(asi_ledf_valid) begin
led_r_data <= asi_ledf_data[23:16];
led_g_data <= asi_ledf_data[15:8];
led_b_data <= asi_ledf_data[7:0];
end
end
else if(avs_ctrl_write) begin
if(avs_ctrl_byteenable[2]) led_r_data <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) led_g_data <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) led_b_data <= avs_ctrl_writedata[7:0];
end
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
led_r_cnt <= 0;
led_g_cnt <= 0;
led_b_cnt <= 0;
led_r <= 1'b1;
led_g <= 1'b1;
led_b <= 1'b1;
end
else begin
led_r_cnt <= led_r_cnt + 1;
led_g_cnt <= led_g_cnt + 1;
led_b_cnt <= led_b_cnt + 1;
if(led_r_cnt < led_r_data) led_r <= 1'b0; else led_r <= 1'b1;
if(led_g_cnt < led_g_data) led_g <= 1'b0; else led_g <= 1'b1;
if(led_b_cnt < led_b_data) led_b <= 1'b0; else led_b <= 1'b1;
end
end
endmodule | module basic_FuncLED(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
input [23:0] asi_ledf_data,
input asi_ledf_valid,
output coe_LED_R,
output coe_LED_G,
output coe_LED_B
); |
assign avs_ctrl_readdata = {led_asi_en, 7'b0, led_r_data, led_g_data, led_b_data};
assign avs_ctrl_waitrequest = 1'b0;
reg [7:0] led_r_data, led_g_data, led_b_data;
reg [7:0] led_r_cnt, led_g_cnt, led_b_cnt;
reg led_r, led_g, led_b;
reg led_asi_en;
assign coe_LED_R = led_r;
assign coe_LED_G = led_g;
assign coe_LED_B = led_b;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
led_r_data <= 0;
led_g_data <= 0;
led_b_data <= 0;
led_asi_en <= 0;
end
else begin
if(avs_ctrl_write) begin
if(avs_ctrl_byteenable[3]) led_asi_en <= avs_ctrl_writedata[31];
end
if(led_asi_en) begin
if(asi_ledf_valid) begin
led_r_data <= asi_ledf_data[23:16];
led_g_data <= asi_ledf_data[15:8];
led_b_data <= asi_ledf_data[7:0];
end
end
else if(avs_ctrl_write) begin
if(avs_ctrl_byteenable[2]) led_r_data <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) led_g_data <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) led_b_data <= avs_ctrl_writedata[7:0];
end
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
led_r_cnt <= 0;
led_g_cnt <= 0;
led_b_cnt <= 0;
led_r <= 1'b1;
led_g <= 1'b1;
led_b <= 1'b1;
end
else begin
led_r_cnt <= led_r_cnt + 1;
led_g_cnt <= led_g_cnt + 1;
led_b_cnt <= led_b_cnt + 1;
if(led_r_cnt < led_r_data) led_r <= 1'b0; else led_r <= 1'b1;
if(led_g_cnt < led_g_data) led_g <= 1'b0; else led_g <= 1'b1;
if(led_b_cnt < led_b_data) led_b <= 1'b0; else led_b <= 1'b1;
end
end
endmodule | 0 |
6,218 | data/full_repos/permissive/11575011/frontier/synthesis/submodules/basic_ShieldCtrl.v | 11,575,011 | basic_ShieldCtrl.v | v | 67 | 149 | [] | [] | [] | [(1, 66)] | null | data/verilator_xmls/9f57d6de-3f3e-4965-8d9d-2a9732ac02b3.xml | null | 7,003 | module | module basic_ShieldCtrl(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
output ins_OC_irq,
input coe_A_OCN,
output coe_A_PWREN,
output coe_A_HOE,
output coe_A_LOE,
input coe_B_OCN,
output coe_B_PWREN,
output coe_B_HOE,
output coe_B_LOE
);
reg rMODA_PWREN = 1;
reg rMODA_HOE = 0;
reg rMODA_LOE = 0;
reg rMODB_PWREN = 1;
reg rMODB_HOE = 0;
reg rMODB_LOE = 0;
assign avs_ctrl_readdata = {6'b0, ~rMODB_PWREN, ~rMODA_PWREN, 6'b0, rMODB_HOE, rMODA_HOE, 6'b0, rMODB_LOE, rMODA_LOE, 6'b0, ~coe_B_OCN, ~coe_A_OCN};
assign avs_ctrl_waitrequest = 1'b0;
assign ins_OC_irq = ~(coe_A_OCN & coe_B_OCN);
assign coe_A_PWREN = rMODA_PWREN;
assign coe_A_HOE = rMODA_HOE;
assign coe_A_LOE = rMODA_LOE;
assign coe_B_PWREN = rMODB_PWREN;
assign coe_B_HOE = rMODB_HOE;
assign coe_B_LOE = rMODB_LOE;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
rMODA_PWREN <= 1;
rMODA_HOE <= 0;
rMODA_LOE <= 0;
rMODB_PWREN <= 1;
rMODB_HOE <= 0;
rMODB_LOE <= 0;
end
else begin
if(avs_ctrl_write) begin
if(avs_ctrl_byteenable[3]) begin rMODB_PWREN <= ~avs_ctrl_writedata[25]; rMODA_PWREN <= ~avs_ctrl_writedata[24]; end
if(avs_ctrl_byteenable[2]) begin rMODB_HOE <= avs_ctrl_writedata[17]; rMODA_HOE <= avs_ctrl_writedata[16]; end
if(avs_ctrl_byteenable[1]) begin rMODB_LOE <= avs_ctrl_writedata[9]; rMODA_LOE <= avs_ctrl_writedata[8]; end
end
end
end
endmodule | module basic_ShieldCtrl(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
output ins_OC_irq,
input coe_A_OCN,
output coe_A_PWREN,
output coe_A_HOE,
output coe_A_LOE,
input coe_B_OCN,
output coe_B_PWREN,
output coe_B_HOE,
output coe_B_LOE
); |
reg rMODA_PWREN = 1;
reg rMODA_HOE = 0;
reg rMODA_LOE = 0;
reg rMODB_PWREN = 1;
reg rMODB_HOE = 0;
reg rMODB_LOE = 0;
assign avs_ctrl_readdata = {6'b0, ~rMODB_PWREN, ~rMODA_PWREN, 6'b0, rMODB_HOE, rMODA_HOE, 6'b0, rMODB_LOE, rMODA_LOE, 6'b0, ~coe_B_OCN, ~coe_A_OCN};
assign avs_ctrl_waitrequest = 1'b0;
assign ins_OC_irq = ~(coe_A_OCN & coe_B_OCN);
assign coe_A_PWREN = rMODA_PWREN;
assign coe_A_HOE = rMODA_HOE;
assign coe_A_LOE = rMODA_LOE;
assign coe_B_PWREN = rMODB_PWREN;
assign coe_B_HOE = rMODB_HOE;
assign coe_B_LOE = rMODB_LOE;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
rMODA_PWREN <= 1;
rMODA_HOE <= 0;
rMODA_LOE <= 0;
rMODB_PWREN <= 1;
rMODB_HOE <= 0;
rMODB_LOE <= 0;
end
else begin
if(avs_ctrl_write) begin
if(avs_ctrl_byteenable[3]) begin rMODB_PWREN <= ~avs_ctrl_writedata[25]; rMODA_PWREN <= ~avs_ctrl_writedata[24]; end
if(avs_ctrl_byteenable[2]) begin rMODB_HOE <= avs_ctrl_writedata[17]; rMODA_HOE <= avs_ctrl_writedata[16]; end
if(avs_ctrl_byteenable[1]) begin rMODB_LOE <= avs_ctrl_writedata[9]; rMODA_LOE <= avs_ctrl_writedata[8]; end
end
end
end
endmodule | 0 |
6,219 | data/full_repos/permissive/11575011/frontier/synthesis/submodules/basic_SysID.v | 11,575,011 | basic_SysID.v | v | 29 | 51 | [] | [] | [] | [(1, 28)] | null | data/verilator_xmls/747e6ec4-a2d8-4d4b-b67c-dcc109fcbaaa.xml | null | 7,004 | module | module basic_SysID(
input rsi_MRST_reset,
input csi_MCLK_clk,
output [31:0] avs_SysID_readdata,
input [1:0] avs_SysID_address,
input avs_SysID_read,
output avs_SysID_waitrequest
);
reg [31:0] out_data;
assign avs_SysID_readdata = out_data;
assign avs_SysID_waitrequest = 1'b0;
always@(avs_SysID_address)
begin:MUX
case(avs_SysID_address)
0: out_data <= {16'hEA68, 16'h0001};
1: out_data <= {16'h0000, 16'h0000};
2: out_data <= 32'hA5A5A5A5;
3: out_data <= 32'h5A5A5A5A;
endcase
end
endmodule | module basic_SysID(
input rsi_MRST_reset,
input csi_MCLK_clk,
output [31:0] avs_SysID_readdata,
input [1:0] avs_SysID_address,
input avs_SysID_read,
output avs_SysID_waitrequest
); |
reg [31:0] out_data;
assign avs_SysID_readdata = out_data;
assign avs_SysID_waitrequest = 1'b0;
always@(avs_SysID_address)
begin:MUX
case(avs_SysID_address)
0: out_data <= {16'hEA68, 16'h0001};
1: out_data <= {16'h0000, 16'h0000};
2: out_data <= 32'hA5A5A5A5;
3: out_data <= 32'h5A5A5A5A;
endcase
end
endmodule | 0 |
6,220 | data/full_repos/permissive/11575011/frontier/synthesis/submodules/grid_CloseID.v | 11,575,011 | grid_CloseID.v | v | 29 | 51 | [] | [] | [] | [(1, 28)] | null | data/verilator_xmls/1e256b21-fd8b-4aa5-98dc-68a9c01a3590.xml | null | 7,011 | module | module grid_CloseID(
input rsi_MRST_reset,
input csi_MCLK_clk,
output [31:0] avs_CloseID_readdata,
input [1:0] avs_CloseID_address,
input avs_CloseID_read,
output avs_CloseID_waitrequest
);
reg [31:0] out_data;
assign avs_CloseID_readdata = out_data;
assign avs_CloseID_waitrequest = 1'b0;
always@(avs_CloseID_address)
begin:MUX
case(avs_CloseID_address)
0: out_data <= 32'h0;
1: out_data <= 32'hA5A5A5A5;
2: out_data <= 32'h0;
3: out_data <= 32'h5A5A5A5A;
endcase
end
endmodule | module grid_CloseID(
input rsi_MRST_reset,
input csi_MCLK_clk,
output [31:0] avs_CloseID_readdata,
input [1:0] avs_CloseID_address,
input avs_CloseID_read,
output avs_CloseID_waitrequest
); |
reg [31:0] out_data;
assign avs_CloseID_readdata = out_data;
assign avs_CloseID_waitrequest = 1'b0;
always@(avs_CloseID_address)
begin:MUX
case(avs_CloseID_address)
0: out_data <= 32'h0;
1: out_data <= 32'hA5A5A5A5;
2: out_data <= 32'h0;
3: out_data <= 32'h5A5A5A5A;
endcase
end
endmodule | 0 |
6,221 | data/full_repos/permissive/11575011/frontier/synthesis/submodules/grid_PIO26.v | 11,575,011 | grid_PIO26.v | v | 339 | 401 | [] | [] | [] | [(1, 338)] | null | data/verilator_xmls/d6cc29d7-41dd-40b4-91c8-fa025a04efab.xml | null | 7,012 | module | module grid_PIO26(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_gpio_writedata,
output [31:0] avs_gpio_readdata,
input [4:0] avs_gpio_address,
input [3:0] avs_gpio_byteenable,
input avs_gpio_write,
input avs_gpio_read,
output avs_gpio_waitrequest,
output ins_gpint_irq,
inout coe_P0,
inout coe_P1,
inout coe_P2,
inout coe_P3,
inout coe_P4,
inout coe_P5,
inout coe_P6,
inout coe_P7,
inout coe_P8,
inout coe_P9,
inout coe_P10,
inout coe_P11,
inout coe_P12,
inout coe_P13,
inout coe_P14,
inout coe_P15,
inout coe_P16,
inout coe_P17,
inout coe_P18,
inout coe_P19,
inout coe_P20,
inout coe_P21,
inout coe_P22,
inout coe_P23,
inout coe_P24,
inout coe_P25
);
reg [25:0] io_data = 0;
reg [25:0] io_out_en = 0;
reg [25:0] io_int_mask = 0;
reg [25:0] io_int_clear = 0;
reg [25:0] io_int_en = 0;
reg [25:0] io_int_inv = 0;
reg [25:0] io_int_edge = 0;
reg [31:0] read_data = 0;
assign avs_gpio_readdata = read_data;
assign avs_gpio_waitrequest = 1'b0;
assign ins_gpint_irq = (io_int_mask == 0) ? 1'b0 : 1'b1;
assign coe_P0 = (io_out_en[0]) ? io_data[0] : 1'bz;
assign coe_P1 = (io_out_en[1]) ? io_data[1] : 1'bz;
assign coe_P2 = (io_out_en[2]) ? io_data[2] : 1'bz;
assign coe_P3 = (io_out_en[3]) ? io_data[3] : 1'bz;
assign coe_P4 = (io_out_en[4]) ? io_data[4] : 1'bz;
assign coe_P5 = (io_out_en[5]) ? io_data[5] : 1'bz;
assign coe_P6 = (io_out_en[6]) ? io_data[6] : 1'bz;
assign coe_P7 = (io_out_en[7]) ? io_data[7] : 1'bz;
assign coe_P8 = (io_out_en[8]) ? io_data[8] : 1'bz;
assign coe_P9 = (io_out_en[9]) ? io_data[9] : 1'bz;
assign coe_P10 = (io_out_en[10]) ? io_data[10] : 1'bz;
assign coe_P11 = (io_out_en[11]) ? io_data[11] : 1'bz;
assign coe_P12 = (io_out_en[12]) ? io_data[12] : 1'bz;
assign coe_P13 = (io_out_en[13]) ? io_data[13] : 1'bz;
assign coe_P14 = (io_out_en[14]) ? io_data[14] : 1'bz;
assign coe_P15 = (io_out_en[15]) ? io_data[15] : 1'bz;
assign coe_P16 = (io_out_en[16]) ? io_data[16] : 1'bz;
assign coe_P17 = (io_out_en[17]) ? io_data[17] : 1'bz;
assign coe_P18 = (io_out_en[18]) ? io_data[18] : 1'bz;
assign coe_P19 = (io_out_en[19]) ? io_data[19] : 1'bz;
assign coe_P20 = (io_out_en[20]) ? io_data[20] : 1'bz;
assign coe_P21 = (io_out_en[21]) ? io_data[21] : 1'bz;
assign coe_P22 = (io_out_en[22]) ? io_data[22] : 1'bz;
assign coe_P23 = (io_out_en[23]) ? io_data[23] : 1'bz;
assign coe_P24 = (io_out_en[24]) ? io_data[24] : 1'bz;
assign coe_P25 = (io_out_en[25]) ? io_data[25] : 1'bz;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
io_int_mask <= 0;
end
else begin
io_int_mask <= 0;
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else begin
case(avs_gpio_address)
0: read_data <= 128;
1: read_data <= 32'hEA680001;
2: read_data <= {4'b0000, io_data[25:22], io_data[21:14], io_data[13:6], 2'b00, io_data[5:0]};
3: read_data <= {4'b0000, coe_P25, coe_P24, coe_P23, coe_P22, coe_P21, coe_P20, coe_P19, coe_P18, coe_P17, coe_P16, coe_P15, coe_P14, coe_P13, coe_P12, coe_P11, coe_P10, coe_P9, coe_P8, coe_P7, coe_P6, 2'b00, coe_P5, coe_P4, coe_P3, coe_P2, coe_P1, coe_P0};
4: read_data <= {4'b0000, io_out_en[25:22], io_out_en[21:14], io_out_en[13:6], 2'b00, io_out_en[5:0]};
8: read_data <= {4'b0000, io_int_mask[25:22], io_int_mask[21:14], io_int_mask[13:6], 2'b00, io_int_mask[5:0]};
9: read_data <= {4'b0000, io_int_clear[25:22], io_int_clear[21:14], io_int_clear[13:6], 2'b00, io_int_clear[5:0]};
10: read_data <= {4'b0000, io_int_en[25:22], io_int_en[21:14], io_int_en[13:6], 2'b00, io_int_en[5:0]};
11: read_data <= {4'b0000, io_int_inv[25:22], io_int_inv[21:14], io_int_inv[13:6], 2'b00, io_int_inv[5:0]};
12: read_data <= {4'b0000, io_int_edge[25:22], io_int_edge[21:14], io_int_edge[13:6], 2'b00, io_int_edge[5:0]};
16: read_data <= {7'b0, coe_P3, 7'b0, coe_P2, 7'b0, coe_P1, 7'b0, coe_P0};
17: read_data <= {7'b0, coe_P7, 7'b0, coe_P6, 7'b0, coe_P5, 7'b0, coe_P4};
18: read_data <= {7'b0, coe_P11, 7'b0, coe_P10, 7'b0, coe_P9, 7'b0, coe_P8};
19: read_data <= {7'b0, coe_P15, 7'b0, coe_P14, 7'b0, coe_P13, 7'b0, coe_P12};
20: read_data <= {7'b0, coe_P19, 7'b0, coe_P18, 7'b0, coe_P17, 7'b0, coe_P16};
21: read_data <= {7'b0, coe_P23, 7'b0, coe_P22, 7'b0, coe_P21, 7'b0, coe_P20};
22: read_data <= {23'b0, coe_P25, 7'b0, coe_P24};
default: read_data <= 0;
endcase
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
io_data <= 0;
io_out_en <= 0;
io_int_clear <= 0;
io_int_en <= 0;
io_int_inv <= 0;
io_int_edge <= 0;
end
else begin
if(avs_gpio_write) begin
case(avs_gpio_address)
2: begin
if(avs_gpio_byteenable[3]) io_data[25:22] <= avs_gpio_writedata[27:24];
if(avs_gpio_byteenable[2]) io_data[21:14] <= avs_gpio_writedata[23:16];
if(avs_gpio_byteenable[1]) io_data[13:6] <= avs_gpio_writedata[15:8];
if(avs_gpio_byteenable[0]) io_data[5:0] <= avs_gpio_writedata[5:0];
end
4: begin
if(avs_gpio_byteenable[3]) io_out_en[25:22] <= avs_gpio_writedata[27:24];
if(avs_gpio_byteenable[2]) io_out_en[21:14] <= avs_gpio_writedata[23:16];
if(avs_gpio_byteenable[1]) io_out_en[13:6] <= avs_gpio_writedata[15:8];
if(avs_gpio_byteenable[0]) io_out_en[5:0] <= avs_gpio_writedata[5:0];
end
9: begin
if(avs_gpio_byteenable[3]) io_int_clear[25:22] <= avs_gpio_writedata[27:24];
else begin
io_int_clear[25] <= io_int_mask[25];
io_int_clear[24] <= io_int_mask[24];
io_int_clear[23] <= io_int_mask[23];
io_int_clear[22] <= io_int_mask[22];
end
if(avs_gpio_byteenable[2]) io_int_clear[21:14] <= avs_gpio_writedata[23:16];
else begin
io_int_clear[21] <= io_int_mask[21];
io_int_clear[20] <= io_int_mask[20];
io_int_clear[19] <= io_int_mask[19];
io_int_clear[18] <= io_int_mask[18];
io_int_clear[17] <= io_int_mask[17];
io_int_clear[16] <= io_int_mask[16];
io_int_clear[15] <= io_int_mask[15];
io_int_clear[14] <= io_int_mask[14];
end
if(avs_gpio_byteenable[1]) io_int_clear[13:6] <= avs_gpio_writedata[15:8];
else begin
io_int_clear[13] <= io_int_mask[13];
io_int_clear[12] <= io_int_mask[12];
io_int_clear[11] <= io_int_mask[11];
io_int_clear[10] <= io_int_mask[10];
io_int_clear[9] <= io_int_mask[9];
io_int_clear[8] <= io_int_mask[8];
io_int_clear[7] <= io_int_mask[7];
io_int_clear[6] <= io_int_mask[6];
end
if(avs_gpio_byteenable[0]) io_int_clear[5:0] <= avs_gpio_writedata[5:0];
else begin
io_int_clear[5] <= io_int_mask[5];
io_int_clear[4] <= io_int_mask[4];
io_int_clear[3] <= io_int_mask[3];
io_int_clear[2] <= io_int_mask[2];
io_int_clear[1] <= io_int_mask[1];
io_int_clear[0] <= io_int_mask[0];
end
end
10: begin
if(avs_gpio_byteenable[3]) io_int_en[25:22] <= avs_gpio_writedata[27:24];
if(avs_gpio_byteenable[2]) io_int_en[21:14] <= avs_gpio_writedata[23:16];
if(avs_gpio_byteenable[1]) io_int_en[13:6] <= avs_gpio_writedata[15:8];
if(avs_gpio_byteenable[0]) io_int_en[5:0] <= avs_gpio_writedata[5:0];
end
11: begin
if(avs_gpio_byteenable[3]) io_int_inv[25:22] <= avs_gpio_writedata[27:24];
if(avs_gpio_byteenable[2]) io_int_inv[21:14] <= avs_gpio_writedata[23:16];
if(avs_gpio_byteenable[1]) io_int_inv[13:6] <= avs_gpio_writedata[15:8];
if(avs_gpio_byteenable[0]) io_int_inv[5:0] <= avs_gpio_writedata[5:0];
end
12: begin
if(avs_gpio_byteenable[3]) io_int_edge[25:22] <= avs_gpio_writedata[27:24];
if(avs_gpio_byteenable[2]) io_int_edge[21:14] <= avs_gpio_writedata[23:16];
if(avs_gpio_byteenable[1]) io_int_edge[13:6] <= avs_gpio_writedata[15:8];
if(avs_gpio_byteenable[0]) io_int_edge[5:0] <= avs_gpio_writedata[5:0];
end
16: begin
if(avs_gpio_byteenable[3]) io_data[3] <= avs_gpio_writedata[24];
if(avs_gpio_byteenable[2]) io_data[2] <= avs_gpio_writedata[16];
if(avs_gpio_byteenable[1]) io_data[1] <= avs_gpio_writedata[8];
if(avs_gpio_byteenable[0]) io_data[0] <= avs_gpio_writedata[0];
end
17: begin
if(avs_gpio_byteenable[3]) io_data[7] <= avs_gpio_writedata[24];
if(avs_gpio_byteenable[2]) io_data[6] <= avs_gpio_writedata[16];
if(avs_gpio_byteenable[1]) io_data[5] <= avs_gpio_writedata[8];
if(avs_gpio_byteenable[0]) io_data[4] <= avs_gpio_writedata[0];
end
18: begin
if(avs_gpio_byteenable[3]) io_data[11] <= avs_gpio_writedata[24];
if(avs_gpio_byteenable[2]) io_data[10] <= avs_gpio_writedata[16];
if(avs_gpio_byteenable[1]) io_data[9] <= avs_gpio_writedata[8];
if(avs_gpio_byteenable[0]) io_data[8] <= avs_gpio_writedata[0];
end
19: begin
if(avs_gpio_byteenable[3]) io_data[15] <= avs_gpio_writedata[24];
if(avs_gpio_byteenable[2]) io_data[14] <= avs_gpio_writedata[16];
if(avs_gpio_byteenable[1]) io_data[13] <= avs_gpio_writedata[8];
if(avs_gpio_byteenable[0]) io_data[12] <= avs_gpio_writedata[0];
end
20: begin
if(avs_gpio_byteenable[3]) io_data[19] <= avs_gpio_writedata[24];
if(avs_gpio_byteenable[2]) io_data[18] <= avs_gpio_writedata[16];
if(avs_gpio_byteenable[1]) io_data[17] <= avs_gpio_writedata[8];
if(avs_gpio_byteenable[0]) io_data[16] <= avs_gpio_writedata[0];
end
21: begin
if(avs_gpio_byteenable[3]) io_data[23] <= avs_gpio_writedata[24];
if(avs_gpio_byteenable[2]) io_data[22] <= avs_gpio_writedata[16];
if(avs_gpio_byteenable[1]) io_data[21] <= avs_gpio_writedata[8];
if(avs_gpio_byteenable[0]) io_data[20] <= avs_gpio_writedata[0];
end
22: begin
if(avs_gpio_byteenable[1]) io_data[25] <= avs_gpio_writedata[8];
if(avs_gpio_byteenable[0]) io_data[24] <= avs_gpio_writedata[0];
end
default: begin end
endcase
end
end
end
endmodule | module grid_PIO26(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_gpio_writedata,
output [31:0] avs_gpio_readdata,
input [4:0] avs_gpio_address,
input [3:0] avs_gpio_byteenable,
input avs_gpio_write,
input avs_gpio_read,
output avs_gpio_waitrequest,
output ins_gpint_irq,
inout coe_P0,
inout coe_P1,
inout coe_P2,
inout coe_P3,
inout coe_P4,
inout coe_P5,
inout coe_P6,
inout coe_P7,
inout coe_P8,
inout coe_P9,
inout coe_P10,
inout coe_P11,
inout coe_P12,
inout coe_P13,
inout coe_P14,
inout coe_P15,
inout coe_P16,
inout coe_P17,
inout coe_P18,
inout coe_P19,
inout coe_P20,
inout coe_P21,
inout coe_P22,
inout coe_P23,
inout coe_P24,
inout coe_P25
); |
reg [25:0] io_data = 0;
reg [25:0] io_out_en = 0;
reg [25:0] io_int_mask = 0;
reg [25:0] io_int_clear = 0;
reg [25:0] io_int_en = 0;
reg [25:0] io_int_inv = 0;
reg [25:0] io_int_edge = 0;
reg [31:0] read_data = 0;
assign avs_gpio_readdata = read_data;
assign avs_gpio_waitrequest = 1'b0;
assign ins_gpint_irq = (io_int_mask == 0) ? 1'b0 : 1'b1;
assign coe_P0 = (io_out_en[0]) ? io_data[0] : 1'bz;
assign coe_P1 = (io_out_en[1]) ? io_data[1] : 1'bz;
assign coe_P2 = (io_out_en[2]) ? io_data[2] : 1'bz;
assign coe_P3 = (io_out_en[3]) ? io_data[3] : 1'bz;
assign coe_P4 = (io_out_en[4]) ? io_data[4] : 1'bz;
assign coe_P5 = (io_out_en[5]) ? io_data[5] : 1'bz;
assign coe_P6 = (io_out_en[6]) ? io_data[6] : 1'bz;
assign coe_P7 = (io_out_en[7]) ? io_data[7] : 1'bz;
assign coe_P8 = (io_out_en[8]) ? io_data[8] : 1'bz;
assign coe_P9 = (io_out_en[9]) ? io_data[9] : 1'bz;
assign coe_P10 = (io_out_en[10]) ? io_data[10] : 1'bz;
assign coe_P11 = (io_out_en[11]) ? io_data[11] : 1'bz;
assign coe_P12 = (io_out_en[12]) ? io_data[12] : 1'bz;
assign coe_P13 = (io_out_en[13]) ? io_data[13] : 1'bz;
assign coe_P14 = (io_out_en[14]) ? io_data[14] : 1'bz;
assign coe_P15 = (io_out_en[15]) ? io_data[15] : 1'bz;
assign coe_P16 = (io_out_en[16]) ? io_data[16] : 1'bz;
assign coe_P17 = (io_out_en[17]) ? io_data[17] : 1'bz;
assign coe_P18 = (io_out_en[18]) ? io_data[18] : 1'bz;
assign coe_P19 = (io_out_en[19]) ? io_data[19] : 1'bz;
assign coe_P20 = (io_out_en[20]) ? io_data[20] : 1'bz;
assign coe_P21 = (io_out_en[21]) ? io_data[21] : 1'bz;
assign coe_P22 = (io_out_en[22]) ? io_data[22] : 1'bz;
assign coe_P23 = (io_out_en[23]) ? io_data[23] : 1'bz;
assign coe_P24 = (io_out_en[24]) ? io_data[24] : 1'bz;
assign coe_P25 = (io_out_en[25]) ? io_data[25] : 1'bz;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
io_int_mask <= 0;
end
else begin
io_int_mask <= 0;
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else begin
case(avs_gpio_address)
0: read_data <= 128;
1: read_data <= 32'hEA680001;
2: read_data <= {4'b0000, io_data[25:22], io_data[21:14], io_data[13:6], 2'b00, io_data[5:0]};
3: read_data <= {4'b0000, coe_P25, coe_P24, coe_P23, coe_P22, coe_P21, coe_P20, coe_P19, coe_P18, coe_P17, coe_P16, coe_P15, coe_P14, coe_P13, coe_P12, coe_P11, coe_P10, coe_P9, coe_P8, coe_P7, coe_P6, 2'b00, coe_P5, coe_P4, coe_P3, coe_P2, coe_P1, coe_P0};
4: read_data <= {4'b0000, io_out_en[25:22], io_out_en[21:14], io_out_en[13:6], 2'b00, io_out_en[5:0]};
8: read_data <= {4'b0000, io_int_mask[25:22], io_int_mask[21:14], io_int_mask[13:6], 2'b00, io_int_mask[5:0]};
9: read_data <= {4'b0000, io_int_clear[25:22], io_int_clear[21:14], io_int_clear[13:6], 2'b00, io_int_clear[5:0]};
10: read_data <= {4'b0000, io_int_en[25:22], io_int_en[21:14], io_int_en[13:6], 2'b00, io_int_en[5:0]};
11: read_data <= {4'b0000, io_int_inv[25:22], io_int_inv[21:14], io_int_inv[13:6], 2'b00, io_int_inv[5:0]};
12: read_data <= {4'b0000, io_int_edge[25:22], io_int_edge[21:14], io_int_edge[13:6], 2'b00, io_int_edge[5:0]};
16: read_data <= {7'b0, coe_P3, 7'b0, coe_P2, 7'b0, coe_P1, 7'b0, coe_P0};
17: read_data <= {7'b0, coe_P7, 7'b0, coe_P6, 7'b0, coe_P5, 7'b0, coe_P4};
18: read_data <= {7'b0, coe_P11, 7'b0, coe_P10, 7'b0, coe_P9, 7'b0, coe_P8};
19: read_data <= {7'b0, coe_P15, 7'b0, coe_P14, 7'b0, coe_P13, 7'b0, coe_P12};
20: read_data <= {7'b0, coe_P19, 7'b0, coe_P18, 7'b0, coe_P17, 7'b0, coe_P16};
21: read_data <= {7'b0, coe_P23, 7'b0, coe_P22, 7'b0, coe_P21, 7'b0, coe_P20};
22: read_data <= {23'b0, coe_P25, 7'b0, coe_P24};
default: read_data <= 0;
endcase
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
io_data <= 0;
io_out_en <= 0;
io_int_clear <= 0;
io_int_en <= 0;
io_int_inv <= 0;
io_int_edge <= 0;
end
else begin
if(avs_gpio_write) begin
case(avs_gpio_address)
2: begin
if(avs_gpio_byteenable[3]) io_data[25:22] <= avs_gpio_writedata[27:24];
if(avs_gpio_byteenable[2]) io_data[21:14] <= avs_gpio_writedata[23:16];
if(avs_gpio_byteenable[1]) io_data[13:6] <= avs_gpio_writedata[15:8];
if(avs_gpio_byteenable[0]) io_data[5:0] <= avs_gpio_writedata[5:0];
end
4: begin
if(avs_gpio_byteenable[3]) io_out_en[25:22] <= avs_gpio_writedata[27:24];
if(avs_gpio_byteenable[2]) io_out_en[21:14] <= avs_gpio_writedata[23:16];
if(avs_gpio_byteenable[1]) io_out_en[13:6] <= avs_gpio_writedata[15:8];
if(avs_gpio_byteenable[0]) io_out_en[5:0] <= avs_gpio_writedata[5:0];
end
9: begin
if(avs_gpio_byteenable[3]) io_int_clear[25:22] <= avs_gpio_writedata[27:24];
else begin
io_int_clear[25] <= io_int_mask[25];
io_int_clear[24] <= io_int_mask[24];
io_int_clear[23] <= io_int_mask[23];
io_int_clear[22] <= io_int_mask[22];
end
if(avs_gpio_byteenable[2]) io_int_clear[21:14] <= avs_gpio_writedata[23:16];
else begin
io_int_clear[21] <= io_int_mask[21];
io_int_clear[20] <= io_int_mask[20];
io_int_clear[19] <= io_int_mask[19];
io_int_clear[18] <= io_int_mask[18];
io_int_clear[17] <= io_int_mask[17];
io_int_clear[16] <= io_int_mask[16];
io_int_clear[15] <= io_int_mask[15];
io_int_clear[14] <= io_int_mask[14];
end
if(avs_gpio_byteenable[1]) io_int_clear[13:6] <= avs_gpio_writedata[15:8];
else begin
io_int_clear[13] <= io_int_mask[13];
io_int_clear[12] <= io_int_mask[12];
io_int_clear[11] <= io_int_mask[11];
io_int_clear[10] <= io_int_mask[10];
io_int_clear[9] <= io_int_mask[9];
io_int_clear[8] <= io_int_mask[8];
io_int_clear[7] <= io_int_mask[7];
io_int_clear[6] <= io_int_mask[6];
end
if(avs_gpio_byteenable[0]) io_int_clear[5:0] <= avs_gpio_writedata[5:0];
else begin
io_int_clear[5] <= io_int_mask[5];
io_int_clear[4] <= io_int_mask[4];
io_int_clear[3] <= io_int_mask[3];
io_int_clear[2] <= io_int_mask[2];
io_int_clear[1] <= io_int_mask[1];
io_int_clear[0] <= io_int_mask[0];
end
end
10: begin
if(avs_gpio_byteenable[3]) io_int_en[25:22] <= avs_gpio_writedata[27:24];
if(avs_gpio_byteenable[2]) io_int_en[21:14] <= avs_gpio_writedata[23:16];
if(avs_gpio_byteenable[1]) io_int_en[13:6] <= avs_gpio_writedata[15:8];
if(avs_gpio_byteenable[0]) io_int_en[5:0] <= avs_gpio_writedata[5:0];
end
11: begin
if(avs_gpio_byteenable[3]) io_int_inv[25:22] <= avs_gpio_writedata[27:24];
if(avs_gpio_byteenable[2]) io_int_inv[21:14] <= avs_gpio_writedata[23:16];
if(avs_gpio_byteenable[1]) io_int_inv[13:6] <= avs_gpio_writedata[15:8];
if(avs_gpio_byteenable[0]) io_int_inv[5:0] <= avs_gpio_writedata[5:0];
end
12: begin
if(avs_gpio_byteenable[3]) io_int_edge[25:22] <= avs_gpio_writedata[27:24];
if(avs_gpio_byteenable[2]) io_int_edge[21:14] <= avs_gpio_writedata[23:16];
if(avs_gpio_byteenable[1]) io_int_edge[13:6] <= avs_gpio_writedata[15:8];
if(avs_gpio_byteenable[0]) io_int_edge[5:0] <= avs_gpio_writedata[5:0];
end
16: begin
if(avs_gpio_byteenable[3]) io_data[3] <= avs_gpio_writedata[24];
if(avs_gpio_byteenable[2]) io_data[2] <= avs_gpio_writedata[16];
if(avs_gpio_byteenable[1]) io_data[1] <= avs_gpio_writedata[8];
if(avs_gpio_byteenable[0]) io_data[0] <= avs_gpio_writedata[0];
end
17: begin
if(avs_gpio_byteenable[3]) io_data[7] <= avs_gpio_writedata[24];
if(avs_gpio_byteenable[2]) io_data[6] <= avs_gpio_writedata[16];
if(avs_gpio_byteenable[1]) io_data[5] <= avs_gpio_writedata[8];
if(avs_gpio_byteenable[0]) io_data[4] <= avs_gpio_writedata[0];
end
18: begin
if(avs_gpio_byteenable[3]) io_data[11] <= avs_gpio_writedata[24];
if(avs_gpio_byteenable[2]) io_data[10] <= avs_gpio_writedata[16];
if(avs_gpio_byteenable[1]) io_data[9] <= avs_gpio_writedata[8];
if(avs_gpio_byteenable[0]) io_data[8] <= avs_gpio_writedata[0];
end
19: begin
if(avs_gpio_byteenable[3]) io_data[15] <= avs_gpio_writedata[24];
if(avs_gpio_byteenable[2]) io_data[14] <= avs_gpio_writedata[16];
if(avs_gpio_byteenable[1]) io_data[13] <= avs_gpio_writedata[8];
if(avs_gpio_byteenable[0]) io_data[12] <= avs_gpio_writedata[0];
end
20: begin
if(avs_gpio_byteenable[3]) io_data[19] <= avs_gpio_writedata[24];
if(avs_gpio_byteenable[2]) io_data[18] <= avs_gpio_writedata[16];
if(avs_gpio_byteenable[1]) io_data[17] <= avs_gpio_writedata[8];
if(avs_gpio_byteenable[0]) io_data[16] <= avs_gpio_writedata[0];
end
21: begin
if(avs_gpio_byteenable[3]) io_data[23] <= avs_gpio_writedata[24];
if(avs_gpio_byteenable[2]) io_data[22] <= avs_gpio_writedata[16];
if(avs_gpio_byteenable[1]) io_data[21] <= avs_gpio_writedata[8];
if(avs_gpio_byteenable[0]) io_data[20] <= avs_gpio_writedata[0];
end
22: begin
if(avs_gpio_byteenable[1]) io_data[25] <= avs_gpio_writedata[8];
if(avs_gpio_byteenable[0]) io_data[24] <= avs_gpio_writedata[0];
end
default: begin end
endcase
end
end
end
endmodule | 0 |
6,222 | data/full_repos/permissive/11575011/frontier/synthesis/submodules/grid_PWM.v | 11,575,011 | grid_PWM.v | v | 170 | 89 | [] | [] | [] | [(1, 169)] | null | data/verilator_xmls/769f546d-b466-4f6a-a733-a1057f303c75.xml | null | 7,013 | module | module grid_PWM(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_pwm_writedata,
output [31:0] avs_pwm_readdata,
input [2:0] avs_pwm_address,
input [3:0] avs_pwm_byteenable,
input avs_pwm_write,
input avs_pwm_read,
output avs_pwm_waitrequest,
input rsi_PWMRST_reset,
input csi_PWMCLK_clk,
input [31:0] asi_fm_data,
input asi_fm_valid,
output asi_fm_ready,
input [31:0] asi_pm_data,
input asi_pm_valid,
output asi_pm_ready,
output coe_PWMOUT
);
assign avs_pwm_readdata = read_data;
assign avs_pwm_waitrequest = 1'b0;
assign asi_fm_ready = fm_ready;
assign asi_pm_ready = pm_ready;
assign coe_PWMOUT = (out_inv) ? ~pwm_out : pwm_out;
reg [31:0] read_data = 0;
reg out_inv = 0;
reg asi_gate_en = 0;
reg asi_dtyc_en = 0;
reg r_reset = 1;
reg [31:0] r_gate = 0;
reg [31:0] r_dtyc = 0;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else begin
case(avs_pwm_address)
0: read_data <= 32;
1: read_data <= 32'hEA680002;
2: read_data <= {7'b0, asi_gate_en, 7'b0, asi_dtyc_en, 7'b0, out_inv, 7'b0, r_reset};
3: read_data <= r_gate;
4: read_data <= r_dtyc;
default: read_data <= 0;
endcase
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
out_inv <= 0;
asi_gate_en <= 0;
asi_dtyc_en <= 0;
r_reset <= 1;
r_gate <= 0;
r_dtyc <= 0;
end
else begin
if(avs_pwm_write) begin
case(avs_pwm_address)
2: begin
if(avs_pwm_byteenable[3]) asi_gate_en <= avs_pwm_writedata[24];
if(avs_pwm_byteenable[2]) asi_dtyc_en <= avs_pwm_writedata[16];
if(avs_pwm_byteenable[1]) out_inv <= avs_pwm_writedata[8];
if(avs_pwm_byteenable[0]) r_reset <= avs_pwm_writedata[0];
end
3: begin
if(avs_pwm_byteenable[3]) r_gate[31:24] <= avs_pwm_writedata[31:24];
if(avs_pwm_byteenable[2]) r_gate[23:16] <= avs_pwm_writedata[23:16];
if(avs_pwm_byteenable[1]) r_gate[15:8] <= avs_pwm_writedata[15:8];
if(avs_pwm_byteenable[0]) r_gate[7:0] <= avs_pwm_writedata[7:0];
end
4: begin
if(avs_pwm_byteenable[3]) r_dtyc[31:24] <= avs_pwm_writedata[31:24];
if(avs_pwm_byteenable[2]) r_dtyc[23:16] <= avs_pwm_writedata[23:16];
if(avs_pwm_byteenable[1]) r_dtyc[15:8] <= avs_pwm_writedata[15:8];
if(avs_pwm_byteenable[0]) r_dtyc[7:0] <= avs_pwm_writedata[7:0];
end
default: begin end
endcase
end
end
end
wire pwm_reset, pwm_gate_reset, pwm_dtyc_reset;
reg [31:0] pwm_gate = 0;
reg [31:0] pwm_dtyc = 0;
reg [31:0] pwm_cnt = 0;
reg pwm_out = 0;
reg fm_ready = 0;
reg pm_ready = 0;
assign pwm_reset = rsi_PWMRST_reset | r_reset;
assign pwm_gate_reset = (asi_gate_en) ? rsi_PWMRST_reset : r_reset;
assign pwm_dtyc_reset = (asi_dtyc_en) ? rsi_PWMRST_reset : r_reset;
always@(posedge csi_PWMCLK_clk or posedge pwm_reset)
begin
if(pwm_reset) begin
pwm_cnt <= 0;
pwm_out <= 0;
end
else begin
if(pwm_cnt != pwm_gate) pwm_cnt <= pwm_cnt + 1; else pwm_cnt <= 0;
if(pwm_cnt < pwm_dtyc) pwm_out <= 0; else pwm_out <= 1;
end
end
always@(posedge csi_PWMCLK_clk or posedge pwm_gate_reset)
begin
if(pwm_gate_reset) begin
pwm_gate <= 0;
fm_ready <= 0;
end
else begin
if(asi_gate_en) begin
fm_ready <= 1;
if(asi_fm_valid) pwm_gate <= asi_fm_data;
end
else begin
fm_ready <= 0;
pwm_gate <= r_gate;
end
end
end
always@(posedge csi_PWMCLK_clk or posedge pwm_dtyc_reset)
begin
if(pwm_dtyc_reset) begin
pwm_dtyc <= 0;
pm_ready <= 0;
end
else begin
if(asi_dtyc_en) begin
pm_ready <= 1;
if(asi_pm_valid) pwm_dtyc <= asi_pm_data;
end
else begin
pm_ready <= 0;
pwm_dtyc <= r_dtyc;
end
end
end
endmodule | module grid_PWM(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_pwm_writedata,
output [31:0] avs_pwm_readdata,
input [2:0] avs_pwm_address,
input [3:0] avs_pwm_byteenable,
input avs_pwm_write,
input avs_pwm_read,
output avs_pwm_waitrequest,
input rsi_PWMRST_reset,
input csi_PWMCLK_clk,
input [31:0] asi_fm_data,
input asi_fm_valid,
output asi_fm_ready,
input [31:0] asi_pm_data,
input asi_pm_valid,
output asi_pm_ready,
output coe_PWMOUT
); |
assign avs_pwm_readdata = read_data;
assign avs_pwm_waitrequest = 1'b0;
assign asi_fm_ready = fm_ready;
assign asi_pm_ready = pm_ready;
assign coe_PWMOUT = (out_inv) ? ~pwm_out : pwm_out;
reg [31:0] read_data = 0;
reg out_inv = 0;
reg asi_gate_en = 0;
reg asi_dtyc_en = 0;
reg r_reset = 1;
reg [31:0] r_gate = 0;
reg [31:0] r_dtyc = 0;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else begin
case(avs_pwm_address)
0: read_data <= 32;
1: read_data <= 32'hEA680002;
2: read_data <= {7'b0, asi_gate_en, 7'b0, asi_dtyc_en, 7'b0, out_inv, 7'b0, r_reset};
3: read_data <= r_gate;
4: read_data <= r_dtyc;
default: read_data <= 0;
endcase
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
out_inv <= 0;
asi_gate_en <= 0;
asi_dtyc_en <= 0;
r_reset <= 1;
r_gate <= 0;
r_dtyc <= 0;
end
else begin
if(avs_pwm_write) begin
case(avs_pwm_address)
2: begin
if(avs_pwm_byteenable[3]) asi_gate_en <= avs_pwm_writedata[24];
if(avs_pwm_byteenable[2]) asi_dtyc_en <= avs_pwm_writedata[16];
if(avs_pwm_byteenable[1]) out_inv <= avs_pwm_writedata[8];
if(avs_pwm_byteenable[0]) r_reset <= avs_pwm_writedata[0];
end
3: begin
if(avs_pwm_byteenable[3]) r_gate[31:24] <= avs_pwm_writedata[31:24];
if(avs_pwm_byteenable[2]) r_gate[23:16] <= avs_pwm_writedata[23:16];
if(avs_pwm_byteenable[1]) r_gate[15:8] <= avs_pwm_writedata[15:8];
if(avs_pwm_byteenable[0]) r_gate[7:0] <= avs_pwm_writedata[7:0];
end
4: begin
if(avs_pwm_byteenable[3]) r_dtyc[31:24] <= avs_pwm_writedata[31:24];
if(avs_pwm_byteenable[2]) r_dtyc[23:16] <= avs_pwm_writedata[23:16];
if(avs_pwm_byteenable[1]) r_dtyc[15:8] <= avs_pwm_writedata[15:8];
if(avs_pwm_byteenable[0]) r_dtyc[7:0] <= avs_pwm_writedata[7:0];
end
default: begin end
endcase
end
end
end
wire pwm_reset, pwm_gate_reset, pwm_dtyc_reset;
reg [31:0] pwm_gate = 0;
reg [31:0] pwm_dtyc = 0;
reg [31:0] pwm_cnt = 0;
reg pwm_out = 0;
reg fm_ready = 0;
reg pm_ready = 0;
assign pwm_reset = rsi_PWMRST_reset | r_reset;
assign pwm_gate_reset = (asi_gate_en) ? rsi_PWMRST_reset : r_reset;
assign pwm_dtyc_reset = (asi_dtyc_en) ? rsi_PWMRST_reset : r_reset;
always@(posedge csi_PWMCLK_clk or posedge pwm_reset)
begin
if(pwm_reset) begin
pwm_cnt <= 0;
pwm_out <= 0;
end
else begin
if(pwm_cnt != pwm_gate) pwm_cnt <= pwm_cnt + 1; else pwm_cnt <= 0;
if(pwm_cnt < pwm_dtyc) pwm_out <= 0; else pwm_out <= 1;
end
end
always@(posedge csi_PWMCLK_clk or posedge pwm_gate_reset)
begin
if(pwm_gate_reset) begin
pwm_gate <= 0;
fm_ready <= 0;
end
else begin
if(asi_gate_en) begin
fm_ready <= 1;
if(asi_fm_valid) pwm_gate <= asi_fm_data;
end
else begin
fm_ready <= 0;
pwm_gate <= r_gate;
end
end
end
always@(posedge csi_PWMCLK_clk or posedge pwm_dtyc_reset)
begin
if(pwm_dtyc_reset) begin
pwm_dtyc <= 0;
pm_ready <= 0;
end
else begin
if(asi_dtyc_en) begin
pm_ready <= 1;
if(asi_pm_valid) pwm_dtyc <= asi_pm_data;
end
else begin
pm_ready <= 0;
pwm_dtyc <= r_dtyc;
end
end
end
endmodule | 0 |
6,223 | data/full_repos/permissive/11575011/frontier/synthesis/submodules/test_LEDState.v | 11,575,011 | test_LEDState.v | v | 140 | 56 | [] | [] | [] | [(1, 139)] | null | data/verilator_xmls/3ae7540f-fdb5-4a23-8b8f-bbae81c67a5e.xml | null | 7,015 | module | module test_LEDState(
input rsi_MRST_reset,
input csi_MCLK_clk,
output [23:0] aso_fled0_data,
output aso_fled0_valid,
output [23:0] aso_fled1_data,
output aso_fled1_valid,
output [23:0] aso_fled2_data,
output aso_fled2_valid,
output [23:0] aso_fled3_data,
output aso_fled3_valid
);
assign aso_fled0_valid = 1;
assign aso_fled0_data = {r_cnt, g_cnt, b_cnt};
assign aso_fled1_valid = 1;
assign aso_fled1_data = {g_cnt, b_cnt, r_cnt};
assign aso_fled2_valid = 1;
assign aso_fled2_data = {b_cnt, r_cnt, g_cnt};
assign aso_fled3_valid = 1;
assign aso_fled3_data = {g_cnt, r_cnt, b_cnt};
reg [5:0] state;
reg [7:0] r_cnt, g_cnt, b_cnt;
reg [18:0] delay_cnt;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
state <= 0;
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
end
else begin
case(state)
0: begin
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) r_cnt <= r_cnt + 1;
if(r_cnt == 255) state <= 1;
end
1: begin
delay_cnt <= 0;
state <= 2;
end
2: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) r_cnt <= r_cnt - 1;
if(r_cnt == 0) state <= 3;
end
3: begin
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
state <= 4;
end
4: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) g_cnt <= g_cnt + 1;
if(g_cnt == 255) state <= 5;
end
5: begin
delay_cnt <= 0;
state <= 6;
end
6: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) g_cnt <= g_cnt - 1;
if(g_cnt == 0) state <= 7;
end
7: begin
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
state <= 8;
end
8: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) b_cnt <= b_cnt + 1;
if(b_cnt == 255) state <= 9;
end
9: begin
delay_cnt <= 0;
state <= 10;
end
10: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) b_cnt <= b_cnt - 1;
if(b_cnt == 0) state <= 11;
end
11: begin
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
state <= 0;
end
default: begin
state <= 0;
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
end
endcase
end
end
endmodule | module test_LEDState(
input rsi_MRST_reset,
input csi_MCLK_clk,
output [23:0] aso_fled0_data,
output aso_fled0_valid,
output [23:0] aso_fled1_data,
output aso_fled1_valid,
output [23:0] aso_fled2_data,
output aso_fled2_valid,
output [23:0] aso_fled3_data,
output aso_fled3_valid
); |
assign aso_fled0_valid = 1;
assign aso_fled0_data = {r_cnt, g_cnt, b_cnt};
assign aso_fled1_valid = 1;
assign aso_fled1_data = {g_cnt, b_cnt, r_cnt};
assign aso_fled2_valid = 1;
assign aso_fled2_data = {b_cnt, r_cnt, g_cnt};
assign aso_fled3_valid = 1;
assign aso_fled3_data = {g_cnt, r_cnt, b_cnt};
reg [5:0] state;
reg [7:0] r_cnt, g_cnt, b_cnt;
reg [18:0] delay_cnt;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
state <= 0;
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
end
else begin
case(state)
0: begin
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) r_cnt <= r_cnt + 1;
if(r_cnt == 255) state <= 1;
end
1: begin
delay_cnt <= 0;
state <= 2;
end
2: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) r_cnt <= r_cnt - 1;
if(r_cnt == 0) state <= 3;
end
3: begin
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
state <= 4;
end
4: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) g_cnt <= g_cnt + 1;
if(g_cnt == 255) state <= 5;
end
5: begin
delay_cnt <= 0;
state <= 6;
end
6: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) g_cnt <= g_cnt - 1;
if(g_cnt == 0) state <= 7;
end
7: begin
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
state <= 8;
end
8: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) b_cnt <= b_cnt + 1;
if(b_cnt == 255) state <= 9;
end
9: begin
delay_cnt <= 0;
state <= 10;
end
10: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) b_cnt <= b_cnt - 1;
if(b_cnt == 0) state <= 11;
end
11: begin
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
state <= 0;
end
default: begin
state <= 0;
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
end
endcase
end
end
endmodule | 0 |
6,224 | data/full_repos/permissive/11575011/qsys_root/grid_AD7490.v | 11,575,011 | grid_AD7490.v | v | 236 | 107 | [] | [] | [] | null | line:40: before: "," | data/verilator_xmls/3cc366a0-ca0a-4d0c-93b8-c63a09e56f7c.xml | null | 7,019 | module | module grid_AD7490(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_address,
input [3:0] avs_ctrl_byteenable,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
input csi_ADCCLK_clk,
output [3:0] aso_adc_channel,
output [15:0] aso_adc_data,
output aso_adc_valid,
input aso_adc_ready,
output coe_DIN,
input coe_DOUT,
output coe_SCLK,
output coe_CSN
);
assign avs_ctrl_readdata = read_data;
assign avs_ctrl_waitrequest = 1'b0;
assign aso_adc_channel = adc_aso_ch;
assign aso_adc_data = {adc_aso_data, 4'b0};
assign aso_adc_valid = adc_aso_valid;
assign coe_DIN = spi_din;
assign spi_dout = coe_DOUT;
assign coe_SCLK = spi_clk;
assign coe_CSN = spi_cs;
reg [31:0] read_data = 0;
reg spi_din = 0, spi_cs = 1, spi_clk = 1;
wire spi_dout;
reg [7:0] state = 0;
reg [7:0] delay = 0;
reg adc_range = 0;
reg adc_coding = 1;
reg adc_reset = 1;
reg [7:0] cnv_delay = 255;
reg [11:0] adc_ch[0:15] = 0;
reg [3:0] adc_addr = 0;
reg [3:0] adc_aso_ch = 0;
reg [11:0] adc_aso_data = 0;
reg adc_aso_valid = 0;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else begin
case(avs_ctrl_address)
0: read_data <= 64;
1: read_data <= 32'hEA680003;
2: read_data <= {4'b0, adc_addr, 7'b0, adc_range, 7'b0, adc_coding, 7'b0, adc_reset};
3: read_data <= {24'b0, cnv_delay};
8: read_data <= {adc_ch[1], 4'b0, adc_ch[0], 4'b0};
9: read_data <= {adc_ch[3], 4'b0, adc_ch[2], 4'b0};
10: read_data <= {adc_ch[5], 4'b0, adc_ch[4], 4'b0};
11: read_data <= {adc_ch[7], 4'b0, adc_ch[6], 4'b0};
12: read_data <= {adc_ch[9], 4'b0, adc_ch[8], 4'b0};
13: read_data <= {adc_ch[11], 4'b0, adc_ch[10], 4'b0};
14: read_data <= {adc_ch[13], 4'b0, adc_ch[12], 4'b0};
15: read_data <= {adc_ch[15], 4'b0, adc_ch[14], 4'b0};
default: read_data <= 0;
endcase
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
adc_range <= 0;
adc_coding <= 1;
adc_reset <= 1;
cnv_delay <= 255;
end
else begin
if(avs_ctrl_write) begin
case(avs_ctrl_address)
2: begin
if(avs_ctrl_byteenable[2]) adc_range <= avs_ctrl_writedata[16];
if(avs_ctrl_byteenable[1]) adc_coding <= avs_ctrl_writedata[8];
if(avs_ctrl_byteenable[0]) adc_reset <= avs_ctrl_writedata[0];
end
3: begin
if(avs_ctrl_byteenable[0]) cnv_delay <= avs_ctrl_writedata[7:0];
end
default: begin end
endcase
end
end
end
wire rWRITE = 1;
wire rSEQ = 0;
wire rPM1 = 1;
wire rPM0 = 1;
wire rSHADOW = 0;
wire rWEAKTRI = 0;
always@(posedge csi_ADCCLK_clk or posedge adc_reset)
begin
if(adc_reset) begin
adc_ch[0] <= 0;
adc_ch[1] <= 0;
adc_ch[2] <= 0;
adc_ch[3] <= 0;
adc_ch[4] <= 0;
adc_ch[5] <= 0;
adc_ch[6] <= 0;
adc_ch[7] <= 0;
adc_ch[8] <= 0;
adc_ch[9] <= 0;
adc_ch[10] <= 0;
adc_ch[11] <= 0;
adc_ch[12] <= 0;
adc_ch[13] <= 0;
adc_ch[14] <= 0;
adc_ch[15] <= 0;
adc_addr <= 0;
adc_aso_ch <= 0;
adc_aso_data <= 0;
adc_aso_valid <= 0;
spi_din <= 0;
spi_cs <= 1;
spi_clk <= 1;
state <= 0;
delay <= 0;
end
else begin
case(state)
0: begin state <= state + 1; spi_clk <= 1; spi_din <= rWRITE; spi_cs <= 1; delay <= 0; end
1: begin if(delay > cnv_delay) begin delay <= 0; state <= state + 1; end else delay <= delay + 1; end
2: begin state <= state + 1; spi_clk <= 1; spi_din <= rWRITE; spi_cs <= 0; end
3: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[3] <= spi_dout; end
4: begin state <= state + 1; spi_clk <= 1; spi_din <= rSEQ; end
5: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[2] <= spi_dout; end
6: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[3]; end
7: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[1] <= spi_dout; end
8: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[2]; end
9: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[0] <= spi_dout; end
10: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[1]; end
11: begin state <= state + 1; spi_clk <= 0; adc_aso_data[11] <= spi_dout; end
12: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[0]; end
13: begin state <= state + 1; spi_clk <= 0; adc_aso_data[10] <= spi_dout; end
14: begin state <= state + 1; spi_clk <= 1; spi_din <= rPM1; end
15: begin state <= state + 1; spi_clk <= 0; adc_aso_data[9] <= spi_dout; end
16: begin state <= state + 1; spi_clk <= 1; spi_din <= rPM0; end
17: begin state <= state + 1; spi_clk <= 0; adc_aso_data[8] <= spi_dout; end
18: begin state <= state + 1; spi_clk <= 1; spi_din <= rSHADOW; end
19: begin state <= state + 1; spi_clk <= 0; adc_aso_data[7] <= spi_dout; end
20: begin state <= state + 1; spi_clk <= 1; spi_din <= rWEAKTRI; end
21: begin state <= state + 1; spi_clk <= 0; adc_aso_data[6] <= spi_dout; end
22: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_range; end
23: begin state <= state + 1; spi_clk <= 0; adc_aso_data[5] <= spi_dout; end
24: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_coding; end
25: begin state <= state + 1; spi_clk <= 0; adc_aso_data[4] <= spi_dout; end
26: begin state <= state + 1; spi_clk <= 1; spi_din <= 0; end
27: begin state <= state + 1; spi_clk <= 0; adc_aso_data[3] <= spi_dout; end
28: begin state <= state + 1; spi_clk <= 1; end
29: begin state <= state + 1; spi_clk <= 0; adc_aso_data[2] <= spi_dout; end
30: begin state <= state + 1; spi_clk <= 1; end
31: begin state <= state + 1; spi_clk <= 0; adc_aso_data[1] <= spi_dout; end
32: begin state <= state + 1; spi_clk <= 1; end
33: begin state <= state + 1; spi_clk <= 0; adc_aso_data[0] <= spi_dout; end
34: begin state <= state + 1; spi_clk <= 1; adc_ch[adc_aso_ch] <= adc_aso_data; adc_aso_valid <= 1; end
35: begin state <= 0; spi_cs <= 1; adc_aso_valid <= 0; adc_addr <= adc_addr + 1; end
default: begin
adc_ch[0] <= 0;
adc_ch[1] <= 0;
adc_ch[2] <= 0;
adc_ch[3] <= 0;
adc_ch[4] <= 0;
adc_ch[5] <= 0;
adc_ch[6] <= 0;
adc_ch[7] <= 0;
adc_ch[8] <= 0;
adc_ch[9] <= 0;
adc_ch[10] <= 0;
adc_ch[11] <= 0;
adc_ch[12] <= 0;
adc_ch[13] <= 0;
adc_ch[14] <= 0;
adc_ch[15] <= 0;
adc_addr <= 0;
adc_aso_ch <= 0;
adc_aso_data <= 0;
adc_aso_valid <= 0;
spi_din <= 0;
spi_cs <= 1;
spi_clk <= 1;
state <= 0;
delay <= 0;
end
endcase
end
end
endmodule | module grid_AD7490(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_address,
input [3:0] avs_ctrl_byteenable,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
input csi_ADCCLK_clk,
output [3:0] aso_adc_channel,
output [15:0] aso_adc_data,
output aso_adc_valid,
input aso_adc_ready,
output coe_DIN,
input coe_DOUT,
output coe_SCLK,
output coe_CSN
); |
assign avs_ctrl_readdata = read_data;
assign avs_ctrl_waitrequest = 1'b0;
assign aso_adc_channel = adc_aso_ch;
assign aso_adc_data = {adc_aso_data, 4'b0};
assign aso_adc_valid = adc_aso_valid;
assign coe_DIN = spi_din;
assign spi_dout = coe_DOUT;
assign coe_SCLK = spi_clk;
assign coe_CSN = spi_cs;
reg [31:0] read_data = 0;
reg spi_din = 0, spi_cs = 1, spi_clk = 1;
wire spi_dout;
reg [7:0] state = 0;
reg [7:0] delay = 0;
reg adc_range = 0;
reg adc_coding = 1;
reg adc_reset = 1;
reg [7:0] cnv_delay = 255;
reg [11:0] adc_ch[0:15] = 0;
reg [3:0] adc_addr = 0;
reg [3:0] adc_aso_ch = 0;
reg [11:0] adc_aso_data = 0;
reg adc_aso_valid = 0;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else begin
case(avs_ctrl_address)
0: read_data <= 64;
1: read_data <= 32'hEA680003;
2: read_data <= {4'b0, adc_addr, 7'b0, adc_range, 7'b0, adc_coding, 7'b0, adc_reset};
3: read_data <= {24'b0, cnv_delay};
8: read_data <= {adc_ch[1], 4'b0, adc_ch[0], 4'b0};
9: read_data <= {adc_ch[3], 4'b0, adc_ch[2], 4'b0};
10: read_data <= {adc_ch[5], 4'b0, adc_ch[4], 4'b0};
11: read_data <= {adc_ch[7], 4'b0, adc_ch[6], 4'b0};
12: read_data <= {adc_ch[9], 4'b0, adc_ch[8], 4'b0};
13: read_data <= {adc_ch[11], 4'b0, adc_ch[10], 4'b0};
14: read_data <= {adc_ch[13], 4'b0, adc_ch[12], 4'b0};
15: read_data <= {adc_ch[15], 4'b0, adc_ch[14], 4'b0};
default: read_data <= 0;
endcase
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
adc_range <= 0;
adc_coding <= 1;
adc_reset <= 1;
cnv_delay <= 255;
end
else begin
if(avs_ctrl_write) begin
case(avs_ctrl_address)
2: begin
if(avs_ctrl_byteenable[2]) adc_range <= avs_ctrl_writedata[16];
if(avs_ctrl_byteenable[1]) adc_coding <= avs_ctrl_writedata[8];
if(avs_ctrl_byteenable[0]) adc_reset <= avs_ctrl_writedata[0];
end
3: begin
if(avs_ctrl_byteenable[0]) cnv_delay <= avs_ctrl_writedata[7:0];
end
default: begin end
endcase
end
end
end
wire rWRITE = 1;
wire rSEQ = 0;
wire rPM1 = 1;
wire rPM0 = 1;
wire rSHADOW = 0;
wire rWEAKTRI = 0;
always@(posedge csi_ADCCLK_clk or posedge adc_reset)
begin
if(adc_reset) begin
adc_ch[0] <= 0;
adc_ch[1] <= 0;
adc_ch[2] <= 0;
adc_ch[3] <= 0;
adc_ch[4] <= 0;
adc_ch[5] <= 0;
adc_ch[6] <= 0;
adc_ch[7] <= 0;
adc_ch[8] <= 0;
adc_ch[9] <= 0;
adc_ch[10] <= 0;
adc_ch[11] <= 0;
adc_ch[12] <= 0;
adc_ch[13] <= 0;
adc_ch[14] <= 0;
adc_ch[15] <= 0;
adc_addr <= 0;
adc_aso_ch <= 0;
adc_aso_data <= 0;
adc_aso_valid <= 0;
spi_din <= 0;
spi_cs <= 1;
spi_clk <= 1;
state <= 0;
delay <= 0;
end
else begin
case(state)
0: begin state <= state + 1; spi_clk <= 1; spi_din <= rWRITE; spi_cs <= 1; delay <= 0; end
1: begin if(delay > cnv_delay) begin delay <= 0; state <= state + 1; end else delay <= delay + 1; end
2: begin state <= state + 1; spi_clk <= 1; spi_din <= rWRITE; spi_cs <= 0; end
3: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[3] <= spi_dout; end
4: begin state <= state + 1; spi_clk <= 1; spi_din <= rSEQ; end
5: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[2] <= spi_dout; end
6: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[3]; end
7: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[1] <= spi_dout; end
8: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[2]; end
9: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[0] <= spi_dout; end
10: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[1]; end
11: begin state <= state + 1; spi_clk <= 0; adc_aso_data[11] <= spi_dout; end
12: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[0]; end
13: begin state <= state + 1; spi_clk <= 0; adc_aso_data[10] <= spi_dout; end
14: begin state <= state + 1; spi_clk <= 1; spi_din <= rPM1; end
15: begin state <= state + 1; spi_clk <= 0; adc_aso_data[9] <= spi_dout; end
16: begin state <= state + 1; spi_clk <= 1; spi_din <= rPM0; end
17: begin state <= state + 1; spi_clk <= 0; adc_aso_data[8] <= spi_dout; end
18: begin state <= state + 1; spi_clk <= 1; spi_din <= rSHADOW; end
19: begin state <= state + 1; spi_clk <= 0; adc_aso_data[7] <= spi_dout; end
20: begin state <= state + 1; spi_clk <= 1; spi_din <= rWEAKTRI; end
21: begin state <= state + 1; spi_clk <= 0; adc_aso_data[6] <= spi_dout; end
22: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_range; end
23: begin state <= state + 1; spi_clk <= 0; adc_aso_data[5] <= spi_dout; end
24: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_coding; end
25: begin state <= state + 1; spi_clk <= 0; adc_aso_data[4] <= spi_dout; end
26: begin state <= state + 1; spi_clk <= 1; spi_din <= 0; end
27: begin state <= state + 1; spi_clk <= 0; adc_aso_data[3] <= spi_dout; end
28: begin state <= state + 1; spi_clk <= 1; end
29: begin state <= state + 1; spi_clk <= 0; adc_aso_data[2] <= spi_dout; end
30: begin state <= state + 1; spi_clk <= 1; end
31: begin state <= state + 1; spi_clk <= 0; adc_aso_data[1] <= spi_dout; end
32: begin state <= state + 1; spi_clk <= 1; end
33: begin state <= state + 1; spi_clk <= 0; adc_aso_data[0] <= spi_dout; end
34: begin state <= state + 1; spi_clk <= 1; adc_ch[adc_aso_ch] <= adc_aso_data; adc_aso_valid <= 1; end
35: begin state <= 0; spi_cs <= 1; adc_aso_valid <= 0; adc_addr <= adc_addr + 1; end
default: begin
adc_ch[0] <= 0;
adc_ch[1] <= 0;
adc_ch[2] <= 0;
adc_ch[3] <= 0;
adc_ch[4] <= 0;
adc_ch[5] <= 0;
adc_ch[6] <= 0;
adc_ch[7] <= 0;
adc_ch[8] <= 0;
adc_ch[9] <= 0;
adc_ch[10] <= 0;
adc_ch[11] <= 0;
adc_ch[12] <= 0;
adc_ch[13] <= 0;
adc_ch[14] <= 0;
adc_ch[15] <= 0;
adc_addr <= 0;
adc_aso_ch <= 0;
adc_aso_data <= 0;
adc_aso_valid <= 0;
spi_din <= 0;
spi_cs <= 1;
spi_clk <= 1;
state <= 0;
delay <= 0;
end
endcase
end
end
endmodule | 0 |
6,225 | data/full_repos/permissive/11575011/qsys_root/test_RegRW32.v | 11,575,011 | test_RegRW32.v | v | 34 | 77 | [] | [] | [] | [(1, 33)] | null | data/verilator_xmls/7af76a76-da3e-4b61-b944-dfeb7e67e4ef.xml | null | 7,025 | module | module test_RegRW32(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_test_writedata,
output [31:0] avs_test_readdata,
input [3:0] avs_test_byteenable,
input avs_test_write,
input avs_test_read,
output avs_test_waitrequest
);
reg [31:0] test_data = 0;
assign avs_test_readdata = test_data;
assign avs_test_waitrequest = 1'b0;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) test_data <= 0;
else begin
if(avs_test_write) begin
if(avs_test_byteenable[3]) test_data[31:24] <= avs_test_writedata[31:24];
if(avs_test_byteenable[2]) test_data[23:16] <= avs_test_writedata[23:16];
if(avs_test_byteenable[1]) test_data[15:8] <= avs_test_writedata[15:8];
if(avs_test_byteenable[0]) test_data[7:0] <= avs_test_writedata[7:0];
end
end
end
endmodule | module test_RegRW32(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_test_writedata,
output [31:0] avs_test_readdata,
input [3:0] avs_test_byteenable,
input avs_test_write,
input avs_test_read,
output avs_test_waitrequest
); |
reg [31:0] test_data = 0;
assign avs_test_readdata = test_data;
assign avs_test_waitrequest = 1'b0;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) test_data <= 0;
else begin
if(avs_test_write) begin
if(avs_test_byteenable[3]) test_data[31:24] <= avs_test_writedata[31:24];
if(avs_test_byteenable[2]) test_data[23:16] <= avs_test_writedata[23:16];
if(avs_test_byteenable[1]) test_data[15:8] <= avs_test_writedata[15:8];
if(avs_test_byteenable[0]) test_data[7:0] <= avs_test_writedata[7:0];
end
end
end
endmodule | 0 |
6,226 | data/full_repos/permissive/11575011/qsys_root/test_RegWaitRW32.v | 11,575,011 | test_RegWaitRW32.v | v | 70 | 110 | [] | [] | [] | [(1, 69)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/11575011/qsys_root/test_RegWaitRW32.v:41: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'avs_test_address\' generates 6 bits.\n : ... In instance test_RegWaitRW32\n out_data <= r_data + avs_test_address;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 7,026 | module | module test_RegWaitRW32(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_test_writedata,
output [31:0] avs_test_readdata,
input [5:0] avs_test_address,
input [3:0] avs_test_byteenable,
input avs_test_write,
input avs_test_read,
output avs_test_readdatavalid,
output avs_test_waitrequest
);
reg [31:0] out_data = 0;
reg [31:0] r_data = 0;
reg r_wait = 0;
reg [3:0] r_wait_cnt = 0;
reg r_valid = 0;
assign avs_test_readdata = out_data;
assign avs_test_waitrequest = r_wait;
assign avs_test_readdatavalid = r_valid;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
out_data <= 0;
r_data <= 0;
r_wait <= 0;
r_wait_cnt <= 0;
r_valid <= 0;
end
else begin
if(r_wait_cnt == 15) r_valid <= 1; else r_valid <= 0;
if(((r_wait_cnt > 0)&&(r_wait_cnt < 15))||(avs_test_read)||(avs_test_write)) r_wait <= 1; else r_wait <= 0;
if(avs_test_read) begin
r_wait_cnt <= r_wait_cnt + 1;
out_data <= r_data + avs_test_address;
end
else if(avs_test_write) begin
r_wait_cnt <= r_wait_cnt + 1;
case(avs_test_address)
0: begin
if(avs_test_byteenable[3]) r_data[31:24] <= avs_test_writedata[31:24];
if(avs_test_byteenable[2]) r_data[23:16] <= avs_test_writedata[23:16];
if(avs_test_byteenable[1]) r_data[15:8] <= avs_test_writedata[15:8];
if(avs_test_byteenable[0]) r_data[7:0] <= avs_test_writedata[7:0];
end
1: begin
if(avs_test_byteenable[3]) r_data[31:24] <= ~avs_test_writedata[31:24];
if(avs_test_byteenable[2]) r_data[23:16] <= ~avs_test_writedata[23:16];
if(avs_test_byteenable[1]) r_data[15:8] <= ~avs_test_writedata[15:8];
if(avs_test_byteenable[0]) r_data[7:0] <= ~avs_test_writedata[7:0];
end
default: begin
r_data <= 0;
end
endcase
end
else begin
if(r_wait_cnt > 0) r_wait_cnt <= r_wait_cnt + 1; else r_wait_cnt <= 0;
end
end
end
endmodule | module test_RegWaitRW32(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_test_writedata,
output [31:0] avs_test_readdata,
input [5:0] avs_test_address,
input [3:0] avs_test_byteenable,
input avs_test_write,
input avs_test_read,
output avs_test_readdatavalid,
output avs_test_waitrequest
); |
reg [31:0] out_data = 0;
reg [31:0] r_data = 0;
reg r_wait = 0;
reg [3:0] r_wait_cnt = 0;
reg r_valid = 0;
assign avs_test_readdata = out_data;
assign avs_test_waitrequest = r_wait;
assign avs_test_readdatavalid = r_valid;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
out_data <= 0;
r_data <= 0;
r_wait <= 0;
r_wait_cnt <= 0;
r_valid <= 0;
end
else begin
if(r_wait_cnt == 15) r_valid <= 1; else r_valid <= 0;
if(((r_wait_cnt > 0)&&(r_wait_cnt < 15))||(avs_test_read)||(avs_test_write)) r_wait <= 1; else r_wait <= 0;
if(avs_test_read) begin
r_wait_cnt <= r_wait_cnt + 1;
out_data <= r_data + avs_test_address;
end
else if(avs_test_write) begin
r_wait_cnt <= r_wait_cnt + 1;
case(avs_test_address)
0: begin
if(avs_test_byteenable[3]) r_data[31:24] <= avs_test_writedata[31:24];
if(avs_test_byteenable[2]) r_data[23:16] <= avs_test_writedata[23:16];
if(avs_test_byteenable[1]) r_data[15:8] <= avs_test_writedata[15:8];
if(avs_test_byteenable[0]) r_data[7:0] <= avs_test_writedata[7:0];
end
1: begin
if(avs_test_byteenable[3]) r_data[31:24] <= ~avs_test_writedata[31:24];
if(avs_test_byteenable[2]) r_data[23:16] <= ~avs_test_writedata[23:16];
if(avs_test_byteenable[1]) r_data[15:8] <= ~avs_test_writedata[15:8];
if(avs_test_byteenable[0]) r_data[7:0] <= ~avs_test_writedata[7:0];
end
default: begin
r_data <= 0;
end
endcase
end
else begin
if(r_wait_cnt > 0) r_wait_cnt <= r_wait_cnt + 1; else r_wait_cnt <= 0;
end
end
end
endmodule | 0 |
6,228 | data/full_repos/permissive/115771353/rtl/dpram/dpram.v | 115,771,353 | dpram.v | v | 48 | 62 | [] | [] | [] | [(6, 47)] | null | data/verilator_xmls/3fc3c751-677e-4786-a3eb-cd97a75aaa89.xml | null | 7,028 | module | module dpram #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 8,
parameter RAM_DEPTH = (1 << ADDR_WIDTH)
)
(
input wire clk,
input wire [ADDR_WIDTH-1:0] WrAddress,
input wire [DATA_WIDTH-1:0] Data,
input wire WE,
input wire [ADDR_WIDTH-1:0] RdAddress,
output wire [DATA_WIDTH-1:0] Q
);
reg [DATA_WIDTH-1:0] data_1_out;
reg [DATA_WIDTH-1:0] Q_out;
reg [DATA_WIDTH-1:0] mem [RAM_DEPTH-1:0];
always @ (posedge clk)
begin : MEM_WRITE
if ( WE ) begin
mem[WrAddress] = Data;
end
end
assign Q = data_1_out;
always @ (posedge clk)
begin : MEM_READ_1
data_1_out = mem[RdAddress];
end
endmodule | module dpram #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 8,
parameter RAM_DEPTH = (1 << ADDR_WIDTH)
)
(
input wire clk,
input wire [ADDR_WIDTH-1:0] WrAddress,
input wire [DATA_WIDTH-1:0] Data,
input wire WE,
input wire [ADDR_WIDTH-1:0] RdAddress,
output wire [DATA_WIDTH-1:0] Q
); |
reg [DATA_WIDTH-1:0] data_1_out;
reg [DATA_WIDTH-1:0] Q_out;
reg [DATA_WIDTH-1:0] mem [RAM_DEPTH-1:0];
always @ (posedge clk)
begin : MEM_WRITE
if ( WE ) begin
mem[WrAddress] = Data;
end
end
assign Q = data_1_out;
always @ (posedge clk)
begin : MEM_READ_1
data_1_out = mem[RdAddress];
end
endmodule | 9 |
6,229 | data/full_repos/permissive/115771353/rtl/hworb/arp_reply_rx.v | 115,771,353 | arp_reply_rx.v | v | 261 | 139 | [] | [] | [] | [(26, 260)] | null | data/verilator_xmls/7d34879a-698f-4c48-b6dd-c696a5975447.xml | null | 7,029 | module | module arp_reply_rx #(
parameter [31:0] DEVICE_IP = 32'h0a0105dd,
parameter [47:0] DEVICE_MAC = 48'h001999cf956f
)
(
input clk,
input reset_n,
input newFrame,
input frameType,
input newFrameByte,
input [7:0] frameData,
input frameValid,
input ARPSendAvail,
input [31:0] requestIP,
output reg genARPRep,
output reg [31:0] genARPIP,
output reg [47:0] lookupMAC,
output reg validEntry
);
parameter [1:0]
RX_ARP_IDLE = 2'd0,
RX_ARP_HANDLEARP = 2'd1,
RX_ARP_OPERATE = 2'd2,
RX_ARP_CHECKVALID = 2'd3;
reg [1:0] arp_rep_rx_cur_fsm;
reg [1:0] arp_rep_rx_nxt_fsm;
reg [4:0] cnt;
reg incCnt;
reg rstCnt;
reg latchFrameData;
reg [7:0] frameDataLatch;
reg shiftSourceIPIn;
reg [31:0] sourceIP;
reg shiftSourceMACIn;
reg [47:0] sourceMAC;
reg ARPOperation;
reg determineOperation;
reg updateARPTable;
reg [31:0] ARPEntryIP;
reg [47:0] ARPEntryMAC;
reg [31:0] ARPEntryIPOld;
reg [47:0] ARPEntryMACOld;
reg doGenARPRep;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
arp_rep_rx_cur_fsm <= RX_ARP_IDLE;
ARPEntryIP <= 32'b0;
ARPEntryMAC <= 48'b0;
ARPEntryIPOld <= 32'b0;
ARPEntryMACOld <= 48'b0;
genARPRep <= 1'b0;
ARPOperation <= 1'b0;
cnt <= 5'b0;
end
else begin
arp_rep_rx_cur_fsm <= arp_rep_rx_nxt_fsm;
if (incCnt)
cnt <= cnt + 1;
else if (rstCnt)
cnt <= 5'b0;
if (latchFrameData)
frameDataLatch <= frameData;
if (determineOperation)
ARPOperation <= frameDataLatch[0];
if (shiftSourceIPIn)
sourceIP <= {sourceIP[23:0], frameDataLatch};
if (shiftSourceMACIn)
sourceMAC <= {sourceMAC[39:0], frameDataLatch};
if (updateARPTable) begin
if (ARPEntryIP == sourceIP)
ARPEntryMAC <= sourceMAC;
else begin
ARPEntryIPOld <= ARPEntryIP;
ARPEntryMACOld <= ARPEntryMAC;
ARPEntryIP <= sourceIP;
ARPEntryMAC <= sourceMAC;
end
end
if (doGenARPRep) begin
genARPRep <= 1'b1;
genARPIP <= sourceIP;
end
else if (ARPSendAvail)
genARPRep <= 1'b0;
end
end
always @(arp_rep_rx_cur_fsm or sourceIP or ARPOperation or cnt or newFrame or frameType or newFrameByte or frameDataLatch or frameValid)
begin
rstCnt <= 1'b0;
incCnt <= 1'b0;
shiftSourceIPIn <= 1'b0;
determineOperation <= 1'b0;
updateARPTable <= 1'b0;
shiftSourceIPIn <= 1'b0;
shiftSourceMACIn <= 1'b0;
latchFrameData <= 1'b0;
doGenARPRep <= 1'b0;
case (arp_rep_rx_cur_fsm)
RX_ARP_IDLE:
begin
if (newFrame && !frameType) begin
arp_rep_rx_nxt_fsm <= RX_ARP_HANDLEARP;
rstCnt <= 1'b1;
end
else
arp_rep_rx_nxt_fsm <= RX_ARP_IDLE;
end
RX_ARP_HANDLEARP:
begin
if (!newFrameByte)
arp_rep_rx_nxt_fsm <= RX_ARP_HANDLEARP;
else begin
arp_rep_rx_nxt_fsm <= RX_ARP_OPERATE;
latchFrameData <= 1'b1;
end
end
RX_ARP_OPERATE:
begin
incCnt <= 1'b1;
if (
((cnt == 5'b0 || cnt == 5'b00011 || cnt == 5'b00110) && frameDataLatch != 8'd0 ) ||
(cnt == 5'b00001 && frameDataLatch != 8'd1) ||
(cnt == 5'b00010 && frameDataLatch != 8'd8) ||
(cnt == 5'b00100 && frameDataLatch != 8'd6) ||
(cnt == 5'b00101 && frameDataLatch != 8'd4) ||
(cnt == 5'b00111 && frameDataLatch != 8'd1 && frameDataLatch != 8'd2 ) ||
(cnt == 5'b11000 && frameDataLatch != DEVICE_IP[31:24]) ||
(cnt == 5'b11001 && frameDataLatch != DEVICE_IP[23:16]) ||
(cnt == 5'b11010 && frameDataLatch != DEVICE_IP[15:8]) ||
(cnt == 5'b11011 && frameDataLatch != DEVICE_IP[7:0])
)
arp_rep_rx_nxt_fsm <= RX_ARP_IDLE;
else if (cnt == 5'b11011)
arp_rep_rx_nxt_fsm <= RX_ARP_CHECKVALID;
else
arp_rep_rx_nxt_fsm <= RX_ARP_HANDLEARP;
if (cnt == 5'b00111)
determineOperation <= 1'b1;
if (cnt == 5'b01000 || cnt == 5'b01001 || cnt == 5'b01010 || cnt == 5'b01011 || cnt == 5'b01100 || cnt == 5'b01101)
shiftSourceMACIn <= 1'b1;
if (cnt == 5'b01110 || cnt == 5'b01111 || cnt == 5'b10000 || cnt == 5'b10001)
shiftSourceIPIn <= 1'b1;
end
RX_ARP_CHECKVALID:
begin
if (!frameValid)
arp_rep_rx_nxt_fsm <= RX_ARP_CHECKVALID;
else begin
if (ARPOperation)
doGenARPRep <= 1'b1;
arp_rep_rx_nxt_fsm <= RX_ARP_IDLE;
updateARPTable <= 1'b1;
end
end
default:
begin
arp_rep_rx_nxt_fsm <= RX_ARP_IDLE;
end
endcase
end
always @(requestIP or ARPEntryIP or ARPEntryMAC or ARPEntryIPOld or ARPEntryMACOld)
begin
if (requestIP == ARPEntryIP) begin
validEntry <= 1'b1;
lookupMAC <= ARPEntryMAC;
end
else if (requestIP == ARPEntryIPOld) begin
validEntry <= 1'b1;
lookupMAC <= ARPEntryMACOld;
end
else begin
validEntry <= 1'b0;
lookupMAC <= 48'b1;
end
end
endmodule | module arp_reply_rx #(
parameter [31:0] DEVICE_IP = 32'h0a0105dd,
parameter [47:0] DEVICE_MAC = 48'h001999cf956f
)
(
input clk,
input reset_n,
input newFrame,
input frameType,
input newFrameByte,
input [7:0] frameData,
input frameValid,
input ARPSendAvail,
input [31:0] requestIP,
output reg genARPRep,
output reg [31:0] genARPIP,
output reg [47:0] lookupMAC,
output reg validEntry
); |
parameter [1:0]
RX_ARP_IDLE = 2'd0,
RX_ARP_HANDLEARP = 2'd1,
RX_ARP_OPERATE = 2'd2,
RX_ARP_CHECKVALID = 2'd3;
reg [1:0] arp_rep_rx_cur_fsm;
reg [1:0] arp_rep_rx_nxt_fsm;
reg [4:0] cnt;
reg incCnt;
reg rstCnt;
reg latchFrameData;
reg [7:0] frameDataLatch;
reg shiftSourceIPIn;
reg [31:0] sourceIP;
reg shiftSourceMACIn;
reg [47:0] sourceMAC;
reg ARPOperation;
reg determineOperation;
reg updateARPTable;
reg [31:0] ARPEntryIP;
reg [47:0] ARPEntryMAC;
reg [31:0] ARPEntryIPOld;
reg [47:0] ARPEntryMACOld;
reg doGenARPRep;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
arp_rep_rx_cur_fsm <= RX_ARP_IDLE;
ARPEntryIP <= 32'b0;
ARPEntryMAC <= 48'b0;
ARPEntryIPOld <= 32'b0;
ARPEntryMACOld <= 48'b0;
genARPRep <= 1'b0;
ARPOperation <= 1'b0;
cnt <= 5'b0;
end
else begin
arp_rep_rx_cur_fsm <= arp_rep_rx_nxt_fsm;
if (incCnt)
cnt <= cnt + 1;
else if (rstCnt)
cnt <= 5'b0;
if (latchFrameData)
frameDataLatch <= frameData;
if (determineOperation)
ARPOperation <= frameDataLatch[0];
if (shiftSourceIPIn)
sourceIP <= {sourceIP[23:0], frameDataLatch};
if (shiftSourceMACIn)
sourceMAC <= {sourceMAC[39:0], frameDataLatch};
if (updateARPTable) begin
if (ARPEntryIP == sourceIP)
ARPEntryMAC <= sourceMAC;
else begin
ARPEntryIPOld <= ARPEntryIP;
ARPEntryMACOld <= ARPEntryMAC;
ARPEntryIP <= sourceIP;
ARPEntryMAC <= sourceMAC;
end
end
if (doGenARPRep) begin
genARPRep <= 1'b1;
genARPIP <= sourceIP;
end
else if (ARPSendAvail)
genARPRep <= 1'b0;
end
end
always @(arp_rep_rx_cur_fsm or sourceIP or ARPOperation or cnt or newFrame or frameType or newFrameByte or frameDataLatch or frameValid)
begin
rstCnt <= 1'b0;
incCnt <= 1'b0;
shiftSourceIPIn <= 1'b0;
determineOperation <= 1'b0;
updateARPTable <= 1'b0;
shiftSourceIPIn <= 1'b0;
shiftSourceMACIn <= 1'b0;
latchFrameData <= 1'b0;
doGenARPRep <= 1'b0;
case (arp_rep_rx_cur_fsm)
RX_ARP_IDLE:
begin
if (newFrame && !frameType) begin
arp_rep_rx_nxt_fsm <= RX_ARP_HANDLEARP;
rstCnt <= 1'b1;
end
else
arp_rep_rx_nxt_fsm <= RX_ARP_IDLE;
end
RX_ARP_HANDLEARP:
begin
if (!newFrameByte)
arp_rep_rx_nxt_fsm <= RX_ARP_HANDLEARP;
else begin
arp_rep_rx_nxt_fsm <= RX_ARP_OPERATE;
latchFrameData <= 1'b1;
end
end
RX_ARP_OPERATE:
begin
incCnt <= 1'b1;
if (
((cnt == 5'b0 || cnt == 5'b00011 || cnt == 5'b00110) && frameDataLatch != 8'd0 ) ||
(cnt == 5'b00001 && frameDataLatch != 8'd1) ||
(cnt == 5'b00010 && frameDataLatch != 8'd8) ||
(cnt == 5'b00100 && frameDataLatch != 8'd6) ||
(cnt == 5'b00101 && frameDataLatch != 8'd4) ||
(cnt == 5'b00111 && frameDataLatch != 8'd1 && frameDataLatch != 8'd2 ) ||
(cnt == 5'b11000 && frameDataLatch != DEVICE_IP[31:24]) ||
(cnt == 5'b11001 && frameDataLatch != DEVICE_IP[23:16]) ||
(cnt == 5'b11010 && frameDataLatch != DEVICE_IP[15:8]) ||
(cnt == 5'b11011 && frameDataLatch != DEVICE_IP[7:0])
)
arp_rep_rx_nxt_fsm <= RX_ARP_IDLE;
else if (cnt == 5'b11011)
arp_rep_rx_nxt_fsm <= RX_ARP_CHECKVALID;
else
arp_rep_rx_nxt_fsm <= RX_ARP_HANDLEARP;
if (cnt == 5'b00111)
determineOperation <= 1'b1;
if (cnt == 5'b01000 || cnt == 5'b01001 || cnt == 5'b01010 || cnt == 5'b01011 || cnt == 5'b01100 || cnt == 5'b01101)
shiftSourceMACIn <= 1'b1;
if (cnt == 5'b01110 || cnt == 5'b01111 || cnt == 5'b10000 || cnt == 5'b10001)
shiftSourceIPIn <= 1'b1;
end
RX_ARP_CHECKVALID:
begin
if (!frameValid)
arp_rep_rx_nxt_fsm <= RX_ARP_CHECKVALID;
else begin
if (ARPOperation)
doGenARPRep <= 1'b1;
arp_rep_rx_nxt_fsm <= RX_ARP_IDLE;
updateARPTable <= 1'b1;
end
end
default:
begin
arp_rep_rx_nxt_fsm <= RX_ARP_IDLE;
end
endcase
end
always @(requestIP or ARPEntryIP or ARPEntryMAC or ARPEntryIPOld or ARPEntryMACOld)
begin
if (requestIP == ARPEntryIP) begin
validEntry <= 1'b1;
lookupMAC <= ARPEntryMAC;
end
else if (requestIP == ARPEntryIPOld) begin
validEntry <= 1'b1;
lookupMAC <= ARPEntryMACOld;
end
else begin
validEntry <= 1'b0;
lookupMAC <= 48'b1;
end
end
endmodule | 9 |
6,231 | data/full_repos/permissive/115771353/rtl/hworb/eth_rx_fifo_wraper.v | 115,771,353 | eth_rx_fifo_wraper.v | v | 203 | 96 | [] | [] | [] | [(20, 202)] | null | null | 1: b"%Error: data/full_repos/permissive/115771353/rtl/hworb/eth_rx_fifo_wraper.v:168: Cannot find file containing module: 'async_fifo'\n async_fifo #(16, 10)\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115771353/rtl/hworb,data/full_repos/permissive/115771353/async_fifo\n data/full_repos/permissive/115771353/rtl/hworb,data/full_repos/permissive/115771353/async_fifo.v\n data/full_repos/permissive/115771353/rtl/hworb,data/full_repos/permissive/115771353/async_fifo.sv\n async_fifo\n async_fifo.v\n async_fifo.sv\n obj_dir/async_fifo\n obj_dir/async_fifo.v\n obj_dir/async_fifo.sv\n%Error: data/full_repos/permissive/115771353/rtl/hworb/eth_rx_fifo_wraper.v:186: Cannot find file containing module: 'async_fifo'\n async_fifo #(8, 10)\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 7,031 | module | module eth_rx_fifo_wraper (
input clk_i,
input reset_n,
input clk_en,
input rx_len_fifo_read,
input rx_data_fifo_read,
input rx_write,
input rx_eof,
input [7:0] rx_dbout,
input rxmac_clk,
output wire [15:0] rx_len_fifo_data,
output wire [7:0] rx_data_fifo_data,
output wire rx_data_fifo_full,
output wire rx_data_fifo_empty,
output wire rx_len_fifo_full,
output wire rx_len_fifo_empty
);
reg rx_write_1d;
reg rx_eof_1d;
reg [7:0] rx_dbout_1d;
reg [12:0] byte_cnt;
reg [1:0] eth_rxfifo_ctrl_fsm;
reg mac_wr_rx_data_fifo;
reg mac_wr_rx_len_fifo;
reg [7:0] rx_fifo_data;
wire [15:0] rx_len_fifo_data_minus1;
wire byte_enb_sel;
wire [15:0] rx_fifo_len;
wire mac_wr_rx_data_fifo_x;
wire mac_wr_rx_len_fifo_x;
parameter [1:0]
RX_FSM_IDLE = 2'd0,
RX_FSM_WR_DATA = 2'd1,
RX_FSM_WR_LEN = 2'd2;
assign byte_enb_sel = ( (rx_write_1d == 1'b1) && byte_cnt < 13'd2047 ) ? 1:0;
assign rx_fifo_len[15:0] = {3'b000, byte_cnt[12:0]};
assign rx_len_fifo_data = (rx_len_fifo_data_minus1 + 1);
assign mac_wr_rx_data_fifo_x = mac_wr_rx_data_fifo & clk_en;
assign mac_wr_rx_len_fifo_x = mac_wr_rx_len_fifo & clk_en;
always @(posedge rxmac_clk or negedge reset_n)
begin
if (!reset_n) begin
rx_write_1d <= 1'b0;
rx_eof_1d <= 1'b0;
rx_dbout_1d <= 8'h00;
mac_wr_rx_data_fifo <= 1'b0;
end
else if (clk_en) begin
rx_write_1d <= rx_write;
rx_eof_1d <= rx_eof;
rx_dbout_1d <= rx_dbout;
mac_wr_rx_data_fifo <= (rx_eof_1d | byte_enb_sel);
end
end
always @(posedge rxmac_clk or negedge reset_n)
begin
if (!reset_n) begin
rx_fifo_data[7:0] <= 8'd0;
end
else if (clk_en) begin
rx_fifo_data[7:0] <= rx_dbout_1d[7:0];
end
end
always @(posedge rxmac_clk or negedge reset_n)
begin
if (!reset_n) begin
eth_rxfifo_ctrl_fsm <= RX_FSM_IDLE;
byte_cnt <= 13'd0;
mac_wr_rx_len_fifo <= 1'b0;
end
else if (clk_en) begin
mac_wr_rx_len_fifo <= 1'b0;
case (eth_rxfifo_ctrl_fsm)
RX_FSM_IDLE:
begin
if (rx_write == 1'b1) begin
byte_cnt <= 13'd0;
eth_rxfifo_ctrl_fsm <= RX_FSM_WR_DATA;
end
end
RX_FSM_WR_DATA:
begin
if (rx_eof_1d == 1'b1) begin
eth_rxfifo_ctrl_fsm <= RX_FSM_WR_LEN;
end
else begin
if (rx_write == 1'b1 && byte_cnt < 13'd2047) begin
byte_cnt <= byte_cnt + 1;
end
eth_rxfifo_ctrl_fsm <= RX_FSM_WR_DATA;
end
end
RX_FSM_WR_LEN:
begin
eth_rxfifo_ctrl_fsm <= RX_FSM_IDLE;
mac_wr_rx_len_fifo <= 1'b1;
end
default:
begin
eth_rxfifo_ctrl_fsm <= RX_FSM_IDLE;
byte_cnt <= 13'd0;
mac_wr_rx_len_fifo <= 1'b0;
end
endcase
end
end
async_fifo #(16, 10)
u_rx_len_fifo
(
.wrst_n (reset_n),
.wclk (rxmac_clk),
.winc (mac_wr_rx_len_fifo_x),
.wdata (rx_fifo_len[15:0]),
.wfull (rx_len_fifo_full),
.rrst_n (reset_n),
.rclk (clk_i),
.rinc (rx_len_fifo_read),
.rdata (rx_len_fifo_data_minus1[15:0]),
.rempty (rx_len_fifo_empty)
);
async_fifo #(8, 10)
u_rx_data_fifo
(
.wrst_n (reset_n),
.wclk (rxmac_clk),
.winc (mac_wr_rx_data_fifo_x),
.wdata (rx_fifo_data[7:0]),
.wfull (rx_data_fifo_full),
.rrst_n (reset_n),
.rclk (clk_i),
.rinc (rx_data_fifo_read),
.rdata (rx_data_fifo_data[7:0]),
.rempty (rx_data_fifo_empty)
);
endmodule | module eth_rx_fifo_wraper (
input clk_i,
input reset_n,
input clk_en,
input rx_len_fifo_read,
input rx_data_fifo_read,
input rx_write,
input rx_eof,
input [7:0] rx_dbout,
input rxmac_clk,
output wire [15:0] rx_len_fifo_data,
output wire [7:0] rx_data_fifo_data,
output wire rx_data_fifo_full,
output wire rx_data_fifo_empty,
output wire rx_len_fifo_full,
output wire rx_len_fifo_empty
); |
reg rx_write_1d;
reg rx_eof_1d;
reg [7:0] rx_dbout_1d;
reg [12:0] byte_cnt;
reg [1:0] eth_rxfifo_ctrl_fsm;
reg mac_wr_rx_data_fifo;
reg mac_wr_rx_len_fifo;
reg [7:0] rx_fifo_data;
wire [15:0] rx_len_fifo_data_minus1;
wire byte_enb_sel;
wire [15:0] rx_fifo_len;
wire mac_wr_rx_data_fifo_x;
wire mac_wr_rx_len_fifo_x;
parameter [1:0]
RX_FSM_IDLE = 2'd0,
RX_FSM_WR_DATA = 2'd1,
RX_FSM_WR_LEN = 2'd2;
assign byte_enb_sel = ( (rx_write_1d == 1'b1) && byte_cnt < 13'd2047 ) ? 1:0;
assign rx_fifo_len[15:0] = {3'b000, byte_cnt[12:0]};
assign rx_len_fifo_data = (rx_len_fifo_data_minus1 + 1);
assign mac_wr_rx_data_fifo_x = mac_wr_rx_data_fifo & clk_en;
assign mac_wr_rx_len_fifo_x = mac_wr_rx_len_fifo & clk_en;
always @(posedge rxmac_clk or negedge reset_n)
begin
if (!reset_n) begin
rx_write_1d <= 1'b0;
rx_eof_1d <= 1'b0;
rx_dbout_1d <= 8'h00;
mac_wr_rx_data_fifo <= 1'b0;
end
else if (clk_en) begin
rx_write_1d <= rx_write;
rx_eof_1d <= rx_eof;
rx_dbout_1d <= rx_dbout;
mac_wr_rx_data_fifo <= (rx_eof_1d | byte_enb_sel);
end
end
always @(posedge rxmac_clk or negedge reset_n)
begin
if (!reset_n) begin
rx_fifo_data[7:0] <= 8'd0;
end
else if (clk_en) begin
rx_fifo_data[7:0] <= rx_dbout_1d[7:0];
end
end
always @(posedge rxmac_clk or negedge reset_n)
begin
if (!reset_n) begin
eth_rxfifo_ctrl_fsm <= RX_FSM_IDLE;
byte_cnt <= 13'd0;
mac_wr_rx_len_fifo <= 1'b0;
end
else if (clk_en) begin
mac_wr_rx_len_fifo <= 1'b0;
case (eth_rxfifo_ctrl_fsm)
RX_FSM_IDLE:
begin
if (rx_write == 1'b1) begin
byte_cnt <= 13'd0;
eth_rxfifo_ctrl_fsm <= RX_FSM_WR_DATA;
end
end
RX_FSM_WR_DATA:
begin
if (rx_eof_1d == 1'b1) begin
eth_rxfifo_ctrl_fsm <= RX_FSM_WR_LEN;
end
else begin
if (rx_write == 1'b1 && byte_cnt < 13'd2047) begin
byte_cnt <= byte_cnt + 1;
end
eth_rxfifo_ctrl_fsm <= RX_FSM_WR_DATA;
end
end
RX_FSM_WR_LEN:
begin
eth_rxfifo_ctrl_fsm <= RX_FSM_IDLE;
mac_wr_rx_len_fifo <= 1'b1;
end
default:
begin
eth_rxfifo_ctrl_fsm <= RX_FSM_IDLE;
byte_cnt <= 13'd0;
mac_wr_rx_len_fifo <= 1'b0;
end
endcase
end
end
async_fifo #(16, 10)
u_rx_len_fifo
(
.wrst_n (reset_n),
.wclk (rxmac_clk),
.winc (mac_wr_rx_len_fifo_x),
.wdata (rx_fifo_len[15:0]),
.wfull (rx_len_fifo_full),
.rrst_n (reset_n),
.rclk (clk_i),
.rinc (rx_len_fifo_read),
.rdata (rx_len_fifo_data_minus1[15:0]),
.rempty (rx_len_fifo_empty)
);
async_fifo #(8, 10)
u_rx_data_fifo
(
.wrst_n (reset_n),
.wclk (rxmac_clk),
.winc (mac_wr_rx_data_fifo_x),
.wdata (rx_fifo_data[7:0]),
.wfull (rx_data_fifo_full),
.rrst_n (reset_n),
.rclk (clk_i),
.rinc (rx_data_fifo_read),
.rdata (rx_data_fifo_data[7:0]),
.rempty (rx_data_fifo_empty)
);
endmodule | 9 |
6,232 | data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v | 115,771,353 | eth_tx_fifo_wraper.v | v | 232 | 96 | [] | [] | [] | [(20, 231)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:131: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_CTRL_FSM_IDLE\' generates 2 bits.\n : ... In instance eth_tx_fifo_wraper\n eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:152: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_CTRL_FSM_DATA_AVAIL\' generates 2 bits.\n : ... In instance eth_tx_fifo_wraper\n eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_DATA_AVAIL;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:160: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_CTRL_FSM_PULL_PKT\' generates 2 bits.\n : ... In instance eth_tx_fifo_wraper\n eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_PULL_PKT;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:168: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_CTRL_FSM_WAIT3\' generates 2 bits.\n : ... In instance eth_tx_fifo_wraper\n eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_WAIT3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:171: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_CTRL_FSM_PULL_PKT\' generates 2 bits.\n : ... In instance eth_tx_fifo_wraper\n eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_PULL_PKT;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:179: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_CTRL_FSM_IDLE\' generates 2 bits.\n : ... In instance eth_tx_fifo_wraper\n eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:184: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_CTRL_FSM_IDLE\' generates 2 bits.\n : ... In instance eth_tx_fifo_wraper\n eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:143: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'TX_CTRL_FSM_IDLE\' generates 2 bits.\n : ... In instance eth_tx_fifo_wraper\n case (eth_txfifo_ctrl_fsm)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:143: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'TX_CTRL_FSM_DATA_AVAIL\' generates 2 bits.\n : ... In instance eth_tx_fifo_wraper\n case (eth_txfifo_ctrl_fsm)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:143: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'TX_CTRL_FSM_PULL_PKT\' generates 2 bits.\n : ... In instance eth_tx_fifo_wraper\n case (eth_txfifo_ctrl_fsm)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:143: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'TX_CTRL_FSM_WAIT3\' generates 2 bits.\n : ... In instance eth_tx_fifo_wraper\n case (eth_txfifo_ctrl_fsm)\n ^~~~\n%Error: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:197: Cannot find file containing module: \'async_fifo\'\n async_fifo #(16, 10)\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115771353/rtl/hworb,data/full_repos/permissive/115771353/async_fifo\n data/full_repos/permissive/115771353/rtl/hworb,data/full_repos/permissive/115771353/async_fifo.v\n data/full_repos/permissive/115771353/rtl/hworb,data/full_repos/permissive/115771353/async_fifo.sv\n async_fifo\n async_fifo.v\n async_fifo.sv\n obj_dir/async_fifo\n obj_dir/async_fifo.v\n obj_dir/async_fifo.sv\n%Error: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:215: Cannot find file containing module: \'async_fifo\'\n async_fifo #(16, 10)\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 11 warning(s)\n' | 7,032 | module | module eth_tx_fifo_wraper
(
input clk_i,
input reset_n,
input clk_en,
input [15:0] tx_len_fifo_data,
input [7:0] tx_data_fifo_data,
input tx_len_fifo_write,
input tx_data_fifo_write,
input tx_macread,
input txmac_clk,
output reg tx_fifoempty,
output wire [7:0] tx_fifodata,
output reg tx_fifoeof
);
reg [15:0] tx_len_fifo_data_1d;
reg [7:0] tx_data_fifo_data_1d;
reg tx_len_fifo_write_1d;
reg tx_data_fifo_write_1d;
reg mac_rd_tx_len_fifo;
reg [15:0] byte_cnt;
reg load_cnt;
reg [2:0] eth_txfifo_ctrl_fsm;
wire mac_rd_tx_data_fifo;
wire [7:0] tx_fifo_data;
wire [15:0] tx_fifo_len;
reg [15:0] tx_fifo_len_minus1;
wire mac_rd_tx_len_fifo_x;
wire mac_rd_tx_data_fifo_x;
wire tx_len_fifo_empty;
wire tx_data_fifo_full;
wire tx_data_fifo_empty;
parameter [1:0]
TX_CTRL_FSM_IDLE = 2'd0,
TX_CTRL_FSM_DATA_AVAIL = 2'd1,
TX_CTRL_FSM_PULL_PKT = 2'd2,
TX_CTRL_FSM_WAIT3 = 2'd3;
assign mac_rd_tx_data_fifo = tx_macread;
assign mac_rd_tx_len_fifo_x = mac_rd_tx_len_fifo & clk_en;
assign mac_rd_tx_data_fifo_x = (mac_rd_tx_data_fifo) & clk_en;
always @(posedge clk_i or negedge reset_n)
begin
if (!reset_n) begin
tx_len_fifo_data_1d <= 16'h0000;
tx_data_fifo_data_1d <= 8'h00;
tx_len_fifo_write_1d <= 1'b0;
tx_data_fifo_write_1d <= 1'b0;
end
else begin
tx_len_fifo_data_1d <= tx_len_fifo_data;
tx_data_fifo_data_1d <= tx_data_fifo_data;
tx_len_fifo_write_1d <= tx_len_fifo_write;
tx_data_fifo_write_1d <= tx_data_fifo_write;
end
end
assign tx_fifodata[7:0] = tx_fifo_data[7:0];
always @(posedge txmac_clk or negedge reset_n)
begin
if (!reset_n) begin
byte_cnt <= 16'd0;
end
else if (clk_en) begin
if (load_cnt) begin
byte_cnt <= tx_fifo_len_minus1[15:0];
end
else if (tx_macread) begin
byte_cnt <= byte_cnt - 1;
end
end
end
always @(posedge txmac_clk or negedge reset_n)
begin
if (!reset_n) begin
tx_fifo_len_minus1 <= 16'd0;
end
else if (clk_en) begin
tx_fifo_len_minus1 <= (tx_fifo_len - 1);
end
end
always @(posedge txmac_clk or negedge reset_n)
begin
if (!reset_n) begin
eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;
tx_fifoempty <= 1'b1;
load_cnt <= 1'b0;
tx_fifoeof <= 1'b0;
mac_rd_tx_len_fifo <= 1'b0;
end
else if (clk_en) begin
load_cnt <= 1'b0;
tx_fifoeof <= 1'b0;
mac_rd_tx_len_fifo <= 1'b0;
case (eth_txfifo_ctrl_fsm)
TX_CTRL_FSM_IDLE:
begin
tx_fifoempty <= 1'b1;
if (!tx_len_fifo_empty) begin
mac_rd_tx_len_fifo <= 1'b1;
load_cnt <= 1'b1;
eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_DATA_AVAIL;
end
end
TX_CTRL_FSM_DATA_AVAIL:
begin
tx_fifoempty <= 1'b0;
eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_PULL_PKT;
end
TX_CTRL_FSM_PULL_PKT:
begin
if (byte_cnt == 16'd0) begin
tx_fifoeof <= 1'b1;
tx_fifoempty <= 1'b1;
eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_WAIT3;
end
else begin
eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_PULL_PKT;
end
end
TX_CTRL_FSM_WAIT3:
begin
eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;
end
default:
begin
eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;
tx_fifoempty <= 1'b1;
load_cnt <= 1'b0;
tx_fifoeof <= 1'b0;
mac_rd_tx_len_fifo <= 1'b0;
end
endcase
end
end
async_fifo #(16, 10)
u_tx_len_fifo
(
.wclk(clk_i),
.wrst_n(reset_n),
.winc(tx_len_fifo_write_1d),
.wdata(tx_len_fifo_data_1d),
.wfull(),
.rclk(txmac_clk),
.rrst_n(reset_n),
.rinc(mac_rd_tx_len_fifo_x),
.rdata(tx_fifo_len[15:0]),
.rempty(tx_len_fifo_empty)
);
async_fifo #(16, 10)
u_tx_data_fifo
(
.wclk(clk_i),
.wrst_n(reset_n),
.winc(tx_data_fifo_write_1d),
.wdata(tx_data_fifo_data_1d),
.wfull(tx_data_fifo_full),
.rclk(txmac_clk),
.rrst_n(reset_n),
.rinc(mac_rd_tx_data_fifo_x),
.rdata(tx_fifo_data[7:0]),
.rempty(tx_data_fifo_empty)
);
endmodule | module eth_tx_fifo_wraper
(
input clk_i,
input reset_n,
input clk_en,
input [15:0] tx_len_fifo_data,
input [7:0] tx_data_fifo_data,
input tx_len_fifo_write,
input tx_data_fifo_write,
input tx_macread,
input txmac_clk,
output reg tx_fifoempty,
output wire [7:0] tx_fifodata,
output reg tx_fifoeof
); |
reg [15:0] tx_len_fifo_data_1d;
reg [7:0] tx_data_fifo_data_1d;
reg tx_len_fifo_write_1d;
reg tx_data_fifo_write_1d;
reg mac_rd_tx_len_fifo;
reg [15:0] byte_cnt;
reg load_cnt;
reg [2:0] eth_txfifo_ctrl_fsm;
wire mac_rd_tx_data_fifo;
wire [7:0] tx_fifo_data;
wire [15:0] tx_fifo_len;
reg [15:0] tx_fifo_len_minus1;
wire mac_rd_tx_len_fifo_x;
wire mac_rd_tx_data_fifo_x;
wire tx_len_fifo_empty;
wire tx_data_fifo_full;
wire tx_data_fifo_empty;
parameter [1:0]
TX_CTRL_FSM_IDLE = 2'd0,
TX_CTRL_FSM_DATA_AVAIL = 2'd1,
TX_CTRL_FSM_PULL_PKT = 2'd2,
TX_CTRL_FSM_WAIT3 = 2'd3;
assign mac_rd_tx_data_fifo = tx_macread;
assign mac_rd_tx_len_fifo_x = mac_rd_tx_len_fifo & clk_en;
assign mac_rd_tx_data_fifo_x = (mac_rd_tx_data_fifo) & clk_en;
always @(posedge clk_i or negedge reset_n)
begin
if (!reset_n) begin
tx_len_fifo_data_1d <= 16'h0000;
tx_data_fifo_data_1d <= 8'h00;
tx_len_fifo_write_1d <= 1'b0;
tx_data_fifo_write_1d <= 1'b0;
end
else begin
tx_len_fifo_data_1d <= tx_len_fifo_data;
tx_data_fifo_data_1d <= tx_data_fifo_data;
tx_len_fifo_write_1d <= tx_len_fifo_write;
tx_data_fifo_write_1d <= tx_data_fifo_write;
end
end
assign tx_fifodata[7:0] = tx_fifo_data[7:0];
always @(posedge txmac_clk or negedge reset_n)
begin
if (!reset_n) begin
byte_cnt <= 16'd0;
end
else if (clk_en) begin
if (load_cnt) begin
byte_cnt <= tx_fifo_len_minus1[15:0];
end
else if (tx_macread) begin
byte_cnt <= byte_cnt - 1;
end
end
end
always @(posedge txmac_clk or negedge reset_n)
begin
if (!reset_n) begin
tx_fifo_len_minus1 <= 16'd0;
end
else if (clk_en) begin
tx_fifo_len_minus1 <= (tx_fifo_len - 1);
end
end
always @(posedge txmac_clk or negedge reset_n)
begin
if (!reset_n) begin
eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;
tx_fifoempty <= 1'b1;
load_cnt <= 1'b0;
tx_fifoeof <= 1'b0;
mac_rd_tx_len_fifo <= 1'b0;
end
else if (clk_en) begin
load_cnt <= 1'b0;
tx_fifoeof <= 1'b0;
mac_rd_tx_len_fifo <= 1'b0;
case (eth_txfifo_ctrl_fsm)
TX_CTRL_FSM_IDLE:
begin
tx_fifoempty <= 1'b1;
if (!tx_len_fifo_empty) begin
mac_rd_tx_len_fifo <= 1'b1;
load_cnt <= 1'b1;
eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_DATA_AVAIL;
end
end
TX_CTRL_FSM_DATA_AVAIL:
begin
tx_fifoempty <= 1'b0;
eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_PULL_PKT;
end
TX_CTRL_FSM_PULL_PKT:
begin
if (byte_cnt == 16'd0) begin
tx_fifoeof <= 1'b1;
tx_fifoempty <= 1'b1;
eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_WAIT3;
end
else begin
eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_PULL_PKT;
end
end
TX_CTRL_FSM_WAIT3:
begin
eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;
end
default:
begin
eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;
tx_fifoempty <= 1'b1;
load_cnt <= 1'b0;
tx_fifoeof <= 1'b0;
mac_rd_tx_len_fifo <= 1'b0;
end
endcase
end
end
async_fifo #(16, 10)
u_tx_len_fifo
(
.wclk(clk_i),
.wrst_n(reset_n),
.winc(tx_len_fifo_write_1d),
.wdata(tx_len_fifo_data_1d),
.wfull(),
.rclk(txmac_clk),
.rrst_n(reset_n),
.rinc(mac_rd_tx_len_fifo_x),
.rdata(tx_fifo_len[15:0]),
.rempty(tx_len_fifo_empty)
);
async_fifo #(16, 10)
u_tx_data_fifo
(
.wclk(clk_i),
.wrst_n(reset_n),
.winc(tx_data_fifo_write_1d),
.wdata(tx_data_fifo_data_1d),
.wfull(tx_data_fifo_full),
.rclk(txmac_clk),
.rrst_n(reset_n),
.rinc(mac_rd_tx_data_fifo_x),
.rdata(tx_fifo_data[7:0]),
.rempty(tx_data_fifo_empty)
);
endmodule | 9 |
6,235 | data/full_repos/permissive/115771353/rtl/hworb/internet_rx.v | 115,771,353 | internet_rx.v | v | 433 | 212 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/internet_rx.v:45: Operator VAR \'RX_INT_IDLE\' expects 2 bits on the Initial value, but Initial value\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance internet_rx\n RX_INT_IDLE = 3\'d0, \n ^~~~~~~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/internet_rx.v:46: Operator VAR \'RX_INT_GETHEADERLEN\' expects 2 bits on the Initial value, but Initial value\'s CONST \'3\'h1\' generates 3 bits.\n : ... In instance internet_rx\n RX_INT_GETHEADERLEN = 3\'d1, \n ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/internet_rx.v:47: Operator VAR \'RX_INT_GETHEADERBYTE\' expects 2 bits on the Initial value, but Initial value\'s CONST \'3\'h2\' generates 3 bits.\n : ... In instance internet_rx\n RX_INT_GETHEADERBYTE = 3\'d2, \n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/internet_rx.v:48: Operator VAR \'RX_INT_COMPLETEFRAGMENT\' expects 2 bits on the Initial value, but Initial value\'s CONST \'3\'h3\' generates 3 bits.\n : ... In instance internet_rx\n RX_INT_COMPLETEFRAGMENT = 3\'d3;\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/internet_rx.v:372: Operator ADD expects 16 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance internet_rx\n assign checksumInt = checksumLong[15:0] + checksumLong[16];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 7,036 | module | module internet_rx #(
parameter [31:0] DEVICE_IP = 32'h8d59342b
)
(
input clk,
input reset_n,
input newFrame,
input frameType,
input newFrameByte,
input [7:0] frameData,
output reg newDatagram,
output reg [15:0] datagramSize,
output wire [7:0] protocol,
output wire [31:0] sourceIP
);
parameter [1:0]
RX_INT_IDLE = 3'd0,
RX_INT_GETHEADERLEN = 3'd1,
RX_INT_GETHEADERBYTE = 3'd2,
RX_INT_COMPLETEFRAGMENT = 3'd3;
reg [1:0] ip_rx_cur_fsm;
reg [1:0] ip_rx_nxt_fsm;
reg [1:0] returnState;
reg [5:0] headerLen;
reg [5:0] nextHeaderLen;
reg [10:0] datagramLen;
reg [10:0] nextDatagramLen;
wire [10:0] dataLen;
reg [10:0] nextDataLen;
reg incCnt;
reg rstCnt;
reg [5:0] cnt;
reg latchFrameData;
reg [7:0] frameDataLatch;
reg [31:0] targetIP;
reg shiftInTargetIP;
reg shiftInSourceIP;
reg latchProtocol;
reg checkState;
parameter stMSB = 1'b0;
parameter stLSB = 1'b1;
reg [16:0] checksumLong;
wire [15:0] checksumInt;
reg [7:0] latchMSB;
reg newHeader;
reg newByte;
reg lastNewByte;
reg [7:0] inByte;
wire [15:0] checksum;
reg [15:0] identification;
reg shiftInIdentification;
reg [12:0] fragmentOffset;
reg shiftInFragmentOffset;
reg moreFragments;
reg latchMoreFragments;
parameter TIMERWIDTH = 7;
reg [6:0] timeout0;
reg resetTimeout;
parameter FULLTIME = 7'b1111111;
reg [31:0] sourceIPSig;
reg [7:0] protocolSig;
assign sourceIP = sourceIPSig;
assign protocol = protocolSig;
assign dataLen = datagramLen - {5'b00000,headerLen[5:0]};
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
ip_rx_cur_fsm <= RX_INT_IDLE;
returnState <= RX_INT_IDLE;
timeout0 <= FULLTIME;
cnt <= 6'b0;
moreFragments <= 1'b0;
end
else begin
ip_rx_cur_fsm <= ip_rx_nxt_fsm;
if (incCnt)
cnt <= cnt + 1;
else if (rstCnt)
cnt <= 6'b0;
if (latchFrameData)
frameDataLatch <= frameData;
headerLen <= nextHeaderLen;
datagramLen <= nextDatagramLen;
if (shiftInSourceIP)
sourceIPSig <= {sourceIPSig[23:0], frameData};
if (shiftInTargetIP)
targetIP <= {targetIP[23:0], frameData};
if (latchProtocol)
protocolSig <= frameData;
if (shiftInFragmentOffset)
fragmentOffset <= {fragmentOffset[4:0], frameData};
if (latchMoreFragments)
moreFragments <= frameData[5];
if (shiftInIdentification)
identification <= {identification[7:0], frameData};
if (resetTimeout)
timeout0 <= 7'b0;
else begin
if (timeout0 != FULLTIME)
timeout0 <= timeout0 + 1;
else
timeout0 <= FULLTIME;
end
end
end
always @(ip_rx_cur_fsm or returnState or cnt or frameData or datagramLen or headerLen or dataLen or newFrame or frameType or checksum or targetIP or timeout0 or fragmentOffset or moreFragments or newFrameByte)
begin
datagramSize <= 16'b0;
incCnt <= 1'b0;
rstCnt <= 1'b0;
newDatagram <= 1'b0;
nextHeaderLen <= headerLen;
nextDatagramLen <= datagramLen;
latchFrameData <= 1'b0;
shiftInSourceIP <= 1'b0;
shiftInTargetIP <= 1'b0;
latchProtocol <= 1'b0;
newHeader <= 1'b0;
newByte <= 1'b0;
inByte <= 8'b0;
latchMoreFragments <= 1'b0;
shiftInFragmentOffset <= 1'b0;
shiftInIdentification <= 1'b0;
resetTimeout <= 1'b0;
case(ip_rx_cur_fsm)
RX_INT_IDLE:
begin
resetTimeout <= 1'b1;
if (!newFrame || !frameType)
ip_rx_nxt_fsm <= RX_INT_IDLE;
else begin
rstCnt <= 1'b1;
newHeader <= 1'b1;
ip_rx_nxt_fsm <= RX_INT_GETHEADERLEN;
end
end
RX_INT_GETHEADERLEN:
begin
if (newFrameByte) begin
if (frameData[7:4] != 4)
ip_rx_nxt_fsm <= RX_INT_IDLE;
else begin
ip_rx_nxt_fsm <= RX_INT_GETHEADERBYTE;
inByte <= frameData;
newByte <= 1'b1;
nextHeaderLen <= {frameData[3:0], 2'b00};
end
incCnt <= 1'b1;
end
else
ip_rx_nxt_fsm <= RX_INT_GETHEADERLEN;
end
RX_INT_GETHEADERBYTE:
begin
if (cnt == headerLen) begin
if (checksum == 0 && (targetIP == DEVICE_IP || targetIP == 32'hFFFFFFFF))
ip_rx_nxt_fsm <= RX_INT_COMPLETEFRAGMENT;
else
ip_rx_nxt_fsm <= RX_INT_IDLE;
end
else if (newFrameByte) begin
newByte <= 1'b1;
inByte <= frameData;
case(cnt[4:0])
5'd2:
begin
nextDatagramLen[10:8] <= frameData[2:0];
end
5'd3:
begin
nextDatagramLen[7:0] <= frameData;
end
5'd4, 5'd5:
begin
shiftInIdentification <= 1'b1;
end
5'd6:
begin
shiftInFragmentOffset <= 1'b1;
latchMoreFragments <= 1'b1;
end
5'd7:
begin
shiftInFragmentOffset <= 1'b1;
end
5'd9:
begin
latchProtocol <= 1'b1;
end
5'd12, 5'd13, 5'd14, 5'd15:
begin
shiftInSourceIP <= 1'b1;
end
5'd16, 5'd17, 5'd18, 5'd19:
begin
shiftInTargetIP <= 1'b1;
end
default:
begin
end
endcase
incCnt <= 1'b1;
ip_rx_nxt_fsm <= RX_INT_GETHEADERBYTE;
resetTimeout <= 1'b1;
end
else if (timeout0 == FULLTIME)
ip_rx_nxt_fsm <= RX_INT_IDLE;
else begin
ip_rx_nxt_fsm <= RX_INT_GETHEADERBYTE;
end
end
RX_INT_COMPLETEFRAGMENT:
begin
ip_rx_nxt_fsm <= RX_INT_IDLE;
if (!moreFragments) begin
newDatagram <= 1'b1;
datagramSize <= {5'b00000, dataLen};
end
end
default:
begin
ip_rx_nxt_fsm <= RX_INT_IDLE;
end
endcase
end
assign checksumInt = checksumLong[15:0] + checksumLong[16];
assign checksum = ~checksumInt;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
checkState <= stMSB;
latchMSB <= 8'b0;
checksumLong <= 17'b0;
lastNewByte <= 1'b0;
end
else begin
lastNewByte <= newByte;
case(checkState)
stMSB:
begin
if (newHeader) begin
checkState <= stMSB;
checksumLong <= 17'b0;
end
else if (newByte && !lastNewByte) begin
checkState <= stLSB;
latchMSB <= inByte;
end
else
checkState <= stMSB;
end
stLSB:
begin
if (newHeader) begin
checkState <= stMSB;
checksumLong <= 17'b0;
end
else if (newByte && !lastNewByte) begin
checkState <= stMSB;
checksumLong <= {1'b0,checksumInt} + {1'b0,latchMSB,inByte};
end
else
checkState <= stLSB;
end
default:
begin
checkState <= stMSB;
end
endcase
end
end
endmodule | module internet_rx #(
parameter [31:0] DEVICE_IP = 32'h8d59342b
)
(
input clk,
input reset_n,
input newFrame,
input frameType,
input newFrameByte,
input [7:0] frameData,
output reg newDatagram,
output reg [15:0] datagramSize,
output wire [7:0] protocol,
output wire [31:0] sourceIP
); |
parameter [1:0]
RX_INT_IDLE = 3'd0,
RX_INT_GETHEADERLEN = 3'd1,
RX_INT_GETHEADERBYTE = 3'd2,
RX_INT_COMPLETEFRAGMENT = 3'd3;
reg [1:0] ip_rx_cur_fsm;
reg [1:0] ip_rx_nxt_fsm;
reg [1:0] returnState;
reg [5:0] headerLen;
reg [5:0] nextHeaderLen;
reg [10:0] datagramLen;
reg [10:0] nextDatagramLen;
wire [10:0] dataLen;
reg [10:0] nextDataLen;
reg incCnt;
reg rstCnt;
reg [5:0] cnt;
reg latchFrameData;
reg [7:0] frameDataLatch;
reg [31:0] targetIP;
reg shiftInTargetIP;
reg shiftInSourceIP;
reg latchProtocol;
reg checkState;
parameter stMSB = 1'b0;
parameter stLSB = 1'b1;
reg [16:0] checksumLong;
wire [15:0] checksumInt;
reg [7:0] latchMSB;
reg newHeader;
reg newByte;
reg lastNewByte;
reg [7:0] inByte;
wire [15:0] checksum;
reg [15:0] identification;
reg shiftInIdentification;
reg [12:0] fragmentOffset;
reg shiftInFragmentOffset;
reg moreFragments;
reg latchMoreFragments;
parameter TIMERWIDTH = 7;
reg [6:0] timeout0;
reg resetTimeout;
parameter FULLTIME = 7'b1111111;
reg [31:0] sourceIPSig;
reg [7:0] protocolSig;
assign sourceIP = sourceIPSig;
assign protocol = protocolSig;
assign dataLen = datagramLen - {5'b00000,headerLen[5:0]};
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
ip_rx_cur_fsm <= RX_INT_IDLE;
returnState <= RX_INT_IDLE;
timeout0 <= FULLTIME;
cnt <= 6'b0;
moreFragments <= 1'b0;
end
else begin
ip_rx_cur_fsm <= ip_rx_nxt_fsm;
if (incCnt)
cnt <= cnt + 1;
else if (rstCnt)
cnt <= 6'b0;
if (latchFrameData)
frameDataLatch <= frameData;
headerLen <= nextHeaderLen;
datagramLen <= nextDatagramLen;
if (shiftInSourceIP)
sourceIPSig <= {sourceIPSig[23:0], frameData};
if (shiftInTargetIP)
targetIP <= {targetIP[23:0], frameData};
if (latchProtocol)
protocolSig <= frameData;
if (shiftInFragmentOffset)
fragmentOffset <= {fragmentOffset[4:0], frameData};
if (latchMoreFragments)
moreFragments <= frameData[5];
if (shiftInIdentification)
identification <= {identification[7:0], frameData};
if (resetTimeout)
timeout0 <= 7'b0;
else begin
if (timeout0 != FULLTIME)
timeout0 <= timeout0 + 1;
else
timeout0 <= FULLTIME;
end
end
end
always @(ip_rx_cur_fsm or returnState or cnt or frameData or datagramLen or headerLen or dataLen or newFrame or frameType or checksum or targetIP or timeout0 or fragmentOffset or moreFragments or newFrameByte)
begin
datagramSize <= 16'b0;
incCnt <= 1'b0;
rstCnt <= 1'b0;
newDatagram <= 1'b0;
nextHeaderLen <= headerLen;
nextDatagramLen <= datagramLen;
latchFrameData <= 1'b0;
shiftInSourceIP <= 1'b0;
shiftInTargetIP <= 1'b0;
latchProtocol <= 1'b0;
newHeader <= 1'b0;
newByte <= 1'b0;
inByte <= 8'b0;
latchMoreFragments <= 1'b0;
shiftInFragmentOffset <= 1'b0;
shiftInIdentification <= 1'b0;
resetTimeout <= 1'b0;
case(ip_rx_cur_fsm)
RX_INT_IDLE:
begin
resetTimeout <= 1'b1;
if (!newFrame || !frameType)
ip_rx_nxt_fsm <= RX_INT_IDLE;
else begin
rstCnt <= 1'b1;
newHeader <= 1'b1;
ip_rx_nxt_fsm <= RX_INT_GETHEADERLEN;
end
end
RX_INT_GETHEADERLEN:
begin
if (newFrameByte) begin
if (frameData[7:4] != 4)
ip_rx_nxt_fsm <= RX_INT_IDLE;
else begin
ip_rx_nxt_fsm <= RX_INT_GETHEADERBYTE;
inByte <= frameData;
newByte <= 1'b1;
nextHeaderLen <= {frameData[3:0], 2'b00};
end
incCnt <= 1'b1;
end
else
ip_rx_nxt_fsm <= RX_INT_GETHEADERLEN;
end
RX_INT_GETHEADERBYTE:
begin
if (cnt == headerLen) begin
if (checksum == 0 && (targetIP == DEVICE_IP || targetIP == 32'hFFFFFFFF))
ip_rx_nxt_fsm <= RX_INT_COMPLETEFRAGMENT;
else
ip_rx_nxt_fsm <= RX_INT_IDLE;
end
else if (newFrameByte) begin
newByte <= 1'b1;
inByte <= frameData;
case(cnt[4:0])
5'd2:
begin
nextDatagramLen[10:8] <= frameData[2:0];
end
5'd3:
begin
nextDatagramLen[7:0] <= frameData;
end
5'd4, 5'd5:
begin
shiftInIdentification <= 1'b1;
end
5'd6:
begin
shiftInFragmentOffset <= 1'b1;
latchMoreFragments <= 1'b1;
end
5'd7:
begin
shiftInFragmentOffset <= 1'b1;
end
5'd9:
begin
latchProtocol <= 1'b1;
end
5'd12, 5'd13, 5'd14, 5'd15:
begin
shiftInSourceIP <= 1'b1;
end
5'd16, 5'd17, 5'd18, 5'd19:
begin
shiftInTargetIP <= 1'b1;
end
default:
begin
end
endcase
incCnt <= 1'b1;
ip_rx_nxt_fsm <= RX_INT_GETHEADERBYTE;
resetTimeout <= 1'b1;
end
else if (timeout0 == FULLTIME)
ip_rx_nxt_fsm <= RX_INT_IDLE;
else begin
ip_rx_nxt_fsm <= RX_INT_GETHEADERBYTE;
end
end
RX_INT_COMPLETEFRAGMENT:
begin
ip_rx_nxt_fsm <= RX_INT_IDLE;
if (!moreFragments) begin
newDatagram <= 1'b1;
datagramSize <= {5'b00000, dataLen};
end
end
default:
begin
ip_rx_nxt_fsm <= RX_INT_IDLE;
end
endcase
end
assign checksumInt = checksumLong[15:0] + checksumLong[16];
assign checksum = ~checksumInt;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
checkState <= stMSB;
latchMSB <= 8'b0;
checksumLong <= 17'b0;
lastNewByte <= 1'b0;
end
else begin
lastNewByte <= newByte;
case(checkState)
stMSB:
begin
if (newHeader) begin
checkState <= stMSB;
checksumLong <= 17'b0;
end
else if (newByte && !lastNewByte) begin
checkState <= stLSB;
latchMSB <= inByte;
end
else
checkState <= stMSB;
end
stLSB:
begin
if (newHeader) begin
checkState <= stMSB;
checksumLong <= 17'b0;
end
else if (newByte && !lastNewByte) begin
checkState <= stMSB;
checksumLong <= {1'b0,checksumInt} + {1'b0,latchMSB,inByte};
end
else
checkState <= stLSB;
end
default:
begin
checkState <= stMSB;
end
endcase
end
end
endmodule | 9 |
6,237 | data/full_repos/permissive/115771353/rtl/hworb/udp_server.v | 115,771,353 | udp_server.v | v | 272 | 99 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/udp_server.v:237: Operator LT expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'cntXmit\' generates 11 bits.\n : ... In instance udp_server\n if (cntXmit < (UDPLEN-2)) begin\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/udp_server.v:243: Operator LT expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'cntXmit\' generates 11 bits.\n : ... In instance udp_server\n if (cntXmit < (UDPLEN-1)) begin\n ^\n%Error: Exiting due to 2 warning(s)\n' | 7,039 | module | module udp_server #(
parameter [15:0] DEVICE_UDP_PORT = 16'hbed0,
parameter [31:0] DEST_IP = 32'h0a0105ce,
parameter [15:0] DEST_UDP_PORT = 16'h1b3b,
parameter [31:0] DEVICE_IP = 32'h0a0105dd
)
(
input clk,
input reset_n,
input wr_complete,
input tx_done_MAC,
input instream_fifoempty,
output wire instream_rden,
input [7:0] instream_rddata,
input [11:0] instream_rcnt,
output reg wrRAM,
output reg [7:0] wrData,
output reg [10:0] wrAddr,
output wire [15:0] sendDatagramSize,
output reg sendDatagram,
output wire [31:0] destinationIP,
output wire [7:0] protocolOut
);
parameter [15:0] UDPLEN = 16'd1292;
parameter [7:0] UDPHEADERLEN = 8'd8;
parameter stMSB = 1'b0;
parameter stLSB = 1'b1;
parameter [1:0]
UDP_SERV_TX_IDLEXMIT = 2'd0,
UDP_SERV_TX_SETWRHEADERXMIT = 2'd1,
UDP_SERV_TX_GETWRDATAXMIT = 2'd2,
UDP_SERV_TX_WRITEFINISHXMIT = 2'd3;
reg [1:0] udp_srv_tx_fsm;
reg [10:0] cntXmit;
reg stream_read_d1;
reg stream_read_i;
assign protocolOut = 8'h11;
assign destinationIP = DEST_IP;
assign sendDatagramSize = UDPLEN;
assign instream_rden = stream_read_i & ~instream_fifoempty;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
udp_srv_tx_fsm <= UDP_SERV_TX_IDLEXMIT;
stream_read_d1 <= 1'b0;
stream_read_i <= 1'b0;
wrRAM <= 1'b0;
wrData <= 8'b0;
wrAddr <= 11'b0;
sendDatagram <= 1'b0;
cntXmit <= 11'b0;
end
else begin
stream_read_i <= 1'b0;
stream_read_d1 <= instream_rden;
wrRAM <= 1'b0;
wrData <= 8'b0;
sendDatagram <= 1'b0;
wrAddr <= cntXmit[10:0] + {3'b000,8'h22};
case(udp_srv_tx_fsm)
UDP_SERV_TX_IDLEXMIT:
begin
cntXmit <= 11'b0;
if (instream_fifoempty) begin
udp_srv_tx_fsm <= UDP_SERV_TX_IDLEXMIT;
end
else begin
udp_srv_tx_fsm <= UDP_SERV_TX_SETWRHEADERXMIT;
end
end
UDP_SERV_TX_SETWRHEADERXMIT:
begin
if (cntXmit < 11'd8) begin
udp_srv_tx_fsm <= UDP_SERV_TX_SETWRHEADERXMIT;
wrRAM <= 1'b1;
cntXmit <= cntXmit + 1;
end
else begin
udp_srv_tx_fsm <= UDP_SERV_TX_GETWRDATAXMIT;
end
case(cntXmit)
11'd0:
begin
wrData <= DEVICE_UDP_PORT[15:8];
end
11'd1:
begin
wrData <= DEVICE_UDP_PORT[7:0];
end
11'd2:
begin
wrData <= DEST_UDP_PORT[15:8];
end
11'd3:
begin
wrData <= DEST_UDP_PORT[7:0];
end
11'd4:
begin
wrData <= UDPLEN[15:8];
end
11'd5:
begin
wrData <= UDPLEN[7:0];
end
11'd6, 11'd7:
begin
wrData <= 8'h00;
end
default:
begin
wrData <= 8'b0;
end
endcase
end
UDP_SERV_TX_GETWRDATAXMIT:
begin
wrData <= instream_rddata[7:0];
wrAddr <= cntXmit[10:0] + {3'b000,8'h22};
if (stream_read_d1) begin
wrRAM <= 1'b1;
cntXmit <= cntXmit + 1;
end
if (cntXmit < (UDPLEN-2)) begin
if (!instream_fifoempty) begin
stream_read_i <= 1'b1;
end
end
if (cntXmit < (UDPLEN-1)) begin
udp_srv_tx_fsm <= UDP_SERV_TX_GETWRDATAXMIT;
end
else begin
udp_srv_tx_fsm <= UDP_SERV_TX_WRITEFINISHXMIT;
sendDatagram <= 1'b1;
end
end
UDP_SERV_TX_WRITEFINISHXMIT:
begin
if (tx_done_MAC) begin
udp_srv_tx_fsm <= UDP_SERV_TX_IDLEXMIT;
end
else begin
udp_srv_tx_fsm <= UDP_SERV_TX_WRITEFINISHXMIT;
end
end
default:
begin
udp_srv_tx_fsm <= UDP_SERV_TX_IDLEXMIT;
end
endcase
end
end
endmodule | module udp_server #(
parameter [15:0] DEVICE_UDP_PORT = 16'hbed0,
parameter [31:0] DEST_IP = 32'h0a0105ce,
parameter [15:0] DEST_UDP_PORT = 16'h1b3b,
parameter [31:0] DEVICE_IP = 32'h0a0105dd
)
(
input clk,
input reset_n,
input wr_complete,
input tx_done_MAC,
input instream_fifoempty,
output wire instream_rden,
input [7:0] instream_rddata,
input [11:0] instream_rcnt,
output reg wrRAM,
output reg [7:0] wrData,
output reg [10:0] wrAddr,
output wire [15:0] sendDatagramSize,
output reg sendDatagram,
output wire [31:0] destinationIP,
output wire [7:0] protocolOut
); |
parameter [15:0] UDPLEN = 16'd1292;
parameter [7:0] UDPHEADERLEN = 8'd8;
parameter stMSB = 1'b0;
parameter stLSB = 1'b1;
parameter [1:0]
UDP_SERV_TX_IDLEXMIT = 2'd0,
UDP_SERV_TX_SETWRHEADERXMIT = 2'd1,
UDP_SERV_TX_GETWRDATAXMIT = 2'd2,
UDP_SERV_TX_WRITEFINISHXMIT = 2'd3;
reg [1:0] udp_srv_tx_fsm;
reg [10:0] cntXmit;
reg stream_read_d1;
reg stream_read_i;
assign protocolOut = 8'h11;
assign destinationIP = DEST_IP;
assign sendDatagramSize = UDPLEN;
assign instream_rden = stream_read_i & ~instream_fifoempty;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
udp_srv_tx_fsm <= UDP_SERV_TX_IDLEXMIT;
stream_read_d1 <= 1'b0;
stream_read_i <= 1'b0;
wrRAM <= 1'b0;
wrData <= 8'b0;
wrAddr <= 11'b0;
sendDatagram <= 1'b0;
cntXmit <= 11'b0;
end
else begin
stream_read_i <= 1'b0;
stream_read_d1 <= instream_rden;
wrRAM <= 1'b0;
wrData <= 8'b0;
sendDatagram <= 1'b0;
wrAddr <= cntXmit[10:0] + {3'b000,8'h22};
case(udp_srv_tx_fsm)
UDP_SERV_TX_IDLEXMIT:
begin
cntXmit <= 11'b0;
if (instream_fifoempty) begin
udp_srv_tx_fsm <= UDP_SERV_TX_IDLEXMIT;
end
else begin
udp_srv_tx_fsm <= UDP_SERV_TX_SETWRHEADERXMIT;
end
end
UDP_SERV_TX_SETWRHEADERXMIT:
begin
if (cntXmit < 11'd8) begin
udp_srv_tx_fsm <= UDP_SERV_TX_SETWRHEADERXMIT;
wrRAM <= 1'b1;
cntXmit <= cntXmit + 1;
end
else begin
udp_srv_tx_fsm <= UDP_SERV_TX_GETWRDATAXMIT;
end
case(cntXmit)
11'd0:
begin
wrData <= DEVICE_UDP_PORT[15:8];
end
11'd1:
begin
wrData <= DEVICE_UDP_PORT[7:0];
end
11'd2:
begin
wrData <= DEST_UDP_PORT[15:8];
end
11'd3:
begin
wrData <= DEST_UDP_PORT[7:0];
end
11'd4:
begin
wrData <= UDPLEN[15:8];
end
11'd5:
begin
wrData <= UDPLEN[7:0];
end
11'd6, 11'd7:
begin
wrData <= 8'h00;
end
default:
begin
wrData <= 8'b0;
end
endcase
end
UDP_SERV_TX_GETWRDATAXMIT:
begin
wrData <= instream_rddata[7:0];
wrAddr <= cntXmit[10:0] + {3'b000,8'h22};
if (stream_read_d1) begin
wrRAM <= 1'b1;
cntXmit <= cntXmit + 1;
end
if (cntXmit < (UDPLEN-2)) begin
if (!instream_fifoempty) begin
stream_read_i <= 1'b1;
end
end
if (cntXmit < (UDPLEN-1)) begin
udp_srv_tx_fsm <= UDP_SERV_TX_GETWRDATAXMIT;
end
else begin
udp_srv_tx_fsm <= UDP_SERV_TX_WRITEFINISHXMIT;
sendDatagram <= 1'b1;
end
end
UDP_SERV_TX_WRITEFINISHXMIT:
begin
if (tx_done_MAC) begin
udp_srv_tx_fsm <= UDP_SERV_TX_IDLEXMIT;
end
else begin
udp_srv_tx_fsm <= UDP_SERV_TX_WRITEFINISHXMIT;
end
end
default:
begin
udp_srv_tx_fsm <= UDP_SERV_TX_IDLEXMIT;
end
endcase
end
end
endmodule | 9 |
6,239 | data/full_repos/permissive/115784205/src/rtl/ubbefpga1.v | 115,784,205 | ubbefpga1.v | v | 100 | 73 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/59f9298e-acf4-428c-ae80-c5a22621e3f1.xml | null | 7,042 | module | module ubbefpga(
input wire clk,
input wire reset_n,
input wire led_inc,
output wire [7 : 0] led
);
parameter DELAY = 32'h0100000;
reg [31 : 0] delay_ctr_reg;
reg [31 : 0] delay_ctr_new;
reg [7 : 0] led_reg;
reg [7 : 0] led_new;
reg led_we;
assign led = led_reg;
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
delay_ctr_reg <= 32'h0;
led_reg <= 8'h0;
end
else
begin
delay_ctr_reg <= delay_ctr_new;
if (led_we)
led_reg <= led_new;
end
end
always @*
begin : delay_ctr
if (delay_ctr_reg == DELAY)
begin
delay_ctr_new = 32'h0;
end
else
delay_ctr_new = delay_ctr_reg + 1'b1;
end
always @*
begin : led_toggle
led_new = 8'h00;
led_we = 0;
if (delay_ctr_reg == 32'h0)
begin
if (led_inc)
begin
led_new = led_reg + 1'b1;
led_we = 1;
end
end
end
endmodule | module ubbefpga(
input wire clk,
input wire reset_n,
input wire led_inc,
output wire [7 : 0] led
); |
parameter DELAY = 32'h0100000;
reg [31 : 0] delay_ctr_reg;
reg [31 : 0] delay_ctr_new;
reg [7 : 0] led_reg;
reg [7 : 0] led_new;
reg led_we;
assign led = led_reg;
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
delay_ctr_reg <= 32'h0;
led_reg <= 8'h0;
end
else
begin
delay_ctr_reg <= delay_ctr_new;
if (led_we)
led_reg <= led_new;
end
end
always @*
begin : delay_ctr
if (delay_ctr_reg == DELAY)
begin
delay_ctr_new = 32'h0;
end
else
delay_ctr_new = delay_ctr_reg + 1'b1;
end
always @*
begin : led_toggle
led_new = 8'h00;
led_we = 0;
if (delay_ctr_reg == 32'h0)
begin
if (led_inc)
begin
led_new = led_reg + 1'b1;
led_we = 1;
end
end
end
endmodule | 1 |
6,243 | data/full_repos/permissive/115837888/source-7400/7410-tb.v | 115,837,888 | 7410-tb.v | v | 169 | 86 | [] | [] | [] | null | line:5: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/7410-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7410-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7410-tb.v:31: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("7410-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7410-tb.v:32: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n#3\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7410-tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Error: Exiting due to 4 error(s), 26 warning(s)\n' | 7,055 | module | module test;
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 5;
localparam WIDTH_IN = 3;
reg [BLOCKS*WIDTH_IN-1:0] A;
wire [BLOCKS-1:0] Y;
ttl_7410 #(.BLOCKS(BLOCKS), .WIDTH_IN(WIDTH_IN), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.A_2D(A),
.Y(Y)
);
initial
begin
reg [WIDTH_IN-1:0] Block1;
reg [WIDTH_IN-1:0] Block2;
reg [WIDTH_IN-1:0] Block3;
reg [WIDTH_IN-1:0] Block4;
reg [WIDTH_IN-1:0] Block5;
integer i;
$dumpfile("7410-tb.vcd");
$dumpvars;
Block1 = {WIDTH_IN{1'b1}};
Block2 = {WIDTH_IN{1'b1}};
Block3 = {WIDTH_IN{1'b1}};
Block4 = {WIDTH_IN{1'b1}};
Block5 = {WIDTH_IN{1'b1}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
for (i = 0; i < BLOCKS; i++)
tbassert(Y[i] == 1'b0, "Test 1");
#0
Block1 = {WIDTH_IN{1'b0}};
Block2 = {WIDTH_IN{1'b0}};
Block3 = {WIDTH_IN{1'b0}};
Block4 = {WIDTH_IN{1'b0}};
Block5 = {WIDTH_IN{1'b0}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
for (i = 0; i < BLOCKS; i++)
tbassert(Y[i] == 1'b1, "Test 2");
#0
Block1 = 3'b110;
Block2 = {WIDTH_IN{1'b1}};
Block3 = {WIDTH_IN{1'b1}};
Block4 = {WIDTH_IN{1'b1}};
Block5 = {WIDTH_IN{1'b1}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00001, "Test 3");
#0
Block1 = 3'b011;
Block2 = {WIDTH_IN{1'b1}};
Block3 = {WIDTH_IN{1'b1}};
Block4 = {WIDTH_IN{1'b1}};
Block5 = {WIDTH_IN{1'b1}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00001, "Test 4");
#0
Block1 = {WIDTH_IN{1'b0}};
Block2 = {WIDTH_IN{1'b0}};
Block3 = {WIDTH_IN{1'b0}};
Block4 = 3'b111;
Block5 = {WIDTH_IN{1'b0}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b10111, "Test 5");
#0
Block1 = 3'b110;
Block2 = 3'b110;
Block3 = 3'b110;
Block4 = 3'b110;
Block5 = 3'b110;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b11111, "Test 6");
#0
Block1 = 3'b101;
Block2 = 3'b101;
Block3 = 3'b101;
Block4 = 3'b101;
Block5 = 3'b101;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b11111, "Test 7");
#0
Block1 = 3'b100;
Block2 = 3'b101;
Block3 = 3'b000;
Block4 = 3'b111;
Block5 = 3'b110;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b10111, "Test 8");
#0
Block1 = 3'b010;
Block2 = 3'b011;
Block3 = 3'b000;
Block4 = 3'b111;
Block5 = 3'b110;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b10111, "Test 9");
#0
Block1 = 3'b000;
Block2 = 3'b111;
Block3 = 3'b010;
Block4 = 3'b101;
Block5 = 3'b111;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b01101, "Test 10");
#0
Block1 = 3'b111;
Block2 = 3'b000;
Block3 = 3'b101;
Block4 = 3'b010;
Block5 = 3'b000;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b11110, "Test 11");
#0
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
Block4 = {WIDTH_IN{1'bx}};
Block5 = {WIDTH_IN{1'bx}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
Block1 = 3'b111;
Block2 = 3'b000;
Block3 = 3'b101;
Block4 = 3'b010;
Block5 = 3'b000;
A = {Block5, Block4, Block3, Block2, Block1};
#3
tbassert(Y === 5'bxxxxx, "Test 12");
#7
tbassert(Y == 5'b11110, "Test 12");
#10
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 5;
localparam WIDTH_IN = 3;
reg [BLOCKS*WIDTH_IN-1:0] A;
wire [BLOCKS-1:0] Y;
ttl_7410 #(.BLOCKS(BLOCKS), .WIDTH_IN(WIDTH_IN), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.A_2D(A),
.Y(Y)
);
initial
begin
reg [WIDTH_IN-1:0] Block1;
reg [WIDTH_IN-1:0] Block2;
reg [WIDTH_IN-1:0] Block3;
reg [WIDTH_IN-1:0] Block4;
reg [WIDTH_IN-1:0] Block5;
integer i;
$dumpfile("7410-tb.vcd");
$dumpvars;
Block1 = {WIDTH_IN{1'b1}};
Block2 = {WIDTH_IN{1'b1}};
Block3 = {WIDTH_IN{1'b1}};
Block4 = {WIDTH_IN{1'b1}};
Block5 = {WIDTH_IN{1'b1}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
for (i = 0; i < BLOCKS; i++)
tbassert(Y[i] == 1'b0, "Test 1");
#0
Block1 = {WIDTH_IN{1'b0}};
Block2 = {WIDTH_IN{1'b0}};
Block3 = {WIDTH_IN{1'b0}};
Block4 = {WIDTH_IN{1'b0}};
Block5 = {WIDTH_IN{1'b0}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
for (i = 0; i < BLOCKS; i++)
tbassert(Y[i] == 1'b1, "Test 2");
#0
Block1 = 3'b110;
Block2 = {WIDTH_IN{1'b1}};
Block3 = {WIDTH_IN{1'b1}};
Block4 = {WIDTH_IN{1'b1}};
Block5 = {WIDTH_IN{1'b1}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00001, "Test 3");
#0
Block1 = 3'b011;
Block2 = {WIDTH_IN{1'b1}};
Block3 = {WIDTH_IN{1'b1}};
Block4 = {WIDTH_IN{1'b1}};
Block5 = {WIDTH_IN{1'b1}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00001, "Test 4");
#0
Block1 = {WIDTH_IN{1'b0}};
Block2 = {WIDTH_IN{1'b0}};
Block3 = {WIDTH_IN{1'b0}};
Block4 = 3'b111;
Block5 = {WIDTH_IN{1'b0}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b10111, "Test 5");
#0
Block1 = 3'b110;
Block2 = 3'b110;
Block3 = 3'b110;
Block4 = 3'b110;
Block5 = 3'b110;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b11111, "Test 6");
#0
Block1 = 3'b101;
Block2 = 3'b101;
Block3 = 3'b101;
Block4 = 3'b101;
Block5 = 3'b101;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b11111, "Test 7");
#0
Block1 = 3'b100;
Block2 = 3'b101;
Block3 = 3'b000;
Block4 = 3'b111;
Block5 = 3'b110;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b10111, "Test 8");
#0
Block1 = 3'b010;
Block2 = 3'b011;
Block3 = 3'b000;
Block4 = 3'b111;
Block5 = 3'b110;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b10111, "Test 9");
#0
Block1 = 3'b000;
Block2 = 3'b111;
Block3 = 3'b010;
Block4 = 3'b101;
Block5 = 3'b111;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b01101, "Test 10");
#0
Block1 = 3'b111;
Block2 = 3'b000;
Block3 = 3'b101;
Block4 = 3'b010;
Block5 = 3'b000;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b11110, "Test 11");
#0
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
Block4 = {WIDTH_IN{1'bx}};
Block5 = {WIDTH_IN{1'bx}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
Block1 = 3'b111;
Block2 = 3'b000;
Block3 = 3'b101;
Block4 = 3'b010;
Block5 = 3'b000;
A = {Block5, Block4, Block3, Block2, Block1};
#3
tbassert(Y === 5'bxxxxx, "Test 12");
#7
tbassert(Y == 5'b11110, "Test 12");
#10
$finish;
end
endmodule | 84 |
6,244 | data/full_repos/permissive/115837888/source-7400/74112-tb.v | 115,837,888 | 74112-tb.v | v | 949 | 99 | [] | [] | [] | null | line:8: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/74112-tb.v:8: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74112-tb.v:8: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74112-tb.v:36: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("74112-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74112-tb.v:37: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n#65\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:191: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:200: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:206: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:209: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:212: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:215: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:218: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:226: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:229: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:232: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:238: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:241: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:245: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:248: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:251: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:254: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:257: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:260: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:264: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:268: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:271: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:274: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:282: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:277: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:285: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:287: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:290: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:293: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:296: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:305: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:308: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:311: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:314: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:317: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:320: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:324: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:328: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:331: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:334: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:337: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:342: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:345: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:347: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:350: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:353: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:356: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:362: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:365: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:369: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:372: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:375: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:379: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:381: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:383: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:386: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:390: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:395: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:398: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:402: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:406: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:409: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:412: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:415: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:418: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:421: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:424: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:427: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:430: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:433: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:435: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:439: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:441: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:443: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:446: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:450: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:453: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:456: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:458: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:462: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:464: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:466: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:469: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:473: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:478: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:481: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:485: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:489: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:492: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:495: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:498: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:501: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:504: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:507: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:510: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:513: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:516: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:518: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:525: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:528: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:531: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:534: Unsupported: Ignoring delay on this delayed statement.\n#13\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:537: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:541: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:544: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:547: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:551: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:553: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:555: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:558: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:562: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:568: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:571: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:576: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:578: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:581: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:584: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:587: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:590: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:594: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:597: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:600: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:603: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:606: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:609: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:612: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:615: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:618: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:621: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:623: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:627: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:629: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:631: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:634: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:638: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:642: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:644: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:647: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:650: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:652: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:656: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:658: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:660: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:663: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:667: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:673: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:676: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:681: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:683: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:686: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:689: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:692: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:695: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:699: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:702: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:705: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:708: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:711: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:714: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:717: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:720: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:723: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:726: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:728: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:734: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:737: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:740: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:742: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:745: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:748: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:751: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:754: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:756: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:758: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:760: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:762: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:765: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:768: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:771: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:773: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:775: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:778: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:780: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:782: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:784: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:787: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:791: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:794: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:796: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:798: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:801: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:804: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:806: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:808: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:811: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:814: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:816: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:819: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:822: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:824: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:826: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:828: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:831: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:839: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:841: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:843: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:846: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:850: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:852: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:854: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:857: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:861: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:864: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:867: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:870: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:873: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:875: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:878: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:881: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:884: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:886: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:890: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:893: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:897: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:899: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:901: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:904: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:908: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:911: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:914: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:917: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:920: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:922: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:926: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:928: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:930: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:937: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:933: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:939: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:941: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74112-tb.v:944: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Error: Exiting due to 4 error(s), 290 warning(s)\n' | 7,059 | module | module test;
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 3;
reg [BLOCKS-1:0] Preset_bar;
reg [BLOCKS-1:0] Clear_bar;
reg [BLOCKS-1:0] J;
reg [BLOCKS-1:0] K;
reg [BLOCKS-1:0] Clk;
wire [BLOCKS-1:0] Q;
wire [BLOCKS-1:0] Q_bar;
ttl_74112 #(.BLOCKS(BLOCKS), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Preset_bar(Preset_bar),
.Clear_bar(Clear_bar),
.J(J),
.K(K),
.Clk(Clk),
.Q(Q),
.Q_bar(Q_bar)
);
initial
begin
$dumpfile("74112-tb.vcd");
$dumpvars;
#65
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b000;
#7
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
J = 3'b000;
K = 3'b111;
#25
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b111;
#2
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b000;
#2
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#5
tbassert(Q == 3'b000, "Test 1");
tbassert(Q_bar == 3'b111, "Test 1");
#140
Clk = 3'b111;
#175
tbassert(Q == 3'b000, "Test 2");
tbassert(Q_bar == 3'b111, "Test 2");
#0
J = 3'b111;
K = 3'b000;
#125
tbassert(Q == 3'b000, "Test 3");
tbassert(Q_bar == 3'b111, "Test 3");
#0
Clk = 3'b000;
#2
tbassert(Q == 3'b000, "Test 3");
tbassert(Q_bar == 3'b111, "Test 3");
#5
tbassert(Q == 3'b111, "Test 3");
tbassert(Q_bar == 3'b000, "Test 3");
#50
Clk = 3'b111;
#125
tbassert(Q == 3'b111, "Test 4");
tbassert(Q_bar == 3'b000, "Test 4");
#0
Preset_bar = 3'b111;
Clear_bar = 3'b111;
#50
tbassert(Q == 3'b111, "Test 4");
tbassert(Q_bar == 3'b000, "Test 4");
#0
J = 3'b010;
K = 3'b101;
#15
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b110, "Test 5");
tbassert(Q_bar == 3'b001, "Test 5");
#25
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b110, "Test 6");
tbassert(Q_bar == 3'b001, "Test 6");
#25
Clk[2] = 1'b0;
#7
tbassert(Q == 3'b010, "Test 7");
tbassert(Q_bar == 3'b101, "Test 7");
#140
Clk[1] = 1'b1;
#7
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#10
Clk[0] = 1'b1;
#7
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#10
Clk[2] = 1'b1;
#50
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#0
J = 3'b111;
K = 3'b111;
#75
tbassert(Q == 3'b010, "Test 9");
tbassert(Q_bar == 3'b101, "Test 9");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b101, "Test 9");
tbassert(Q_bar == 3'b010, "Test 9");
#50
Clk = 3'b111;
#50
tbassert(Q == 3'b101, "Test 10");
tbassert(Q_bar == 3'b010, "Test 10");
#0
#15
tbassert(Q == 3'b101, "Test 11");
tbassert(Q_bar == 3'b010, "Test 11");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b010, "Test 11");
tbassert(Q_bar == 3'b101, "Test 11");
#10
Clk = 3'b111;
#75
tbassert(Q == 3'b010, "Test 12");
tbassert(Q_bar == 3'b101, "Test 12");
#0
#15
Clk[2] = 1'b0;
#7
tbassert(Q == 3'b110, "Test 13");
tbassert(Q_bar == 3'b001, "Test 13");
#15
Clk[2] = 1'b1;
#50
tbassert(Q == 3'b110, "Test 14");
tbassert(Q_bar == 3'b001, "Test 14");
#0
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b100, "Test 15");
tbassert(Q_bar == 3'b011, "Test 15");
#10
Clk = 3'b111;
#100
tbassert(Q == 3'b100, "Test 16");
tbassert(Q_bar == 3'b011, "Test 16");
#0
J = 3'b101;
K = 3'b110;
#125
tbassert(Q == 3'b100, "Test 17");
tbassert(Q_bar == 3'b011, "Test 17");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b001, "Test 17");
tbassert(Q_bar == 3'b110, "Test 17");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b001, "Test 18");
tbassert(Q_bar == 3'b110, "Test 18");
#0
J = 3'b101;
K = 3'b011;
#125
tbassert(Q == 3'b001, "Test 19");
tbassert(Q_bar == 3'b110, "Test 19");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b100, "Test 19");
tbassert(Q_bar == 3'b011, "Test 19");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b100, "Test 20");
tbassert(Q_bar == 3'b011, "Test 20");
#0
J = 3'b011;
K = 3'b101;
#15
Clk = 3'b100;
#7
tbassert(Q == 3'b111, "Test 21");
tbassert(Q_bar == 3'b000, "Test 21");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b111, "Test 22");
tbassert(Q_bar == 3'b000, "Test 22");
#0
#15
tbassert(Q == 3'b111, "Test 23");
tbassert(Q_bar == 3'b000, "Test 23");
#0
Clk = 3'b100;
#7
tbassert(Q == 3'b110, "Test 23");
tbassert(Q_bar == 3'b001, "Test 23");
#10
Clk = 3'b111;
#100
tbassert(Q == 3'b110, "Test 24");
tbassert(Q_bar == 3'b001, "Test 24");
#0
J = 3'b101;
K = 3'b100;
#40
tbassert(Q == 3'b110, "Test 25");
tbassert(Q_bar == 3'b001, "Test 25");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b011, "Test 25");
tbassert(Q_bar == 3'b100, "Test 25");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b011, "Test 26");
tbassert(Q_bar == 3'b100, "Test 26");
#0
J = 3'b010;
K = 3'b110;
#15
Clk = 3'b100;
#7
tbassert(Q == 3'b001, "Test 27");
tbassert(Q_bar == 3'b110, "Test 27");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b001, "Test 28");
tbassert(Q_bar == 3'b110, "Test 28");
#0
J = 3'b100;
K = 3'b100;
#15
tbassert(Q == 3'b001, "Test 29");
tbassert(Q_bar == 3'b110, "Test 29");
#0
Clk = 3'b010;
#7
tbassert(Q == 3'b101, "Test 29");
tbassert(Q_bar == 3'b010, "Test 29");
#10
Clk = 3'b111;
#50
tbassert(Q == 3'b101, "Test 30");
tbassert(Q_bar == 3'b010, "Test 30");
#0
Clear_bar = 3'b000;
#2
tbassert(Q == 3'b101, "Test 31");
tbassert(Q_bar == 3'b010, "Test 31");
#5
tbassert(Q == 3'b000, "Test 31");
tbassert(Q_bar == 3'b111, "Test 31");
#150
Clear_bar = 3'b111;
#120
tbassert(Q == 3'b000, "Test 32");
tbassert(Q_bar == 3'b111, "Test 32");
#50
J = 3'b011;
K = 3'b100;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b011, "Test 33");
tbassert(Q_bar == 3'b100, "Test 33");
#0
J = 3'b111;
K = 3'b111;
#15
Clear_bar = 3'b000;
Clk = 3'b001;
#2
tbassert(Q == 3'b011, "Test 33");
tbassert(Q_bar == 3'b100, "Test 33");
#5
tbassert(Q == 3'b000, "Test 33");
tbassert(Q_bar == 3'b111, "Test 33");
#10
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b000, "Test 33");
tbassert(Q_bar == 3'b111, "Test 33");
#150
Clear_bar[1] = 1'b1;
#20
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#0
Clear_bar[0] = 1'b1;
#7
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#10
Clear_bar[2] = 1'b1;
#70
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#0
Clk = 3'b101;
#70
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#0
Clk[1] = 1'b1;
#50
J = 3'b111;
K = 3'b001;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b111, "Test 35");
tbassert(Q_bar == 3'b000, "Test 35");
#0
J = 3'b110;
K = 3'b011;
#15
Clear_bar[2] = 1'b0;
#20
tbassert(Q == 3'b011, "Test 35");
tbassert(Q_bar == 3'b100, "Test 35");
#0
Clear_bar[2] = 1'b1;
#50
J = 3'b011;
K = 3'b100;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b011, "Test 36");
tbassert(Q_bar == 3'b100, "Test 36");
#0
J = 3'b110;
K = 3'b101;
#40
Clear_bar = 3'b000;
Clk = 3'b001;
#2
tbassert(Q == 3'b011, "Test 36");
tbassert(Q_bar == 3'b100, "Test 36");
#5
tbassert(Q == 3'b000, "Test 36");
tbassert(Q_bar == 3'b111, "Test 36");
#10
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b000, "Test 37");
tbassert(Q_bar == 3'b111, "Test 37");
#70
Clear_bar[1] = 1'b1;
#20
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#0
Clear_bar[2] = 1'b1;
#7
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#10
Clear_bar[0] = 1'b1;
#70
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#0
Clk = 3'b101;
#70
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#0
Clk[1] = 1'b1;
#50
Preset_bar = 3'b000;
#15
tbassert(Q == 3'b000, "Test 39");
tbassert(Q_bar == 3'b111, "Test 39");
#0
Clk = 3'b000;
#2
tbassert(Q == 3'b000, "Test 39");
tbassert(Q_bar == 3'b111, "Test 39");
#13
Clk = 3'b111;
#5
tbassert(Q == 3'b111, "Test 39");
tbassert(Q_bar == 3'b000, "Test 39");
#150
Preset_bar = 3'b111;
#120
tbassert(Q == 3'b111, "Test 40");
tbassert(Q_bar == 3'b000, "Test 40");
#50
J = 3'b011;
K = 3'b100;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b011, "Test 41");
tbassert(Q_bar == 3'b100, "Test 41");
#0
J = 3'b111;
K = 3'b111;
#15
Clk = 3'b001;
#2
tbassert(Q == 3'b011, "Test 41");
tbassert(Q_bar == 3'b100, "Test 41");
#5
tbassert(Q == 3'b101, "Test 41");
tbassert(Q_bar == 3'b010, "Test 41");
#0
Preset_bar = 3'b000;
#10
tbassert(Q == 3'b101, "Test 41");
tbassert(Q_bar == 3'b010, "Test 41");
#10
Clk[0] = 1'b0;
#10
tbassert(Q == 3'b101, "Test 41");
tbassert(Q_bar == 3'b010, "Test 41");
#5
Clk[1] = 1'b1;
#15
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b111, "Test 41");
tbassert(Q_bar == 3'b000, "Test 41");
#150
Preset_bar[1] = 1'b1;
#20
tbassert(Q == 3'b111, "Test 42");
tbassert(Q_bar == 3'b000, "Test 42");
#0
Preset_bar[0] = 1'b1;
#7
tbassert(Q == 3'b111, "Test 42");
tbassert(Q_bar == 3'b000, "Test 42");
#10
Preset_bar[2] = 1'b1;
#70
tbassert(Q == 3'b111, "Test 42");
tbassert(Q_bar == 3'b000, "Test 42");
#0
Clk = 3'b101;
#70
tbassert(Q == 3'b111, "Test 42");
tbassert(Q_bar == 3'b000, "Test 42");
#0
Clk[1] = 1'b1;
#50
J = 3'b011;
K = 3'b110;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b001, "Test 43");
tbassert(Q_bar == 3'b110, "Test 43");
#0
J = 3'b010;
K = 3'b011;
#15
Preset_bar[2] = 1'b0;
#10
Clk[2] = 1'b0;
#15
Clk[2] = 1'b1;
#20
tbassert(Q == 3'b101, "Test 43");
tbassert(Q_bar == 3'b010, "Test 43");
#0
Preset_bar[2] = 1'b1;
#50
J = 3'b011;
K = 3'b101;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b010, "Test 44");
tbassert(Q_bar == 3'b101, "Test 44");
#0
J = 3'b110;
K = 3'b011;
#40
Clk = 3'b001;
#2
tbassert(Q == 3'b010, "Test 44");
tbassert(Q_bar == 3'b101, "Test 44");
#5
tbassert(Q == 3'b100, "Test 44");
tbassert(Q_bar == 3'b011, "Test 44");
#0
Preset_bar = 3'b000;
#10
tbassert(Q == 3'b100, "Test 44");
tbassert(Q_bar == 3'b011, "Test 44");
#10
Clk[0] = 1'b0;
#10
tbassert(Q == 3'b101, "Test 44");
tbassert(Q_bar == 3'b010, "Test 44");
#5
Clk[1] = 1'b1;
#15
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b111, "Test 45");
tbassert(Q_bar == 3'b000, "Test 45");
#70
Preset_bar[1] = 1'b1;
#20
tbassert(Q == 3'b111, "Test 46");
tbassert(Q_bar == 3'b000, "Test 46");
#0
Preset_bar[2] = 1'b1;
#7
tbassert(Q == 3'b111, "Test 46");
tbassert(Q_bar == 3'b000, "Test 46");
#10
Preset_bar[0] = 1'b1;
#70
tbassert(Q == 3'b111, "Test 46");
tbassert(Q_bar == 3'b000, "Test 46");
#0
Clk = 3'b101;
#70
tbassert(Q == 3'b111, "Test 46");
tbassert(Q_bar == 3'b000, "Test 46");
#0
Clk = 3'b111;
#15
Preset_bar = 3'b000;
#25
Clear_bar = 3'b010;
#7
tbassert(Q == 3'b010, "Test 47");
tbassert(Q_bar == 3'b101, "Test 47");
#15
Clear_bar = 3'b111;
#25
Preset_bar = 3'b111;
#15
tbassert(Q == 3'b010, "Test 47");
tbassert(Q_bar == 3'b101, "Test 47");
#0
J = 3'b010;
K = 3'b101;
#15
Clk = 3'b001;
#15
Clk = 3'b111;
#15
Clk = 3'b010;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b010, "Test 47");
tbassert(Q_bar == 3'b101, "Test 47");
#0
Clear_bar = 3'b000;
#10
tbassert(Q == 3'b000, "Test 48");
tbassert(Q_bar == 3'b111, "Test 48");
#20
Clear_bar = 3'b111;
#10
Clk = 3'b111;
#20
Clear_bar = 3'b000;
#10
Clk = 3'b000;
#20
Clear_bar = 3'b111;
#15
Clk = 3'b111;
#7
tbassert(Q == 3'b000, "Test 49");
tbassert(Q_bar == 3'b111, "Test 49");
#0
J = 3'b011;
K = 3'b101;
#15
Preset_bar = 3'b000;
#25
Preset_bar = 3'b111;
#7
Clk = 3'b000;
#7
Clear_bar = 3'b010;
#7
tbassert(Q == 3'b010, "Test 50");
tbassert(Q_bar == 3'b101, "Test 50");
#15
Clear_bar = 3'b111;
#25
Clk = 3'b111;
#15
Clk = 3'b000;
#7
tbassert(Q == 3'b011, "Test 51");
tbassert(Q_bar == 3'b100, "Test 51");
#15
Clk = 3'b111;
#0
J = 3'b011;
K = 3'b100;
#15
Clk = 3'b001;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b011, "Test 51");
tbassert(Q_bar == 3'b100, "Test 51");
#0
J = 3'b101;
K = 3'b010;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b101, "Test 52");
tbassert(Q_bar == 3'b010, "Test 52");
#0
J = 3'b000;
K = 3'b000;
#7
Clk = 3'b000;
#25
Clk = 3'b111;
#15
tbassert(Q == 3'b101, "Test 52");
tbassert(Q_bar == 3'b010, "Test 52");
#0
J = 3'b101;
K = 3'b010;
#7
Clk = 3'b011;
#20
tbassert(Q == 3'b101, "Test 53");
tbassert(Q_bar == 3'b010, "Test 53");
#0
Clk = 3'b000;
#20
tbassert(Q == 3'b101, "Test 53");
tbassert(Q_bar == 3'b010, "Test 53");
#0
Clk = 3'b111;
#15
Clk = 3'b000;
#7
J = 3'b011;
K = 3'b101;
#75
tbassert(Q == 3'b101, "Test 54");
tbassert(Q_bar == 3'b010, "Test 54");
#0
Clk = 3'b111;
#25
J = 3'bzz0;
K = 3'bz01;
#50
tbassert(Q == 3'b101, "Test 54");
tbassert(Q_bar == 3'b010, "Test 54");
#0
J = 3'bz10;
K = 3'bz11;
#40
Clk = 3'b110;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b100, "Test 55");
tbassert(Q_bar == 3'b011, "Test 55");
#0
J = 3'b100;
K = 3'b011;
#7
Clk = 3'b110;
#20
tbassert(Q == 3'b100, "Test 56");
tbassert(Q_bar == 3'b011, "Test 56");
#0
Clk = 3'b001;
#40
tbassert(Q == 3'b100, "Test 57");
tbassert(Q_bar == 3'b011, "Test 57");
#0
Clk = 3'b111;
#15
J = 3'b011;
K = 3'b011;
#40
Clk = 3'b011;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b100, "Test 58");
tbassert(Q_bar == 3'b011, "Test 58");
#0
#40
Clk = 3'b110;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b101, "Test 59");
tbassert(Q_bar == 3'b010, "Test 59");
#50
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 3;
reg [BLOCKS-1:0] Preset_bar;
reg [BLOCKS-1:0] Clear_bar;
reg [BLOCKS-1:0] J;
reg [BLOCKS-1:0] K;
reg [BLOCKS-1:0] Clk;
wire [BLOCKS-1:0] Q;
wire [BLOCKS-1:0] Q_bar;
ttl_74112 #(.BLOCKS(BLOCKS), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Preset_bar(Preset_bar),
.Clear_bar(Clear_bar),
.J(J),
.K(K),
.Clk(Clk),
.Q(Q),
.Q_bar(Q_bar)
);
initial
begin
$dumpfile("74112-tb.vcd");
$dumpvars;
#65
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b000;
#7
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
J = 3'b000;
K = 3'b111;
#25
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b111;
#2
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b000;
#2
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#5
tbassert(Q == 3'b000, "Test 1");
tbassert(Q_bar == 3'b111, "Test 1");
#140
Clk = 3'b111;
#175
tbassert(Q == 3'b000, "Test 2");
tbassert(Q_bar == 3'b111, "Test 2");
#0
J = 3'b111;
K = 3'b000;
#125
tbassert(Q == 3'b000, "Test 3");
tbassert(Q_bar == 3'b111, "Test 3");
#0
Clk = 3'b000;
#2
tbassert(Q == 3'b000, "Test 3");
tbassert(Q_bar == 3'b111, "Test 3");
#5
tbassert(Q == 3'b111, "Test 3");
tbassert(Q_bar == 3'b000, "Test 3");
#50
Clk = 3'b111;
#125
tbassert(Q == 3'b111, "Test 4");
tbassert(Q_bar == 3'b000, "Test 4");
#0
Preset_bar = 3'b111;
Clear_bar = 3'b111;
#50
tbassert(Q == 3'b111, "Test 4");
tbassert(Q_bar == 3'b000, "Test 4");
#0
J = 3'b010;
K = 3'b101;
#15
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b110, "Test 5");
tbassert(Q_bar == 3'b001, "Test 5");
#25
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b110, "Test 6");
tbassert(Q_bar == 3'b001, "Test 6");
#25
Clk[2] = 1'b0;
#7
tbassert(Q == 3'b010, "Test 7");
tbassert(Q_bar == 3'b101, "Test 7");
#140
Clk[1] = 1'b1;
#7
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#10
Clk[0] = 1'b1;
#7
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#10
Clk[2] = 1'b1;
#50
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#0
J = 3'b111;
K = 3'b111;
#75
tbassert(Q == 3'b010, "Test 9");
tbassert(Q_bar == 3'b101, "Test 9");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b101, "Test 9");
tbassert(Q_bar == 3'b010, "Test 9");
#50
Clk = 3'b111;
#50
tbassert(Q == 3'b101, "Test 10");
tbassert(Q_bar == 3'b010, "Test 10");
#0
#15
tbassert(Q == 3'b101, "Test 11");
tbassert(Q_bar == 3'b010, "Test 11");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b010, "Test 11");
tbassert(Q_bar == 3'b101, "Test 11");
#10
Clk = 3'b111;
#75
tbassert(Q == 3'b010, "Test 12");
tbassert(Q_bar == 3'b101, "Test 12");
#0
#15
Clk[2] = 1'b0;
#7
tbassert(Q == 3'b110, "Test 13");
tbassert(Q_bar == 3'b001, "Test 13");
#15
Clk[2] = 1'b1;
#50
tbassert(Q == 3'b110, "Test 14");
tbassert(Q_bar == 3'b001, "Test 14");
#0
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b100, "Test 15");
tbassert(Q_bar == 3'b011, "Test 15");
#10
Clk = 3'b111;
#100
tbassert(Q == 3'b100, "Test 16");
tbassert(Q_bar == 3'b011, "Test 16");
#0
J = 3'b101;
K = 3'b110;
#125
tbassert(Q == 3'b100, "Test 17");
tbassert(Q_bar == 3'b011, "Test 17");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b001, "Test 17");
tbassert(Q_bar == 3'b110, "Test 17");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b001, "Test 18");
tbassert(Q_bar == 3'b110, "Test 18");
#0
J = 3'b101;
K = 3'b011;
#125
tbassert(Q == 3'b001, "Test 19");
tbassert(Q_bar == 3'b110, "Test 19");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b100, "Test 19");
tbassert(Q_bar == 3'b011, "Test 19");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b100, "Test 20");
tbassert(Q_bar == 3'b011, "Test 20");
#0
J = 3'b011;
K = 3'b101;
#15
Clk = 3'b100;
#7
tbassert(Q == 3'b111, "Test 21");
tbassert(Q_bar == 3'b000, "Test 21");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b111, "Test 22");
tbassert(Q_bar == 3'b000, "Test 22");
#0
#15
tbassert(Q == 3'b111, "Test 23");
tbassert(Q_bar == 3'b000, "Test 23");
#0
Clk = 3'b100;
#7
tbassert(Q == 3'b110, "Test 23");
tbassert(Q_bar == 3'b001, "Test 23");
#10
Clk = 3'b111;
#100
tbassert(Q == 3'b110, "Test 24");
tbassert(Q_bar == 3'b001, "Test 24");
#0
J = 3'b101;
K = 3'b100;
#40
tbassert(Q == 3'b110, "Test 25");
tbassert(Q_bar == 3'b001, "Test 25");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b011, "Test 25");
tbassert(Q_bar == 3'b100, "Test 25");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b011, "Test 26");
tbassert(Q_bar == 3'b100, "Test 26");
#0
J = 3'b010;
K = 3'b110;
#15
Clk = 3'b100;
#7
tbassert(Q == 3'b001, "Test 27");
tbassert(Q_bar == 3'b110, "Test 27");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b001, "Test 28");
tbassert(Q_bar == 3'b110, "Test 28");
#0
J = 3'b100;
K = 3'b100;
#15
tbassert(Q == 3'b001, "Test 29");
tbassert(Q_bar == 3'b110, "Test 29");
#0
Clk = 3'b010;
#7
tbassert(Q == 3'b101, "Test 29");
tbassert(Q_bar == 3'b010, "Test 29");
#10
Clk = 3'b111;
#50
tbassert(Q == 3'b101, "Test 30");
tbassert(Q_bar == 3'b010, "Test 30");
#0
Clear_bar = 3'b000;
#2
tbassert(Q == 3'b101, "Test 31");
tbassert(Q_bar == 3'b010, "Test 31");
#5
tbassert(Q == 3'b000, "Test 31");
tbassert(Q_bar == 3'b111, "Test 31");
#150
Clear_bar = 3'b111;
#120
tbassert(Q == 3'b000, "Test 32");
tbassert(Q_bar == 3'b111, "Test 32");
#50
J = 3'b011;
K = 3'b100;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b011, "Test 33");
tbassert(Q_bar == 3'b100, "Test 33");
#0
J = 3'b111;
K = 3'b111;
#15
Clear_bar = 3'b000;
Clk = 3'b001;
#2
tbassert(Q == 3'b011, "Test 33");
tbassert(Q_bar == 3'b100, "Test 33");
#5
tbassert(Q == 3'b000, "Test 33");
tbassert(Q_bar == 3'b111, "Test 33");
#10
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b000, "Test 33");
tbassert(Q_bar == 3'b111, "Test 33");
#150
Clear_bar[1] = 1'b1;
#20
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#0
Clear_bar[0] = 1'b1;
#7
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#10
Clear_bar[2] = 1'b1;
#70
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#0
Clk = 3'b101;
#70
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#0
Clk[1] = 1'b1;
#50
J = 3'b111;
K = 3'b001;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b111, "Test 35");
tbassert(Q_bar == 3'b000, "Test 35");
#0
J = 3'b110;
K = 3'b011;
#15
Clear_bar[2] = 1'b0;
#20
tbassert(Q == 3'b011, "Test 35");
tbassert(Q_bar == 3'b100, "Test 35");
#0
Clear_bar[2] = 1'b1;
#50
J = 3'b011;
K = 3'b100;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b011, "Test 36");
tbassert(Q_bar == 3'b100, "Test 36");
#0
J = 3'b110;
K = 3'b101;
#40
Clear_bar = 3'b000;
Clk = 3'b001;
#2
tbassert(Q == 3'b011, "Test 36");
tbassert(Q_bar == 3'b100, "Test 36");
#5
tbassert(Q == 3'b000, "Test 36");
tbassert(Q_bar == 3'b111, "Test 36");
#10
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b000, "Test 37");
tbassert(Q_bar == 3'b111, "Test 37");
#70
Clear_bar[1] = 1'b1;
#20
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#0
Clear_bar[2] = 1'b1;
#7
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#10
Clear_bar[0] = 1'b1;
#70
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#0
Clk = 3'b101;
#70
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#0
Clk[1] = 1'b1;
#50
Preset_bar = 3'b000;
#15
tbassert(Q == 3'b000, "Test 39");
tbassert(Q_bar == 3'b111, "Test 39");
#0
Clk = 3'b000;
#2
tbassert(Q == 3'b000, "Test 39");
tbassert(Q_bar == 3'b111, "Test 39");
#13
Clk = 3'b111;
#5
tbassert(Q == 3'b111, "Test 39");
tbassert(Q_bar == 3'b000, "Test 39");
#150
Preset_bar = 3'b111;
#120
tbassert(Q == 3'b111, "Test 40");
tbassert(Q_bar == 3'b000, "Test 40");
#50
J = 3'b011;
K = 3'b100;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b011, "Test 41");
tbassert(Q_bar == 3'b100, "Test 41");
#0
J = 3'b111;
K = 3'b111;
#15
Clk = 3'b001;
#2
tbassert(Q == 3'b011, "Test 41");
tbassert(Q_bar == 3'b100, "Test 41");
#5
tbassert(Q == 3'b101, "Test 41");
tbassert(Q_bar == 3'b010, "Test 41");
#0
Preset_bar = 3'b000;
#10
tbassert(Q == 3'b101, "Test 41");
tbassert(Q_bar == 3'b010, "Test 41");
#10
Clk[0] = 1'b0;
#10
tbassert(Q == 3'b101, "Test 41");
tbassert(Q_bar == 3'b010, "Test 41");
#5
Clk[1] = 1'b1;
#15
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b111, "Test 41");
tbassert(Q_bar == 3'b000, "Test 41");
#150
Preset_bar[1] = 1'b1;
#20
tbassert(Q == 3'b111, "Test 42");
tbassert(Q_bar == 3'b000, "Test 42");
#0
Preset_bar[0] = 1'b1;
#7
tbassert(Q == 3'b111, "Test 42");
tbassert(Q_bar == 3'b000, "Test 42");
#10
Preset_bar[2] = 1'b1;
#70
tbassert(Q == 3'b111, "Test 42");
tbassert(Q_bar == 3'b000, "Test 42");
#0
Clk = 3'b101;
#70
tbassert(Q == 3'b111, "Test 42");
tbassert(Q_bar == 3'b000, "Test 42");
#0
Clk[1] = 1'b1;
#50
J = 3'b011;
K = 3'b110;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b001, "Test 43");
tbassert(Q_bar == 3'b110, "Test 43");
#0
J = 3'b010;
K = 3'b011;
#15
Preset_bar[2] = 1'b0;
#10
Clk[2] = 1'b0;
#15
Clk[2] = 1'b1;
#20
tbassert(Q == 3'b101, "Test 43");
tbassert(Q_bar == 3'b010, "Test 43");
#0
Preset_bar[2] = 1'b1;
#50
J = 3'b011;
K = 3'b101;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b010, "Test 44");
tbassert(Q_bar == 3'b101, "Test 44");
#0
J = 3'b110;
K = 3'b011;
#40
Clk = 3'b001;
#2
tbassert(Q == 3'b010, "Test 44");
tbassert(Q_bar == 3'b101, "Test 44");
#5
tbassert(Q == 3'b100, "Test 44");
tbassert(Q_bar == 3'b011, "Test 44");
#0
Preset_bar = 3'b000;
#10
tbassert(Q == 3'b100, "Test 44");
tbassert(Q_bar == 3'b011, "Test 44");
#10
Clk[0] = 1'b0;
#10
tbassert(Q == 3'b101, "Test 44");
tbassert(Q_bar == 3'b010, "Test 44");
#5
Clk[1] = 1'b1;
#15
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b111, "Test 45");
tbassert(Q_bar == 3'b000, "Test 45");
#70
Preset_bar[1] = 1'b1;
#20
tbassert(Q == 3'b111, "Test 46");
tbassert(Q_bar == 3'b000, "Test 46");
#0
Preset_bar[2] = 1'b1;
#7
tbassert(Q == 3'b111, "Test 46");
tbassert(Q_bar == 3'b000, "Test 46");
#10
Preset_bar[0] = 1'b1;
#70
tbassert(Q == 3'b111, "Test 46");
tbassert(Q_bar == 3'b000, "Test 46");
#0
Clk = 3'b101;
#70
tbassert(Q == 3'b111, "Test 46");
tbassert(Q_bar == 3'b000, "Test 46");
#0
Clk = 3'b111;
#15
Preset_bar = 3'b000;
#25
Clear_bar = 3'b010;
#7
tbassert(Q == 3'b010, "Test 47");
tbassert(Q_bar == 3'b101, "Test 47");
#15
Clear_bar = 3'b111;
#25
Preset_bar = 3'b111;
#15
tbassert(Q == 3'b010, "Test 47");
tbassert(Q_bar == 3'b101, "Test 47");
#0
J = 3'b010;
K = 3'b101;
#15
Clk = 3'b001;
#15
Clk = 3'b111;
#15
Clk = 3'b010;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b010, "Test 47");
tbassert(Q_bar == 3'b101, "Test 47");
#0
Clear_bar = 3'b000;
#10
tbassert(Q == 3'b000, "Test 48");
tbassert(Q_bar == 3'b111, "Test 48");
#20
Clear_bar = 3'b111;
#10
Clk = 3'b111;
#20
Clear_bar = 3'b000;
#10
Clk = 3'b000;
#20
Clear_bar = 3'b111;
#15
Clk = 3'b111;
#7
tbassert(Q == 3'b000, "Test 49");
tbassert(Q_bar == 3'b111, "Test 49");
#0
J = 3'b011;
K = 3'b101;
#15
Preset_bar = 3'b000;
#25
Preset_bar = 3'b111;
#7
Clk = 3'b000;
#7
Clear_bar = 3'b010;
#7
tbassert(Q == 3'b010, "Test 50");
tbassert(Q_bar == 3'b101, "Test 50");
#15
Clear_bar = 3'b111;
#25
Clk = 3'b111;
#15
Clk = 3'b000;
#7
tbassert(Q == 3'b011, "Test 51");
tbassert(Q_bar == 3'b100, "Test 51");
#15
Clk = 3'b111;
#0
J = 3'b011;
K = 3'b100;
#15
Clk = 3'b001;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b011, "Test 51");
tbassert(Q_bar == 3'b100, "Test 51");
#0
J = 3'b101;
K = 3'b010;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b101, "Test 52");
tbassert(Q_bar == 3'b010, "Test 52");
#0
J = 3'b000;
K = 3'b000;
#7
Clk = 3'b000;
#25
Clk = 3'b111;
#15
tbassert(Q == 3'b101, "Test 52");
tbassert(Q_bar == 3'b010, "Test 52");
#0
J = 3'b101;
K = 3'b010;
#7
Clk = 3'b011;
#20
tbassert(Q == 3'b101, "Test 53");
tbassert(Q_bar == 3'b010, "Test 53");
#0
Clk = 3'b000;
#20
tbassert(Q == 3'b101, "Test 53");
tbassert(Q_bar == 3'b010, "Test 53");
#0
Clk = 3'b111;
#15
Clk = 3'b000;
#7
J = 3'b011;
K = 3'b101;
#75
tbassert(Q == 3'b101, "Test 54");
tbassert(Q_bar == 3'b010, "Test 54");
#0
Clk = 3'b111;
#25
J = 3'bzz0;
K = 3'bz01;
#50
tbassert(Q == 3'b101, "Test 54");
tbassert(Q_bar == 3'b010, "Test 54");
#0
J = 3'bz10;
K = 3'bz11;
#40
Clk = 3'b110;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b100, "Test 55");
tbassert(Q_bar == 3'b011, "Test 55");
#0
J = 3'b100;
K = 3'b011;
#7
Clk = 3'b110;
#20
tbassert(Q == 3'b100, "Test 56");
tbassert(Q_bar == 3'b011, "Test 56");
#0
Clk = 3'b001;
#40
tbassert(Q == 3'b100, "Test 57");
tbassert(Q_bar == 3'b011, "Test 57");
#0
Clk = 3'b111;
#15
J = 3'b011;
K = 3'b011;
#40
Clk = 3'b011;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b100, "Test 58");
tbassert(Q_bar == 3'b011, "Test 58");
#0
#40
Clk = 3'b110;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b101, "Test 59");
tbassert(Q_bar == 3'b010, "Test 59");
#50
$finish;
end
endmodule | 84 |
6,247 | data/full_repos/permissive/115837888/source-7400/74139.v | 115,837,888 | 74139.v | v | 36 | 86 | [] | [] | [] | null | line:19: before: "+" | null | 1: b"%Error: data/full_repos/permissive/115837888/source-7400/74139.v:32: Define or directive not defined: '`ASSIGN_UNPACK_ARRAY'\n`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74139.v:32: syntax error, unexpected '('\n`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)\n ^~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74139.v:33: Define or directive not defined: '`PACK_ARRAY'\nassign #(DELAY_RISE, DELAY_FALL) Y_2D = `PACK_ARRAY(BLOCKS, WIDTH_OUT, computed)\n ^~~~~~~~~~~\n%Error: Cannot continue\n" | 7,064 | module | module ttl_74139 #(parameter BLOCKS = 2, WIDTH_OUT = 4, WIDTH_IN = $clog2(WIDTH_OUT),
DELAY_RISE = 0, DELAY_FALL = 0)
(
input [BLOCKS-1:0] Enable_bar,
input [BLOCKS*WIDTH_IN-1:0] A_2D,
output [BLOCKS*WIDTH_OUT-1:0] Y_2D
);
wire [WIDTH_IN-1:0] A [0:BLOCKS-1];
reg [WIDTH_OUT-1:0] computed [0:BLOCKS-1];
integer i;
integer j;
always @(*)
begin
for (i = 0; i < BLOCKS; i++)
begin
for (j = 0; j < WIDTH_OUT; j++)
begin
if (!Enable_bar[i] && j == A[i])
computed[i][j] = 1'b0;
else
computed[i][j] = 1'b1;
end
end
end
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y_2D = `PACK_ARRAY(BLOCKS, WIDTH_OUT, computed)
endmodule | module ttl_74139 #(parameter BLOCKS = 2, WIDTH_OUT = 4, WIDTH_IN = $clog2(WIDTH_OUT),
DELAY_RISE = 0, DELAY_FALL = 0)
(
input [BLOCKS-1:0] Enable_bar,
input [BLOCKS*WIDTH_IN-1:0] A_2D,
output [BLOCKS*WIDTH_OUT-1:0] Y_2D
); |
wire [WIDTH_IN-1:0] A [0:BLOCKS-1];
reg [WIDTH_OUT-1:0] computed [0:BLOCKS-1];
integer i;
integer j;
always @(*)
begin
for (i = 0; i < BLOCKS; i++)
begin
for (j = 0; j < WIDTH_OUT; j++)
begin
if (!Enable_bar[i] && j == A[i])
computed[i][j] = 1'b0;
else
computed[i][j] = 1'b1;
end
end
end
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y_2D = `PACK_ARRAY(BLOCKS, WIDTH_OUT, computed)
endmodule | 84 |
6,248 | data/full_repos/permissive/115837888/source-7400/74147-tb.v | 115,837,888 | 74147-tb.v | v | 129 | 96 | [] | [] | [] | null | line:5: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/74147-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74147-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74147-tb.v:24: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("74147-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74147-tb.v:25: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Error: Exiting due to 4 error(s), 36 warning(s)\n' | 7,065 | module | module test;
`TBASSERT_METHOD(tbassert)
localparam WIDTH_IN = 9;
localparam WIDTH_OUT = 4;
reg [WIDTH_IN-1:0] A_bar;
wire [WIDTH_OUT-1:0] Y_bar;
ttl_74147 #(.DELAY_RISE(5), .DELAY_FALL(3)) dut(
.A_bar(A_bar),
.Y_bar(Y_bar)
);
initial
begin
$dumpfile("74147-tb.vcd");
$dumpvars;
A_bar = 9'b000000000;
#6
tbassert(Y_bar == ~4'b1001, "Test 1");
#0
A_bar = 9'b111111111;
#6
tbassert(Y_bar == ~4'b0000, "Test 2");
#0
A_bar = 9'b111011111;
#6
tbassert(Y_bar == ~4'b0110, "Test 3");
#0
A_bar = 9'b111010101;
#6
tbassert(Y_bar == ~4'b0110, "Test 4");
#0
A_bar = 9'b111110101;
#6
tbassert(Y_bar == ~4'b0100, "Test 5");
#0
A_bar = 9'b111111110;
#6
tbassert(Y_bar == ~4'b0001, "Test 6");
#0
A_bar = 9'b101111110;
#6
tbassert(Y_bar == ~4'b1000, "Test 7");
#0
A_bar = 9'b010000001;
#6
tbassert(Y_bar == ~4'b1001, "Test 8");
#0
A_bar = 9'b011111111;
#6
tbassert(Y_bar == ~4'b1001, "Test 9");
#0
A_bar = 9'b110101100;
#6
tbassert(Y_bar == ~4'b0111, "Test 10");
#0
A_bar = 9'b110000111;
#6
tbassert(Y_bar == ~4'b0111, "Test 10");
#0
A_bar = 9'b111111111;
#6
tbassert(Y_bar == ~4'b0000, "Test 11");
#0
A_bar = 9'b111000110;
#6
tbassert(Y_bar == ~4'b0110, "Test 11");
#0
A_bar = 9'b111111111;
#6
tbassert(Y_bar == ~4'b0000, "Test 12");
#0
A_bar = 9'b011111111;
#6
tbassert(Y_bar == ~4'b1001, "Test 13");
#0
A_bar = 9'b0zz0zz000;
#6
tbassert(Y_bar == ~4'b1001, "Test 14");
#0
A_bar = 9'b1110z01zz;
#6
tbassert(Y_bar == ~4'b0110, "Test 15");
#0
A_bar = 9'b11111110z;
#6
tbassert(Y_bar == ~4'b0010, "Test 16");
#10
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
localparam WIDTH_IN = 9;
localparam WIDTH_OUT = 4;
reg [WIDTH_IN-1:0] A_bar;
wire [WIDTH_OUT-1:0] Y_bar;
ttl_74147 #(.DELAY_RISE(5), .DELAY_FALL(3)) dut(
.A_bar(A_bar),
.Y_bar(Y_bar)
);
initial
begin
$dumpfile("74147-tb.vcd");
$dumpvars;
A_bar = 9'b000000000;
#6
tbassert(Y_bar == ~4'b1001, "Test 1");
#0
A_bar = 9'b111111111;
#6
tbassert(Y_bar == ~4'b0000, "Test 2");
#0
A_bar = 9'b111011111;
#6
tbassert(Y_bar == ~4'b0110, "Test 3");
#0
A_bar = 9'b111010101;
#6
tbassert(Y_bar == ~4'b0110, "Test 4");
#0
A_bar = 9'b111110101;
#6
tbassert(Y_bar == ~4'b0100, "Test 5");
#0
A_bar = 9'b111111110;
#6
tbassert(Y_bar == ~4'b0001, "Test 6");
#0
A_bar = 9'b101111110;
#6
tbassert(Y_bar == ~4'b1000, "Test 7");
#0
A_bar = 9'b010000001;
#6
tbassert(Y_bar == ~4'b1001, "Test 8");
#0
A_bar = 9'b011111111;
#6
tbassert(Y_bar == ~4'b1001, "Test 9");
#0
A_bar = 9'b110101100;
#6
tbassert(Y_bar == ~4'b0111, "Test 10");
#0
A_bar = 9'b110000111;
#6
tbassert(Y_bar == ~4'b0111, "Test 10");
#0
A_bar = 9'b111111111;
#6
tbassert(Y_bar == ~4'b0000, "Test 11");
#0
A_bar = 9'b111000110;
#6
tbassert(Y_bar == ~4'b0110, "Test 11");
#0
A_bar = 9'b111111111;
#6
tbassert(Y_bar == ~4'b0000, "Test 12");
#0
A_bar = 9'b011111111;
#6
tbassert(Y_bar == ~4'b1001, "Test 13");
#0
A_bar = 9'b0zz0zz000;
#6
tbassert(Y_bar == ~4'b1001, "Test 14");
#0
A_bar = 9'b1110z01zz;
#6
tbassert(Y_bar == ~4'b0110, "Test 15");
#0
A_bar = 9'b11111110z;
#6
tbassert(Y_bar == ~4'b0010, "Test 16");
#10
$finish;
end
endmodule | 84 |
6,249 | data/full_repos/permissive/115837888/source-7400/74147.v | 115,837,888 | 74147.v | v | 33 | 90 | [] | [] | [] | null | line:30: before: "," | data/verilator_xmls/dafe6585-7714-4e18-9d3e-c503bb8d1d17.xml | null | 7,066 | module | module ttl_74147 #(parameter WIDTH_IN = 9, WIDTH_OUT = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
input [WIDTH_IN-1:0] A_bar,
output [WIDTH_OUT-1:0] Y_bar
);
reg [WIDTH_OUT-1:0] computed;
always @(*)
begin
casez (A_bar)
9'b0????????: computed = 4'b1001;
9'b10???????: computed = 4'b1000;
9'b110??????: computed = 4'b0111;
9'b1110?????: computed = 4'b0110;
9'b11110????: computed = 4'b0101;
9'b111110???: computed = 4'b0100;
9'b1111110??: computed = 4'b0011;
9'b11111110?: computed = 4'b0010;
9'b111111110: computed = 4'b0001;
9'b111111111: computed = 4'b0000;
default: computed = 4'b0000;
endcase
end
assign #(DELAY_RISE, DELAY_FALL) Y_bar = ~computed;
endmodule | module ttl_74147 #(parameter WIDTH_IN = 9, WIDTH_OUT = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
input [WIDTH_IN-1:0] A_bar,
output [WIDTH_OUT-1:0] Y_bar
); |
reg [WIDTH_OUT-1:0] computed;
always @(*)
begin
casez (A_bar)
9'b0????????: computed = 4'b1001;
9'b10???????: computed = 4'b1000;
9'b110??????: computed = 4'b0111;
9'b1110?????: computed = 4'b0110;
9'b11110????: computed = 4'b0101;
9'b111110???: computed = 4'b0100;
9'b1111110??: computed = 4'b0011;
9'b11111110?: computed = 4'b0010;
9'b111111110: computed = 4'b0001;
9'b111111111: computed = 4'b0000;
default: computed = 4'b0000;
endcase
end
assign #(DELAY_RISE, DELAY_FALL) Y_bar = ~computed;
endmodule | 84 |
6,252 | data/full_repos/permissive/115837888/source-7400/74150-tb.v | 115,837,888 | 74150-tb.v | v | 181 | 93 | [] | [] | [] | null | line:5: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/74150-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74150-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74150-tb.v:30: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("74150-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74150-tb.v:31: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74150-tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Error: Exiting due to 4 error(s), 51 warning(s)\n' | 7,069 | module | module test;
`TBASSERT_METHOD(tbassert)
localparam WIDTH_IN = 5;
localparam WIDTH_SELECT = $clog2(WIDTH_IN);
reg Enable_bar;
reg [WIDTH_SELECT-1:0] Select;
reg [WIDTH_IN-1:0] D;
wire Y_bar;
ttl_74150 #(.WIDTH_IN(WIDTH_IN), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Enable_bar(Enable_bar),
.Select(Select),
.D(D),
.Y_bar(Y_bar)
);
initial
begin
$dumpfile("74150-tb.vcd");
$dumpvars;
Enable_bar = 1'b0;
Select = 3'b000;
D = 5'b01011;
#6
tbassert(Y_bar == 1'b0, "Test 1");
#0
Enable_bar = 1'b1;
#6
tbassert(Y_bar == 1'b1, "Test 2");
#0
Select = 3'b011;
#10
tbassert(Y_bar == 1'b1, "Test 3");
#0
Enable_bar = 1'b0;
#10
tbassert(Y_bar == 1'b0, "Test 4");
#0
Select = 3'b100;
#10
tbassert(Y_bar == 1'b1, "Test 5");
#0
Enable_bar = 1'b1;
#10
tbassert(Y_bar == 1'b1, "Test 6");
#0
Select = 3'b001;
#10
tbassert(Y_bar == 1'b1, "Test 7");
#0
Enable_bar = 1'b0;
#10
tbassert(Y_bar == 1'b0, "Test 8");
#0
Select = 3'b000;
#10
tbassert(Y_bar == 1'b0, "Test 9");
#0
Select = 3'b001;
#10
tbassert(Y_bar == 1'b0, "Test 10");
Select = 3'b100;
#10
tbassert(Y_bar == 1'b1, "Test 10");
#0
D = 5'b11110;
#10
tbassert(Y_bar == 1'b0, "Test 11");
#0
Select = 3'b000;
#10
tbassert(Y_bar == 1'b1, "Test 12");
#0
Enable_bar = 1'b1;
#6
tbassert(Y_bar == 1'b1, "Test 13");
#0
Select = 3'b010;
#10
tbassert(Y_bar == 1'b1, "Test 14");
#0
Enable_bar = 1'b0;
D = 5'b00000;
#10
tbassert(Y_bar == 1'b1, "Test 15");
#0
Select = 3'b100;
#10
tbassert(Y_bar == 1'b1, "Test 16");
#0
D = 5'b11111;
#6
tbassert(Y_bar == 1'b0, "Test 17");
#0
D = 5'b00010;
#10
tbassert(Y_bar == 1'b1, "Test 18");
Select = 3'b001;
#6
tbassert(Y_bar == 1'b0, "Test 18");
#0
Enable_bar = 1'b1;
#10
tbassert(Y_bar == 1'b1, "Test 19");
#0
Enable_bar = 1'b0;
#10
tbassert(Y_bar == 1'b0, "Test 20");
D = 5'b11110;
#10
tbassert(Y_bar == 1'b0, "Test 20");
#0
Select = 3'b010;
D = 5'b10101;
#10
tbassert(Y_bar == 1'b0, "Test 21");
#0
Select = 3'b011;
D = 5'b01010;
#10
tbassert(Y_bar == 1'b0, "Test 22");
#0
Enable_bar = 1'b0;
Select = 3'b101;
D = 5'b11111;
#10
tbassert(Y_bar === 1'bx, "Test 23");
#0
Enable_bar = 1'b0;
Select = 3'b111;
D = 5'b00000;
#10
tbassert(Y_bar === 1'bx, "Test 24");
#10
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
localparam WIDTH_IN = 5;
localparam WIDTH_SELECT = $clog2(WIDTH_IN);
reg Enable_bar;
reg [WIDTH_SELECT-1:0] Select;
reg [WIDTH_IN-1:0] D;
wire Y_bar;
ttl_74150 #(.WIDTH_IN(WIDTH_IN), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Enable_bar(Enable_bar),
.Select(Select),
.D(D),
.Y_bar(Y_bar)
);
initial
begin
$dumpfile("74150-tb.vcd");
$dumpvars;
Enable_bar = 1'b0;
Select = 3'b000;
D = 5'b01011;
#6
tbassert(Y_bar == 1'b0, "Test 1");
#0
Enable_bar = 1'b1;
#6
tbassert(Y_bar == 1'b1, "Test 2");
#0
Select = 3'b011;
#10
tbassert(Y_bar == 1'b1, "Test 3");
#0
Enable_bar = 1'b0;
#10
tbassert(Y_bar == 1'b0, "Test 4");
#0
Select = 3'b100;
#10
tbassert(Y_bar == 1'b1, "Test 5");
#0
Enable_bar = 1'b1;
#10
tbassert(Y_bar == 1'b1, "Test 6");
#0
Select = 3'b001;
#10
tbassert(Y_bar == 1'b1, "Test 7");
#0
Enable_bar = 1'b0;
#10
tbassert(Y_bar == 1'b0, "Test 8");
#0
Select = 3'b000;
#10
tbassert(Y_bar == 1'b0, "Test 9");
#0
Select = 3'b001;
#10
tbassert(Y_bar == 1'b0, "Test 10");
Select = 3'b100;
#10
tbassert(Y_bar == 1'b1, "Test 10");
#0
D = 5'b11110;
#10
tbassert(Y_bar == 1'b0, "Test 11");
#0
Select = 3'b000;
#10
tbassert(Y_bar == 1'b1, "Test 12");
#0
Enable_bar = 1'b1;
#6
tbassert(Y_bar == 1'b1, "Test 13");
#0
Select = 3'b010;
#10
tbassert(Y_bar == 1'b1, "Test 14");
#0
Enable_bar = 1'b0;
D = 5'b00000;
#10
tbassert(Y_bar == 1'b1, "Test 15");
#0
Select = 3'b100;
#10
tbassert(Y_bar == 1'b1, "Test 16");
#0
D = 5'b11111;
#6
tbassert(Y_bar == 1'b0, "Test 17");
#0
D = 5'b00010;
#10
tbassert(Y_bar == 1'b1, "Test 18");
Select = 3'b001;
#6
tbassert(Y_bar == 1'b0, "Test 18");
#0
Enable_bar = 1'b1;
#10
tbassert(Y_bar == 1'b1, "Test 19");
#0
Enable_bar = 1'b0;
#10
tbassert(Y_bar == 1'b0, "Test 20");
D = 5'b11110;
#10
tbassert(Y_bar == 1'b0, "Test 20");
#0
Select = 3'b010;
D = 5'b10101;
#10
tbassert(Y_bar == 1'b0, "Test 21");
#0
Select = 3'b011;
D = 5'b01010;
#10
tbassert(Y_bar == 1'b0, "Test 22");
#0
Enable_bar = 1'b0;
Select = 3'b101;
D = 5'b11111;
#10
tbassert(Y_bar === 1'bx, "Test 23");
#0
Enable_bar = 1'b0;
Select = 3'b111;
D = 5'b00000;
#10
tbassert(Y_bar === 1'bx, "Test 24");
#10
$finish;
end
endmodule | 84 |
6,255 | data/full_repos/permissive/115837888/source-7400/74154-tb.v | 115,837,888 | 74154-tb.v | v | 193 | 94 | [] | [] | [] | null | line:5: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/74154-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74154-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74154-tb.v:6: Define or directive not defined: \'`TBASSERT_2_METHOD\'\n`TBASSERT_2_METHOD(tbassert2)\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74154-tb.v:33: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("74154-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74154-tb.v:34: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:181: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Error: Exiting due to 5 error(s), 30 warning(s)\n' | 7,075 | module | module test;
`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)
localparam WIDTH_OUT = 16;
localparam WIDTH_IN = $clog2(WIDTH_OUT);
reg Enable1_bar;
reg Enable2_bar;
reg [WIDTH_IN-1:0] A;
wire [WIDTH_OUT-1:0] Y;
ttl_74154 #(.WIDTH_OUT(WIDTH_OUT), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Enable1_bar(Enable1_bar),
.Enable2_bar(Enable2_bar),
.A(A),
.Y(Y)
);
initial
begin
reg [WIDTH_OUT-1:0] Y_expected;
integer i;
$dumpfile("74154-tb.vcd");
$dumpvars;
Enable1_bar = 1'b0;
Enable2_bar = 1'b0;
A = 4'b0000;
#6
tbassert(Y == 16'b1111111111111110, "Test 1");
#0
Enable2_bar = 1'b1;
#6
tbassert(Y == 16'b1111111111111111, "Test 2");
#0
Enable1_bar = 1'b1;
#6
tbassert(Y == 16'b1111111111111111, "Test 3");
#0
Enable2_bar = 1'b0;
#6
tbassert(Y == 16'b1111111111111111, "Test 4");
#0
A = 4'b0001;
#6
tbassert(Y == 16'b1111111111111111, "Test 5");
#0
Enable1_bar = 1'b0;
#10
tbassert(Y == 16'b1111111111111101, "Test 6");
#0
Enable1_bar = 1'b1;
Enable2_bar = 1'b1;
A = 4'b0011;
#10
tbassert(Y == 16'b1111111111111111, "Test 7");
#0
Enable1_bar = 1'b0;
Enable2_bar = 1'b0;
#10
tbassert(Y == 16'b1111111111110111, "Test 7");
#0
A = 4'b1111;
#10
tbassert(Y == 16'b0111111111111111, "Test 8");
#0
for (i = 14; i >= 0; i--)
begin
A = i;
case (i)
14:
begin
Y_expected = 16'b1011111111111111;
end
13:
begin
Y_expected = 16'b1101111111111111;
end
12:
begin
Y_expected = 16'b1110111111111111;
end
11:
begin
Y_expected = 16'b1111011111111111;
end
10:
begin
Y_expected = 16'b1111101111111111;
end
9:
begin
Y_expected = 16'b1111110111111111;
end
8:
begin
Y_expected = 16'b1111111011111111;
end
7:
begin
Y_expected = 16'b1111111101111111;
end
6:
begin
Y_expected = 16'b1111111110111111;
end
5:
begin
Y_expected = 16'b1111111111011111;
end
4:
begin
Y_expected = 16'b1111111111101111;
end
3:
begin
Y_expected = 16'b1111111111110111;
end
2:
begin
Y_expected = 16'b1111111111111011;
end
1:
begin
Y_expected = 16'b1111111111111101;
end
0:
begin
Y_expected = 16'b1111111111111110;
end
endcase
#10
tbassert2(Y == Y_expected, "Test", (15 - i), "9");
end
#0
Enable1_bar = 1'b1;
Enable2_bar = 1'b1;
#6
tbassert(Y == 16'b1111111111111111, "Test 10");
#0
A = 4'b0101;
#6
tbassert(Y == 16'b1111111111111111, "Test 10");
#0
A = 4'b1010;
#6
tbassert(Y == 16'b1111111111111111, "Test 11");
#0
Enable1_bar = 1'b0;
Enable2_bar = 1'b0;
A = 4'b0101;
#6
tbassert(Y == 16'b1111111111011111, "Test 12");
#0
A = 4'b1010;
#6
tbassert(Y == 16'b1111101111111111, "Test 13");
#10
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)
localparam WIDTH_OUT = 16;
localparam WIDTH_IN = $clog2(WIDTH_OUT);
reg Enable1_bar;
reg Enable2_bar;
reg [WIDTH_IN-1:0] A;
wire [WIDTH_OUT-1:0] Y;
ttl_74154 #(.WIDTH_OUT(WIDTH_OUT), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Enable1_bar(Enable1_bar),
.Enable2_bar(Enable2_bar),
.A(A),
.Y(Y)
);
initial
begin
reg [WIDTH_OUT-1:0] Y_expected;
integer i;
$dumpfile("74154-tb.vcd");
$dumpvars;
Enable1_bar = 1'b0;
Enable2_bar = 1'b0;
A = 4'b0000;
#6
tbassert(Y == 16'b1111111111111110, "Test 1");
#0
Enable2_bar = 1'b1;
#6
tbassert(Y == 16'b1111111111111111, "Test 2");
#0
Enable1_bar = 1'b1;
#6
tbassert(Y == 16'b1111111111111111, "Test 3");
#0
Enable2_bar = 1'b0;
#6
tbassert(Y == 16'b1111111111111111, "Test 4");
#0
A = 4'b0001;
#6
tbassert(Y == 16'b1111111111111111, "Test 5");
#0
Enable1_bar = 1'b0;
#10
tbassert(Y == 16'b1111111111111101, "Test 6");
#0
Enable1_bar = 1'b1;
Enable2_bar = 1'b1;
A = 4'b0011;
#10
tbassert(Y == 16'b1111111111111111, "Test 7");
#0
Enable1_bar = 1'b0;
Enable2_bar = 1'b0;
#10
tbassert(Y == 16'b1111111111110111, "Test 7");
#0
A = 4'b1111;
#10
tbassert(Y == 16'b0111111111111111, "Test 8");
#0
for (i = 14; i >= 0; i--)
begin
A = i;
case (i)
14:
begin
Y_expected = 16'b1011111111111111;
end
13:
begin
Y_expected = 16'b1101111111111111;
end
12:
begin
Y_expected = 16'b1110111111111111;
end
11:
begin
Y_expected = 16'b1111011111111111;
end
10:
begin
Y_expected = 16'b1111101111111111;
end
9:
begin
Y_expected = 16'b1111110111111111;
end
8:
begin
Y_expected = 16'b1111111011111111;
end
7:
begin
Y_expected = 16'b1111111101111111;
end
6:
begin
Y_expected = 16'b1111111110111111;
end
5:
begin
Y_expected = 16'b1111111111011111;
end
4:
begin
Y_expected = 16'b1111111111101111;
end
3:
begin
Y_expected = 16'b1111111111110111;
end
2:
begin
Y_expected = 16'b1111111111111011;
end
1:
begin
Y_expected = 16'b1111111111111101;
end
0:
begin
Y_expected = 16'b1111111111111110;
end
endcase
#10
tbassert2(Y == Y_expected, "Test", (15 - i), "9");
end
#0
Enable1_bar = 1'b1;
Enable2_bar = 1'b1;
#6
tbassert(Y == 16'b1111111111111111, "Test 10");
#0
A = 4'b0101;
#6
tbassert(Y == 16'b1111111111111111, "Test 10");
#0
A = 4'b1010;
#6
tbassert(Y == 16'b1111111111111111, "Test 11");
#0
Enable1_bar = 1'b0;
Enable2_bar = 1'b0;
A = 4'b0101;
#6
tbassert(Y == 16'b1111111111011111, "Test 12");
#0
A = 4'b1010;
#6
tbassert(Y == 16'b1111101111111111, "Test 13");
#10
$finish;
end
endmodule | 84 |
6,256 | data/full_repos/permissive/115837888/source-7400/74154.v | 115,837,888 | 74154.v | v | 31 | 75 | [] | [] | [] | null | line:18: before: "+" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/115837888/source-7400/74154.v:20: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'A\' generates 4 bits.\n : ... In instance ttl_74154\n if (!Enable1_bar && !Enable2_bar && i == A)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 7,076 | module | module ttl_74154 #(parameter WIDTH_OUT = 16, WIDTH_IN = $clog2(WIDTH_OUT),
DELAY_RISE = 0, DELAY_FALL = 0)
(
input Enable1_bar,
input Enable2_bar,
input [WIDTH_IN-1:0] A,
output [WIDTH_OUT-1:0] Y
);
reg [WIDTH_OUT-1:0] computed;
integer i;
always @(*)
begin
for (i = 0; i < WIDTH_OUT; i++)
begin
if (!Enable1_bar && !Enable2_bar && i == A)
computed[i] = 1'b0;
else
computed[i] = 1'b1;
end
end
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule | module ttl_74154 #(parameter WIDTH_OUT = 16, WIDTH_IN = $clog2(WIDTH_OUT),
DELAY_RISE = 0, DELAY_FALL = 0)
(
input Enable1_bar,
input Enable2_bar,
input [WIDTH_IN-1:0] A,
output [WIDTH_OUT-1:0] Y
); |
reg [WIDTH_OUT-1:0] computed;
integer i;
always @(*)
begin
for (i = 0; i < WIDTH_OUT; i++)
begin
if (!Enable1_bar && !Enable2_bar && i == A)
computed[i] = 1'b0;
else
computed[i] = 1'b1;
end
end
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule | 84 |
6,257 | data/full_repos/permissive/115837888/source-7400/74155-tb.v | 115,837,888 | 74155-tb.v | v | 301 | 100 | [] | [] | [] | null | line:5: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/74155-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74155-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74155-tb.v:6: Define or directive not defined: \'`TBASSERT_2_METHOD\'\n`TBASSERT_2_METHOD(tbassert2)\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74155-tb.v:41: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("74155-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74155-tb.v:42: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:198: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:206: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:246: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:254: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:261: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:265: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:267: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:271: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:274: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:278: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:285: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:289: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:292: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74155-tb.v:296: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Error: Exiting due to 5 error(s), 42 warning(s)\n' | 7,077 | module | module test;
`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)
localparam BLOCKS_DIFFERENT = 2;
localparam WIDTH_OUT = 8;
localparam WIDTH_IN = $clog2(WIDTH_OUT);
reg Enable1C;
reg Enable1G_bar;
reg Enable2C_bar;
reg Enable2G_bar;
reg [WIDTH_IN-1:0] A;
wire [BLOCKS_DIFFERENT*WIDTH_OUT-1:0] Y;
ttl_74155 #(.BLOCKS_DIFFERENT(BLOCKS_DIFFERENT), .WIDTH_OUT(WIDTH_OUT),
.DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Enable1C(Enable1C),
.Enable1G_bar(Enable1G_bar),
.Enable2C_bar(Enable2C_bar),
.Enable2G_bar(Enable2G_bar),
.A(A),
.Y_2D(Y)
);
initial
begin
reg [WIDTH_OUT-1:0] Block1;
reg [WIDTH_OUT-1:0] Block2;
reg [WIDTH_OUT-1:0] Y_expected;
integer i;
$dumpfile("74155-tb.vcd");
$dumpvars;
Enable1C = 1'b1;
Enable1G_bar = 1'b0;
Enable2C_bar = 1'b0;
Enable2G_bar = 1'b0;
A = 3'b000;
#6
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111110, "Test 1");
tbassert(Block2 == 8'b11111110, "Test 1");
#0
Enable1C = 1'b0;
#6
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 2");
tbassert(Block2 == 8'b11111110, "Test 2");
#0
Enable1C = 1'b1;
Enable2C_bar = 1'b1;
#6
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111110, "Test 3");
tbassert(Block2 == 8'b11111111, "Test 3");
#0
Enable2C_bar = 1'b0;
Enable2G_bar = 1'b1;
#6
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111110, "Test 4");
tbassert(Block2 == 8'b11111111, "Test 4");
#0
Enable1C = 1'b0;
Enable1G_bar = 1'b1;
Enable2C_bar = 1'b1;
Enable2G_bar = 1'b1;
A = 3'b001;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 5");
tbassert(Block2 == 8'b11111111, "Test 5");
#0
Enable2C_bar = 1'b0;
Enable2G_bar = 1'b0;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 6");
tbassert(Block2 == 8'b11111101, "Test 6");
#0
Enable1G_bar = 1'b0;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 7");
tbassert(Block2 == 8'b11111101, "Test 7");
#0
Enable1C = 1'b1;
Enable1G_bar = 1'b1;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 8");
tbassert(Block2 == 8'b11111101, "Test 8");
#0
Enable1G_bar = 1'b0;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111101, "Test 9");
tbassert(Block2 == 8'b11111101, "Test 9");
#0
Enable1C = 1'b0;
Enable2G_bar = 1'b1;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 9");
tbassert(Block2 == 8'b11111111, "Test 9");
#0
Enable1C = 1'b1;
Enable1G_bar = 1'b1;
Enable2C_bar = 1'b0;
Enable2G_bar = 1'b1;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 10");
tbassert(Block2 == 8'b11111111, "Test 10");
#0
Enable1C = 1'b0;
Enable1G_bar = 1'b0;
Enable2C_bar = 1'b1;
Enable2G_bar = 1'b0;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 10");
tbassert(Block2 == 8'b11111111, "Test 10");
#0
Enable1C = 1'b1;
Enable2C_bar = 1'b0;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111101, "Test 11");
tbassert(Block2 == 8'b11111101, "Test 11");
#0
A = 3'b111;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b01111111, "Test 12");
tbassert(Block2 == 8'b01111111, "Test 12");
#0
for (i = 6; i >= 0; i--)
begin
A = i;
case (i)
6:
begin
Y_expected = 8'b10111111;
end
5:
begin
Y_expected = 8'b11011111;
end
4:
begin
Y_expected = 8'b11101111;
end
3:
begin
Y_expected = 8'b11110111;
end
2:
begin
Y_expected = 8'b11111011;
end
1:
begin
Y_expected = 8'b11111101;
end
0:
begin
Y_expected = 8'b11111110;
end
endcase
#10
{Block2, Block1} = Y;
tbassert2(Block1 == Y_expected, "Test", (7 - i), "13");
tbassert2(Block2 == Y_expected, "Test", (7 - i), "13");
end
#0
Enable1C = 1'b0;
for (i = 6; i >= 0; i--)
begin
A = i;
case (i)
6:
begin
Y_expected = 8'b10111111;
end
5:
begin
Y_expected = 8'b11011111;
end
4:
begin
Y_expected = 8'b11101111;
end
3:
begin
Y_expected = 8'b11110111;
end
2:
begin
Y_expected = 8'b11111011;
end
1:
begin
Y_expected = 8'b11111101;
end
0:
begin
Y_expected = 8'b11111110;
end
endcase
#10
{Block2, Block1} = Y;
tbassert2(Block1 == 8'b11111111, "Test", (7 - i), "14");
tbassert2(Block2 == Y_expected, "Test", (7 - i), "14");
end
#0
Enable1C = 1'b0;
Enable1G_bar = 1'b1;
Enable2C_bar = 1'b1;
Enable2G_bar = 1'b1;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 15");
tbassert(Block2 == 8'b11111111, "Test 15");
#0
A = 3'b101;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 15");
tbassert(Block2 == 8'b11111111, "Test 15");
#0
A = 3'b010;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 16");
tbassert(Block2 == 8'b11111111, "Test 16");
#0
Enable1C = 1'b1;
Enable1G_bar = 1'b0;
Enable2C_bar = 1'b0;
Enable2G_bar = 1'b0;
A = 3'b101;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11011111, "Test 17");
tbassert(Block2 == 8'b11011111, "Test 17");
#0
A = 3'b010;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111011, "Test 18");
tbassert(Block2 == 8'b11111011, "Test 18");
#10
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)
localparam BLOCKS_DIFFERENT = 2;
localparam WIDTH_OUT = 8;
localparam WIDTH_IN = $clog2(WIDTH_OUT);
reg Enable1C;
reg Enable1G_bar;
reg Enable2C_bar;
reg Enable2G_bar;
reg [WIDTH_IN-1:0] A;
wire [BLOCKS_DIFFERENT*WIDTH_OUT-1:0] Y;
ttl_74155 #(.BLOCKS_DIFFERENT(BLOCKS_DIFFERENT), .WIDTH_OUT(WIDTH_OUT),
.DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Enable1C(Enable1C),
.Enable1G_bar(Enable1G_bar),
.Enable2C_bar(Enable2C_bar),
.Enable2G_bar(Enable2G_bar),
.A(A),
.Y_2D(Y)
);
initial
begin
reg [WIDTH_OUT-1:0] Block1;
reg [WIDTH_OUT-1:0] Block2;
reg [WIDTH_OUT-1:0] Y_expected;
integer i;
$dumpfile("74155-tb.vcd");
$dumpvars;
Enable1C = 1'b1;
Enable1G_bar = 1'b0;
Enable2C_bar = 1'b0;
Enable2G_bar = 1'b0;
A = 3'b000;
#6
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111110, "Test 1");
tbassert(Block2 == 8'b11111110, "Test 1");
#0
Enable1C = 1'b0;
#6
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 2");
tbassert(Block2 == 8'b11111110, "Test 2");
#0
Enable1C = 1'b1;
Enable2C_bar = 1'b1;
#6
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111110, "Test 3");
tbassert(Block2 == 8'b11111111, "Test 3");
#0
Enable2C_bar = 1'b0;
Enable2G_bar = 1'b1;
#6
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111110, "Test 4");
tbassert(Block2 == 8'b11111111, "Test 4");
#0
Enable1C = 1'b0;
Enable1G_bar = 1'b1;
Enable2C_bar = 1'b1;
Enable2G_bar = 1'b1;
A = 3'b001;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 5");
tbassert(Block2 == 8'b11111111, "Test 5");
#0
Enable2C_bar = 1'b0;
Enable2G_bar = 1'b0;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 6");
tbassert(Block2 == 8'b11111101, "Test 6");
#0
Enable1G_bar = 1'b0;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 7");
tbassert(Block2 == 8'b11111101, "Test 7");
#0
Enable1C = 1'b1;
Enable1G_bar = 1'b1;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 8");
tbassert(Block2 == 8'b11111101, "Test 8");
#0
Enable1G_bar = 1'b0;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111101, "Test 9");
tbassert(Block2 == 8'b11111101, "Test 9");
#0
Enable1C = 1'b0;
Enable2G_bar = 1'b1;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 9");
tbassert(Block2 == 8'b11111111, "Test 9");
#0
Enable1C = 1'b1;
Enable1G_bar = 1'b1;
Enable2C_bar = 1'b0;
Enable2G_bar = 1'b1;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 10");
tbassert(Block2 == 8'b11111111, "Test 10");
#0
Enable1C = 1'b0;
Enable1G_bar = 1'b0;
Enable2C_bar = 1'b1;
Enable2G_bar = 1'b0;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 10");
tbassert(Block2 == 8'b11111111, "Test 10");
#0
Enable1C = 1'b1;
Enable2C_bar = 1'b0;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111101, "Test 11");
tbassert(Block2 == 8'b11111101, "Test 11");
#0
A = 3'b111;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b01111111, "Test 12");
tbassert(Block2 == 8'b01111111, "Test 12");
#0
for (i = 6; i >= 0; i--)
begin
A = i;
case (i)
6:
begin
Y_expected = 8'b10111111;
end
5:
begin
Y_expected = 8'b11011111;
end
4:
begin
Y_expected = 8'b11101111;
end
3:
begin
Y_expected = 8'b11110111;
end
2:
begin
Y_expected = 8'b11111011;
end
1:
begin
Y_expected = 8'b11111101;
end
0:
begin
Y_expected = 8'b11111110;
end
endcase
#10
{Block2, Block1} = Y;
tbassert2(Block1 == Y_expected, "Test", (7 - i), "13");
tbassert2(Block2 == Y_expected, "Test", (7 - i), "13");
end
#0
Enable1C = 1'b0;
for (i = 6; i >= 0; i--)
begin
A = i;
case (i)
6:
begin
Y_expected = 8'b10111111;
end
5:
begin
Y_expected = 8'b11011111;
end
4:
begin
Y_expected = 8'b11101111;
end
3:
begin
Y_expected = 8'b11110111;
end
2:
begin
Y_expected = 8'b11111011;
end
1:
begin
Y_expected = 8'b11111101;
end
0:
begin
Y_expected = 8'b11111110;
end
endcase
#10
{Block2, Block1} = Y;
tbassert2(Block1 == 8'b11111111, "Test", (7 - i), "14");
tbassert2(Block2 == Y_expected, "Test", (7 - i), "14");
end
#0
Enable1C = 1'b0;
Enable1G_bar = 1'b1;
Enable2C_bar = 1'b1;
Enable2G_bar = 1'b1;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 15");
tbassert(Block2 == 8'b11111111, "Test 15");
#0
A = 3'b101;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 15");
tbassert(Block2 == 8'b11111111, "Test 15");
#0
A = 3'b010;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111111, "Test 16");
tbassert(Block2 == 8'b11111111, "Test 16");
#0
Enable1C = 1'b1;
Enable1G_bar = 1'b0;
Enable2C_bar = 1'b0;
Enable2G_bar = 1'b0;
A = 3'b101;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11011111, "Test 17");
tbassert(Block2 == 8'b11011111, "Test 17");
#0
A = 3'b010;
#10
{Block2, Block1} = Y;
tbassert(Block1 == 8'b11111011, "Test 18");
tbassert(Block2 == 8'b11111011, "Test 18");
#10
$finish;
end
endmodule | 84 |
6,258 | data/full_repos/permissive/115837888/source-7400/74157-tb.v | 115,837,888 | 74157-tb.v | v | 255 | 88 | [] | [] | [] | null | line:5: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/74157-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74157-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74157-tb.v:37: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("74157-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74157-tb.v:38: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:146: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n#3\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:192: Unsupported: Ignoring delay on this delayed statement.\n#3\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:202: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:207: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:209: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n#3\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:213: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:223: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:228: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:230: Unsupported: Ignoring delay on this delayed statement.\n#3\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:232: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:239: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:241: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:246: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:248: Unsupported: Ignoring delay on this delayed statement.\n#3\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74157-tb.v:250: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Error: Exiting due to 4 error(s), 60 warning(s)\n' | 7,079 | module | module test;
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 3;
localparam WIDTH_IN = 2;
localparam WIDTH_SELECT = $clog2(WIDTH_IN);
reg Enable_bar;
reg [WIDTH_SELECT-1:0] Select;
reg [BLOCKS*WIDTH_IN-1:0] A;
wire [BLOCKS-1:0] Y;
ttl_74157 #(.BLOCKS(BLOCKS), .WIDTH_IN(WIDTH_IN), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Enable_bar(Enable_bar),
.Select(Select),
.A_2D(A),
.Y(Y)
);
localparam SELECT_A = 1'b0;
localparam SELECT_B = 1'b1;
initial
begin
reg [WIDTH_IN-1:0] Block1;
reg [WIDTH_IN-1:0] Block2;
reg [WIDTH_IN-1:0] Block3;
$dumpfile("74157-tb.vcd");
$dumpvars;
Enable_bar = 1'b0;
Select = SELECT_A;
Block1 = 2'b11;
Block2 = 2'b11;
Block3 = 2'b10;
A = {Block3, Block2, Block1};
#6
tbassert(Y == 3'b011, "Test 1");
#0
Enable_bar = 1'b1;
#6
tbassert(Y == 3'b000, "Test 2");
#0
Select = SELECT_B;
#10
tbassert(Y == 3'b000, "Test 3");
#0
Enable_bar = 1'b0;
#10
tbassert(Y == 3'b111, "Test 4");
#0
Select = SELECT_A;
#10
tbassert(Y == 3'b011, "Test 5");
#0
Block1 = 2'b10;
Block2 = 2'b01;
Block3 = 2'b01;
A = {Block3, Block2, Block1};
#10
tbassert(Y == 3'b110, "Test 6");
#0
Select = SELECT_B;
#10
tbassert(Y == 3'b001, "Test 7");
#0
Enable_bar = 1'b1;
#6
tbassert(Y == 3'b000, "Test 8");
#0
Select = SELECT_A;
#10
tbassert(Y == 3'b000, "Test 9");
#0
Enable_bar = 1'b0;
Block1 = 2'b10;
Block2 = 2'b00;
Block3 = 2'b00;
A = {Block3, Block2, Block1};
#10
tbassert(Y == 3'b000, "Test 10");
#0
Select = SELECT_B;
Block1 = 2'b00;
Block2 = 2'b01;
Block3 = 2'b00;
A = {Block3, Block2, Block1};
#10
tbassert(Y == 3'b000, "Test 11");
#0
Block1 = 2'b10;
Block2 = 2'b11;
Block3 = 2'b10;
A = {Block3, Block2, Block1};
#6
tbassert(Y == 3'b111, "Test 12");
#0
Block1 = 2'b01;
Block2 = 2'b10;
Block3 = 2'b10;
A = {Block3, Block2, Block1};
#6
tbassert(Y == 3'b110, "Test 13");
#0
Select = SELECT_A;
#6
tbassert(Y == 3'b001, "Test 13");
#0
Block1 = 2'b01;
Block2 = 2'b11;
Block3 = 2'b11;
A = {Block3, Block2, Block1};
#6
tbassert(Y == 3'b111, "Test 14");
#0
Enable_bar = 1'b1;
#10
tbassert(Y == 3'b000, "Test 14");
#0
Enable_bar = 1'b0;
#6
tbassert(Y == 3'b111, "Test 15");
#10
Select = SELECT_B;
Block1 = 2'b10;
Block2 = 2'b10;
Block3 = 2'b10;
A = {Block3, Block2, Block1};
#10
tbassert(Y == 3'b111, "Test 15");
#0
Enable_bar = 1'b0;
Select = 1'bx;
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
A = {Block3, Block2, Block1};
#10
Select = SELECT_A;
Block1 = 2'b11;
Block2 = 2'b01;
Block3 = 2'b10;
A = {Block3, Block2, Block1};
#2
tbassert(Y === 3'bxxx, "Test 16");
#3
tbassert(Y == 3'b011, "Test 16");
#0
Enable_bar = 1'b0;
Select = 1'bx;
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
A = {Block3, Block2, Block1};
#10
Block1 = 2'b11;
Block2 = 2'b01;
Block3 = 2'b10;
A = {Block3, Block2, Block1};
#6
Select = SELECT_A;
#2
tbassert(Y === 3'bxxx, "Test 17");
#3
tbassert(Y == 3'b011, "Test 17");
#0
Enable_bar = 1'b0;
Select = 1'bx;
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
A = {Block3, Block2, Block1};
#10
Block1 = 2'b10;
Block2 = 2'b11;
Block3 = 2'b11;
A = {Block3, Block2, Block1};
#6
Select = SELECT_B;
#2
tbassert(Y === 3'bxxx, "Test 18");
#3
tbassert(Y == 3'b111, "Test 18");
#0
Select = 1'bx;
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
A = {Block3, Block2, Block1};
#10
Select = SELECT_B;
#6
Block1 = 2'b11;
Block2 = 2'b01;
Block3 = 2'b10;
A = {Block3, Block2, Block1};
#2
tbassert(Y === 3'bxxx, "Test 19");
#3
tbassert(Y == 3'b101, "Test 19");
#0
Select = 1'bx;
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
A = {Block3, Block2, Block1};
#10
Select = SELECT_A;
#6
Block1[0] = 1'b1;
Block2[0] = 1'b1;
Block3[0] = 1'b0;
A = {Block3, Block2, Block1};
#2
tbassert(Y === 3'bxxx, "Test 20");
#3
tbassert(Y == 3'b011, "Test 20");
#10
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 3;
localparam WIDTH_IN = 2;
localparam WIDTH_SELECT = $clog2(WIDTH_IN);
reg Enable_bar;
reg [WIDTH_SELECT-1:0] Select;
reg [BLOCKS*WIDTH_IN-1:0] A;
wire [BLOCKS-1:0] Y;
ttl_74157 #(.BLOCKS(BLOCKS), .WIDTH_IN(WIDTH_IN), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Enable_bar(Enable_bar),
.Select(Select),
.A_2D(A),
.Y(Y)
);
localparam SELECT_A = 1'b0;
localparam SELECT_B = 1'b1;
initial
begin
reg [WIDTH_IN-1:0] Block1;
reg [WIDTH_IN-1:0] Block2;
reg [WIDTH_IN-1:0] Block3;
$dumpfile("74157-tb.vcd");
$dumpvars;
Enable_bar = 1'b0;
Select = SELECT_A;
Block1 = 2'b11;
Block2 = 2'b11;
Block3 = 2'b10;
A = {Block3, Block2, Block1};
#6
tbassert(Y == 3'b011, "Test 1");
#0
Enable_bar = 1'b1;
#6
tbassert(Y == 3'b000, "Test 2");
#0
Select = SELECT_B;
#10
tbassert(Y == 3'b000, "Test 3");
#0
Enable_bar = 1'b0;
#10
tbassert(Y == 3'b111, "Test 4");
#0
Select = SELECT_A;
#10
tbassert(Y == 3'b011, "Test 5");
#0
Block1 = 2'b10;
Block2 = 2'b01;
Block3 = 2'b01;
A = {Block3, Block2, Block1};
#10
tbassert(Y == 3'b110, "Test 6");
#0
Select = SELECT_B;
#10
tbassert(Y == 3'b001, "Test 7");
#0
Enable_bar = 1'b1;
#6
tbassert(Y == 3'b000, "Test 8");
#0
Select = SELECT_A;
#10
tbassert(Y == 3'b000, "Test 9");
#0
Enable_bar = 1'b0;
Block1 = 2'b10;
Block2 = 2'b00;
Block3 = 2'b00;
A = {Block3, Block2, Block1};
#10
tbassert(Y == 3'b000, "Test 10");
#0
Select = SELECT_B;
Block1 = 2'b00;
Block2 = 2'b01;
Block3 = 2'b00;
A = {Block3, Block2, Block1};
#10
tbassert(Y == 3'b000, "Test 11");
#0
Block1 = 2'b10;
Block2 = 2'b11;
Block3 = 2'b10;
A = {Block3, Block2, Block1};
#6
tbassert(Y == 3'b111, "Test 12");
#0
Block1 = 2'b01;
Block2 = 2'b10;
Block3 = 2'b10;
A = {Block3, Block2, Block1};
#6
tbassert(Y == 3'b110, "Test 13");
#0
Select = SELECT_A;
#6
tbassert(Y == 3'b001, "Test 13");
#0
Block1 = 2'b01;
Block2 = 2'b11;
Block3 = 2'b11;
A = {Block3, Block2, Block1};
#6
tbassert(Y == 3'b111, "Test 14");
#0
Enable_bar = 1'b1;
#10
tbassert(Y == 3'b000, "Test 14");
#0
Enable_bar = 1'b0;
#6
tbassert(Y == 3'b111, "Test 15");
#10
Select = SELECT_B;
Block1 = 2'b10;
Block2 = 2'b10;
Block3 = 2'b10;
A = {Block3, Block2, Block1};
#10
tbassert(Y == 3'b111, "Test 15");
#0
Enable_bar = 1'b0;
Select = 1'bx;
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
A = {Block3, Block2, Block1};
#10
Select = SELECT_A;
Block1 = 2'b11;
Block2 = 2'b01;
Block3 = 2'b10;
A = {Block3, Block2, Block1};
#2
tbassert(Y === 3'bxxx, "Test 16");
#3
tbassert(Y == 3'b011, "Test 16");
#0
Enable_bar = 1'b0;
Select = 1'bx;
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
A = {Block3, Block2, Block1};
#10
Block1 = 2'b11;
Block2 = 2'b01;
Block3 = 2'b10;
A = {Block3, Block2, Block1};
#6
Select = SELECT_A;
#2
tbassert(Y === 3'bxxx, "Test 17");
#3
tbassert(Y == 3'b011, "Test 17");
#0
Enable_bar = 1'b0;
Select = 1'bx;
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
A = {Block3, Block2, Block1};
#10
Block1 = 2'b10;
Block2 = 2'b11;
Block3 = 2'b11;
A = {Block3, Block2, Block1};
#6
Select = SELECT_B;
#2
tbassert(Y === 3'bxxx, "Test 18");
#3
tbassert(Y == 3'b111, "Test 18");
#0
Select = 1'bx;
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
A = {Block3, Block2, Block1};
#10
Select = SELECT_B;
#6
Block1 = 2'b11;
Block2 = 2'b01;
Block3 = 2'b10;
A = {Block3, Block2, Block1};
#2
tbassert(Y === 3'bxxx, "Test 19");
#3
tbassert(Y == 3'b101, "Test 19");
#0
Select = 1'bx;
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
A = {Block3, Block2, Block1};
#10
Select = SELECT_A;
#6
Block1[0] = 1'b1;
Block2[0] = 1'b1;
Block3[0] = 1'b0;
A = {Block3, Block2, Block1};
#2
tbassert(Y === 3'bxxx, "Test 20");
#3
tbassert(Y == 3'b011, "Test 20");
#10
$finish;
end
endmodule | 84 |
6,261 | data/full_repos/permissive/115837888/source-7400/74162-tb.v | 115,837,888 | 74162-tb.v | v | 540 | 96 | [] | [] | [] | null | line:5: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:6: Define or directive not defined: \'`TBASSERT_2_METHOD\'\n`TBASSERT_2_METHOD(tbassert2)\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:7: Define or directive not defined: \'`CASE_TBASSERT_2_METHOD\'\n`CASE_TBASSERT_2_METHOD(case_tbassert2, tbassert2)\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:8: Define or directive not defined: \'`TBCLK_WAIT_TICK_METHOD\'\n`TBCLK_WAIT_TICK_METHOD(wait_tick)\n^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:38: Unsupported: Ignoring delay on this delayed statement.\nalways #50 Clk = ~Clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:43: syntax error, unexpected \'@\'\n repeat (2) @(posedge Clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:54: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("74162-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:55: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n#225\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n#110\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n#110\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n#105\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n#95\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:191: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n#22\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:198: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:202: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:205: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:208: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:216: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:218: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n#97\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:223: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:226: Unsupported: Ignoring delay on this delayed statement.\n#97\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:229: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:233: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:236: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:239: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:241: Unsupported: Ignoring delay on this delayed statement.\n#80\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:244: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:251: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:254: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:257: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:260: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:264: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:267: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:270: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:273: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:276: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:279: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:281: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:284: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:287: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:290: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:293: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:296: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:298: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:301: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:304: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:307: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:313: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:310: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:316: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:318: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:321: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:324: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:327: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:330: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:332: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:335: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:338: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:341: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:344: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:347: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:349: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:352: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:355: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:358: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:363: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:367: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:370: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:373: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:376: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:380: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:383: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:387: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:390: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:393: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:396: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:400: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:404: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:407: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:410: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:413: Unsupported: Ignoring delay on this delayed statement.\n#200\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:416: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:419: Unsupported: Ignoring delay on this delayed statement.\n#85\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:422: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:425: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:429: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:432: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:435: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:438: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:441: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:444: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:447: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:450: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:453: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:457: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:460: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:464: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:467: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:469: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:472: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:485: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:488: Unsupported: Ignoring delay on this delayed statement.\n#80\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:475: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:496: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:506: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:509: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:516: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:522: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:524: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:526: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:529: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:531: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:533: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:535: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Error: Exiting due to 8 error(s), 131 warning(s)\n' | 7,087 | module | module test;
`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)
`CASE_TBASSERT_2_METHOD(case_tbassert2, tbassert2)
`TBCLK_WAIT_TICK_METHOD(wait_tick)
localparam WIDTH = 4;
reg Clear_bar;
reg Load_bar;
reg ENT;
reg ENP;
reg [WIDTH-1:0] D;
reg Clk;
wire RCO;
wire [WIDTH-1:0] Q;
ttl_74162 #(.DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Clear_bar(Clear_bar),
.Load_bar(Load_bar),
.ENT(ENT),
.ENP(ENP),
.D(D),
.Clk(Clk),
.RCO(RCO),
.Q(Q)
);
initial Clk = 1'b0;
always #50 Clk = ~Clk;
task parallel_load_and_tick(input [WIDTH-1:0] D_next);
Load_bar = 1'b0;
D = D_next;
repeat (2) @(posedge Clk);
#7
Load_bar = 1'b1;
endtask
initial
begin
reg [WIDTH-1:0] D_next;
reg [WIDTH-1:0] Q_expected;
integer i;
$dumpfile("74162-tb.vcd");
$dumpvars;
#225
tbassert(Q === 4'bxxxx, "Test 1");
tbassert(RCO === 1'bx, "Test 1");
#0
Load_bar = 1'b0;
D = 4'b0000;
#25
tbassert(Q === 4'bxxxx, "Test 1");
tbassert(RCO === 1'bx, "Test 1");
#2
tbassert(Q === 4'bxxxx, "Test 1");
tbassert(RCO === 1'bx, "Test 1");
#2
tbassert(Q == 4'b0000, "Test 1");
tbassert(RCO == 1'b0, "Test 1");
#140
Load_bar = 1'b1;
#175
tbassert(Q == 4'b0000, "Test 2");
tbassert(RCO == 1'b0, "Test 2");
#0
Load_bar = 1'b0;
ENT = 1'b1;
D = 4'b1111;
#125
Load_bar = 1'b1;
#110
tbassert(Q == 4'b1111, "Test 3");
tbassert(RCO == 1'b0, "Test 3");
#0
Load_bar = 1'b0;
D = 4'b1001;
#90
Load_bar = 1'b1;
#110
tbassert(Q == 4'b1001, "Test 4");
tbassert(RCO == 1'b1, "Test 4");
#0
D_next = 4'b1001;
for (i = 1; i <= 6; i++)
begin
Q_expected = D_next;
D_next = (Q_expected + 1) ^ 5;
case (i)
1:
begin
ENT = 1'b0;
end
2:
begin
ENT = 1'b0;
ENP = 1'b0;
end
3:
begin
ENT = 1'b1;
ENP = 1'b0;
end
4:
begin
ENT = 1'b0;
ENP = 1'b1;
end
5:
begin
Clear_bar = 1'b1;
ENT = 1'b0;
ENP = 1'b1;
end
6:
begin
Clear_bar = 1'b1;
ENT = 1'b1;
ENP = 1'b0;
end
endcase
#75
tbassert2(Q == Q_expected, "Test", i, "5");
tbassert2(RCO == 1'b0, "Test", i, "5");
#0
Load_bar = 1'b0;
D = D_next;
#100
tbassert2(Q == D_next, "Test", i, "5");
tbassert2(RCO == 1'b0, "Test", i, "5");
#0
Load_bar = 1'b1;
#105
tbassert2(Q == D_next, "Test", i, "5");
tbassert2(RCO == 1'b0, "Test", i, "5");
end
tbassert2(Q == 4'b1101, "Test", 6, "5");
#175
wait_tick();
#7
Clear_bar = 1'b0;
#95
tbassert(Q == 4'b1101, "Test 6");
tbassert(RCO == 1'b0, "Test 6");
#2
tbassert(Q == 4'b0000, "Test 6");
tbassert(RCO == 1'b0, "Test 6");
#150
Clear_bar = 1'b1;
#50
ENT = 1'b1;
parallel_load_and_tick(4'b1001);
#70
Clear_bar = 1'b0;
#22
tbassert(Q == 4'b1001, "Test 7");
tbassert(RCO == 1'b1, "Test 7");
#5
tbassert(Q == 4'b0000, "Test 7");
tbassert(RCO == 1'b0, "Test 7");
#10
Clear_bar = 1'b1;
#120
tbassert(Q == 4'b0000, "Test 8");
tbassert(RCO == 1'b0, "Test 8");
#50
Clear_bar = 1'bx;
Load_bar = 1'bx;
ENT = 1'bx;
ENP = 1'bx;
#15
parallel_load_and_tick(4'bxxxx);
#0
Load_bar = 1'bx;
#97
tbassert(Q === 4'bxxxx, "Test 9");
tbassert(RCO === 1'bx, "Test 9");
#0
Clear_bar = 1'b0;
#97
tbassert(Q === 4'bxxxx, "Test 9");
tbassert(RCO === 1'bx, "Test 9");
#2
tbassert(Q == 4'b0000, "Test 9");
tbassert(RCO == 1'b0, "Test 9");
#15
Clear_bar = 1'b1;
#120
tbassert(Q == 4'b0000, "Test 10");
tbassert(RCO == 1'b0, "Test 10");
#0
Load_bar = 1'b1;
#80
tbassert(Q == 4'b0000, "Test 10");
tbassert(RCO == 1'b0, "Test 10");
#0
ENT = 1'b0;
ENP = 1'b1;
#7
tbassert(Q == 4'b0000, "Test 11");
tbassert(RCO == 1'b0, "Test 11");
#50
tbassert(Q == 4'b0000, "Test 11");
tbassert(RCO == 1'b0, "Test 11");
#100
tbassert(Q == 4'b0000, "Test 11");
tbassert(RCO == 1'b0, "Test 11");
#15
ENT = 1'b1;
ENP = 1'b0;
#7
tbassert(Q == 4'b0000, "Test 12");
tbassert(RCO == 1'b0, "Test 12");
#50
tbassert(Q == 4'b0000, "Test 12");
tbassert(RCO == 1'b0, "Test 12");
#100
tbassert(Q == 4'b0000, "Test 12");
tbassert(RCO == 1'b0, "Test 12");
#0
wait_tick();
#15
Load_bar = 1'b0;
D = 4'b1110;
#15
Load_bar = 1'b1;
#7
tbassert(Q == 4'b0000, "Test 13");
tbassert(RCO == 1'b0, "Test 13");
#50
tbassert(Q == 4'b0000, "Test 13");
tbassert(RCO == 1'b0, "Test 13");
#100
tbassert(Q == 4'b0000, "Test 13");
tbassert(RCO == 1'b0, "Test 13");
#0
wait_tick();
#20
ENT = 1'b1;
ENP = 1'b1;
#15
ENT = 1'b0;
#15
tbassert(Q == 4'b0000, "Test 14");
tbassert(RCO == 1'b0, "Test 14");
#50
tbassert(Q == 4'b0000, "Test 14");
tbassert(RCO == 1'b0, "Test 14");
#100
tbassert(Q == 4'b0000, "Test 14");
tbassert(RCO == 1'b0, "Test 14");
#20
parallel_load_and_tick(4'b1001);
#50
#175
tbassert(Q == 4'b1001, "Test 15");
tbassert(RCO == 1'b0, "Test 15");
#0
ENP = 1'b0;
#50
tbassert(Q == 4'b1001, "Test 15");
tbassert(RCO == 1'b0, "Test 15");
#100
tbassert(Q == 4'b1001, "Test 15");
tbassert(RCO == 1'b0, "Test 15");
#0
wait_tick();
#25
Load_bar = 1'b0;
D = 4'b0010;
#15
Load_bar = 1'b1;
#7
tbassert(Q == 4'b1001, "Test 16");
tbassert(RCO == 1'b0, "Test 16");
#50
tbassert(Q == 4'b1001, "Test 16");
tbassert(RCO == 1'b0, "Test 16");
#100
tbassert(Q == 4'b1001, "Test 16");
tbassert(RCO == 1'b0, "Test 16");
#0
wait_tick();
#15
ENT = 1'b1;
ENP = 1'b1;
#15
ENT = 1'b0;
#7
tbassert(Q == 4'b1001, "Test 17");
tbassert(RCO == 1'b0, "Test 17");
#50
tbassert(Q == 4'b1001, "Test 17");
tbassert(RCO == 1'b0, "Test 17");
#100
tbassert(Q == 4'b1001, "Test 17");
tbassert(RCO == 1'b0, "Test 17");
#0
wait_tick();
#10
ENT = 1'b1;
ENP = 1'b1;
#40
tbassert(Q == 4'b1001, "Test 18");
tbassert(RCO == 1'b1, "Test 18");
#50
tbassert(Q == 4'b1001, "Test 18");
tbassert(RCO == 1'b1, "Test 18");
#7
tbassert(Q == 4'b0000, "Test 18");
tbassert(RCO == 1'b0, "Test 18");
#90
tbassert(Q == 4'b0000, "Test 19");
tbassert(RCO == 1'b0, "Test 19");
#10
tbassert(Q == 4'b0001, "Test 19");
tbassert(RCO == 1'b0, "Test 19");
#90
tbassert(Q == 4'b0001, "Test 20");
tbassert(RCO == 1'b0, "Test 20");
#10
tbassert(Q == 4'b0010, "Test 20");
tbassert(RCO == 1'b0, "Test 20");
#7
parallel_load_and_tick(4'b0111);
#0
tbassert(Q == 4'b0111, "Test 21");
tbassert(RCO == 1'b0, "Test 21");
#100
tbassert(Q == 4'b1000, "Test 22");
tbassert(RCO == 1'b0, "Test 22");
#100
tbassert(Q == 4'b1001, "Test 23");
tbassert(RCO == 1'b1, "Test 23");
#0
ENP = 1'b0;
#50
tbassert(Q == 4'b1001, "Test 24");
tbassert(RCO == 1'b1, "Test 24");
#50
tbassert(Q == 4'b1001, "Test 24");
tbassert(RCO == 1'b1, "Test 24");
#200
tbassert(Q == 4'b1001, "Test 24");
tbassert(RCO == 1'b1, "Test 24");
#0
ENP = 1'b1;
#85
tbassert(Q == 4'b1001, "Test 25");
tbassert(RCO == 1'b1, "Test 25");
#15
tbassert(Q == 4'b0000, "Test 25");
tbassert(RCO == 1'b0, "Test 25");
#100
tbassert(Q == 4'b0001, "Test 26");
tbassert(RCO == 1'b0, "Test 26");
#0
Clear_bar = 1'b0;
#90
tbassert(Q == 4'b0001, "Test 27");
tbassert(RCO == 1'b0, "Test 27");
#10
tbassert(Q == 4'b0000, "Test 27");
tbassert(RCO == 1'b0, "Test 27");
#0
Clear_bar = 1'b1;
#90
tbassert(Q == 4'b0000, "Test 28");
tbassert(RCO == 1'b0, "Test 28");
#10
tbassert(Q == 4'b0001, "Test 28");
tbassert(RCO == 1'b0, "Test 28");
#50
Clear_bar = 1'b0;
#50
Clear_bar = 1'b1;
parallel_load_and_tick(4'b0101);
#90
tbassert(Q == 4'b0101, "Test 29");
tbassert(RCO == 1'b0, "Test 29");
#10
tbassert(Q == 4'b0110, "Test 29");
tbassert(RCO == 1'b0, "Test 29");
#20
ENP = 1'b0;
#50
tbassert(Q == 4'b0110, "Test 30");
tbassert(RCO == 1'b0, "Test 30");
#0
ENP = 1'b1;
#2
tbassert(Q == 4'b0110, "Test 30");
tbassert(RCO == 1'b0, "Test 30");
#50
tbassert(Q == 4'b0111, "Test 30");
tbassert(RCO == 1'b0, "Test 30");
#0
for (i = 10; i <= 15; i++)
begin
parallel_load_and_tick(i);
#20
tbassert2(Q > 4'b1001, "Test", (i - 9), "31");
tbassert2(RCO == 1'b0, "Test", (i - 9), "31");
#80
tbassert2(Q >= 0 && Q <= 4'b1001, "Test", (i - 9), "31");
case_tbassert2(Q < 4'b1001, RCO == 1'b0, "Test", (i - 9), "31");
case_tbassert2(Q == 4'b1001, RCO == 1'b1, "Test", (i - 9), "31");
end
#0
ENT = 1'b1;
ENP = 1'b0;
for (i = 10; i <= 15; i++)
begin
parallel_load_and_tick(i);
#20
tbassert2(Q > 4'b1001, "Test", (i - 9), "32");
tbassert2(RCO == 1'b0, "Test", (i - 9), "32");
#120
tbassert2(Q > 4'b1001, "Test", (i - 9), "32");
tbassert2(RCO == 1'b0, "Test", (i - 9), "32");
end
#0
ENT = 1'b0;
ENP = 1'b1;
parallel_load_and_tick(4'b1001);
#100
tbassert(RCO == 1'b0, "Test 33");
#10
ENT = 1'b1;
#15
tbassert(Q == 4'b1001, "Test 33");
tbassert(RCO == 1'b1, "Test 33");
#0
ENT = 1'b0;
#15
tbassert(RCO == 1'b0, "Test 33");
#0
wait_tick();
#50
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)
`CASE_TBASSERT_2_METHOD(case_tbassert2, tbassert2)
`TBCLK_WAIT_TICK_METHOD(wait_tick)
localparam WIDTH = 4;
reg Clear_bar;
reg Load_bar;
reg ENT;
reg ENP;
reg [WIDTH-1:0] D;
reg Clk;
wire RCO;
wire [WIDTH-1:0] Q;
ttl_74162 #(.DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Clear_bar(Clear_bar),
.Load_bar(Load_bar),
.ENT(ENT),
.ENP(ENP),
.D(D),
.Clk(Clk),
.RCO(RCO),
.Q(Q)
);
initial Clk = 1'b0;
always #50 Clk = ~Clk;
task parallel_load_and_tick(input [WIDTH-1:0] D_next);
Load_bar = 1'b0;
D = D_next;
repeat (2) @(posedge Clk);
#7
Load_bar = 1'b1;
endtask
initial
begin
reg [WIDTH-1:0] D_next;
reg [WIDTH-1:0] Q_expected;
integer i;
$dumpfile("74162-tb.vcd");
$dumpvars;
#225
tbassert(Q === 4'bxxxx, "Test 1");
tbassert(RCO === 1'bx, "Test 1");
#0
Load_bar = 1'b0;
D = 4'b0000;
#25
tbassert(Q === 4'bxxxx, "Test 1");
tbassert(RCO === 1'bx, "Test 1");
#2
tbassert(Q === 4'bxxxx, "Test 1");
tbassert(RCO === 1'bx, "Test 1");
#2
tbassert(Q == 4'b0000, "Test 1");
tbassert(RCO == 1'b0, "Test 1");
#140
Load_bar = 1'b1;
#175
tbassert(Q == 4'b0000, "Test 2");
tbassert(RCO == 1'b0, "Test 2");
#0
Load_bar = 1'b0;
ENT = 1'b1;
D = 4'b1111;
#125
Load_bar = 1'b1;
#110
tbassert(Q == 4'b1111, "Test 3");
tbassert(RCO == 1'b0, "Test 3");
#0
Load_bar = 1'b0;
D = 4'b1001;
#90
Load_bar = 1'b1;
#110
tbassert(Q == 4'b1001, "Test 4");
tbassert(RCO == 1'b1, "Test 4");
#0
D_next = 4'b1001;
for (i = 1; i <= 6; i++)
begin
Q_expected = D_next;
D_next = (Q_expected + 1) ^ 5;
case (i)
1:
begin
ENT = 1'b0;
end
2:
begin
ENT = 1'b0;
ENP = 1'b0;
end
3:
begin
ENT = 1'b1;
ENP = 1'b0;
end
4:
begin
ENT = 1'b0;
ENP = 1'b1;
end
5:
begin
Clear_bar = 1'b1;
ENT = 1'b0;
ENP = 1'b1;
end
6:
begin
Clear_bar = 1'b1;
ENT = 1'b1;
ENP = 1'b0;
end
endcase
#75
tbassert2(Q == Q_expected, "Test", i, "5");
tbassert2(RCO == 1'b0, "Test", i, "5");
#0
Load_bar = 1'b0;
D = D_next;
#100
tbassert2(Q == D_next, "Test", i, "5");
tbassert2(RCO == 1'b0, "Test", i, "5");
#0
Load_bar = 1'b1;
#105
tbassert2(Q == D_next, "Test", i, "5");
tbassert2(RCO == 1'b0, "Test", i, "5");
end
tbassert2(Q == 4'b1101, "Test", 6, "5");
#175
wait_tick();
#7
Clear_bar = 1'b0;
#95
tbassert(Q == 4'b1101, "Test 6");
tbassert(RCO == 1'b0, "Test 6");
#2
tbassert(Q == 4'b0000, "Test 6");
tbassert(RCO == 1'b0, "Test 6");
#150
Clear_bar = 1'b1;
#50
ENT = 1'b1;
parallel_load_and_tick(4'b1001);
#70
Clear_bar = 1'b0;
#22
tbassert(Q == 4'b1001, "Test 7");
tbassert(RCO == 1'b1, "Test 7");
#5
tbassert(Q == 4'b0000, "Test 7");
tbassert(RCO == 1'b0, "Test 7");
#10
Clear_bar = 1'b1;
#120
tbassert(Q == 4'b0000, "Test 8");
tbassert(RCO == 1'b0, "Test 8");
#50
Clear_bar = 1'bx;
Load_bar = 1'bx;
ENT = 1'bx;
ENP = 1'bx;
#15
parallel_load_and_tick(4'bxxxx);
#0
Load_bar = 1'bx;
#97
tbassert(Q === 4'bxxxx, "Test 9");
tbassert(RCO === 1'bx, "Test 9");
#0
Clear_bar = 1'b0;
#97
tbassert(Q === 4'bxxxx, "Test 9");
tbassert(RCO === 1'bx, "Test 9");
#2
tbassert(Q == 4'b0000, "Test 9");
tbassert(RCO == 1'b0, "Test 9");
#15
Clear_bar = 1'b1;
#120
tbassert(Q == 4'b0000, "Test 10");
tbassert(RCO == 1'b0, "Test 10");
#0
Load_bar = 1'b1;
#80
tbassert(Q == 4'b0000, "Test 10");
tbassert(RCO == 1'b0, "Test 10");
#0
ENT = 1'b0;
ENP = 1'b1;
#7
tbassert(Q == 4'b0000, "Test 11");
tbassert(RCO == 1'b0, "Test 11");
#50
tbassert(Q == 4'b0000, "Test 11");
tbassert(RCO == 1'b0, "Test 11");
#100
tbassert(Q == 4'b0000, "Test 11");
tbassert(RCO == 1'b0, "Test 11");
#15
ENT = 1'b1;
ENP = 1'b0;
#7
tbassert(Q == 4'b0000, "Test 12");
tbassert(RCO == 1'b0, "Test 12");
#50
tbassert(Q == 4'b0000, "Test 12");
tbassert(RCO == 1'b0, "Test 12");
#100
tbassert(Q == 4'b0000, "Test 12");
tbassert(RCO == 1'b0, "Test 12");
#0
wait_tick();
#15
Load_bar = 1'b0;
D = 4'b1110;
#15
Load_bar = 1'b1;
#7
tbassert(Q == 4'b0000, "Test 13");
tbassert(RCO == 1'b0, "Test 13");
#50
tbassert(Q == 4'b0000, "Test 13");
tbassert(RCO == 1'b0, "Test 13");
#100
tbassert(Q == 4'b0000, "Test 13");
tbassert(RCO == 1'b0, "Test 13");
#0
wait_tick();
#20
ENT = 1'b1;
ENP = 1'b1;
#15
ENT = 1'b0;
#15
tbassert(Q == 4'b0000, "Test 14");
tbassert(RCO == 1'b0, "Test 14");
#50
tbassert(Q == 4'b0000, "Test 14");
tbassert(RCO == 1'b0, "Test 14");
#100
tbassert(Q == 4'b0000, "Test 14");
tbassert(RCO == 1'b0, "Test 14");
#20
parallel_load_and_tick(4'b1001);
#50
#175
tbassert(Q == 4'b1001, "Test 15");
tbassert(RCO == 1'b0, "Test 15");
#0
ENP = 1'b0;
#50
tbassert(Q == 4'b1001, "Test 15");
tbassert(RCO == 1'b0, "Test 15");
#100
tbassert(Q == 4'b1001, "Test 15");
tbassert(RCO == 1'b0, "Test 15");
#0
wait_tick();
#25
Load_bar = 1'b0;
D = 4'b0010;
#15
Load_bar = 1'b1;
#7
tbassert(Q == 4'b1001, "Test 16");
tbassert(RCO == 1'b0, "Test 16");
#50
tbassert(Q == 4'b1001, "Test 16");
tbassert(RCO == 1'b0, "Test 16");
#100
tbassert(Q == 4'b1001, "Test 16");
tbassert(RCO == 1'b0, "Test 16");
#0
wait_tick();
#15
ENT = 1'b1;
ENP = 1'b1;
#15
ENT = 1'b0;
#7
tbassert(Q == 4'b1001, "Test 17");
tbassert(RCO == 1'b0, "Test 17");
#50
tbassert(Q == 4'b1001, "Test 17");
tbassert(RCO == 1'b0, "Test 17");
#100
tbassert(Q == 4'b1001, "Test 17");
tbassert(RCO == 1'b0, "Test 17");
#0
wait_tick();
#10
ENT = 1'b1;
ENP = 1'b1;
#40
tbassert(Q == 4'b1001, "Test 18");
tbassert(RCO == 1'b1, "Test 18");
#50
tbassert(Q == 4'b1001, "Test 18");
tbassert(RCO == 1'b1, "Test 18");
#7
tbassert(Q == 4'b0000, "Test 18");
tbassert(RCO == 1'b0, "Test 18");
#90
tbassert(Q == 4'b0000, "Test 19");
tbassert(RCO == 1'b0, "Test 19");
#10
tbassert(Q == 4'b0001, "Test 19");
tbassert(RCO == 1'b0, "Test 19");
#90
tbassert(Q == 4'b0001, "Test 20");
tbassert(RCO == 1'b0, "Test 20");
#10
tbassert(Q == 4'b0010, "Test 20");
tbassert(RCO == 1'b0, "Test 20");
#7
parallel_load_and_tick(4'b0111);
#0
tbassert(Q == 4'b0111, "Test 21");
tbassert(RCO == 1'b0, "Test 21");
#100
tbassert(Q == 4'b1000, "Test 22");
tbassert(RCO == 1'b0, "Test 22");
#100
tbassert(Q == 4'b1001, "Test 23");
tbassert(RCO == 1'b1, "Test 23");
#0
ENP = 1'b0;
#50
tbassert(Q == 4'b1001, "Test 24");
tbassert(RCO == 1'b1, "Test 24");
#50
tbassert(Q == 4'b1001, "Test 24");
tbassert(RCO == 1'b1, "Test 24");
#200
tbassert(Q == 4'b1001, "Test 24");
tbassert(RCO == 1'b1, "Test 24");
#0
ENP = 1'b1;
#85
tbassert(Q == 4'b1001, "Test 25");
tbassert(RCO == 1'b1, "Test 25");
#15
tbassert(Q == 4'b0000, "Test 25");
tbassert(RCO == 1'b0, "Test 25");
#100
tbassert(Q == 4'b0001, "Test 26");
tbassert(RCO == 1'b0, "Test 26");
#0
Clear_bar = 1'b0;
#90
tbassert(Q == 4'b0001, "Test 27");
tbassert(RCO == 1'b0, "Test 27");
#10
tbassert(Q == 4'b0000, "Test 27");
tbassert(RCO == 1'b0, "Test 27");
#0
Clear_bar = 1'b1;
#90
tbassert(Q == 4'b0000, "Test 28");
tbassert(RCO == 1'b0, "Test 28");
#10
tbassert(Q == 4'b0001, "Test 28");
tbassert(RCO == 1'b0, "Test 28");
#50
Clear_bar = 1'b0;
#50
Clear_bar = 1'b1;
parallel_load_and_tick(4'b0101);
#90
tbassert(Q == 4'b0101, "Test 29");
tbassert(RCO == 1'b0, "Test 29");
#10
tbassert(Q == 4'b0110, "Test 29");
tbassert(RCO == 1'b0, "Test 29");
#20
ENP = 1'b0;
#50
tbassert(Q == 4'b0110, "Test 30");
tbassert(RCO == 1'b0, "Test 30");
#0
ENP = 1'b1;
#2
tbassert(Q == 4'b0110, "Test 30");
tbassert(RCO == 1'b0, "Test 30");
#50
tbassert(Q == 4'b0111, "Test 30");
tbassert(RCO == 1'b0, "Test 30");
#0
for (i = 10; i <= 15; i++)
begin
parallel_load_and_tick(i);
#20
tbassert2(Q > 4'b1001, "Test", (i - 9), "31");
tbassert2(RCO == 1'b0, "Test", (i - 9), "31");
#80
tbassert2(Q >= 0 && Q <= 4'b1001, "Test", (i - 9), "31");
case_tbassert2(Q < 4'b1001, RCO == 1'b0, "Test", (i - 9), "31");
case_tbassert2(Q == 4'b1001, RCO == 1'b1, "Test", (i - 9), "31");
end
#0
ENT = 1'b1;
ENP = 1'b0;
for (i = 10; i <= 15; i++)
begin
parallel_load_and_tick(i);
#20
tbassert2(Q > 4'b1001, "Test", (i - 9), "32");
tbassert2(RCO == 1'b0, "Test", (i - 9), "32");
#120
tbassert2(Q > 4'b1001, "Test", (i - 9), "32");
tbassert2(RCO == 1'b0, "Test", (i - 9), "32");
end
#0
ENT = 1'b0;
ENP = 1'b1;
parallel_load_and_tick(4'b1001);
#100
tbassert(RCO == 1'b0, "Test 33");
#10
ENT = 1'b1;
#15
tbassert(Q == 4'b1001, "Test 33");
tbassert(RCO == 1'b1, "Test 33");
#0
ENT = 1'b0;
#15
tbassert(RCO == 1'b0, "Test 33");
#0
wait_tick();
#50
$finish;
end
endmodule | 84 |
6,262 | data/full_repos/permissive/115837888/source-7400/74163-tb.v | 115,837,888 | 74163-tb.v | v | 496 | 96 | [] | [] | [] | null | line:5: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/74163-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74163-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74163-tb.v:6: Define or directive not defined: \'`TBASSERT_2_METHOD\'\n`TBASSERT_2_METHOD(tbassert2)\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74163-tb.v:7: Define or directive not defined: \'`TBCLK_WAIT_TICK_METHOD\'\n`TBCLK_WAIT_TICK_METHOD(wait_tick)\n^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:37: Unsupported: Ignoring delay on this delayed statement.\nalways #50 Clk = ~Clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115837888/source-7400/74163-tb.v:42: syntax error, unexpected \'@\'\n repeat (2) @(posedge Clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Error: data/full_repos/permissive/115837888/source-7400/74163-tb.v:53: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("74163-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74163-tb.v:54: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n#225\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n#110\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:146: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n#105\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n#95\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:177: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n#22\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:199: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:207: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:209: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n#97\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:214: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:217: Unsupported: Ignoring delay on this delayed statement.\n#97\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:227: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:230: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:232: Unsupported: Ignoring delay on this delayed statement.\n#80\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:242: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:245: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:248: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:251: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:255: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:261: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:264: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:267: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:270: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:272: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:275: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:278: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:281: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:284: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:287: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:289: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:292: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:295: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:298: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:304: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:301: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:307: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:309: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:312: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:315: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:318: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:321: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:323: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:326: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:329: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:332: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:335: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:338: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:340: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:343: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:346: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:349: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:354: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:358: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:361: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:364: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:367: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:371: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:374: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:378: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:381: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:384: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:387: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:391: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:395: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:399: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:402: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:405: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:408: Unsupported: Ignoring delay on this delayed statement.\n#200\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:411: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:414: Unsupported: Ignoring delay on this delayed statement.\n#85\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:417: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:420: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:424: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:427: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:430: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:433: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:436: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:439: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:442: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:445: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:448: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:452: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:455: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:459: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:462: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:464: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:467: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:470: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:478: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:480: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:482: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:485: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:487: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:489: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:491: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Error: Exiting due to 7 error(s), 124 warning(s)\n' | 7,089 | module | module test;
`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)
`TBCLK_WAIT_TICK_METHOD(wait_tick)
localparam WIDTH = 3;
reg Clear_bar;
reg Load_bar;
reg ENT;
reg ENP;
reg [WIDTH-1:0] D;
reg Clk;
wire RCO;
wire [WIDTH-1:0] Q;
ttl_74163 #(.WIDTH(WIDTH), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Clear_bar(Clear_bar),
.Load_bar(Load_bar),
.ENT(ENT),
.ENP(ENP),
.D(D),
.Clk(Clk),
.RCO(RCO),
.Q(Q)
);
initial Clk = 1'b0;
always #50 Clk = ~Clk;
task parallel_load_and_tick(input [WIDTH-1:0] D_next);
Load_bar = 1'b0;
D = D_next;
repeat (2) @(posedge Clk);
#7
Load_bar = 1'b1;
endtask
initial
begin
reg [WIDTH-1:0] D_next;
reg [WIDTH-1:0] Q_expected;
integer i;
$dumpfile("74163-tb.vcd");
$dumpvars;
#225
tbassert(Q === 3'bxxx, "Test 1");
tbassert(RCO === 1'bx, "Test 1");
#0
Load_bar = 1'b0;
D = 3'b000;
#25
tbassert(Q === 3'bxxx, "Test 1");
tbassert(RCO === 1'bx, "Test 1");
#2
tbassert(Q === 3'bxxx, "Test 1");
tbassert(RCO === 1'bx, "Test 1");
#2
tbassert(Q == 3'b000, "Test 1");
tbassert(RCO == 1'b0, "Test 1");
#140
Load_bar = 1'b1;
#175
tbassert(Q == 3'b000, "Test 2");
tbassert(RCO == 1'b0, "Test 2");
#0
Load_bar = 1'b0;
ENT = 1'b1;
D = 3'b111;
#125
Load_bar = 1'b1;
#110
tbassert(Q == 3'b111, "Test 3");
tbassert(RCO == 1'b1, "Test 3");
#0
ENT = 1'b0;
#0
D_next = 3'b111;
for (i = 1; i <= 6; i++)
begin
Q_expected = D_next;
D_next = (Q_expected + 2) ^ 5;
case (i)
1:
begin
ENT = 1'b0;
end
2:
begin
ENT = 1'b0;
ENP = 1'b0;
end
3:
begin
ENT = 1'b1;
ENP = 1'b0;
end
4:
begin
ENT = 1'b0;
ENP = 1'b1;
end
5:
begin
Clear_bar = 1'b1;
ENT = 1'b0;
ENP = 1'b1;
end
6:
begin
Clear_bar = 1'b1;
ENT = 1'b1;
ENP = 1'b0;
end
endcase
#75
tbassert2(Q == Q_expected, "Test", i, "4");
tbassert2(RCO == 1'b0, "Test", i, "4");
#0
Load_bar = 1'b0;
D = D_next;
#100
tbassert2(Q == D_next, "Test", i, "4");
tbassert2(RCO == 1'b0, "Test", i, "4");
#0
Load_bar = 1'b1;
#105
tbassert2(Q == D_next, "Test", i, "4");
tbassert2(RCO == 1'b0, "Test", i, "4");
end
tbassert2(Q == 3'b011, "Test", 6, "4");
#175
wait_tick();
#7
Clear_bar = 1'b0;
#95
tbassert(Q == 3'b011, "Test 5");
tbassert(RCO == 1'b0, "Test 5");
#2
tbassert(Q == 3'b000, "Test 5");
tbassert(RCO == 1'b0, "Test 5");
#150
Clear_bar = 1'b1;
#50
ENT = 1'b1;
parallel_load_and_tick(3'b111);
#70
Clear_bar = 1'b0;
#22
tbassert(Q == 3'b111, "Test 6");
tbassert(RCO == 1'b1, "Test 6");
#5
tbassert(Q == 3'b000, "Test 6");
tbassert(RCO == 1'b0, "Test 6");
#10
Clear_bar = 1'b1;
#120
tbassert(Q == 3'b000, "Test 7");
tbassert(RCO == 1'b0, "Test 7");
#50
Clear_bar = 1'bx;
Load_bar = 1'bx;
ENT = 1'bx;
ENP = 1'bx;
#15
parallel_load_and_tick(3'bxxx);
#0
Load_bar = 1'bx;
#97
tbassert(Q === 3'bxxx, "Test 8");
tbassert(RCO === 1'bx, "Test 8");
#0
Clear_bar = 1'b0;
#97
tbassert(Q === 3'bxxx, "Test 8");
tbassert(RCO === 1'bx, "Test 8");
#2
tbassert(Q == 3'b000, "Test 8");
tbassert(RCO == 1'b0, "Test 8");
#15
Clear_bar = 1'b1;
#120
tbassert(Q == 3'b000, "Test 9");
tbassert(RCO == 1'b0, "Test 9");
#0
Load_bar = 1'b1;
#80
tbassert(Q == 3'b000, "Test 9");
tbassert(RCO == 1'b0, "Test 9");
#0
ENT = 1'b0;
ENP = 1'b1;
#7
tbassert(Q == 3'b000, "Test 10");
tbassert(RCO == 1'b0, "Test 10");
#50
tbassert(Q == 3'b000, "Test 10");
tbassert(RCO == 1'b0, "Test 10");
#100
tbassert(Q == 3'b000, "Test 10");
tbassert(RCO == 1'b0, "Test 10");
#15
ENT = 1'b1;
ENP = 1'b0;
#7
tbassert(Q == 3'b000, "Test 11");
tbassert(RCO == 1'b0, "Test 11");
#50
tbassert(Q == 3'b000, "Test 11");
tbassert(RCO == 1'b0, "Test 11");
#100
tbassert(Q == 3'b000, "Test 11");
tbassert(RCO == 1'b0, "Test 11");
#0
wait_tick();
#15
Load_bar = 1'b0;
D = 3'b111;
#15
Load_bar = 1'b1;
#7
tbassert(Q == 3'b000, "Test 12");
tbassert(RCO == 1'b0, "Test 12");
#50
tbassert(Q == 3'b000, "Test 12");
tbassert(RCO == 1'b0, "Test 12");
#100
tbassert(Q == 3'b000, "Test 12");
tbassert(RCO == 1'b0, "Test 12");
#0
wait_tick();
#20
ENT = 1'b1;
ENP = 1'b1;
#15
ENT = 1'b0;
#15
tbassert(Q == 3'b000, "Test 13");
tbassert(RCO == 1'b0, "Test 13");
#50
tbassert(Q == 3'b000, "Test 13");
tbassert(RCO == 1'b0, "Test 13");
#100
tbassert(Q == 3'b000, "Test 13");
tbassert(RCO == 1'b0, "Test 13");
#20
parallel_load_and_tick(3'b111);
#50
#175
tbassert(Q == 3'b111, "Test 14");
tbassert(RCO == 1'b0, "Test 14");
#0
ENP = 1'b0;
#50
tbassert(Q == 3'b111, "Test 14");
tbassert(RCO == 1'b0, "Test 14");
#100
tbassert(Q == 3'b111, "Test 14");
tbassert(RCO == 1'b0, "Test 14");
#0
wait_tick();
#25
Load_bar = 1'b0;
D = 3'b010;
#15
Load_bar = 1'b1;
#7
tbassert(Q == 3'b111, "Test 15");
tbassert(RCO == 1'b0, "Test 15");
#50
tbassert(Q == 3'b111, "Test 15");
tbassert(RCO == 1'b0, "Test 15");
#100
tbassert(Q == 3'b111, "Test 15");
tbassert(RCO == 1'b0, "Test 15");
#0
wait_tick();
#15
ENT = 1'b1;
ENP = 1'b1;
#15
ENT = 1'b0;
#7
tbassert(Q == 3'b111, "Test 16");
tbassert(RCO == 1'b0, "Test 16");
#50
tbassert(Q == 3'b111, "Test 16");
tbassert(RCO == 1'b0, "Test 16");
#100
tbassert(Q == 3'b111, "Test 16");
tbassert(RCO == 1'b0, "Test 16");
#0
wait_tick();
#10
ENT = 1'b1;
ENP = 1'b1;
#40
tbassert(Q == 3'b111, "Test 17");
tbassert(RCO == 1'b1, "Test 17");
#50
tbassert(Q == 3'b111, "Test 17");
tbassert(RCO == 1'b1, "Test 17");
#7
tbassert(Q == 3'b000, "Test 17");
tbassert(RCO == 1'b0, "Test 17");
#90
tbassert(Q == 3'b000, "Test 18");
tbassert(RCO == 1'b0, "Test 18");
#10
tbassert(Q == 3'b001, "Test 18");
tbassert(RCO == 1'b0, "Test 18");
#90
tbassert(Q == 3'b001, "Test 19");
tbassert(RCO == 1'b0, "Test 19");
#10
tbassert(Q == 3'b010, "Test 19");
tbassert(RCO == 1'b0, "Test 19");
#7
parallel_load_and_tick(3'b110);
#0
tbassert(Q == 3'b110, "Test 20");
tbassert(RCO == 1'b0, "Test 20");
#100
tbassert(Q == 3'b111, "Test 21");
tbassert(RCO == 1'b1, "Test 21");
#100
tbassert(Q == 3'b000, "Test 22");
tbassert(RCO == 1'b0, "Test 22");
#100
tbassert(Q == 3'b001, "Test 23");
tbassert(RCO == 1'b0, "Test 23");
#0
ENP = 1'b0;
#50
tbassert(Q == 3'b001, "Test 24");
tbassert(RCO == 1'b0, "Test 24");
#50
tbassert(Q == 3'b001, "Test 24");
tbassert(RCO == 1'b0, "Test 24");
#200
tbassert(Q == 3'b001, "Test 24");
tbassert(RCO == 1'b0, "Test 24");
#0
ENP = 1'b1;
#85
tbassert(Q == 3'b001, "Test 25");
tbassert(RCO == 1'b0, "Test 25");
#15
tbassert(Q == 3'b010, "Test 25");
tbassert(RCO == 1'b0, "Test 25");
#100
tbassert(Q == 3'b011, "Test 26");
tbassert(RCO == 1'b0, "Test 26");
#0
Clear_bar = 1'b0;
#90
tbassert(Q == 3'b011, "Test 27");
tbassert(RCO == 1'b0, "Test 27");
#10
tbassert(Q == 3'b000, "Test 27");
tbassert(RCO == 1'b0, "Test 27");
#0
Clear_bar = 1'b1;
#90
tbassert(Q == 3'b000, "Test 28");
tbassert(RCO == 1'b0, "Test 28");
#10
tbassert(Q == 3'b001, "Test 28");
tbassert(RCO == 1'b0, "Test 28");
#50
Clear_bar = 1'b0;
#50
Clear_bar = 1'b1;
parallel_load_and_tick(3'b011);
#90
tbassert(Q == 3'b011, "Test 29");
tbassert(RCO == 1'b0, "Test 29");
#10
tbassert(Q == 3'b100, "Test 29");
tbassert(RCO == 1'b0, "Test 29");
#20
ENP = 1'b0;
#50
tbassert(Q == 3'b100, "Test 30");
tbassert(RCO == 1'b0, "Test 30");
#0
ENP = 1'b1;
#2
tbassert(Q == 3'b100, "Test 30");
tbassert(RCO == 1'b0, "Test 30");
#50
tbassert(Q == 3'b101, "Test 30");
tbassert(RCO == 1'b0, "Test 30");
#0
ENT = 1'b0;
ENP = 1'b1;
parallel_load_and_tick(3'b111);
#100
tbassert(RCO == 1'b0, "Test 31");
#10
ENT = 1'b1;
#15
tbassert(Q == 3'b111, "Test 31");
tbassert(RCO == 1'b1, "Test 31");
#0
ENT = 1'b0;
#15
tbassert(RCO == 1'b0, "Test 31");
#0
wait_tick();
#50
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)
`TBCLK_WAIT_TICK_METHOD(wait_tick)
localparam WIDTH = 3;
reg Clear_bar;
reg Load_bar;
reg ENT;
reg ENP;
reg [WIDTH-1:0] D;
reg Clk;
wire RCO;
wire [WIDTH-1:0] Q;
ttl_74163 #(.WIDTH(WIDTH), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Clear_bar(Clear_bar),
.Load_bar(Load_bar),
.ENT(ENT),
.ENP(ENP),
.D(D),
.Clk(Clk),
.RCO(RCO),
.Q(Q)
);
initial Clk = 1'b0;
always #50 Clk = ~Clk;
task parallel_load_and_tick(input [WIDTH-1:0] D_next);
Load_bar = 1'b0;
D = D_next;
repeat (2) @(posedge Clk);
#7
Load_bar = 1'b1;
endtask
initial
begin
reg [WIDTH-1:0] D_next;
reg [WIDTH-1:0] Q_expected;
integer i;
$dumpfile("74163-tb.vcd");
$dumpvars;
#225
tbassert(Q === 3'bxxx, "Test 1");
tbassert(RCO === 1'bx, "Test 1");
#0
Load_bar = 1'b0;
D = 3'b000;
#25
tbassert(Q === 3'bxxx, "Test 1");
tbassert(RCO === 1'bx, "Test 1");
#2
tbassert(Q === 3'bxxx, "Test 1");
tbassert(RCO === 1'bx, "Test 1");
#2
tbassert(Q == 3'b000, "Test 1");
tbassert(RCO == 1'b0, "Test 1");
#140
Load_bar = 1'b1;
#175
tbassert(Q == 3'b000, "Test 2");
tbassert(RCO == 1'b0, "Test 2");
#0
Load_bar = 1'b0;
ENT = 1'b1;
D = 3'b111;
#125
Load_bar = 1'b1;
#110
tbassert(Q == 3'b111, "Test 3");
tbassert(RCO == 1'b1, "Test 3");
#0
ENT = 1'b0;
#0
D_next = 3'b111;
for (i = 1; i <= 6; i++)
begin
Q_expected = D_next;
D_next = (Q_expected + 2) ^ 5;
case (i)
1:
begin
ENT = 1'b0;
end
2:
begin
ENT = 1'b0;
ENP = 1'b0;
end
3:
begin
ENT = 1'b1;
ENP = 1'b0;
end
4:
begin
ENT = 1'b0;
ENP = 1'b1;
end
5:
begin
Clear_bar = 1'b1;
ENT = 1'b0;
ENP = 1'b1;
end
6:
begin
Clear_bar = 1'b1;
ENT = 1'b1;
ENP = 1'b0;
end
endcase
#75
tbassert2(Q == Q_expected, "Test", i, "4");
tbassert2(RCO == 1'b0, "Test", i, "4");
#0
Load_bar = 1'b0;
D = D_next;
#100
tbassert2(Q == D_next, "Test", i, "4");
tbassert2(RCO == 1'b0, "Test", i, "4");
#0
Load_bar = 1'b1;
#105
tbassert2(Q == D_next, "Test", i, "4");
tbassert2(RCO == 1'b0, "Test", i, "4");
end
tbassert2(Q == 3'b011, "Test", 6, "4");
#175
wait_tick();
#7
Clear_bar = 1'b0;
#95
tbassert(Q == 3'b011, "Test 5");
tbassert(RCO == 1'b0, "Test 5");
#2
tbassert(Q == 3'b000, "Test 5");
tbassert(RCO == 1'b0, "Test 5");
#150
Clear_bar = 1'b1;
#50
ENT = 1'b1;
parallel_load_and_tick(3'b111);
#70
Clear_bar = 1'b0;
#22
tbassert(Q == 3'b111, "Test 6");
tbassert(RCO == 1'b1, "Test 6");
#5
tbassert(Q == 3'b000, "Test 6");
tbassert(RCO == 1'b0, "Test 6");
#10
Clear_bar = 1'b1;
#120
tbassert(Q == 3'b000, "Test 7");
tbassert(RCO == 1'b0, "Test 7");
#50
Clear_bar = 1'bx;
Load_bar = 1'bx;
ENT = 1'bx;
ENP = 1'bx;
#15
parallel_load_and_tick(3'bxxx);
#0
Load_bar = 1'bx;
#97
tbassert(Q === 3'bxxx, "Test 8");
tbassert(RCO === 1'bx, "Test 8");
#0
Clear_bar = 1'b0;
#97
tbassert(Q === 3'bxxx, "Test 8");
tbassert(RCO === 1'bx, "Test 8");
#2
tbassert(Q == 3'b000, "Test 8");
tbassert(RCO == 1'b0, "Test 8");
#15
Clear_bar = 1'b1;
#120
tbassert(Q == 3'b000, "Test 9");
tbassert(RCO == 1'b0, "Test 9");
#0
Load_bar = 1'b1;
#80
tbassert(Q == 3'b000, "Test 9");
tbassert(RCO == 1'b0, "Test 9");
#0
ENT = 1'b0;
ENP = 1'b1;
#7
tbassert(Q == 3'b000, "Test 10");
tbassert(RCO == 1'b0, "Test 10");
#50
tbassert(Q == 3'b000, "Test 10");
tbassert(RCO == 1'b0, "Test 10");
#100
tbassert(Q == 3'b000, "Test 10");
tbassert(RCO == 1'b0, "Test 10");
#15
ENT = 1'b1;
ENP = 1'b0;
#7
tbassert(Q == 3'b000, "Test 11");
tbassert(RCO == 1'b0, "Test 11");
#50
tbassert(Q == 3'b000, "Test 11");
tbassert(RCO == 1'b0, "Test 11");
#100
tbassert(Q == 3'b000, "Test 11");
tbassert(RCO == 1'b0, "Test 11");
#0
wait_tick();
#15
Load_bar = 1'b0;
D = 3'b111;
#15
Load_bar = 1'b1;
#7
tbassert(Q == 3'b000, "Test 12");
tbassert(RCO == 1'b0, "Test 12");
#50
tbassert(Q == 3'b000, "Test 12");
tbassert(RCO == 1'b0, "Test 12");
#100
tbassert(Q == 3'b000, "Test 12");
tbassert(RCO == 1'b0, "Test 12");
#0
wait_tick();
#20
ENT = 1'b1;
ENP = 1'b1;
#15
ENT = 1'b0;
#15
tbassert(Q == 3'b000, "Test 13");
tbassert(RCO == 1'b0, "Test 13");
#50
tbassert(Q == 3'b000, "Test 13");
tbassert(RCO == 1'b0, "Test 13");
#100
tbassert(Q == 3'b000, "Test 13");
tbassert(RCO == 1'b0, "Test 13");
#20
parallel_load_and_tick(3'b111);
#50
#175
tbassert(Q == 3'b111, "Test 14");
tbassert(RCO == 1'b0, "Test 14");
#0
ENP = 1'b0;
#50
tbassert(Q == 3'b111, "Test 14");
tbassert(RCO == 1'b0, "Test 14");
#100
tbassert(Q == 3'b111, "Test 14");
tbassert(RCO == 1'b0, "Test 14");
#0
wait_tick();
#25
Load_bar = 1'b0;
D = 3'b010;
#15
Load_bar = 1'b1;
#7
tbassert(Q == 3'b111, "Test 15");
tbassert(RCO == 1'b0, "Test 15");
#50
tbassert(Q == 3'b111, "Test 15");
tbassert(RCO == 1'b0, "Test 15");
#100
tbassert(Q == 3'b111, "Test 15");
tbassert(RCO == 1'b0, "Test 15");
#0
wait_tick();
#15
ENT = 1'b1;
ENP = 1'b1;
#15
ENT = 1'b0;
#7
tbassert(Q == 3'b111, "Test 16");
tbassert(RCO == 1'b0, "Test 16");
#50
tbassert(Q == 3'b111, "Test 16");
tbassert(RCO == 1'b0, "Test 16");
#100
tbassert(Q == 3'b111, "Test 16");
tbassert(RCO == 1'b0, "Test 16");
#0
wait_tick();
#10
ENT = 1'b1;
ENP = 1'b1;
#40
tbassert(Q == 3'b111, "Test 17");
tbassert(RCO == 1'b1, "Test 17");
#50
tbassert(Q == 3'b111, "Test 17");
tbassert(RCO == 1'b1, "Test 17");
#7
tbassert(Q == 3'b000, "Test 17");
tbassert(RCO == 1'b0, "Test 17");
#90
tbassert(Q == 3'b000, "Test 18");
tbassert(RCO == 1'b0, "Test 18");
#10
tbassert(Q == 3'b001, "Test 18");
tbassert(RCO == 1'b0, "Test 18");
#90
tbassert(Q == 3'b001, "Test 19");
tbassert(RCO == 1'b0, "Test 19");
#10
tbassert(Q == 3'b010, "Test 19");
tbassert(RCO == 1'b0, "Test 19");
#7
parallel_load_and_tick(3'b110);
#0
tbassert(Q == 3'b110, "Test 20");
tbassert(RCO == 1'b0, "Test 20");
#100
tbassert(Q == 3'b111, "Test 21");
tbassert(RCO == 1'b1, "Test 21");
#100
tbassert(Q == 3'b000, "Test 22");
tbassert(RCO == 1'b0, "Test 22");
#100
tbassert(Q == 3'b001, "Test 23");
tbassert(RCO == 1'b0, "Test 23");
#0
ENP = 1'b0;
#50
tbassert(Q == 3'b001, "Test 24");
tbassert(RCO == 1'b0, "Test 24");
#50
tbassert(Q == 3'b001, "Test 24");
tbassert(RCO == 1'b0, "Test 24");
#200
tbassert(Q == 3'b001, "Test 24");
tbassert(RCO == 1'b0, "Test 24");
#0
ENP = 1'b1;
#85
tbassert(Q == 3'b001, "Test 25");
tbassert(RCO == 1'b0, "Test 25");
#15
tbassert(Q == 3'b010, "Test 25");
tbassert(RCO == 1'b0, "Test 25");
#100
tbassert(Q == 3'b011, "Test 26");
tbassert(RCO == 1'b0, "Test 26");
#0
Clear_bar = 1'b0;
#90
tbassert(Q == 3'b011, "Test 27");
tbassert(RCO == 1'b0, "Test 27");
#10
tbassert(Q == 3'b000, "Test 27");
tbassert(RCO == 1'b0, "Test 27");
#0
Clear_bar = 1'b1;
#90
tbassert(Q == 3'b000, "Test 28");
tbassert(RCO == 1'b0, "Test 28");
#10
tbassert(Q == 3'b001, "Test 28");
tbassert(RCO == 1'b0, "Test 28");
#50
Clear_bar = 1'b0;
#50
Clear_bar = 1'b1;
parallel_load_and_tick(3'b011);
#90
tbassert(Q == 3'b011, "Test 29");
tbassert(RCO == 1'b0, "Test 29");
#10
tbassert(Q == 3'b100, "Test 29");
tbassert(RCO == 1'b0, "Test 29");
#20
ENP = 1'b0;
#50
tbassert(Q == 3'b100, "Test 30");
tbassert(RCO == 1'b0, "Test 30");
#0
ENP = 1'b1;
#2
tbassert(Q == 3'b100, "Test 30");
tbassert(RCO == 1'b0, "Test 30");
#50
tbassert(Q == 3'b101, "Test 30");
tbassert(RCO == 1'b0, "Test 30");
#0
ENT = 1'b0;
ENP = 1'b1;
parallel_load_and_tick(3'b111);
#100
tbassert(RCO == 1'b0, "Test 31");
#10
ENT = 1'b1;
#15
tbassert(Q == 3'b111, "Test 31");
tbassert(RCO == 1'b1, "Test 31");
#0
ENT = 1'b0;
#15
tbassert(RCO == 1'b0, "Test 31");
#0
wait_tick();
#50
$finish;
end
endmodule | 84 |
6,263 | data/full_repos/permissive/115837888/source-7400/74181.v | 115,837,888 | 74181.v | v | 172 | 99 | [] | [] | [] | null | line:165: before: "," | data/verilator_xmls/a2236118-a384-4645-b3c1-23cf1c2213b0.xml | null | 7,092 | module | module ttl_74181 #(parameter WIDTH = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
input [3:0] Select,
input Mode,
input C_in,
input [WIDTH-1:0] A_bar,
input [WIDTH-1:0] B_bar,
output CP_bar,
output CG_bar,
output Equal,
output C_out,
output [WIDTH-1:0] F_bar
);
reg CP_computed;
reg CG_computed;
wire Equal_computed;
reg C_computed;
reg [WIDTH-1:0] F_computed;
wire [WIDTH-1:0] P_internal;
wire [WIDTH-1:0] G_internal;
wire [WIDTH-1:0] C_internal;
wire [WIDTH-1:0] CG_internal;
generate
genvar i;
for (i = 0; i < WIDTH; i = i + 1)
begin: gen_internals
wire [WIDTH-1:0] C_and_P_term;
wire [WIDTH-1:0] P_and_G_term;
wire [WIDTH-1:0] G_term;
assign P_internal[i] = ~(A_bar[i] & ~B_bar[i] & Select[2] | A_bar[i] & B_bar[i] & Select[3]);
assign G_internal[i] = ~(A_bar[i] | B_bar[i] & Select[0] | ~B_bar[i] & Select[1]);
if (i == 0)
begin
assign C_and_P_term[i] = C_in & !Mode;
end
else
begin
localparam i_minus_1 = i - 1;
assign C_and_P_term[i] = C_in & (&P_internal[i_minus_1:0]) & !Mode;
assign G_term[i] = G_internal[i_minus_1] & !Mode;
if (i > 1)
begin
genvar j;
for (j = 0; j < i_minus_1; j = j + 1)
begin: gen_P_and_G_term
localparam j_plus_one = j + 1;
assign P_and_G_term[j] = (&P_internal[i_minus_1:j_plus_one]) & G_internal[j] & !Mode;
end
end
end
if (i == 0)
begin
assign C_internal[i] = ~C_and_P_term[i];
end
else if (i == 1)
begin
assign C_internal[i] = ~(C_and_P_term[i] | G_term[i]);
end
else
begin
assign C_internal[i] = ~(C_and_P_term[i] | (|P_and_G_term[(i - 2):0]) | G_term[i]);
end
if (i < WIDTH - 1)
begin
assign CG_internal[i] = (&P_internal[(WIDTH - 1):(i + 1)]) & G_internal[i];
end
else
begin
assign CG_internal[i] = G_internal[i];
end
end
endgenerate
always @(*)
begin
CP_computed = ~(&P_internal);
CG_computed = ~(|CG_internal);
C_computed = C_in & (&P_internal) | (|CG_internal);
F_computed = P_internal ^ G_internal ^ C_internal;
end
assign Equal_computed = &F_computed;
assign #(DELAY_RISE, DELAY_FALL) CP_bar = CP_computed;
assign #(DELAY_RISE, DELAY_FALL) CG_bar = CG_computed;
assign #(DELAY_RISE, DELAY_FALL) Equal = Equal_computed;
assign #(DELAY_RISE, DELAY_FALL) C_out = C_computed;
assign #(DELAY_RISE, DELAY_FALL) F_bar = F_computed;
endmodule | module ttl_74181 #(parameter WIDTH = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
input [3:0] Select,
input Mode,
input C_in,
input [WIDTH-1:0] A_bar,
input [WIDTH-1:0] B_bar,
output CP_bar,
output CG_bar,
output Equal,
output C_out,
output [WIDTH-1:0] F_bar
); |
reg CP_computed;
reg CG_computed;
wire Equal_computed;
reg C_computed;
reg [WIDTH-1:0] F_computed;
wire [WIDTH-1:0] P_internal;
wire [WIDTH-1:0] G_internal;
wire [WIDTH-1:0] C_internal;
wire [WIDTH-1:0] CG_internal;
generate
genvar i;
for (i = 0; i < WIDTH; i = i + 1)
begin: gen_internals
wire [WIDTH-1:0] C_and_P_term;
wire [WIDTH-1:0] P_and_G_term;
wire [WIDTH-1:0] G_term;
assign P_internal[i] = ~(A_bar[i] & ~B_bar[i] & Select[2] | A_bar[i] & B_bar[i] & Select[3]);
assign G_internal[i] = ~(A_bar[i] | B_bar[i] & Select[0] | ~B_bar[i] & Select[1]);
if (i == 0)
begin
assign C_and_P_term[i] = C_in & !Mode;
end
else
begin
localparam i_minus_1 = i - 1;
assign C_and_P_term[i] = C_in & (&P_internal[i_minus_1:0]) & !Mode;
assign G_term[i] = G_internal[i_minus_1] & !Mode;
if (i > 1)
begin
genvar j;
for (j = 0; j < i_minus_1; j = j + 1)
begin: gen_P_and_G_term
localparam j_plus_one = j + 1;
assign P_and_G_term[j] = (&P_internal[i_minus_1:j_plus_one]) & G_internal[j] & !Mode;
end
end
end
if (i == 0)
begin
assign C_internal[i] = ~C_and_P_term[i];
end
else if (i == 1)
begin
assign C_internal[i] = ~(C_and_P_term[i] | G_term[i]);
end
else
begin
assign C_internal[i] = ~(C_and_P_term[i] | (|P_and_G_term[(i - 2):0]) | G_term[i]);
end
if (i < WIDTH - 1)
begin
assign CG_internal[i] = (&P_internal[(WIDTH - 1):(i + 1)]) & G_internal[i];
end
else
begin
assign CG_internal[i] = G_internal[i];
end
end
endgenerate
always @(*)
begin
CP_computed = ~(&P_internal);
CG_computed = ~(|CG_internal);
C_computed = C_in & (&P_internal) | (|CG_internal);
F_computed = P_internal ^ G_internal ^ C_internal;
end
assign Equal_computed = &F_computed;
assign #(DELAY_RISE, DELAY_FALL) CP_bar = CP_computed;
assign #(DELAY_RISE, DELAY_FALL) CG_bar = CG_computed;
assign #(DELAY_RISE, DELAY_FALL) Equal = Equal_computed;
assign #(DELAY_RISE, DELAY_FALL) C_out = C_computed;
assign #(DELAY_RISE, DELAY_FALL) F_bar = F_computed;
endmodule | 84 |
6,264 | data/full_repos/permissive/115837888/source-7400/7420.v | 115,837,888 | 7420.v | v | 25 | 86 | [] | [] | [] | null | line:16: before: "+" | null | 1: b"%Error: data/full_repos/permissive/115837888/source-7400/7420.v:21: Define or directive not defined: '`ASSIGN_UNPACK_ARRAY'\n`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7420.v:21: syntax error, unexpected '('\n`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)\n ^~~~~~\n%Error: Exiting due to 2 error(s)\n" | 7,094 | module | module ttl_7420 #(parameter BLOCKS = 2, WIDTH_IN = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
input [BLOCKS*WIDTH_IN-1:0] A_2D,
output [BLOCKS-1:0] Y
);
wire [WIDTH_IN-1:0] A [0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;
always @(*)
begin
for (i = 0; i < BLOCKS; i++)
computed[i] = ~(&A[i]);
end
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule | module ttl_7420 #(parameter BLOCKS = 2, WIDTH_IN = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
input [BLOCKS*WIDTH_IN-1:0] A_2D,
output [BLOCKS-1:0] Y
); |
wire [WIDTH_IN-1:0] A [0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;
always @(*)
begin
for (i = 0; i < BLOCKS; i++)
computed[i] = ~(&A[i]);
end
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule | 84 |
6,268 | data/full_repos/permissive/115837888/source-7400/7427-tb.v | 115,837,888 | 7427-tb.v | v | 166 | 86 | [] | [] | [] | null | line:5: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/7427-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7427-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7427-tb.v:30: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("7427-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7427-tb.v:31: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n#3\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7427-tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Error: Exiting due to 4 error(s), 26 warning(s)\n' | 7,103 | module | module test;
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 5;
localparam WIDTH_IN = 3;
reg [BLOCKS*WIDTH_IN-1:0] A;
wire [BLOCKS-1:0] Y;
ttl_7427 #(.BLOCKS(BLOCKS), .WIDTH_IN(WIDTH_IN), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.A_2D(A),
.Y(Y)
);
initial
begin
reg [WIDTH_IN-1:0] Block1;
reg [WIDTH_IN-1:0] Block2;
reg [WIDTH_IN-1:0] Block3;
reg [WIDTH_IN-1:0] Block4;
reg [WIDTH_IN-1:0] Block5;
$dumpfile("7427-tb.vcd");
$dumpvars;
Block1 = {WIDTH_IN{1'b1}};
Block2 = {WIDTH_IN{1'b1}};
Block3 = {WIDTH_IN{1'b1}};
Block4 = {WIDTH_IN{1'b1}};
Block5 = {WIDTH_IN{1'b1}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00000, "Test 1");
#0
Block1 = {WIDTH_IN{1'b0}};
Block2 = {WIDTH_IN{1'b0}};
Block3 = {WIDTH_IN{1'b0}};
Block4 = {WIDTH_IN{1'b0}};
Block5 = {WIDTH_IN{1'b0}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b11111, "Test 2");
#0
Block5 = 3'b001;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b01111, "Test 3");
#0
Block5 = 3'b100;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b01111, "Test 4");
#0
Block1 = {WIDTH_IN{1'b1}};
Block2 = {WIDTH_IN{1'b1}};
Block3 = 3'b000;
Block4 = {WIDTH_IN{1'b1}};
Block5 = {WIDTH_IN{1'b1}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00100, "Test 5");
#0
Block1 = 3'b010;
Block2 = 3'b010;
Block3 = 3'b010;
Block4 = 3'b010;
Block5 = 3'b010;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00000, "Test 6");
#0
Block1 = 3'b001;
Block2 = 3'b001;
Block3 = 3'b001;
Block4 = 3'b001;
Block5 = 3'b001;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00000, "Test 7");
#0
Block1 = 3'b001;
Block2 = 3'b000;
Block3 = 3'b000;
Block4 = 3'b111;
Block5 = 3'b110;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b00110, "Test 8");
#0
Block1 = 3'b010;
Block2 = 3'b000;
Block3 = 3'b000;
Block4 = 3'b111;
Block5 = 3'b011;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b00110, "Test 9");
#0
Block1 = 3'b001;
Block2 = 3'b000;
Block3 = 3'b010;
Block4 = 3'b101;
Block5 = 3'b111;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b00010, "Test 10");
#0
Block1 = 3'b110;
Block2 = 3'b111;
Block3 = 3'b101;
Block4 = 3'b010;
Block5 = 3'b000;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b10000, "Test 11");
#0
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
Block4 = {WIDTH_IN{1'bx}};
Block5 = {WIDTH_IN{1'bx}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
Block1 = 3'b110;
Block2 = 3'b111;
Block3 = 3'b101;
Block4 = 3'b010;
Block5 = 3'b000;
A = {Block5, Block4, Block3, Block2, Block1};
#3
tbassert(Y === 5'bxxxxx, "Test 12");
#7
tbassert(Y == 5'b10000, "Test 12");
#10
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 5;
localparam WIDTH_IN = 3;
reg [BLOCKS*WIDTH_IN-1:0] A;
wire [BLOCKS-1:0] Y;
ttl_7427 #(.BLOCKS(BLOCKS), .WIDTH_IN(WIDTH_IN), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.A_2D(A),
.Y(Y)
);
initial
begin
reg [WIDTH_IN-1:0] Block1;
reg [WIDTH_IN-1:0] Block2;
reg [WIDTH_IN-1:0] Block3;
reg [WIDTH_IN-1:0] Block4;
reg [WIDTH_IN-1:0] Block5;
$dumpfile("7427-tb.vcd");
$dumpvars;
Block1 = {WIDTH_IN{1'b1}};
Block2 = {WIDTH_IN{1'b1}};
Block3 = {WIDTH_IN{1'b1}};
Block4 = {WIDTH_IN{1'b1}};
Block5 = {WIDTH_IN{1'b1}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00000, "Test 1");
#0
Block1 = {WIDTH_IN{1'b0}};
Block2 = {WIDTH_IN{1'b0}};
Block3 = {WIDTH_IN{1'b0}};
Block4 = {WIDTH_IN{1'b0}};
Block5 = {WIDTH_IN{1'b0}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b11111, "Test 2");
#0
Block5 = 3'b001;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b01111, "Test 3");
#0
Block5 = 3'b100;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b01111, "Test 4");
#0
Block1 = {WIDTH_IN{1'b1}};
Block2 = {WIDTH_IN{1'b1}};
Block3 = 3'b000;
Block4 = {WIDTH_IN{1'b1}};
Block5 = {WIDTH_IN{1'b1}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00100, "Test 5");
#0
Block1 = 3'b010;
Block2 = 3'b010;
Block3 = 3'b010;
Block4 = 3'b010;
Block5 = 3'b010;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00000, "Test 6");
#0
Block1 = 3'b001;
Block2 = 3'b001;
Block3 = 3'b001;
Block4 = 3'b001;
Block5 = 3'b001;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00000, "Test 7");
#0
Block1 = 3'b001;
Block2 = 3'b000;
Block3 = 3'b000;
Block4 = 3'b111;
Block5 = 3'b110;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b00110, "Test 8");
#0
Block1 = 3'b010;
Block2 = 3'b000;
Block3 = 3'b000;
Block4 = 3'b111;
Block5 = 3'b011;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b00110, "Test 9");
#0
Block1 = 3'b001;
Block2 = 3'b000;
Block3 = 3'b010;
Block4 = 3'b101;
Block5 = 3'b111;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b00010, "Test 10");
#0
Block1 = 3'b110;
Block2 = 3'b111;
Block3 = 3'b101;
Block4 = 3'b010;
Block5 = 3'b000;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b10000, "Test 11");
#0
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
Block4 = {WIDTH_IN{1'bx}};
Block5 = {WIDTH_IN{1'bx}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
Block1 = 3'b110;
Block2 = 3'b111;
Block3 = 3'b101;
Block4 = 3'b010;
Block5 = 3'b000;
A = {Block5, Block4, Block3, Block2, Block1};
#3
tbassert(Y === 5'bxxxxx, "Test 12");
#7
tbassert(Y == 5'b10000, "Test 12");
#10
$finish;
end
endmodule | 84 |
6,269 | data/full_repos/permissive/115837888/source-7400/74273-tb.v | 115,837,888 | 74273-tb.v | v | 241 | 81 | [] | [] | [] | null | line:5: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/74273-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74273-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74273-tb.v:6: Define or directive not defined: \'`TBASSERT_2R_METHOD\'\n`TBASSERT_2R_METHOD(tbassert2R)\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74273-tb.v:32: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("74273-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74273-tb.v:33: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n#65\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n#4\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n#80\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:206: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:209: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:213: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:215: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:217: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:222: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:226: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:228: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:236: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Error: Exiting due to 5 error(s), 67 warning(s)\n' | 7,105 | module | module test;
`TBASSERT_METHOD(tbassert)
`TBASSERT_2R_METHOD(tbassert2R)
localparam WIDTH = 3;
reg Clear_bar;
reg [WIDTH-1:0] D;
reg Clk;
wire [WIDTH-1:0] Q;
ttl_74273 #(.WIDTH(WIDTH), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Clear_bar(Clear_bar),
.D(D),
.Clk(Clk),
.Q(Q)
);
initial
begin
reg [WIDTH-1:0] D_next;
reg [WIDTH-1:0] Q_expected;
integer i;
$dumpfile("74273-tb.vcd");
$dumpvars;
#65
tbassert(Q === 3'bxxx, "Test 1");
#0
Clk = 1'b0;
#7
tbassert(Q === 3'bxxx, "Test 1");
#0
D = 3'b000;
#25
tbassert(Q === 3'bxxx, "Test 1");
#0
Clk = 1'b1;
#2
tbassert(Q === 3'bxxx, "Test 1");
#2
tbassert(Q == 3'b000, "Test 1");
#140
Clk = 1'b0;
#175
tbassert(Q == 3'b000, "Test 2");
#0
D = 3'b111;
#125
tbassert(Q == 3'b000, "Test 3");
#0
Clk = 1'b1;
#4
tbassert(Q == 3'b000, "Test 3");
#2
tbassert(Q == 3'b111, "Test 3");
#50
Clk = 1'b0;
#125
tbassert(Q == 3'b111, "Test 4");
#0
Clear_bar = 1'b1;
#50
tbassert(Q == 3'b111, "Test 4");
#0
D = 3'b101;
#15
Clk = 1'b1;
#7
tbassert(Q == 3'b101, "Test 5");
#140
Clk = 1'b0;
#50
tbassert(Q == 3'b101, "Test 6");
#0
Clear_bar = 1'b0;
#2
tbassert(Q == 3'b101, "Test 7");
#2
tbassert(Q == 3'b000, "Test 7");
#150
Clear_bar = 1'b1;
#120
tbassert(Q == 3'b000, "Test 8");
#50
D = 3'b011;
#15
Clk = 1'b1;
#15
Clk = 1'b0;
#15
tbassert(Q == 3'b011, "Test 9");
#0
D = 3'b010;
#15
Clear_bar = 1'b0;
Clk = 1'b1;
#2
tbassert(Q == 3'b011, "Test 9");
#2
tbassert(Q == 3'b000, "Test 9");
#150
Clear_bar = 1'b1;
#70
tbassert(Q == 3'b000, "Test 10");
#50
D = 3'bxxx;
#15
Clk = 1'b0;
#15
Clk = 1'b1;
#15
tbassert(Q === 3'bxxx, "Test 11");
#0
Clear_bar = 1'bx;
Clk = 1'bx;
#15
Clear_bar = 1'b0;
#2
tbassert(Q === 3'bxxx, "Test 11");
#2
tbassert(Q == 3'b000, "Test 11");
#75
Clear_bar = 1'b1;
#80
tbassert(Q == 3'b000, "Test 12");
#0
D = 3'b000;
#15
Clk = 1'b1;
#15
tbassert(Q == 3'b000, "Test 12");
#0
Clk = 1'b0;
#15
tbassert(Q == 3'b000, "Test 12");
#0
D_next = 3'b000;
for (i = 1; i <= 3; i++)
begin
Q_expected = D_next;
case (i)
1:
begin
D_next = 3'b110;
end
2:
begin
D_next = 3'b001;
end
3:
begin
D_next = 3'b111;
end
endcase
#20
D = Q_expected;
#7
Clk = 1'b1;
#20
tbassert2R(Q == Q_expected, "Test", "1", (12 + i));
#0
Clk = 1'b0;
#50
tbassert2R(Q == Q_expected, "Test", "1", (12 + i));
#0
Clk = 1'b1;
#7
D = D_next;
#75
tbassert2R(Q == Q_expected, "Test", "2", (12 + i));
#0
Clk = 1'b0;
#25
D = 3'bzzz;
#25
tbassert2R(Q == Q_expected, "Test", "2", (12 + i));
end
tbassert2R(Q == 3'b001, "Test", "2", 15);
#50
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
`TBASSERT_2R_METHOD(tbassert2R)
localparam WIDTH = 3;
reg Clear_bar;
reg [WIDTH-1:0] D;
reg Clk;
wire [WIDTH-1:0] Q;
ttl_74273 #(.WIDTH(WIDTH), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Clear_bar(Clear_bar),
.D(D),
.Clk(Clk),
.Q(Q)
);
initial
begin
reg [WIDTH-1:0] D_next;
reg [WIDTH-1:0] Q_expected;
integer i;
$dumpfile("74273-tb.vcd");
$dumpvars;
#65
tbassert(Q === 3'bxxx, "Test 1");
#0
Clk = 1'b0;
#7
tbassert(Q === 3'bxxx, "Test 1");
#0
D = 3'b000;
#25
tbassert(Q === 3'bxxx, "Test 1");
#0
Clk = 1'b1;
#2
tbassert(Q === 3'bxxx, "Test 1");
#2
tbassert(Q == 3'b000, "Test 1");
#140
Clk = 1'b0;
#175
tbassert(Q == 3'b000, "Test 2");
#0
D = 3'b111;
#125
tbassert(Q == 3'b000, "Test 3");
#0
Clk = 1'b1;
#4
tbassert(Q == 3'b000, "Test 3");
#2
tbassert(Q == 3'b111, "Test 3");
#50
Clk = 1'b0;
#125
tbassert(Q == 3'b111, "Test 4");
#0
Clear_bar = 1'b1;
#50
tbassert(Q == 3'b111, "Test 4");
#0
D = 3'b101;
#15
Clk = 1'b1;
#7
tbassert(Q == 3'b101, "Test 5");
#140
Clk = 1'b0;
#50
tbassert(Q == 3'b101, "Test 6");
#0
Clear_bar = 1'b0;
#2
tbassert(Q == 3'b101, "Test 7");
#2
tbassert(Q == 3'b000, "Test 7");
#150
Clear_bar = 1'b1;
#120
tbassert(Q == 3'b000, "Test 8");
#50
D = 3'b011;
#15
Clk = 1'b1;
#15
Clk = 1'b0;
#15
tbassert(Q == 3'b011, "Test 9");
#0
D = 3'b010;
#15
Clear_bar = 1'b0;
Clk = 1'b1;
#2
tbassert(Q == 3'b011, "Test 9");
#2
tbassert(Q == 3'b000, "Test 9");
#150
Clear_bar = 1'b1;
#70
tbassert(Q == 3'b000, "Test 10");
#50
D = 3'bxxx;
#15
Clk = 1'b0;
#15
Clk = 1'b1;
#15
tbassert(Q === 3'bxxx, "Test 11");
#0
Clear_bar = 1'bx;
Clk = 1'bx;
#15
Clear_bar = 1'b0;
#2
tbassert(Q === 3'bxxx, "Test 11");
#2
tbassert(Q == 3'b000, "Test 11");
#75
Clear_bar = 1'b1;
#80
tbassert(Q == 3'b000, "Test 12");
#0
D = 3'b000;
#15
Clk = 1'b1;
#15
tbassert(Q == 3'b000, "Test 12");
#0
Clk = 1'b0;
#15
tbassert(Q == 3'b000, "Test 12");
#0
D_next = 3'b000;
for (i = 1; i <= 3; i++)
begin
Q_expected = D_next;
case (i)
1:
begin
D_next = 3'b110;
end
2:
begin
D_next = 3'b001;
end
3:
begin
D_next = 3'b111;
end
endcase
#20
D = Q_expected;
#7
Clk = 1'b1;
#20
tbassert2R(Q == Q_expected, "Test", "1", (12 + i));
#0
Clk = 1'b0;
#50
tbassert2R(Q == Q_expected, "Test", "1", (12 + i));
#0
Clk = 1'b1;
#7
D = D_next;
#75
tbassert2R(Q == Q_expected, "Test", "2", (12 + i));
#0
Clk = 1'b0;
#25
D = 3'bzzz;
#25
tbassert2R(Q == Q_expected, "Test", "2", (12 + i));
end
tbassert2R(Q == 3'b001, "Test", "2", 15);
#50
$finish;
end
endmodule | 84 |
6,270 | data/full_repos/permissive/115837888/source-7400/74273.v | 115,837,888 | 74273.v | v | 26 | 72 | [] | [] | [] | null | line:23: before: "," | data/verilator_xmls/8dbe33ef-e49e-4405-a0ee-7e8685b45e41.xml | null | 7,106 | module | module ttl_74273 #(parameter WIDTH = 8, DELAY_RISE = 0, DELAY_FALL = 0)
(
input Clear_bar,
input [WIDTH-1:0] D,
input Clk,
output [WIDTH-1:0] Q
);
reg [WIDTH-1:0] Q_current;
always @(posedge Clk or negedge Clear_bar)
begin
if (!Clear_bar)
Q_current <= {WIDTH{1'b0}};
else
Q_current <= D;
end
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule | module ttl_74273 #(parameter WIDTH = 8, DELAY_RISE = 0, DELAY_FALL = 0)
(
input Clear_bar,
input [WIDTH-1:0] D,
input Clk,
output [WIDTH-1:0] Q
); |
reg [WIDTH-1:0] Q_current;
always @(posedge Clk or negedge Clear_bar)
begin
if (!Clear_bar)
Q_current <= {WIDTH{1'b0}};
else
Q_current <= D;
end
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule | 84 |
6,271 | data/full_repos/permissive/115837888/source-7400/74283-tb.v | 115,837,888 | 74283-tb.v | v | 305 | 89 | [] | [] | [] | null | line:5: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/74283-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74283-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74283-tb.v:6: Define or directive not defined: \'`TBASSERT_2R_METHOD\'\n`TBASSERT_2R_METHOD(tbassert2R)\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74283-tb.v:7: Define or directive not defined: \'`CASE_TBASSERT_2R_METHOD\'\n`CASE_TBASSERT_2R_METHOD(case_tbassert2R, tbassert2R)\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74283-tb.v:33: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("74283-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74283-tb.v:34: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n#4\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:177: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:192: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:200: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:205: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:208: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:213: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:216: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:229: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:232: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:237: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:240: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:245: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:248: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:253: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:256: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:261: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:264: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:273: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:276: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:281: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:284: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:289: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:292: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:297: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74283-tb.v:300: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Error: Exiting due to 6 error(s), 56 warning(s)\n' | 7,107 | module | module test;
`TBASSERT_METHOD(tbassert)
`TBASSERT_2R_METHOD(tbassert2R)
`CASE_TBASSERT_2R_METHOD(case_tbassert2R, tbassert2R)
localparam WIDTH = 5;
reg [WIDTH-1:0] A;
reg [WIDTH-1:0] B;
reg C_in;
wire [WIDTH-1:0] Sum;
wire C_out;
ttl_74283 #(.WIDTH(WIDTH), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.A(A),
.B(B),
.C_in(C_in),
.Sum(Sum),
.C_out(C_out)
);
initial
begin
integer i;
$dumpfile("74283-tb.vcd");
$dumpvars;
A = {WIDTH{1'b0}};
B = {WIDTH{1'b0}};
C_in = 1'b0;
#4
tbassert(Sum == 5'b00000, "Test 1");
tbassert(C_out == 1'b0, "Test 1");
#0
A = {WIDTH{1'b1}};
B = {WIDTH{1'b1}};
C_in = 1'b1;
#6
tbassert(Sum == 5'b11111, "Test 2");
tbassert(C_out == 1'b1, "Test 2");
#0
for (i = 3; i <= 4; i++)
begin
case (i)
3:
begin
C_in = 1'b0;
end
4:
begin
C_in = 1'b1;
end
endcase
A = 5'b00001;
B = 5'b00001;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b00010, "Test", "1", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00011, "Test", "1", i);
tbassert2R(C_out == 1'b0, "Test", "1", i);
#0
B = 5'b00010;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b00011, "Test", "2", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00100, "Test", "2", i);
tbassert2R(C_out == 1'b0, "Test", "2", i);
#0
A = 5'b00010;
B = 5'b00001;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b00011, "Test", "3", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00100, "Test", "3", i);
tbassert2R(C_out == 1'b0, "Test", "3", i);
#0
A = 5'b00000;
B = 5'b11111;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b11111, "Test", "4", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00000, "Test", "4", i);
case_tbassert2R(C_in == 1'b0, C_out == 1'b0, "Test", "4", i);
case_tbassert2R(C_in == 1'b1, C_out == 1'b1, "Test", "4", i);
#0
A = 5'b11111;
B = 5'b00000;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b11111, "Test", "5", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00000, "Test", "5", i);
case_tbassert2R(C_in == 1'b0, C_out == 1'b0, "Test", "5", i);
case_tbassert2R(C_in == 1'b1, C_out == 1'b1, "Test", "5", i);
#0
A = 5'b10000;
B = 5'b01111;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b11111, "Test", "6", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00000, "Test", "6", i);
case_tbassert2R(C_in == 1'b0, C_out == 1'b0, "Test", "6", i);
case_tbassert2R(C_in == 1'b1, C_out == 1'b1, "Test", "6", i);
#0
A = 5'b01111;
B = 5'b10000;
C_in = ~C_in;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b11111, "Test", "7", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00000, "Test", "7", i);
case_tbassert2R(C_in == 1'b0, C_out == 1'b0, "Test", "7", i);
case_tbassert2R(C_in == 1'b1, C_out == 1'b1, "Test", "7", i);
#0
C_in = ~C_in;
#10
A = 5'b10000;
B = 5'b10000;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b00000, "Test", "8", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00001, "Test", "8", i);
tbassert2R(C_out == 1'b1, "Test", "8", i);
#0
B = 5'b10010;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b00010, "Test", "9", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00011, "Test", "9", i);
tbassert2R(C_out == 1'b1, "Test", "9", i);
#0
B = 5'b10001;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b00001, "Test", "10", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00010, "Test", "10", i);
tbassert2R(C_out == 1'b1, "Test", "10", i);
#0
A = 5'b01111;
B = 5'b01110;
C_in = ~C_in;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b11101, "Test", "11", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b11110, "Test", "11", i);
tbassert2R(C_out == 1'b0, "Test", "11", i);
#0
C_in = ~C_in;
end
#0
A = 5'b00010;
B = 5'b00010;
C_in = 1'b0;
#6
tbassert(Sum == 5'b00100, "Test 5");
tbassert(C_out == 1'b0, "Test 5");
#0
C_in = 1'b1;
#6
tbassert(Sum == 5'b00101, "Test 6");
tbassert(C_out == 1'b0, "Test 6");
#0
A = 5'b00011;
B = 5'b00101;
C_in = 1'b1;
#6
tbassert(Sum == 5'b01001, "Test 7");
tbassert(C_out == 1'b0, "Test 7");
#0
A = 5'b01101;
B = 5'b01101;
C_in = 1'b1;
#6
tbassert(Sum == 5'b11011, "Test 8");
tbassert(C_out == 1'b0, "Test 8");
#0
A = 5'b01101;
B = 5'b10001;
C_in = 1'b1;
#6
tbassert(Sum == 5'b11111, "Test 9");
tbassert(C_out == 1'b0, "Test 9");
#0
A = 5'b10001;
B = 5'b10001;
C_in = 1'b1;
#6
tbassert(Sum == 5'b00011, "Test 10");
tbassert(C_out == 1'b1, "Test 10");
#0
A = 5'b00111;
B = 5'b11011;
C_in = 1'b1;
#6
tbassert(Sum == 5'b00011, "Test 11");
tbassert(C_out == 1'b1, "Test 11");
#0
A = 5'b10011;
B = 5'b11111;
C_in = 1'b1;
#6
tbassert(Sum == 5'b10011, "Test 12");
tbassert(C_out == 1'b1, "Test 12");
#0
A = 5'b10111;
B = 5'b11101;
C_in = 1'b0;
#6
tbassert(Sum == 5'b10100, "Test 13");
tbassert(C_out == 1'b1, "Test 13");
#0
C_in = 1'b1;
#6
tbassert(Sum == 5'b10101, "Test 14");
tbassert(C_out == 1'b1, "Test 14");
#0
A = 5'b00011;
B = 5'b00101;
C_in = 1'b0;
#6
tbassert(Sum == 5'b01000, "Test 15");
tbassert(C_out == 1'b0, "Test 15");
#0
A = 5'b00010;
C_in = 1'b1;
#6
tbassert(Sum == 5'b01000, "Test 16");
tbassert(C_out == 1'b0, "Test 16");
#0
A = 5'b10011;
B = 5'b11101;
C_in = 1'b0;
#6
tbassert(Sum == 5'b10000, "Test 17");
tbassert(C_out == 1'b1, "Test 17");
#0
A = 5'b11101;
B = 5'b10010;
C_in = 1'b1;
#6
tbassert(Sum == 5'b10000, "Test 18");
tbassert(C_out == 1'b1, "Test 18");
#10
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
`TBASSERT_2R_METHOD(tbassert2R)
`CASE_TBASSERT_2R_METHOD(case_tbassert2R, tbassert2R)
localparam WIDTH = 5;
reg [WIDTH-1:0] A;
reg [WIDTH-1:0] B;
reg C_in;
wire [WIDTH-1:0] Sum;
wire C_out;
ttl_74283 #(.WIDTH(WIDTH), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.A(A),
.B(B),
.C_in(C_in),
.Sum(Sum),
.C_out(C_out)
);
initial
begin
integer i;
$dumpfile("74283-tb.vcd");
$dumpvars;
A = {WIDTH{1'b0}};
B = {WIDTH{1'b0}};
C_in = 1'b0;
#4
tbassert(Sum == 5'b00000, "Test 1");
tbassert(C_out == 1'b0, "Test 1");
#0
A = {WIDTH{1'b1}};
B = {WIDTH{1'b1}};
C_in = 1'b1;
#6
tbassert(Sum == 5'b11111, "Test 2");
tbassert(C_out == 1'b1, "Test 2");
#0
for (i = 3; i <= 4; i++)
begin
case (i)
3:
begin
C_in = 1'b0;
end
4:
begin
C_in = 1'b1;
end
endcase
A = 5'b00001;
B = 5'b00001;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b00010, "Test", "1", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00011, "Test", "1", i);
tbassert2R(C_out == 1'b0, "Test", "1", i);
#0
B = 5'b00010;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b00011, "Test", "2", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00100, "Test", "2", i);
tbassert2R(C_out == 1'b0, "Test", "2", i);
#0
A = 5'b00010;
B = 5'b00001;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b00011, "Test", "3", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00100, "Test", "3", i);
tbassert2R(C_out == 1'b0, "Test", "3", i);
#0
A = 5'b00000;
B = 5'b11111;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b11111, "Test", "4", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00000, "Test", "4", i);
case_tbassert2R(C_in == 1'b0, C_out == 1'b0, "Test", "4", i);
case_tbassert2R(C_in == 1'b1, C_out == 1'b1, "Test", "4", i);
#0
A = 5'b11111;
B = 5'b00000;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b11111, "Test", "5", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00000, "Test", "5", i);
case_tbassert2R(C_in == 1'b0, C_out == 1'b0, "Test", "5", i);
case_tbassert2R(C_in == 1'b1, C_out == 1'b1, "Test", "5", i);
#0
A = 5'b10000;
B = 5'b01111;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b11111, "Test", "6", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00000, "Test", "6", i);
case_tbassert2R(C_in == 1'b0, C_out == 1'b0, "Test", "6", i);
case_tbassert2R(C_in == 1'b1, C_out == 1'b1, "Test", "6", i);
#0
A = 5'b01111;
B = 5'b10000;
C_in = ~C_in;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b11111, "Test", "7", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00000, "Test", "7", i);
case_tbassert2R(C_in == 1'b0, C_out == 1'b0, "Test", "7", i);
case_tbassert2R(C_in == 1'b1, C_out == 1'b1, "Test", "7", i);
#0
C_in = ~C_in;
#10
A = 5'b10000;
B = 5'b10000;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b00000, "Test", "8", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00001, "Test", "8", i);
tbassert2R(C_out == 1'b1, "Test", "8", i);
#0
B = 5'b10010;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b00010, "Test", "9", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00011, "Test", "9", i);
tbassert2R(C_out == 1'b1, "Test", "9", i);
#0
B = 5'b10001;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b00001, "Test", "10", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b00010, "Test", "10", i);
tbassert2R(C_out == 1'b1, "Test", "10", i);
#0
A = 5'b01111;
B = 5'b01110;
C_in = ~C_in;
#10
case_tbassert2R(C_in == 1'b0, Sum == 5'b11101, "Test", "11", i);
case_tbassert2R(C_in == 1'b1, Sum == 5'b11110, "Test", "11", i);
tbassert2R(C_out == 1'b0, "Test", "11", i);
#0
C_in = ~C_in;
end
#0
A = 5'b00010;
B = 5'b00010;
C_in = 1'b0;
#6
tbassert(Sum == 5'b00100, "Test 5");
tbassert(C_out == 1'b0, "Test 5");
#0
C_in = 1'b1;
#6
tbassert(Sum == 5'b00101, "Test 6");
tbassert(C_out == 1'b0, "Test 6");
#0
A = 5'b00011;
B = 5'b00101;
C_in = 1'b1;
#6
tbassert(Sum == 5'b01001, "Test 7");
tbassert(C_out == 1'b0, "Test 7");
#0
A = 5'b01101;
B = 5'b01101;
C_in = 1'b1;
#6
tbassert(Sum == 5'b11011, "Test 8");
tbassert(C_out == 1'b0, "Test 8");
#0
A = 5'b01101;
B = 5'b10001;
C_in = 1'b1;
#6
tbassert(Sum == 5'b11111, "Test 9");
tbassert(C_out == 1'b0, "Test 9");
#0
A = 5'b10001;
B = 5'b10001;
C_in = 1'b1;
#6
tbassert(Sum == 5'b00011, "Test 10");
tbassert(C_out == 1'b1, "Test 10");
#0
A = 5'b00111;
B = 5'b11011;
C_in = 1'b1;
#6
tbassert(Sum == 5'b00011, "Test 11");
tbassert(C_out == 1'b1, "Test 11");
#0
A = 5'b10011;
B = 5'b11111;
C_in = 1'b1;
#6
tbassert(Sum == 5'b10011, "Test 12");
tbassert(C_out == 1'b1, "Test 12");
#0
A = 5'b10111;
B = 5'b11101;
C_in = 1'b0;
#6
tbassert(Sum == 5'b10100, "Test 13");
tbassert(C_out == 1'b1, "Test 13");
#0
C_in = 1'b1;
#6
tbassert(Sum == 5'b10101, "Test 14");
tbassert(C_out == 1'b1, "Test 14");
#0
A = 5'b00011;
B = 5'b00101;
C_in = 1'b0;
#6
tbassert(Sum == 5'b01000, "Test 15");
tbassert(C_out == 1'b0, "Test 15");
#0
A = 5'b00010;
C_in = 1'b1;
#6
tbassert(Sum == 5'b01000, "Test 16");
tbassert(C_out == 1'b0, "Test 16");
#0
A = 5'b10011;
B = 5'b11101;
C_in = 1'b0;
#6
tbassert(Sum == 5'b10000, "Test 17");
tbassert(C_out == 1'b1, "Test 17");
#0
A = 5'b11101;
B = 5'b10010;
C_in = 1'b1;
#6
tbassert(Sum == 5'b10000, "Test 18");
tbassert(C_out == 1'b1, "Test 18");
#10
$finish;
end
endmodule | 84 |
6,272 | data/full_repos/permissive/115837888/source-7400/74283.v | 115,837,888 | 74283.v | v | 26 | 72 | [] | [] | [] | null | line:22: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/115837888/source-7400/74283.v:18: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'C_in\' generates 1 bits.\n : ... In instance ttl_74283\n {C_computed, Sum_computed} = {1\'b0, A} + {1\'b0, B} + C_in;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 7,108 | module | module ttl_74283 #(parameter WIDTH = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
input [WIDTH-1:0] A,
input [WIDTH-1:0] B,
input C_in,
output [WIDTH-1:0] Sum,
output C_out
);
reg [WIDTH-1:0] Sum_computed;
reg C_computed;
always @(*)
begin
{C_computed, Sum_computed} = {1'b0, A} + {1'b0, B} + C_in;
end
assign #(DELAY_RISE, DELAY_FALL) Sum = Sum_computed;
assign #(DELAY_RISE, DELAY_FALL) C_out = C_computed;
endmodule | module ttl_74283 #(parameter WIDTH = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
input [WIDTH-1:0] A,
input [WIDTH-1:0] B,
input C_in,
output [WIDTH-1:0] Sum,
output C_out
); |
reg [WIDTH-1:0] Sum_computed;
reg C_computed;
always @(*)
begin
{C_computed, Sum_computed} = {1'b0, A} + {1'b0, B} + C_in;
end
assign #(DELAY_RISE, DELAY_FALL) Sum = Sum_computed;
assign #(DELAY_RISE, DELAY_FALL) C_out = C_computed;
endmodule | 84 |
6,275 | data/full_repos/permissive/115837888/source-7400/74377-tb.v | 115,837,888 | 74377-tb.v | v | 280 | 92 | [] | [] | [] | null | line:5: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/74377-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74377-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74377-tb.v:6: Define or directive not defined: \'`TBASSERT_2R_METHOD\'\n`TBASSERT_2R_METHOD(tbassert2R)\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74377-tb.v:32: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("74377-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74377-tb.v:33: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n#65\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n#4\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n#35\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n#35\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:181: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:184: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:187: Unsupported: Ignoring delay on this delayed statement.\n#80\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:192: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:199: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:201: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:227: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:231: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:233: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:237: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:239: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:242: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:244: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:246: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:248: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:252: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:254: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:256: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:260: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:262: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:264: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:267: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:275: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Error: Exiting due to 5 error(s), 85 warning(s)\n' | 7,115 | module | module test;
`TBASSERT_METHOD(tbassert)
`TBASSERT_2R_METHOD(tbassert2R)
localparam WIDTH = 3;
reg Enable_bar;
reg [WIDTH-1:0] D;
reg Clk;
wire [WIDTH-1:0] Q;
ttl_74377 #(.WIDTH(WIDTH), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Enable_bar(Enable_bar),
.D(D),
.Clk(Clk),
.Q(Q)
);
initial
begin
reg [WIDTH-1:0] D_next;
reg [WIDTH-1:0] Q_expected;
integer i;
$dumpfile("74377-tb.vcd");
$dumpvars;
#65
tbassert(Q === 3'bxxx, "Test 1");
#0
Clk = 1'b0;
#7
tbassert(Q === 3'bxxx, "Test 1");
#0
D = 3'b000;
#25
tbassert(Q === 3'bxxx, "Test 1");
#0
Clk = 1'b1;
#50
Clk = 1'b0;
#50
Clk = 1'b1;
#50
tbassert(Q === 3'bxxx, "Test 1");
#0
Enable_bar = 1'b1;
#50
tbassert(Q === 3'bxxx, "Test 1");
#0
Enable_bar = 1'b0;
Clk = 1'b0;
#25
tbassert(Q === 3'bxxx, "Test 1");
#0
Clk = 1'b1;
#2
tbassert(Q === 3'bxxx, "Test 1");
#2
tbassert(Q == 3'b000, "Test 1");
#140
Clk = 1'b0;
#175
tbassert(Q == 3'b000, "Test 2");
#0
D = 3'b111;
#125
tbassert(Q == 3'b000, "Test 3");
#0
Clk = 1'b1;
#4
tbassert(Q == 3'b000, "Test 3");
#2
tbassert(Q == 3'b111, "Test 3");
#50
Clk = 1'b0;
#125
tbassert(Q == 3'b111, "Test 4");
#0
D = 3'b101;
#15
Clk = 1'b1;
#7
tbassert(Q == 3'b101, "Test 5");
#140
Clk = 1'b0;
#50
tbassert(Q == 3'b101, "Test 6");
#0
Enable_bar = 1'b1;
#25
tbassert(Q == 3'b101, "Test 7");
#0
D = 3'b011;
#15
Clk = 1'b1;
#50
Clk = 1'b0;
#50
tbassert(Q == 3'b101, "Test 7");
#50
Clk = 1'b1;
#15
tbassert(Q == 3'b101, "Test 7");
#0
Enable_bar = 1'b0;
#50
Clk = 1'b0;
#50
tbassert(Q == 3'b101, "Test 8");
#50
Clk = 1'b1;
#15
tbassert(Q == 3'b011, "Test 8");
#75
Enable_bar = 1'b1;
#25
tbassert(Q == 3'b011, "Test 9");
#0
D = 3'b100;
#25
Clk = 1'b0;
#50
Clk = 1'b1;
#15
tbassert(Q == 3'b011, "Test 9");
#35
Clk = 1'b0;
#50
Clk = 1'b1;
#15
tbassert(Q == 3'b011, "Test 9");
#35
Clk = 1'b0;
#0
Enable_bar = 1'b0;
#25
Clk = 1'b1;
#2
tbassert(Q == 3'b011, "Test 10");
#5
tbassert(Q == 3'b100, "Test 10");
#75
Clk = 1'b0;
#80
tbassert(Q == 3'b100, "Test 11");
#0
Clk = 1'b1;
#50
Clk = 1'b0;
#50
tbassert(Q == 3'b100, "Test 12");
#0
Enable_bar = 1'b1;
#75
tbassert(Q == 3'b100, "Test 13");
#0
Enable_bar = 1'b0;
#0
D_next = 3'b100;
for (i = 1; i <= 3; i++)
begin
Q_expected = D_next;
case (i)
1:
begin
D_next = 3'b110;
end
2:
begin
D_next = 3'b001;
end
3:
begin
D_next = 3'b111;
end
endcase
#20
D = Q_expected;
#7
Clk = 1'b1;
#20
tbassert2R(Q == Q_expected, "Test", "1", (13 + i));
#0
Clk = 1'b0;
#50
tbassert2R(Q == Q_expected, "Test", "1", (13 + i));
#0
Clk = 1'b1;
#7
D = D_next;
#75
tbassert2R(Q == Q_expected, "Test", "2", (13 + i));
#0
Clk = 1'b0;
#25
Enable_bar = 1'b1;
#25
Clk = 1'b1;
#75
tbassert2R(Q == Q_expected, "Test", "3", (13 + i));
#0
Clk = 1'b0;
#50
Clk = 1'b1;
#50
tbassert2R(Q == Q_expected, "Test", "3", (13 + i));
#0
Clk = 1'b0;
#25
Enable_bar = 1'b0;
D = 3'bzzz;
#25
tbassert2R(Q == Q_expected, "Test", "3", (13 + i));
end
tbassert2R(Q == 3'b001, "Test", "3", 16);
#50
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
`TBASSERT_2R_METHOD(tbassert2R)
localparam WIDTH = 3;
reg Enable_bar;
reg [WIDTH-1:0] D;
reg Clk;
wire [WIDTH-1:0] Q;
ttl_74377 #(.WIDTH(WIDTH), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Enable_bar(Enable_bar),
.D(D),
.Clk(Clk),
.Q(Q)
);
initial
begin
reg [WIDTH-1:0] D_next;
reg [WIDTH-1:0] Q_expected;
integer i;
$dumpfile("74377-tb.vcd");
$dumpvars;
#65
tbassert(Q === 3'bxxx, "Test 1");
#0
Clk = 1'b0;
#7
tbassert(Q === 3'bxxx, "Test 1");
#0
D = 3'b000;
#25
tbassert(Q === 3'bxxx, "Test 1");
#0
Clk = 1'b1;
#50
Clk = 1'b0;
#50
Clk = 1'b1;
#50
tbassert(Q === 3'bxxx, "Test 1");
#0
Enable_bar = 1'b1;
#50
tbassert(Q === 3'bxxx, "Test 1");
#0
Enable_bar = 1'b0;
Clk = 1'b0;
#25
tbassert(Q === 3'bxxx, "Test 1");
#0
Clk = 1'b1;
#2
tbassert(Q === 3'bxxx, "Test 1");
#2
tbassert(Q == 3'b000, "Test 1");
#140
Clk = 1'b0;
#175
tbassert(Q == 3'b000, "Test 2");
#0
D = 3'b111;
#125
tbassert(Q == 3'b000, "Test 3");
#0
Clk = 1'b1;
#4
tbassert(Q == 3'b000, "Test 3");
#2
tbassert(Q == 3'b111, "Test 3");
#50
Clk = 1'b0;
#125
tbassert(Q == 3'b111, "Test 4");
#0
D = 3'b101;
#15
Clk = 1'b1;
#7
tbassert(Q == 3'b101, "Test 5");
#140
Clk = 1'b0;
#50
tbassert(Q == 3'b101, "Test 6");
#0
Enable_bar = 1'b1;
#25
tbassert(Q == 3'b101, "Test 7");
#0
D = 3'b011;
#15
Clk = 1'b1;
#50
Clk = 1'b0;
#50
tbassert(Q == 3'b101, "Test 7");
#50
Clk = 1'b1;
#15
tbassert(Q == 3'b101, "Test 7");
#0
Enable_bar = 1'b0;
#50
Clk = 1'b0;
#50
tbassert(Q == 3'b101, "Test 8");
#50
Clk = 1'b1;
#15
tbassert(Q == 3'b011, "Test 8");
#75
Enable_bar = 1'b1;
#25
tbassert(Q == 3'b011, "Test 9");
#0
D = 3'b100;
#25
Clk = 1'b0;
#50
Clk = 1'b1;
#15
tbassert(Q == 3'b011, "Test 9");
#35
Clk = 1'b0;
#50
Clk = 1'b1;
#15
tbassert(Q == 3'b011, "Test 9");
#35
Clk = 1'b0;
#0
Enable_bar = 1'b0;
#25
Clk = 1'b1;
#2
tbassert(Q == 3'b011, "Test 10");
#5
tbassert(Q == 3'b100, "Test 10");
#75
Clk = 1'b0;
#80
tbassert(Q == 3'b100, "Test 11");
#0
Clk = 1'b1;
#50
Clk = 1'b0;
#50
tbassert(Q == 3'b100, "Test 12");
#0
Enable_bar = 1'b1;
#75
tbassert(Q == 3'b100, "Test 13");
#0
Enable_bar = 1'b0;
#0
D_next = 3'b100;
for (i = 1; i <= 3; i++)
begin
Q_expected = D_next;
case (i)
1:
begin
D_next = 3'b110;
end
2:
begin
D_next = 3'b001;
end
3:
begin
D_next = 3'b111;
end
endcase
#20
D = Q_expected;
#7
Clk = 1'b1;
#20
tbassert2R(Q == Q_expected, "Test", "1", (13 + i));
#0
Clk = 1'b0;
#50
tbassert2R(Q == Q_expected, "Test", "1", (13 + i));
#0
Clk = 1'b1;
#7
D = D_next;
#75
tbassert2R(Q == Q_expected, "Test", "2", (13 + i));
#0
Clk = 1'b0;
#25
Enable_bar = 1'b1;
#25
Clk = 1'b1;
#75
tbassert2R(Q == Q_expected, "Test", "3", (13 + i));
#0
Clk = 1'b0;
#50
Clk = 1'b1;
#50
tbassert2R(Q == Q_expected, "Test", "3", (13 + i));
#0
Clk = 1'b0;
#25
Enable_bar = 1'b0;
D = 3'bzzz;
#25
tbassert2R(Q == Q_expected, "Test", "3", (13 + i));
end
tbassert2R(Q == 3'b001, "Test", "3", 16);
#50
$finish;
end
endmodule | 84 |
6,276 | data/full_repos/permissive/115837888/source-7400/74377.v | 115,837,888 | 74377.v | v | 24 | 72 | [] | [] | [] | null | line:21: before: "," | data/verilator_xmls/1dc2a604-46db-42f4-8062-480015af25bb.xml | null | 7,116 | module | module ttl_74377 #(parameter WIDTH = 8, DELAY_RISE = 0, DELAY_FALL = 0)
(
input Enable_bar,
input [WIDTH-1:0] D,
input Clk,
output [WIDTH-1:0] Q
);
reg [WIDTH-1:0] Q_current;
always @(posedge Clk)
begin
if (!Enable_bar)
Q_current <= D;
end
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule | module ttl_74377 #(parameter WIDTH = 8, DELAY_RISE = 0, DELAY_FALL = 0)
(
input Enable_bar,
input [WIDTH-1:0] D,
input Clk,
output [WIDTH-1:0] Q
); |
reg [WIDTH-1:0] Q_current;
always @(posedge Clk)
begin
if (!Enable_bar)
Q_current <= D;
end
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule | 84 |
6,277 | data/full_repos/permissive/115837888/source-7400/7442-tb.v | 115,837,888 | 7442-tb.v | v | 133 | 84 | [] | [] | [] | null | line:5: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/7442-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7442-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7442-tb.v:6: Define or directive not defined: \'`TBASSERT_2_METHOD\'\n`TBASSERT_2_METHOD(tbassert2)\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7442-tb.v:30: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("7442-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7442-tb.v:31: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Error: Exiting due to 5 error(s), 18 warning(s)\n' | 7,117 | module | module test;
`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)
localparam WIDTH_OUT = 10;
localparam WIDTH_IN = $clog2(WIDTH_OUT);
reg [WIDTH_IN-1:0] A;
wire [WIDTH_OUT-1:0] Y;
ttl_7442 #(.DELAY_RISE(5), .DELAY_FALL(3)) dut(
.A(A),
.Y(Y)
);
initial
begin
reg [WIDTH_OUT-1:0] Y_expected;
integer i;
$dumpfile("7442-tb.vcd");
$dumpvars;
A = 4'b0000;
#6
tbassert(Y == 10'b1111111110, "Test 1");
#0
A = 4'b0001;
#6
tbassert(Y == 10'b1111111101, "Test 2");
#0
A = 4'b1001;
#6
tbassert(Y == 10'b0111111111, "Test 3");
#0
A = 4'b1111;
#10
tbassert(Y == 10'b1111111111, "Test 4");
#0
A = 4'b1010;
#10
tbassert(Y == 10'b1111111111, "Test 5");
#0
for (i = 9; i >= 0; i--)
begin
A = i;
case (i)
9:
begin
Y_expected = 10'b0111111111;
end
8:
begin
Y_expected = 10'b1011111111;
end
7:
begin
Y_expected = 10'b1101111111;
end
6:
begin
Y_expected = 10'b1110111111;
end
5:
begin
Y_expected = 10'b1111011111;
end
4:
begin
Y_expected = 10'b1111101111;
end
3:
begin
Y_expected = 10'b1111110111;
end
2:
begin
Y_expected = 10'b1111111011;
end
1:
begin
Y_expected = 10'b1111111101;
end
0:
begin
Y_expected = 10'b1111111110;
end
endcase
#10
tbassert2(Y == Y_expected, "Test", (10 - i), "6");
end
#0
A = 4'b1110;
#6
tbassert(Y == 10'b1111111111, "Test 7");
#0
A = 4'b0110;
#6
tbassert(Y == 10'b1110111111, "Test 7");
#0
A = 4'b1001;
#6
tbassert(Y == 10'b0111111111, "Test 8");
#10
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)
localparam WIDTH_OUT = 10;
localparam WIDTH_IN = $clog2(WIDTH_OUT);
reg [WIDTH_IN-1:0] A;
wire [WIDTH_OUT-1:0] Y;
ttl_7442 #(.DELAY_RISE(5), .DELAY_FALL(3)) dut(
.A(A),
.Y(Y)
);
initial
begin
reg [WIDTH_OUT-1:0] Y_expected;
integer i;
$dumpfile("7442-tb.vcd");
$dumpvars;
A = 4'b0000;
#6
tbassert(Y == 10'b1111111110, "Test 1");
#0
A = 4'b0001;
#6
tbassert(Y == 10'b1111111101, "Test 2");
#0
A = 4'b1001;
#6
tbassert(Y == 10'b0111111111, "Test 3");
#0
A = 4'b1111;
#10
tbassert(Y == 10'b1111111111, "Test 4");
#0
A = 4'b1010;
#10
tbassert(Y == 10'b1111111111, "Test 5");
#0
for (i = 9; i >= 0; i--)
begin
A = i;
case (i)
9:
begin
Y_expected = 10'b0111111111;
end
8:
begin
Y_expected = 10'b1011111111;
end
7:
begin
Y_expected = 10'b1101111111;
end
6:
begin
Y_expected = 10'b1110111111;
end
5:
begin
Y_expected = 10'b1111011111;
end
4:
begin
Y_expected = 10'b1111101111;
end
3:
begin
Y_expected = 10'b1111110111;
end
2:
begin
Y_expected = 10'b1111111011;
end
1:
begin
Y_expected = 10'b1111111101;
end
0:
begin
Y_expected = 10'b1111111110;
end
endcase
#10
tbassert2(Y == Y_expected, "Test", (10 - i), "6");
end
#0
A = 4'b1110;
#6
tbassert(Y == 10'b1111111111, "Test 7");
#0
A = 4'b0110;
#6
tbassert(Y == 10'b1110111111, "Test 7");
#0
A = 4'b1001;
#6
tbassert(Y == 10'b0111111111, "Test 8");
#10
$finish;
end
endmodule | 84 |
6,278 | data/full_repos/permissive/115837888/source-7400/7473-tb.v | 115,837,888 | 7473-tb.v | v | 630 | 97 | [] | [] | [] | null | line:5: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/7473-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7473-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7473-tb.v:31: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("7473-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7473-tb.v:32: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n#65\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:191: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:200: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:206: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:209: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:212: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:223: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:226: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:229: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:232: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:239: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:242: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:245: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:248: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:251: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:254: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:262: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:265: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:268: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:276: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:271: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:279: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:281: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:284: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:287: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:290: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:299: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:302: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:305: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:308: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:311: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:314: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:318: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:322: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:325: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:328: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:331: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:336: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:339: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:341: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:344: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:347: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:350: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:356: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:359: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:363: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:366: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:369: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:373: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:375: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:377: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:380: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:384: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:389: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:392: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:396: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:400: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:403: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:406: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:409: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:412: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:415: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:418: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:421: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:424: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:427: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:429: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:433: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:435: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:437: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:440: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:444: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:447: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:450: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:452: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:456: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:458: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:460: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:463: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:467: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:472: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:475: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:479: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:483: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:486: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:489: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:492: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:495: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:498: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:501: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:504: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:507: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:510: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:512: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:520: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:522: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:524: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:527: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:531: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:533: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:535: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:538: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:542: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:545: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:548: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:551: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:554: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:556: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:559: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:562: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:565: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:567: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:571: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:574: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:578: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:580: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:582: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:585: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:589: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:592: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:595: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:598: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:601: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:603: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:607: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:609: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:611: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:618: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:614: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:620: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:622: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7473-tb.v:625: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Error: Exiting due to 4 error(s), 185 warning(s)\n' | 7,119 | module | module test;
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 3;
reg [BLOCKS-1:0] Clear_bar;
reg [BLOCKS-1:0] J;
reg [BLOCKS-1:0] K;
reg [BLOCKS-1:0] Clk;
wire [BLOCKS-1:0] Q;
wire [BLOCKS-1:0] Q_bar;
ttl_7473 #(.BLOCKS(BLOCKS), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Clear_bar(Clear_bar),
.J(J),
.K(K),
.Clk(Clk),
.Q(Q),
.Q_bar(Q_bar)
);
initial
begin
$dumpfile("7473-tb.vcd");
$dumpvars;
#65
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b000;
#7
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
J = 3'b000;
K = 3'b111;
#25
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b111;
#2
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b000;
#2
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#5
tbassert(Q == 3'b000, "Test 1");
tbassert(Q_bar == 3'b111, "Test 1");
#140
Clk = 3'b111;
#175
tbassert(Q == 3'b000, "Test 2");
tbassert(Q_bar == 3'b111, "Test 2");
#0
J = 3'b111;
K = 3'b000;
#125
tbassert(Q == 3'b000, "Test 3");
tbassert(Q_bar == 3'b111, "Test 3");
#0
Clk = 3'b000;
#2
tbassert(Q == 3'b000, "Test 3");
tbassert(Q_bar == 3'b111, "Test 3");
#5
tbassert(Q == 3'b111, "Test 3");
tbassert(Q_bar == 3'b000, "Test 3");
#50
Clk = 3'b111;
#125
tbassert(Q == 3'b111, "Test 4");
tbassert(Q_bar == 3'b000, "Test 4");
#0
Clear_bar = 3'b111;
#50
tbassert(Q == 3'b111, "Test 4");
tbassert(Q_bar == 3'b000, "Test 4");
#0
J = 3'b010;
K = 3'b101;
#15
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b110, "Test 5");
tbassert(Q_bar == 3'b001, "Test 5");
#25
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b110, "Test 6");
tbassert(Q_bar == 3'b001, "Test 6");
#25
Clk[2] = 1'b0;
#7
tbassert(Q == 3'b010, "Test 7");
tbassert(Q_bar == 3'b101, "Test 7");
#140
Clk[1] = 1'b1;
#7
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#10
Clk[0] = 1'b1;
#7
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#10
Clk[2] = 1'b1;
#50
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#0
J = 3'b111;
K = 3'b111;
#75
tbassert(Q == 3'b010, "Test 9");
tbassert(Q_bar == 3'b101, "Test 9");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b101, "Test 9");
tbassert(Q_bar == 3'b010, "Test 9");
#50
Clk = 3'b111;
#50
tbassert(Q == 3'b101, "Test 10");
tbassert(Q_bar == 3'b010, "Test 10");
#0
#15
tbassert(Q == 3'b101, "Test 11");
tbassert(Q_bar == 3'b010, "Test 11");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b010, "Test 11");
tbassert(Q_bar == 3'b101, "Test 11");
#10
Clk = 3'b111;
#75
tbassert(Q == 3'b010, "Test 12");
tbassert(Q_bar == 3'b101, "Test 12");
#0
#15
Clk[2] = 1'b0;
#7
tbassert(Q == 3'b110, "Test 13");
tbassert(Q_bar == 3'b001, "Test 13");
#15
Clk[2] = 1'b1;
#50
tbassert(Q == 3'b110, "Test 14");
tbassert(Q_bar == 3'b001, "Test 14");
#0
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b100, "Test 15");
tbassert(Q_bar == 3'b011, "Test 15");
#10
Clk = 3'b111;
#100
tbassert(Q == 3'b100, "Test 16");
tbassert(Q_bar == 3'b011, "Test 16");
#0
J = 3'b101;
K = 3'b110;
#125
tbassert(Q == 3'b100, "Test 17");
tbassert(Q_bar == 3'b011, "Test 17");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b001, "Test 17");
tbassert(Q_bar == 3'b110, "Test 17");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b001, "Test 18");
tbassert(Q_bar == 3'b110, "Test 18");
#0
J = 3'b101;
K = 3'b011;
#125
tbassert(Q == 3'b001, "Test 19");
tbassert(Q_bar == 3'b110, "Test 19");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b100, "Test 19");
tbassert(Q_bar == 3'b011, "Test 19");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b100, "Test 20");
tbassert(Q_bar == 3'b011, "Test 20");
#0
J = 3'b011;
K = 3'b101;
#15
Clk = 3'b100;
#7
tbassert(Q == 3'b111, "Test 21");
tbassert(Q_bar == 3'b000, "Test 21");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b111, "Test 22");
tbassert(Q_bar == 3'b000, "Test 22");
#0
#15
tbassert(Q == 3'b111, "Test 23");
tbassert(Q_bar == 3'b000, "Test 23");
#0
Clk = 3'b100;
#7
tbassert(Q == 3'b110, "Test 23");
tbassert(Q_bar == 3'b001, "Test 23");
#10
Clk = 3'b111;
#100
tbassert(Q == 3'b110, "Test 24");
tbassert(Q_bar == 3'b001, "Test 24");
#0
J = 3'b101;
K = 3'b100;
#40
tbassert(Q == 3'b110, "Test 25");
tbassert(Q_bar == 3'b001, "Test 25");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b011, "Test 25");
tbassert(Q_bar == 3'b100, "Test 25");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b011, "Test 26");
tbassert(Q_bar == 3'b100, "Test 26");
#0
J = 3'b010;
K = 3'b110;
#15
Clk = 3'b100;
#7
tbassert(Q == 3'b001, "Test 27");
tbassert(Q_bar == 3'b110, "Test 27");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b001, "Test 28");
tbassert(Q_bar == 3'b110, "Test 28");
#0
J = 3'b100;
K = 3'b100;
#15
tbassert(Q == 3'b001, "Test 29");
tbassert(Q_bar == 3'b110, "Test 29");
#0
Clk = 3'b010;
#7
tbassert(Q == 3'b101, "Test 29");
tbassert(Q_bar == 3'b010, "Test 29");
#10
Clk = 3'b111;
#50
tbassert(Q == 3'b101, "Test 30");
tbassert(Q_bar == 3'b010, "Test 30");
#0
Clear_bar = 3'b000;
#2
tbassert(Q == 3'b101, "Test 31");
tbassert(Q_bar == 3'b010, "Test 31");
#5
tbassert(Q == 3'b000, "Test 31");
tbassert(Q_bar == 3'b111, "Test 31");
#150
Clear_bar = 3'b111;
#120
tbassert(Q == 3'b000, "Test 32");
tbassert(Q_bar == 3'b111, "Test 32");
#50
J = 3'b011;
K = 3'b100;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b011, "Test 33");
tbassert(Q_bar == 3'b100, "Test 33");
#0
J = 3'b111;
K = 3'b111;
#15
Clear_bar = 3'b000;
Clk = 3'b001;
#2
tbassert(Q == 3'b011, "Test 33");
tbassert(Q_bar == 3'b100, "Test 33");
#5
tbassert(Q == 3'b000, "Test 33");
tbassert(Q_bar == 3'b111, "Test 33");
#10
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b000, "Test 33");
tbassert(Q_bar == 3'b111, "Test 33");
#150
Clear_bar[1] = 1'b1;
#20
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#0
Clear_bar[0] = 1'b1;
#7
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#10
Clear_bar[2] = 1'b1;
#70
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#0
Clk = 3'b101;
#70
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#0
Clk[1] = 1'b1;
#50
J = 3'b111;
K = 3'b001;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b111, "Test 35");
tbassert(Q_bar == 3'b000, "Test 35");
#0
J = 3'b110;
K = 3'b011;
#15
Clear_bar[2] = 1'b0;
#20
tbassert(Q == 3'b011, "Test 35");
tbassert(Q_bar == 3'b100, "Test 35");
#0
Clear_bar[2] = 1'b1;
#50
J = 3'b011;
K = 3'b100;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b011, "Test 36");
tbassert(Q_bar == 3'b100, "Test 36");
#0
J = 3'b110;
K = 3'b101;
#40
Clear_bar = 3'b000;
Clk = 3'b001;
#2
tbassert(Q == 3'b011, "Test 36");
tbassert(Q_bar == 3'b100, "Test 36");
#5
tbassert(Q == 3'b000, "Test 36");
tbassert(Q_bar == 3'b111, "Test 36");
#10
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b000, "Test 37");
tbassert(Q_bar == 3'b111, "Test 37");
#70
Clear_bar[1] = 1'b1;
#20
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#0
Clear_bar[2] = 1'b1;
#7
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#10
Clear_bar[0] = 1'b1;
#70
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#0
Clk = 3'b101;
#70
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#0
Clk[1] = 1'b1;
#50
J = 3'b101;
K = 3'b010;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b101, "Test 39");
tbassert(Q_bar == 3'b010, "Test 39");
#0
J = 3'b000;
K = 3'b000;
#7
Clk = 3'b000;
#25
Clk = 3'b111;
#15
tbassert(Q == 3'b101, "Test 39");
tbassert(Q_bar == 3'b010, "Test 39");
#0
J = 3'b101;
K = 3'b010;
#7
Clk = 3'b011;
#20
tbassert(Q == 3'b101, "Test 40");
tbassert(Q_bar == 3'b010, "Test 40");
#0
Clk = 3'b000;
#20
tbassert(Q == 3'b101, "Test 40");
tbassert(Q_bar == 3'b010, "Test 40");
#0
Clk = 3'b111;
#15
Clk = 3'b000;
#7
J = 3'b011;
K = 3'b101;
#75
tbassert(Q == 3'b101, "Test 41");
tbassert(Q_bar == 3'b010, "Test 41");
#0
Clk = 3'b111;
#25
J = 3'bzz0;
K = 3'bz01;
#50
tbassert(Q == 3'b101, "Test 41");
tbassert(Q_bar == 3'b010, "Test 41");
#0
J = 3'bz10;
K = 3'bz11;
#40
Clk = 3'b110;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b100, "Test 42");
tbassert(Q_bar == 3'b011, "Test 42");
#0
J = 3'b100;
K = 3'b011;
#7
Clk = 3'b110;
#20
tbassert(Q == 3'b100, "Test 43");
tbassert(Q_bar == 3'b011, "Test 43");
#0
Clk = 3'b001;
#40
tbassert(Q == 3'b100, "Test 44");
tbassert(Q_bar == 3'b011, "Test 44");
#0
Clk = 3'b111;
#15
J = 3'b011;
K = 3'b011;
#40
Clk = 3'b011;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b100, "Test 45");
tbassert(Q_bar == 3'b011, "Test 45");
#0
#40
Clk = 3'b110;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b101, "Test 46");
tbassert(Q_bar == 3'b010, "Test 46");
#50
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 3;
reg [BLOCKS-1:0] Clear_bar;
reg [BLOCKS-1:0] J;
reg [BLOCKS-1:0] K;
reg [BLOCKS-1:0] Clk;
wire [BLOCKS-1:0] Q;
wire [BLOCKS-1:0] Q_bar;
ttl_7473 #(.BLOCKS(BLOCKS), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Clear_bar(Clear_bar),
.J(J),
.K(K),
.Clk(Clk),
.Q(Q),
.Q_bar(Q_bar)
);
initial
begin
$dumpfile("7473-tb.vcd");
$dumpvars;
#65
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b000;
#7
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
J = 3'b000;
K = 3'b111;
#25
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b111;
#2
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b000;
#2
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#5
tbassert(Q == 3'b000, "Test 1");
tbassert(Q_bar == 3'b111, "Test 1");
#140
Clk = 3'b111;
#175
tbassert(Q == 3'b000, "Test 2");
tbassert(Q_bar == 3'b111, "Test 2");
#0
J = 3'b111;
K = 3'b000;
#125
tbassert(Q == 3'b000, "Test 3");
tbassert(Q_bar == 3'b111, "Test 3");
#0
Clk = 3'b000;
#2
tbassert(Q == 3'b000, "Test 3");
tbassert(Q_bar == 3'b111, "Test 3");
#5
tbassert(Q == 3'b111, "Test 3");
tbassert(Q_bar == 3'b000, "Test 3");
#50
Clk = 3'b111;
#125
tbassert(Q == 3'b111, "Test 4");
tbassert(Q_bar == 3'b000, "Test 4");
#0
Clear_bar = 3'b111;
#50
tbassert(Q == 3'b111, "Test 4");
tbassert(Q_bar == 3'b000, "Test 4");
#0
J = 3'b010;
K = 3'b101;
#15
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b110, "Test 5");
tbassert(Q_bar == 3'b001, "Test 5");
#25
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b110, "Test 6");
tbassert(Q_bar == 3'b001, "Test 6");
#25
Clk[2] = 1'b0;
#7
tbassert(Q == 3'b010, "Test 7");
tbassert(Q_bar == 3'b101, "Test 7");
#140
Clk[1] = 1'b1;
#7
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#10
Clk[0] = 1'b1;
#7
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#10
Clk[2] = 1'b1;
#50
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#0
J = 3'b111;
K = 3'b111;
#75
tbassert(Q == 3'b010, "Test 9");
tbassert(Q_bar == 3'b101, "Test 9");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b101, "Test 9");
tbassert(Q_bar == 3'b010, "Test 9");
#50
Clk = 3'b111;
#50
tbassert(Q == 3'b101, "Test 10");
tbassert(Q_bar == 3'b010, "Test 10");
#0
#15
tbassert(Q == 3'b101, "Test 11");
tbassert(Q_bar == 3'b010, "Test 11");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b010, "Test 11");
tbassert(Q_bar == 3'b101, "Test 11");
#10
Clk = 3'b111;
#75
tbassert(Q == 3'b010, "Test 12");
tbassert(Q_bar == 3'b101, "Test 12");
#0
#15
Clk[2] = 1'b0;
#7
tbassert(Q == 3'b110, "Test 13");
tbassert(Q_bar == 3'b001, "Test 13");
#15
Clk[2] = 1'b1;
#50
tbassert(Q == 3'b110, "Test 14");
tbassert(Q_bar == 3'b001, "Test 14");
#0
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b100, "Test 15");
tbassert(Q_bar == 3'b011, "Test 15");
#10
Clk = 3'b111;
#100
tbassert(Q == 3'b100, "Test 16");
tbassert(Q_bar == 3'b011, "Test 16");
#0
J = 3'b101;
K = 3'b110;
#125
tbassert(Q == 3'b100, "Test 17");
tbassert(Q_bar == 3'b011, "Test 17");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b001, "Test 17");
tbassert(Q_bar == 3'b110, "Test 17");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b001, "Test 18");
tbassert(Q_bar == 3'b110, "Test 18");
#0
J = 3'b101;
K = 3'b011;
#125
tbassert(Q == 3'b001, "Test 19");
tbassert(Q_bar == 3'b110, "Test 19");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b100, "Test 19");
tbassert(Q_bar == 3'b011, "Test 19");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b100, "Test 20");
tbassert(Q_bar == 3'b011, "Test 20");
#0
J = 3'b011;
K = 3'b101;
#15
Clk = 3'b100;
#7
tbassert(Q == 3'b111, "Test 21");
tbassert(Q_bar == 3'b000, "Test 21");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b111, "Test 22");
tbassert(Q_bar == 3'b000, "Test 22");
#0
#15
tbassert(Q == 3'b111, "Test 23");
tbassert(Q_bar == 3'b000, "Test 23");
#0
Clk = 3'b100;
#7
tbassert(Q == 3'b110, "Test 23");
tbassert(Q_bar == 3'b001, "Test 23");
#10
Clk = 3'b111;
#100
tbassert(Q == 3'b110, "Test 24");
tbassert(Q_bar == 3'b001, "Test 24");
#0
J = 3'b101;
K = 3'b100;
#40
tbassert(Q == 3'b110, "Test 25");
tbassert(Q_bar == 3'b001, "Test 25");
#0
Clk = 3'b000;
#7
tbassert(Q == 3'b011, "Test 25");
tbassert(Q_bar == 3'b100, "Test 25");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b011, "Test 26");
tbassert(Q_bar == 3'b100, "Test 26");
#0
J = 3'b010;
K = 3'b110;
#15
Clk = 3'b100;
#7
tbassert(Q == 3'b001, "Test 27");
tbassert(Q_bar == 3'b110, "Test 27");
#50
Clk = 3'b111;
#40
tbassert(Q == 3'b001, "Test 28");
tbassert(Q_bar == 3'b110, "Test 28");
#0
J = 3'b100;
K = 3'b100;
#15
tbassert(Q == 3'b001, "Test 29");
tbassert(Q_bar == 3'b110, "Test 29");
#0
Clk = 3'b010;
#7
tbassert(Q == 3'b101, "Test 29");
tbassert(Q_bar == 3'b010, "Test 29");
#10
Clk = 3'b111;
#50
tbassert(Q == 3'b101, "Test 30");
tbassert(Q_bar == 3'b010, "Test 30");
#0
Clear_bar = 3'b000;
#2
tbassert(Q == 3'b101, "Test 31");
tbassert(Q_bar == 3'b010, "Test 31");
#5
tbassert(Q == 3'b000, "Test 31");
tbassert(Q_bar == 3'b111, "Test 31");
#150
Clear_bar = 3'b111;
#120
tbassert(Q == 3'b000, "Test 32");
tbassert(Q_bar == 3'b111, "Test 32");
#50
J = 3'b011;
K = 3'b100;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b011, "Test 33");
tbassert(Q_bar == 3'b100, "Test 33");
#0
J = 3'b111;
K = 3'b111;
#15
Clear_bar = 3'b000;
Clk = 3'b001;
#2
tbassert(Q == 3'b011, "Test 33");
tbassert(Q_bar == 3'b100, "Test 33");
#5
tbassert(Q == 3'b000, "Test 33");
tbassert(Q_bar == 3'b111, "Test 33");
#10
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b000, "Test 33");
tbassert(Q_bar == 3'b111, "Test 33");
#150
Clear_bar[1] = 1'b1;
#20
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#0
Clear_bar[0] = 1'b1;
#7
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#10
Clear_bar[2] = 1'b1;
#70
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#0
Clk = 3'b101;
#70
tbassert(Q == 3'b000, "Test 34");
tbassert(Q_bar == 3'b111, "Test 34");
#0
Clk[1] = 1'b1;
#50
J = 3'b111;
K = 3'b001;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b111, "Test 35");
tbassert(Q_bar == 3'b000, "Test 35");
#0
J = 3'b110;
K = 3'b011;
#15
Clear_bar[2] = 1'b0;
#20
tbassert(Q == 3'b011, "Test 35");
tbassert(Q_bar == 3'b100, "Test 35");
#0
Clear_bar[2] = 1'b1;
#50
J = 3'b011;
K = 3'b100;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b011, "Test 36");
tbassert(Q_bar == 3'b100, "Test 36");
#0
J = 3'b110;
K = 3'b101;
#40
Clear_bar = 3'b000;
Clk = 3'b001;
#2
tbassert(Q == 3'b011, "Test 36");
tbassert(Q_bar == 3'b100, "Test 36");
#5
tbassert(Q == 3'b000, "Test 36");
tbassert(Q_bar == 3'b111, "Test 36");
#10
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b000, "Test 37");
tbassert(Q_bar == 3'b111, "Test 37");
#70
Clear_bar[1] = 1'b1;
#20
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#0
Clear_bar[2] = 1'b1;
#7
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#10
Clear_bar[0] = 1'b1;
#70
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#0
Clk = 3'b101;
#70
tbassert(Q == 3'b000, "Test 38");
tbassert(Q_bar == 3'b111, "Test 38");
#0
Clk[1] = 1'b1;
#50
J = 3'b101;
K = 3'b010;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b101, "Test 39");
tbassert(Q_bar == 3'b010, "Test 39");
#0
J = 3'b000;
K = 3'b000;
#7
Clk = 3'b000;
#25
Clk = 3'b111;
#15
tbassert(Q == 3'b101, "Test 39");
tbassert(Q_bar == 3'b010, "Test 39");
#0
J = 3'b101;
K = 3'b010;
#7
Clk = 3'b011;
#20
tbassert(Q == 3'b101, "Test 40");
tbassert(Q_bar == 3'b010, "Test 40");
#0
Clk = 3'b000;
#20
tbassert(Q == 3'b101, "Test 40");
tbassert(Q_bar == 3'b010, "Test 40");
#0
Clk = 3'b111;
#15
Clk = 3'b000;
#7
J = 3'b011;
K = 3'b101;
#75
tbassert(Q == 3'b101, "Test 41");
tbassert(Q_bar == 3'b010, "Test 41");
#0
Clk = 3'b111;
#25
J = 3'bzz0;
K = 3'bz01;
#50
tbassert(Q == 3'b101, "Test 41");
tbassert(Q_bar == 3'b010, "Test 41");
#0
J = 3'bz10;
K = 3'bz11;
#40
Clk = 3'b110;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b100, "Test 42");
tbassert(Q_bar == 3'b011, "Test 42");
#0
J = 3'b100;
K = 3'b011;
#7
Clk = 3'b110;
#20
tbassert(Q == 3'b100, "Test 43");
tbassert(Q_bar == 3'b011, "Test 43");
#0
Clk = 3'b001;
#40
tbassert(Q == 3'b100, "Test 44");
tbassert(Q_bar == 3'b011, "Test 44");
#0
Clk = 3'b111;
#15
J = 3'b011;
K = 3'b011;
#40
Clk = 3'b011;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b100, "Test 45");
tbassert(Q_bar == 3'b011, "Test 45");
#0
#40
Clk = 3'b110;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b101, "Test 46");
tbassert(Q_bar == 3'b010, "Test 46");
#50
$finish;
end
endmodule | 84 |
6,280 | data/full_repos/permissive/115837888/source-7400/7474-tb.v | 115,837,888 | 7474-tb.v | v | 672 | 99 | [] | [] | [] | null | line:8: before: "tbassert" | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/7474-tb.v:8: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7474-tb.v:8: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7474-tb.v:34: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("7474-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7474-tb.v:35: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n#65\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:181: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:184: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:192: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:195: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:198: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:201: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:204: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:207: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:210: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:213: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:216: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:219: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:226: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:228: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:231: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:234: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:237: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:240: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:242: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:245: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:247: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:249: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:252: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:259: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:262: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:266: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:268: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:271: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:273: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:282: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:279: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:284: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:287: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:292: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:295: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:298: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:302: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:305: Unsupported: Ignoring delay on this delayed statement.\n#80\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:308: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:311: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:314: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:316: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:319: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:322: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:324: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:327: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:329: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:332: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:334: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:338: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:341: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:344: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:347: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:349: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:358: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:355: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:360: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:363: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:368: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:373: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:377: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:380: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:383: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:386: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:390: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:393: Unsupported: Ignoring delay on this delayed statement.\n#80\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:396: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:398: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:401: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:404: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:406: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:409: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:411: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:414: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:418: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:421: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:424: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:428: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:431: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:433: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:436: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:438: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:440: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:443: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:446: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:451: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:454: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:457: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:463: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:466: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:471: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:474: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:476: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:478: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:481: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:484: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:487: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:489: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:492: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:499: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:502: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:505: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:507: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:510: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:513: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:516: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:518: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:520: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:522: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:524: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:527: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:530: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:533: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:535: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:537: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:540: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:542: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:544: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:546: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:549: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:552: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:555: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:557: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:559: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:562: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:565: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:567: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:569: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:572: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:575: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:577: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:580: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:582: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:584: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:586: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:589: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:596: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:598: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:600: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:606: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:603: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:609: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:612: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:615: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:618: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:621: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:624: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:626: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:629: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:631: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:634: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:636: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:639: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:642: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:645: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:647: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:649: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:652: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:655: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:658: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:661: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:664: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7474-tb.v:667: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Error: Exiting due to 4 error(s), 211 warning(s)\n' | 7,121 | module | module test;
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 3;
reg [BLOCKS-1:0] Preset_bar;
reg [BLOCKS-1:0] Clear_bar;
reg [BLOCKS-1:0] D;
reg [BLOCKS-1:0] Clk;
wire [BLOCKS-1:0] Q;
wire [BLOCKS-1:0] Q_bar;
ttl_7474 #(.BLOCKS(BLOCKS), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Preset_bar(Preset_bar),
.Clear_bar(Clear_bar),
.D(D),
.Clk(Clk),
.Q(Q),
.Q_bar(Q_bar)
);
initial
begin
$dumpfile("7474-tb.vcd");
$dumpvars;
#65
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b000;
#7
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
D = 3'b000;
#25
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b111;
#2
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#5
tbassert(Q == 3'b000, "Test 1");
tbassert(Q_bar == 3'b111, "Test 1");
#140
Clk = 3'b000;
#175
tbassert(Q == 3'b000, "Test 2");
tbassert(Q_bar == 3'b111, "Test 2");
#0
D = 3'b111;
#125
tbassert(Q == 3'b000, "Test 3");
tbassert(Q_bar == 3'b111, "Test 3");
#0
Clk = 3'b111;
#2
tbassert(Q == 3'b000, "Test 3");
tbassert(Q_bar == 3'b111, "Test 3");
#5
tbassert(Q == 3'b111, "Test 3");
tbassert(Q_bar == 3'b000, "Test 3");
#50
Clk = 3'b000;
#125
tbassert(Q == 3'b111, "Test 4");
tbassert(Q_bar == 3'b000, "Test 4");
#0
Clear_bar = 3'b111;
#50
tbassert(Q == 3'b111, "Test 4");
tbassert(Q_bar == 3'b000, "Test 4");
#0
Preset_bar = 3'b111;
#50
tbassert(Q == 3'b111, "Test 4");
tbassert(Q_bar == 3'b000, "Test 4");
#0
D = 3'b010;
#15
Clk[0] = 1'b1;
#7
tbassert(Q == 3'b110, "Test 5");
tbassert(Q_bar == 3'b001, "Test 5");
#25
Clk[1] = 1'b1;
#7
tbassert(Q == 3'b110, "Test 6");
tbassert(Q_bar == 3'b001, "Test 6");
#25
Clk[2] = 1'b1;
#7
tbassert(Q == 3'b010, "Test 7");
tbassert(Q_bar == 3'b101, "Test 7");
#140
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#10
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#10
Clk[2] = 1'b0;
#50
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#0
Clear_bar = 3'b000;
#2
tbassert(Q == 3'b010, "Test 9");
tbassert(Q_bar == 3'b101, "Test 9");
#5
tbassert(Q == 3'b000, "Test 9");
tbassert(Q_bar == 3'b111, "Test 9");
#150
Clear_bar = 3'b111;
#120
tbassert(Q == 3'b000, "Test 10");
tbassert(Q_bar == 3'b111, "Test 10");
#50
D = 3'b011;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b011, "Test 11");
tbassert(Q_bar == 3'b100, "Test 11");
#0
D = 3'b010;
#15
Clear_bar = 3'b000;
Clk = 3'b110;
#2
tbassert(Q == 3'b011, "Test 11");
tbassert(Q_bar == 3'b100, "Test 11");
#5
tbassert(Q == 3'b000, "Test 11");
tbassert(Q_bar == 3'b111, "Test 11");
#10
Clk[0] = 1'b1;
#7
tbassert(Q == 3'b000, "Test 11");
tbassert(Q_bar == 3'b111, "Test 11");
#150
Clear_bar[1] = 1'b1;
#20
tbassert(Q == 3'b000, "Test 12");
tbassert(Q_bar == 3'b111, "Test 12");
#0
Clear_bar[0] = 1'b1;
#7
tbassert(Q == 3'b000, "Test 12");
tbassert(Q_bar == 3'b111, "Test 12");
#10
Clear_bar[2] = 1'b1;
#70
tbassert(Q == 3'b000, "Test 12");
tbassert(Q_bar == 3'b111, "Test 12");
#0
Clk = 3'b010;
#70
tbassert(Q == 3'b000, "Test 12");
tbassert(Q_bar == 3'b111, "Test 12");
#0
Clk[1] = 1'b0;
#50
D = 3'b111;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b111, "Test 13");
tbassert(Q_bar == 3'b000, "Test 13");
#0
D = 3'b110;
#15
Clear_bar[2] = 1'b0;
#20
tbassert(Q == 3'b011, "Test 13");
tbassert(Q_bar == 3'b100, "Test 13");
#0
Clear_bar[2] = 1'b1;
#50
D = 3'b111;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b111, "Test 14");
tbassert(Q_bar == 3'b000, "Test 14");
#0
Clear_bar[0] = 1'b0;
Clear_bar[1] = 1'b0;
Clk[1] = 1'b1;
#2
tbassert(Q == 3'b111, "Test 14");
tbassert(Q_bar == 3'b000, "Test 14");
#5
tbassert(Q == 3'b100, "Test 14");
tbassert(Q_bar == 3'b011, "Test 14");
#10
Clear_bar = 3'b111;
#25
tbassert(Q == 3'b100, "Test 14");
tbassert(Q_bar == 3'b011, "Test 14");
#0
Clk[1] = 1'b0;
#0
D = 3'bxxx;
#15
#15
Clk = 3'b111;
#15
tbassert(Q === 3'bxxx, "Test 15");
tbassert(Q_bar === 3'bxxx, "Test 15");
#0
Preset_bar = 3'bxxx;
Clear_bar = 3'bxxx;
Clk = 3'bxxx;
#15
Clear_bar = 3'b000;
#2
tbassert(Q === 3'bxxx, "Test 15");
tbassert(Q_bar === 3'bxxx, "Test 15");
#5
tbassert(Q == 3'b000, "Test 15");
tbassert(Q_bar == 3'b111, "Test 15");
#75
Clear_bar = 3'b111;
#80
tbassert(Q == 3'b000, "Test 16");
tbassert(Q_bar == 3'b111, "Test 16");
#0
Preset_bar = 3'b111;
#50
tbassert(Q == 3'b000, "Test 16");
tbassert(Q_bar == 3'b111, "Test 16");
#0
D = 3'b000;
#15
Clk[0] = 1'b1;
#15
tbassert(Q == 3'b000, "Test 16");
tbassert(Q_bar == 3'b111, "Test 16");
#0
Clk[1] = 1'b1;
#7
tbassert(Q == 3'b000, "Test 16");
tbassert(Q_bar == 3'b111, "Test 16");
#10
Clk[2] = 1'b0;
#15
tbassert(Q == 3'b000, "Test 16");
tbassert(Q_bar == 3'b111, "Test 16");
#0
Clk[1] = 1'b0;
#0
Clk[2] = 1'b1;
#15
tbassert(Q == 3'b000, "Test 16");
tbassert(Q_bar == 3'b111, "Test 16");
#0
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b000, "Test 16");
tbassert(Q_bar == 3'b111, "Test 16");
#7
Clk[2] = 1'b0;
#0
D = 3'bxxx;
#15
#15
Clk = 3'b111;
#15
tbassert(Q === 3'bxxx, "Test 17");
tbassert(Q_bar === 3'bxxx, "Test 17");
#0
Preset_bar = 3'bxxx;
Clear_bar = 3'bxxx;
Clk = 3'bxxx;
#15
Preset_bar = 3'b111;
Clk = 3'b111;
#15
Preset_bar = 3'b000;
Clk = 3'b000;
#15
Clk = 3'b111;
#2
tbassert(Q === 3'bxxx, "Test 17");
tbassert(Q_bar === 3'bxxx, "Test 17");
#15
Clk = 3'bxxx;
#5
tbassert(Q == 3'b111, "Test 17");
tbassert(Q_bar == 3'b000, "Test 17");
#75
Preset_bar = 3'b111;
#80
tbassert(Q == 3'b111, "Test 18");
tbassert(Q_bar == 3'b000, "Test 18");
#0
D = 3'b111;
#15
Clk[0] = 1'b1;
#15
tbassert(Q == 3'b111, "Test 18");
tbassert(Q_bar == 3'b000, "Test 18");
#0
Clk[2] = 1'b0;
#7
tbassert(Q == 3'b111, "Test 18");
tbassert(Q_bar == 3'b000, "Test 18");
#10
Clk[1] = 1'b1;
#15
tbassert(Q == 3'b111, "Test 18");
tbassert(Q_bar == 3'b000, "Test 18");
#0
Clk[2] = 1'b1;
#15
tbassert(Q == 3'b111, "Test 18");
tbassert(Q_bar == 3'b000, "Test 18");
#0
Clear_bar = 3'b111;
#0
Clk[0] = 1'b0;
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b111, "Test 18");
tbassert(Q_bar == 3'b000, "Test 18");
#10
Clk[2] = 1'b0;
#50
D = 3'b000;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b000, "Test 19");
tbassert(Q_bar == 3'b111, "Test 19");
#0
D = 3'b010;
#15
Preset_bar[2] = 1'b0;
#15
Clk[2] = 1'b1;
#20
tbassert(Q == 3'b100, "Test 19");
tbassert(Q_bar == 3'b011, "Test 19");
#0
Clk[0] = 1'b1;
Clk[1] = 1'b1;
#2
tbassert(Q == 3'b100, "Test 20");
tbassert(Q_bar == 3'b011, "Test 20");
#5
tbassert(Q == 3'b110, "Test 20");
tbassert(Q_bar == 3'b001, "Test 20");
#0
Preset_bar[0] = 1'b0;
Preset_bar[1] = 1'b0;
#15
Clk = 3'b000;
#7
Preset_bar = 3'b111;
#15
tbassert(Q == 3'b110, "Test 20");
tbassert(Q_bar == 3'b001, "Test 20");
#0
D = 3'b111;
#15
Clk = 3'b111;
#25
Clk = 3'b000;
#15
tbassert(Q == 3'b111, "Test 20");
tbassert(Q_bar == 3'b000, "Test 20");
#0
Preset_bar = 3'b000;
D = 3'b010;
#25
Clear_bar = 3'b010;
#7
tbassert(Q == 3'b010, "Test 21");
tbassert(Q_bar == 3'b101, "Test 21");
#15
Clear_bar = 3'b111;
#25
Preset_bar = 3'b111;
#15
tbassert(Q == 3'b010, "Test 21");
tbassert(Q_bar == 3'b101, "Test 21");
#15
Clk = 3'b110;
#15
Clk = 3'b000;
#15
Clk = 3'b101;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b010, "Test 21");
tbassert(Q_bar == 3'b101, "Test 21");
#0
Clear_bar = 3'b000;
#10
tbassert(Q == 3'b000, "Test 22");
tbassert(Q_bar == 3'b111, "Test 22");
#20
Clear_bar = 3'b111;
#10
Clk = 3'b000;
#20
Clear_bar = 3'b000;
#10
Clk = 3'b111;
#20
Clear_bar = 3'b111;
#15
Clk = 3'b000;
#7
tbassert(Q == 3'b000, "Test 23");
tbassert(Q_bar == 3'b111, "Test 23");
#0
D = 3'b011;
#15
Preset_bar = 3'b000;
#25
Preset_bar = 3'b111;
#7
Clk = 3'b111;
#7
Clear_bar = 3'b010;
#7
tbassert(Q == 3'b010, "Test 24");
tbassert(Q_bar == 3'b101, "Test 24");
#15
Clear_bar = 3'b111;
#25
Clk = 3'b000;
#15
Clk = 3'b111;
#7
tbassert(Q == 3'b011, "Test 25");
tbassert(Q_bar == 3'b100, "Test 25");
#15
Clk = 3'b000;
#15
Clk = 3'b110;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b011, "Test 25");
tbassert(Q_bar == 3'b100, "Test 25");
#0
D = 3'b101;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b101, "Test 26");
tbassert(Q_bar == 3'b010, "Test 26");
#0
#7
Clk = 3'b100;
#20
tbassert(Q == 3'b101, "Test 26");
tbassert(Q_bar == 3'b010, "Test 26");
#0
Clk = 3'b110;
#20
tbassert(Q == 3'b101, "Test 26");
tbassert(Q_bar == 3'b010, "Test 26");
#0
Clk = 3'b111;
#20
tbassert(Q == 3'b101, "Test 26");
tbassert(Q_bar == 3'b010, "Test 26");
#0
Clk = 3'b000;
#15
Clk = 3'b111;
#7
D = 3'b011;
#75
tbassert(Q == 3'b101, "Test 27");
tbassert(Q_bar == 3'b010, "Test 27");
#0
Clk = 3'b000;
#25
D = 3'bzz0;
#50
tbassert(Q == 3'b101, "Test 27");
tbassert(Q_bar == 3'b010, "Test 27");
#0
D = 3'bz10;
#40
Clk = 3'b001;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b100, "Test 28");
tbassert(Q_bar == 3'b011, "Test 28");
#0
D = 3'b100;
#7
Clk = 3'b001;
#20
tbassert(Q == 3'b100, "Test 29");
tbassert(Q_bar == 3'b011, "Test 29");
#0
Clk = 3'b110;
#40
tbassert(Q == 3'b100, "Test 30");
tbassert(Q_bar == 3'b011, "Test 30");
#50
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 3;
reg [BLOCKS-1:0] Preset_bar;
reg [BLOCKS-1:0] Clear_bar;
reg [BLOCKS-1:0] D;
reg [BLOCKS-1:0] Clk;
wire [BLOCKS-1:0] Q;
wire [BLOCKS-1:0] Q_bar;
ttl_7474 #(.BLOCKS(BLOCKS), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.Preset_bar(Preset_bar),
.Clear_bar(Clear_bar),
.D(D),
.Clk(Clk),
.Q(Q),
.Q_bar(Q_bar)
);
initial
begin
$dumpfile("7474-tb.vcd");
$dumpvars;
#65
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b000;
#7
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
D = 3'b000;
#25
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#0
Clk = 3'b111;
#2
tbassert(Q === 3'bxxx, "Test 1");
tbassert(Q_bar === 3'bxxx, "Test 1");
#5
tbassert(Q == 3'b000, "Test 1");
tbassert(Q_bar == 3'b111, "Test 1");
#140
Clk = 3'b000;
#175
tbassert(Q == 3'b000, "Test 2");
tbassert(Q_bar == 3'b111, "Test 2");
#0
D = 3'b111;
#125
tbassert(Q == 3'b000, "Test 3");
tbassert(Q_bar == 3'b111, "Test 3");
#0
Clk = 3'b111;
#2
tbassert(Q == 3'b000, "Test 3");
tbassert(Q_bar == 3'b111, "Test 3");
#5
tbassert(Q == 3'b111, "Test 3");
tbassert(Q_bar == 3'b000, "Test 3");
#50
Clk = 3'b000;
#125
tbassert(Q == 3'b111, "Test 4");
tbassert(Q_bar == 3'b000, "Test 4");
#0
Clear_bar = 3'b111;
#50
tbassert(Q == 3'b111, "Test 4");
tbassert(Q_bar == 3'b000, "Test 4");
#0
Preset_bar = 3'b111;
#50
tbassert(Q == 3'b111, "Test 4");
tbassert(Q_bar == 3'b000, "Test 4");
#0
D = 3'b010;
#15
Clk[0] = 1'b1;
#7
tbassert(Q == 3'b110, "Test 5");
tbassert(Q_bar == 3'b001, "Test 5");
#25
Clk[1] = 1'b1;
#7
tbassert(Q == 3'b110, "Test 6");
tbassert(Q_bar == 3'b001, "Test 6");
#25
Clk[2] = 1'b1;
#7
tbassert(Q == 3'b010, "Test 7");
tbassert(Q_bar == 3'b101, "Test 7");
#140
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#10
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#10
Clk[2] = 1'b0;
#50
tbassert(Q == 3'b010, "Test 8");
tbassert(Q_bar == 3'b101, "Test 8");
#0
Clear_bar = 3'b000;
#2
tbassert(Q == 3'b010, "Test 9");
tbassert(Q_bar == 3'b101, "Test 9");
#5
tbassert(Q == 3'b000, "Test 9");
tbassert(Q_bar == 3'b111, "Test 9");
#150
Clear_bar = 3'b111;
#120
tbassert(Q == 3'b000, "Test 10");
tbassert(Q_bar == 3'b111, "Test 10");
#50
D = 3'b011;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b011, "Test 11");
tbassert(Q_bar == 3'b100, "Test 11");
#0
D = 3'b010;
#15
Clear_bar = 3'b000;
Clk = 3'b110;
#2
tbassert(Q == 3'b011, "Test 11");
tbassert(Q_bar == 3'b100, "Test 11");
#5
tbassert(Q == 3'b000, "Test 11");
tbassert(Q_bar == 3'b111, "Test 11");
#10
Clk[0] = 1'b1;
#7
tbassert(Q == 3'b000, "Test 11");
tbassert(Q_bar == 3'b111, "Test 11");
#150
Clear_bar[1] = 1'b1;
#20
tbassert(Q == 3'b000, "Test 12");
tbassert(Q_bar == 3'b111, "Test 12");
#0
Clear_bar[0] = 1'b1;
#7
tbassert(Q == 3'b000, "Test 12");
tbassert(Q_bar == 3'b111, "Test 12");
#10
Clear_bar[2] = 1'b1;
#70
tbassert(Q == 3'b000, "Test 12");
tbassert(Q_bar == 3'b111, "Test 12");
#0
Clk = 3'b010;
#70
tbassert(Q == 3'b000, "Test 12");
tbassert(Q_bar == 3'b111, "Test 12");
#0
Clk[1] = 1'b0;
#50
D = 3'b111;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b111, "Test 13");
tbassert(Q_bar == 3'b000, "Test 13");
#0
D = 3'b110;
#15
Clear_bar[2] = 1'b0;
#20
tbassert(Q == 3'b011, "Test 13");
tbassert(Q_bar == 3'b100, "Test 13");
#0
Clear_bar[2] = 1'b1;
#50
D = 3'b111;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b111, "Test 14");
tbassert(Q_bar == 3'b000, "Test 14");
#0
Clear_bar[0] = 1'b0;
Clear_bar[1] = 1'b0;
Clk[1] = 1'b1;
#2
tbassert(Q == 3'b111, "Test 14");
tbassert(Q_bar == 3'b000, "Test 14");
#5
tbassert(Q == 3'b100, "Test 14");
tbassert(Q_bar == 3'b011, "Test 14");
#10
Clear_bar = 3'b111;
#25
tbassert(Q == 3'b100, "Test 14");
tbassert(Q_bar == 3'b011, "Test 14");
#0
Clk[1] = 1'b0;
#0
D = 3'bxxx;
#15
#15
Clk = 3'b111;
#15
tbassert(Q === 3'bxxx, "Test 15");
tbassert(Q_bar === 3'bxxx, "Test 15");
#0
Preset_bar = 3'bxxx;
Clear_bar = 3'bxxx;
Clk = 3'bxxx;
#15
Clear_bar = 3'b000;
#2
tbassert(Q === 3'bxxx, "Test 15");
tbassert(Q_bar === 3'bxxx, "Test 15");
#5
tbassert(Q == 3'b000, "Test 15");
tbassert(Q_bar == 3'b111, "Test 15");
#75
Clear_bar = 3'b111;
#80
tbassert(Q == 3'b000, "Test 16");
tbassert(Q_bar == 3'b111, "Test 16");
#0
Preset_bar = 3'b111;
#50
tbassert(Q == 3'b000, "Test 16");
tbassert(Q_bar == 3'b111, "Test 16");
#0
D = 3'b000;
#15
Clk[0] = 1'b1;
#15
tbassert(Q == 3'b000, "Test 16");
tbassert(Q_bar == 3'b111, "Test 16");
#0
Clk[1] = 1'b1;
#7
tbassert(Q == 3'b000, "Test 16");
tbassert(Q_bar == 3'b111, "Test 16");
#10
Clk[2] = 1'b0;
#15
tbassert(Q == 3'b000, "Test 16");
tbassert(Q_bar == 3'b111, "Test 16");
#0
Clk[1] = 1'b0;
#0
Clk[2] = 1'b1;
#15
tbassert(Q == 3'b000, "Test 16");
tbassert(Q_bar == 3'b111, "Test 16");
#0
Clk[0] = 1'b0;
#7
tbassert(Q == 3'b000, "Test 16");
tbassert(Q_bar == 3'b111, "Test 16");
#7
Clk[2] = 1'b0;
#0
D = 3'bxxx;
#15
#15
Clk = 3'b111;
#15
tbassert(Q === 3'bxxx, "Test 17");
tbassert(Q_bar === 3'bxxx, "Test 17");
#0
Preset_bar = 3'bxxx;
Clear_bar = 3'bxxx;
Clk = 3'bxxx;
#15
Preset_bar = 3'b111;
Clk = 3'b111;
#15
Preset_bar = 3'b000;
Clk = 3'b000;
#15
Clk = 3'b111;
#2
tbassert(Q === 3'bxxx, "Test 17");
tbassert(Q_bar === 3'bxxx, "Test 17");
#15
Clk = 3'bxxx;
#5
tbassert(Q == 3'b111, "Test 17");
tbassert(Q_bar == 3'b000, "Test 17");
#75
Preset_bar = 3'b111;
#80
tbassert(Q == 3'b111, "Test 18");
tbassert(Q_bar == 3'b000, "Test 18");
#0
D = 3'b111;
#15
Clk[0] = 1'b1;
#15
tbassert(Q == 3'b111, "Test 18");
tbassert(Q_bar == 3'b000, "Test 18");
#0
Clk[2] = 1'b0;
#7
tbassert(Q == 3'b111, "Test 18");
tbassert(Q_bar == 3'b000, "Test 18");
#10
Clk[1] = 1'b1;
#15
tbassert(Q == 3'b111, "Test 18");
tbassert(Q_bar == 3'b000, "Test 18");
#0
Clk[2] = 1'b1;
#15
tbassert(Q == 3'b111, "Test 18");
tbassert(Q_bar == 3'b000, "Test 18");
#0
Clear_bar = 3'b111;
#0
Clk[0] = 1'b0;
Clk[1] = 1'b0;
#7
tbassert(Q == 3'b111, "Test 18");
tbassert(Q_bar == 3'b000, "Test 18");
#10
Clk[2] = 1'b0;
#50
D = 3'b000;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b000, "Test 19");
tbassert(Q_bar == 3'b111, "Test 19");
#0
D = 3'b010;
#15
Preset_bar[2] = 1'b0;
#15
Clk[2] = 1'b1;
#20
tbassert(Q == 3'b100, "Test 19");
tbassert(Q_bar == 3'b011, "Test 19");
#0
Clk[0] = 1'b1;
Clk[1] = 1'b1;
#2
tbassert(Q == 3'b100, "Test 20");
tbassert(Q_bar == 3'b011, "Test 20");
#5
tbassert(Q == 3'b110, "Test 20");
tbassert(Q_bar == 3'b001, "Test 20");
#0
Preset_bar[0] = 1'b0;
Preset_bar[1] = 1'b0;
#15
Clk = 3'b000;
#7
Preset_bar = 3'b111;
#15
tbassert(Q == 3'b110, "Test 20");
tbassert(Q_bar == 3'b001, "Test 20");
#0
D = 3'b111;
#15
Clk = 3'b111;
#25
Clk = 3'b000;
#15
tbassert(Q == 3'b111, "Test 20");
tbassert(Q_bar == 3'b000, "Test 20");
#0
Preset_bar = 3'b000;
D = 3'b010;
#25
Clear_bar = 3'b010;
#7
tbassert(Q == 3'b010, "Test 21");
tbassert(Q_bar == 3'b101, "Test 21");
#15
Clear_bar = 3'b111;
#25
Preset_bar = 3'b111;
#15
tbassert(Q == 3'b010, "Test 21");
tbassert(Q_bar == 3'b101, "Test 21");
#15
Clk = 3'b110;
#15
Clk = 3'b000;
#15
Clk = 3'b101;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
tbassert(Q == 3'b010, "Test 21");
tbassert(Q_bar == 3'b101, "Test 21");
#0
Clear_bar = 3'b000;
#10
tbassert(Q == 3'b000, "Test 22");
tbassert(Q_bar == 3'b111, "Test 22");
#20
Clear_bar = 3'b111;
#10
Clk = 3'b000;
#20
Clear_bar = 3'b000;
#10
Clk = 3'b111;
#20
Clear_bar = 3'b111;
#15
Clk = 3'b000;
#7
tbassert(Q == 3'b000, "Test 23");
tbassert(Q_bar == 3'b111, "Test 23");
#0
D = 3'b011;
#15
Preset_bar = 3'b000;
#25
Preset_bar = 3'b111;
#7
Clk = 3'b111;
#7
Clear_bar = 3'b010;
#7
tbassert(Q == 3'b010, "Test 24");
tbassert(Q_bar == 3'b101, "Test 24");
#15
Clear_bar = 3'b111;
#25
Clk = 3'b000;
#15
Clk = 3'b111;
#7
tbassert(Q == 3'b011, "Test 25");
tbassert(Q_bar == 3'b100, "Test 25");
#15
Clk = 3'b000;
#15
Clk = 3'b110;
#15
Clk = 3'b000;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b011, "Test 25");
tbassert(Q_bar == 3'b100, "Test 25");
#0
D = 3'b101;
#15
Clk = 3'b111;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b101, "Test 26");
tbassert(Q_bar == 3'b010, "Test 26");
#0
#7
Clk = 3'b100;
#20
tbassert(Q == 3'b101, "Test 26");
tbassert(Q_bar == 3'b010, "Test 26");
#0
Clk = 3'b110;
#20
tbassert(Q == 3'b101, "Test 26");
tbassert(Q_bar == 3'b010, "Test 26");
#0
Clk = 3'b111;
#20
tbassert(Q == 3'b101, "Test 26");
tbassert(Q_bar == 3'b010, "Test 26");
#0
Clk = 3'b000;
#15
Clk = 3'b111;
#7
D = 3'b011;
#75
tbassert(Q == 3'b101, "Test 27");
tbassert(Q_bar == 3'b010, "Test 27");
#0
Clk = 3'b000;
#25
D = 3'bzz0;
#50
tbassert(Q == 3'b101, "Test 27");
tbassert(Q_bar == 3'b010, "Test 27");
#0
D = 3'bz10;
#40
Clk = 3'b001;
#15
Clk = 3'b000;
#15
tbassert(Q == 3'b100, "Test 28");
tbassert(Q_bar == 3'b011, "Test 28");
#0
D = 3'b100;
#7
Clk = 3'b001;
#20
tbassert(Q == 3'b100, "Test 29");
tbassert(Q_bar == 3'b011, "Test 29");
#0
Clk = 3'b110;
#40
tbassert(Q == 3'b100, "Test 30");
tbassert(Q_bar == 3'b011, "Test 30");
#50
$finish;
end
endmodule | 84 |
6,282 | data/full_repos/permissive/115837888/source-7400/7485.v | 115,837,888 | 7485.v | v | 44 | 74 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/6dc024a3-5d36-49fb-bf8d-aa4b0001babc.xml | null | 7,124 | module | module ttl_7485 #(parameter WIDTH_IN = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
input [WIDTH_IN-1:0] A,
input [WIDTH_IN-1:0] B,
input ALess_in,
input Equal_in,
input AGreater_in,
output ALess_out,
output Equal_out,
output AGreater_out
);
reg ALess_computed;
reg Equal_computed;
reg AGreater_computed;
always @(*)
begin
if (A == B && !Equal_in && ALess_in == AGreater_in)
begin
Equal_computed = 1'b0;
ALess_computed = !ALess_in;
AGreater_computed = !AGreater_in;
end
else
begin
Equal_computed = A == B && Equal_in;
ALess_computed = !Equal_computed && {A, 1'b0} < {B, ALess_in};
AGreater_computed = !Equal_computed && {A, AGreater_in} > {B, 1'b0};
end
end
assign #(DELAY_RISE, DELAY_FALL) ALess_out = ALess_computed;
assign #(DELAY_RISE, DELAY_FALL) Equal_out = Equal_computed;
assign #(DELAY_RISE, DELAY_FALL) AGreater_out = AGreater_computed;
endmodule | module ttl_7485 #(parameter WIDTH_IN = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
input [WIDTH_IN-1:0] A,
input [WIDTH_IN-1:0] B,
input ALess_in,
input Equal_in,
input AGreater_in,
output ALess_out,
output Equal_out,
output AGreater_out
); |
reg ALess_computed;
reg Equal_computed;
reg AGreater_computed;
always @(*)
begin
if (A == B && !Equal_in && ALess_in == AGreater_in)
begin
Equal_computed = 1'b0;
ALess_computed = !ALess_in;
AGreater_computed = !AGreater_in;
end
else
begin
Equal_computed = A == B && Equal_in;
ALess_computed = !Equal_computed && {A, 1'b0} < {B, ALess_in};
AGreater_computed = !Equal_computed && {A, AGreater_in} > {B, 1'b0};
end
end
assign #(DELAY_RISE, DELAY_FALL) ALess_out = ALess_computed;
assign #(DELAY_RISE, DELAY_FALL) Equal_out = Equal_computed;
assign #(DELAY_RISE, DELAY_FALL) AGreater_out = AGreater_computed;
endmodule | 84 |
6,283 | data/full_repos/permissive/115837888/source-7400/7486-tb.v | 115,837,888 | 7486-tb.v | v | 173 | 90 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/115837888/source-7400/7486-tb.v:12: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7486-tb.v:12: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7486-tb.v:37: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("7486-tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7486-tb.v:38: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n#4\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7486-tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Error: Exiting due to 4 error(s), 26 warning(s)\n' | 7,125 | module | module test;
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 5;
localparam WIDTH_IN = 3;
reg [BLOCKS*WIDTH_IN-1:0] A;
wire [BLOCKS-1:0] Y;
ttl_7486 #(.BLOCKS(BLOCKS), .WIDTH_IN(WIDTH_IN), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.A_2D(A),
.Y(Y)
);
initial
begin
reg [WIDTH_IN-1:0] Block1;
reg [WIDTH_IN-1:0] Block2;
reg [WIDTH_IN-1:0] Block3;
reg [WIDTH_IN-1:0] Block4;
reg [WIDTH_IN-1:0] Block5;
$dumpfile("7486-tb.vcd");
$dumpvars;
Block1 = {WIDTH_IN{1'b0}};
Block2 = {WIDTH_IN{1'b0}};
Block3 = {WIDTH_IN{1'b0}};
Block4 = {WIDTH_IN{1'b0}};
Block5 = {WIDTH_IN{1'b0}};
A = {Block5, Block4, Block3, Block2, Block1};
#5
tbassert(Y == 5'b00000, "Test 1");
#0
Block4 = 3'b001;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b01000, "Test 2");
#0
Block4 = 3'b100;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b01000, "Test 3");
#0
Block1 = {WIDTH_IN{1'b0}};
Block2 = 3'b011;
Block3 = {WIDTH_IN{1'b0}};
Block4 = {WIDTH_IN{1'b0}};
Block5 = {WIDTH_IN{1'b0}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00000, "Test 4");
#0
Block2 = 3'b110;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00000, "Test 5");
#0
Block1 = 3'b000;
Block2 = 3'b000;
Block3 = 3'b101;
Block4 = 3'b110;
Block5 = 3'b011;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00000, "Test 6");
#0
Block1 = 3'b000;
Block2 = 3'b000;
Block3 = 3'b111;
Block4 = 3'b000;
Block5 = 3'b000;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00100, "Test 7");
#0
Block1 = 3'b111;
Block2 = 3'b111;
Block3 = 3'b000;
Block4 = 3'b111;
Block5 = 3'b111;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b11011, "Test 8");
#0
Block1 = 3'b111;
Block2 = 3'b111;
Block3 = 3'b111;
Block4 = 3'b011;
Block5 = 3'b111;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b10111, "Test 9");
#0
Block1 = 3'b111;
Block2 = 3'b111;
Block3 = 3'b111;
Block4 = 3'b101;
Block5 = 3'b111;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b10111, "Test 10");
#0
Block1 = 3'b111;
Block2 = 3'b010;
Block3 = 3'b100;
Block4 = 3'b001;
Block5 = 3'b111;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b11111, "Test 11");
#0
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
Block4 = {WIDTH_IN{1'bx}};
Block5 = {WIDTH_IN{1'bx}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
Block1 = 3'b111;
Block2 = 3'b000;
Block3 = 3'b101;
Block4 = 3'b010;
Block5 = 3'b011;
A = {Block5, Block4, Block3, Block2, Block1};
#2
tbassert(Y === 5'bxxxxx, "Test 12");
#4
tbassert(Y == 5'b01001, "Test 12");
#10
$finish;
end
endmodule | module test; |
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 5;
localparam WIDTH_IN = 3;
reg [BLOCKS*WIDTH_IN-1:0] A;
wire [BLOCKS-1:0] Y;
ttl_7486 #(.BLOCKS(BLOCKS), .WIDTH_IN(WIDTH_IN), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.A_2D(A),
.Y(Y)
);
initial
begin
reg [WIDTH_IN-1:0] Block1;
reg [WIDTH_IN-1:0] Block2;
reg [WIDTH_IN-1:0] Block3;
reg [WIDTH_IN-1:0] Block4;
reg [WIDTH_IN-1:0] Block5;
$dumpfile("7486-tb.vcd");
$dumpvars;
Block1 = {WIDTH_IN{1'b0}};
Block2 = {WIDTH_IN{1'b0}};
Block3 = {WIDTH_IN{1'b0}};
Block4 = {WIDTH_IN{1'b0}};
Block5 = {WIDTH_IN{1'b0}};
A = {Block5, Block4, Block3, Block2, Block1};
#5
tbassert(Y == 5'b00000, "Test 1");
#0
Block4 = 3'b001;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b01000, "Test 2");
#0
Block4 = 3'b100;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b01000, "Test 3");
#0
Block1 = {WIDTH_IN{1'b0}};
Block2 = 3'b011;
Block3 = {WIDTH_IN{1'b0}};
Block4 = {WIDTH_IN{1'b0}};
Block5 = {WIDTH_IN{1'b0}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00000, "Test 4");
#0
Block2 = 3'b110;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00000, "Test 5");
#0
Block1 = 3'b000;
Block2 = 3'b000;
Block3 = 3'b101;
Block4 = 3'b110;
Block5 = 3'b011;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00000, "Test 6");
#0
Block1 = 3'b000;
Block2 = 3'b000;
Block3 = 3'b111;
Block4 = 3'b000;
Block5 = 3'b000;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00100, "Test 7");
#0
Block1 = 3'b111;
Block2 = 3'b111;
Block3 = 3'b000;
Block4 = 3'b111;
Block5 = 3'b111;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b11011, "Test 8");
#0
Block1 = 3'b111;
Block2 = 3'b111;
Block3 = 3'b111;
Block4 = 3'b011;
Block5 = 3'b111;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b10111, "Test 9");
#0
Block1 = 3'b111;
Block2 = 3'b111;
Block3 = 3'b111;
Block4 = 3'b101;
Block5 = 3'b111;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b10111, "Test 10");
#0
Block1 = 3'b111;
Block2 = 3'b010;
Block3 = 3'b100;
Block4 = 3'b001;
Block5 = 3'b111;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b11111, "Test 11");
#0
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
Block4 = {WIDTH_IN{1'bx}};
Block5 = {WIDTH_IN{1'bx}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
Block1 = 3'b111;
Block2 = 3'b000;
Block3 = 3'b101;
Block4 = 3'b010;
Block5 = 3'b011;
A = {Block5, Block4, Block3, Block2, Block1};
#2
tbassert(Y === 5'bxxxxx, "Test 12");
#4
tbassert(Y == 5'b01001, "Test 12");
#10
$finish;
end
endmodule | 84 |
6,285 | data/full_repos/permissive/11584509/experimental/CM1/flasher.v | 11,584,509 | flasher.v | v | 36 | 83 | [] | [] | [] | [(6, 35)] | null | data/verilator_xmls/2d09b61c-5058-49f7-af41-65cfb8339615.xml | null | 7,132 | module | module flasher(
clk,
flash
);
parameter BITS = 24;
input clk;
output flash;
reg [BITS-1:0] counter;
assign flash = counter[BITS-1];
always @(posedge clk)
counter <= counter + 1;
endmodule | module flasher(
clk,
flash
); |
parameter BITS = 24;
input clk;
output flash;
reg [BITS-1:0] counter;
assign flash = counter[BITS-1];
always @(posedge clk)
counter <= counter + 1;
endmodule | 270 |
6,286 | data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v | 11,584,509 | hashvoodoo.v | v | 319 | 137 | [] | [] | [] | null | line:20: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:117: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS #(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/IBUFGDS\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/IBUFGDS.v\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/IBUFGDS.sv\n IBUFGDS\n IBUFGDS.v\n IBUFGDS.sv\n obj_dir/IBUFGDS\n obj_dir/IBUFGDS.v\n obj_dir/IBUFGDS.sv\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:127: Cannot find file containing module: \'BUFG\'\n BUFG CLK_COMM_BUF\n ^~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:134: Cannot find file containing module: \'main_dcm\'\n main_dcm #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:154: Cannot find file containing module: \'dcm_controller\'\n dcm_controller #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:172: Cannot find file containing module: \'hub_core\'\n hub_core #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:186: Cannot find file containing module: \'serial_core\'\n serial_core #(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:210: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance HASHVOODOO\n reg [3:0]syncloadnonce = 3\'d0;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:221: Cannot find file containing module: \'pbkdfengine\'\n pbkdfengine #(.SBITS(SBITS)) P1\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:228: Cannot find file containing module: \'salsaengine\'\n salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:263: Cannot find file containing module: \'flasher\'\n flasher #(\n ^~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:271: Cannot find file containing module: \'pwm_fade\'\n pwm_fade PWM_FADE_NONCE (\n ^~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:278: Cannot find file containing module: \'pwm_fade\'\n pwm_fade PWM_FADE_COMM (\n ^~~~~~~~\n%Error: Exiting due to 11 error(s), 1 warning(s)\n' | 7,133 | module | module HASHVOODOO (
clk_p,
clk_n,
clk_comm,
RxD,
TxD,
led,
dip,
reset_a,
reset_b,
reset_select
);
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
parameter CLOCK_RATE = 25000000;
parameter DCM_DIVIDER = 10;
parameter DCM_MULTIPLIER_START = 70;
parameter DCM_MULTIPLIER_CAP = 120;
parameter DCM_MULTIPLIER_MIN = 20;
parameter UART_BAUD_RATE = 115200;
parameter UART_SAMPLE_POINT = 8;
parameter CLOCK_FLASH_BITS = 26;
`ifdef DUALCORE
localparam LOCAL_MINERS = 2;
`else
localparam LOCAL_MINERS = 1;
`endif
localparam ADDRBITS = 12 - clog2(LOCAL_MINERS);
localparam SBITS = 8;
input clk_p;
input clk_n;
input clk_comm;
input RxD;
output TxD;
output [3:0] led;
input [3:0]dip;
input reset_a;
input reset_b;
input reset_select;
reg reset;
wire clk_buf;
wire clk_dcm;
wire clk_comm_buf;
wire clock_flash;
wire miner_busy;
wire serial_send;
wire serial_busy;
wire [31:0] golden_nonce;
wire [255:0] data1, data2;
wire [127:0] data3;
wire start_mining;
wire syncstart_mining;
reg syncstart_mining_d = 1'b0;
wire led_nonce_fade;
wire led_serial_fade;
wire dcm_prog_en;
wire dcm_prog_data;
wire dcm_prog_done;
wire dcm_valid;
wire dcm_reset = 1'b0;
wire identify_flag;
wire identify_flasher;
reg [3:0] syncticket1 = 0;
wire got_ticket1;
`ifdef DUALCORE
wire [63:0] slave_nonces;
reg [1:0] new_nonces;
reg [3:0] syncticket2 = 0;
wire got_ticket2;
`else
wire [31:0] slave_nonces;
reg [0:0] new_nonces;
`endif
assign led[0] = (led_serial_fade || identify_flasher);
assign led[1] = (clock_flash || ~dcm_valid || identify_flasher);
assign led[2] = (led_nonce_fade || identify_flasher);
assign led[3] = (~miner_busy || identify_flasher);
assign identify_flasher = (clock_flash && identify_flag);
`ifndef SIM
IBUFGDS #(
.DIFF_TERM("TRUE"),
.IOSTANDARD("DEFAULT")
) CLK_LVDS_BUF (
.O(clk_buf),
.I(clk_p),
.IB(clk_n)
);
BUFG CLK_COMM_BUF
(
.I (clk_comm),
.O (clk_comm_buf)
);
main_dcm #(
.DCM_DIVIDER(DCM_DIVIDER),
.DCM_MULTIPLIER(DCM_MULTIPLIER_START)
) MAINDCM(
.RESET(dcm_reset),
.CLK_VALID(dcm_valid),
.CLK_OSC(clk_buf),
.CLK_HASH(clk_dcm),
.PROGCLK(clk_comm_buf),
.PROGDATA(dcm_prog_data),
.PROGEN(dcm_prog_en),
.PROGDONE(dcm_prog_done)
);
`else
assign clk_buf = clk_p;
assign clk_dcm = clk_buf;
assign clk_comm_buf = clk_comm;
`endif
dcm_controller #(
.MAXIMUM_MULTIPLIER(DCM_MULTIPLIER_CAP),
.MINIMUM_MULTIPLIER(DCM_MULTIPLIER_MIN),
.INITIAL_MULTIPLIER(DCM_MULTIPLIER_START),
.INITIAL_DIVIDER(DCM_DIVIDER)
) DCM_CONTROL (
.clk(clk_comm_buf),
.data2({data2[255:96], data3[95:0]}),
.midstate(data1),
.start(start_mining),
.dcm_prog_clk(clk_comm_buf),
.dcm_prog_en(dcm_prog_en),
.dcm_prog_data(dcm_prog_data),
.dcm_prog_done(dcm_prog_done),
.identify(identify_flag)
);
hub_core #(
.SLAVES(LOCAL_MINERS)
) HUBCORE (
.hash_clk(clk_comm_buf),
.new_nonces(new_nonces),
.golden_nonce(golden_nonce),
.serial_send(serial_send),
.serial_busy(serial_busy),
.slave_nonces(slave_nonces)
);
wire unused_rx_busy;
serial_core #(
.CLOCK(CLOCK_RATE),
.BAUD(UART_BAUD_RATE),
.SAMPLE_POINT(UART_SAMPLE_POINT)
) SERIAL_COMM (
.clk(clk_comm_buf),
.rx(RxD),
.tx(TxD),
.rx_ready(start_mining),
.tx_ready(serial_send),
.data1(data1),
.data2(data2),
.data3(data3),
.word(golden_nonce),
.tx_busy(serial_busy),
.rx_busy(unused_rx_busy)
);
wire [31:0] unused_nonce_out1, unused_hash_out1;
wire [31:0] unused_nonce_out2, unused_hash_out2;
reg loadnonce = 1'b0;
reg [3:0]syncloadnonce = 3'd0;
wire [31:0] mod_target = 32'h00007fff;
wire gn_match_1;
wire [31:0] golden_nonce_1;
wire [31:0] hash_1, nonce_out_1;
wire salsa_busy_1, salsa_result_1, salsa_reset_1, salsa_start_1, salsa_shift_1;
wire [SBITS-1:0] salsa_din_1;
wire [SBITS-1:0] salsa_dout_1;
pbkdfengine #(.SBITS(SBITS)) P1
(.hash_clk(clk_dcm), .pbkdf_clk(clk_dcm), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb( 4'd0 ), .nonce_out(nonce_out_1), .golden_nonce_out(golden_nonce_1),
.golden_nonce_match(gn_match_1), .loadnonce(loadnonce),
.salsa_din(salsa_din_1), .salsa_dout(salsa_dout_1), .salsa_busy(salsa_busy_1), .salsa_result(salsa_result_1),
.salsa_reset(salsa_reset_1), .salsa_start(salsa_start_1), .salsa_shift(salsa_shift_1), .hash_out(hash_1));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1
(.hash_clk(clk_dcm), .reset(salsa_reset_1), .din(salsa_din_1), .dout(salsa_dout_1),
.shift(salsa_shift_1), .start(salsa_start_1), .busy(salsa_busy_1), .result(salsa_result_1) );
`ifdef DUALCORE
wire gn_match_2;
wire [31:0] golden_nonce_2;
wire [31:0] hash_2, nonce_out_2;
wire salsa_busy_2, salsa_result_2, salsa_reset_2, salsa_start_2, salsa_shift_2;
wire [SBITS-1:0] salsa_din_2;
wire [SBITS-1:0] salsa_dout_2;
pbkdfengine #(.SBITS(SBITS)) P2
(.hash_clk(clk_dcm), .pbkdf_clk(clk_dcm), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb( 4'd8 ), .nonce_out(nonce_out_2), .golden_nonce_out(golden_nonce_2),
.golden_nonce_match(gn_match_2), .loadnonce(loadnonce),
.salsa_din(salsa_din_2), .salsa_dout(salsa_dout_2), .salsa_busy(salsa_busy_2), .salsa_result(salsa_result_2),
.salsa_reset(salsa_reset_2), .salsa_start(salsa_start_2), .salsa_shift(salsa_shift_2), .hash_out(hash_2));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S2
(.hash_clk(clk_dcm), .reset(salsa_reset_2), .din(salsa_din_2), .dout(salsa_dout_2),
.shift(salsa_shift_2), .start(salsa_start_2), .busy(salsa_busy_2), .result(salsa_result_2) );
assign got_ticket1 = gn_match_1;
assign got_ticket2 = gn_match_2;
assign slave_nonces = { golden_nonce_2 , golden_nonce_1 };
`else
assign got_ticket1 = gn_match_1;
assign slave_nonces = golden_nonce_1;
`endif
assign miner_busy = ~ (|nonce_out_1[30:20]);
flasher #(
.BITS(CLOCK_FLASH_BITS)
) CLK_FLASH (
.clk(clk_dcm),
.flash(clock_flash)
);
pwm_fade PWM_FADE_NONCE (
.clk(clk_comm_buf),
.trigger(|new_nonces),
.drive(led_nonce_fade)
);
pwm_fade PWM_FADE_COMM (
.clk(clk_comm_buf),
.trigger(~TxD || ~RxD),
.drive(led_serial_fade)
);
`ifdef SIM
assign syncstart_mining = reset_a;
`else
assign syncstart_mining = start_mining;
`endif
always@ (posedge clk_dcm)
begin
if (got_ticket1)
syncticket1[0] <= ~syncticket1[0];
`ifdef DUALCORE
if (got_ticket2)
syncticket2[0] <= ~syncticket2[0];
`endif
syncloadnonce[3:1] <= syncloadnonce[2:0];
loadnonce <= (syncloadnonce[3] != syncloadnonce[2]);
end
always@ (posedge clk_comm_buf)
begin
syncticket1[3:1] <= syncticket1[2:0];
new_nonces[0] <= (syncticket1[3] != syncticket1[2]);
`ifdef DUALCORE
syncticket2[3:1] <= syncticket2[2:0];
new_nonces[1] <= (syncticket2[3] != syncticket2[2]);
`endif
syncstart_mining_d <= syncstart_mining;
if (syncstart_mining & ~syncstart_mining_d)
syncloadnonce[0] <= ~ syncloadnonce[0];
end
endmodule | module HASHVOODOO (
clk_p,
clk_n,
clk_comm,
RxD,
TxD,
led,
dip,
reset_a,
reset_b,
reset_select
); |
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
parameter CLOCK_RATE = 25000000;
parameter DCM_DIVIDER = 10;
parameter DCM_MULTIPLIER_START = 70;
parameter DCM_MULTIPLIER_CAP = 120;
parameter DCM_MULTIPLIER_MIN = 20;
parameter UART_BAUD_RATE = 115200;
parameter UART_SAMPLE_POINT = 8;
parameter CLOCK_FLASH_BITS = 26;
`ifdef DUALCORE
localparam LOCAL_MINERS = 2;
`else
localparam LOCAL_MINERS = 1;
`endif
localparam ADDRBITS = 12 - clog2(LOCAL_MINERS);
localparam SBITS = 8;
input clk_p;
input clk_n;
input clk_comm;
input RxD;
output TxD;
output [3:0] led;
input [3:0]dip;
input reset_a;
input reset_b;
input reset_select;
reg reset;
wire clk_buf;
wire clk_dcm;
wire clk_comm_buf;
wire clock_flash;
wire miner_busy;
wire serial_send;
wire serial_busy;
wire [31:0] golden_nonce;
wire [255:0] data1, data2;
wire [127:0] data3;
wire start_mining;
wire syncstart_mining;
reg syncstart_mining_d = 1'b0;
wire led_nonce_fade;
wire led_serial_fade;
wire dcm_prog_en;
wire dcm_prog_data;
wire dcm_prog_done;
wire dcm_valid;
wire dcm_reset = 1'b0;
wire identify_flag;
wire identify_flasher;
reg [3:0] syncticket1 = 0;
wire got_ticket1;
`ifdef DUALCORE
wire [63:0] slave_nonces;
reg [1:0] new_nonces;
reg [3:0] syncticket2 = 0;
wire got_ticket2;
`else
wire [31:0] slave_nonces;
reg [0:0] new_nonces;
`endif
assign led[0] = (led_serial_fade || identify_flasher);
assign led[1] = (clock_flash || ~dcm_valid || identify_flasher);
assign led[2] = (led_nonce_fade || identify_flasher);
assign led[3] = (~miner_busy || identify_flasher);
assign identify_flasher = (clock_flash && identify_flag);
`ifndef SIM
IBUFGDS #(
.DIFF_TERM("TRUE"),
.IOSTANDARD("DEFAULT")
) CLK_LVDS_BUF (
.O(clk_buf),
.I(clk_p),
.IB(clk_n)
);
BUFG CLK_COMM_BUF
(
.I (clk_comm),
.O (clk_comm_buf)
);
main_dcm #(
.DCM_DIVIDER(DCM_DIVIDER),
.DCM_MULTIPLIER(DCM_MULTIPLIER_START)
) MAINDCM(
.RESET(dcm_reset),
.CLK_VALID(dcm_valid),
.CLK_OSC(clk_buf),
.CLK_HASH(clk_dcm),
.PROGCLK(clk_comm_buf),
.PROGDATA(dcm_prog_data),
.PROGEN(dcm_prog_en),
.PROGDONE(dcm_prog_done)
);
`else
assign clk_buf = clk_p;
assign clk_dcm = clk_buf;
assign clk_comm_buf = clk_comm;
`endif
dcm_controller #(
.MAXIMUM_MULTIPLIER(DCM_MULTIPLIER_CAP),
.MINIMUM_MULTIPLIER(DCM_MULTIPLIER_MIN),
.INITIAL_MULTIPLIER(DCM_MULTIPLIER_START),
.INITIAL_DIVIDER(DCM_DIVIDER)
) DCM_CONTROL (
.clk(clk_comm_buf),
.data2({data2[255:96], data3[95:0]}),
.midstate(data1),
.start(start_mining),
.dcm_prog_clk(clk_comm_buf),
.dcm_prog_en(dcm_prog_en),
.dcm_prog_data(dcm_prog_data),
.dcm_prog_done(dcm_prog_done),
.identify(identify_flag)
);
hub_core #(
.SLAVES(LOCAL_MINERS)
) HUBCORE (
.hash_clk(clk_comm_buf),
.new_nonces(new_nonces),
.golden_nonce(golden_nonce),
.serial_send(serial_send),
.serial_busy(serial_busy),
.slave_nonces(slave_nonces)
);
wire unused_rx_busy;
serial_core #(
.CLOCK(CLOCK_RATE),
.BAUD(UART_BAUD_RATE),
.SAMPLE_POINT(UART_SAMPLE_POINT)
) SERIAL_COMM (
.clk(clk_comm_buf),
.rx(RxD),
.tx(TxD),
.rx_ready(start_mining),
.tx_ready(serial_send),
.data1(data1),
.data2(data2),
.data3(data3),
.word(golden_nonce),
.tx_busy(serial_busy),
.rx_busy(unused_rx_busy)
);
wire [31:0] unused_nonce_out1, unused_hash_out1;
wire [31:0] unused_nonce_out2, unused_hash_out2;
reg loadnonce = 1'b0;
reg [3:0]syncloadnonce = 3'd0;
wire [31:0] mod_target = 32'h00007fff;
wire gn_match_1;
wire [31:0] golden_nonce_1;
wire [31:0] hash_1, nonce_out_1;
wire salsa_busy_1, salsa_result_1, salsa_reset_1, salsa_start_1, salsa_shift_1;
wire [SBITS-1:0] salsa_din_1;
wire [SBITS-1:0] salsa_dout_1;
pbkdfengine #(.SBITS(SBITS)) P1
(.hash_clk(clk_dcm), .pbkdf_clk(clk_dcm), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb( 4'd0 ), .nonce_out(nonce_out_1), .golden_nonce_out(golden_nonce_1),
.golden_nonce_match(gn_match_1), .loadnonce(loadnonce),
.salsa_din(salsa_din_1), .salsa_dout(salsa_dout_1), .salsa_busy(salsa_busy_1), .salsa_result(salsa_result_1),
.salsa_reset(salsa_reset_1), .salsa_start(salsa_start_1), .salsa_shift(salsa_shift_1), .hash_out(hash_1));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1
(.hash_clk(clk_dcm), .reset(salsa_reset_1), .din(salsa_din_1), .dout(salsa_dout_1),
.shift(salsa_shift_1), .start(salsa_start_1), .busy(salsa_busy_1), .result(salsa_result_1) );
`ifdef DUALCORE
wire gn_match_2;
wire [31:0] golden_nonce_2;
wire [31:0] hash_2, nonce_out_2;
wire salsa_busy_2, salsa_result_2, salsa_reset_2, salsa_start_2, salsa_shift_2;
wire [SBITS-1:0] salsa_din_2;
wire [SBITS-1:0] salsa_dout_2;
pbkdfengine #(.SBITS(SBITS)) P2
(.hash_clk(clk_dcm), .pbkdf_clk(clk_dcm), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb( 4'd8 ), .nonce_out(nonce_out_2), .golden_nonce_out(golden_nonce_2),
.golden_nonce_match(gn_match_2), .loadnonce(loadnonce),
.salsa_din(salsa_din_2), .salsa_dout(salsa_dout_2), .salsa_busy(salsa_busy_2), .salsa_result(salsa_result_2),
.salsa_reset(salsa_reset_2), .salsa_start(salsa_start_2), .salsa_shift(salsa_shift_2), .hash_out(hash_2));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S2
(.hash_clk(clk_dcm), .reset(salsa_reset_2), .din(salsa_din_2), .dout(salsa_dout_2),
.shift(salsa_shift_2), .start(salsa_start_2), .busy(salsa_busy_2), .result(salsa_result_2) );
assign got_ticket1 = gn_match_1;
assign got_ticket2 = gn_match_2;
assign slave_nonces = { golden_nonce_2 , golden_nonce_1 };
`else
assign got_ticket1 = gn_match_1;
assign slave_nonces = golden_nonce_1;
`endif
assign miner_busy = ~ (|nonce_out_1[30:20]);
flasher #(
.BITS(CLOCK_FLASH_BITS)
) CLK_FLASH (
.clk(clk_dcm),
.flash(clock_flash)
);
pwm_fade PWM_FADE_NONCE (
.clk(clk_comm_buf),
.trigger(|new_nonces),
.drive(led_nonce_fade)
);
pwm_fade PWM_FADE_COMM (
.clk(clk_comm_buf),
.trigger(~TxD || ~RxD),
.drive(led_serial_fade)
);
`ifdef SIM
assign syncstart_mining = reset_a;
`else
assign syncstart_mining = start_mining;
`endif
always@ (posedge clk_dcm)
begin
if (got_ticket1)
syncticket1[0] <= ~syncticket1[0];
`ifdef DUALCORE
if (got_ticket2)
syncticket2[0] <= ~syncticket2[0];
`endif
syncloadnonce[3:1] <= syncloadnonce[2:0];
loadnonce <= (syncloadnonce[3] != syncloadnonce[2]);
end
always@ (posedge clk_comm_buf)
begin
syncticket1[3:1] <= syncticket1[2:0];
new_nonces[0] <= (syncticket1[3] != syncticket1[2]);
`ifdef DUALCORE
syncticket2[3:1] <= syncticket2[2:0];
new_nonces[1] <= (syncticket2[3] != syncticket2[2]);
`endif
syncstart_mining_d <= syncstart_mining;
if (syncstart_mining & ~syncstart_mining_d)
syncloadnonce[0] <= ~ syncloadnonce[0];
end
endmodule | 270 |
6,287 | data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v | 11,584,509 | hashvoodoo.v | v | 319 | 137 | [] | [] | [] | null | line:20: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:117: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS #(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/IBUFGDS\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/IBUFGDS.v\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/IBUFGDS.sv\n IBUFGDS\n IBUFGDS.v\n IBUFGDS.sv\n obj_dir/IBUFGDS\n obj_dir/IBUFGDS.v\n obj_dir/IBUFGDS.sv\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:127: Cannot find file containing module: \'BUFG\'\n BUFG CLK_COMM_BUF\n ^~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:134: Cannot find file containing module: \'main_dcm\'\n main_dcm #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:154: Cannot find file containing module: \'dcm_controller\'\n dcm_controller #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:172: Cannot find file containing module: \'hub_core\'\n hub_core #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:186: Cannot find file containing module: \'serial_core\'\n serial_core #(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:210: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance HASHVOODOO\n reg [3:0]syncloadnonce = 3\'d0;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:221: Cannot find file containing module: \'pbkdfengine\'\n pbkdfengine #(.SBITS(SBITS)) P1\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:228: Cannot find file containing module: \'salsaengine\'\n salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:263: Cannot find file containing module: \'flasher\'\n flasher #(\n ^~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:271: Cannot find file containing module: \'pwm_fade\'\n pwm_fade PWM_FADE_NONCE (\n ^~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:278: Cannot find file containing module: \'pwm_fade\'\n pwm_fade PWM_FADE_COMM (\n ^~~~~~~~\n%Error: Exiting due to 11 error(s), 1 warning(s)\n' | 7,133 | function | function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction | function integer clog2; |
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction | 270 |
6,292 | data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v | 11,584,509 | sha256_transform.v | v | 161 | 81 | [] | [] | [] | [(38, 116), (119, 160)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:73: Operator DIV expects 32 bits on the RHS, but RHS\'s VARREF \'LOOP\' generates 7 bits.\n : ... In instance sha256_transform\n for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:133: Cannot find file containing module: \'e0\'\n e0 e0_blk (rx_state[(((0)+1)*(32)-1):((0)*(32))], e0_w);\n ^~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/e0\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/e0.v\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/e0.sv\n e0\n e0.v\n e0.sv\n obj_dir/e0\n obj_dir/e0.v\n obj_dir/e0.sv\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:134: Cannot find file containing module: \'e1\'\n e1 e1_blk (rx_state[(((4)+1)*(32)-1):((4)*(32))], e1_w);\n ^~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:135: Cannot find file containing module: \'ch\'\n ch ch_blk (rx_state[(((4)+1)*(32)-1):((4)*(32))], rx_state[(((5)+1)*(32)-1):((5)*(32))], rx_state[(((6)+1)*(32)-1):((6)*(32))], ch_w);\n ^~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:136: Cannot find file containing module: \'maj\'\n maj maj_blk (rx_state[(((0)+1)*(32)-1):((0)*(32))], rx_state[(((1)+1)*(32)-1):((1)*(32))], rx_state[(((2)+1)*(32)-1):((2)*(32))], maj_w);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:137: Cannot find file containing module: \'s0\'\n s0 s0_blk (rx_w[63:32], s0_w);\n ^~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:138: Cannot find file containing module: \'s1\'\n s1 s1_blk (rx_w[479:448], s1_w);\n ^~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n' | 7,143 | module | module sha256_transform #(
parameter LOOP = 7'd64
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
wire [511:0] W;
wire [255:0] state;
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule | module sha256_transform #(
parameter LOOP = 7'd64
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
); |
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
wire [511:0] W;
wire [255:0] state;
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule | 270 |
6,293 | data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v | 11,584,509 | sha256_transform.v | v | 161 | 81 | [] | [] | [] | [(38, 116), (119, 160)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:73: Operator DIV expects 32 bits on the RHS, but RHS\'s VARREF \'LOOP\' generates 7 bits.\n : ... In instance sha256_transform\n for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:133: Cannot find file containing module: \'e0\'\n e0 e0_blk (rx_state[(((0)+1)*(32)-1):((0)*(32))], e0_w);\n ^~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/e0\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/e0.v\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/e0.sv\n e0\n e0.v\n e0.sv\n obj_dir/e0\n obj_dir/e0.v\n obj_dir/e0.sv\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:134: Cannot find file containing module: \'e1\'\n e1 e1_blk (rx_state[(((4)+1)*(32)-1):((4)*(32))], e1_w);\n ^~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:135: Cannot find file containing module: \'ch\'\n ch ch_blk (rx_state[(((4)+1)*(32)-1):((4)*(32))], rx_state[(((5)+1)*(32)-1):((5)*(32))], rx_state[(((6)+1)*(32)-1):((6)*(32))], ch_w);\n ^~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:136: Cannot find file containing module: \'maj\'\n maj maj_blk (rx_state[(((0)+1)*(32)-1):((0)*(32))], rx_state[(((1)+1)*(32)-1):((1)*(32))], rx_state[(((2)+1)*(32)-1):((2)*(32))], maj_w);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:137: Cannot find file containing module: \'s0\'\n s0 s0_blk (rx_w[63:32], s0_w);\n ^~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:138: Cannot find file containing module: \'s1\'\n s1 s1_blk (rx_w[479:448], s1_w);\n ^~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n' | 7,143 | module | module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule | module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state); |
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule | 270 |
6,297 | data/full_repos/permissive/11584509/experimental/CM1/uart_tx.v | 11,584,509 | uart_tx.v | v | 101 | 83 | [] | [] | [] | [(8, 100)] | null | null | 1: b"%Error: data/full_repos/permissive/11584509/experimental/CM1/uart_tx.v:42: Cannot find file containing module: 'uart_baudgenerator'\n uart_baudgenerator #(\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/uart_baudgenerator\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/uart_baudgenerator.v\n data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/uart_baudgenerator.sv\n uart_baudgenerator\n uart_baudgenerator.v\n uart_baudgenerator.sv\n obj_dir/uart_baudgenerator\n obj_dir/uart_baudgenerator.v\n obj_dir/uart_baudgenerator.sv\n%Error: Exiting due to 1 error(s)\n" | 7,147 | module | module uart_tx(
clk,
tx,
tx_byte,
start,
busy
);
parameter CLOCK = 25000000;
parameter BAUD = 9600;
input clk;
wire baudtick;
output reg tx;
input [7:0] tx_byte;
input start;
output busy;
reg [3:0] state = 0;
reg [7:0] byte_buf;
reg muxflag;
wire ready;
uart_baudgenerator #(
.CLOCK(CLOCK),
.BAUD(BAUD),
.ROUNDBITS(5)
) BAUDGEN (
.clk(clk),
.baudtick(baudtick)
);
assign ready = (state==0);
assign busy = ~ready;
always @(posedge clk)
if(ready & start)
byte_buf <= tx_byte;
always @(posedge clk)
case(state)
4'b0000: if(start) state <= 4'b0001;
4'b0001: if(baudtick) state <= 4'b0100;
4'b0100: if(baudtick) state <= 4'b1000;
4'b1000: if(baudtick) state <= 4'b1001;
4'b1001: if(baudtick) state <= 4'b1010;
4'b1010: if(baudtick) state <= 4'b1011;
4'b1011: if(baudtick) state <= 4'b1100;
4'b1100: if(baudtick) state <= 4'b1101;
4'b1101: if(baudtick) state <= 4'b1110;
4'b1110: if(baudtick) state <= 4'b1111;
4'b1111: if(baudtick) state <= 4'b0010;
4'b0010: if(baudtick) state <= 4'b0011;
4'b0011: if(baudtick) state <= 4'b0000;
default: if(baudtick) state <= 4'b0000;
endcase
always @(*)
case(state[2:0])
3'd0: muxflag <= byte_buf[0];
3'd1: muxflag <= byte_buf[1];
3'd2: muxflag <= byte_buf[2];
3'd3: muxflag <= byte_buf[3];
3'd4: muxflag <= byte_buf[4];
3'd5: muxflag <= byte_buf[5];
3'd6: muxflag <= byte_buf[6];
3'd7: muxflag <= byte_buf[7];
endcase
always @(posedge clk)
tx <= (state<4) | (state[3] & muxflag);
endmodule | module uart_tx(
clk,
tx,
tx_byte,
start,
busy
); |
parameter CLOCK = 25000000;
parameter BAUD = 9600;
input clk;
wire baudtick;
output reg tx;
input [7:0] tx_byte;
input start;
output busy;
reg [3:0] state = 0;
reg [7:0] byte_buf;
reg muxflag;
wire ready;
uart_baudgenerator #(
.CLOCK(CLOCK),
.BAUD(BAUD),
.ROUNDBITS(5)
) BAUDGEN (
.clk(clk),
.baudtick(baudtick)
);
assign ready = (state==0);
assign busy = ~ready;
always @(posedge clk)
if(ready & start)
byte_buf <= tx_byte;
always @(posedge clk)
case(state)
4'b0000: if(start) state <= 4'b0001;
4'b0001: if(baudtick) state <= 4'b0100;
4'b0100: if(baudtick) state <= 4'b1000;
4'b1000: if(baudtick) state <= 4'b1001;
4'b1001: if(baudtick) state <= 4'b1010;
4'b1010: if(baudtick) state <= 4'b1011;
4'b1011: if(baudtick) state <= 4'b1100;
4'b1100: if(baudtick) state <= 4'b1101;
4'b1101: if(baudtick) state <= 4'b1110;
4'b1110: if(baudtick) state <= 4'b1111;
4'b1111: if(baudtick) state <= 4'b0010;
4'b0010: if(baudtick) state <= 4'b0011;
4'b0011: if(baudtick) state <= 4'b0000;
default: if(baudtick) state <= 4'b0000;
endcase
always @(*)
case(state[2:0])
3'd0: muxflag <= byte_buf[0];
3'd1: muxflag <= byte_buf[1];
3'd2: muxflag <= byte_buf[2];
3'd3: muxflag <= byte_buf[3];
3'd4: muxflag <= byte_buf[4];
3'd5: muxflag <= byte_buf[5];
3'd6: muxflag <= byte_buf[6];
3'd7: muxflag <= byte_buf[7];
endcase
always @(posedge clk)
tx <= (state<4) | (state[3] & muxflag);
endmodule | 270 |
6,298 | data/full_repos/permissive/11584509/experimental/CM1/xilinx_ram.v | 11,584,509 | xilinx_ram.v | v | 31 | 55 | [] | [] | [] | [(3, 31)] | null | data/verilator_xmls/9ee8ec4c-b44a-4da8-93d1-b5706846912d.xml | null | 7,148 | module | module ram # ( parameter ADDRBITS=10 ) (
raddr,
waddr,
clock,
data,
wren,
q);
input [ADDRBITS-1:0] raddr;
input [ADDRBITS-1:0] waddr;
input clock;
input [255:0] data;
input wren;
output [255:0] q;
reg [255:0] store [(2 << (ADDRBITS-1))-1:0];
reg[ADDRBITS-1:0] raddr_reg;
always @ (posedge clock)
begin
raddr_reg <= raddr;
if (wren)
store[waddr] <= data;
end
assign q = store[raddr_reg];
endmodule | module ram # ( parameter ADDRBITS=10 ) (
raddr,
waddr,
clock,
data,
wren,
q); |
input [ADDRBITS-1:0] raddr;
input [ADDRBITS-1:0] waddr;
input clock;
input [255:0] data;
input wren;
output [255:0] q;
reg [255:0] store [(2 << (ADDRBITS-1))-1:0];
reg[ADDRBITS-1:0] raddr_reg;
always @ (posedge clock)
begin
raddr_reg <= raddr;
if (wren)
store[waddr] <= data;
end
assign q = store[raddr_reg];
endmodule | 270 |
6,300 | data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v | 11,584,509 | ltcminer.v | v | 210 | 127 | [] | [] | [] | null | line:43: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:66: Cannot find file containing module: \'main_pll\'\n main_pll #(.SPEED_MHZ(SPEED_MHZ)) pll_blk (osc_clk, hash_clk);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN,data/full_repos/permissive/11584509/main_pll\n data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN,data/full_repos/permissive/11584509/main_pll.v\n data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN,data/full_repos/permissive/11584509/main_pll.sv\n main_pll\n main_pll.v\n main_pll.sv\n obj_dir/main_pll\n obj_dir/main_pll.v\n obj_dir/main_pll.sv\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:87: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h7ff\' generates 31 bits.\n : ... In instance ltcminer\n reg [31:0] target = 31\'h000007ff; \n ^~~~~~~~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:111: Cannot find file containing module: \'pbkdfengine\'\n pbkdfengine #(.SBITS(SBITS)) P\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:118: Cannot find file containing module: \'salsaengine\'\n salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:159: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n : ... In instance ltcminer\n clear_nonces[port_counter] <= 1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:156: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n : ... In instance ltcminer\n if (new_nonces_flag[port_counter])\n ^\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:177: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT1")) data1_vw_blk(.probe(), .source(data1_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:178: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:179: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(128), .INSTANCE_ID("DAT3")) data3_vw_blk(.probe(), .source(data3_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:180: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(32), .INSTANCE_ID("TARG")) target_vw_blk(.probe(), .source(target_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:192: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce_out), .source());\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:193: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce_out), .source());\n ^~~~~~~~~~~~\n%Error: Exiting due to 9 error(s), 3 warning(s)\n' | 7,151 | module | module ltcminer (osc_clk);
`else
module ltcminer (osc_clk, LEDS_out);
`endif
`ifdef SPEED_MHZ
parameter SPEED_MHZ = `SPEED_MHZ;
`else
parameter SPEED_MHZ = 25;
`endif
`ifdef LOCAL_MINERS
parameter LOCAL_MINERS = `LOCAL_MINERS;
`else
parameter LOCAL_MINERS = 1;
`endif
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
`ifdef ADDRBITS
parameter ADDRBITS = `ADDRBITS;
`else
parameter ADDRBITS = 12 - clog2(LOCAL_MINERS);
`endif
localparam SBITS = 8;
input osc_clk;
`ifndef NOLEDS
output reg [7:0]LEDS_out;
`endif
wire hash_clk;
`ifndef SIM
main_pll #(.SPEED_MHZ(SPEED_MHZ)) pll_blk (osc_clk, hash_clk);
`else
assign hash_clk = osc_clk;
`endif
`ifndef SIM
reg [255:0] data1 = 256'd0;
reg [255:0] data2 = 256'd0;
reg [127:0] data3 = 128'd0;
`else
reg [255:0] data1 = 256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
reg [255:0] data2 = 256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756;
reg [127:0] data3 = 128'h0000318f7e71441b141fe951b2b0c7df;
`endif
reg [31:0] target = 31'h000007ff;
wire [31:0]golden_nonce_out;
wire [31:0] nonce_out;
wire loadnonce = 1'b0;
wire [LOCAL_MINERS*32-1:0] golden_nonce_i;
wire [LOCAL_MINERS-1:0] golden_nonce_match;
wire pbkdf_clk = hash_clk;
generate
genvar i;
for (i = 0; i < LOCAL_MINERS; i = i + 1)
begin: miners
wire [31:0] nonce_out_i;
wire [3:0] nonce_core = i;
wire gn_match;
wire salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift;
wire [SBITS-1:0] salsa_din;
wire [SBITS-1:0] salsa_dout;
wire [3:0] dummy;
pbkdfengine #(.SBITS(SBITS)) P
(.hash_clk(hash_clk), .pbkdf_clk(pbkdf_clk), .data1(data1), .data2(data2), .data3(data3), .target(target),
.nonce_msb({nonce_core}), .nonce_out(nonce_out_i), .golden_nonce_out(golden_nonce_i[(i+1)*32-1:i*32]),
.golden_nonce_match(golden_nonce_match[i]), .loadnonce(loadnonce),
.salsa_din(salsa_din), .salsa_dout(salsa_dout), .salsa_busy(salsa_busy), .salsa_result(salsa_result),
.salsa_reset(salsa_reset), .salsa_start(salsa_start), .salsa_shift(salsa_shift));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S
(.hash_clk(hash_clk), .reset(salsa_reset), .din(salsa_din), .dout(salsa_dout),
.shift(salsa_shift), .start(salsa_start), .busy(salsa_busy), .result(salsa_result) );
if (i==0)
assign nonce_out = nonce_out_i;
end
endgenerate
reg [LOCAL_MINERS-1:0]new_nonces_flag = 0;
reg [clog2(LOCAL_MINERS)+1:0] port_counter = 0;
reg [LOCAL_MINERS*32-1:0] nonces_shifted = 0;
assign golden_nonce_out = nonces_shifted[31:0];
reg [LOCAL_MINERS-1:0] clear_nonces = 0;
always @(posedge pbkdf_clk)
begin
new_nonces_flag <= (new_nonces_flag & ~clear_nonces) | golden_nonce_match;
if (port_counter == LOCAL_MINERS-1)
port_counter <= 0;
else
port_counter <= port_counter + 1'd1;
if (new_nonces_flag[port_counter])
begin
nonces_shifted <= golden_nonce_i >> port_counter*32;
clear_nonces[port_counter] <= 1;
end
else
begin
clear_nonces <= 0;
end
end
`ifndef SIM
wire [255:0] data1_vw;
wire [255:0] data2_vw;
wire [127:0] data3_vw;
wire [31:0] target_vw;
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT1")) data1_vw_blk(.probe(), .source(data1_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(128), .INSTANCE_ID("DAT3")) data3_vw_blk(.probe(), .source(data3_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(32), .INSTANCE_ID("TARG")) target_vw_blk(.probe(), .source(target_vw));
always @ (posedge pbkdf_clk)
begin
data1 <= data1_vw;
data2 <= data2_vw;
data3 <= data3_vw;
target <= target_vw;
end
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce_out), .source());
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce_out), .source());
`endif
`ifndef NOLEDS
always @(posedge pbkdf_clk) begin
`ifdef INVERTLEDS
LEDS_out <= ~nonce_out[15:8];
`else
LEDS_out <= nonce_out[15:8];
`endif
end
`endif
endmodule | module ltcminer (osc_clk); |
`else
module ltcminer (osc_clk, LEDS_out);
`endif
`ifdef SPEED_MHZ
parameter SPEED_MHZ = `SPEED_MHZ;
`else
parameter SPEED_MHZ = 25;
`endif
`ifdef LOCAL_MINERS
parameter LOCAL_MINERS = `LOCAL_MINERS;
`else
parameter LOCAL_MINERS = 1;
`endif
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
`ifdef ADDRBITS
parameter ADDRBITS = `ADDRBITS;
`else
parameter ADDRBITS = 12 - clog2(LOCAL_MINERS);
`endif
localparam SBITS = 8;
input osc_clk;
`ifndef NOLEDS
output reg [7:0]LEDS_out;
`endif
wire hash_clk;
`ifndef SIM
main_pll #(.SPEED_MHZ(SPEED_MHZ)) pll_blk (osc_clk, hash_clk);
`else
assign hash_clk = osc_clk;
`endif
`ifndef SIM
reg [255:0] data1 = 256'd0;
reg [255:0] data2 = 256'd0;
reg [127:0] data3 = 128'd0;
`else
reg [255:0] data1 = 256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
reg [255:0] data2 = 256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756;
reg [127:0] data3 = 128'h0000318f7e71441b141fe951b2b0c7df;
`endif
reg [31:0] target = 31'h000007ff;
wire [31:0]golden_nonce_out;
wire [31:0] nonce_out;
wire loadnonce = 1'b0;
wire [LOCAL_MINERS*32-1:0] golden_nonce_i;
wire [LOCAL_MINERS-1:0] golden_nonce_match;
wire pbkdf_clk = hash_clk;
generate
genvar i;
for (i = 0; i < LOCAL_MINERS; i = i + 1)
begin: miners
wire [31:0] nonce_out_i;
wire [3:0] nonce_core = i;
wire gn_match;
wire salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift;
wire [SBITS-1:0] salsa_din;
wire [SBITS-1:0] salsa_dout;
wire [3:0] dummy;
pbkdfengine #(.SBITS(SBITS)) P
(.hash_clk(hash_clk), .pbkdf_clk(pbkdf_clk), .data1(data1), .data2(data2), .data3(data3), .target(target),
.nonce_msb({nonce_core}), .nonce_out(nonce_out_i), .golden_nonce_out(golden_nonce_i[(i+1)*32-1:i*32]),
.golden_nonce_match(golden_nonce_match[i]), .loadnonce(loadnonce),
.salsa_din(salsa_din), .salsa_dout(salsa_dout), .salsa_busy(salsa_busy), .salsa_result(salsa_result),
.salsa_reset(salsa_reset), .salsa_start(salsa_start), .salsa_shift(salsa_shift));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S
(.hash_clk(hash_clk), .reset(salsa_reset), .din(salsa_din), .dout(salsa_dout),
.shift(salsa_shift), .start(salsa_start), .busy(salsa_busy), .result(salsa_result) );
if (i==0)
assign nonce_out = nonce_out_i;
end
endgenerate
reg [LOCAL_MINERS-1:0]new_nonces_flag = 0;
reg [clog2(LOCAL_MINERS)+1:0] port_counter = 0;
reg [LOCAL_MINERS*32-1:0] nonces_shifted = 0;
assign golden_nonce_out = nonces_shifted[31:0];
reg [LOCAL_MINERS-1:0] clear_nonces = 0;
always @(posedge pbkdf_clk)
begin
new_nonces_flag <= (new_nonces_flag & ~clear_nonces) | golden_nonce_match;
if (port_counter == LOCAL_MINERS-1)
port_counter <= 0;
else
port_counter <= port_counter + 1'd1;
if (new_nonces_flag[port_counter])
begin
nonces_shifted <= golden_nonce_i >> port_counter*32;
clear_nonces[port_counter] <= 1;
end
else
begin
clear_nonces <= 0;
end
end
`ifndef SIM
wire [255:0] data1_vw;
wire [255:0] data2_vw;
wire [127:0] data3_vw;
wire [31:0] target_vw;
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT1")) data1_vw_blk(.probe(), .source(data1_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(128), .INSTANCE_ID("DAT3")) data3_vw_blk(.probe(), .source(data3_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(32), .INSTANCE_ID("TARG")) target_vw_blk(.probe(), .source(target_vw));
always @ (posedge pbkdf_clk)
begin
data1 <= data1_vw;
data2 <= data2_vw;
data3 <= data3_vw;
target <= target_vw;
end
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce_out), .source());
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce_out), .source());
`endif
`ifndef NOLEDS
always @(posedge pbkdf_clk) begin
`ifdef INVERTLEDS
LEDS_out <= ~nonce_out[15:8];
`else
LEDS_out <= nonce_out[15:8];
`endif
end
`endif
endmodule | 270 |
6,301 | data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v | 11,584,509 | ltcminer.v | v | 210 | 127 | [] | [] | [] | null | line:43: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:66: Cannot find file containing module: \'main_pll\'\n main_pll #(.SPEED_MHZ(SPEED_MHZ)) pll_blk (osc_clk, hash_clk);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN,data/full_repos/permissive/11584509/main_pll\n data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN,data/full_repos/permissive/11584509/main_pll.v\n data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN,data/full_repos/permissive/11584509/main_pll.sv\n main_pll\n main_pll.v\n main_pll.sv\n obj_dir/main_pll\n obj_dir/main_pll.v\n obj_dir/main_pll.sv\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:87: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h7ff\' generates 31 bits.\n : ... In instance ltcminer\n reg [31:0] target = 31\'h000007ff; \n ^~~~~~~~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:111: Cannot find file containing module: \'pbkdfengine\'\n pbkdfengine #(.SBITS(SBITS)) P\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:118: Cannot find file containing module: \'salsaengine\'\n salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:159: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n : ... In instance ltcminer\n clear_nonces[port_counter] <= 1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:156: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n : ... In instance ltcminer\n if (new_nonces_flag[port_counter])\n ^\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:177: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT1")) data1_vw_blk(.probe(), .source(data1_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:178: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:179: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(128), .INSTANCE_ID("DAT3")) data3_vw_blk(.probe(), .source(data3_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:180: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(32), .INSTANCE_ID("TARG")) target_vw_blk(.probe(), .source(target_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:192: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce_out), .source());\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/ltcminer.v:193: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce_out), .source());\n ^~~~~~~~~~~~\n%Error: Exiting due to 9 error(s), 3 warning(s)\n' | 7,151 | function | function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction | function integer clog2; |
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction | 270 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.