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6,302 | data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/pbkdfengine.v | 11,584,509 | pbkdfengine.v | v | 643 | 153 | [] | [] | [] | [(25, 643)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/pbkdfengine.v:50: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance pbkdfengine\n reg [4:0]resetcycles = 4\'d0;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/pbkdfengine.v:200: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance pbkdfengine\n reg [3:0]Xbuf_load_request = 1\'b0;\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/pbkdfengine.v:201: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance pbkdfengine\n reg [3:0]shift_request = 1\'b0;\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/pbkdfengine.v:202: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance pbkdfengine\n reg [3:0]shift_acknowledge = 1\'b0;\n ^~~~\n%Error: data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN/pbkdfengine.v:634: Cannot find file containing module: \'sha256_transform\'\n sha256_transform # (.LOOP(64)) sha256_blk (\n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN,data/full_repos/permissive/11584509/sha256_transform\n data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN,data/full_repos/permissive/11584509/sha256_transform.v\n data/full_repos/permissive/11584509/experimental/DE2-115-SLOWSIXTEEN,data/full_repos/permissive/11584509/sha256_transform.sv\n sha256_transform\n sha256_transform.v\n sha256_transform.sv\n obj_dir/sha256_transform\n obj_dir/sha256_transform.v\n obj_dir/sha256_transform.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n' | 7,152 | module | module pbkdfengine
(hash_clk, pbkdf_clk, data1, data2, data3, target, nonce_msb, nonce_out, golden_nonce_out, golden_nonce_match, loadnonce,
salsa_din, salsa_dout, salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift);
input hash_clk;
input pbkdf_clk;
input [255:0] data1;
input [255:0] data2;
input [127:0] data3;
input [31:0] target;
input [3:0] nonce_msb;
output [31:0] nonce_out;
output [31:0] golden_nonce_out;
output golden_nonce_match;
input loadnonce;
parameter SBITS = 8;
input [SBITS-1:0] salsa_dout;
output [SBITS-1:0] salsa_din;
input salsa_busy, salsa_result;
output salsa_reset;
output salsa_start;
output reg salsa_shift = 1'b0;
reg [4:0]resetcycles = 4'd0;
reg reset = 1'b0;
assign salsa_reset = reset;
`ifdef WANTCYCLICRESET
reg [23:0]cycresetcount = 24'd0;
`endif
always @ (posedge pbkdf_clk)
begin
resetcycles <= resetcycles + 1'd1;
if (resetcycles == 0)
reset <= 1'b1;
if (resetcycles == 31)
begin
reset <= 1'b0;
resetcycles <= 31;
end
`ifdef WANTCYCLICRESET
cycresetcount <= cycresetcount + 1'd1;
if (cycresetcount == 2_500_000)
begin
cycresetcount <= 24'd0;
resetcycles <= 5'd0;
end
`endif
if (loadnonce)
resetcycles <= 5'd0;
end
`ifndef ICARUS
reg [31:0] nonce_previous_load = 32'hffffffff;
`endif
`ifndef NOMULTICORE
`ifdef SIM
reg [27:0] nonce_cnt = 28'h318f;
`else
reg [27:0] nonce_cnt = 28'd0;
`endif
wire [31:0] nonce;
assign nonce = { nonce_msb, nonce_cnt };
`else
reg [31:0] nonce = 32'd0;
`endif
assign nonce_out = nonce;
reg [31:0] nonce_sr = 32'd0;
reg [31:0] golden_nonce = 32'd0;
assign golden_nonce_out = golden_nonce;
reg golden_nonce_match = 1'b0;
reg [2:0] nonce_wait = 3'd0;
reg [255:0] rx_state;
reg [511:0] rx_input;
wire [255:0] tx_hash;
reg [255:0] khash = 256'd0;
reg [255:0] ihash = 256'd0;
reg [255:0] ohash = 256'd0;
`ifdef SIM
reg [255:0] final_hash = 256'd0;
`endif
reg [2:0] blockcnt = 3'd0;
reg [1023:0] Xbuf = 1024'd0;
reg [5:0] cnt = 6'd0;
wire feedback;
assign feedback = (cnt != 6'b0);
assign salsa_din = Xbuf[1023:1024-SBITS];
wire [1023:0] MixOutRewire;
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] mix;
assign mix = Xbuf[`IDX(i)];
assign MixOutRewire[`IDX(i)] = { mix[7:0], mix[15:8], mix[23:16], mix[31:24] };
end
endgenerate
reg SMixInRdy_state = 1'b0;
reg SMixOutRdy_state = 1'b0;
wire SMixInRdy;
wire SMixOutRdy;
reg Set_SMixInRdy = 1'b0;
reg Clr_SMixOutRdy = 1'b0;
wire Clr_SMixInRdy;
wire Set_SMixOutRdy;
reg [4:0]salsa_busy_d = 0;
reg [4:0]salsa_result_d = 0;
always @ (posedge hash_clk)
begin
salsa_busy_d[0] <= salsa_busy;
if (salsa_busy & ~ salsa_busy_d[0])
salsa_busy_d[1] <= ~ salsa_busy_d[1];
salsa_result_d[0] <= salsa_result;
if (salsa_result & ~ salsa_result_d[0])
salsa_result_d[1] <= ~ salsa_result_d[1];
end
always @ (posedge pbkdf_clk)
begin
salsa_busy_d[4:2] <= salsa_busy_d[3:1];
salsa_result_d[4:2] <= salsa_result_d[3:1];
if (Set_SMixInRdy)
SMixInRdy_state <= 1'b1;
if (Clr_SMixInRdy)
SMixInRdy_state <= 1'b0;
if (Set_SMixOutRdy)
SMixOutRdy_state <= 1'b1;
if (Clr_SMixOutRdy)
SMixOutRdy_state <= 1'b0;
if (reset)
begin
SMixInRdy_state <= 1'b0;
SMixOutRdy_state <= 1'b0;
end
end
assign Clr_SMixInRdy = SMixInRdy_state & (salsa_busy_d[3] ^ salsa_busy_d[4]);
assign Set_SMixOutRdy = ~SMixOutRdy_state & (salsa_result_d[3] ^ salsa_result_d[4]);
assign SMixInRdy = Clr_SMixInRdy ? 1'b0 : Set_SMixInRdy ? 1'b1 : SMixInRdy_state;
assign SMixOutRdy = Clr_SMixOutRdy ? 1'b0 : Set_SMixOutRdy ? 1'b1 : SMixOutRdy_state;
assign salsa_start = SMixInRdy;
reg [3:0]Xbuf_load_request = 1'b0;
reg [3:0]shift_request = 1'b0;
reg [3:0]shift_acknowledge = 1'b0;
parameter S_IDLE=0,
S_H1= 1, S_H2= 2, S_H3= 3, S_H4= 4, S_H5= 5, S_H6= 6,
S_I1= 7, S_I2= 8, S_I3= 9, S_I4=10, S_I5=11, S_I6=12,
S_O1=13, S_O2=14, S_O3=15,
S_B1=16, S_B2=17, S_B3=18, S_B4=19, S_B5=20, S_B6=21,
S_NONCE=22, S_SHIFT_IN=41, S_SHIFT_OUT=42,
S_R1=23, S_R2=24, S_R3=25, S_R4=26, S_R5=27, S_R6=28,
S_R7=29, S_R8=30, S_R9=31, S_R10=32, S_R11=33, S_R12=34,
S_R13=35, S_R14=36, S_R15=37, S_R16=38, S_R17=39, S_R18=40;
reg [5:0] state = S_IDLE;
reg mode = 0;
reg start_output = 0;
always @ (posedge pbkdf_clk)
begin
Set_SMixInRdy <= 1'b0;
Clr_SMixOutRdy <= 1'b0;
golden_nonce_match <= 1'b0;
shift_acknowledge[3:1] <= shift_acknowledge[2:0];
`ifdef ICARUS
if (loadnonce)
`else
if (loadnonce || (nonce_previous_load != data3[127:96]))
`endif
begin
`ifdef NOMULTICORE
nonce <= data3[127:96];
`else
nonce_cnt <= data3[123:96];
`endif
`ifndef ICARUS
nonce_previous_load <= data3[127:96];
`endif
end
if (reset == 1'b1)
begin
state <= S_IDLE;
start_output <= 1'b0;
end
else
begin
case (state)
S_IDLE: begin
if (SMixOutRdy & ~start_output)
begin
shift_request[0] <= ~shift_request[0];
state <= S_SHIFT_OUT;
end
else
begin
if (start_output ||
!SMixInRdy)
begin
start_output <= 1'b0;
mode <= 1'b0;
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { data2, data1 };
blockcnt <= 3'd1;
cnt <= 6'd0;
if (SMixOutRdy)
mode <= 1'b1;
state <= S_H1;
end
end
end
S_H1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H2;
end
end
S_H2: begin
state <= S_H3;
end
S_H3: begin
rx_state <= tx_hash;
rx_input <= { 384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000,
mode ? nonce_sr : nonce, data3[95:0] };
state <= S_H4;
end
S_H4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H5;
end
end
S_H5: begin
state <= S_H6;
end
S_H6: begin
khash <= tx_hash;
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h3636363636363636363636363636363636363636363636363636363636363636 ,
tx_hash ^ 256'h3636363636363636363636363636363636363636363636363636363636363636 };
cnt <= 6'd0;
if (mode)
state <= S_R1;
else
state <= S_I1;
end
S_I1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I2;
end
end
S_I2: begin
state <= S_I3;
end
S_I3: begin
rx_state <= tx_hash;
rx_input <= { data2, data1 };
state <= S_I4;
end
S_I4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I5;
end
end
S_I5: begin
state <= S_I6;
end
S_I6: begin
ihash <= tx_hash;
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_O1;
end
S_O1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_O2;
end
end
S_O2: begin
state <= S_O3;
end
S_O3: begin
ohash <= tx_hash;
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] };
blockcnt <= blockcnt + 1'd1;
cnt <= 6'd0;
state <= S_B1;
end
S_B1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B2;
end
end
S_B2: begin
state <= S_B3;
end
S_B3: begin
rx_state <= ohash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, tx_hash };
state <= S_B4;
end
S_B4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B5;
end
end
S_B5: begin
state <= S_B6;
end
S_B6: begin
khash <= tx_hash;
Xbuf_load_request[0] <= ~Xbuf_load_request[0];
if (blockcnt == 3'd5)
begin
nonce_wait <= 3'd7;
state <= S_NONCE;
end
else begin
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] };
blockcnt <= blockcnt + 1'd1;
cnt <= 6'd0;
state <= S_B1;
end
end
S_NONCE: begin
nonce_wait <= nonce_wait - 1'd1;
if (nonce_wait == 0)
begin
`ifndef NOMULTICORE
nonce_cnt <= nonce_cnt + 1'd1;
`else
nonce <= nonce + 1'd1;
`endif
shift_request[0] <= ~shift_request[0];
state <= S_SHIFT_IN;
end
end
S_SHIFT_IN: begin
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
Set_SMixInRdy <= 1'd1;
state <= S_IDLE;
end
end
S_SHIFT_OUT: begin
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
start_output <= 1'd1;
state <= S_IDLE;
end
end
S_R1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R2;
end
end
S_R2: begin
state <= S_R3;
end
S_R3: begin
rx_state <= tx_hash;
rx_input <= MixOutRewire[511:0];
state <= S_R4;
end
S_R4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R5;
end
end
S_R5: begin
state <= S_R6;
end
S_R6: begin
rx_state <= tx_hash;
rx_input <= MixOutRewire[1023:512];
state <= S_R7;
end
S_R7: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R8;
end
end
S_R8: begin
state <= S_R9;
end
S_R9: begin
rx_state <= tx_hash;
rx_input <= 512'h00000620000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000001;
state <= S_R10;
end
S_R10: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R11;
end
end
S_R11: begin
state <= S_R12;
end
S_R12: begin
ihash <= tx_hash;
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_R13;
end
S_R13: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R14;
end
end
S_R14: begin
state <= S_R15;
end
S_R15: begin
rx_state <= tx_hash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, ihash };
state <= S_R16;
end
S_R16: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R17;
end
end
S_R17: begin
state <= S_R18;
end
S_R18: begin
`ifdef SIM
final_hash <= tx_hash;
`endif
if ( { tx_hash[231:224], tx_hash[239:232], tx_hash[247:240], tx_hash[255:248] } < target)
begin
golden_nonce <= nonce_sr;
golden_nonce_match <= 1'b1;
end
state <= S_IDLE;
mode <= 1'b0;
Clr_SMixOutRdy <= 1'b1;
end
endcase
end
end
reg [10:0]shift_count = 11'd0;
always @ (posedge hash_clk)
begin
if (reset)
begin
salsa_shift <= 1'b0;
shift_count <= 11'd0;
end
Xbuf_load_request[3:1] <= Xbuf_load_request[2:0];
if (Xbuf_load_request[3] != Xbuf_load_request[2])
begin
Xbuf[255:0] <= Xbuf[511:256];
Xbuf[511:256] <= Xbuf[767:512];
Xbuf[767:512] <= Xbuf[1023:768];
Xbuf[1023:768] <= khash;
nonce_sr <= nonce;
end
shift_request[3:1] <= shift_request[2:0];
if (shift_request[3] != shift_request[2])
begin
salsa_shift <= 1'b1;
end
if (salsa_shift)
begin
shift_count <= shift_count + 1'b1;
Xbuf <= { Xbuf[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], salsa_dout };
end
if (shift_count == (1024+32)/SBITS-1)
begin
shift_acknowledge[0] = ~shift_acknowledge[0];
shift_count <= 0;
salsa_shift <= 0;
end
end
sha256_transform # (.LOOP(64)) sha256_blk (
.clk(pbkdf_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(rx_state),
.rx_input(rx_input),
.tx_hash(tx_hash)
);
endmodule | module pbkdfengine
(hash_clk, pbkdf_clk, data1, data2, data3, target, nonce_msb, nonce_out, golden_nonce_out, golden_nonce_match, loadnonce,
salsa_din, salsa_dout, salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift); |
input hash_clk;
input pbkdf_clk;
input [255:0] data1;
input [255:0] data2;
input [127:0] data3;
input [31:0] target;
input [3:0] nonce_msb;
output [31:0] nonce_out;
output [31:0] golden_nonce_out;
output golden_nonce_match;
input loadnonce;
parameter SBITS = 8;
input [SBITS-1:0] salsa_dout;
output [SBITS-1:0] salsa_din;
input salsa_busy, salsa_result;
output salsa_reset;
output salsa_start;
output reg salsa_shift = 1'b0;
reg [4:0]resetcycles = 4'd0;
reg reset = 1'b0;
assign salsa_reset = reset;
`ifdef WANTCYCLICRESET
reg [23:0]cycresetcount = 24'd0;
`endif
always @ (posedge pbkdf_clk)
begin
resetcycles <= resetcycles + 1'd1;
if (resetcycles == 0)
reset <= 1'b1;
if (resetcycles == 31)
begin
reset <= 1'b0;
resetcycles <= 31;
end
`ifdef WANTCYCLICRESET
cycresetcount <= cycresetcount + 1'd1;
if (cycresetcount == 2_500_000)
begin
cycresetcount <= 24'd0;
resetcycles <= 5'd0;
end
`endif
if (loadnonce)
resetcycles <= 5'd0;
end
`ifndef ICARUS
reg [31:0] nonce_previous_load = 32'hffffffff;
`endif
`ifndef NOMULTICORE
`ifdef SIM
reg [27:0] nonce_cnt = 28'h318f;
`else
reg [27:0] nonce_cnt = 28'd0;
`endif
wire [31:0] nonce;
assign nonce = { nonce_msb, nonce_cnt };
`else
reg [31:0] nonce = 32'd0;
`endif
assign nonce_out = nonce;
reg [31:0] nonce_sr = 32'd0;
reg [31:0] golden_nonce = 32'd0;
assign golden_nonce_out = golden_nonce;
reg golden_nonce_match = 1'b0;
reg [2:0] nonce_wait = 3'd0;
reg [255:0] rx_state;
reg [511:0] rx_input;
wire [255:0] tx_hash;
reg [255:0] khash = 256'd0;
reg [255:0] ihash = 256'd0;
reg [255:0] ohash = 256'd0;
`ifdef SIM
reg [255:0] final_hash = 256'd0;
`endif
reg [2:0] blockcnt = 3'd0;
reg [1023:0] Xbuf = 1024'd0;
reg [5:0] cnt = 6'd0;
wire feedback;
assign feedback = (cnt != 6'b0);
assign salsa_din = Xbuf[1023:1024-SBITS];
wire [1023:0] MixOutRewire;
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] mix;
assign mix = Xbuf[`IDX(i)];
assign MixOutRewire[`IDX(i)] = { mix[7:0], mix[15:8], mix[23:16], mix[31:24] };
end
endgenerate
reg SMixInRdy_state = 1'b0;
reg SMixOutRdy_state = 1'b0;
wire SMixInRdy;
wire SMixOutRdy;
reg Set_SMixInRdy = 1'b0;
reg Clr_SMixOutRdy = 1'b0;
wire Clr_SMixInRdy;
wire Set_SMixOutRdy;
reg [4:0]salsa_busy_d = 0;
reg [4:0]salsa_result_d = 0;
always @ (posedge hash_clk)
begin
salsa_busy_d[0] <= salsa_busy;
if (salsa_busy & ~ salsa_busy_d[0])
salsa_busy_d[1] <= ~ salsa_busy_d[1];
salsa_result_d[0] <= salsa_result;
if (salsa_result & ~ salsa_result_d[0])
salsa_result_d[1] <= ~ salsa_result_d[1];
end
always @ (posedge pbkdf_clk)
begin
salsa_busy_d[4:2] <= salsa_busy_d[3:1];
salsa_result_d[4:2] <= salsa_result_d[3:1];
if (Set_SMixInRdy)
SMixInRdy_state <= 1'b1;
if (Clr_SMixInRdy)
SMixInRdy_state <= 1'b0;
if (Set_SMixOutRdy)
SMixOutRdy_state <= 1'b1;
if (Clr_SMixOutRdy)
SMixOutRdy_state <= 1'b0;
if (reset)
begin
SMixInRdy_state <= 1'b0;
SMixOutRdy_state <= 1'b0;
end
end
assign Clr_SMixInRdy = SMixInRdy_state & (salsa_busy_d[3] ^ salsa_busy_d[4]);
assign Set_SMixOutRdy = ~SMixOutRdy_state & (salsa_result_d[3] ^ salsa_result_d[4]);
assign SMixInRdy = Clr_SMixInRdy ? 1'b0 : Set_SMixInRdy ? 1'b1 : SMixInRdy_state;
assign SMixOutRdy = Clr_SMixOutRdy ? 1'b0 : Set_SMixOutRdy ? 1'b1 : SMixOutRdy_state;
assign salsa_start = SMixInRdy;
reg [3:0]Xbuf_load_request = 1'b0;
reg [3:0]shift_request = 1'b0;
reg [3:0]shift_acknowledge = 1'b0;
parameter S_IDLE=0,
S_H1= 1, S_H2= 2, S_H3= 3, S_H4= 4, S_H5= 5, S_H6= 6,
S_I1= 7, S_I2= 8, S_I3= 9, S_I4=10, S_I5=11, S_I6=12,
S_O1=13, S_O2=14, S_O3=15,
S_B1=16, S_B2=17, S_B3=18, S_B4=19, S_B5=20, S_B6=21,
S_NONCE=22, S_SHIFT_IN=41, S_SHIFT_OUT=42,
S_R1=23, S_R2=24, S_R3=25, S_R4=26, S_R5=27, S_R6=28,
S_R7=29, S_R8=30, S_R9=31, S_R10=32, S_R11=33, S_R12=34,
S_R13=35, S_R14=36, S_R15=37, S_R16=38, S_R17=39, S_R18=40;
reg [5:0] state = S_IDLE;
reg mode = 0;
reg start_output = 0;
always @ (posedge pbkdf_clk)
begin
Set_SMixInRdy <= 1'b0;
Clr_SMixOutRdy <= 1'b0;
golden_nonce_match <= 1'b0;
shift_acknowledge[3:1] <= shift_acknowledge[2:0];
`ifdef ICARUS
if (loadnonce)
`else
if (loadnonce || (nonce_previous_load != data3[127:96]))
`endif
begin
`ifdef NOMULTICORE
nonce <= data3[127:96];
`else
nonce_cnt <= data3[123:96];
`endif
`ifndef ICARUS
nonce_previous_load <= data3[127:96];
`endif
end
if (reset == 1'b1)
begin
state <= S_IDLE;
start_output <= 1'b0;
end
else
begin
case (state)
S_IDLE: begin
if (SMixOutRdy & ~start_output)
begin
shift_request[0] <= ~shift_request[0];
state <= S_SHIFT_OUT;
end
else
begin
if (start_output ||
!SMixInRdy)
begin
start_output <= 1'b0;
mode <= 1'b0;
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { data2, data1 };
blockcnt <= 3'd1;
cnt <= 6'd0;
if (SMixOutRdy)
mode <= 1'b1;
state <= S_H1;
end
end
end
S_H1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H2;
end
end
S_H2: begin
state <= S_H3;
end
S_H3: begin
rx_state <= tx_hash;
rx_input <= { 384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000,
mode ? nonce_sr : nonce, data3[95:0] };
state <= S_H4;
end
S_H4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H5;
end
end
S_H5: begin
state <= S_H6;
end
S_H6: begin
khash <= tx_hash;
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h3636363636363636363636363636363636363636363636363636363636363636 ,
tx_hash ^ 256'h3636363636363636363636363636363636363636363636363636363636363636 };
cnt <= 6'd0;
if (mode)
state <= S_R1;
else
state <= S_I1;
end
S_I1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I2;
end
end
S_I2: begin
state <= S_I3;
end
S_I3: begin
rx_state <= tx_hash;
rx_input <= { data2, data1 };
state <= S_I4;
end
S_I4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I5;
end
end
S_I5: begin
state <= S_I6;
end
S_I6: begin
ihash <= tx_hash;
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_O1;
end
S_O1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_O2;
end
end
S_O2: begin
state <= S_O3;
end
S_O3: begin
ohash <= tx_hash;
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] };
blockcnt <= blockcnt + 1'd1;
cnt <= 6'd0;
state <= S_B1;
end
S_B1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B2;
end
end
S_B2: begin
state <= S_B3;
end
S_B3: begin
rx_state <= ohash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, tx_hash };
state <= S_B4;
end
S_B4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B5;
end
end
S_B5: begin
state <= S_B6;
end
S_B6: begin
khash <= tx_hash;
Xbuf_load_request[0] <= ~Xbuf_load_request[0];
if (blockcnt == 3'd5)
begin
nonce_wait <= 3'd7;
state <= S_NONCE;
end
else begin
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] };
blockcnt <= blockcnt + 1'd1;
cnt <= 6'd0;
state <= S_B1;
end
end
S_NONCE: begin
nonce_wait <= nonce_wait - 1'd1;
if (nonce_wait == 0)
begin
`ifndef NOMULTICORE
nonce_cnt <= nonce_cnt + 1'd1;
`else
nonce <= nonce + 1'd1;
`endif
shift_request[0] <= ~shift_request[0];
state <= S_SHIFT_IN;
end
end
S_SHIFT_IN: begin
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
Set_SMixInRdy <= 1'd1;
state <= S_IDLE;
end
end
S_SHIFT_OUT: begin
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
start_output <= 1'd1;
state <= S_IDLE;
end
end
S_R1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R2;
end
end
S_R2: begin
state <= S_R3;
end
S_R3: begin
rx_state <= tx_hash;
rx_input <= MixOutRewire[511:0];
state <= S_R4;
end
S_R4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R5;
end
end
S_R5: begin
state <= S_R6;
end
S_R6: begin
rx_state <= tx_hash;
rx_input <= MixOutRewire[1023:512];
state <= S_R7;
end
S_R7: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R8;
end
end
S_R8: begin
state <= S_R9;
end
S_R9: begin
rx_state <= tx_hash;
rx_input <= 512'h00000620000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000001;
state <= S_R10;
end
S_R10: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R11;
end
end
S_R11: begin
state <= S_R12;
end
S_R12: begin
ihash <= tx_hash;
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_R13;
end
S_R13: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R14;
end
end
S_R14: begin
state <= S_R15;
end
S_R15: begin
rx_state <= tx_hash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, ihash };
state <= S_R16;
end
S_R16: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R17;
end
end
S_R17: begin
state <= S_R18;
end
S_R18: begin
`ifdef SIM
final_hash <= tx_hash;
`endif
if ( { tx_hash[231:224], tx_hash[239:232], tx_hash[247:240], tx_hash[255:248] } < target)
begin
golden_nonce <= nonce_sr;
golden_nonce_match <= 1'b1;
end
state <= S_IDLE;
mode <= 1'b0;
Clr_SMixOutRdy <= 1'b1;
end
endcase
end
end
reg [10:0]shift_count = 11'd0;
always @ (posedge hash_clk)
begin
if (reset)
begin
salsa_shift <= 1'b0;
shift_count <= 11'd0;
end
Xbuf_load_request[3:1] <= Xbuf_load_request[2:0];
if (Xbuf_load_request[3] != Xbuf_load_request[2])
begin
Xbuf[255:0] <= Xbuf[511:256];
Xbuf[511:256] <= Xbuf[767:512];
Xbuf[767:512] <= Xbuf[1023:768];
Xbuf[1023:768] <= khash;
nonce_sr <= nonce;
end
shift_request[3:1] <= shift_request[2:0];
if (shift_request[3] != shift_request[2])
begin
salsa_shift <= 1'b1;
end
if (salsa_shift)
begin
shift_count <= shift_count + 1'b1;
Xbuf <= { Xbuf[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], salsa_dout };
end
if (shift_count == (1024+32)/SBITS-1)
begin
shift_acknowledge[0] = ~shift_acknowledge[0];
shift_count <= 0;
salsa_shift <= 0;
end
end
sha256_transform # (.LOOP(64)) sha256_blk (
.clk(pbkdf_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(rx_state),
.rx_input(rx_input),
.tx_hash(tx_hash)
);
endmodule | 270 |
6,304 | data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v | 11,584,509 | salsaengine.v | v | 544 | 193 | [] | [] | [] | null | line:54: before: "integer" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:84: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance salsaengine\n reg [5:0] mcount = 5\'d0; \n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:197: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance salsaengine\n assign rd_addr = { phase_addr+1, addrsourceSave_in ? memtop[ADDRBITS-THREADS_BITS:1] : adj_addr }; \n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:197: Unsized numbers/parameters not allowed in replications.\n : ... In instance salsaengine\n assign rd_addr = { phase_addr+1, addrsourceSave_in ? memtop[ADDRBITS-THREADS_BITS:1] : adj_addr }; \n ^\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:215: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram1_blk (rd_addr1, wr_addr1, ram_clk, ram1_din, ram_wren_d, ram1_dout);\n ^~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A,data/full_repos/permissive/11584509/ram\n data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A,data/full_repos/permissive/11584509/ram.v\n data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A,data/full_repos/permissive/11584509/ram.sv\n ram\n ram.v\n ram.sv\n obj_dir/ram\n obj_dir/ram.v\n obj_dir/ram.sv\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:216: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram2_blk (rd_addr2, wr_addr2, ram_clk, ram2_din, ram_wren_d, ram2_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:217: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram3_blk (rd_addr3, wr_addr3, ram_clk, ram3_din, ram_wren_d, ram3_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:218: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram4_blk (rd_addr4, wr_addr4, ram_clk, ram4_din, ram_wren_d, ram4_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:224: Cannot find file containing module: \'salsa\'\n salsa salsa_blk (hash_clk, mixfeedback_d, X0, X1, Xmix, X0out, X1out, Xaddr);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:240: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n : ... In instance salsaengine\n assign { mstate_in, mcount_in, writeaddr_in, cycle_in, doneROM_in, mixfeedback_in, addrsourceMix_in, addrsourceSave_in, mixspecial_in, intcycles_in} = (phase == THREADS) ? 0 : sstate[phase];\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:240: Operator ASSIGNW expects 41 bits on the Assign RHS, but Assign RHS\'s COND generates 42 bits.\n : ... In instance salsaengine\n assign { mstate_in, mcount_in, writeaddr_in, cycle_in, doneROM_in, mixfeedback_in, addrsourceMix_in, addrsourceSave_in, mixspecial_in, intcycles_in} = (phase == THREADS) ? 0 : sstate[phase];\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:274: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n : ... In instance salsaengine\n sstate[phase_d] <= reset ? 0 : { mstate, mcount, writeaddr, cycle, doneROM, mixfeedback, addrsourceMix,\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:274: Operator COND expects 42 bits on the Conditional False, but Conditional False\'s REPLICATE generates 41 bits.\n : ... In instance salsaengine\n sstate[phase_d] <= reset ? 0 : { mstate, mcount, writeaddr, cycle, doneROM, mixfeedback, addrsourceMix,\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:297: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'phase\' generates 4 bits.\n : ... In instance salsaengine\n phase_addr_d1 <= phase;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:298: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'phase\' generates 4 bits.\n : ... In instance salsaengine\n phase_addr_d2 <= phase;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:299: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'phase\' generates 4 bits.\n : ... In instance salsaengine\n phase_addr_d3 <= phase;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:300: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'phase\' generates 4 bits.\n : ... In instance salsaengine\n phase_addr_d4 <= phase;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:325: Operator EQ expects 32 or 19 bits on the LHS, but LHS\'s VARREF \'start_count\' generates 16 bits.\n : ... In instance salsaengine\n if (reset || start_count == START_INTERVAL)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:343: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n : ... In instance salsaengine\n nonce_sr <= snonce[phase_d]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:344: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n : ... In instance salsaengine\n snonce[phase_d] <= nonce_sr;\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:419: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance salsaengine\n intcycles <= { {THREADS_BITS+12-ADDRBITSX{1\'b0}}, Xaddr[12-ADDRBITSX:0] }; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:422: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance salsaengine\n intcycles <= { {THREADS_BITS+11-ADDRBITSX{1\'b0}}, 1\'b1, Xaddr[12-ADDRBITSX:0] };\n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:489: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance salsaengine\n intcycles <= { {THREADS_BITS+12-ADDRBITSX{1\'b0}}, Xaddr[12-ADDRBITSX:0] }; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:492: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance salsaengine\n intcycles <= { {THREADS_BITS+11-ADDRBITSX{1\'b0}}, 1\'b1, Xaddr[12-ADDRBITSX:0] };\n ^~\n%Error: Exiting due to 5 error(s), 18 warning(s)\n' | 7,161 | module | module salsaengine (hash_clk, reset, din, dout, shift, start, busy, result );
input hash_clk;
input reset;
input din;
input shift;
input start;
output busy;
output reg result = 1'b0;
output dout;
parameter ADDRBITS = 12;
parameter THREADS = 8;
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
parameter THREADS_BITS = clog2(THREADS);
parameter ADDRBITSX = (ADDRBITS == 13) ? ADDRBITS-1 : ADDRBITS;
reg [THREADS_BITS:0]phase = 0;
reg [THREADS_BITS:0]phase_d = THREADS;
always @ (posedge hash_clk)
begin
phase <= (phase == THREADS) ? 0 : phase + 1;
phase_d <= phase;
end
parameter XSnull = 0, XSload = 1, XSmix = 2, XSram = 4;
reg [2:0] XCtl = XSnull;
parameter R_IDLE=0, R_START=1, R_WRITE=2, R_MIX=4, R_INT=8;
reg [3:0] mstate = R_IDLE;
reg [10:0] cycle = 11'd0;
reg [5:0] mcount = 5'd0;
reg doneROM = 1'd0;
reg mixfeedback = 1'b0;
reg mixfeedback_d = 1'b0;
reg addrsourceMix = 1'b0;
reg addrsourceMix_d = 1'b0;
reg addrsourceSave = 1'b0;
reg mixspecial = 1'b0;
reg xoren = 1'b1;
reg [THREADS_BITS+1:0] intcycles = 0;
wire [511:0] Xmix;
reg [511:0] X0;
reg [511:0] X1;
wire [511:0] X0in;
wire [511:0] X1in;
wire [511:0] X0out;
wire [511:0] X1out;
reg [1023:0] salsaShiftReg;
reg [31:0] nonce_sr;
assign dout = salsaShiftReg[1023];
reg [511:0] Xmix_d;
reg [511:0] X1out_d;
reg [THREADS_BITS+38:0] sstate [THREADS-1:0];
wire [3:0] mstate_in;
wire [10:0] cycle_in;
wire [5:0] mcount_in;
wire [9:0] writeaddr_in;
wire doneROM_in;
wire mixfeedback_in;
wire addrsourceMix_in;
wire addrsourceSave_in;
wire mixspecial_in;
wire [THREADS_BITS+1:0] intcycles_in;
reg [31:0] snonce [THREADS-1:0];
wire [1023:0] X;
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] tmp;
assign tmp = salsaShiftReg[`IDX(i)];
assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] };
end
endgenerate
reg [9:0] writeaddr = 10'd0;
(* S = "TRUE" *) reg [9:0] writeaddr_d1 = 10'd0;
(* S = "TRUE" *) reg [9:0] writeaddr_d2 = 10'd0;
(* S = "TRUE" *) reg [9:0] writeaddr_d3 = 10'd0;
(* S = "TRUE" *) reg [9:0] writeaddr_d4 = 10'd0;
wire [9:0] Xaddr;
wire [ADDRBITS-1:0]rd_addr;
(* S = "TRUE" *) wire [ADDRBITS-1:0]wr_addr1;
(* S = "TRUE" *) wire [ADDRBITS-1:0]wr_addr2;
(* S = "TRUE" *) wire [ADDRBITS-1:0]wr_addr3;
(* S = "TRUE" *) wire [ADDRBITS-1:0]wr_addr4;
wire [255:0]ram1_din;
wire [255:0]ram1_dout;
wire [255:0]ram2_din;
wire [255:0]ram2_dout;
wire [255:0]ram3_din;
wire [255:0]ram3_dout;
wire [255:0]ram4_din;
wire [255:0]ram4_dout;
wire [1023:0]ramout;
reg ram_wren = 1'b0;
reg ram_wren_d = 1'b0;
wire ram_clk;
assign ram_clk = hash_clk;
wire [15:0] memtop = 16'hfffe;
wire [ADDRBITS-THREADS_BITS-1:0] adj_addr;
if (ADDRBITS < 13)
assign adj_addr = (Xaddr[9:13-ADDRBITS] == memtop[9:13-ADDRBITS]) ?
memtop[ADDRBITS-THREADS_BITS-1:0] : Xaddr[9:13-ADDRBITS];
else
assign adj_addr = Xaddr;
wire [THREADS_BITS-1:0] phase_addr;
(* S = "TRUE" *) reg [THREADS_BITS-1:0] phase_addr_d1;
(* S = "TRUE" *) reg [THREADS_BITS-1:0] phase_addr_d2;
(* S = "TRUE" *) reg [THREADS_BITS-1:0] phase_addr_d3;
(* S = "TRUE" *) reg [THREADS_BITS-1:0] phase_addr_d4;
assign phase_addr = phase[THREADS_BITS-1:0];
assign rd_addr = { phase_addr+1, addrsourceSave_in ? memtop[ADDRBITS-THREADS_BITS:1] : adj_addr };
assign wr_addr1 = { phase_addr_d1, writeaddr_d1[9:13-ADDRBITS] };
assign wr_addr2 = { phase_addr_d2, writeaddr_d2[9:13-ADDRBITS] };
assign wr_addr3 = { phase_addr_d3, writeaddr_d3[9:13-ADDRBITS] };
assign wr_addr4 = { phase_addr_d4, writeaddr_d4[9:13-ADDRBITS] };
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_1 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_2 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_3 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_4 = 0;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr1 = rd_addr | rd_addr_z_1;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr2 = rd_addr | rd_addr_z_2;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr3 = rd_addr | rd_addr_z_3;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr4 = rd_addr | rd_addr_z_4;
ram # (.ADDRBITS(ADDRBITS)) ram1_blk (rd_addr1, wr_addr1, ram_clk, ram1_din, ram_wren_d, ram1_dout);
ram # (.ADDRBITS(ADDRBITS)) ram2_blk (rd_addr2, wr_addr2, ram_clk, ram2_din, ram_wren_d, ram2_dout);
ram # (.ADDRBITS(ADDRBITS)) ram3_blk (rd_addr3, wr_addr3, ram_clk, ram3_din, ram_wren_d, ram3_dout);
ram # (.ADDRBITS(ADDRBITS)) ram4_blk (rd_addr4, wr_addr4, ram_clk, ram4_din, ram_wren_d, ram4_dout);
assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout };
assign { ram4_din, ram3_din, ram2_din, ram1_din } = addrsourceMix_d ? { Xmix_d, X1out_d} : { X1, X0} ;
salsa salsa_blk (hash_clk, mixfeedback_d, X0, X1, Xmix, X0out, X1out, Xaddr);
wire [511:0] Zbits;
assign Zbits = {512{xoren}};
assign X0in = (XCtl==XSmix) ? X1out : (XCtl==XSram) ? ((mixspecial ? X1out : X0out) & Zbits) ^ ramout[511:0] : (XCtl==XSload) ? X[511:0] : X0out;
assign X1in = (XCtl==XSmix) ? Xmix : (XCtl==XSram) ? ((mixspecial ? Xmix : X1out) & Zbits) ^ ramout[1023:512] : (XCtl==XSload) ? X[1023:512] : X1out;
assign { mstate_in, mcount_in, writeaddr_in, cycle_in, doneROM_in, mixfeedback_in, addrsourceMix_in, addrsourceSave_in, mixspecial_in, intcycles_in} = (phase == THREADS) ? 0 : sstate[phase];
reg busy_flag = 1'b0;
`ifdef ONETHREAD
reg start_once = 1'b0;
wire start_flag;
assign start_flag = start & ~start_once;
assign busy = busy_flag;
`else
reg [15:0] start_count = 0;
parameter START_INTERVAL = ((ADDRBITS == 12) ? 184320 : (ADDRBITS == 11) ? 258048 : 405504) / THREADS;
reg start_flag = 1'b0;
assign busy = busy_flag;
`endif
always @ (posedge hash_clk)
begin
X0 <= X0in;
X1 <= X1in;
if (phase_d != THREADS)
sstate[phase_d] <= reset ? 0 : { mstate, mcount, writeaddr, cycle, doneROM, mixfeedback, addrsourceMix,
addrsourceSave, mixspecial, intcycles };
mstate <= mstate_in;
mcount <= mcount_in;
writeaddr <= writeaddr_in;
cycle <= cycle_in;
intcycles <= intcycles_in;
doneROM <= doneROM_in;
mixfeedback <= mixfeedback_in;
addrsourceMix <= addrsourceMix_in;
addrsourceSave <= addrsourceSave_in;
mixspecial <= mixspecial_in;
mixfeedback_d <= mixfeedback;
addrsourceMix_d <= addrsourceMix;
ram_wren_d <= ram_wren;
writeaddr_d1 <= addrsourceMix ? memtop[10:1] : writeaddr;
writeaddr_d2 <= addrsourceMix ? memtop[10:1] : writeaddr;
writeaddr_d3 <= addrsourceMix ? memtop[10:1] : writeaddr;
writeaddr_d4 <= addrsourceMix ? memtop[10:1] : writeaddr;
phase_addr_d1 <= phase;
phase_addr_d2 <= phase;
phase_addr_d3 <= phase;
phase_addr_d4 <= phase;
rd_addr_z_1 <= {ADDRBITS{reset}};
rd_addr_z_2 <= {ADDRBITS{reset}};
rd_addr_z_3 <= {ADDRBITS{reset}};
rd_addr_z_4 <= {ADDRBITS{reset}};
Xmix_d <= Xmix;
X1out_d <= X1out;
XCtl <= XSnull;
addrsourceSave <= 0;
ram_wren <= 0;
xoren <= 1;
`ifdef ONETHREAD
if (start)
start_once <= 1'b1;
if (reset)
start_once <= 1'b0;
`else
start_count <= start_count + 1;
if (reset || start_count == START_INTERVAL)
begin
start_count <= 0;
if (~reset && start)
start_flag <= 1'b1;
end
`endif
if (shift)
begin
salsaShiftReg <= { salsaShiftReg[1022:0], nonce_sr[31] };
nonce_sr <= { nonce_sr[30:0], din };
end
else
if (XCtl==XSload && phase_d != THREADS)
begin
salsaShiftReg <= { Xmix, X1out };
nonce_sr <= snonce[phase_d];
snonce[phase_d] <= nonce_sr;
end
if (reset == 1'b1)
begin
mstate <= R_IDLE;
busy_flag <= 1'b0;
result <= 1'b0;
end
else
begin
case (mstate_in)
R_IDLE: begin
if ((phase!=THREADS) && start_flag)
begin
XCtl <= XSload;
`ifndef ONETHREAD
start_flag <= 1'b0;
`endif
busy_flag <= 1'b0;
mstate <= R_START;
end
end
R_START: begin
writeaddr <= 0;
mcount <= 0;
cycle <= 0;
mixfeedback <= 1'b0;
addrsourceMix <= 1'b0;
mixspecial <= 1'b0;
doneROM <= 1'b0;
busy_flag <= 1'b1;
result <= 1'b0;
ram_wren <= 1'b1;
mstate <= R_WRITE;
end
R_WRITE: begin
mcount <= mcount_in + 6'd1;
if (mcount_in==0)
begin
mixfeedback <= 1'b1;
if (writeaddr_in==1023)
doneROM <= 1'b1;
writeaddr <= writeaddr_in + 10'd1;
end
if (mcount_in==4 || mcount_in==8)
mixfeedback <= 1'b1;
if (mcount_in==3 || mcount_in==7)
begin
XCtl <= XSmix;
mixfeedback <= 1'b0;
end
if (mcount_in==6 && doneROM_in)
addrsourceMix <= 1'b1;
if (mcount_in==7)
begin
mcount <= 0;
if (doneROM_in)
begin
mstate <= R_MIX;
XCtl <= XSram;
mixspecial <= 1'b1;
if (ADDRBITS < 13)
begin
intcycles <= { {THREADS_BITS+12-ADDRBITSX{1'b0}}, Xaddr[12-ADDRBITSX:0] };
if ( Xaddr[9:13-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] )
intcycles <= { {THREADS_BITS+11-ADDRBITSX{1'b0}}, 1'b1, Xaddr[12-ADDRBITSX:0] };
if ( (Xaddr[9:13-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1]) || |Xaddr[12-ADDRBITSX:0] )
begin
addrsourceSave <= 1'b1;
ram_wren <= 1'b1;
xoren <= 0;
end
end
end
else
begin
if (ADDRBITS < 13)
ram_wren <= ~|writeaddr_in[12-ADDRBITSX:0];
else
ram_wren <= 1'b1;
end
end
end
R_MIX: begin
mcount <= mcount_in + 6'd1;
if (mcount_in==0)
begin
mixfeedback <= 1'b1;
if (intcycles_in != 0)
mstate <= R_INT;
end
if (mcount_in==4 || mcount_in==8)
mixfeedback <= 1'b1;
if (mcount_in==3 || mcount_in==7)
begin
XCtl <= XSmix;
mixfeedback <= 1'b0;
end
if (mcount_in==7)
begin
cycle <= cycle_in + 11'd1;
mcount <= 0;
if (cycle_in==1023)
begin
busy_flag <= 1'b0;
if (start)
begin
XCtl <= XSload;
result <= 1'b1;
mstate <= R_START;
end
else
begin
mstate <= R_IDLE;
end
end
else
begin
XCtl <= XSram;
if (ADDRBITS < 13)
begin
intcycles <= { {THREADS_BITS+12-ADDRBITSX{1'b0}}, Xaddr[12-ADDRBITSX:0] };
if ( Xaddr[9:13-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] )
intcycles <= { {THREADS_BITS+11-ADDRBITSX{1'b0}}, 1'b1, Xaddr[12-ADDRBITSX:0] };
if ( (Xaddr[9:13-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1]) || |Xaddr[12-ADDRBITSX:0] )
begin
addrsourceSave <= 1'b1;
ram_wren <= 1'b1;
xoren <= 0;
end
end
end
end
end
R_INT: begin
mcount <= mcount_in + 6'd1;
if (mcount_in==4 || mcount_in==8)
mixfeedback <= 1'b1;
if (mcount_in==3 || mcount_in==7)
begin
XCtl <= XSmix;
mixfeedback <= 1'b0;
end
if (mcount_in==6)
addrsourceSave <= 1'b1;
if (mcount_in==7)
begin
if (intcycles_in==1)
XCtl <= XSram;
end
if (mcount_in==8)
begin
intcycles <= intcycles_in - 1;
mcount <= 1;
if (intcycles_in==1)
mstate <= R_MIX;
end
end
endcase
end
`ifdef SIM
if (mstate==R_MIX && mcount==0)
$display ("phase %d cycle %d Xmix %08x\n", phase, cycle-1, Xmix[511:480]);
`endif
end
endmodule | module salsaengine (hash_clk, reset, din, dout, shift, start, busy, result ); |
input hash_clk;
input reset;
input din;
input shift;
input start;
output busy;
output reg result = 1'b0;
output dout;
parameter ADDRBITS = 12;
parameter THREADS = 8;
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
parameter THREADS_BITS = clog2(THREADS);
parameter ADDRBITSX = (ADDRBITS == 13) ? ADDRBITS-1 : ADDRBITS;
reg [THREADS_BITS:0]phase = 0;
reg [THREADS_BITS:0]phase_d = THREADS;
always @ (posedge hash_clk)
begin
phase <= (phase == THREADS) ? 0 : phase + 1;
phase_d <= phase;
end
parameter XSnull = 0, XSload = 1, XSmix = 2, XSram = 4;
reg [2:0] XCtl = XSnull;
parameter R_IDLE=0, R_START=1, R_WRITE=2, R_MIX=4, R_INT=8;
reg [3:0] mstate = R_IDLE;
reg [10:0] cycle = 11'd0;
reg [5:0] mcount = 5'd0;
reg doneROM = 1'd0;
reg mixfeedback = 1'b0;
reg mixfeedback_d = 1'b0;
reg addrsourceMix = 1'b0;
reg addrsourceMix_d = 1'b0;
reg addrsourceSave = 1'b0;
reg mixspecial = 1'b0;
reg xoren = 1'b1;
reg [THREADS_BITS+1:0] intcycles = 0;
wire [511:0] Xmix;
reg [511:0] X0;
reg [511:0] X1;
wire [511:0] X0in;
wire [511:0] X1in;
wire [511:0] X0out;
wire [511:0] X1out;
reg [1023:0] salsaShiftReg;
reg [31:0] nonce_sr;
assign dout = salsaShiftReg[1023];
reg [511:0] Xmix_d;
reg [511:0] X1out_d;
reg [THREADS_BITS+38:0] sstate [THREADS-1:0];
wire [3:0] mstate_in;
wire [10:0] cycle_in;
wire [5:0] mcount_in;
wire [9:0] writeaddr_in;
wire doneROM_in;
wire mixfeedback_in;
wire addrsourceMix_in;
wire addrsourceSave_in;
wire mixspecial_in;
wire [THREADS_BITS+1:0] intcycles_in;
reg [31:0] snonce [THREADS-1:0];
wire [1023:0] X;
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] tmp;
assign tmp = salsaShiftReg[`IDX(i)];
assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] };
end
endgenerate
reg [9:0] writeaddr = 10'd0;
(* S = "TRUE" *) reg [9:0] writeaddr_d1 = 10'd0;
(* S = "TRUE" *) reg [9:0] writeaddr_d2 = 10'd0;
(* S = "TRUE" *) reg [9:0] writeaddr_d3 = 10'd0;
(* S = "TRUE" *) reg [9:0] writeaddr_d4 = 10'd0;
wire [9:0] Xaddr;
wire [ADDRBITS-1:0]rd_addr;
(* S = "TRUE" *) wire [ADDRBITS-1:0]wr_addr1;
(* S = "TRUE" *) wire [ADDRBITS-1:0]wr_addr2;
(* S = "TRUE" *) wire [ADDRBITS-1:0]wr_addr3;
(* S = "TRUE" *) wire [ADDRBITS-1:0]wr_addr4;
wire [255:0]ram1_din;
wire [255:0]ram1_dout;
wire [255:0]ram2_din;
wire [255:0]ram2_dout;
wire [255:0]ram3_din;
wire [255:0]ram3_dout;
wire [255:0]ram4_din;
wire [255:0]ram4_dout;
wire [1023:0]ramout;
reg ram_wren = 1'b0;
reg ram_wren_d = 1'b0;
wire ram_clk;
assign ram_clk = hash_clk;
wire [15:0] memtop = 16'hfffe;
wire [ADDRBITS-THREADS_BITS-1:0] adj_addr;
if (ADDRBITS < 13)
assign adj_addr = (Xaddr[9:13-ADDRBITS] == memtop[9:13-ADDRBITS]) ?
memtop[ADDRBITS-THREADS_BITS-1:0] : Xaddr[9:13-ADDRBITS];
else
assign adj_addr = Xaddr;
wire [THREADS_BITS-1:0] phase_addr;
(* S = "TRUE" *) reg [THREADS_BITS-1:0] phase_addr_d1;
(* S = "TRUE" *) reg [THREADS_BITS-1:0] phase_addr_d2;
(* S = "TRUE" *) reg [THREADS_BITS-1:0] phase_addr_d3;
(* S = "TRUE" *) reg [THREADS_BITS-1:0] phase_addr_d4;
assign phase_addr = phase[THREADS_BITS-1:0];
assign rd_addr = { phase_addr+1, addrsourceSave_in ? memtop[ADDRBITS-THREADS_BITS:1] : adj_addr };
assign wr_addr1 = { phase_addr_d1, writeaddr_d1[9:13-ADDRBITS] };
assign wr_addr2 = { phase_addr_d2, writeaddr_d2[9:13-ADDRBITS] };
assign wr_addr3 = { phase_addr_d3, writeaddr_d3[9:13-ADDRBITS] };
assign wr_addr4 = { phase_addr_d4, writeaddr_d4[9:13-ADDRBITS] };
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_1 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_2 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_3 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_4 = 0;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr1 = rd_addr | rd_addr_z_1;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr2 = rd_addr | rd_addr_z_2;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr3 = rd_addr | rd_addr_z_3;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr4 = rd_addr | rd_addr_z_4;
ram # (.ADDRBITS(ADDRBITS)) ram1_blk (rd_addr1, wr_addr1, ram_clk, ram1_din, ram_wren_d, ram1_dout);
ram # (.ADDRBITS(ADDRBITS)) ram2_blk (rd_addr2, wr_addr2, ram_clk, ram2_din, ram_wren_d, ram2_dout);
ram # (.ADDRBITS(ADDRBITS)) ram3_blk (rd_addr3, wr_addr3, ram_clk, ram3_din, ram_wren_d, ram3_dout);
ram # (.ADDRBITS(ADDRBITS)) ram4_blk (rd_addr4, wr_addr4, ram_clk, ram4_din, ram_wren_d, ram4_dout);
assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout };
assign { ram4_din, ram3_din, ram2_din, ram1_din } = addrsourceMix_d ? { Xmix_d, X1out_d} : { X1, X0} ;
salsa salsa_blk (hash_clk, mixfeedback_d, X0, X1, Xmix, X0out, X1out, Xaddr);
wire [511:0] Zbits;
assign Zbits = {512{xoren}};
assign X0in = (XCtl==XSmix) ? X1out : (XCtl==XSram) ? ((mixspecial ? X1out : X0out) & Zbits) ^ ramout[511:0] : (XCtl==XSload) ? X[511:0] : X0out;
assign X1in = (XCtl==XSmix) ? Xmix : (XCtl==XSram) ? ((mixspecial ? Xmix : X1out) & Zbits) ^ ramout[1023:512] : (XCtl==XSload) ? X[1023:512] : X1out;
assign { mstate_in, mcount_in, writeaddr_in, cycle_in, doneROM_in, mixfeedback_in, addrsourceMix_in, addrsourceSave_in, mixspecial_in, intcycles_in} = (phase == THREADS) ? 0 : sstate[phase];
reg busy_flag = 1'b0;
`ifdef ONETHREAD
reg start_once = 1'b0;
wire start_flag;
assign start_flag = start & ~start_once;
assign busy = busy_flag;
`else
reg [15:0] start_count = 0;
parameter START_INTERVAL = ((ADDRBITS == 12) ? 184320 : (ADDRBITS == 11) ? 258048 : 405504) / THREADS;
reg start_flag = 1'b0;
assign busy = busy_flag;
`endif
always @ (posedge hash_clk)
begin
X0 <= X0in;
X1 <= X1in;
if (phase_d != THREADS)
sstate[phase_d] <= reset ? 0 : { mstate, mcount, writeaddr, cycle, doneROM, mixfeedback, addrsourceMix,
addrsourceSave, mixspecial, intcycles };
mstate <= mstate_in;
mcount <= mcount_in;
writeaddr <= writeaddr_in;
cycle <= cycle_in;
intcycles <= intcycles_in;
doneROM <= doneROM_in;
mixfeedback <= mixfeedback_in;
addrsourceMix <= addrsourceMix_in;
addrsourceSave <= addrsourceSave_in;
mixspecial <= mixspecial_in;
mixfeedback_d <= mixfeedback;
addrsourceMix_d <= addrsourceMix;
ram_wren_d <= ram_wren;
writeaddr_d1 <= addrsourceMix ? memtop[10:1] : writeaddr;
writeaddr_d2 <= addrsourceMix ? memtop[10:1] : writeaddr;
writeaddr_d3 <= addrsourceMix ? memtop[10:1] : writeaddr;
writeaddr_d4 <= addrsourceMix ? memtop[10:1] : writeaddr;
phase_addr_d1 <= phase;
phase_addr_d2 <= phase;
phase_addr_d3 <= phase;
phase_addr_d4 <= phase;
rd_addr_z_1 <= {ADDRBITS{reset}};
rd_addr_z_2 <= {ADDRBITS{reset}};
rd_addr_z_3 <= {ADDRBITS{reset}};
rd_addr_z_4 <= {ADDRBITS{reset}};
Xmix_d <= Xmix;
X1out_d <= X1out;
XCtl <= XSnull;
addrsourceSave <= 0;
ram_wren <= 0;
xoren <= 1;
`ifdef ONETHREAD
if (start)
start_once <= 1'b1;
if (reset)
start_once <= 1'b0;
`else
start_count <= start_count + 1;
if (reset || start_count == START_INTERVAL)
begin
start_count <= 0;
if (~reset && start)
start_flag <= 1'b1;
end
`endif
if (shift)
begin
salsaShiftReg <= { salsaShiftReg[1022:0], nonce_sr[31] };
nonce_sr <= { nonce_sr[30:0], din };
end
else
if (XCtl==XSload && phase_d != THREADS)
begin
salsaShiftReg <= { Xmix, X1out };
nonce_sr <= snonce[phase_d];
snonce[phase_d] <= nonce_sr;
end
if (reset == 1'b1)
begin
mstate <= R_IDLE;
busy_flag <= 1'b0;
result <= 1'b0;
end
else
begin
case (mstate_in)
R_IDLE: begin
if ((phase!=THREADS) && start_flag)
begin
XCtl <= XSload;
`ifndef ONETHREAD
start_flag <= 1'b0;
`endif
busy_flag <= 1'b0;
mstate <= R_START;
end
end
R_START: begin
writeaddr <= 0;
mcount <= 0;
cycle <= 0;
mixfeedback <= 1'b0;
addrsourceMix <= 1'b0;
mixspecial <= 1'b0;
doneROM <= 1'b0;
busy_flag <= 1'b1;
result <= 1'b0;
ram_wren <= 1'b1;
mstate <= R_WRITE;
end
R_WRITE: begin
mcount <= mcount_in + 6'd1;
if (mcount_in==0)
begin
mixfeedback <= 1'b1;
if (writeaddr_in==1023)
doneROM <= 1'b1;
writeaddr <= writeaddr_in + 10'd1;
end
if (mcount_in==4 || mcount_in==8)
mixfeedback <= 1'b1;
if (mcount_in==3 || mcount_in==7)
begin
XCtl <= XSmix;
mixfeedback <= 1'b0;
end
if (mcount_in==6 && doneROM_in)
addrsourceMix <= 1'b1;
if (mcount_in==7)
begin
mcount <= 0;
if (doneROM_in)
begin
mstate <= R_MIX;
XCtl <= XSram;
mixspecial <= 1'b1;
if (ADDRBITS < 13)
begin
intcycles <= { {THREADS_BITS+12-ADDRBITSX{1'b0}}, Xaddr[12-ADDRBITSX:0] };
if ( Xaddr[9:13-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] )
intcycles <= { {THREADS_BITS+11-ADDRBITSX{1'b0}}, 1'b1, Xaddr[12-ADDRBITSX:0] };
if ( (Xaddr[9:13-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1]) || |Xaddr[12-ADDRBITSX:0] )
begin
addrsourceSave <= 1'b1;
ram_wren <= 1'b1;
xoren <= 0;
end
end
end
else
begin
if (ADDRBITS < 13)
ram_wren <= ~|writeaddr_in[12-ADDRBITSX:0];
else
ram_wren <= 1'b1;
end
end
end
R_MIX: begin
mcount <= mcount_in + 6'd1;
if (mcount_in==0)
begin
mixfeedback <= 1'b1;
if (intcycles_in != 0)
mstate <= R_INT;
end
if (mcount_in==4 || mcount_in==8)
mixfeedback <= 1'b1;
if (mcount_in==3 || mcount_in==7)
begin
XCtl <= XSmix;
mixfeedback <= 1'b0;
end
if (mcount_in==7)
begin
cycle <= cycle_in + 11'd1;
mcount <= 0;
if (cycle_in==1023)
begin
busy_flag <= 1'b0;
if (start)
begin
XCtl <= XSload;
result <= 1'b1;
mstate <= R_START;
end
else
begin
mstate <= R_IDLE;
end
end
else
begin
XCtl <= XSram;
if (ADDRBITS < 13)
begin
intcycles <= { {THREADS_BITS+12-ADDRBITSX{1'b0}}, Xaddr[12-ADDRBITSX:0] };
if ( Xaddr[9:13-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] )
intcycles <= { {THREADS_BITS+11-ADDRBITSX{1'b0}}, 1'b1, Xaddr[12-ADDRBITSX:0] };
if ( (Xaddr[9:13-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1]) || |Xaddr[12-ADDRBITSX:0] )
begin
addrsourceSave <= 1'b1;
ram_wren <= 1'b1;
xoren <= 0;
end
end
end
end
end
R_INT: begin
mcount <= mcount_in + 6'd1;
if (mcount_in==4 || mcount_in==8)
mixfeedback <= 1'b1;
if (mcount_in==3 || mcount_in==7)
begin
XCtl <= XSmix;
mixfeedback <= 1'b0;
end
if (mcount_in==6)
addrsourceSave <= 1'b1;
if (mcount_in==7)
begin
if (intcycles_in==1)
XCtl <= XSram;
end
if (mcount_in==8)
begin
intcycles <= intcycles_in - 1;
mcount <= 1;
if (intcycles_in==1)
mstate <= R_MIX;
end
end
endcase
end
`ifdef SIM
if (mstate==R_MIX && mcount==0)
$display ("phase %d cycle %d Xmix %08x\n", phase, cycle-1, Xmix[511:480]);
`endif
end
endmodule | 270 |
6,305 | data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v | 11,584,509 | salsaengine.v | v | 544 | 193 | [] | [] | [] | null | line:54: before: "integer" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:84: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance salsaengine\n reg [5:0] mcount = 5\'d0; \n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:197: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance salsaengine\n assign rd_addr = { phase_addr+1, addrsourceSave_in ? memtop[ADDRBITS-THREADS_BITS:1] : adj_addr }; \n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:197: Unsized numbers/parameters not allowed in replications.\n : ... In instance salsaengine\n assign rd_addr = { phase_addr+1, addrsourceSave_in ? memtop[ADDRBITS-THREADS_BITS:1] : adj_addr }; \n ^\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:215: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram1_blk (rd_addr1, wr_addr1, ram_clk, ram1_din, ram_wren_d, ram1_dout);\n ^~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A,data/full_repos/permissive/11584509/ram\n data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A,data/full_repos/permissive/11584509/ram.v\n data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A,data/full_repos/permissive/11584509/ram.sv\n ram\n ram.v\n ram.sv\n obj_dir/ram\n obj_dir/ram.v\n obj_dir/ram.sv\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:216: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram2_blk (rd_addr2, wr_addr2, ram_clk, ram2_din, ram_wren_d, ram2_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:217: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram3_blk (rd_addr3, wr_addr3, ram_clk, ram3_din, ram_wren_d, ram3_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:218: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram4_blk (rd_addr4, wr_addr4, ram_clk, ram4_din, ram_wren_d, ram4_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:224: Cannot find file containing module: \'salsa\'\n salsa salsa_blk (hash_clk, mixfeedback_d, X0, X1, Xmix, X0out, X1out, Xaddr);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:240: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n : ... In instance salsaengine\n assign { mstate_in, mcount_in, writeaddr_in, cycle_in, doneROM_in, mixfeedback_in, addrsourceMix_in, addrsourceSave_in, mixspecial_in, intcycles_in} = (phase == THREADS) ? 0 : sstate[phase];\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:240: Operator ASSIGNW expects 41 bits on the Assign RHS, but Assign RHS\'s COND generates 42 bits.\n : ... In instance salsaengine\n assign { mstate_in, mcount_in, writeaddr_in, cycle_in, doneROM_in, mixfeedback_in, addrsourceMix_in, addrsourceSave_in, mixspecial_in, intcycles_in} = (phase == THREADS) ? 0 : sstate[phase];\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:274: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n : ... In instance salsaengine\n sstate[phase_d] <= reset ? 0 : { mstate, mcount, writeaddr, cycle, doneROM, mixfeedback, addrsourceMix,\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:274: Operator COND expects 42 bits on the Conditional False, but Conditional False\'s REPLICATE generates 41 bits.\n : ... In instance salsaengine\n sstate[phase_d] <= reset ? 0 : { mstate, mcount, writeaddr, cycle, doneROM, mixfeedback, addrsourceMix,\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:297: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'phase\' generates 4 bits.\n : ... In instance salsaengine\n phase_addr_d1 <= phase;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:298: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'phase\' generates 4 bits.\n : ... In instance salsaengine\n phase_addr_d2 <= phase;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:299: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'phase\' generates 4 bits.\n : ... In instance salsaengine\n phase_addr_d3 <= phase;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:300: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'phase\' generates 4 bits.\n : ... In instance salsaengine\n phase_addr_d4 <= phase;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:325: Operator EQ expects 32 or 19 bits on the LHS, but LHS\'s VARREF \'start_count\' generates 16 bits.\n : ... In instance salsaengine\n if (reset || start_count == START_INTERVAL)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:343: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n : ... In instance salsaengine\n nonce_sr <= snonce[phase_d]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:344: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n : ... In instance salsaengine\n snonce[phase_d] <= nonce_sr;\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:419: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance salsaengine\n intcycles <= { {THREADS_BITS+12-ADDRBITSX{1\'b0}}, Xaddr[12-ADDRBITSX:0] }; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:422: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance salsaengine\n intcycles <= { {THREADS_BITS+11-ADDRBITSX{1\'b0}}, 1\'b1, Xaddr[12-ADDRBITSX:0] };\n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:489: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance salsaengine\n intcycles <= { {THREADS_BITS+12-ADDRBITSX{1\'b0}}, Xaddr[12-ADDRBITSX:0] }; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:492: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance salsaengine\n intcycles <= { {THREADS_BITS+11-ADDRBITSX{1\'b0}}, 1\'b1, Xaddr[12-ADDRBITSX:0] };\n ^~\n%Error: Exiting due to 5 error(s), 18 warning(s)\n' | 7,161 | function | function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction | function integer clog2; |
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction | 270 |
6,308 | data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C/salsa_piped.v | 11,584,509 | salsa_piped.v | v | 320 | 121 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C/salsa_piped.v:169: Cannot find include file: sgen.inc\n`include "sgen.inc" // .inc so it does not accidentally get compiled separately as .v \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C,data/full_repos/permissive/11584509/sgen.inc\n data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C,data/full_repos/permissive/11584509/sgen.inc.v\n data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C,data/full_repos/permissive/11584509/sgen.inc.sv\n sgen.inc\n sgen.inc.v\n sgen.inc.sv\n obj_dir/sgen.inc\n obj_dir/sgen.inc.v\n obj_dir/sgen.inc.sv\n%Error: Exiting due to 1 error(s)\n' | 7,177 | module | module salsa (clk, feedback, B, Bx, Bo, X0out, X1out, Xaddr);
input clk;
input feedback;
input [511:0]B;
input [511:0]Bx;
output [511:0]Bo;
output [511:0]X0out;
output [511:0]X1out;
output [9:0]Xaddr;
wire [511:0]xx;
wire [511:0]xxd9;
wire [511:0]xr;
reg [511:0]xrd;
reg [511:0]xrd2;
wire [9:0]addr;
reg [9:0]xxd7_addr;
reg [511:0]x0d1;
reg [511:0]x0d2;
reg [511:0]x0d3;
reg [511:0]x0d4;
reg [511:0]x0d5;
reg [511:0]x0d6;
reg [511:0]x0d7;
reg [511:0]x0d8;
reg [511:0]x0d9;
reg [511:0]x1d1;
reg [511:0]x1d2;
reg [511:0]x1d3;
reg [511:0]x1d4;
reg [511:0]x1d5;
reg [511:0]x1d6;
reg [511:0]x1d7;
reg [511:0]x1d8;
reg [511:0]x1d9;
assign X0out = x0d9;
assign X1out = x1d9;
salsa_core salsa1 (clk, feedback ? xrd2 : xx, xr, addr);
always @ (posedge clk)
begin
xrd <= xr;
xrd2 <= xrd;
x0d1 <= B;
x0d2 <= x0d1;
x0d3 <= x0d2;
x0d4 <= x0d3;
x0d5 <= x0d4;
x0d6 <= x0d5;
x0d7 <= x0d6;
x0d8 <= x0d7;
x0d9 <= x0d8;
x1d1 <= Bx;
x1d2 <= x1d1;
x1d3 <= x1d2;
x1d4 <= x1d3;
x1d5 <= x1d4;
x1d6 <= x1d5;
x1d7 <= x1d6;
x1d8 <= x1d7;
x1d9 <= x1d8;
xxd7_addr <= x0d6[9:0] ^ x1d6[9:0];
end
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : XX
assign xx[`IDX(i)] = B[`IDX(i)] ^ Bx[`IDX(i)];
assign xxd9[`IDX(i)] = x0d9[`IDX(i)] ^ x1d9[`IDX(i)];
assign Bo[`IDX(i)] = xxd9[`IDX(i)] + xrd[`IDX(i)];
end
endgenerate
assign Xaddr = xxd7_addr + addr;
endmodule | module salsa (clk, feedback, B, Bx, Bo, X0out, X1out, Xaddr); |
input clk;
input feedback;
input [511:0]B;
input [511:0]Bx;
output [511:0]Bo;
output [511:0]X0out;
output [511:0]X1out;
output [9:0]Xaddr;
wire [511:0]xx;
wire [511:0]xxd9;
wire [511:0]xr;
reg [511:0]xrd;
reg [511:0]xrd2;
wire [9:0]addr;
reg [9:0]xxd7_addr;
reg [511:0]x0d1;
reg [511:0]x0d2;
reg [511:0]x0d3;
reg [511:0]x0d4;
reg [511:0]x0d5;
reg [511:0]x0d6;
reg [511:0]x0d7;
reg [511:0]x0d8;
reg [511:0]x0d9;
reg [511:0]x1d1;
reg [511:0]x1d2;
reg [511:0]x1d3;
reg [511:0]x1d4;
reg [511:0]x1d5;
reg [511:0]x1d6;
reg [511:0]x1d7;
reg [511:0]x1d8;
reg [511:0]x1d9;
assign X0out = x0d9;
assign X1out = x1d9;
salsa_core salsa1 (clk, feedback ? xrd2 : xx, xr, addr);
always @ (posedge clk)
begin
xrd <= xr;
xrd2 <= xrd;
x0d1 <= B;
x0d2 <= x0d1;
x0d3 <= x0d2;
x0d4 <= x0d3;
x0d5 <= x0d4;
x0d6 <= x0d5;
x0d7 <= x0d6;
x0d8 <= x0d7;
x0d9 <= x0d8;
x1d1 <= Bx;
x1d2 <= x1d1;
x1d3 <= x1d2;
x1d4 <= x1d3;
x1d5 <= x1d4;
x1d6 <= x1d5;
x1d7 <= x1d6;
x1d8 <= x1d7;
x1d9 <= x1d8;
xxd7_addr <= x0d6[9:0] ^ x1d6[9:0];
end
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : XX
assign xx[`IDX(i)] = B[`IDX(i)] ^ Bx[`IDX(i)];
assign xxd9[`IDX(i)] = x0d9[`IDX(i)] ^ x1d9[`IDX(i)];
assign Bo[`IDX(i)] = xxd9[`IDX(i)] + xrd[`IDX(i)];
end
endgenerate
assign Xaddr = xxd7_addr + addr;
endmodule | 270 |
6,309 | data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C/salsa_piped.v | 11,584,509 | salsa_piped.v | v | 320 | 121 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C/salsa_piped.v:169: Cannot find include file: sgen.inc\n`include "sgen.inc" // .inc so it does not accidentally get compiled separately as .v \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C,data/full_repos/permissive/11584509/sgen.inc\n data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C,data/full_repos/permissive/11584509/sgen.inc.v\n data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C,data/full_repos/permissive/11584509/sgen.inc.sv\n sgen.inc\n sgen.inc.v\n sgen.inc.sv\n obj_dir/sgen.inc\n obj_dir/sgen.inc.v\n obj_dir/sgen.inc.sv\n%Error: Exiting due to 1 error(s)\n' | 7,177 | module | module salsa_core (clk, x, out, addr);
input clk;
input [511:0]x;
output [511:0]out;
output [9:0]addr;
wire [31:0] x00;
wire [31:0] x01;
wire [31:0] x02;
wire [31:0] x03;
wire [31:0] x04;
wire [31:0] x05;
wire [31:0] x06;
wire [31:0] x07;
wire [31:0] x08;
wire [31:0] x09;
wire [31:0] x10;
wire [31:0] x11;
wire [31:0] x12;
wire [31:0] x13;
wire [31:0] x14;
wire [31:0] x15;
assign x00 = x[`IDX(0)];
assign x01 = x[`IDX(1)];
assign x02 = x[`IDX(2)];
assign x03 = x[`IDX(3)];
assign x04 = x[`IDX(4)];
assign x05 = x[`IDX(5)];
assign x06 = x[`IDX(6)];
assign x07 = x[`IDX(7)];
assign x08 = x[`IDX(8)];
assign x09 = x[`IDX(9)];
assign x10 = x[`IDX(10)];
assign x11 = x[`IDX(11)];
assign x12 = x[`IDX(12)];
assign x13 = x[`IDX(13)];
assign x14 = x[`IDX(14)];
assign x15 = x[`IDX(15)];
`include "sgen.inc"
wire [31:0]c00s;
wire [31:0]c01s;
wire [31:0]c02s;
wire [31:0]c03s;
wire [31:0]c04s;
wire [31:0]c05s;
wire [31:0]c06s;
wire [31:0]c07s;
wire [31:0]c08s;
wire [31:0]c09s;
wire [31:0]c10s;
wire [31:0]c11s;
wire [31:0]c12s;
wire [31:0]c13s;
wire [31:0]c14s;
wire [31:0]c15s;
wire [31:0]r00s;
wire [31:0]r01s;
wire [31:0]r02s;
wire [31:0]r03s;
wire [31:0]r04s;
wire [31:0]r05s;
wire [31:0]r06s;
wire [31:0]r07s;
wire [31:0]r08s;
wire [31:0]r09s;
wire [31:0]r10s;
wire [31:0]r11s;
wire [31:0]r12s;
wire [31:0]r13s;
wire [31:0]r14s;
wire [31:0]r15s;
wire [31:0]r00sx;
assign c04s = x00 + x12;
assign c09s = x05 + x01;
assign c14s = x10 + x06;
assign c03s = x15 + x11;
assign c08s = c04 + x00d1;
assign c13s = c09 + x05d1;
assign c02s = c14 + x10d1;
assign c07s = c03 + x15d1;
assign c12s = c08 + c04d1;
assign c01s = c13 + c09d1;
assign c06s = c02 + c14d1;
assign c11s = c07 + c03d1;
assign c00s = c12 + c08d1;
assign c05s = c01 + c13d1;
assign c10s = c06 + c02d1;
assign c15s = c11 + c07d1;
assign r01s = c00 + c03d3;
assign r06s = c05 + c04d3;
assign r11s = c10 + c09d3;
assign r12s = c15 + c14d3;
assign r02s = r01 + c00d1;
assign r07s = r06 + c05d1;
assign r08s = r11 + c10d1;
assign r13s = r12 + c15d1;
assign r03s = r02 + r01d1;
assign r04s = r07 + r06d1;
assign r09s = r08 + r11d1;
assign r14s = r13 + r12d1;
assign r00s = r03 + r02d1;
assign r05s = r04 + r07d1;
assign r10s = r09 + r08d1;
assign r15s = r14 + r13d1;
assign r00sx = c00d3 ^ { r00s[13:0], r00s[31:14] };
assign addr = r00sx[9:0];
assign out = { r15, r14d1, r13d2, r12d3, r11d3, r10, r09d1, r08d2, r07d2, r06d3, r05, r04d1, r03d1, r02d2, r01d3, r00 };
always @ (posedge clk)
begin
c04 <= x04 ^ { c04s[24:0], c04s[31:25] };
c09 <= x09 ^ { c09s[24:0], c09s[31:25] };
c14 <= x14 ^ { c14s[24:0], c14s[31:25] };
c03 <= x03 ^ { c03s[24:0], c03s[31:25] };
c08 <= x08d1 ^ { c08s[22:0], c08s[31:23] };
c13 <= x13d1 ^ { c13s[22:0], c13s[31:23] };
c02 <= x02d1 ^ { c02s[22:0], c02s[31:23] };
c07 <= x07d1 ^ { c07s[22:0], c07s[31:23] };
c12 <= x12d2 ^ { c12s[18:0], c12s[31:19] };
c01 <= x01d2 ^ { c01s[18:0], c01s[31:19] };
c06 <= x06d2 ^ { c06s[18:0], c06s[31:19] };
c11 <= x11d2 ^ { c11s[18:0], c11s[31:19] };
c00 <= x00d3 ^ { c00s[13:0], c00s[31:14] };
c05 <= x05d3 ^ { c05s[13:0], c05s[31:14] };
c10 <= x10d3 ^ { c10s[13:0], c10s[31:14] };
c15 <= x15d3 ^ { c15s[13:0], c15s[31:14] };
r01 <= c01d1 ^ { r01s[24:0], r01s[31:25] };
r06 <= c06d1 ^ { r06s[24:0], r06s[31:25] };
r11 <= c11d1 ^ { r11s[24:0], r11s[31:25] };
r12 <= c12d1 ^ { r12s[24:0], r12s[31:25] };
r02 <= c02d3 ^ { r02s[22:0], r02s[31:23] };
r07 <= c07d3 ^ { r07s[22:0], r07s[31:23] };
r08 <= c08d3 ^ { r08s[22:0], r08s[31:23] };
r13 <= c13d3 ^ { r13s[22:0], r13s[31:23] };
r03 <= c03d5 ^ { r03s[18:0], r03s[31:19] };
r04 <= c04d5 ^ { r04s[18:0], r04s[31:19] };
r09 <= c09d5 ^ { r09s[18:0], r09s[31:19] };
r14 <= c14d5 ^ { r14s[18:0], r14s[31:19] };
r00 <= r00sx;
r05 <= c05d3 ^ { r05s[13:0], r05s[31:14] };
r10 <= c10d3 ^ { r10s[13:0], r10s[31:14] };
r15 <= c15d3 ^ { r15s[13:0], r15s[31:14] };
end
endmodule | module salsa_core (clk, x, out, addr); |
input clk;
input [511:0]x;
output [511:0]out;
output [9:0]addr;
wire [31:0] x00;
wire [31:0] x01;
wire [31:0] x02;
wire [31:0] x03;
wire [31:0] x04;
wire [31:0] x05;
wire [31:0] x06;
wire [31:0] x07;
wire [31:0] x08;
wire [31:0] x09;
wire [31:0] x10;
wire [31:0] x11;
wire [31:0] x12;
wire [31:0] x13;
wire [31:0] x14;
wire [31:0] x15;
assign x00 = x[`IDX(0)];
assign x01 = x[`IDX(1)];
assign x02 = x[`IDX(2)];
assign x03 = x[`IDX(3)];
assign x04 = x[`IDX(4)];
assign x05 = x[`IDX(5)];
assign x06 = x[`IDX(6)];
assign x07 = x[`IDX(7)];
assign x08 = x[`IDX(8)];
assign x09 = x[`IDX(9)];
assign x10 = x[`IDX(10)];
assign x11 = x[`IDX(11)];
assign x12 = x[`IDX(12)];
assign x13 = x[`IDX(13)];
assign x14 = x[`IDX(14)];
assign x15 = x[`IDX(15)];
`include "sgen.inc"
wire [31:0]c00s;
wire [31:0]c01s;
wire [31:0]c02s;
wire [31:0]c03s;
wire [31:0]c04s;
wire [31:0]c05s;
wire [31:0]c06s;
wire [31:0]c07s;
wire [31:0]c08s;
wire [31:0]c09s;
wire [31:0]c10s;
wire [31:0]c11s;
wire [31:0]c12s;
wire [31:0]c13s;
wire [31:0]c14s;
wire [31:0]c15s;
wire [31:0]r00s;
wire [31:0]r01s;
wire [31:0]r02s;
wire [31:0]r03s;
wire [31:0]r04s;
wire [31:0]r05s;
wire [31:0]r06s;
wire [31:0]r07s;
wire [31:0]r08s;
wire [31:0]r09s;
wire [31:0]r10s;
wire [31:0]r11s;
wire [31:0]r12s;
wire [31:0]r13s;
wire [31:0]r14s;
wire [31:0]r15s;
wire [31:0]r00sx;
assign c04s = x00 + x12;
assign c09s = x05 + x01;
assign c14s = x10 + x06;
assign c03s = x15 + x11;
assign c08s = c04 + x00d1;
assign c13s = c09 + x05d1;
assign c02s = c14 + x10d1;
assign c07s = c03 + x15d1;
assign c12s = c08 + c04d1;
assign c01s = c13 + c09d1;
assign c06s = c02 + c14d1;
assign c11s = c07 + c03d1;
assign c00s = c12 + c08d1;
assign c05s = c01 + c13d1;
assign c10s = c06 + c02d1;
assign c15s = c11 + c07d1;
assign r01s = c00 + c03d3;
assign r06s = c05 + c04d3;
assign r11s = c10 + c09d3;
assign r12s = c15 + c14d3;
assign r02s = r01 + c00d1;
assign r07s = r06 + c05d1;
assign r08s = r11 + c10d1;
assign r13s = r12 + c15d1;
assign r03s = r02 + r01d1;
assign r04s = r07 + r06d1;
assign r09s = r08 + r11d1;
assign r14s = r13 + r12d1;
assign r00s = r03 + r02d1;
assign r05s = r04 + r07d1;
assign r10s = r09 + r08d1;
assign r15s = r14 + r13d1;
assign r00sx = c00d3 ^ { r00s[13:0], r00s[31:14] };
assign addr = r00sx[9:0];
assign out = { r15, r14d1, r13d2, r12d3, r11d3, r10, r09d1, r08d2, r07d2, r06d3, r05, r04d1, r03d1, r02d2, r01d3, r00 };
always @ (posedge clk)
begin
c04 <= x04 ^ { c04s[24:0], c04s[31:25] };
c09 <= x09 ^ { c09s[24:0], c09s[31:25] };
c14 <= x14 ^ { c14s[24:0], c14s[31:25] };
c03 <= x03 ^ { c03s[24:0], c03s[31:25] };
c08 <= x08d1 ^ { c08s[22:0], c08s[31:23] };
c13 <= x13d1 ^ { c13s[22:0], c13s[31:23] };
c02 <= x02d1 ^ { c02s[22:0], c02s[31:23] };
c07 <= x07d1 ^ { c07s[22:0], c07s[31:23] };
c12 <= x12d2 ^ { c12s[18:0], c12s[31:19] };
c01 <= x01d2 ^ { c01s[18:0], c01s[31:19] };
c06 <= x06d2 ^ { c06s[18:0], c06s[31:19] };
c11 <= x11d2 ^ { c11s[18:0], c11s[31:19] };
c00 <= x00d3 ^ { c00s[13:0], c00s[31:14] };
c05 <= x05d3 ^ { c05s[13:0], c05s[31:14] };
c10 <= x10d3 ^ { c10s[13:0], c10s[31:14] };
c15 <= x15d3 ^ { c15s[13:0], c15s[31:14] };
r01 <= c01d1 ^ { r01s[24:0], r01s[31:25] };
r06 <= c06d1 ^ { r06s[24:0], r06s[31:25] };
r11 <= c11d1 ^ { r11s[24:0], r11s[31:25] };
r12 <= c12d1 ^ { r12s[24:0], r12s[31:25] };
r02 <= c02d3 ^ { r02s[22:0], r02s[31:23] };
r07 <= c07d3 ^ { r07s[22:0], r07s[31:23] };
r08 <= c08d3 ^ { r08s[22:0], r08s[31:23] };
r13 <= c13d3 ^ { r13s[22:0], r13s[31:23] };
r03 <= c03d5 ^ { r03s[18:0], r03s[31:19] };
r04 <= c04d5 ^ { r04s[18:0], r04s[31:19] };
r09 <= c09d5 ^ { r09s[18:0], r09s[31:19] };
r14 <= c14d5 ^ { r14s[18:0], r14s[31:19] };
r00 <= r00sx;
r05 <= c05d3 ^ { r05s[13:0], r05s[31:14] };
r10 <= c10d3 ^ { r10s[13:0], r10s[31:14] };
r15 <= c15d3 ^ { r15s[13:0], r15s[31:14] };
end
endmodule | 270 |
6,310 | data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v | 11,584,509 | salsaengine.v | v | 508 | 132 | [] | [] | [] | null | line:60: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:217: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram1_blk (rd_addr1, wr_addr1, ram_clk, ram1_din, ram_wren, ram1_dout);\n ^~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A,data/full_repos/permissive/11584509/ram\n data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A,data/full_repos/permissive/11584509/ram.v\n data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A,data/full_repos/permissive/11584509/ram.sv\n ram\n ram.v\n ram.sv\n obj_dir/ram\n obj_dir/ram.v\n obj_dir/ram.sv\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:218: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram2_blk (rd_addr2, wr_addr2, ram_clk, ram2_din, ram_wren, ram2_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:219: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram3_blk (rd_addr3, wr_addr3, ram_clk, ram3_din, ram_wren, ram3_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:220: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram4_blk (rd_addr4, wr_addr4, ram_clk, ram4_din, ram_wren, ram4_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:228: Cannot find file containing module: \'salsa\'\n salsa salsa_blk (hash_clk, X0, X1, Xmix, X0out, Xaddr);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:245: Bit extraction of array[63:0] requires 6 bit index, not 7 bits.\n : ... In instance salsaengine\n (phase == THREADS ) ? 0 : sstate[phase]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:283: Bit extraction of array[63:0] requires 6 bit index, not 7 bits.\n : ... In instance salsaengine\n sstate[phase_d] <= fsmreset ? 0 : { mstate, writeaddr, cycle, doneROM, addrwriteMix, addrreadInit, addrreadSave, intcycles };\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:335: Bit extraction of array[63:0] requires 6 bit index, not 7 bits.\n : ... In instance salsaengine\n nonce_sr <= snonce[phase_d]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:336: Bit extraction of array[63:0] requires 6 bit index, not 7 bits.\n : ... In instance salsaengine\n snonce[phase_d] <= nonce_sr;\n ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n' | 7,184 | module | module salsaengine (hash_clk, reset, din, dout, shift, start, busy, result );
input hash_clk;
input reset;
input shift;
input start;
output busy;
output reg result = 1'b0;
parameter SBITS = 8;
input [SBITS-1:0] din;
output [SBITS-1:0] dout;
parameter ADDRBITS = 12;
parameter THREADS = 64;
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
parameter THREADS_BITS = clog2(THREADS);
reg [THREADS_BITS:0]phase = 0;
reg [THREADS_BITS:0]phase_d = THREADS;
reg reset_d=0, fsmreset=0, start_d=0, fsmstart=0;
always @ (posedge hash_clk)
begin
phase <= (phase == THREADS) ? 0 : phase + 1;
phase_d <= phase;
reset_d <= reset;
fsmreset <= reset_d;
start_d <= start;
fsmstart <= start_d;
end
parameter XSmix = 0, XSload = 1, XSram = 2;
reg [1:0] XCtl = XSmix;
parameter R_IDLE=0, R_START=1, R_LOAD=2, R_WRITE=3, R_MIX=4, R_INT=5, R_WAIT=6;
reg [2:0] mstate = R_IDLE;
reg [10:0] cycle = 11'd0;
reg doneROM = 1'd0;
reg addrwriteMix = 1'b0;
reg addrreadInit = 1'b0;
reg addrreadSave = 1'b0;
reg xoren = 1'b0;
parameter INT_BITS = THREADS_BITS - ADDRBITS + 10;
parameter INT_BITX = (INT_BITS > 0) ? INT_BITS : INT_BITS+1;
reg [INT_BITS:0] intcycles = 0;
wire [511:0] Xmix;
reg [511:0] X0;
reg [511:0] X1;
wire [511:0] X0in;
wire [511:0] X1in;
wire [511:0] X0out;
reg [1023:0] salsaShiftReg;
reg [31:0] nonce_sr;
assign dout = salsaShiftReg[1023:1024-SBITS];
reg [INT_BITS+28:0] sstate [THREADS-1:0];
wire [2:0] mstate_in;
wire [10:0] cycle_in;
wire [9:0] writeaddr_in;
wire doneROM_in;
wire addrwriteMix_in;
wire addrreadInit_in;
wire addrreadSave_in;
wire [INT_BITS:0] intcycles_in;
wire [9:0] writeaddr_next = writeaddr_in + 10'd1;
reg [31:0] snonce [THREADS-1:0];
wire [1023:0] X;
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] tmp;
assign tmp = salsaShiftReg[`IDX(i)];
assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] };
end
endgenerate
(* S = "TRUE" *) reg [9:0] writeaddr = 10'd0;
wire [9:0] Xaddr;
wire [ADDRBITS-1:0]rd_addr;
wire [ADDRBITS-1:0]wr_addr1;
wire [ADDRBITS-1:0]wr_addr2;
wire [ADDRBITS-1:0]wr_addr3;
wire [ADDRBITS-1:0]wr_addr4;
wire [255:0]ram1_din;
wire [255:0]ram1_dout;
wire [255:0]ram2_din;
wire [255:0]ram2_dout;
wire [255:0]ram3_din;
wire [255:0]ram3_dout;
wire [255:0]ram4_din;
wire [255:0]ram4_dout;
wire [1023:0]ramout;
(* S = "TRUE" *) reg ram_wren = 1'b0;
wire ram_clk;
assign ram_clk = hash_clk;
wire [15:0] memtop = 16'hfffe;
wire [9-INT_BITS:0] adj_addr;
if (INT_BITS > 0)
assign adj_addr = (Xaddr[9:INT_BITS] == memtop[9:INT_BITS]) ?
memtop[9-INT_BITS:0] : Xaddr[9:INT_BITS];
else
assign adj_addr = Xaddr;
wire [THREADS_BITS-1:0] phase_addr;
assign phase_addr = phase[THREADS_BITS-1:0];
reg [THREADS_BITS-1:0] phase_addr_d = 0;
assign rd_addr = { phase_addr,
(addrreadSave_in | addrreadInit_in) ?
(addrreadInit_in ? {ADDRBITS-THREADS_BITS{1'b0}} : memtop[ADDRBITS-THREADS_BITS:1])
:
adj_addr };
wire [9:0] writeaddr_adj = addrwriteMix ? memtop[10:1] : writeaddr;
assign wr_addr1 = { phase_addr_d, writeaddr_adj[9:INT_BITS] };
assign wr_addr2 = { phase_addr_d, writeaddr_adj[9:INT_BITS] };
assign wr_addr3 = { phase_addr_d, writeaddr_adj[9:INT_BITS] };
assign wr_addr4 = { phase_addr_d, writeaddr_adj[9:INT_BITS] };
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_1 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_2 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_3 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_4 = 0;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr1 = rd_addr | rd_addr_z_1;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr2 = rd_addr | rd_addr_z_2;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr3 = rd_addr | rd_addr_z_3;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr4 = rd_addr | rd_addr_z_4;
ram # (.ADDRBITS(ADDRBITS)) ram1_blk (rd_addr1, wr_addr1, ram_clk, ram1_din, ram_wren, ram1_dout);
ram # (.ADDRBITS(ADDRBITS)) ram2_blk (rd_addr2, wr_addr2, ram_clk, ram2_din, ram_wren, ram2_dout);
ram # (.ADDRBITS(ADDRBITS)) ram3_blk (rd_addr3, wr_addr3, ram_clk, ram3_din, ram_wren, ram3_dout);
ram # (.ADDRBITS(ADDRBITS)) ram4_blk (rd_addr4, wr_addr4, ram_clk, ram4_din, ram_wren, ram4_dout);
assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout };
assign { ram4_din, ram3_din, ram2_din, ram1_din } = XCtl[0] ? X : { Xmix, X0out};
salsa salsa_blk (hash_clk, X0, X1, Xmix, X0out, Xaddr);
wire [511:0] Zbits;
assign Zbits = {512{xoren}};
assign X0in = XCtl[1] ? (X0out & Zbits) ^ ramout[511:0] : X0out;
assign X1in = XCtl[1] ? (Xmix & Zbits) ^ ramout[1023:512] : Xmix;
assign { mstate_in, writeaddr_in, cycle_in, doneROM_in, addrwriteMix_in, addrreadInit_in, addrreadSave_in, intcycles_in} =
(phase == THREADS ) ? 0 : sstate[phase];
reg busy_flag = 1'b0;
`ifdef ONETHREAD
reg start_once = 1'b0;
wire start_flag;
assign start_flag = fsmstart & ~start_once;
assign busy = busy_flag;
`else
reg [15:0] start_count = 0;
parameter START_INTERVAL = (THREADS+1) * 1024 * ((1 << (15-ADDRBITS)) * THREADS / 32 + 3) / THREADS / 2;
reg start_flag = 1'b0;
assign busy = busy_flag;
`endif
always @ (posedge hash_clk)
begin
X0 <= X0in;
X1 <= X1in;
if (phase_d != THREADS)
sstate[phase_d] <= fsmreset ? 0 : { mstate, writeaddr, cycle, doneROM, addrwriteMix, addrreadInit, addrreadSave, intcycles };
mstate <= mstate_in;
writeaddr <= writeaddr_in;
cycle <= cycle_in;
intcycles <= intcycles_in;
doneROM <= doneROM_in;
addrwriteMix <= addrwriteMix_in;
addrreadInit <= addrreadInit_in;
addrreadSave <= addrreadSave_in;
rd_addr_z_1 <= {ADDRBITS{fsmreset}};
rd_addr_z_2 <= {ADDRBITS{fsmreset}};
rd_addr_z_3 <= {ADDRBITS{fsmreset}};
rd_addr_z_4 <= {ADDRBITS{fsmreset}};
phase_addr_d <= phase[THREADS_BITS-1:0];
XCtl <= XSmix;
addrreadInit <= 1'b0;
addrreadSave <= 1'b0;
ram_wren <= 1'b0;
xoren <= 1'b1;
`ifdef ONETHREAD
if (fsmstart && phase!=THREADS)
start_once <= 1'b1;
if (fsmreset)
start_once <= 1'b0;
`else
start_count <= start_count + 1;
if (fsmreset || start_count == START_INTERVAL)
begin
start_count <= 0;
if (~fsmreset && fsmstart)
start_flag <= 1'b1;
end
`endif
if (shift)
begin
salsaShiftReg <= { salsaShiftReg[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], din};
end
else
if (XCtl[0] && phase_d != THREADS)
begin
salsaShiftReg <= ramout;
nonce_sr <= snonce[phase_d];
snonce[phase_d] <= nonce_sr;
end
if (fsmreset == 1'b1)
begin
mstate <= R_IDLE;
busy_flag <= 1'b0;
result <= 1'b0;
end
else
begin
case (mstate_in)
R_IDLE: begin
if (phase!=THREADS && start_flag)
begin
`ifndef ONETHREAD
start_flag <= 1'b0;
`endif
busy_flag <= 1'b0;
mstate <= R_START;
writeaddr <= 0;
addrwriteMix <= 1'b0;
ram_wren <= 1'b1;
XCtl <= XSload;
addrreadInit <= 1'b1;
end
end
R_START: begin
XCtl <= XSram;
xoren <= 1'b0;
cycle <= 0;
doneROM <= 1'b0;
busy_flag <= 1'b1;
result <= 1'b0;
mstate <= R_LOAD;
end
R_LOAD: begin
writeaddr <= writeaddr_next;
if (INT_BITS == 0)
ram_wren <= 1'b1;
mstate <= R_WRITE;
end
R_WRITE: begin
writeaddr <= writeaddr_next;
if (writeaddr_in==1022)
doneROM <= 1'b1;
if (doneROM_in)
begin
addrwriteMix <= 1'b1;
mstate <= R_MIX;
XCtl <= XSram;
if (INT_BITS > 0)
begin
intcycles <= { 1'b0, Xaddr[INT_BITX-1:0] };
if ( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] )
intcycles <= { 1'b1, Xaddr[INT_BITX-1:0] };
if ( (Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1]) || |Xaddr[INT_BITX-1:0] )
begin
ram_wren <= 1'b1;
xoren <= 1'b0;
mstate <= R_INT;
end
if (
( Xaddr[INT_BITX-1:0] == 1 ) &&
!( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] )
)
addrreadSave <= 1'b1;
end
end
else
begin
ram_wren <= (INT_BITS > 0) ? ~|writeaddr_next[INT_BITX-1:0] : 1'b1;
end
end
R_MIX: begin
cycle <= cycle_in + 11'd1;
if (cycle_in==1023)
begin
mstate <= R_WAIT;
addrreadSave <= 1'b1;
ram_wren <= 1'b1;
end
else
begin
XCtl <= XSram;
if (INT_BITS > 0)
begin
intcycles <= { 1'b0, Xaddr[INT_BITX-1:0] };
if ( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] )
intcycles <= { 1'b1, Xaddr[INT_BITX-1:0] };
if ( (Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1]) || |Xaddr[INT_BITX-1:0] )
begin
ram_wren <= 1'b1;
xoren <= 1'b0;
mstate <= R_INT;
end
if (
( Xaddr[INT_BITX-1:0] == 1 ) &&
!( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] )
)
addrreadSave <= 1'b1;
end
end
end
R_INT: begin
intcycles <= intcycles_in - 1;
if (intcycles_in==2)
addrreadSave <= 1'b1;
if (intcycles_in==1)
begin
XCtl <= XSram;
mstate <= R_MIX;
end
end
R_WAIT: begin
if (fsmstart)
begin
busy_flag <= 1'b0;
result <= 1'b1;
mstate <= R_START;
writeaddr <= 0;
addrwriteMix <= 1'b0;
ram_wren <= 1'b1;
XCtl <= XSload;
addrreadInit <= 1'b1;
end
else
addrreadSave <= 1'b1;
end
endcase
end
`ifdef SIM
if (mstate==R_MIX)
$display ("phase %d cycle %d Xmix %08x\n", phase, cycle-1, Xmix[511:480]);
`endif
end
endmodule | module salsaengine (hash_clk, reset, din, dout, shift, start, busy, result ); |
input hash_clk;
input reset;
input shift;
input start;
output busy;
output reg result = 1'b0;
parameter SBITS = 8;
input [SBITS-1:0] din;
output [SBITS-1:0] dout;
parameter ADDRBITS = 12;
parameter THREADS = 64;
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
parameter THREADS_BITS = clog2(THREADS);
reg [THREADS_BITS:0]phase = 0;
reg [THREADS_BITS:0]phase_d = THREADS;
reg reset_d=0, fsmreset=0, start_d=0, fsmstart=0;
always @ (posedge hash_clk)
begin
phase <= (phase == THREADS) ? 0 : phase + 1;
phase_d <= phase;
reset_d <= reset;
fsmreset <= reset_d;
start_d <= start;
fsmstart <= start_d;
end
parameter XSmix = 0, XSload = 1, XSram = 2;
reg [1:0] XCtl = XSmix;
parameter R_IDLE=0, R_START=1, R_LOAD=2, R_WRITE=3, R_MIX=4, R_INT=5, R_WAIT=6;
reg [2:0] mstate = R_IDLE;
reg [10:0] cycle = 11'd0;
reg doneROM = 1'd0;
reg addrwriteMix = 1'b0;
reg addrreadInit = 1'b0;
reg addrreadSave = 1'b0;
reg xoren = 1'b0;
parameter INT_BITS = THREADS_BITS - ADDRBITS + 10;
parameter INT_BITX = (INT_BITS > 0) ? INT_BITS : INT_BITS+1;
reg [INT_BITS:0] intcycles = 0;
wire [511:0] Xmix;
reg [511:0] X0;
reg [511:0] X1;
wire [511:0] X0in;
wire [511:0] X1in;
wire [511:0] X0out;
reg [1023:0] salsaShiftReg;
reg [31:0] nonce_sr;
assign dout = salsaShiftReg[1023:1024-SBITS];
reg [INT_BITS+28:0] sstate [THREADS-1:0];
wire [2:0] mstate_in;
wire [10:0] cycle_in;
wire [9:0] writeaddr_in;
wire doneROM_in;
wire addrwriteMix_in;
wire addrreadInit_in;
wire addrreadSave_in;
wire [INT_BITS:0] intcycles_in;
wire [9:0] writeaddr_next = writeaddr_in + 10'd1;
reg [31:0] snonce [THREADS-1:0];
wire [1023:0] X;
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] tmp;
assign tmp = salsaShiftReg[`IDX(i)];
assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] };
end
endgenerate
(* S = "TRUE" *) reg [9:0] writeaddr = 10'd0;
wire [9:0] Xaddr;
wire [ADDRBITS-1:0]rd_addr;
wire [ADDRBITS-1:0]wr_addr1;
wire [ADDRBITS-1:0]wr_addr2;
wire [ADDRBITS-1:0]wr_addr3;
wire [ADDRBITS-1:0]wr_addr4;
wire [255:0]ram1_din;
wire [255:0]ram1_dout;
wire [255:0]ram2_din;
wire [255:0]ram2_dout;
wire [255:0]ram3_din;
wire [255:0]ram3_dout;
wire [255:0]ram4_din;
wire [255:0]ram4_dout;
wire [1023:0]ramout;
(* S = "TRUE" *) reg ram_wren = 1'b0;
wire ram_clk;
assign ram_clk = hash_clk;
wire [15:0] memtop = 16'hfffe;
wire [9-INT_BITS:0] adj_addr;
if (INT_BITS > 0)
assign adj_addr = (Xaddr[9:INT_BITS] == memtop[9:INT_BITS]) ?
memtop[9-INT_BITS:0] : Xaddr[9:INT_BITS];
else
assign adj_addr = Xaddr;
wire [THREADS_BITS-1:0] phase_addr;
assign phase_addr = phase[THREADS_BITS-1:0];
reg [THREADS_BITS-1:0] phase_addr_d = 0;
assign rd_addr = { phase_addr,
(addrreadSave_in | addrreadInit_in) ?
(addrreadInit_in ? {ADDRBITS-THREADS_BITS{1'b0}} : memtop[ADDRBITS-THREADS_BITS:1])
:
adj_addr };
wire [9:0] writeaddr_adj = addrwriteMix ? memtop[10:1] : writeaddr;
assign wr_addr1 = { phase_addr_d, writeaddr_adj[9:INT_BITS] };
assign wr_addr2 = { phase_addr_d, writeaddr_adj[9:INT_BITS] };
assign wr_addr3 = { phase_addr_d, writeaddr_adj[9:INT_BITS] };
assign wr_addr4 = { phase_addr_d, writeaddr_adj[9:INT_BITS] };
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_1 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_2 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_3 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_4 = 0;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr1 = rd_addr | rd_addr_z_1;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr2 = rd_addr | rd_addr_z_2;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr3 = rd_addr | rd_addr_z_3;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr4 = rd_addr | rd_addr_z_4;
ram # (.ADDRBITS(ADDRBITS)) ram1_blk (rd_addr1, wr_addr1, ram_clk, ram1_din, ram_wren, ram1_dout);
ram # (.ADDRBITS(ADDRBITS)) ram2_blk (rd_addr2, wr_addr2, ram_clk, ram2_din, ram_wren, ram2_dout);
ram # (.ADDRBITS(ADDRBITS)) ram3_blk (rd_addr3, wr_addr3, ram_clk, ram3_din, ram_wren, ram3_dout);
ram # (.ADDRBITS(ADDRBITS)) ram4_blk (rd_addr4, wr_addr4, ram_clk, ram4_din, ram_wren, ram4_dout);
assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout };
assign { ram4_din, ram3_din, ram2_din, ram1_din } = XCtl[0] ? X : { Xmix, X0out};
salsa salsa_blk (hash_clk, X0, X1, Xmix, X0out, Xaddr);
wire [511:0] Zbits;
assign Zbits = {512{xoren}};
assign X0in = XCtl[1] ? (X0out & Zbits) ^ ramout[511:0] : X0out;
assign X1in = XCtl[1] ? (Xmix & Zbits) ^ ramout[1023:512] : Xmix;
assign { mstate_in, writeaddr_in, cycle_in, doneROM_in, addrwriteMix_in, addrreadInit_in, addrreadSave_in, intcycles_in} =
(phase == THREADS ) ? 0 : sstate[phase];
reg busy_flag = 1'b0;
`ifdef ONETHREAD
reg start_once = 1'b0;
wire start_flag;
assign start_flag = fsmstart & ~start_once;
assign busy = busy_flag;
`else
reg [15:0] start_count = 0;
parameter START_INTERVAL = (THREADS+1) * 1024 * ((1 << (15-ADDRBITS)) * THREADS / 32 + 3) / THREADS / 2;
reg start_flag = 1'b0;
assign busy = busy_flag;
`endif
always @ (posedge hash_clk)
begin
X0 <= X0in;
X1 <= X1in;
if (phase_d != THREADS)
sstate[phase_d] <= fsmreset ? 0 : { mstate, writeaddr, cycle, doneROM, addrwriteMix, addrreadInit, addrreadSave, intcycles };
mstate <= mstate_in;
writeaddr <= writeaddr_in;
cycle <= cycle_in;
intcycles <= intcycles_in;
doneROM <= doneROM_in;
addrwriteMix <= addrwriteMix_in;
addrreadInit <= addrreadInit_in;
addrreadSave <= addrreadSave_in;
rd_addr_z_1 <= {ADDRBITS{fsmreset}};
rd_addr_z_2 <= {ADDRBITS{fsmreset}};
rd_addr_z_3 <= {ADDRBITS{fsmreset}};
rd_addr_z_4 <= {ADDRBITS{fsmreset}};
phase_addr_d <= phase[THREADS_BITS-1:0];
XCtl <= XSmix;
addrreadInit <= 1'b0;
addrreadSave <= 1'b0;
ram_wren <= 1'b0;
xoren <= 1'b1;
`ifdef ONETHREAD
if (fsmstart && phase!=THREADS)
start_once <= 1'b1;
if (fsmreset)
start_once <= 1'b0;
`else
start_count <= start_count + 1;
if (fsmreset || start_count == START_INTERVAL)
begin
start_count <= 0;
if (~fsmreset && fsmstart)
start_flag <= 1'b1;
end
`endif
if (shift)
begin
salsaShiftReg <= { salsaShiftReg[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], din};
end
else
if (XCtl[0] && phase_d != THREADS)
begin
salsaShiftReg <= ramout;
nonce_sr <= snonce[phase_d];
snonce[phase_d] <= nonce_sr;
end
if (fsmreset == 1'b1)
begin
mstate <= R_IDLE;
busy_flag <= 1'b0;
result <= 1'b0;
end
else
begin
case (mstate_in)
R_IDLE: begin
if (phase!=THREADS && start_flag)
begin
`ifndef ONETHREAD
start_flag <= 1'b0;
`endif
busy_flag <= 1'b0;
mstate <= R_START;
writeaddr <= 0;
addrwriteMix <= 1'b0;
ram_wren <= 1'b1;
XCtl <= XSload;
addrreadInit <= 1'b1;
end
end
R_START: begin
XCtl <= XSram;
xoren <= 1'b0;
cycle <= 0;
doneROM <= 1'b0;
busy_flag <= 1'b1;
result <= 1'b0;
mstate <= R_LOAD;
end
R_LOAD: begin
writeaddr <= writeaddr_next;
if (INT_BITS == 0)
ram_wren <= 1'b1;
mstate <= R_WRITE;
end
R_WRITE: begin
writeaddr <= writeaddr_next;
if (writeaddr_in==1022)
doneROM <= 1'b1;
if (doneROM_in)
begin
addrwriteMix <= 1'b1;
mstate <= R_MIX;
XCtl <= XSram;
if (INT_BITS > 0)
begin
intcycles <= { 1'b0, Xaddr[INT_BITX-1:0] };
if ( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] )
intcycles <= { 1'b1, Xaddr[INT_BITX-1:0] };
if ( (Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1]) || |Xaddr[INT_BITX-1:0] )
begin
ram_wren <= 1'b1;
xoren <= 1'b0;
mstate <= R_INT;
end
if (
( Xaddr[INT_BITX-1:0] == 1 ) &&
!( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] )
)
addrreadSave <= 1'b1;
end
end
else
begin
ram_wren <= (INT_BITS > 0) ? ~|writeaddr_next[INT_BITX-1:0] : 1'b1;
end
end
R_MIX: begin
cycle <= cycle_in + 11'd1;
if (cycle_in==1023)
begin
mstate <= R_WAIT;
addrreadSave <= 1'b1;
ram_wren <= 1'b1;
end
else
begin
XCtl <= XSram;
if (INT_BITS > 0)
begin
intcycles <= { 1'b0, Xaddr[INT_BITX-1:0] };
if ( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] )
intcycles <= { 1'b1, Xaddr[INT_BITX-1:0] };
if ( (Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1]) || |Xaddr[INT_BITX-1:0] )
begin
ram_wren <= 1'b1;
xoren <= 1'b0;
mstate <= R_INT;
end
if (
( Xaddr[INT_BITX-1:0] == 1 ) &&
!( Xaddr[9:INT_BITX] == memtop[10-INT_BITX:1] )
)
addrreadSave <= 1'b1;
end
end
end
R_INT: begin
intcycles <= intcycles_in - 1;
if (intcycles_in==2)
addrreadSave <= 1'b1;
if (intcycles_in==1)
begin
XCtl <= XSram;
mstate <= R_MIX;
end
end
R_WAIT: begin
if (fsmstart)
begin
busy_flag <= 1'b0;
result <= 1'b1;
mstate <= R_START;
writeaddr <= 0;
addrwriteMix <= 1'b0;
ram_wren <= 1'b1;
XCtl <= XSload;
addrreadInit <= 1'b1;
end
else
addrreadSave <= 1'b1;
end
endcase
end
`ifdef SIM
if (mstate==R_MIX)
$display ("phase %d cycle %d Xmix %08x\n", phase, cycle-1, Xmix[511:480]);
`endif
end
endmodule | 270 |
6,311 | data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v | 11,584,509 | salsaengine.v | v | 508 | 132 | [] | [] | [] | null | line:60: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:217: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram1_blk (rd_addr1, wr_addr1, ram_clk, ram1_din, ram_wren, ram1_dout);\n ^~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A,data/full_repos/permissive/11584509/ram\n data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A,data/full_repos/permissive/11584509/ram.v\n data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A,data/full_repos/permissive/11584509/ram.sv\n ram\n ram.v\n ram.sv\n obj_dir/ram\n obj_dir/ram.v\n obj_dir/ram.sv\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:218: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram2_blk (rd_addr2, wr_addr2, ram_clk, ram2_din, ram_wren, ram2_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:219: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram3_blk (rd_addr3, wr_addr3, ram_clk, ram3_din, ram_wren, ram3_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:220: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram4_blk (rd_addr4, wr_addr4, ram_clk, ram4_din, ram_wren, ram4_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:228: Cannot find file containing module: \'salsa\'\n salsa salsa_blk (hash_clk, X0, X1, Xmix, X0out, Xaddr);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:245: Bit extraction of array[63:0] requires 6 bit index, not 7 bits.\n : ... In instance salsaengine\n (phase == THREADS ) ? 0 : sstate[phase]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:283: Bit extraction of array[63:0] requires 6 bit index, not 7 bits.\n : ... In instance salsaengine\n sstate[phase_d] <= fsmreset ? 0 : { mstate, writeaddr, cycle, doneROM, addrwriteMix, addrreadInit, addrreadSave, intcycles };\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:335: Bit extraction of array[63:0] requires 6 bit index, not 7 bits.\n : ... In instance salsaengine\n nonce_sr <= snonce[phase_d]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-SIXTYFOUR-A/salsaengine.v:336: Bit extraction of array[63:0] requires 6 bit index, not 7 bits.\n : ... In instance salsaengine\n snonce[phase_d] <= nonce_sr;\n ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n' | 7,184 | function | function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction | function integer clog2; |
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction | 270 |
6,316 | data/full_repos/permissive/11584509/experimental/LX150-SPLIT/ltcminer_icarus.v | 11,584,509 | ltcminer_icarus.v | v | 200 | 205 | [] | [] | [] | null | line:666: before: "=" | null | 1: b'%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/ltcminer_icarus.v:7: Cannot find include file: ../../source/sha-256-functions.v\n`include "../../source/sha-256-functions.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/LX150-SPLIT,data/full_repos/permissive/11584509/../../source/sha-256-functions.v\n data/full_repos/permissive/11584509/experimental/LX150-SPLIT,data/full_repos/permissive/11584509/../../source/sha-256-functions.v.v\n data/full_repos/permissive/11584509/experimental/LX150-SPLIT,data/full_repos/permissive/11584509/../../source/sha-256-functions.v.sv\n ../../source/sha-256-functions.v\n ../../source/sha-256-functions.v.v\n ../../source/sha-256-functions.v.sv\n obj_dir/../../source/sha-256-functions.v\n obj_dir/../../source/sha-256-functions.v.v\n obj_dir/../../source/sha-256-functions.v.sv\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/ltcminer_icarus.v:8: Cannot find include file: ../../source/sha256_transform.v\n`include "../../source/sha256_transform.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/ltcminer_icarus.v:9: Cannot find include file: ../../source/salsa.v\n`include "../../source/salsa.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/ltcminer_icarus.v:10: Cannot find include file: ../../ICARUS-LX150/xilinx_ram.v\n`include "../../ICARUS-LX150/xilinx_ram.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/ltcminer_icarus.v:11: Cannot find include file: ../../ICARUS-LX150/xilinx_pll.v\n`include "../../ICARUS-LX150/xilinx_pll.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/ltcminer_icarus.v:12: Cannot find include file: ../../ICARUS-LX150/uart_receiver.v\n`include "../../ICARUS-LX150/uart_receiver.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/ltcminer_icarus.v:13: Cannot find include file: ../../ICARUS-LX150/uart_transmitter.v\n`include "../../ICARUS-LX150/uart_transmitter.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/ltcminer_icarus.v:14: Cannot find include file: ../../ICARUS-LX150/serial.v\n`include "../../ICARUS-LX150/serial.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/ltcminer_icarus.v:15: Cannot find include file: ../../ICARUS-LX150/serial_hub.v\n`include "../../ICARUS-LX150/serial_hub.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/ltcminer_icarus.v:16: Cannot find include file: ../../ICARUS-LX150/hub_core.v\n`include "../../ICARUS-LX150/hub_core.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/ltcminer_icarus.v:17: Cannot find include file: ../../ICARUS-LX150/pwm_fade.v\n`include "../../ICARUS-LX150/pwm_fade.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n' | 7,205 | module | module ltcminer_icarus (osc_clk, RxD, TxD, led, extminer_rxd, extminer_txd, dip, TMP_SCL, TMP_SDA, TMP_ALERT);
`ifdef SPEED_MHZ
parameter SPEED_MHZ = `SPEED_MHZ;
`else
parameter SPEED_MHZ = 25;
`endif
`ifdef SERIAL_CLK
parameter comm_clk_frequency = `SERIAL_CLK;
`else
parameter comm_clk_frequency = 12_500_000;
`endif
`ifdef BAUD_RATE
parameter BAUD_RATE = `BAUD_RATE;
`else
parameter BAUD_RATE = 115_200;
`endif
input osc_clk;
wire hash_clk, uart_clk;
`ifndef SIM
main_pll # (.SPEED_MHZ(SPEED_MHZ)) pll_blk (.CLKIN_IN(osc_clk), .CLKFX_OUT(hash_clk), .CLKDV_OUT(uart_clk));
`else
assign hash_clk = osc_clk;
assign uart_clk = osc_clk;
`endif
`ifdef LOCAL_MINERS
parameter LOCAL_MINERS = `LOCAL_MINERS;
`else
parameter LOCAL_MINERS = 1;
`endif
`ifdef EXT_PORTS
parameter EXT_PORTS = `EXT_PORTS;
`else
parameter EXT_PORTS = 1;
`endif
localparam SLAVES = LOCAL_MINERS + EXT_PORTS;
input TMP_SCL, TMP_SDA, TMP_ALERT;
input [3:0]dip;
wire reset, nonce_chip;
assign reset = dip[0];
assign nonce_chip = dip[1];
input RxD;
output TxD;
wire [SLAVES*32-1:0] slave_nonces;
wire [SLAVES-1:0] new_nonces;
wire serial_send;
wire serial_busy;
wire [31:0] golden_nonce;
serial_transmit #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) sertx (.clk(uart_clk), .TxD(TxD), .send(serial_send), .busy(serial_busy), .word(golden_nonce));
hub_core #(.SLAVES(SLAVES)) hc (.uart_clk(uart_clk), .new_nonces(new_nonces), .golden_nonce(golden_nonce), .serial_send(serial_send), .serial_busy(serial_busy), .slave_nonces(slave_nonces));
wire [255:0] data1, data2;
wire [127:0] data3;
wire [31:0] target;
reg [31:0] targetreg = 32'h000007ff;
wire rx_done;
reg rx_done_toggle = 1'b0;
always @ (posedge uart_clk)
rx_done_toggle <= rx_done_toggle ^ rx_done;
reg rx_done_toggle_d1 = 1'b0;
reg rx_done_toggle_d2 = 1'b0;
reg rx_done_toggle_d3 = 1'b0;
wire loadnonce;
assign loadnonce = rx_done_toggle_d3 ^ rx_done_toggle_d2;
always @ (posedge hash_clk)
begin
rx_done_toggle_d1 <= rx_done_toggle;
rx_done_toggle_d2 <= rx_done_toggle_d1;
rx_done_toggle_d3 <= rx_done_toggle_d2;
if (loadnonce)
targetreg <= target;
end
serial_receive #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) serrx (.clk(uart_clk), .RxD(RxD), .data1(data1),
.data2(data2), .data3(data3), .target(target), .rx_done(rx_done));
generate
genvar i;
for (i = 0; i < LOCAL_MINERS; i = i + 1)
begin: for_local_miners
wire [31:0] nonce_out;
wire [2:0] nonce_core = i;
wire gn_match;
wire salsa_din, salsa_dout, salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift;
pbkdfengine P (.hash_clk(hash_clk), .data1(data1), .data2(data2), .data3(data3), .target(targetreg),
.nonce_msb({nonce_chip, nonce_core}), .nonce_out(nonce_out), .golden_nonce_out(slave_nonces[i*32+31:i*32]),
.golden_nonce_match(gn_match), .loadnonce(loadnonce),
.salsa_din(salsa_din), .salsa_dout(salsa_dout), .salsa_busy(salsa_busy), .salsa_result(salsa_result),
.salsa_reset(salsa_reset), .salsa_start(salsa_start), .salsa_shift(salsa_shift));
salsaengine S (.hash_clk(hash_clk), .reset(salsa_reset), .din(salsa_din), .dout(salsa_dout), .shift(salsa_shift),
.start(salsa_start), .busy(salsa_busy), .result(salsa_result) );
reg gn_match_toggle = 1'b0;
always @ (posedge hash_clk)
gn_match_toggle <= gn_match_toggle ^ gn_match;
reg gn_match_toggle_d1 = 1'b0;
reg gn_match_toggle_d2 = 1'b0;
reg gn_match_toggle_d3 = 1'b0;
assign new_nonces[i] = gn_match_toggle_d3 ^ gn_match_toggle_d2;
always @ (posedge uart_clk)
begin
gn_match_toggle_d1 <= gn_match_toggle;
gn_match_toggle_d2 <= gn_match_toggle_d1;
gn_match_toggle_d3 <= gn_match_toggle_d2;
end
end
endgenerate
output [EXT_PORTS-1:0] extminer_txd;
input [EXT_PORTS-1:0] extminer_rxd;
assign extminer_txd = {EXT_PORTS{RxD}};
generate
genvar j;
for (j = LOCAL_MINERS; j < SLAVES; j = j + 1)
begin: for_ports
slave_receive #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) slrx (.clk(uart_clk), .RxD(extminer_rxd[j-LOCAL_MINERS]), .nonce(slave_nonces[j*32+31:j*32]), .new_nonce(new_nonces[j]));
end
endgenerate
output [3:0] led;
assign led[1] = ~RxD;
assign led[2] = ~TxD;
assign led[3] = ~ (TMP_SCL | TMP_SDA | TMP_ALERT);
pwm_fade pf (.clk(uart_clk), .trigger(|new_nonces[LOCAL_MINERS-1:0]), .drive(led[0]));
endmodule | module ltcminer_icarus (osc_clk, RxD, TxD, led, extminer_rxd, extminer_txd, dip, TMP_SCL, TMP_SDA, TMP_ALERT); |
`ifdef SPEED_MHZ
parameter SPEED_MHZ = `SPEED_MHZ;
`else
parameter SPEED_MHZ = 25;
`endif
`ifdef SERIAL_CLK
parameter comm_clk_frequency = `SERIAL_CLK;
`else
parameter comm_clk_frequency = 12_500_000;
`endif
`ifdef BAUD_RATE
parameter BAUD_RATE = `BAUD_RATE;
`else
parameter BAUD_RATE = 115_200;
`endif
input osc_clk;
wire hash_clk, uart_clk;
`ifndef SIM
main_pll # (.SPEED_MHZ(SPEED_MHZ)) pll_blk (.CLKIN_IN(osc_clk), .CLKFX_OUT(hash_clk), .CLKDV_OUT(uart_clk));
`else
assign hash_clk = osc_clk;
assign uart_clk = osc_clk;
`endif
`ifdef LOCAL_MINERS
parameter LOCAL_MINERS = `LOCAL_MINERS;
`else
parameter LOCAL_MINERS = 1;
`endif
`ifdef EXT_PORTS
parameter EXT_PORTS = `EXT_PORTS;
`else
parameter EXT_PORTS = 1;
`endif
localparam SLAVES = LOCAL_MINERS + EXT_PORTS;
input TMP_SCL, TMP_SDA, TMP_ALERT;
input [3:0]dip;
wire reset, nonce_chip;
assign reset = dip[0];
assign nonce_chip = dip[1];
input RxD;
output TxD;
wire [SLAVES*32-1:0] slave_nonces;
wire [SLAVES-1:0] new_nonces;
wire serial_send;
wire serial_busy;
wire [31:0] golden_nonce;
serial_transmit #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) sertx (.clk(uart_clk), .TxD(TxD), .send(serial_send), .busy(serial_busy), .word(golden_nonce));
hub_core #(.SLAVES(SLAVES)) hc (.uart_clk(uart_clk), .new_nonces(new_nonces), .golden_nonce(golden_nonce), .serial_send(serial_send), .serial_busy(serial_busy), .slave_nonces(slave_nonces));
wire [255:0] data1, data2;
wire [127:0] data3;
wire [31:0] target;
reg [31:0] targetreg = 32'h000007ff;
wire rx_done;
reg rx_done_toggle = 1'b0;
always @ (posedge uart_clk)
rx_done_toggle <= rx_done_toggle ^ rx_done;
reg rx_done_toggle_d1 = 1'b0;
reg rx_done_toggle_d2 = 1'b0;
reg rx_done_toggle_d3 = 1'b0;
wire loadnonce;
assign loadnonce = rx_done_toggle_d3 ^ rx_done_toggle_d2;
always @ (posedge hash_clk)
begin
rx_done_toggle_d1 <= rx_done_toggle;
rx_done_toggle_d2 <= rx_done_toggle_d1;
rx_done_toggle_d3 <= rx_done_toggle_d2;
if (loadnonce)
targetreg <= target;
end
serial_receive #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) serrx (.clk(uart_clk), .RxD(RxD), .data1(data1),
.data2(data2), .data3(data3), .target(target), .rx_done(rx_done));
generate
genvar i;
for (i = 0; i < LOCAL_MINERS; i = i + 1)
begin: for_local_miners
wire [31:0] nonce_out;
wire [2:0] nonce_core = i;
wire gn_match;
wire salsa_din, salsa_dout, salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift;
pbkdfengine P (.hash_clk(hash_clk), .data1(data1), .data2(data2), .data3(data3), .target(targetreg),
.nonce_msb({nonce_chip, nonce_core}), .nonce_out(nonce_out), .golden_nonce_out(slave_nonces[i*32+31:i*32]),
.golden_nonce_match(gn_match), .loadnonce(loadnonce),
.salsa_din(salsa_din), .salsa_dout(salsa_dout), .salsa_busy(salsa_busy), .salsa_result(salsa_result),
.salsa_reset(salsa_reset), .salsa_start(salsa_start), .salsa_shift(salsa_shift));
salsaengine S (.hash_clk(hash_clk), .reset(salsa_reset), .din(salsa_din), .dout(salsa_dout), .shift(salsa_shift),
.start(salsa_start), .busy(salsa_busy), .result(salsa_result) );
reg gn_match_toggle = 1'b0;
always @ (posedge hash_clk)
gn_match_toggle <= gn_match_toggle ^ gn_match;
reg gn_match_toggle_d1 = 1'b0;
reg gn_match_toggle_d2 = 1'b0;
reg gn_match_toggle_d3 = 1'b0;
assign new_nonces[i] = gn_match_toggle_d3 ^ gn_match_toggle_d2;
always @ (posedge uart_clk)
begin
gn_match_toggle_d1 <= gn_match_toggle;
gn_match_toggle_d2 <= gn_match_toggle_d1;
gn_match_toggle_d3 <= gn_match_toggle_d2;
end
end
endgenerate
output [EXT_PORTS-1:0] extminer_txd;
input [EXT_PORTS-1:0] extminer_rxd;
assign extminer_txd = {EXT_PORTS{RxD}};
generate
genvar j;
for (j = LOCAL_MINERS; j < SLAVES; j = j + 1)
begin: for_ports
slave_receive #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) slrx (.clk(uart_clk), .RxD(extminer_rxd[j-LOCAL_MINERS]), .nonce(slave_nonces[j*32+31:j*32]), .new_nonce(new_nonces[j]));
end
endgenerate
output [3:0] led;
assign led[1] = ~RxD;
assign led[2] = ~TxD;
assign led[3] = ~ (TMP_SCL | TMP_SDA | TMP_ALERT);
pwm_fade pf (.clk(uart_clk), .trigger(|new_nonces[LOCAL_MINERS-1:0]), .drive(led[0]));
endmodule | 270 |
6,317 | data/full_repos/permissive/11584509/experimental/LX150-SPLIT/salsaengine.v | 11,584,509 | salsaengine.v | v | 317 | 133 | [] | [] | [] | [(28, 317)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/salsaengine.v:43: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance salsaengine\n reg [5:0] mcount = 5\'d0; \n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/salsaengine.v:110: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram1_blk (ram_addr, ram_clk, ram1_din, ram_wren, ram1_dout);\n ^~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/LX150-SPLIT,data/full_repos/permissive/11584509/ram\n data/full_repos/permissive/11584509/experimental/LX150-SPLIT,data/full_repos/permissive/11584509/ram.v\n data/full_repos/permissive/11584509/experimental/LX150-SPLIT,data/full_repos/permissive/11584509/ram.sv\n ram\n ram.v\n ram.sv\n obj_dir/ram\n obj_dir/ram.v\n obj_dir/ram.sv\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/salsaengine.v:111: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram2_blk (ram_addr, ram_clk, ram2_din, ram_wren, ram2_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/salsaengine.v:112: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram3_blk (ram_addr, ram_clk, ram3_din, ram_wren, ram3_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/salsaengine.v:113: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram4_blk (ram_addr, ram_clk, ram4_din, ram_wren, ram4_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/salsaengine.v:119: Cannot find file containing module: \'salsa\'\n salsa salsa_blk (hash_clk, mixfeedback, X0, X1, Xmix);\n ^~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n' | 7,207 | module | module salsaengine (hash_clk, reset, din, dout, shift, start, busy, result );
input hash_clk, reset, din, shift, start;
output reg busy = 1'b0;
output reg result = 1'b0;
output dout;
parameter XSnull = 0, XSload = 1, XSmix = 2, XSram = 4;
reg [2:0] XCtl = XSnull;
parameter R_IDLE=0, R_START=1, R_WRITE=2, R_MIX=4, R_INT=8;
reg [3:0] mstate = R_IDLE;
reg [10:0] cycle = 11'd0;
reg [5:0] mcount = 5'd0;
reg doneROM = 1'd0;
reg mixfeedback = 1'b0;
reg addrsourceMix = 1'b0;
reg addrsourceSave = 1'b0;
reg xoren = 1'b1;
reg [1:0] intcycles = 2'b0;
wire [511:0] Xmix;
reg [511:0] X0;
reg [511:0] X1;
wire [511:0] X0in;
wire [511:0] X1in;
reg [1023:0] salsaShiftReg;
assign dout = salsaShiftReg[1023];
wire [1023:0] X;
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] tmp;
assign tmp = salsaShiftReg[`IDX(i)];
assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] };
end
endgenerate
reg [9:0] writeaddr = 10'd0;
`ifdef HALFRAM
parameter ADDRBITS = 9;
`else
parameter ADDRBITS = 10;
`endif
wire [ADDRBITS-1:0]ram_addr;
wire [255:0]ram1_din;
wire [255:0]ram1_dout;
wire [255:0]ram2_din;
wire [255:0]ram2_dout;
wire [255:0]ram3_din;
wire [255:0]ram3_dout;
wire [255:0]ram4_din;
wire [255:0]ram4_dout;
wire [1023:0]ramout;
reg ram_wren = 1'b0;
wire ram_clk;
assign ram_clk = hash_clk;
`ifdef HALFRAM
wire [8:0] adj_addr = (Xmix[9:1] == 9'h1ff) ? 9'h1fe : Xmix[9:1];
assign ram_addr = addrsourceMix ? (addrsourceSave ? 9'h1ff : adj_addr) : writeaddr[9:1];
`else
assign ram_addr = addrsourceMix ? Xmix[9:0] : writeaddr;
`endif
ram # (.ADDRBITS(ADDRBITS)) ram1_blk (ram_addr, ram_clk, ram1_din, ram_wren, ram1_dout);
ram # (.ADDRBITS(ADDRBITS)) ram2_blk (ram_addr, ram_clk, ram2_din, ram_wren, ram2_dout);
ram # (.ADDRBITS(ADDRBITS)) ram3_blk (ram_addr, ram_clk, ram3_din, ram_wren, ram3_dout);
ram # (.ADDRBITS(ADDRBITS)) ram4_blk (ram_addr, ram_clk, ram4_din, ram_wren, ram4_dout);
assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout };
assign { ram4_din, ram3_din, ram2_din, ram1_din } = { X1, X0} ;
salsa salsa_blk (hash_clk, mixfeedback, X0, X1, Xmix);
wire [511:0] Zbits;
assign Zbits = {512{xoren}};
assign X0in = (XCtl==XSmix) ? X1 : (XCtl==XSram) ? (X0 & Zbits) ^ ramout[511:0] : (XCtl==XSload) ? X[511:0] : X0;
assign X1in = (XCtl==XSmix) ? Xmix : (XCtl==XSram) ? (X1 & Zbits) ^ ramout[1023:512] : (XCtl==XSload) ? X[1023:512] : X1;
always @ (posedge hash_clk)
begin
X0 <= X0in;
X1 <= X1in;
XCtl <= XSnull;
addrsourceSave <= 0;
ram_wren <= 0;
xoren <= 1;
if (shift)
salsaShiftReg <= { salsaShiftReg[1022:0], din };
if (reset == 1'b1)
begin
mstate <= R_IDLE;
result <= 1'b0;
end
else
begin
case (mstate)
R_IDLE: begin
writeaddr <= 0;
mcount <= 0;
mixfeedback <= 1'b0;
addrsourceMix <= 1'b0;
if (start)
begin
if (~result)
XCtl <= XSload;
doneROM <= 1'b0;
busy <= 1'b1;
result <= 1'b0;
mstate <= R_START;
end
end
R_START: begin
ram_wren <= 1'b1;
mstate <= R_WRITE;
end
R_WRITE: begin
mcount <= mcount + 6'd1;
if (mcount==0)
begin
mixfeedback <= 1'b1;
if (writeaddr==1023)
doneROM <= 1'b1;
writeaddr <= writeaddr + 10'd1;
end
if (mcount==4)
mixfeedback <= 1'b1;
if (mcount == 2 || mcount == 6)
XCtl <= XSmix;
if (mcount == 3 || mcount == 7)
mixfeedback <= 1'b0;
if (mcount == 6 && doneROM)
addrsourceMix <= 1'b1;
if (mcount == 7)
begin
mcount <= 0;
if (doneROM)
begin
cycle <= 0;
mstate <= R_MIX;
XCtl <= XSram;
`ifdef HALFRAM
intcycles <= { 1'b0, Xmix[0] };
if ( Xmix[9:1] == 9'h1ff )
intcycles <= { 1'b1, Xmix[0] };
if ( (Xmix[9:1] == 9'h1ff) || Xmix[0])
begin
addrsourceSave <= 1'b1;
ram_wren <= 1'b1;
xoren <= 0;
end
`endif
end
else
begin
`ifdef HALFRAM
if (!writeaddr[0])
ram_wren <= 1'b1;
`else
ram_wren <= 1'b1;
`endif
end
end
end
R_MIX: begin
mcount <= mcount + 5'd1;
if (mcount == 0)
begin
mixfeedback <= 1'b0;
`ifdef HALFRAM
if (intcycles != 0)
mstate <= R_INT;
`endif
end
if (mcount==1 || mcount==5)
mixfeedback <= 1;
if (mcount == 3 || mcount == 7)
XCtl <= XSmix;
if (mcount == 4 || mcount == 8)
mixfeedback <= 1'b0;
if (mcount == 7 && cycle == 1023)
XCtl <= XSload;
if (mcount == 8)
begin
mcount <= 0;
cycle <= cycle + 11'd1;
if (cycle == 1023)
begin
salsaShiftReg <= { Xmix, X1 };
result <= 1'b1;
busy <= 1'b0;
mstate <= R_IDLE;
end
else
begin
XCtl <= XSram;
`ifdef HALFRAM
intcycles <= { 1'b0, Xmix[0] };
if ( Xmix[9:1] == 9'h1ff )
intcycles <= { 1'b1, Xmix[0] };
if ( (Xmix[9:1] == 9'h1ff) || Xmix[0])
begin
addrsourceSave <= 1'b1;
ram_wren <= 1'b1;
xoren <= 0;
end
`endif
end
end
end
`ifdef HALFRAM
R_INT: begin
mcount <= mcount + 6'd1;
if (mcount==1 || mcount==5)
mixfeedback <= 1'b1;
if (mcount == 3 || mcount == 7)
XCtl <= XSmix;
if (mcount == 4 || mcount == 8)
mixfeedback <= 1'b0;
if (mcount == 7)
addrsourceSave <= 1'b1;
if (mcount == 8)
begin
if (intcycles == 1)
XCtl <= XSram;
end
if (mcount == 9)
begin
intcycles <= intcycles - 1;
mcount <= 1;
if (intcycles == 1)
mstate <= R_MIX;
end
end
`endif
endcase
end
`ifdef SIM
if (mstate == R_MIX && mcount == 8)
$display ("cycle %d Xmix %08x\n", cycle, Xmix[511:480]);
`endif
end
endmodule | module salsaengine (hash_clk, reset, din, dout, shift, start, busy, result ); |
input hash_clk, reset, din, shift, start;
output reg busy = 1'b0;
output reg result = 1'b0;
output dout;
parameter XSnull = 0, XSload = 1, XSmix = 2, XSram = 4;
reg [2:0] XCtl = XSnull;
parameter R_IDLE=0, R_START=1, R_WRITE=2, R_MIX=4, R_INT=8;
reg [3:0] mstate = R_IDLE;
reg [10:0] cycle = 11'd0;
reg [5:0] mcount = 5'd0;
reg doneROM = 1'd0;
reg mixfeedback = 1'b0;
reg addrsourceMix = 1'b0;
reg addrsourceSave = 1'b0;
reg xoren = 1'b1;
reg [1:0] intcycles = 2'b0;
wire [511:0] Xmix;
reg [511:0] X0;
reg [511:0] X1;
wire [511:0] X0in;
wire [511:0] X1in;
reg [1023:0] salsaShiftReg;
assign dout = salsaShiftReg[1023];
wire [1023:0] X;
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] tmp;
assign tmp = salsaShiftReg[`IDX(i)];
assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] };
end
endgenerate
reg [9:0] writeaddr = 10'd0;
`ifdef HALFRAM
parameter ADDRBITS = 9;
`else
parameter ADDRBITS = 10;
`endif
wire [ADDRBITS-1:0]ram_addr;
wire [255:0]ram1_din;
wire [255:0]ram1_dout;
wire [255:0]ram2_din;
wire [255:0]ram2_dout;
wire [255:0]ram3_din;
wire [255:0]ram3_dout;
wire [255:0]ram4_din;
wire [255:0]ram4_dout;
wire [1023:0]ramout;
reg ram_wren = 1'b0;
wire ram_clk;
assign ram_clk = hash_clk;
`ifdef HALFRAM
wire [8:0] adj_addr = (Xmix[9:1] == 9'h1ff) ? 9'h1fe : Xmix[9:1];
assign ram_addr = addrsourceMix ? (addrsourceSave ? 9'h1ff : adj_addr) : writeaddr[9:1];
`else
assign ram_addr = addrsourceMix ? Xmix[9:0] : writeaddr;
`endif
ram # (.ADDRBITS(ADDRBITS)) ram1_blk (ram_addr, ram_clk, ram1_din, ram_wren, ram1_dout);
ram # (.ADDRBITS(ADDRBITS)) ram2_blk (ram_addr, ram_clk, ram2_din, ram_wren, ram2_dout);
ram # (.ADDRBITS(ADDRBITS)) ram3_blk (ram_addr, ram_clk, ram3_din, ram_wren, ram3_dout);
ram # (.ADDRBITS(ADDRBITS)) ram4_blk (ram_addr, ram_clk, ram4_din, ram_wren, ram4_dout);
assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout };
assign { ram4_din, ram3_din, ram2_din, ram1_din } = { X1, X0} ;
salsa salsa_blk (hash_clk, mixfeedback, X0, X1, Xmix);
wire [511:0] Zbits;
assign Zbits = {512{xoren}};
assign X0in = (XCtl==XSmix) ? X1 : (XCtl==XSram) ? (X0 & Zbits) ^ ramout[511:0] : (XCtl==XSload) ? X[511:0] : X0;
assign X1in = (XCtl==XSmix) ? Xmix : (XCtl==XSram) ? (X1 & Zbits) ^ ramout[1023:512] : (XCtl==XSload) ? X[1023:512] : X1;
always @ (posedge hash_clk)
begin
X0 <= X0in;
X1 <= X1in;
XCtl <= XSnull;
addrsourceSave <= 0;
ram_wren <= 0;
xoren <= 1;
if (shift)
salsaShiftReg <= { salsaShiftReg[1022:0], din };
if (reset == 1'b1)
begin
mstate <= R_IDLE;
result <= 1'b0;
end
else
begin
case (mstate)
R_IDLE: begin
writeaddr <= 0;
mcount <= 0;
mixfeedback <= 1'b0;
addrsourceMix <= 1'b0;
if (start)
begin
if (~result)
XCtl <= XSload;
doneROM <= 1'b0;
busy <= 1'b1;
result <= 1'b0;
mstate <= R_START;
end
end
R_START: begin
ram_wren <= 1'b1;
mstate <= R_WRITE;
end
R_WRITE: begin
mcount <= mcount + 6'd1;
if (mcount==0)
begin
mixfeedback <= 1'b1;
if (writeaddr==1023)
doneROM <= 1'b1;
writeaddr <= writeaddr + 10'd1;
end
if (mcount==4)
mixfeedback <= 1'b1;
if (mcount == 2 || mcount == 6)
XCtl <= XSmix;
if (mcount == 3 || mcount == 7)
mixfeedback <= 1'b0;
if (mcount == 6 && doneROM)
addrsourceMix <= 1'b1;
if (mcount == 7)
begin
mcount <= 0;
if (doneROM)
begin
cycle <= 0;
mstate <= R_MIX;
XCtl <= XSram;
`ifdef HALFRAM
intcycles <= { 1'b0, Xmix[0] };
if ( Xmix[9:1] == 9'h1ff )
intcycles <= { 1'b1, Xmix[0] };
if ( (Xmix[9:1] == 9'h1ff) || Xmix[0])
begin
addrsourceSave <= 1'b1;
ram_wren <= 1'b1;
xoren <= 0;
end
`endif
end
else
begin
`ifdef HALFRAM
if (!writeaddr[0])
ram_wren <= 1'b1;
`else
ram_wren <= 1'b1;
`endif
end
end
end
R_MIX: begin
mcount <= mcount + 5'd1;
if (mcount == 0)
begin
mixfeedback <= 1'b0;
`ifdef HALFRAM
if (intcycles != 0)
mstate <= R_INT;
`endif
end
if (mcount==1 || mcount==5)
mixfeedback <= 1;
if (mcount == 3 || mcount == 7)
XCtl <= XSmix;
if (mcount == 4 || mcount == 8)
mixfeedback <= 1'b0;
if (mcount == 7 && cycle == 1023)
XCtl <= XSload;
if (mcount == 8)
begin
mcount <= 0;
cycle <= cycle + 11'd1;
if (cycle == 1023)
begin
salsaShiftReg <= { Xmix, X1 };
result <= 1'b1;
busy <= 1'b0;
mstate <= R_IDLE;
end
else
begin
XCtl <= XSram;
`ifdef HALFRAM
intcycles <= { 1'b0, Xmix[0] };
if ( Xmix[9:1] == 9'h1ff )
intcycles <= { 1'b1, Xmix[0] };
if ( (Xmix[9:1] == 9'h1ff) || Xmix[0])
begin
addrsourceSave <= 1'b1;
ram_wren <= 1'b1;
xoren <= 0;
end
`endif
end
end
end
`ifdef HALFRAM
R_INT: begin
mcount <= mcount + 6'd1;
if (mcount==1 || mcount==5)
mixfeedback <= 1'b1;
if (mcount == 3 || mcount == 7)
XCtl <= XSmix;
if (mcount == 4 || mcount == 8)
mixfeedback <= 1'b0;
if (mcount == 7)
addrsourceSave <= 1'b1;
if (mcount == 8)
begin
if (intcycles == 1)
XCtl <= XSram;
end
if (mcount == 9)
begin
intcycles <= intcycles - 1;
mcount <= 1;
if (intcycles == 1)
mstate <= R_MIX;
end
end
`endif
endcase
end
`ifdef SIM
if (mstate == R_MIX && mcount == 8)
$display ("cycle %d Xmix %08x\n", cycle, Xmix[511:480]);
`endif
end
endmodule | 270 |
6,318 | data/full_repos/permissive/11584509/experimental/ZTEX/ztex_ufm1_15b1_litecoin.v | 11,584,509 | ztex_ufm1_15b1_litecoin.v | v | 161 | 131 | [] | [] | [] | [(19, 159)] | null | null | 1: b"%Error: data/full_repos/permissive/11584509/experimental/ZTEX/ztex_ufm1_15b1_litecoin.v:54: Cannot find file containing module: 'hashcore'\n hashcore M (.hash_clk(clk), .data1(data1), .data2(data2), .data3(data3), .target(target),\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/ZTEX,data/full_repos/permissive/11584509/hashcore\n data/full_repos/permissive/11584509/experimental/ZTEX,data/full_repos/permissive/11584509/hashcore.v\n data/full_repos/permissive/11584509/experimental/ZTEX,data/full_repos/permissive/11584509/hashcore.sv\n hashcore\n hashcore.v\n hashcore.sv\n obj_dir/hashcore\n obj_dir/hashcore.v\n obj_dir/hashcore.sv\n%Error: data/full_repos/permissive/11584509/experimental/ZTEX/ztex_ufm1_15b1_litecoin.v:58: Cannot find file containing module: 'BUFG'\n BUFG bufg_fxclk (\n ^~~~\n%Error: data/full_repos/permissive/11584509/experimental/ZTEX/ztex_ufm1_15b1_litecoin.v:63: Cannot find file containing module: 'BUFG'\n BUFG bufg_clk (\n ^~~~\n%Error: data/full_repos/permissive/11584509/experimental/ZTEX/ztex_ufm1_15b1_litecoin.v:68: Cannot find file containing module: 'DCM_CLKGEN'\n DCM_CLKGEN #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/ZTEX/ztex_ufm1_15b1_litecoin.v:85: Cannot find file containing module: 'PLL_BASE'\n PLL_BASE #(\n ^~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 7,208 | module | module ztex_ufm1_15b1 (fxclk_in, reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start, read, write);
input fxclk_in, reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start;
input [7:0] read;
output [7:0] write;
reg [3:0] rd_clk_b, wr_clk_b;
reg wr_start_b1, wr_start_b2, reset_buf;
reg dcm_progclk_buf, dcm_progdata_buf, dcm_progen_buf;
reg [4:0] wr_delay;
reg [671:0] inbuf, inbuf_tmp;
reg [95:0] outbuf;
reg [7:0] read_buf, write_buf;
wire fxclk, clk, dcm_clk, pll_fb, pll_clk0, dcm_locked, pll_reset;
wire [31:0] golden_nonce, nonce2, hash2;
wire [255:0] data1, data2;
wire [127:0] data3;
wire [31:0] target;
assign target = inbuf[671:640];
assign data3 = inbuf[639:512];
assign data2 = inbuf[511:256];
assign data1 = inbuf[255:0];
wire gn_match;
wire loadnonce;
assign loadnonce = 1'b0;
assign hash2 = 32'd0;
hashcore M (.hash_clk(clk), .data1(data1), .data2(data2), .data3(data3), .target(target),
.nonce_msb(4'd0), .nonce_out(nonce2), .golden_nonce_out(golden_nonce),
.golden_nonce_match(gn_match), .loadnonce(loadnonce));
BUFG bufg_fxclk (
.I(fxclk_in),
.O(fxclk)
);
BUFG bufg_clk (
.I(pll_clk0),
.O(clk)
);
DCM_CLKGEN #(
.CLKFX_DIVIDE(6),
.CLKFX_MULTIPLY(20),
.CLKFXDV_DIVIDE(2),
.CLKIN_PERIOD(20.8)
)
dcm0 (
.CLKIN(fxclk),
.CLKFX(dcm_clk),
.FREEZEDCM(1'b0),
.PROGCLK(dcm_progclk_buf),
.PROGDATA(dcm_progdata_buf),
.PROGEN(dcm_progen_buf),
.LOCKED(dcm_locked),
.RST(1'b0)
);
PLL_BASE #(
.BANDWIDTH("LOW"),
.CLKFBOUT_MULT(5),
.CLKOUT0_DIVIDE(32),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLK_FEEDBACK("CLKFBOUT"),
.COMPENSATION("DCM2PLL"),
.DIVCLK_DIVIDE(1),
.REF_JITTER(0.05),
.RESET_ON_LOSS_OF_LOCK("FALSE"),
.CLKIN_PERIOD(6.25)
)
pll0 (
.CLKFBOUT(pll_fb),
.CLKOUT0(pll_clk0),
.CLKFBIN(pll_fb),
.CLKIN(dcm_clk),
.RST(pll_reset)
);
assign write = write_buf;
assign pll_reset = pll_stop | ~dcm_locked;
always @ (posedge clk)
begin
if ( (rd_clk_b[3] == rd_clk_b[2]) && (rd_clk_b[2] == rd_clk_b[1]) && (rd_clk_b[1] != rd_clk_b[0]) )
begin
inbuf_tmp[671:664] <= read_buf;
inbuf_tmp[663:0] <= inbuf_tmp[671:8];
end;
inbuf <= inbuf_tmp;
if ( wr_start_b1 && wr_start_b2 )
begin
wr_delay <= 5'd0;
end else
begin
wr_delay[0] <= 1'b1;
wr_delay[4:1] <= wr_delay[3:0];
end
if ( ! wr_delay[4] )
begin
outbuf <= { hash2, nonce2, golden_nonce };
end else
begin
if ( (wr_clk_b[3] == wr_clk_b[2]) && (wr_clk_b[2] == wr_clk_b[1]) && (wr_clk_b[1] != wr_clk_b[0]) )
outbuf[87:0] <= outbuf[95:8];
end
read_buf <= read;
write_buf <= outbuf[7:0];
rd_clk_b[0] <= rd_clk;
rd_clk_b[3:1] <= rd_clk_b[2:0];
wr_clk_b[0] <= wr_clk;
wr_clk_b[3:1] <= wr_clk_b[2:0];
wr_start_b1 <= wr_start;
wr_start_b2 <= wr_start_b1;
reset_buf <= reset;
end
always @ (posedge fxclk)
begin
dcm_progclk_buf <= dcm_progclk;
dcm_progdata_buf <= dcm_progdata;
dcm_progen_buf <= dcm_progen;
end
endmodule | module ztex_ufm1_15b1 (fxclk_in, reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start, read, write); |
input fxclk_in, reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start;
input [7:0] read;
output [7:0] write;
reg [3:0] rd_clk_b, wr_clk_b;
reg wr_start_b1, wr_start_b2, reset_buf;
reg dcm_progclk_buf, dcm_progdata_buf, dcm_progen_buf;
reg [4:0] wr_delay;
reg [671:0] inbuf, inbuf_tmp;
reg [95:0] outbuf;
reg [7:0] read_buf, write_buf;
wire fxclk, clk, dcm_clk, pll_fb, pll_clk0, dcm_locked, pll_reset;
wire [31:0] golden_nonce, nonce2, hash2;
wire [255:0] data1, data2;
wire [127:0] data3;
wire [31:0] target;
assign target = inbuf[671:640];
assign data3 = inbuf[639:512];
assign data2 = inbuf[511:256];
assign data1 = inbuf[255:0];
wire gn_match;
wire loadnonce;
assign loadnonce = 1'b0;
assign hash2 = 32'd0;
hashcore M (.hash_clk(clk), .data1(data1), .data2(data2), .data3(data3), .target(target),
.nonce_msb(4'd0), .nonce_out(nonce2), .golden_nonce_out(golden_nonce),
.golden_nonce_match(gn_match), .loadnonce(loadnonce));
BUFG bufg_fxclk (
.I(fxclk_in),
.O(fxclk)
);
BUFG bufg_clk (
.I(pll_clk0),
.O(clk)
);
DCM_CLKGEN #(
.CLKFX_DIVIDE(6),
.CLKFX_MULTIPLY(20),
.CLKFXDV_DIVIDE(2),
.CLKIN_PERIOD(20.8)
)
dcm0 (
.CLKIN(fxclk),
.CLKFX(dcm_clk),
.FREEZEDCM(1'b0),
.PROGCLK(dcm_progclk_buf),
.PROGDATA(dcm_progdata_buf),
.PROGEN(dcm_progen_buf),
.LOCKED(dcm_locked),
.RST(1'b0)
);
PLL_BASE #(
.BANDWIDTH("LOW"),
.CLKFBOUT_MULT(5),
.CLKOUT0_DIVIDE(32),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLK_FEEDBACK("CLKFBOUT"),
.COMPENSATION("DCM2PLL"),
.DIVCLK_DIVIDE(1),
.REF_JITTER(0.05),
.RESET_ON_LOSS_OF_LOCK("FALSE"),
.CLKIN_PERIOD(6.25)
)
pll0 (
.CLKFBOUT(pll_fb),
.CLKOUT0(pll_clk0),
.CLKFBIN(pll_fb),
.CLKIN(dcm_clk),
.RST(pll_reset)
);
assign write = write_buf;
assign pll_reset = pll_stop | ~dcm_locked;
always @ (posedge clk)
begin
if ( (rd_clk_b[3] == rd_clk_b[2]) && (rd_clk_b[2] == rd_clk_b[1]) && (rd_clk_b[1] != rd_clk_b[0]) )
begin
inbuf_tmp[671:664] <= read_buf;
inbuf_tmp[663:0] <= inbuf_tmp[671:8];
end;
inbuf <= inbuf_tmp;
if ( wr_start_b1 && wr_start_b2 )
begin
wr_delay <= 5'd0;
end else
begin
wr_delay[0] <= 1'b1;
wr_delay[4:1] <= wr_delay[3:0];
end
if ( ! wr_delay[4] )
begin
outbuf <= { hash2, nonce2, golden_nonce };
end else
begin
if ( (wr_clk_b[3] == wr_clk_b[2]) && (wr_clk_b[2] == wr_clk_b[1]) && (wr_clk_b[1] != wr_clk_b[0]) )
outbuf[87:0] <= outbuf[95:8];
end
read_buf <= read;
write_buf <= outbuf[7:0];
rd_clk_b[0] <= rd_clk;
rd_clk_b[3:1] <= rd_clk_b[2:0];
wr_clk_b[0] <= wr_clk;
wr_clk_b[3:1] <= wr_clk_b[2:0];
wr_start_b1 <= wr_start;
wr_start_b2 <= wr_start_b1;
reset_buf <= reset;
end
always @ (posedge fxclk)
begin
dcm_progclk_buf <= dcm_progclk;
dcm_progdata_buf <= dcm_progdata;
dcm_progen_buf <= dcm_progen;
end
endmodule | 270 |
6,320 | data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v | 11,584,509 | ztex_ufm1_15y1.v | v | 328 | 150 | [] | [] | [] | null | line:26: before: "integer" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:230: Signal definition not found, creating implicitly: \'gn_match\'\n : ... Suggested alternative: \'gn_match_1\'\n assign gn_match = gn_match_1;\n ^~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:68: Cannot find file containing module: \'IBUFG\'\n IBUFG bufg_fxclk (\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/Ztex-1-15y,data/full_repos/permissive/11584509/IBUFG\n data/full_repos/permissive/11584509/experimental/Ztex-1-15y,data/full_repos/permissive/11584509/IBUFG.v\n data/full_repos/permissive/11584509/experimental/Ztex-1-15y,data/full_repos/permissive/11584509/IBUFG.sv\n IBUFG\n IBUFG.v\n IBUFG.sv\n obj_dir/IBUFG\n obj_dir/IBUFG.v\n obj_dir/IBUFG.sv\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:79: Cannot find file containing module: \'BUFGCE\'\n BUFGCE bufg_clk (\n ^~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:86: Cannot find file containing module: \'DCM_CLKGEN\'\n DCM_CLKGEN #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:191: Cannot find file containing module: \'pbkdfengine\'\n pbkdfengine #(.SBITS(SBITS)) P1\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:198: Cannot find file containing module: \'salsaengine\'\n salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:255: Operator ASSIGNDLY expects 608 bits on the Assign RHS, but Assign RHS\'s VARREF \'inbuf_tmp\' generates 640 bits.\n : ... In instance ztex_ufm1_15y1\n inbuf <= inbuf_tmp; \n ^~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n' | 7,216 | module | module ztex_ufm1_15y1 (fxclk_in, reset, select, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start, read, write);
input fxclk_in, select, reset, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start;
input [7:0] read;
output [7:0] write;
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
`ifdef DUALCORE
localparam LOCAL_MINERS = 2;
`else
localparam LOCAL_MINERS = 1;
`endif
localparam ADDRBITS = 12 - clog2(LOCAL_MINERS);
localparam SBITS = 8;
`ifdef DUALCORE
reg phase = 1'b0;
`endif
reg [3:0] rd_clk_b, wr_clk_b;
reg wr_start_b1 = 0, wr_start_b2 = 0, reset_buf = 0, reset_buf_d = 0, clk_reset_buf = 1, pll_stop_buf = 1, select_buf = 0;
reg dcm_progclk_buf, dcm_progdata_buf, dcm_progen_buf;
reg [4:0] wr_delay;
reg [127:0] outbuf;
reg [7:0] read_buf, write_buf;
reg [31:0] golden_nonce_a = 32'd0, golden_nonce_b = 32'd0;
wire fxclk, clk, dcm_clk, pll_fb, pll_clk0, dcm_locked, pll_reset;
wire [2:1] dcm_status;
wire [31:0] golden_nonce_1, hash_1;
wire [31:0] golden_nonce_2, hash_2;
wire [31:0] golden_nonce, nonce_a, hash_a;
wire gn_match_1, gn_match_2;
`define NOPLL
`ifndef SIM
IBUFG bufg_fxclk (
.I(fxclk_in),
.O(fxclk)
);
`ifndef NOPLL
BUFG bufg_clk (
.I(pll_clk0),
.O(clk)
);
`else
BUFGCE bufg_clk (
.I(dcm_clk),
.CE(~pll_reset),
.O(clk)
);
`endif
DCM_CLKGEN #(
.CLKFX_DIVIDE(4),
.CLKFX_MULTIPLY(16),
.CLKFXDV_DIVIDE(4),
.CLKIN_PERIOD(20.8333)
)
dcm0 (
.CLKIN(fxclk),
.CLKFXDV(dcm_clk),
.FREEZEDCM(1'b0),
.PROGCLK(dcm_progclk_buf),
.PROGDATA(dcm_progdata_buf),
.PROGEN(dcm_progen_buf),
.LOCKED(dcm_locked),
.STATUS(dcm_status),
.RST(clk_reset_buf)
);
`ifndef NOPLL
PLL_BASE #(
.BANDWIDTH("LOW"),
.CLKFBOUT_MULT(4),
.CLKOUT0_DIVIDE(4),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLK_FEEDBACK("CLKFBOUT"),
.COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(1),
.REF_JITTER(0.10),
.CLKIN_PERIOD(5.2),
.RESET_ON_LOSS_OF_LOCK("FALSE")
)
pll0 (
.CLKFBOUT(pll_fb),
.CLKOUT0(pll_clk0),
.CLKFBIN(pll_fb),
.CLKIN(dcm_clk),
.RST(pll_reset)
);
`endif
`else
assign clk = fxclk_in;
`endif
assign write = select ? write_buf : 8'bz;
assign pll_reset = pll_stop_buf | ~dcm_locked | clk_reset_buf | dcm_status[2];
`ifdef SIM
`ifdef PROTOCOL80
reg [639:0] inbuf_tmp = {
128'h0000318f7e71441b141fe951b2b0c7df,
256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756,
256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
};
`else
reg [607:0] inbuf_tmp = {
96'h7e71441b141fe951b2b0c7df,
256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756,
256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
};
`endif
`else
`ifdef PROTOCOL80
reg [639:0] inbuf_tmp;
`else
reg [639:0] inbuf_tmp;
`endif
`endif
`ifdef PROTOCOL80
reg [639:0] inbuf;
`else
reg [607:0] inbuf;
`endif
wire [31:0] mod_target = 32'h00007fff;
wire [255:0] data1 = inbuf[255:0];
wire [255:0] data2 = inbuf[511:256];
`ifdef PROTOCOL80
wire [127:0] data3 = inbuf[639:512];
`else
`ifdef SIM
wire [127:0] data3 = { 32'h0000318f, inbuf[607:512] };
`else
wire [127:0] data3 = { 32'd0, inbuf[607:512] };
`endif
`endif
reg loadnonce = 1'b0;
reg loadnonce_d = 1'b0;
wire [31:0] nonce_out_1;
wire salsa_busy_1, salsa_result_1, salsa_reset_1, salsa_start_1, salsa_shift_1;
wire [SBITS-1:0] salsa_din_1;
wire [SBITS-1:0] salsa_dout_1;
pbkdfengine #(.SBITS(SBITS)) P1
(.hash_clk(clk), .pbkdf_clk(clk), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb( 4'd0 ), .nonce_out(nonce_out_1), .golden_nonce_out(golden_nonce_1),
.golden_nonce_match(gn_match_1), .loadnonce(loadnonce_d),
.salsa_din(salsa_din_1), .salsa_dout(salsa_dout_1), .salsa_busy(salsa_busy_1), .salsa_result(salsa_result_1),
.salsa_reset(salsa_reset_1), .salsa_start(salsa_start_1), .salsa_shift(salsa_shift_1), .hash_out(hash_1));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1
(.hash_clk(clk), .reset(salsa_reset_1), .din(salsa_din_1), .dout(salsa_dout_1),
.shift(salsa_shift_1), .start(salsa_start_1), .busy(salsa_busy_1), .result(salsa_result_1) );
`ifdef DUALCORE
wire [31:0] nonce_out_2;
wire salsa_busy_2, salsa_result_2, salsa_reset_2, salsa_start_2, salsa_shift_2;
wire [SBITS-1:0] salsa_din_2;
wire [SBITS-1:0] salsa_dout_2;
pbkdfengine #(.SBITS(SBITS)) P2
(.hash_clk(clk), .pbkdf_clk(clk), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb( 4'd8 ), .nonce_out(nonce_out_2), .golden_nonce_out(golden_nonce_2),
.golden_nonce_match(gn_match_2), .loadnonce(loadnonce_d),
.salsa_din(salsa_din_2), .salsa_dout(salsa_dout_2), .salsa_busy(salsa_busy_2), .salsa_result(salsa_result_2),
.salsa_reset(salsa_reset_2), .salsa_start(salsa_start_2), .salsa_shift(salsa_shift_2), .hash_out(hash_2));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S2
(.hash_clk(clk), .reset(salsa_reset_2), .din(salsa_din_2), .dout(salsa_dout_2),
.shift(salsa_shift_2), .start(salsa_start_2), .busy(salsa_busy_2), .result(salsa_result_2) );
assign nonce_a = phase ? nonce_out_2 : nonce_out_1;
assign hash_a = phase ? hash_2 : hash_1;
assign gn_match = gn_match_1 | gn_match_2;
assign golden_nonce = gn_match_1 ? golden_nonce_1 : golden_nonce_2;
`else
assign nonce_a = nonce_out_1;
assign hash_a = hash_1;
assign gn_match = gn_match_1;
assign golden_nonce = golden_nonce_1;
`endif
always @ (posedge clk)
begin
loadnonce <= 1'b0;
loadnonce_d <= loadnonce;
if ( (rd_clk_b[3] == rd_clk_b[2]) && (rd_clk_b[2] == rd_clk_b[1]) && (rd_clk_b[1] != rd_clk_b[0]) && select_buf )
begin
`ifdef PROTOCOL80
inbuf_tmp[639:632] <= read_buf;
inbuf_tmp[631:0] <= inbuf_tmp[639:8];
`else
inbuf_tmp[607:600] <= read_buf;
inbuf_tmp[599:0] <= inbuf_tmp[607:8];
`endif
loadnonce <= 1'b1;
end
inbuf <= inbuf_tmp;
if ( wr_start_b1 && wr_start_b2 )
begin
wr_delay <= 5'd0;
end else
begin
wr_delay[0] <= 1'b1;
wr_delay[4:1] <= wr_delay[3:0];
end
if ( ! wr_delay[4] )
begin
outbuf <= { golden_nonce_b, hash_a, nonce_a, golden_nonce_a };
end else
begin
if ( (wr_clk_b[3] == wr_clk_b[2]) && (wr_clk_b[2] == wr_clk_b[1]) && (wr_clk_b[1] != wr_clk_b[0]) )
outbuf[119:0] <= outbuf[127:8];
end
if ( reset_buf | loadnonce )
begin
golden_nonce_a <= 32'd0;
golden_nonce_b <= 32'd0;
end else if ( gn_match )
begin
golden_nonce_b <= golden_nonce_a;
golden_nonce_a <= golden_nonce;
end
read_buf <= read;
write_buf <= outbuf[7:0];
rd_clk_b[0] <= rd_clk;
rd_clk_b[3:1] <= rd_clk_b[2:0];
wr_clk_b[0] <= wr_clk;
wr_clk_b[3:1] <= wr_clk_b[2:0];
wr_start_b1 <= wr_start;
wr_start_b2 <= wr_start_b1;
select_buf <= select;
if ( select )
begin
reset_buf <= reset;
end
reset_buf_d <= reset_buf;
if (reset_buf_d & ~reset_buf)
begin
`ifdef DUALCORE
phase <= ~phase;
`endif
end
end
always @ (posedge fxclk)
begin
dcm_progclk_buf <= dcm_progclk;
dcm_progdata_buf <= dcm_progdata;
dcm_progen_buf <= dcm_progen & select;
if ( select )
begin
clk_reset_buf <= clk_reset;
pll_stop_buf <= pll_stop;
end
end
endmodule | module ztex_ufm1_15y1 (fxclk_in, reset, select, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start, read, write); |
input fxclk_in, select, reset, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start;
input [7:0] read;
output [7:0] write;
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
`ifdef DUALCORE
localparam LOCAL_MINERS = 2;
`else
localparam LOCAL_MINERS = 1;
`endif
localparam ADDRBITS = 12 - clog2(LOCAL_MINERS);
localparam SBITS = 8;
`ifdef DUALCORE
reg phase = 1'b0;
`endif
reg [3:0] rd_clk_b, wr_clk_b;
reg wr_start_b1 = 0, wr_start_b2 = 0, reset_buf = 0, reset_buf_d = 0, clk_reset_buf = 1, pll_stop_buf = 1, select_buf = 0;
reg dcm_progclk_buf, dcm_progdata_buf, dcm_progen_buf;
reg [4:0] wr_delay;
reg [127:0] outbuf;
reg [7:0] read_buf, write_buf;
reg [31:0] golden_nonce_a = 32'd0, golden_nonce_b = 32'd0;
wire fxclk, clk, dcm_clk, pll_fb, pll_clk0, dcm_locked, pll_reset;
wire [2:1] dcm_status;
wire [31:0] golden_nonce_1, hash_1;
wire [31:0] golden_nonce_2, hash_2;
wire [31:0] golden_nonce, nonce_a, hash_a;
wire gn_match_1, gn_match_2;
`define NOPLL
`ifndef SIM
IBUFG bufg_fxclk (
.I(fxclk_in),
.O(fxclk)
);
`ifndef NOPLL
BUFG bufg_clk (
.I(pll_clk0),
.O(clk)
);
`else
BUFGCE bufg_clk (
.I(dcm_clk),
.CE(~pll_reset),
.O(clk)
);
`endif
DCM_CLKGEN #(
.CLKFX_DIVIDE(4),
.CLKFX_MULTIPLY(16),
.CLKFXDV_DIVIDE(4),
.CLKIN_PERIOD(20.8333)
)
dcm0 (
.CLKIN(fxclk),
.CLKFXDV(dcm_clk),
.FREEZEDCM(1'b0),
.PROGCLK(dcm_progclk_buf),
.PROGDATA(dcm_progdata_buf),
.PROGEN(dcm_progen_buf),
.LOCKED(dcm_locked),
.STATUS(dcm_status),
.RST(clk_reset_buf)
);
`ifndef NOPLL
PLL_BASE #(
.BANDWIDTH("LOW"),
.CLKFBOUT_MULT(4),
.CLKOUT0_DIVIDE(4),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLK_FEEDBACK("CLKFBOUT"),
.COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(1),
.REF_JITTER(0.10),
.CLKIN_PERIOD(5.2),
.RESET_ON_LOSS_OF_LOCK("FALSE")
)
pll0 (
.CLKFBOUT(pll_fb),
.CLKOUT0(pll_clk0),
.CLKFBIN(pll_fb),
.CLKIN(dcm_clk),
.RST(pll_reset)
);
`endif
`else
assign clk = fxclk_in;
`endif
assign write = select ? write_buf : 8'bz;
assign pll_reset = pll_stop_buf | ~dcm_locked | clk_reset_buf | dcm_status[2];
`ifdef SIM
`ifdef PROTOCOL80
reg [639:0] inbuf_tmp = {
128'h0000318f7e71441b141fe951b2b0c7df,
256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756,
256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
};
`else
reg [607:0] inbuf_tmp = {
96'h7e71441b141fe951b2b0c7df,
256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756,
256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
};
`endif
`else
`ifdef PROTOCOL80
reg [639:0] inbuf_tmp;
`else
reg [639:0] inbuf_tmp;
`endif
`endif
`ifdef PROTOCOL80
reg [639:0] inbuf;
`else
reg [607:0] inbuf;
`endif
wire [31:0] mod_target = 32'h00007fff;
wire [255:0] data1 = inbuf[255:0];
wire [255:0] data2 = inbuf[511:256];
`ifdef PROTOCOL80
wire [127:0] data3 = inbuf[639:512];
`else
`ifdef SIM
wire [127:0] data3 = { 32'h0000318f, inbuf[607:512] };
`else
wire [127:0] data3 = { 32'd0, inbuf[607:512] };
`endif
`endif
reg loadnonce = 1'b0;
reg loadnonce_d = 1'b0;
wire [31:0] nonce_out_1;
wire salsa_busy_1, salsa_result_1, salsa_reset_1, salsa_start_1, salsa_shift_1;
wire [SBITS-1:0] salsa_din_1;
wire [SBITS-1:0] salsa_dout_1;
pbkdfengine #(.SBITS(SBITS)) P1
(.hash_clk(clk), .pbkdf_clk(clk), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb( 4'd0 ), .nonce_out(nonce_out_1), .golden_nonce_out(golden_nonce_1),
.golden_nonce_match(gn_match_1), .loadnonce(loadnonce_d),
.salsa_din(salsa_din_1), .salsa_dout(salsa_dout_1), .salsa_busy(salsa_busy_1), .salsa_result(salsa_result_1),
.salsa_reset(salsa_reset_1), .salsa_start(salsa_start_1), .salsa_shift(salsa_shift_1), .hash_out(hash_1));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1
(.hash_clk(clk), .reset(salsa_reset_1), .din(salsa_din_1), .dout(salsa_dout_1),
.shift(salsa_shift_1), .start(salsa_start_1), .busy(salsa_busy_1), .result(salsa_result_1) );
`ifdef DUALCORE
wire [31:0] nonce_out_2;
wire salsa_busy_2, salsa_result_2, salsa_reset_2, salsa_start_2, salsa_shift_2;
wire [SBITS-1:0] salsa_din_2;
wire [SBITS-1:0] salsa_dout_2;
pbkdfengine #(.SBITS(SBITS)) P2
(.hash_clk(clk), .pbkdf_clk(clk), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb( 4'd8 ), .nonce_out(nonce_out_2), .golden_nonce_out(golden_nonce_2),
.golden_nonce_match(gn_match_2), .loadnonce(loadnonce_d),
.salsa_din(salsa_din_2), .salsa_dout(salsa_dout_2), .salsa_busy(salsa_busy_2), .salsa_result(salsa_result_2),
.salsa_reset(salsa_reset_2), .salsa_start(salsa_start_2), .salsa_shift(salsa_shift_2), .hash_out(hash_2));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S2
(.hash_clk(clk), .reset(salsa_reset_2), .din(salsa_din_2), .dout(salsa_dout_2),
.shift(salsa_shift_2), .start(salsa_start_2), .busy(salsa_busy_2), .result(salsa_result_2) );
assign nonce_a = phase ? nonce_out_2 : nonce_out_1;
assign hash_a = phase ? hash_2 : hash_1;
assign gn_match = gn_match_1 | gn_match_2;
assign golden_nonce = gn_match_1 ? golden_nonce_1 : golden_nonce_2;
`else
assign nonce_a = nonce_out_1;
assign hash_a = hash_1;
assign gn_match = gn_match_1;
assign golden_nonce = golden_nonce_1;
`endif
always @ (posedge clk)
begin
loadnonce <= 1'b0;
loadnonce_d <= loadnonce;
if ( (rd_clk_b[3] == rd_clk_b[2]) && (rd_clk_b[2] == rd_clk_b[1]) && (rd_clk_b[1] != rd_clk_b[0]) && select_buf )
begin
`ifdef PROTOCOL80
inbuf_tmp[639:632] <= read_buf;
inbuf_tmp[631:0] <= inbuf_tmp[639:8];
`else
inbuf_tmp[607:600] <= read_buf;
inbuf_tmp[599:0] <= inbuf_tmp[607:8];
`endif
loadnonce <= 1'b1;
end
inbuf <= inbuf_tmp;
if ( wr_start_b1 && wr_start_b2 )
begin
wr_delay <= 5'd0;
end else
begin
wr_delay[0] <= 1'b1;
wr_delay[4:1] <= wr_delay[3:0];
end
if ( ! wr_delay[4] )
begin
outbuf <= { golden_nonce_b, hash_a, nonce_a, golden_nonce_a };
end else
begin
if ( (wr_clk_b[3] == wr_clk_b[2]) && (wr_clk_b[2] == wr_clk_b[1]) && (wr_clk_b[1] != wr_clk_b[0]) )
outbuf[119:0] <= outbuf[127:8];
end
if ( reset_buf | loadnonce )
begin
golden_nonce_a <= 32'd0;
golden_nonce_b <= 32'd0;
end else if ( gn_match )
begin
golden_nonce_b <= golden_nonce_a;
golden_nonce_a <= golden_nonce;
end
read_buf <= read;
write_buf <= outbuf[7:0];
rd_clk_b[0] <= rd_clk;
rd_clk_b[3:1] <= rd_clk_b[2:0];
wr_clk_b[0] <= wr_clk;
wr_clk_b[3:1] <= wr_clk_b[2:0];
wr_start_b1 <= wr_start;
wr_start_b2 <= wr_start_b1;
select_buf <= select;
if ( select )
begin
reset_buf <= reset;
end
reset_buf_d <= reset_buf;
if (reset_buf_d & ~reset_buf)
begin
`ifdef DUALCORE
phase <= ~phase;
`endif
end
end
always @ (posedge fxclk)
begin
dcm_progclk_buf <= dcm_progclk;
dcm_progdata_buf <= dcm_progdata;
dcm_progen_buf <= dcm_progen & select;
if ( select )
begin
clk_reset_buf <= clk_reset;
pll_stop_buf <= pll_stop;
end
end
endmodule | 270 |
6,321 | data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v | 11,584,509 | ztex_ufm1_15y1.v | v | 328 | 150 | [] | [] | [] | null | line:26: before: "integer" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:230: Signal definition not found, creating implicitly: \'gn_match\'\n : ... Suggested alternative: \'gn_match_1\'\n assign gn_match = gn_match_1;\n ^~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:68: Cannot find file containing module: \'IBUFG\'\n IBUFG bufg_fxclk (\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/experimental/Ztex-1-15y,data/full_repos/permissive/11584509/IBUFG\n data/full_repos/permissive/11584509/experimental/Ztex-1-15y,data/full_repos/permissive/11584509/IBUFG.v\n data/full_repos/permissive/11584509/experimental/Ztex-1-15y,data/full_repos/permissive/11584509/IBUFG.sv\n IBUFG\n IBUFG.v\n IBUFG.sv\n obj_dir/IBUFG\n obj_dir/IBUFG.v\n obj_dir/IBUFG.sv\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:79: Cannot find file containing module: \'BUFGCE\'\n BUFGCE bufg_clk (\n ^~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:86: Cannot find file containing module: \'DCM_CLKGEN\'\n DCM_CLKGEN #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:191: Cannot find file containing module: \'pbkdfengine\'\n pbkdfengine #(.SBITS(SBITS)) P1\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:198: Cannot find file containing module: \'salsaengine\'\n salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:255: Operator ASSIGNDLY expects 608 bits on the Assign RHS, but Assign RHS\'s VARREF \'inbuf_tmp\' generates 640 bits.\n : ... In instance ztex_ufm1_15y1\n inbuf <= inbuf_tmp; \n ^~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n' | 7,216 | function | function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction | function integer clog2; |
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction | 270 |
6,325 | data/full_repos/permissive/11584509/ICARUS-LX150/serial.v | 11,584,509 | serial.v | v | 151 | 185 | [] | [] | [] | [(7, 90), (92, 150)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/11584509/ICARUS-LX150/serial.v:92: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'serial_receive\'\nmodule serial_receive # (\n ^~~~~~~~~~~~~~\n : ... Top module \'serial_transmit\'\nmodule serial_transmit # (\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/ICARUS-LX150/serial.v:148: Cannot find file containing module: \'uart_transmitter\'\n uart_transmitter #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) utx (.clk(clk), .uart_tx(TxD), .rx_new_byte(TxD_start), .rx_byte(out_byte), .tx_ready(TxD_ready));\n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/ICARUS-LX150,data/full_repos/permissive/11584509/uart_transmitter\n data/full_repos/permissive/11584509/ICARUS-LX150,data/full_repos/permissive/11584509/uart_transmitter.v\n data/full_repos/permissive/11584509/ICARUS-LX150,data/full_repos/permissive/11584509/uart_transmitter.sv\n uart_transmitter\n uart_transmitter.v\n uart_transmitter.sv\n obj_dir/uart_transmitter\n obj_dir/uart_transmitter.v\n obj_dir/uart_transmitter.sv\n%Error: data/full_repos/permissive/11584509/ICARUS-LX150/serial.v:26: Cannot find file containing module: \'uart_receiver\'\n uart_receiver #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) urx (.clk(clk), .uart_rx(RxD), .tx_new_byte(RxD_data_ready), .tx_byte(RxD_data));\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 7,224 | module | module serial_receive # (
parameter baud_rate = 115_200,
parameter comm_clk_frequency = 100_000_000 )
( clk, RxD, data1, data2, data3, target, rx_done );
input clk;
input RxD;
wire RxD_data_ready;
wire [7:0] RxD_data;
`ifdef CONFIG_SERIAL_TIMEOUT
parameter SERIAL_TIMEOUT = `CONFIG_SERIAL_TIMEOUT;
`else
parameter SERIAL_TIMEOUT = 24'h800000;
`endif
uart_receiver #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) urx (.clk(clk), .uart_rx(RxD), .tx_new_byte(RxD_data_ready), .tx_byte(RxD_data));
output [255:0] data1;
output [255:0] data2;
output [127:0] data3;
output [31:0] target;
output reg rx_done = 1'b0;
reg [671:0] input_buffer = 0;
reg [671:0] input_copy = 0;
reg [6:0] demux_state = 7'b0000000;
reg [23:0] timer = 0;
`ifdef SIM
assign target = input_copy[671:640];
assign data1 = 256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
assign data2 = 256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756;
assign data3 = 128'h0000318f7e71441b141fe951b2b0c7df;
`else
assign target = input_copy[671:640];
assign data3 = input_copy[639:512];
assign data2 = input_copy[511:256];
assign data1 = input_copy[255:0];
`endif
always @(posedge clk)
case (demux_state)
7'd84:
begin
rx_done <= 1;
input_copy <= input_buffer;
demux_state <= 0;
end
default:
begin
rx_done <= 0;
if(RxD_data_ready)
begin
input_buffer <= input_buffer << 8;
input_buffer[7:0] <= RxD_data;
demux_state <= demux_state + 1;
timer <= 0;
end
else
begin
timer <= timer + 1;
if (timer == SERIAL_TIMEOUT)
demux_state <= 0;
end
end
endcase
endmodule | module serial_receive # (
parameter baud_rate = 115_200,
parameter comm_clk_frequency = 100_000_000 )
( clk, RxD, data1, data2, data3, target, rx_done ); |
input clk;
input RxD;
wire RxD_data_ready;
wire [7:0] RxD_data;
`ifdef CONFIG_SERIAL_TIMEOUT
parameter SERIAL_TIMEOUT = `CONFIG_SERIAL_TIMEOUT;
`else
parameter SERIAL_TIMEOUT = 24'h800000;
`endif
uart_receiver #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) urx (.clk(clk), .uart_rx(RxD), .tx_new_byte(RxD_data_ready), .tx_byte(RxD_data));
output [255:0] data1;
output [255:0] data2;
output [127:0] data3;
output [31:0] target;
output reg rx_done = 1'b0;
reg [671:0] input_buffer = 0;
reg [671:0] input_copy = 0;
reg [6:0] demux_state = 7'b0000000;
reg [23:0] timer = 0;
`ifdef SIM
assign target = input_copy[671:640];
assign data1 = 256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
assign data2 = 256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756;
assign data3 = 128'h0000318f7e71441b141fe951b2b0c7df;
`else
assign target = input_copy[671:640];
assign data3 = input_copy[639:512];
assign data2 = input_copy[511:256];
assign data1 = input_copy[255:0];
`endif
always @(posedge clk)
case (demux_state)
7'd84:
begin
rx_done <= 1;
input_copy <= input_buffer;
demux_state <= 0;
end
default:
begin
rx_done <= 0;
if(RxD_data_ready)
begin
input_buffer <= input_buffer << 8;
input_buffer[7:0] <= RxD_data;
demux_state <= demux_state + 1;
timer <= 0;
end
else
begin
timer <= timer + 1;
if (timer == SERIAL_TIMEOUT)
demux_state <= 0;
end
end
endcase
endmodule | 270 |
6,326 | data/full_repos/permissive/11584509/ICARUS-LX150/serial.v | 11,584,509 | serial.v | v | 151 | 185 | [] | [] | [] | [(7, 90), (92, 150)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/11584509/ICARUS-LX150/serial.v:92: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'serial_receive\'\nmodule serial_receive # (\n ^~~~~~~~~~~~~~\n : ... Top module \'serial_transmit\'\nmodule serial_transmit # (\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/ICARUS-LX150/serial.v:148: Cannot find file containing module: \'uart_transmitter\'\n uart_transmitter #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) utx (.clk(clk), .uart_tx(TxD), .rx_new_byte(TxD_start), .rx_byte(out_byte), .tx_ready(TxD_ready));\n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/ICARUS-LX150,data/full_repos/permissive/11584509/uart_transmitter\n data/full_repos/permissive/11584509/ICARUS-LX150,data/full_repos/permissive/11584509/uart_transmitter.v\n data/full_repos/permissive/11584509/ICARUS-LX150,data/full_repos/permissive/11584509/uart_transmitter.sv\n uart_transmitter\n uart_transmitter.v\n uart_transmitter.sv\n obj_dir/uart_transmitter\n obj_dir/uart_transmitter.v\n obj_dir/uart_transmitter.sv\n%Error: data/full_repos/permissive/11584509/ICARUS-LX150/serial.v:26: Cannot find file containing module: \'uart_receiver\'\n uart_receiver #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) urx (.clk(clk), .uart_rx(RxD), .tx_new_byte(RxD_data_ready), .tx_byte(RxD_data));\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 7,224 | module | module serial_transmit # (
parameter baud_rate = 115_200,
parameter comm_clk_frequency = 100_000_000 )
(clk, TxD, busy, send, word);
wire TxD_start;
wire TxD_ready;
reg [7:0] out_byte = 0;
reg serial_start = 0;
reg [3:0] mux_state = 4'b0000;
assign TxD_start = serial_start;
input clk;
output TxD;
input [31:0] word;
input send;
output busy;
reg [31:0] word_copy = 0;
assign busy = (|mux_state);
always @(posedge clk)
begin
if (!busy && send)
begin
mux_state <= 4'b1000;
word_copy <= word;
end
else if (mux_state[3] && ~mux_state[0] && TxD_ready)
begin
serial_start <= 1;
mux_state <= mux_state + 1;
out_byte <= word_copy[31:24];
word_copy <= (word_copy << 8);
end
else if (mux_state[3] && mux_state[0])
begin
serial_start <= 0;
if (TxD_ready) mux_state <= mux_state + 1;
end
end
uart_transmitter #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) utx (.clk(clk), .uart_tx(TxD), .rx_new_byte(TxD_start), .rx_byte(out_byte), .tx_ready(TxD_ready));
endmodule | module serial_transmit # (
parameter baud_rate = 115_200,
parameter comm_clk_frequency = 100_000_000 )
(clk, TxD, busy, send, word); |
wire TxD_start;
wire TxD_ready;
reg [7:0] out_byte = 0;
reg serial_start = 0;
reg [3:0] mux_state = 4'b0000;
assign TxD_start = serial_start;
input clk;
output TxD;
input [31:0] word;
input send;
output busy;
reg [31:0] word_copy = 0;
assign busy = (|mux_state);
always @(posedge clk)
begin
if (!busy && send)
begin
mux_state <= 4'b1000;
word_copy <= word;
end
else if (mux_state[3] && ~mux_state[0] && TxD_ready)
begin
serial_start <= 1;
mux_state <= mux_state + 1;
out_byte <= word_copy[31:24];
word_copy <= (word_copy << 8);
end
else if (mux_state[3] && mux_state[0])
begin
serial_start <= 0;
if (TxD_ready) mux_state <= mux_state + 1;
end
end
uart_transmitter #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) utx (.clk(clk), .uart_tx(TxD), .rx_new_byte(TxD_start), .rx_byte(out_byte), .tx_ready(TxD_ready));
endmodule | 270 |
6,331 | data/full_repos/permissive/11584509/source/hashcore.v | 11,584,509 | hashcore.v | v | 733 | 153 | [] | [] | [] | [(25, 733)] | null | null | 1: b'%Error: data/full_repos/permissive/11584509/source/hashcore.v:86: Cannot find file containing module: \'sha256_transform\'\n sha256_transform # (.LOOP(64)) sha256_blk (\n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/source,data/full_repos/permissive/11584509/sha256_transform\n data/full_repos/permissive/11584509/source,data/full_repos/permissive/11584509/sha256_transform.v\n data/full_repos/permissive/11584509/source,data/full_repos/permissive/11584509/sha256_transform.sv\n sha256_transform\n sha256_transform.v\n sha256_transform.sv\n obj_dir/sha256_transform\n obj_dir/sha256_transform.v\n obj_dir/sha256_transform.sv\n%Warning-WIDTH: data/full_repos/permissive/11584509/source/hashcore.v:487: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance hashcore\n reg [5:0] mcount = 5\'d0; \n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/source/hashcore.v:536: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram1_blk (ram_addr, ram_clk, ram1_din, ram_wren, ram1_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/source/hashcore.v:537: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram2_blk (ram_addr, ram_clk, ram2_din, ram_wren, ram2_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/source/hashcore.v:538: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram3_blk (ram_addr, ram_clk, ram3_din, ram_wren, ram3_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/source/hashcore.v:539: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram4_blk (ram_addr, ram_clk, ram4_din, ram_wren, ram4_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/source/hashcore.v:545: Cannot find file containing module: \'salsa\'\n salsa salsa_blk (hash_clk, mixfeedback, X0, X1, Xmix);\n ^~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n' | 7,235 | module | module hashcore (hash_clk, data1, data2, data3, target, nonce_msb, nonce_out, golden_nonce_out, golden_nonce_match, loadnonce);
input hash_clk;
input [255:0] data1;
input [255:0] data2;
input [127:0] data3;
input [31:0] target;
input [3:0] nonce_msb;
output [31:0] nonce_out;
output [31:0] golden_nonce_out;
output golden_nonce_match;
input loadnonce;
reg poweron_reset = 1'b1;
reg reset = 1'b1;
always @ (posedge hash_clk)
begin
poweron_reset <= 1'b0;
reset <= poweron_reset;
end
`ifndef ICARUS
reg [31:0] nonce_prevous_load = 32'hffffffff;
`endif
`ifndef NOMULTICORE
reg [27:0] nonce_cnt = 28'd0;
wire [31:0] nonce;
assign nonce = { nonce_msb, nonce_cnt };
`else
reg [31:0] nonce = 32'd0;
`endif
assign nonce_out = nonce;
reg [31:0] nonce_1 = 32'd0;
reg [31:0] nonce_2 = 32'd0;
reg [31:0] golden_nonce = 32'd0;
assign golden_nonce_out = golden_nonce;
reg golden_nonce_match = 1'b0;
reg [255:0] rx_state;
reg [511:0] rx_input;
wire [255:0] tx_hash;
reg [255:0] khash = 256'd0;
reg [255:0] ihash = 256'd0;
reg [255:0] ohash = 256'd0;
`ifdef SIM
reg [255:0] final_hash = 256'd0;
`endif
reg [31:0] blockcnt = 32'd0;
reg [1023:0] Xbuf = 1024'd0;
reg [1023:0] MixOut;
wire [1023:0] MixOutRewire;
reg [5:0] cnt = 6'd0;
wire feedback;
assign feedback = (cnt != 6'b0);
sha256_transform # (.LOOP(64)) sha256_blk (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(rx_state),
.rx_input(rx_input),
.tx_hash(tx_hash)
);
reg SMixInRdy_state = 1'b0;
reg SMixOutRdy_state = 1'b0;
wire SMixInRdy;
wire SMixOutRdy;
reg Set_SMixInRdy = 1'b0;
reg Clr_SMixInRdy = 1'b0;
reg Set_SMixOutRdy = 1'b0;
reg Clr_SMixOutRdy = 1'b0;
always @ (posedge hash_clk)
begin
if (Set_SMixInRdy)
SMixInRdy_state <= 1'b1;
if (Clr_SMixInRdy)
SMixInRdy_state <= 1'b0;
if (Set_SMixOutRdy)
SMixOutRdy_state <= 1'b1;
if (Clr_SMixOutRdy)
SMixOutRdy_state <= 1'b0;
end
assign SMixInRdy = Clr_SMixInRdy ? 1'b0 : Set_SMixInRdy ? 1'b1 : SMixInRdy_state;
assign SMixOutRdy = Clr_SMixOutRdy ? 1'b0 : Set_SMixOutRdy ? 1'b1 : SMixOutRdy_state;
parameter S_IDLE=0,
S_H1= 1, S_H2= 2, S_H3= 3, S_H4= 4, S_H5= 5, S_H6= 6,
S_I1= 7, S_I2= 8, S_I3= 9, S_I4=10, S_I5=11, S_I6=12,
S_O1=13, S_O2=14, S_O3=15,
S_B1=16, S_B2=17, S_B3=18, S_B4=19, S_B5=20, S_B6=21,
S_XX=22,
S_R1=23, S_R2=24, S_R3=25, S_R4=26, S_R5=27, S_R6=28,
S_R7=29, S_R8=30, S_R9=31, S_R10=32, S_R11=33, S_R12=34,
S_R13=35, S_R14=36, S_R15=37, S_R16=38, S_R17=39, S_R18=40;
reg [5:0] state = S_IDLE;
reg mode = 0;
always @ (posedge hash_clk)
begin
Set_SMixInRdy <= 1'b0;
Clr_SMixOutRdy <= 1'b0;
golden_nonce_match <= 1'b0;
if (reset == 1'b1)
state <= S_IDLE;
else
begin
case (state)
S_IDLE: begin
if (SMixOutRdy ||
!SMixInRdy)
begin
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { data2, data1 };
blockcnt <= 32'd1;
cnt <= 6'd0;
if (SMixOutRdy)
mode <= 1'b1;
else
mode <= 1'b0;
state <= S_H1;
end
end
S_H1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H2;
end
end
S_H2: begin
state <= S_H3;
end
S_H3: begin
rx_state <= tx_hash;
rx_input <= { 384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000,
mode ? nonce_2 : nonce, data3[95:0] };
state <= S_H4;
end
S_H4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H5;
end
end
S_H5: begin
state <= S_H6;
end
S_H6: begin
khash <= tx_hash;
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h3636363636363636363636363636363636363636363636363636363636363636 ,
tx_hash ^ 256'h3636363636363636363636363636363636363636363636363636363636363636 };
cnt <= 6'd0;
if (mode)
state <= S_R1;
else
state <= S_I1;
end
S_I1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I2;
end
end
S_I2: begin
state <= S_I3;
end
S_I3: begin
rx_state <= tx_hash;
rx_input <= { data2, data1 };
state <= S_I4;
end
S_I4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I5;
end
end
S_I5: begin
state <= S_I6;
end
S_I6: begin
ihash <= tx_hash;
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_O1;
end
S_O1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_O2;
end
end
S_O2: begin
state <= S_O3;
end
S_O3: begin
ohash <= tx_hash;
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
blockcnt, nonce, data3[95:0] };
blockcnt <= blockcnt + 1;
cnt <= 6'd0;
state <= S_B1;
end
S_B1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B2;
end
end
S_B2: begin
state <= S_B3;
end
S_B3: begin
rx_state <= ohash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, tx_hash };
state <= S_B4;
end
S_B4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B5;
end
end
S_B5: begin
state <= S_B6;
end
S_B6: begin
Xbuf[255:0] <= Xbuf[511:256];
Xbuf[511:256] <= Xbuf[767:512];
Xbuf[767:512] <= Xbuf[1023:768];
Xbuf[1023:768] <= tx_hash;
if (blockcnt == 5)
state <= S_XX;
else begin
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
blockcnt, nonce, data3[95:0] };
blockcnt <= blockcnt + 1;
cnt <= 6'd0;
state <= S_B1;
end
end
S_XX: begin
Set_SMixInRdy <= 1;
state <= S_IDLE;
end
S_R1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R2;
end
end
S_R2: begin
state <= S_R3;
end
S_R3: begin
rx_state <= tx_hash;
rx_input <= MixOutRewire[511:0];
state <= S_R4;
end
S_R4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R5;
end
end
S_R5: begin
state <= S_R6;
end
S_R6: begin
rx_state <= tx_hash;
rx_input <= MixOutRewire[1023:512];
state <= S_R7;
end
S_R7: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R8;
end
end
S_R8: begin
state <= S_R9;
end
S_R9: begin
rx_state <= tx_hash;
rx_input <= 512'h00000620000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000001;
state <= S_R10;
end
S_R10: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R11;
end
end
S_R11: begin
state <= S_R12;
end
S_R12: begin
ihash <= tx_hash;
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_R13;
end
S_R13: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R14;
end
end
S_R14: begin
state <= S_R15;
end
S_R15: begin
rx_state <= tx_hash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, ihash };
state <= S_R16;
end
S_R16: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R17;
end
end
S_R17: begin
state <= S_R18;
end
S_R18: begin
`ifdef SIM
final_hash <= tx_hash;
`endif
if ( { tx_hash[231:224], tx_hash[239:232], tx_hash[247:240], tx_hash[255:248] } < target)
begin
golden_nonce <= nonce_2;
golden_nonce_match <= 1'b1;
end
state <= S_IDLE;
mode <= 0;
Clr_SMixOutRdy <= 1'b1;
end
endcase
end
end
wire [1023:0] X;
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] tmp;
assign tmp = Xbuf[`IDX(i)];
assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] };
wire [31:0] mix;
assign mix = MixOut[`IDX(i)];
assign MixOutRewire[`IDX(i)] = { mix[7:0], mix[15:8], mix[23:16], mix[31:24] };
end
endgenerate
parameter R_IDLE=0, R_WRITE=1, R_MIX=2, R_INT=3;
reg [1:0] mstate = R_IDLE;
reg [10:0] cycle = 11'd0;
reg [5:0] mcount = 5'd0;
reg doneROM = 1'd0;
reg mixfeedback = 1'b0;
reg addrsourceMix = 1'b0;
reg [511:0] X0;
reg [511:0] X1;
`ifdef HALFRAM
reg [511:0] X0Save;
reg [511:0] X1Save;
reg oddAddr = 1'b0;
`endif
wire [511:0] Xmix;
reg [9:0] writeaddr = 10'd0;
`ifdef HALFRAM
parameter ADDRBITS = 9;
`else
parameter ADDRBITS = 10;
`endif
wire [ADDRBITS-1:0]ram_addr;
wire [255:0]ram1_din;
wire [255:0]ram1_dout;
wire [255:0]ram2_din;
wire [255:0]ram2_dout;
wire [255:0]ram3_din;
wire [255:0]ram3_dout;
wire [255:0]ram4_din;
wire [255:0]ram4_dout;
wire [1023:0]ramout;
reg ram_wren;
wire ram_clk;
assign ram_clk = hash_clk;
`ifdef HALFRAM
assign ram_addr = addrsourceMix ? Xmix[9:1] : writeaddr[9:1];
`else
assign ram_addr = addrsourceMix ? Xmix[9:0] : writeaddr;
`endif
ram # (.ADDRBITS(ADDRBITS)) ram1_blk (ram_addr, ram_clk, ram1_din, ram_wren, ram1_dout);
ram # (.ADDRBITS(ADDRBITS)) ram2_blk (ram_addr, ram_clk, ram2_din, ram_wren, ram2_dout);
ram # (.ADDRBITS(ADDRBITS)) ram3_blk (ram_addr, ram_clk, ram3_din, ram_wren, ram3_dout);
ram # (.ADDRBITS(ADDRBITS)) ram4_blk (ram_addr, ram_clk, ram4_din, ram_wren, ram4_dout);
assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout };
assign { ram4_din, ram3_din, ram2_din, ram1_din } = { X1, X0} ;
salsa salsa_blk (hash_clk, mixfeedback, X0, X1, Xmix);
always @ (posedge hash_clk)
begin
Set_SMixOutRdy <= 1'b0;
Clr_SMixInRdy <= 1'b0;
`ifdef HALFRAM
oddAddr <= Xmix[0];
`endif
`ifdef ICARUS
if (loadnonce)
`else
if (loadnonce || (nonce_prevous_load != data3[127:96]))
`endif
begin
`ifdef NOMULTICORE
nonce <= data3[127:96];
`else
nonce_cnt <= data3[123:96];
`endif
`ifndef ICARUS
nonce_prevous_load <= data3[127:96];
`endif
end
if (reset == 1'b1)
mstate <= R_IDLE;
else
begin
case (mstate)
R_IDLE: begin
writeaddr <= 0;
mcount <= 0;
X0 <= X[511:0];
X1 <= X[1023:512];
mixfeedback <= 1'b0;
addrsourceMix <= 1'b0;
if (SMixInRdy)
begin
mstate <= R_WRITE;
doneROM <= 1'b0;
ram_wren <= 1'b1;
Clr_SMixInRdy <= 1;
nonce_1 <= nonce;
`ifndef NOMULTICORE
nonce_cnt <= nonce_cnt + 28'd1;
`else
nonce <= nonce + 32'd1;
`endif
end
end
R_WRITE: begin
mcount <= mcount + 6'd1;
ram_wren <= 0;
if (mcount==0)
begin
mixfeedback <= 1'b1;
if (writeaddr==1023)
doneROM <= 1'b1;
writeaddr <= writeaddr + 10'd1;
end
if (mcount==4)
mixfeedback <= 1'b1;
if (mcount == 3 || mcount == 7)
begin
X0 <= X1;
X1 <= Xmix;
mixfeedback <= 1'b0;
end
if (mcount == 6 && doneROM)
addrsourceMix <= 1'b1;
if (mcount == 7)
begin
mcount <= 0;
if (doneROM)
begin
cycle <= 0;
mstate <= R_MIX;
end
else
begin
`ifdef HALFRAM
if (!doneROM && !writeaddr[0])
ram_wren <= 1'b1;
`else
if (!doneROM)
ram_wren <= 1'b1;
`endif
end
end
end
R_MIX: begin
mcount <= mcount + 5'd1;
if (mcount == 0)
begin
`ifdef HALFRAM
if (oddAddr)
begin
X0Save <= X0;
X0 <= ramout[511:0];
X1Save <= X1;
X1 <= ramout[1023:512];
mixfeedback <= 0;
mstate <= R_INT;
end
else
begin
mixfeedback <= 1'b0;
X0 <= X0 ^ ramout[511:0];
X1 <= X1 ^ ramout[1023:512];
end
`else
mixfeedback <= 1'b0;
X0 <= X0 ^ ramout[511:0];
X1 <= X1 ^ ramout[1023:512];
`endif
end
if (mcount==1 || mcount==5)
mixfeedback <= 1;
if (mcount == 4 || mcount == 8)
begin
mixfeedback <= 1'b0;
X0 <= X1;
X1 <= Xmix;
end
if (mcount == 8)
begin
mcount <= 0;
cycle <= cycle + 11'd1;
if (cycle == 1023)
begin
MixOut <= { Xmix, X1 };
Set_SMixOutRdy <= 1'b1;
nonce_2 <= nonce_1;
mstate <= R_IDLE;
end
end
end
`ifdef HALFRAM
R_INT: begin
mcount <= mcount + 6'd1;
if (mcount==1 || mcount==5)
mixfeedback <= 1'b1;
if (mcount == 4)
begin
mixfeedback <= 0;
X0 <= X1;
X1 <= Xmix;
end
if (mcount == 8)
begin
mixfeedback <= 0;
X0 <= X1 ^ X0Save;
X1 <= Xmix ^ X1Save;
mcount <= 1;
mstate <= R_MIX;
end
end
`endif
endcase
end
end
endmodule | module hashcore (hash_clk, data1, data2, data3, target, nonce_msb, nonce_out, golden_nonce_out, golden_nonce_match, loadnonce); |
input hash_clk;
input [255:0] data1;
input [255:0] data2;
input [127:0] data3;
input [31:0] target;
input [3:0] nonce_msb;
output [31:0] nonce_out;
output [31:0] golden_nonce_out;
output golden_nonce_match;
input loadnonce;
reg poweron_reset = 1'b1;
reg reset = 1'b1;
always @ (posedge hash_clk)
begin
poweron_reset <= 1'b0;
reset <= poweron_reset;
end
`ifndef ICARUS
reg [31:0] nonce_prevous_load = 32'hffffffff;
`endif
`ifndef NOMULTICORE
reg [27:0] nonce_cnt = 28'd0;
wire [31:0] nonce;
assign nonce = { nonce_msb, nonce_cnt };
`else
reg [31:0] nonce = 32'd0;
`endif
assign nonce_out = nonce;
reg [31:0] nonce_1 = 32'd0;
reg [31:0] nonce_2 = 32'd0;
reg [31:0] golden_nonce = 32'd0;
assign golden_nonce_out = golden_nonce;
reg golden_nonce_match = 1'b0;
reg [255:0] rx_state;
reg [511:0] rx_input;
wire [255:0] tx_hash;
reg [255:0] khash = 256'd0;
reg [255:0] ihash = 256'd0;
reg [255:0] ohash = 256'd0;
`ifdef SIM
reg [255:0] final_hash = 256'd0;
`endif
reg [31:0] blockcnt = 32'd0;
reg [1023:0] Xbuf = 1024'd0;
reg [1023:0] MixOut;
wire [1023:0] MixOutRewire;
reg [5:0] cnt = 6'd0;
wire feedback;
assign feedback = (cnt != 6'b0);
sha256_transform # (.LOOP(64)) sha256_blk (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(rx_state),
.rx_input(rx_input),
.tx_hash(tx_hash)
);
reg SMixInRdy_state = 1'b0;
reg SMixOutRdy_state = 1'b0;
wire SMixInRdy;
wire SMixOutRdy;
reg Set_SMixInRdy = 1'b0;
reg Clr_SMixInRdy = 1'b0;
reg Set_SMixOutRdy = 1'b0;
reg Clr_SMixOutRdy = 1'b0;
always @ (posedge hash_clk)
begin
if (Set_SMixInRdy)
SMixInRdy_state <= 1'b1;
if (Clr_SMixInRdy)
SMixInRdy_state <= 1'b0;
if (Set_SMixOutRdy)
SMixOutRdy_state <= 1'b1;
if (Clr_SMixOutRdy)
SMixOutRdy_state <= 1'b0;
end
assign SMixInRdy = Clr_SMixInRdy ? 1'b0 : Set_SMixInRdy ? 1'b1 : SMixInRdy_state;
assign SMixOutRdy = Clr_SMixOutRdy ? 1'b0 : Set_SMixOutRdy ? 1'b1 : SMixOutRdy_state;
parameter S_IDLE=0,
S_H1= 1, S_H2= 2, S_H3= 3, S_H4= 4, S_H5= 5, S_H6= 6,
S_I1= 7, S_I2= 8, S_I3= 9, S_I4=10, S_I5=11, S_I6=12,
S_O1=13, S_O2=14, S_O3=15,
S_B1=16, S_B2=17, S_B3=18, S_B4=19, S_B5=20, S_B6=21,
S_XX=22,
S_R1=23, S_R2=24, S_R3=25, S_R4=26, S_R5=27, S_R6=28,
S_R7=29, S_R8=30, S_R9=31, S_R10=32, S_R11=33, S_R12=34,
S_R13=35, S_R14=36, S_R15=37, S_R16=38, S_R17=39, S_R18=40;
reg [5:0] state = S_IDLE;
reg mode = 0;
always @ (posedge hash_clk)
begin
Set_SMixInRdy <= 1'b0;
Clr_SMixOutRdy <= 1'b0;
golden_nonce_match <= 1'b0;
if (reset == 1'b1)
state <= S_IDLE;
else
begin
case (state)
S_IDLE: begin
if (SMixOutRdy ||
!SMixInRdy)
begin
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { data2, data1 };
blockcnt <= 32'd1;
cnt <= 6'd0;
if (SMixOutRdy)
mode <= 1'b1;
else
mode <= 1'b0;
state <= S_H1;
end
end
S_H1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H2;
end
end
S_H2: begin
state <= S_H3;
end
S_H3: begin
rx_state <= tx_hash;
rx_input <= { 384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000,
mode ? nonce_2 : nonce, data3[95:0] };
state <= S_H4;
end
S_H4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H5;
end
end
S_H5: begin
state <= S_H6;
end
S_H6: begin
khash <= tx_hash;
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h3636363636363636363636363636363636363636363636363636363636363636 ,
tx_hash ^ 256'h3636363636363636363636363636363636363636363636363636363636363636 };
cnt <= 6'd0;
if (mode)
state <= S_R1;
else
state <= S_I1;
end
S_I1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I2;
end
end
S_I2: begin
state <= S_I3;
end
S_I3: begin
rx_state <= tx_hash;
rx_input <= { data2, data1 };
state <= S_I4;
end
S_I4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I5;
end
end
S_I5: begin
state <= S_I6;
end
S_I6: begin
ihash <= tx_hash;
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_O1;
end
S_O1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_O2;
end
end
S_O2: begin
state <= S_O3;
end
S_O3: begin
ohash <= tx_hash;
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
blockcnt, nonce, data3[95:0] };
blockcnt <= blockcnt + 1;
cnt <= 6'd0;
state <= S_B1;
end
S_B1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B2;
end
end
S_B2: begin
state <= S_B3;
end
S_B3: begin
rx_state <= ohash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, tx_hash };
state <= S_B4;
end
S_B4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B5;
end
end
S_B5: begin
state <= S_B6;
end
S_B6: begin
Xbuf[255:0] <= Xbuf[511:256];
Xbuf[511:256] <= Xbuf[767:512];
Xbuf[767:512] <= Xbuf[1023:768];
Xbuf[1023:768] <= tx_hash;
if (blockcnt == 5)
state <= S_XX;
else begin
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
blockcnt, nonce, data3[95:0] };
blockcnt <= blockcnt + 1;
cnt <= 6'd0;
state <= S_B1;
end
end
S_XX: begin
Set_SMixInRdy <= 1;
state <= S_IDLE;
end
S_R1: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R2;
end
end
S_R2: begin
state <= S_R3;
end
S_R3: begin
rx_state <= tx_hash;
rx_input <= MixOutRewire[511:0];
state <= S_R4;
end
S_R4: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R5;
end
end
S_R5: begin
state <= S_R6;
end
S_R6: begin
rx_state <= tx_hash;
rx_input <= MixOutRewire[1023:512];
state <= S_R7;
end
S_R7: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R8;
end
end
S_R8: begin
state <= S_R9;
end
S_R9: begin
rx_state <= tx_hash;
rx_input <= 512'h00000620000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000001;
state <= S_R10;
end
S_R10: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R11;
end
end
S_R11: begin
state <= S_R12;
end
S_R12: begin
ihash <= tx_hash;
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_R13;
end
S_R13: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R14;
end
end
S_R14: begin
state <= S_R15;
end
S_R15: begin
rx_state <= tx_hash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, ihash };
state <= S_R16;
end
S_R16: begin
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R17;
end
end
S_R17: begin
state <= S_R18;
end
S_R18: begin
`ifdef SIM
final_hash <= tx_hash;
`endif
if ( { tx_hash[231:224], tx_hash[239:232], tx_hash[247:240], tx_hash[255:248] } < target)
begin
golden_nonce <= nonce_2;
golden_nonce_match <= 1'b1;
end
state <= S_IDLE;
mode <= 0;
Clr_SMixOutRdy <= 1'b1;
end
endcase
end
end
wire [1023:0] X;
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] tmp;
assign tmp = Xbuf[`IDX(i)];
assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] };
wire [31:0] mix;
assign mix = MixOut[`IDX(i)];
assign MixOutRewire[`IDX(i)] = { mix[7:0], mix[15:8], mix[23:16], mix[31:24] };
end
endgenerate
parameter R_IDLE=0, R_WRITE=1, R_MIX=2, R_INT=3;
reg [1:0] mstate = R_IDLE;
reg [10:0] cycle = 11'd0;
reg [5:0] mcount = 5'd0;
reg doneROM = 1'd0;
reg mixfeedback = 1'b0;
reg addrsourceMix = 1'b0;
reg [511:0] X0;
reg [511:0] X1;
`ifdef HALFRAM
reg [511:0] X0Save;
reg [511:0] X1Save;
reg oddAddr = 1'b0;
`endif
wire [511:0] Xmix;
reg [9:0] writeaddr = 10'd0;
`ifdef HALFRAM
parameter ADDRBITS = 9;
`else
parameter ADDRBITS = 10;
`endif
wire [ADDRBITS-1:0]ram_addr;
wire [255:0]ram1_din;
wire [255:0]ram1_dout;
wire [255:0]ram2_din;
wire [255:0]ram2_dout;
wire [255:0]ram3_din;
wire [255:0]ram3_dout;
wire [255:0]ram4_din;
wire [255:0]ram4_dout;
wire [1023:0]ramout;
reg ram_wren;
wire ram_clk;
assign ram_clk = hash_clk;
`ifdef HALFRAM
assign ram_addr = addrsourceMix ? Xmix[9:1] : writeaddr[9:1];
`else
assign ram_addr = addrsourceMix ? Xmix[9:0] : writeaddr;
`endif
ram # (.ADDRBITS(ADDRBITS)) ram1_blk (ram_addr, ram_clk, ram1_din, ram_wren, ram1_dout);
ram # (.ADDRBITS(ADDRBITS)) ram2_blk (ram_addr, ram_clk, ram2_din, ram_wren, ram2_dout);
ram # (.ADDRBITS(ADDRBITS)) ram3_blk (ram_addr, ram_clk, ram3_din, ram_wren, ram3_dout);
ram # (.ADDRBITS(ADDRBITS)) ram4_blk (ram_addr, ram_clk, ram4_din, ram_wren, ram4_dout);
assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout };
assign { ram4_din, ram3_din, ram2_din, ram1_din } = { X1, X0} ;
salsa salsa_blk (hash_clk, mixfeedback, X0, X1, Xmix);
always @ (posedge hash_clk)
begin
Set_SMixOutRdy <= 1'b0;
Clr_SMixInRdy <= 1'b0;
`ifdef HALFRAM
oddAddr <= Xmix[0];
`endif
`ifdef ICARUS
if (loadnonce)
`else
if (loadnonce || (nonce_prevous_load != data3[127:96]))
`endif
begin
`ifdef NOMULTICORE
nonce <= data3[127:96];
`else
nonce_cnt <= data3[123:96];
`endif
`ifndef ICARUS
nonce_prevous_load <= data3[127:96];
`endif
end
if (reset == 1'b1)
mstate <= R_IDLE;
else
begin
case (mstate)
R_IDLE: begin
writeaddr <= 0;
mcount <= 0;
X0 <= X[511:0];
X1 <= X[1023:512];
mixfeedback <= 1'b0;
addrsourceMix <= 1'b0;
if (SMixInRdy)
begin
mstate <= R_WRITE;
doneROM <= 1'b0;
ram_wren <= 1'b1;
Clr_SMixInRdy <= 1;
nonce_1 <= nonce;
`ifndef NOMULTICORE
nonce_cnt <= nonce_cnt + 28'd1;
`else
nonce <= nonce + 32'd1;
`endif
end
end
R_WRITE: begin
mcount <= mcount + 6'd1;
ram_wren <= 0;
if (mcount==0)
begin
mixfeedback <= 1'b1;
if (writeaddr==1023)
doneROM <= 1'b1;
writeaddr <= writeaddr + 10'd1;
end
if (mcount==4)
mixfeedback <= 1'b1;
if (mcount == 3 || mcount == 7)
begin
X0 <= X1;
X1 <= Xmix;
mixfeedback <= 1'b0;
end
if (mcount == 6 && doneROM)
addrsourceMix <= 1'b1;
if (mcount == 7)
begin
mcount <= 0;
if (doneROM)
begin
cycle <= 0;
mstate <= R_MIX;
end
else
begin
`ifdef HALFRAM
if (!doneROM && !writeaddr[0])
ram_wren <= 1'b1;
`else
if (!doneROM)
ram_wren <= 1'b1;
`endif
end
end
end
R_MIX: begin
mcount <= mcount + 5'd1;
if (mcount == 0)
begin
`ifdef HALFRAM
if (oddAddr)
begin
X0Save <= X0;
X0 <= ramout[511:0];
X1Save <= X1;
X1 <= ramout[1023:512];
mixfeedback <= 0;
mstate <= R_INT;
end
else
begin
mixfeedback <= 1'b0;
X0 <= X0 ^ ramout[511:0];
X1 <= X1 ^ ramout[1023:512];
end
`else
mixfeedback <= 1'b0;
X0 <= X0 ^ ramout[511:0];
X1 <= X1 ^ ramout[1023:512];
`endif
end
if (mcount==1 || mcount==5)
mixfeedback <= 1;
if (mcount == 4 || mcount == 8)
begin
mixfeedback <= 1'b0;
X0 <= X1;
X1 <= Xmix;
end
if (mcount == 8)
begin
mcount <= 0;
cycle <= cycle + 11'd1;
if (cycle == 1023)
begin
MixOut <= { Xmix, X1 };
Set_SMixOutRdy <= 1'b1;
nonce_2 <= nonce_1;
mstate <= R_IDLE;
end
end
end
`ifdef HALFRAM
R_INT: begin
mcount <= mcount + 6'd1;
if (mcount==1 || mcount==5)
mixfeedback <= 1'b1;
if (mcount == 4)
begin
mixfeedback <= 0;
X0 <= X1;
X1 <= Xmix;
end
if (mcount == 8)
begin
mixfeedback <= 0;
X0 <= X1 ^ X0Save;
X1 <= Xmix ^ X1Save;
mcount <= 1;
mstate <= R_MIX;
end
end
`endif
endcase
end
end
endmodule | 270 |
6,332 | data/full_repos/permissive/11584509/source/ltcminer.v | 11,584,509 | ltcminer.v | v | 182 | 147 | [] | [] | [] | null | line:101: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/11584509/source/ltcminer.v:49: Cannot find file containing module: \'main_pll\'\n main_pll #(.SPEED_MHZ(SPEED_MHZ)) pll_blk (osc_clk, hash_clk);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/source,data/full_repos/permissive/11584509/main_pll\n data/full_repos/permissive/11584509/source,data/full_repos/permissive/11584509/main_pll.v\n data/full_repos/permissive/11584509/source,data/full_repos/permissive/11584509/main_pll.sv\n main_pll\n main_pll.v\n main_pll.sv\n obj_dir/main_pll\n obj_dir/main_pll.v\n obj_dir/main_pll.sv\n%Warning-WIDTH: data/full_repos/permissive/11584509/source/ltcminer.v:70: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h7ff\' generates 31 bits.\n : ... In instance ltcminer\n reg [31:0] target = 31\'h000007ff; \n ^~~~~~~~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:85: Cannot find file containing module: \'hashcore\'\n hashcore M (hash_clk, data1, data2, data3, target, nonce_core, nonce_out_i, golden_nonce_i[(i+1)*32-1:i*32], golden_nonce_match[i], loadnonce);\n ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/source/ltcminer.v:131: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n : ... In instance ltcminer\n clear_nonces[port_counter] <= 1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/source/ltcminer.v:128: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n : ... In instance ltcminer\n if (new_nonces_flag[port_counter])\n ^\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:149: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT1")) data1_vw_blk(.probe(), .source(data1_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:150: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:151: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(128), .INSTANCE_ID("DAT3")) data3_vw_blk(.probe(), .source(data3_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:152: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(32), .INSTANCE_ID("TARG")) target_vw_blk(.probe(), .source(target_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:164: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce_out), .source());\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:165: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce_out), .source());\n ^~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 3 warning(s)\n' | 7,236 | module | module ltcminer (osc_clk);
`else
module ltcminer (osc_clk, LEDS_out);
`endif
`ifdef SPEED_MHZ
parameter SPEED_MHZ = `SPEED_MHZ;
`else
parameter SPEED_MHZ = 25;
`endif
`ifdef LOCAL_MINERS
parameter LOCAL_MINERS = `LOCAL_MINERS;
`else
parameter LOCAL_MINERS = 1;
`endif
input osc_clk;
`ifndef NOLEDS
output reg [7:0]LEDS_out;
`endif
wire hash_clk;
`ifndef SIM
main_pll #(.SPEED_MHZ(SPEED_MHZ)) pll_blk (osc_clk, hash_clk);
`else
assign hash_clk = osc_clk;
`endif
`ifndef SIM
reg [255:0] data1 = 256'd0;
reg [255:0] data2 = 256'd0;
reg [127:0] data3 = 128'd0;
`else
reg [255:0] data1 = 256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
reg [255:0] data2 = 256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756;
reg [127:0] data3 = 128'h0000318f7e71441b141fe951b2b0c7df;
`endif
reg [31:0] target = 31'h000007ff;
wire [31:0]golden_nonce_out;
wire [31:0] nonce_out;
wire loadnonce = 1'b0;
wire [LOCAL_MINERS*32-1:0] golden_nonce_i;
wire [LOCAL_MINERS-1:0] golden_nonce_match;
generate
genvar i;
for (i = 0; i < LOCAL_MINERS; i = i + 1)
begin: for_local_miners
wire [31:0] nonce_out_i;
wire [3:0] nonce_core = i;
hashcore M (hash_clk, data1, data2, data3, target, nonce_core, nonce_out_i, golden_nonce_i[(i+1)*32-1:i*32], golden_nonce_match[i], loadnonce);
if (i==0)
assign nonce_out = nonce_out_i;
end
endgenerate
reg [LOCAL_MINERS-1:0]new_nonces_flag = 0;
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
reg [clog2(LOCAL_MINERS)+1:0] port_counter = 0;
reg [LOCAL_MINERS*32-1:0] nonces_shifted = 0;
assign golden_nonce_out = nonces_shifted[31:0];
reg [LOCAL_MINERS-1:0] clear_nonces = 0;
always @(posedge hash_clk)
begin
new_nonces_flag <= (new_nonces_flag & ~clear_nonces) | golden_nonce_match;
if (port_counter == LOCAL_MINERS-1)
port_counter <= 0;
else
port_counter <= port_counter + 1'd1;
if (new_nonces_flag[port_counter])
begin
nonces_shifted <= golden_nonce_i >> port_counter*32;
clear_nonces[port_counter] <= 1;
end
else
begin
clear_nonces <= 0;
end
end
`ifndef SIM
wire [255:0] data1_vw;
wire [255:0] data2_vw;
wire [127:0] data3_vw;
wire [31:0] target_vw;
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT1")) data1_vw_blk(.probe(), .source(data1_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(128), .INSTANCE_ID("DAT3")) data3_vw_blk(.probe(), .source(data3_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(32), .INSTANCE_ID("TARG")) target_vw_blk(.probe(), .source(target_vw));
always @ (posedge hash_clk)
begin
data1 <= data1_vw;
data2 <= data2_vw;
data3 <= data3_vw;
target <= target_vw;
end
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce_out), .source());
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce_out), .source());
`endif
`ifndef NOLEDS
always @(posedge hash_clk) begin
`ifdef INVERTLEDS
LEDS_out <= ~nonce_out[15:8];
`else
LEDS_out <= nonce_out[15:8];
`endif
end
`endif
endmodule | module ltcminer (osc_clk); |
`else
module ltcminer (osc_clk, LEDS_out);
`endif
`ifdef SPEED_MHZ
parameter SPEED_MHZ = `SPEED_MHZ;
`else
parameter SPEED_MHZ = 25;
`endif
`ifdef LOCAL_MINERS
parameter LOCAL_MINERS = `LOCAL_MINERS;
`else
parameter LOCAL_MINERS = 1;
`endif
input osc_clk;
`ifndef NOLEDS
output reg [7:0]LEDS_out;
`endif
wire hash_clk;
`ifndef SIM
main_pll #(.SPEED_MHZ(SPEED_MHZ)) pll_blk (osc_clk, hash_clk);
`else
assign hash_clk = osc_clk;
`endif
`ifndef SIM
reg [255:0] data1 = 256'd0;
reg [255:0] data2 = 256'd0;
reg [127:0] data3 = 128'd0;
`else
reg [255:0] data1 = 256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
reg [255:0] data2 = 256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756;
reg [127:0] data3 = 128'h0000318f7e71441b141fe951b2b0c7df;
`endif
reg [31:0] target = 31'h000007ff;
wire [31:0]golden_nonce_out;
wire [31:0] nonce_out;
wire loadnonce = 1'b0;
wire [LOCAL_MINERS*32-1:0] golden_nonce_i;
wire [LOCAL_MINERS-1:0] golden_nonce_match;
generate
genvar i;
for (i = 0; i < LOCAL_MINERS; i = i + 1)
begin: for_local_miners
wire [31:0] nonce_out_i;
wire [3:0] nonce_core = i;
hashcore M (hash_clk, data1, data2, data3, target, nonce_core, nonce_out_i, golden_nonce_i[(i+1)*32-1:i*32], golden_nonce_match[i], loadnonce);
if (i==0)
assign nonce_out = nonce_out_i;
end
endgenerate
reg [LOCAL_MINERS-1:0]new_nonces_flag = 0;
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
reg [clog2(LOCAL_MINERS)+1:0] port_counter = 0;
reg [LOCAL_MINERS*32-1:0] nonces_shifted = 0;
assign golden_nonce_out = nonces_shifted[31:0];
reg [LOCAL_MINERS-1:0] clear_nonces = 0;
always @(posedge hash_clk)
begin
new_nonces_flag <= (new_nonces_flag & ~clear_nonces) | golden_nonce_match;
if (port_counter == LOCAL_MINERS-1)
port_counter <= 0;
else
port_counter <= port_counter + 1'd1;
if (new_nonces_flag[port_counter])
begin
nonces_shifted <= golden_nonce_i >> port_counter*32;
clear_nonces[port_counter] <= 1;
end
else
begin
clear_nonces <= 0;
end
end
`ifndef SIM
wire [255:0] data1_vw;
wire [255:0] data2_vw;
wire [127:0] data3_vw;
wire [31:0] target_vw;
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT1")) data1_vw_blk(.probe(), .source(data1_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(128), .INSTANCE_ID("DAT3")) data3_vw_blk(.probe(), .source(data3_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(32), .INSTANCE_ID("TARG")) target_vw_blk(.probe(), .source(target_vw));
always @ (posedge hash_clk)
begin
data1 <= data1_vw;
data2 <= data2_vw;
data3 <= data3_vw;
target <= target_vw;
end
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce_out), .source());
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce_out), .source());
`endif
`ifndef NOLEDS
always @(posedge hash_clk) begin
`ifdef INVERTLEDS
LEDS_out <= ~nonce_out[15:8];
`else
LEDS_out <= nonce_out[15:8];
`endif
end
`endif
endmodule | 270 |
6,333 | data/full_repos/permissive/11584509/source/ltcminer.v | 11,584,509 | ltcminer.v | v | 182 | 147 | [] | [] | [] | null | line:101: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/11584509/source/ltcminer.v:49: Cannot find file containing module: \'main_pll\'\n main_pll #(.SPEED_MHZ(SPEED_MHZ)) pll_blk (osc_clk, hash_clk);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11584509/source,data/full_repos/permissive/11584509/main_pll\n data/full_repos/permissive/11584509/source,data/full_repos/permissive/11584509/main_pll.v\n data/full_repos/permissive/11584509/source,data/full_repos/permissive/11584509/main_pll.sv\n main_pll\n main_pll.v\n main_pll.sv\n obj_dir/main_pll\n obj_dir/main_pll.v\n obj_dir/main_pll.sv\n%Warning-WIDTH: data/full_repos/permissive/11584509/source/ltcminer.v:70: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h7ff\' generates 31 bits.\n : ... In instance ltcminer\n reg [31:0] target = 31\'h000007ff; \n ^~~~~~~~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:85: Cannot find file containing module: \'hashcore\'\n hashcore M (hash_clk, data1, data2, data3, target, nonce_core, nonce_out_i, golden_nonce_i[(i+1)*32-1:i*32], golden_nonce_match[i], loadnonce);\n ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/source/ltcminer.v:131: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n : ... In instance ltcminer\n clear_nonces[port_counter] <= 1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/source/ltcminer.v:128: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n : ... In instance ltcminer\n if (new_nonces_flag[port_counter])\n ^\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:149: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT1")) data1_vw_blk(.probe(), .source(data1_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:150: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:151: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(128), .INSTANCE_ID("DAT3")) data3_vw_blk(.probe(), .source(data3_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:152: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(32), .INSTANCE_ID("TARG")) target_vw_blk(.probe(), .source(target_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:164: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce_out), .source());\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:165: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce_out), .source());\n ^~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 3 warning(s)\n' | 7,236 | function | function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction | function integer clog2; |
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction | 270 |
6,334 | data/full_repos/permissive/11584509/source/salsa.v | 11,584,509 | salsa.v | v | 263 | 99 | [] | [] | [] | [(25, 78), (80, 262)] | null | data/verilator_xmls/a8b85f06-4d1d-4e6b-8aa2-c71e9c804937.xml | null | 7,237 | module | module salsa (clk, feedback, B, Bx, Bo);
input clk;
input feedback;
input [511:0]B;
input [511:0]Bx;
output [511:0]Bo;
wire [511:0]xx;
wire [511:0]xr;
reg [511:0]xrd;
salsa_core salsa1 (clk, feedback ? xrd : xx, xr);
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : XX
assign xx[`IDX(i)] = B[`IDX(i)] ^ Bx[`IDX(i)];
assign Bo[`IDX(i)] = xx[`IDX(i)] + xr[`IDX(i)];
end
endgenerate
always @ (posedge clk)
xrd <= xr;
endmodule | module salsa (clk, feedback, B, Bx, Bo); |
input clk;
input feedback;
input [511:0]B;
input [511:0]Bx;
output [511:0]Bo;
wire [511:0]xx;
wire [511:0]xr;
reg [511:0]xrd;
salsa_core salsa1 (clk, feedback ? xrd : xx, xr);
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : XX
assign xx[`IDX(i)] = B[`IDX(i)] ^ Bx[`IDX(i)];
assign Bo[`IDX(i)] = xx[`IDX(i)] + xr[`IDX(i)];
end
endgenerate
always @ (posedge clk)
xrd <= xr;
endmodule | 270 |
6,335 | data/full_repos/permissive/11584509/source/salsa.v | 11,584,509 | salsa.v | v | 263 | 99 | [] | [] | [] | [(25, 78), (80, 262)] | null | data/verilator_xmls/a8b85f06-4d1d-4e6b-8aa2-c71e9c804937.xml | null | 7,237 | module | module salsa_core (clk, xx, out);
input clk;
input [511:0]xx;
output [511:0]out;
wire [31:0]c00;
wire [31:0]c01;
wire [31:0]c02;
wire [31:0]c03;
wire [31:0]c04;
wire [31:0]c05;
wire [31:0]c06;
wire [31:0]c07;
wire [31:0]c08;
wire [31:0]c09;
wire [31:0]c10;
wire [31:0]c11;
wire [31:0]c12;
wire [31:0]c13;
wire [31:0]c14;
wire [31:0]c15;
wire [31:0]r00;
wire [31:0]r01;
wire [31:0]r02;
wire [31:0]r03;
wire [31:0]r04;
wire [31:0]r05;
wire [31:0]r06;
wire [31:0]r07;
wire [31:0]r08;
wire [31:0]r09;
wire [31:0]r10;
wire [31:0]r11;
wire [31:0]r12;
wire [31:0]r13;
wire [31:0]r14;
wire [31:0]r15;
wire [31:0]c00s;
wire [31:0]c01s;
wire [31:0]c02s;
wire [31:0]c03s;
wire [31:0]c04s;
wire [31:0]c05s;
wire [31:0]c06s;
wire [31:0]c07s;
wire [31:0]c08s;
wire [31:0]c09s;
wire [31:0]c10s;
wire [31:0]c11s;
wire [31:0]c12s;
wire [31:0]c13s;
wire [31:0]c14s;
wire [31:0]c15s;
wire [31:0]r00s;
wire [31:0]r01s;
wire [31:0]r02s;
wire [31:0]r03s;
wire [31:0]r04s;
wire [31:0]r05s;
wire [31:0]r06s;
wire [31:0]r07s;
wire [31:0]r08s;
wire [31:0]r09s;
wire [31:0]r10s;
wire [31:0]r11s;
wire [31:0]r12s;
wire [31:0]r13s;
wire [31:0]r14s;
wire [31:0]r15s;
assign c04s = xx[`IDX(0)] + xx[`IDX(12)];
assign c04 = xx[`IDX(4)] ^ { c04s[24:0], c04s[31:25] };
assign c09s = xx[`IDX(5)] + xx[`IDX(1)];
assign c09 = xx[`IDX(9)] ^ { c09s[24:0], c09s[31:25] };
assign c14s = xx[`IDX(10)] + xx[`IDX(6)];
assign c14 = xx[`IDX(14)] ^ { c14s[24:0], c14s[31:25] };
assign c03s = xx[`IDX(15)] + xx[`IDX(11)];
assign c03 = xx[`IDX(03)] ^ { c03s[24:0], c03s[31:25] };
assign c08s = c04 + xx[`IDX(0)];
assign c08 = xx[`IDX(8)] ^ { c08s[22:0], c08s[31:23] };
assign c13s = c09 + xx[`IDX(5)];
assign c13 = xx[`IDX(13)] ^ { c13s[22:0], c13s[31:23] };
assign c02s = c14 + xx[`IDX(10)];
assign c02 = xx[`IDX(2)] ^ { c02s[22:0], c02s[31:23] };
assign c07s = c03 + xx[`IDX(15)];
assign c07 = xx[`IDX(7)] ^ { c07s[22:0], c07s[31:23] };
assign c12s = c08 + c04;
assign c12 = xx[`IDX(12)] ^ { c12s[18:0], c12s[31:19] };
assign c01s = c13 + c09;
assign c01 = xx[`IDX(1)] ^ { c01s[18:0], c01s[31:19] };
assign c06s = c02 + c14;
assign c06 = xx[`IDX(6)] ^ { c06s[18:0], c06s[31:19] };
assign c11s = c07 + c03;
assign c11 = xx[`IDX(11)] ^ { c11s[18:0], c11s[31:19] };
assign c00s = c12 + c08;
assign c00 = xx[`IDX(0)] ^ { c00s[13:0], c00s[31:14] };
assign c05s = c01 + c13;
assign c05 = xx[`IDX(5)] ^ { c05s[13:0], c05s[31:14] };
assign c10s = c06 + c02;
assign c10 = xx[`IDX(10)] ^ { c10s[13:0], c10s[31:14] };
assign c15s = c11 + c07;
assign c15 = xx[`IDX(15)] ^ { c15s[13:0], c15s[31:14] };
assign r01s = c00 + c03;
assign r01 = c01 ^ { r01s[24:0], r01s[31:25] };
assign r06s = c05 + c04;
assign r06 = c06 ^ { r06s[24:0], r06s[31:25] };
assign r11s = c10 + c09;
assign r11 = c11 ^ { r11s[24:0], r11s[31:25] };
assign r12s = c15 + c14;
assign r12 = c12 ^ { r12s[24:0], r12s[31:25] };
assign r02s = r01 + c00;
assign r02 = c02 ^ { r02s[22:0], r02s[31:23] };
assign r07s = r06 + c05;
assign r07 = c07 ^ { r07s[22:0], r07s[31:23] };
assign r08s = r11 + c10;
assign r08 = c08 ^ { r08s[22:0], r08s[31:23] };
assign r13s = r12 + c15;
assign r13 = c13 ^ { r13s[22:0], r13s[31:23] };
assign r03s = r02 + r01;
assign r03 = c03 ^ { r03s[18:0], r03s[31:19] };
assign r04s = r07 + r06;
assign r04 = c04 ^ { r04s[18:0], r04s[31:19] };
assign r09s = r08 + r11;
assign r09 = c09 ^ { r09s[18:0], r09s[31:19] };
assign r14s = r13 + r12;
assign r14 = c14 ^ { r14s[18:0], r14s[31:19] };
assign r00s = r03 + r02;
assign r00 = c00 ^ { r00s[13:0], r00s[31:14] };
assign r05s = r04 + r07;
assign r05 = c05 ^ { r05s[13:0], r05s[31:14] };
assign r10s = r09 + r08;
assign r10 = c10 ^ { r10s[13:0], r10s[31:14] };
assign r15s = r14 + r13;
assign r15 = c15 ^ { r15s[13:0], r15s[31:14] };
assign out = { r15, r14, r13, r12, r11, r10, r09, r08, r07, r06, r05, r04, r03, r02, r01, r00 };
endmodule | module salsa_core (clk, xx, out); |
input clk;
input [511:0]xx;
output [511:0]out;
wire [31:0]c00;
wire [31:0]c01;
wire [31:0]c02;
wire [31:0]c03;
wire [31:0]c04;
wire [31:0]c05;
wire [31:0]c06;
wire [31:0]c07;
wire [31:0]c08;
wire [31:0]c09;
wire [31:0]c10;
wire [31:0]c11;
wire [31:0]c12;
wire [31:0]c13;
wire [31:0]c14;
wire [31:0]c15;
wire [31:0]r00;
wire [31:0]r01;
wire [31:0]r02;
wire [31:0]r03;
wire [31:0]r04;
wire [31:0]r05;
wire [31:0]r06;
wire [31:0]r07;
wire [31:0]r08;
wire [31:0]r09;
wire [31:0]r10;
wire [31:0]r11;
wire [31:0]r12;
wire [31:0]r13;
wire [31:0]r14;
wire [31:0]r15;
wire [31:0]c00s;
wire [31:0]c01s;
wire [31:0]c02s;
wire [31:0]c03s;
wire [31:0]c04s;
wire [31:0]c05s;
wire [31:0]c06s;
wire [31:0]c07s;
wire [31:0]c08s;
wire [31:0]c09s;
wire [31:0]c10s;
wire [31:0]c11s;
wire [31:0]c12s;
wire [31:0]c13s;
wire [31:0]c14s;
wire [31:0]c15s;
wire [31:0]r00s;
wire [31:0]r01s;
wire [31:0]r02s;
wire [31:0]r03s;
wire [31:0]r04s;
wire [31:0]r05s;
wire [31:0]r06s;
wire [31:0]r07s;
wire [31:0]r08s;
wire [31:0]r09s;
wire [31:0]r10s;
wire [31:0]r11s;
wire [31:0]r12s;
wire [31:0]r13s;
wire [31:0]r14s;
wire [31:0]r15s;
assign c04s = xx[`IDX(0)] + xx[`IDX(12)];
assign c04 = xx[`IDX(4)] ^ { c04s[24:0], c04s[31:25] };
assign c09s = xx[`IDX(5)] + xx[`IDX(1)];
assign c09 = xx[`IDX(9)] ^ { c09s[24:0], c09s[31:25] };
assign c14s = xx[`IDX(10)] + xx[`IDX(6)];
assign c14 = xx[`IDX(14)] ^ { c14s[24:0], c14s[31:25] };
assign c03s = xx[`IDX(15)] + xx[`IDX(11)];
assign c03 = xx[`IDX(03)] ^ { c03s[24:0], c03s[31:25] };
assign c08s = c04 + xx[`IDX(0)];
assign c08 = xx[`IDX(8)] ^ { c08s[22:0], c08s[31:23] };
assign c13s = c09 + xx[`IDX(5)];
assign c13 = xx[`IDX(13)] ^ { c13s[22:0], c13s[31:23] };
assign c02s = c14 + xx[`IDX(10)];
assign c02 = xx[`IDX(2)] ^ { c02s[22:0], c02s[31:23] };
assign c07s = c03 + xx[`IDX(15)];
assign c07 = xx[`IDX(7)] ^ { c07s[22:0], c07s[31:23] };
assign c12s = c08 + c04;
assign c12 = xx[`IDX(12)] ^ { c12s[18:0], c12s[31:19] };
assign c01s = c13 + c09;
assign c01 = xx[`IDX(1)] ^ { c01s[18:0], c01s[31:19] };
assign c06s = c02 + c14;
assign c06 = xx[`IDX(6)] ^ { c06s[18:0], c06s[31:19] };
assign c11s = c07 + c03;
assign c11 = xx[`IDX(11)] ^ { c11s[18:0], c11s[31:19] };
assign c00s = c12 + c08;
assign c00 = xx[`IDX(0)] ^ { c00s[13:0], c00s[31:14] };
assign c05s = c01 + c13;
assign c05 = xx[`IDX(5)] ^ { c05s[13:0], c05s[31:14] };
assign c10s = c06 + c02;
assign c10 = xx[`IDX(10)] ^ { c10s[13:0], c10s[31:14] };
assign c15s = c11 + c07;
assign c15 = xx[`IDX(15)] ^ { c15s[13:0], c15s[31:14] };
assign r01s = c00 + c03;
assign r01 = c01 ^ { r01s[24:0], r01s[31:25] };
assign r06s = c05 + c04;
assign r06 = c06 ^ { r06s[24:0], r06s[31:25] };
assign r11s = c10 + c09;
assign r11 = c11 ^ { r11s[24:0], r11s[31:25] };
assign r12s = c15 + c14;
assign r12 = c12 ^ { r12s[24:0], r12s[31:25] };
assign r02s = r01 + c00;
assign r02 = c02 ^ { r02s[22:0], r02s[31:23] };
assign r07s = r06 + c05;
assign r07 = c07 ^ { r07s[22:0], r07s[31:23] };
assign r08s = r11 + c10;
assign r08 = c08 ^ { r08s[22:0], r08s[31:23] };
assign r13s = r12 + c15;
assign r13 = c13 ^ { r13s[22:0], r13s[31:23] };
assign r03s = r02 + r01;
assign r03 = c03 ^ { r03s[18:0], r03s[31:19] };
assign r04s = r07 + r06;
assign r04 = c04 ^ { r04s[18:0], r04s[31:19] };
assign r09s = r08 + r11;
assign r09 = c09 ^ { r09s[18:0], r09s[31:19] };
assign r14s = r13 + r12;
assign r14 = c14 ^ { r14s[18:0], r14s[31:19] };
assign r00s = r03 + r02;
assign r00 = c00 ^ { r00s[13:0], r00s[31:14] };
assign r05s = r04 + r07;
assign r05 = c05 ^ { r05s[13:0], r05s[31:14] };
assign r10s = r09 + r08;
assign r10 = c10 ^ { r10s[13:0], r10s[31:14] };
assign r15s = r14 + r13;
assign r15 = c15 ^ { r15s[13:0], r15s[31:14] };
assign out = { r15, r14, r13, r12, r11, r10, r09, r08, r07, r06, r05, r04, r03, r02, r01, r00 };
endmodule | 270 |
6,341 | data/full_repos/permissive/115852809/rtl/ttl_7402.v | 115,852,809 | ttl_7402.v | v | 52 | 50 | [] | [] | [] | [(28, 38)] | null | data/verilator_xmls/3dc60f3e-4b4c-4ceb-a188-7817e37322d6.xml | null | 7,247 | module | module ttl_7402(
input _1A, input _1B, output _1Y,
input _2A, input _2B, output _2Y,
input _3A, input _3B, output _3Y,
input _4A, input _4B, output _4Y
);
nor(_1Y,_1A,_1B);
nor(_2Y,_2A,_2B);
nor(_3Y,_3A,_3B);
nor(_4Y,_4A,_4B);
endmodule | module ttl_7402(
input _1A, input _1B, output _1Y,
input _2A, input _2B, output _2Y,
input _3A, input _3B, output _3Y,
input _4A, input _4B, output _4Y
); |
nor(_1Y,_1A,_1B);
nor(_2Y,_2A,_2B);
nor(_3Y,_3A,_3B);
nor(_4Y,_4A,_4B);
endmodule | 1 |
6,342 | data/full_repos/permissive/115852809/rtl/ttl_7404.v | 115,852,809 | ttl_7404.v | v | 37 | 54 | [] | [] | [] | [(23, 37)] | null | data/verilator_xmls/6df42598-60ca-4195-931d-995198a70f6d.xml | null | 7,248 | module | module ttl_7404(
input _1A, output _1Y,
input _2A, output _2Y,
input _3A, output _3Y,
input _4A, output _4Y,
input _5A, output _5Y,
input _6A, output _6Y
);
not(_1Y,_1A);
not(_2Y,_2A);
not(_3Y,_3A);
not(_4Y,_4A);
not(_5Y,_5A);
not(_6Y,_6A);
endmodule | module ttl_7404(
input _1A, output _1Y,
input _2A, output _2Y,
input _3A, output _3Y,
input _4A, output _4Y,
input _5A, output _5Y,
input _6A, output _6Y
); |
not(_1Y,_1A);
not(_2Y,_2A);
not(_3Y,_3A);
not(_4Y,_4A);
not(_5Y,_5A);
not(_6Y,_6A);
endmodule | 1 |
6,345 | data/full_repos/permissive/115852809/rtl/ttl_74244.v | 115,852,809 | ttl_74244.v | v | 32 | 52 | [] | [] | [] | [(18, 32)] | null | data/verilator_xmls/08dd84e3-17ed-4942-8a21-20c1e55ca238.xml | null | 7,251 | module | module ttl_74244(
input _1G_n,
input [4:1] _1A, output [4:1] _1Y,
input _2G_n,
input [4:1] _2A, output [4:1] _2Y
);
bufif0(_1Y[1],_1A[1],_1G_n);
bufif0(_1Y[2],_1A[2],_1G_n);
bufif0(_1Y[3],_1A[3],_1G_n);
bufif0(_1Y[4],_1A[4],_1G_n);
bufif0(_2Y[1],_2A[1],_2G_n);
bufif0(_2Y[2],_2A[2],_2G_n);
bufif0(_2Y[3],_2A[3],_2G_n);
bufif0(_2Y[4],_2A[4],_2G_n);
endmodule | module ttl_74244(
input _1G_n,
input [4:1] _1A, output [4:1] _1Y,
input _2G_n,
input [4:1] _2A, output [4:1] _2Y
); |
bufif0(_1Y[1],_1A[1],_1G_n);
bufif0(_1Y[2],_1A[2],_1G_n);
bufif0(_1Y[3],_1A[3],_1G_n);
bufif0(_1Y[4],_1A[4],_1G_n);
bufif0(_2Y[1],_2A[1],_2G_n);
bufif0(_2Y[2],_2A[2],_2G_n);
bufif0(_2Y[3],_2A[3],_2G_n);
bufif0(_2Y[4],_2A[4],_2G_n);
endmodule | 1 |
6,347 | data/full_repos/permissive/115852809/tb/mcs4eval_tb.v | 115,852,809 | mcs4eval_tb.v | v | 34 | 141 | [] | [] | [] | null | line:31: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115852809/tb/mcs4eval_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n #(96) clk <= !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115852809/tb/mcs4eval_tb.v:28: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("mcs4eval_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115852809/tb/mcs4eval_tb.v:29: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, mcs4eval_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115852809/tb/mcs4eval_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #8000000\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,253 | module | module mcs4eval_tb();
reg clk = 1'b0;
wire phi1;
wire phi2;
wire sync;
wire cm_rom;
wire [3:0] data_bus;
always
#(96) clk <= !clk;
i4001 #(.ROM_FILENAME("build/roms/mcs4eval.mem")) rom(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_i(sync),.D_io(data_bus),.CM_i(cm_rom));
i4002 ram_0(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_i(sync),.D_io(data_bus),.CM_i(cm_rom),.P0_i(1'b0));
i4002 ram_1(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_i(sync),.D_io(data_bus),.CM_i(cm_rom),.P0_i(1'b1));
i4004 cpu(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_o(sync),.D_io(data_bus),.CM_ROM_o(cm_rom),.TEST_i(1'b1));
mcs4_clk_gen generator(.clk_i(clk),.PHI1_o(phi1),.PHI2_o(phi2));
initial
begin
$dumpfile("mcs4eval_tb.vcd");
$dumpvars(0, mcs4eval_tb);
#8000000
$finish;
end
endmodule | module mcs4eval_tb(); |
reg clk = 1'b0;
wire phi1;
wire phi2;
wire sync;
wire cm_rom;
wire [3:0] data_bus;
always
#(96) clk <= !clk;
i4001 #(.ROM_FILENAME("build/roms/mcs4eval.mem")) rom(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_i(sync),.D_io(data_bus),.CM_i(cm_rom));
i4002 ram_0(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_i(sync),.D_io(data_bus),.CM_i(cm_rom),.P0_i(1'b0));
i4002 ram_1(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_i(sync),.D_io(data_bus),.CM_i(cm_rom),.P0_i(1'b1));
i4004 cpu(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_o(sync),.D_io(data_bus),.CM_ROM_o(cm_rom),.TEST_i(1'b1));
mcs4_clk_gen generator(.clk_i(clk),.PHI1_o(phi1),.PHI2_o(phi2));
initial
begin
$dumpfile("mcs4eval_tb.vcd");
$dumpvars(0, mcs4eval_tb);
#8000000
$finish;
end
endmodule | 1 |
6,350 | data/full_repos/permissive/115920613/rtl/pwr_reset.v | 115,920,613 | pwr_reset.v | v | 56 | 64 | [] | ['apache license'] | [] | [(26, 55)] | null | data/verilator_xmls/1f3b158d-f220-41b3-9800-7679fce1ff48.xml | null | 7,257 | module | module pwr_reset(
input clk25,
input rst_n,
input enable,
output rst
);
reg hard_reset;
reg [5:0] reset_cnt;
wire pwr_up_flag = &reset_cnt;
always @(posedge clk25)
begin
if (rst_n == 1'b0)
begin
reset_cnt <= 6'b0;
hard_reset <= 1'b0;
end
else if (enable)
begin
if (!pwr_up_flag)
reset_cnt <= reset_cnt + 6'b1;
hard_reset <= pwr_up_flag;
end
end
assign rst = ~hard_reset;
endmodule | module pwr_reset(
input clk25,
input rst_n,
input enable,
output rst
); |
reg hard_reset;
reg [5:0] reset_cnt;
wire pwr_up_flag = &reset_cnt;
always @(posedge clk25)
begin
if (rst_n == 1'b0)
begin
reset_cnt <= 6'b0;
hard_reset <= 1'b0;
end
else if (enable)
begin
if (!pwr_up_flag)
reset_cnt <= reset_cnt + 6'b1;
hard_reset <= pwr_up_flag;
end
end
assign rst = ~hard_reset;
endmodule | 106 |
6,351 | data/full_repos/permissive/115920613/rtl/ram.v | 115,920,613 | ram.v | v | 48 | 64 | [] | ['apache license'] | [] | [(25, 46)] | null | data/verilator_xmls/2c2a6d23-66cc-49fc-8576-ab079a89003d.xml | null | 7,258 | module | module ram #(
parameter RAM_FILENAME = "../../../roms/ram.hex"
) (
input clk,
input [12:0] address,
input w_en,
input [7:0] din,
output reg [7:0] dout
);
reg [7:0] ram_data[0:8191];
initial
$readmemh(RAM_FILENAME, ram_data, 0, 8191);
always @(posedge clk)
begin
dout <= ram_data[address];
if (w_en) ram_data[address] <= din;
end
endmodule | module ram #(
parameter RAM_FILENAME = "../../../roms/ram.hex"
) (
input clk,
input [12:0] address,
input w_en,
input [7:0] din,
output reg [7:0] dout
); |
reg [7:0] ram_data[0:8191];
initial
$readmemh(RAM_FILENAME, ram_data, 0, 8191);
always @(posedge clk)
begin
dout <= ram_data[address];
if (w_en) ram_data[address] <= din;
end
endmodule | 106 |
6,352 | data/full_repos/permissive/115920613/rtl/rom_basic.v | 115,920,613 | rom_basic.v | v | 42 | 64 | [] | ['apache license'] | [] | [(25, 41)] | null | data/verilator_xmls/bca791ce-c603-4e67-aac6-24b84ed0c7bc.xml | null | 7,259 | module | module rom_basic #(
parameter BASIC_FILENAME = "../../../roms/basic.hex"
) (
input clk,
input [11:0] address,
output reg [7:0] dout
);
reg [7:0] rom_data[0:4095];
initial
$readmemh(BASIC_FILENAME, rom_data, 0, 4095);
always @(posedge clk)
dout <= rom_data[address];
endmodule | module rom_basic #(
parameter BASIC_FILENAME = "../../../roms/basic.hex"
) (
input clk,
input [11:0] address,
output reg [7:0] dout
); |
reg [7:0] rom_data[0:4095];
initial
$readmemh(BASIC_FILENAME, rom_data, 0, 4095);
always @(posedge clk)
dout <= rom_data[address];
endmodule | 106 |
6,355 | data/full_repos/permissive/115920613/rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v | 115,920,613 | apple1_hx8k.v | v | 158 | 79 | [] | ['apache license'] | [] | null | line:83: before: ")" | null | 1: b"%Error: data/full_repos/permissive/115920613/rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v:67: Cannot find file containing module: 'pll'\n pll my_pll(\n ^~~\n ... Looked in:\n data/full_repos/permissive/115920613/rtl/boards/ice40hx8k-b-evn,data/full_repos/permissive/115920613/pll\n data/full_repos/permissive/115920613/rtl/boards/ice40hx8k-b-evn,data/full_repos/permissive/115920613/pll.v\n data/full_repos/permissive/115920613/rtl/boards/ice40hx8k-b-evn,data/full_repos/permissive/115920613/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Error: data/full_repos/permissive/115920613/rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v:77: Cannot find file containing module: 'SB_IO'\n SB_IO #(\n ^~~~~\n%Error: data/full_repos/permissive/115920613/rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v:85: Cannot find file containing module: 'SB_IO'\n SB_IO #(\n ^~~~~\n%Error: data/full_repos/permissive/115920613/rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v:98: Cannot find file containing module: 'debounce'\n debounce reset_button (\n ^~~~~~~~\n%Error: data/full_repos/permissive/115920613/rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v:107: Cannot find file containing module: 'debounce'\n debounce clr_button (\n ^~~~~~~~\n%Error: data/full_repos/permissive/115920613/rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v:117: Cannot find file containing module: 'debounce'\n debounce ps2_button (\n ^~~~~~~~\n%Error: data/full_repos/permissive/115920613/rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v:133: Cannot find file containing module: 'apple1'\n apple1 #(\n ^~~~~~\n%Error: Exiting due to 7 error(s)\n" | 7,262 | module | module apple1_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input clk,
input uart_rx,
output uart_tx,
output uart_cts,
input ps2_clk,
input ps2_din,
output vga_h_sync,
output vga_v_sync,
output reg vga_red,
output reg vga_grn,
output reg vga_blu,
output [7:0] led,
output [7:0] ledx,
input [3:0] button
);
wire clk25;
wire [15:0] pc_monitor;
assign led[7:0] = pc_monitor[7:0];
assign ledx[7:0] = ~pc_monitor[15:8];
pll my_pll(
.clock_in(clk),
.clock_out(clk25)
);
wire ps2__clk, ps2__din;
SB_IO #(
.PIN_TYPE(6'b000001),
.PULLUP(1'b1)
) my_ps2_clk (
.PACKAGE_PIN(ps2_clk),
.D_IN_0(ps2__clk),
);
SB_IO #(
.PIN_TYPE(6'b000001),
.PULLUP(1'b1)
) my_ps2_din (
.PACKAGE_PIN(ps2_din),
.D_IN_0(ps2__din),
);
wire reset_n;
debounce reset_button (
.clk25(clk25),
.rst(1'b0),
.sig_in(button[0]),
.sig_out(reset_n)
);
wire clr_screen_n;
debounce clr_button (
.clk25(clk25),
.rst(~reset_n),
.sig_in(button[1]),
.sig_out(clr_screen_n)
);
wire ps2_toggle;
reg ps2_select;
debounce ps2_button (
.clk25(clk25),
.rst(~reset_n),
.sig_in(button[2]),
.sig_out(ps2_toggle)
);
always @(posedge ps2_toggle)
ps2_select <= ~ps2_select;
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) my_apple1(
.clk25(clk25),
.rst_n(reset_n),
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.uart_cts(uart_cts),
.ps2_clk(ps2__clk),
.ps2_din(ps2__din),
.ps2_select(ps2_select),
.vga_h_sync(vga_h_sync),
.vga_v_sync(vga_v_sync),
.vga_red(vga_red),
.vga_grn(vga_grn),
.vga_blu(vga_blu),
.vga_cls(~clr_screen_n),
.pc_monitor(pc_monitor)
);
endmodule | module apple1_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input clk,
input uart_rx,
output uart_tx,
output uart_cts,
input ps2_clk,
input ps2_din,
output vga_h_sync,
output vga_v_sync,
output reg vga_red,
output reg vga_grn,
output reg vga_blu,
output [7:0] led,
output [7:0] ledx,
input [3:0] button
); |
wire clk25;
wire [15:0] pc_monitor;
assign led[7:0] = pc_monitor[7:0];
assign ledx[7:0] = ~pc_monitor[15:8];
pll my_pll(
.clock_in(clk),
.clock_out(clk25)
);
wire ps2__clk, ps2__din;
SB_IO #(
.PIN_TYPE(6'b000001),
.PULLUP(1'b1)
) my_ps2_clk (
.PACKAGE_PIN(ps2_clk),
.D_IN_0(ps2__clk),
);
SB_IO #(
.PIN_TYPE(6'b000001),
.PULLUP(1'b1)
) my_ps2_din (
.PACKAGE_PIN(ps2_din),
.D_IN_0(ps2__din),
);
wire reset_n;
debounce reset_button (
.clk25(clk25),
.rst(1'b0),
.sig_in(button[0]),
.sig_out(reset_n)
);
wire clr_screen_n;
debounce clr_button (
.clk25(clk25),
.rst(~reset_n),
.sig_in(button[1]),
.sig_out(clr_screen_n)
);
wire ps2_toggle;
reg ps2_select;
debounce ps2_button (
.clk25(clk25),
.rst(~reset_n),
.sig_in(button[2]),
.sig_out(ps2_toggle)
);
always @(posedge ps2_toggle)
ps2_select <= ~ps2_select;
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) my_apple1(
.clk25(clk25),
.rst_n(reset_n),
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.uart_cts(uart_cts),
.ps2_clk(ps2__clk),
.ps2_din(ps2__din),
.ps2_select(ps2_select),
.vga_h_sync(vga_h_sync),
.vga_v_sync(vga_v_sync),
.vga_red(vga_red),
.vga_grn(vga_grn),
.vga_blu(vga_blu),
.vga_cls(~clr_screen_n),
.pc_monitor(pc_monitor)
);
endmodule | 106 |
6,357 | data/full_repos/permissive/115920613/rtl/boards/olimex_ice40hx8k/apple1_hx8k.v | 115,920,613 | apple1_hx8k.v | v | 112 | 78 | [] | ['apache license'] | [] | null | line:59: before: ")" | null | 1: b"%Error: data/full_repos/permissive/115920613/rtl/boards/olimex_ice40hx8k/apple1_hx8k.v:56: Cannot find file containing module: 'pll'\n pll pll(\n ^~~\n ... Looked in:\n data/full_repos/permissive/115920613/rtl/boards/olimex_ice40hx8k,data/full_repos/permissive/115920613/pll\n data/full_repos/permissive/115920613/rtl/boards/olimex_ice40hx8k,data/full_repos/permissive/115920613/pll.v\n data/full_repos/permissive/115920613/rtl/boards/olimex_ice40hx8k,data/full_repos/permissive/115920613/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Error: data/full_repos/permissive/115920613/rtl/boards/olimex_ice40hx8k/apple1_hx8k.v:68: Cannot find file containing module: 'debounce'\n debounce reset_button (\n ^~~~~~~~\n%Error: data/full_repos/permissive/115920613/rtl/boards/olimex_ice40hx8k/apple1_hx8k.v:77: Cannot find file containing module: 'debounce'\n debounce clr_button (\n ^~~~~~~~\n%Error: data/full_repos/permissive/115920613/rtl/boards/olimex_ice40hx8k/apple1_hx8k.v:85: Cannot find file containing module: 'apple1'\n apple1 #(\n ^~~~~~\n%Error: Exiting due to 4 error(s)\n" | 7,264 | module | module apple1_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input clk,
input uart_rx,
output uart_tx,
output uart_cts,
input ps2_clk,
input ps2_din,
output vga_h_sync,
output vga_v_sync,
output [2:0] vga_r,
output [2:0] vga_g,
output [2:0] vga_b,
input [1:0] button
);
wire clk25;
pll pll(
.clock_in(clk),
.clock_out(clk25),
);
wire vga_red, vga_green, vga_blue;
assign vga_r[2:0] = {vga_red, vga_red, vga_red};
assign vga_g[2:0] = {vga_green, vga_green, vga_green};
assign vga_b[2:0] = {vga_blue, vga_blue, vga_blue};
wire reset_n;
debounce reset_button (
.clk25(clk25),
.rst(1'b0),
.sig_in(button[0]),
.sig_out(reset_n)
);
wire clr_screen_n;
debounce clr_button (
.clk25(clk25),
.rst(~reset_n),
.sig_in(button[1]),
.sig_out(clr_screen_n)
);
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) my_apple1(
.clk25(clk25),
.rst_n(reset_n),
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.uart_cts(uart_cts),
.ps2_clk(ps2_clk),
.ps2_din(ps2_din),
.ps2_select(1'b1),
.vga_h_sync(vga_h_sync),
.vga_v_sync(vga_v_sync),
.vga_red(vga_red),
.vga_grn(vga_green),
.vga_blu(vga_blue),
.vga_cls(~clr_screen_n),
);
endmodule | module apple1_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input clk,
input uart_rx,
output uart_tx,
output uart_cts,
input ps2_clk,
input ps2_din,
output vga_h_sync,
output vga_v_sync,
output [2:0] vga_r,
output [2:0] vga_g,
output [2:0] vga_b,
input [1:0] button
); |
wire clk25;
pll pll(
.clock_in(clk),
.clock_out(clk25),
);
wire vga_red, vga_green, vga_blue;
assign vga_r[2:0] = {vga_red, vga_red, vga_red};
assign vga_g[2:0] = {vga_green, vga_green, vga_green};
assign vga_b[2:0] = {vga_blue, vga_blue, vga_blue};
wire reset_n;
debounce reset_button (
.clk25(clk25),
.rst(1'b0),
.sig_in(button[0]),
.sig_out(reset_n)
);
wire clr_screen_n;
debounce clr_button (
.clk25(clk25),
.rst(~reset_n),
.sig_in(button[1]),
.sig_out(clr_screen_n)
);
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) my_apple1(
.clk25(clk25),
.rst_n(reset_n),
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.uart_cts(uart_cts),
.ps2_clk(ps2_clk),
.ps2_din(ps2_din),
.ps2_select(1'b1),
.vga_h_sync(vga_h_sync),
.vga_v_sync(vga_v_sync),
.vga_red(vga_red),
.vga_grn(vga_green),
.vga_blu(vga_blue),
.vga_cls(~clr_screen_n),
);
endmodule | 106 |
6,358 | data/full_repos/permissive/115920613/rtl/boards/spartan3e_starterkit/apple1_s3e_starterkit_top.v | 115,920,613 | apple1_s3e_starterkit_top.v | v | 93 | 83 | [] | ['apache license'] | [] | [(26, 92)] | null | null | 1: b"%Error: data/full_repos/permissive/115920613/rtl/boards/spartan3e_starterkit/apple1_s3e_starterkit_top.v:68: Cannot find file containing module: 'apple1'\n apple1 #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/115920613/rtl/boards/spartan3e_starterkit,data/full_repos/permissive/115920613/apple1\n data/full_repos/permissive/115920613/rtl/boards/spartan3e_starterkit,data/full_repos/permissive/115920613/apple1.v\n data/full_repos/permissive/115920613/rtl/boards/spartan3e_starterkit,data/full_repos/permissive/115920613/apple1.sv\n apple1\n apple1.v\n apple1.sv\n obj_dir/apple1\n obj_dir/apple1.v\n obj_dir/apple1.sv\n%Error: Exiting due to 1 error(s)\n" | 7,266 | module | module apple1_s3e_starterkit_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input CLK_50MHZ,
output UART_TXD,
input UART_RXD,
input PS2_KBCLK,
input PS2_KBDAT,
input BUTTON,
input SWITCH,
output VGA_R,
output VGA_G,
output VGA_B,
output VGA_HS,
output VGA_VS
);
reg clk25;
wire [15:0] pc_monitor;
wire rst_n;
assign rst_n = ~BUTTON;
always @(posedge CLK_50MHZ)
begin
clk25 <= ~clk25;
end
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) apple1_top(
.clk25(clk25),
.rst_n(rst_n),
.uart_rx(UART_RXD),
.uart_tx(UART_TXD),
.ps2_clk(PS2_KBCLK),
.ps2_din(PS2_KBDAT),
.ps2_select(SWITCH),
.vga_h_sync(VGA_HS),
.vga_v_sync(VGA_VS),
.vga_red(VGA_R),
.vga_grn(VGA_G),
.vga_blu(VGA_B),
.vga_cls(~rst_n),
.pc_monitor(pc_monitor)
);
endmodule | module apple1_s3e_starterkit_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input CLK_50MHZ,
output UART_TXD,
input UART_RXD,
input PS2_KBCLK,
input PS2_KBDAT,
input BUTTON,
input SWITCH,
output VGA_R,
output VGA_G,
output VGA_B,
output VGA_HS,
output VGA_VS
); |
reg clk25;
wire [15:0] pc_monitor;
wire rst_n;
assign rst_n = ~BUTTON;
always @(posedge CLK_50MHZ)
begin
clk25 <= ~clk25;
end
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) apple1_top(
.clk25(clk25),
.rst_n(rst_n),
.uart_rx(UART_RXD),
.uart_tx(UART_TXD),
.ps2_clk(PS2_KBCLK),
.ps2_din(PS2_KBDAT),
.ps2_select(SWITCH),
.vga_h_sync(VGA_HS),
.vga_v_sync(VGA_VS),
.vga_red(VGA_R),
.vga_grn(VGA_G),
.vga_blu(VGA_B),
.vga_cls(~rst_n),
.pc_monitor(pc_monitor)
);
endmodule | 106 |
6,359 | data/full_repos/permissive/115920613/rtl/boards/terasic_de0/apple1_de0_top.v | 115,920,613 | apple1_de0_top.v | v | 133 | 83 | [] | ['apache license'] | [] | [(25, 132)] | null | null | 1: b"%Error: data/full_repos/permissive/115920613/rtl/boards/terasic_de0/apple1_de0_top.v:71: Cannot find file containing module: 'apple1'\n apple1 #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/115920613/rtl/boards/terasic_de0,data/full_repos/permissive/115920613/apple1\n data/full_repos/permissive/115920613/rtl/boards/terasic_de0,data/full_repos/permissive/115920613/apple1.v\n data/full_repos/permissive/115920613/rtl/boards/terasic_de0,data/full_repos/permissive/115920613/apple1.sv\n apple1\n apple1.v\n apple1.sv\n obj_dir/apple1\n obj_dir/apple1.v\n obj_dir/apple1.sv\n%Error: data/full_repos/permissive/115920613/rtl/boards/terasic_de0/apple1_de0_top.v:102: Cannot find file containing module: 'segmentdisplay'\n segmentdisplay seg1(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115920613/rtl/boards/terasic_de0/apple1_de0_top.v:109: Cannot find file containing module: 'segmentdisplay'\n segmentdisplay seg2(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115920613/rtl/boards/terasic_de0/apple1_de0_top.v:116: Cannot find file containing module: 'segmentdisplay'\n segmentdisplay seg3(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115920613/rtl/boards/terasic_de0/apple1_de0_top.v:123: Cannot find file containing module: 'segmentdisplay'\n segmentdisplay seg4(\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 7,267 | module | module apple1_de0_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input CLOCK_50,
output UART_TXD,
input UART_RXD,
output UART_CTS,
output [7:0] LEDG,
input [2:0] BUTTON,
output [6:0] HEX0_D,
output [6:0] HEX1_D,
output [6:0] HEX2_D,
output [6:0] HEX3_D,
input PS2_KBCLK,
input PS2_KBDAT,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS
);
reg clk25;
wire [15:0] pc_monitor;
always @(posedge CLOCK_50)
begin
clk25 <= ~clk25;
end
wire r_bit, g_bit, b_bit;
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) apple1_top(
.clk25(clk25),
.rst_n(BUTTON[0]),
.uart_rx(UART_RXD),
.uart_tx(UART_TXD),
.uart_cts(UART_CTS),
.ps2_clk(PS2_KBCLK),
.ps2_din(PS2_KBDAT),
.ps2_select(1'b1),
.vga_h_sync(VGA_HS),
.vga_v_sync(VGA_VS),
.vga_red(r_bit),
.vga_grn(g_bit),
.vga_blu(b_bit),
.pc_monitor(pc_monitor)
);
assign VGA_R[3:0] = {4{r_bit}};
assign VGA_G[3:0] = {4{g_bit}};
assign VGA_B[3:0] = {4{b_bit}};
segmentdisplay seg1(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[3:0]),
.display_out(HEX0_D)
);
segmentdisplay seg2(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[7:4]),
.display_out(HEX1_D)
);
segmentdisplay seg3(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[11:8]),
.display_out(HEX2_D)
);
segmentdisplay seg4(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[15:12]),
.display_out(HEX3_D)
);
assign LEDG = 0;
endmodule | module apple1_de0_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input CLOCK_50,
output UART_TXD,
input UART_RXD,
output UART_CTS,
output [7:0] LEDG,
input [2:0] BUTTON,
output [6:0] HEX0_D,
output [6:0] HEX1_D,
output [6:0] HEX2_D,
output [6:0] HEX3_D,
input PS2_KBCLK,
input PS2_KBDAT,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS
); |
reg clk25;
wire [15:0] pc_monitor;
always @(posedge CLOCK_50)
begin
clk25 <= ~clk25;
end
wire r_bit, g_bit, b_bit;
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) apple1_top(
.clk25(clk25),
.rst_n(BUTTON[0]),
.uart_rx(UART_RXD),
.uart_tx(UART_TXD),
.uart_cts(UART_CTS),
.ps2_clk(PS2_KBCLK),
.ps2_din(PS2_KBDAT),
.ps2_select(1'b1),
.vga_h_sync(VGA_HS),
.vga_v_sync(VGA_VS),
.vga_red(r_bit),
.vga_grn(g_bit),
.vga_blu(b_bit),
.pc_monitor(pc_monitor)
);
assign VGA_R[3:0] = {4{r_bit}};
assign VGA_G[3:0] = {4{g_bit}};
assign VGA_B[3:0] = {4{b_bit}};
segmentdisplay seg1(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[3:0]),
.display_out(HEX0_D)
);
segmentdisplay seg2(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[7:4]),
.display_out(HEX1_D)
);
segmentdisplay seg3(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[11:8]),
.display_out(HEX2_D)
);
segmentdisplay seg4(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[15:12]),
.display_out(HEX3_D)
);
assign LEDG = 0;
endmodule | 106 |
6,361 | data/full_repos/permissive/115920613/rtl/boards/tinyfpga_b2/clock_pll.v | 115,920,613 | clock_pll.v | v | 39 | 144 | [] | [] | [] | null | line:25: before: "." | null | 1: b"%Error: data/full_repos/permissive/115920613/rtl/boards/tinyfpga_b2/clock_pll.v:11: Cannot find file containing module: 'SB_PLL40_CORE'\nSB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK),\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115920613/rtl/boards/tinyfpga_b2,data/full_repos/permissive/115920613/SB_PLL40_CORE\n data/full_repos/permissive/115920613/rtl/boards/tinyfpga_b2,data/full_repos/permissive/115920613/SB_PLL40_CORE.v\n data/full_repos/permissive/115920613/rtl/boards/tinyfpga_b2,data/full_repos/permissive/115920613/SB_PLL40_CORE.sv\n SB_PLL40_CORE\n SB_PLL40_CORE.v\n SB_PLL40_CORE.sv\n obj_dir/SB_PLL40_CORE\n obj_dir/SB_PLL40_CORE.v\n obj_dir/SB_PLL40_CORE.sv\n%Error: Exiting due to 1 error(s)\n" | 7,270 | module | module clock_pll(REFERENCECLK,
PLLOUTCORE,
PLLOUTGLOBAL,
RESET);
input REFERENCECLK;
input RESET;
output PLLOUTCORE;
output PLLOUTGLOBAL;
SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK),
.PLLOUTCORE(PLLOUTCORE),
.PLLOUTGLOBAL(PLLOUTGLOBAL),
.EXTFEEDBACK(),
.DYNAMICDELAY(),
.RESETB(RESET),
.BYPASS(1'b0),
.LATCHINPUTVALUE(),
.LOCK(),
.SDI(),
.SDO(),
.SCLK());
defparam clock_pll_inst.DIVR = 4'b0000;
defparam clock_pll_inst.DIVF = 7'b0110001;
defparam clock_pll_inst.DIVQ = 3'b101;
defparam clock_pll_inst.FILTER_RANGE = 3'b001;
defparam clock_pll_inst.FEEDBACK_PATH = "SIMPLE";
defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
defparam clock_pll_inst.FDA_FEEDBACK = 4'b0000;
defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
defparam clock_pll_inst.FDA_RELATIVE = 4'b0000;
defparam clock_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
defparam clock_pll_inst.PLLOUT_SELECT = "GENCLK";
defparam clock_pll_inst.ENABLE_ICEGATE = 1'b0;
endmodule | module clock_pll(REFERENCECLK,
PLLOUTCORE,
PLLOUTGLOBAL,
RESET); |
input REFERENCECLK;
input RESET;
output PLLOUTCORE;
output PLLOUTGLOBAL;
SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK),
.PLLOUTCORE(PLLOUTCORE),
.PLLOUTGLOBAL(PLLOUTGLOBAL),
.EXTFEEDBACK(),
.DYNAMICDELAY(),
.RESETB(RESET),
.BYPASS(1'b0),
.LATCHINPUTVALUE(),
.LOCK(),
.SDI(),
.SDO(),
.SCLK());
defparam clock_pll_inst.DIVR = 4'b0000;
defparam clock_pll_inst.DIVF = 7'b0110001;
defparam clock_pll_inst.DIVQ = 3'b101;
defparam clock_pll_inst.FILTER_RANGE = 3'b001;
defparam clock_pll_inst.FEEDBACK_PATH = "SIMPLE";
defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
defparam clock_pll_inst.FDA_FEEDBACK = 4'b0000;
defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
defparam clock_pll_inst.FDA_RELATIVE = 4'b0000;
defparam clock_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
defparam clock_pll_inst.PLLOUT_SELECT = "GENCLK";
defparam clock_pll_inst.ENABLE_ICEGATE = 1'b0;
endmodule | 106 |
6,363 | data/full_repos/permissive/115920613/rtl/cpu/aholme_6502.v | 115,920,613 | aholme_6502.v | v | 33 | 28 | [] | [] | [] | [(1, 32)] | null | null | 1: b"%Error: data/full_repos/permissive/115920613/rtl/cpu/aholme_6502.v:16: Cannot find file containing module: 'chip_6502'\n chip_6502 aholme_cpu (\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115920613/rtl/cpu,data/full_repos/permissive/115920613/chip_6502\n data/full_repos/permissive/115920613/rtl/cpu,data/full_repos/permissive/115920613/chip_6502.v\n data/full_repos/permissive/115920613/rtl/cpu,data/full_repos/permissive/115920613/chip_6502.sv\n chip_6502\n chip_6502.v\n chip_6502.sv\n obj_dir/chip_6502\n obj_dir/chip_6502.v\n obj_dir/chip_6502.sv\n%Error: Exiting due to 1 error(s)\n" | 7,272 | module | module aholme_6502(
input clk,
input enable,
input reset,
output [15:0] ab,
input [7:0] dbi,
output [7:0] dbo,
output we,
input irq,
input nmi,
input ready
);
wire we_c;
chip_6502 aholme_cpu (
.clk(clk),
.phi(clk & enable),
.res(~reset),
.so(1'b0),
.rdy(ready),
.nmi(nmi_n),
.irq(irq_n),
.rw(we_c),
.dbi(dbi),
.dbo(dbo),
.ab(ab)
);
assign we = ~we_c;
endmodule | module aholme_6502(
input clk,
input enable,
input reset,
output [15:0] ab,
input [7:0] dbi,
output [7:0] dbo,
output we,
input irq,
input nmi,
input ready
); |
wire we_c;
chip_6502 aholme_cpu (
.clk(clk),
.phi(clk & enable),
.res(~reset),
.so(1'b0),
.rdy(ready),
.nmi(nmi_n),
.irq(irq_n),
.rw(we_c),
.dbi(dbi),
.dbo(dbo),
.ab(ab)
);
assign we = ~we_c;
endmodule | 106 |
6,364 | data/full_repos/permissive/115920613/rtl/cpu/arlet_6502.v | 115,920,613 | arlet_6502.v | v | 73 | 80 | [] | ['apache license'] | [] | [(25, 72)] | null | null | 1: b"%Error: data/full_repos/permissive/115920613/rtl/cpu/arlet_6502.v:43: Cannot find file containing module: 'cpu'\n cpu arlet_cpu(\n ^~~\n ... Looked in:\n data/full_repos/permissive/115920613/rtl/cpu,data/full_repos/permissive/115920613/cpu\n data/full_repos/permissive/115920613/rtl/cpu,data/full_repos/permissive/115920613/cpu.v\n data/full_repos/permissive/115920613/rtl/cpu,data/full_repos/permissive/115920613/cpu.sv\n cpu\n cpu.v\n cpu.sv\n obj_dir/cpu\n obj_dir/cpu.v\n obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s)\n" | 7,273 | module | module arlet_6502(
input clk,
input enable,
input rst,
output reg [15:0] ab,
input [7:0] dbi,
output reg [7:0] dbo,
output reg we,
input irq_n,
input nmi_n,
input ready,
output [15:0] pc_monitor
);
wire [7:0] dbo_c;
wire [15:0] ab_c;
wire we_c;
cpu arlet_cpu(
.clk(clk),
.reset(rst),
.AB(ab_c),
.DI(dbi),
.DO(dbo_c),
.WE(we_c),
.IRQ(~irq_n),
.NMI(~nmi_n),
.RDY(ready),
.PC_MONITOR(pc_monitor)
);
always @(posedge clk or posedge rst)
begin
if (rst)
begin
ab <= 16'd0;
dbo <= 8'd0;
we <= 1'b0;
end
else
if (enable)
begin
ab <= ab_c;
dbo <= dbo_c;
we <= we_c;
end
end
endmodule | module arlet_6502(
input clk,
input enable,
input rst,
output reg [15:0] ab,
input [7:0] dbi,
output reg [7:0] dbo,
output reg we,
input irq_n,
input nmi_n,
input ready,
output [15:0] pc_monitor
); |
wire [7:0] dbo_c;
wire [15:0] ab_c;
wire we_c;
cpu arlet_cpu(
.clk(clk),
.reset(rst),
.AB(ab_c),
.DI(dbi),
.DO(dbo_c),
.WE(we_c),
.IRQ(~irq_n),
.NMI(~nmi_n),
.RDY(ready),
.PC_MONITOR(pc_monitor)
);
always @(posedge clk or posedge rst)
begin
if (rst)
begin
ab <= 16'd0;
dbo <= 8'd0;
we <= 1'b0;
end
else
if (enable)
begin
ab <= ab_c;
dbo <= dbo_c;
we <= we_c;
end
end
endmodule | 106 |
6,366 | data/full_repos/permissive/115920613/rtl/led_and_key/led_and_key.v | 115,920,613 | led_and_key.v | v | 168 | 89 | [] | [] | [] | [(1, 167)] | null | null | 1: b"%Error: data/full_repos/permissive/115920613/rtl/led_and_key/led_and_key.v:44: Cannot find file containing module: 'SB_IO'\n SB_IO #(\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115920613/rtl/led_and_key,data/full_repos/permissive/115920613/SB_IO\n data/full_repos/permissive/115920613/rtl/led_and_key,data/full_repos/permissive/115920613/SB_IO.v\n data/full_repos/permissive/115920613/rtl/led_and_key,data/full_repos/permissive/115920613/SB_IO.sv\n SB_IO\n SB_IO.v\n SB_IO.sv\n obj_dir/SB_IO\n obj_dir/SB_IO.v\n obj_dir/SB_IO.sv\n%Error: data/full_repos/permissive/115920613/rtl/led_and_key/led_and_key.v:74: Cannot find file containing module: 'tm1638'\n tm1638 u_tm1638 (\n ^~~~~~\n%Error: Exiting due to 2 error(s)\n" | 7,278 | module | module ledAndKey(
input clk,
input clk_en,
input rst,
input [3:0] display,
input [7:0] digit1,
input [7:0] digit2,
input [7:0] digit3,
input [7:0] digit4,
input [7:0] digit5,
input [7:0] digit6,
input [7:0] digit7,
input [7:0] digit8,
input [7:0] leds,
output reg [7:0] keys,
output reg tm_cs,
output tm_clk,
inout tm_dio
);
localparam
HIGH = 1'b1,
LOW = 1'b0;
localparam [7:0]
C_READ = 8'b01000010,
C_WRITE = 8'b01000000,
C_DISP = 8'b10001111,
C_ADDR = 8'b11000000;
reg counter;
reg [5:0] instruction_step;
reg tm_rw;
wire dio_in, dio_out;
SB_IO #(
.PIN_TYPE(6'b101001),
.PULLUP(1'b1)
) tm_dio_io (
.PACKAGE_PIN(tm_dio),
.OUTPUT_ENABLE(tm_rw),
.D_IN_0(dio_in),
.D_OUT_0(dio_out)
);
reg tm_latch;
wire busy;
wire [7:0] tm_data, tm_in;
reg [7:0] tm_out;
assign tm_in = tm_data;
assign tm_data = tm_rw ? tm_out : 8'hZZ;
tm1638 u_tm1638 (
.clk(clk),
.clk_en(clk_en),
.rst(rst),
.data_latch(tm_latch),
.data(tm_data),
.rw(tm_rw),
.busy(busy),
.sclk(tm_clk),
.dio_in(dio_in),
.dio_out(dio_out)
);
always @(posedge clk) begin
if (clk_en) begin
if (rst) begin
instruction_step <= 6'b0;
tm_cs <= HIGH;
tm_rw <= HIGH;
counter <= 1'b0;
keys <= 8'b0;
end else begin
if (counter && ~busy) begin
case (instruction_step)
1: {tm_cs, tm_rw} <= {LOW, HIGH};
2: {tm_latch, tm_out} <= {HIGH, C_READ};
3: {tm_latch, tm_rw} <= {HIGH, LOW};
4: {keys[7], keys[3]} <= {tm_in[0], tm_in[4]};
5: {tm_latch} <= {HIGH};
6: {keys[6], keys[2]} <= {tm_in[0], tm_in[4]};
7: {tm_latch} <= {HIGH};
8: {keys[5], keys[1]} <= {tm_in[0], tm_in[4]};
9: {tm_latch} <= {HIGH};
10: {keys[4], keys[0]} <= {tm_in[0], tm_in[4]};
11: {tm_cs} <= {HIGH};
12: {tm_cs, tm_rw} <= {LOW, HIGH};
13: {tm_latch, tm_out} <= {HIGH, C_WRITE};
14: {tm_cs} <= {HIGH};
15: {tm_cs, tm_rw} <= {LOW, HIGH};
16: {tm_latch, tm_out} <= {HIGH, C_ADDR};
17: {tm_latch, tm_out} <= {HIGH, digit1};
18: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[7]}};
19: {tm_latch, tm_out} <= {HIGH, digit2};
20: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[6]}};
21: {tm_latch, tm_out} <= {HIGH, digit3};
22: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[5]}};
23: {tm_latch, tm_out} <= {HIGH, digit4};
24: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[4]}};
25: {tm_latch, tm_out} <= {HIGH, digit5};
26: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[3]}};
27: {tm_latch, tm_out} <= {HIGH, digit6};
28: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[2]}};
29: {tm_latch, tm_out} <= {HIGH, digit7};
30: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[1]}};
31: {tm_latch, tm_out} <= {HIGH, digit8};
32: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[0]}};
33: {tm_cs} <= {HIGH};
34: {tm_cs, tm_rw} <= {LOW, HIGH};
35: {tm_latch, tm_out} <= {HIGH, {4'b1000, display}};
36: {tm_cs, instruction_step} <= {HIGH, 6'b0};
endcase
instruction_step <= instruction_step + 1;
end else if (busy) begin
tm_latch <= LOW;
end
counter <= ~counter;
end
end
end
endmodule | module ledAndKey(
input clk,
input clk_en,
input rst,
input [3:0] display,
input [7:0] digit1,
input [7:0] digit2,
input [7:0] digit3,
input [7:0] digit4,
input [7:0] digit5,
input [7:0] digit6,
input [7:0] digit7,
input [7:0] digit8,
input [7:0] leds,
output reg [7:0] keys,
output reg tm_cs,
output tm_clk,
inout tm_dio
); |
localparam
HIGH = 1'b1,
LOW = 1'b0;
localparam [7:0]
C_READ = 8'b01000010,
C_WRITE = 8'b01000000,
C_DISP = 8'b10001111,
C_ADDR = 8'b11000000;
reg counter;
reg [5:0] instruction_step;
reg tm_rw;
wire dio_in, dio_out;
SB_IO #(
.PIN_TYPE(6'b101001),
.PULLUP(1'b1)
) tm_dio_io (
.PACKAGE_PIN(tm_dio),
.OUTPUT_ENABLE(tm_rw),
.D_IN_0(dio_in),
.D_OUT_0(dio_out)
);
reg tm_latch;
wire busy;
wire [7:0] tm_data, tm_in;
reg [7:0] tm_out;
assign tm_in = tm_data;
assign tm_data = tm_rw ? tm_out : 8'hZZ;
tm1638 u_tm1638 (
.clk(clk),
.clk_en(clk_en),
.rst(rst),
.data_latch(tm_latch),
.data(tm_data),
.rw(tm_rw),
.busy(busy),
.sclk(tm_clk),
.dio_in(dio_in),
.dio_out(dio_out)
);
always @(posedge clk) begin
if (clk_en) begin
if (rst) begin
instruction_step <= 6'b0;
tm_cs <= HIGH;
tm_rw <= HIGH;
counter <= 1'b0;
keys <= 8'b0;
end else begin
if (counter && ~busy) begin
case (instruction_step)
1: {tm_cs, tm_rw} <= {LOW, HIGH};
2: {tm_latch, tm_out} <= {HIGH, C_READ};
3: {tm_latch, tm_rw} <= {HIGH, LOW};
4: {keys[7], keys[3]} <= {tm_in[0], tm_in[4]};
5: {tm_latch} <= {HIGH};
6: {keys[6], keys[2]} <= {tm_in[0], tm_in[4]};
7: {tm_latch} <= {HIGH};
8: {keys[5], keys[1]} <= {tm_in[0], tm_in[4]};
9: {tm_latch} <= {HIGH};
10: {keys[4], keys[0]} <= {tm_in[0], tm_in[4]};
11: {tm_cs} <= {HIGH};
12: {tm_cs, tm_rw} <= {LOW, HIGH};
13: {tm_latch, tm_out} <= {HIGH, C_WRITE};
14: {tm_cs} <= {HIGH};
15: {tm_cs, tm_rw} <= {LOW, HIGH};
16: {tm_latch, tm_out} <= {HIGH, C_ADDR};
17: {tm_latch, tm_out} <= {HIGH, digit1};
18: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[7]}};
19: {tm_latch, tm_out} <= {HIGH, digit2};
20: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[6]}};
21: {tm_latch, tm_out} <= {HIGH, digit3};
22: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[5]}};
23: {tm_latch, tm_out} <= {HIGH, digit4};
24: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[4]}};
25: {tm_latch, tm_out} <= {HIGH, digit5};
26: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[3]}};
27: {tm_latch, tm_out} <= {HIGH, digit6};
28: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[2]}};
29: {tm_latch, tm_out} <= {HIGH, digit7};
30: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[1]}};
31: {tm_latch, tm_out} <= {HIGH, digit8};
32: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[0]}};
33: {tm_cs} <= {HIGH};
34: {tm_cs, tm_rw} <= {LOW, HIGH};
35: {tm_latch, tm_out} <= {HIGH, {4'b1000, display}};
36: {tm_cs, instruction_step} <= {HIGH, 6'b0};
endcase
instruction_step <= instruction_step + 1;
end else if (busy) begin
tm_latch <= LOW;
end
counter <= ~counter;
end
end
end
endmodule | 106 |
6,368 | data/full_repos/permissive/115920613/rtl/uart/uart.v | 115,920,613 | uart.v | v | 170 | 84 | [] | ['apache license'] | [] | [(25, 169)] | null | null | 1: b"%Error: data/full_repos/permissive/115920613/rtl/uart/uart.v:47: Cannot find file containing module: 'async_transmitter'\n async_transmitter #(ClkFrequency, Baud) my_tx (\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115920613/rtl/uart,data/full_repos/permissive/115920613/async_transmitter\n data/full_repos/permissive/115920613/rtl/uart,data/full_repos/permissive/115920613/async_transmitter.v\n data/full_repos/permissive/115920613/rtl/uart,data/full_repos/permissive/115920613/async_transmitter.sv\n async_transmitter\n async_transmitter.v\n async_transmitter.sv\n obj_dir/async_transmitter\n obj_dir/async_transmitter.v\n obj_dir/async_transmitter.sv\n%Error: data/full_repos/permissive/115920613/rtl/uart/uart.v:61: Cannot find file containing module: 'async_receiver'\n async_receiver #(ClkFrequency, Baud, Oversampling) my_rx(\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 7,283 | module | module uart(
input clk,
input enable,
input rst,
input [1:0] address,
input w_en,
input [7:0] din,
output reg [7:0] dout,
input uart_rx,
output uart_tx,
output uart_cts
);
parameter ClkFrequency = 25000000;
parameter Baud = 115200;
parameter Oversampling = 16;
reg uart_tx_stb, uart_tx_init;
reg [7:0] uart_tx_byte;
wire uart_tx_status;
async_transmitter #(ClkFrequency, Baud) my_tx (
.clk(clk),
.rst(rst),
.TxD_start(uart_tx_stb),
.TxD_data(uart_tx_byte),
.TxD(uart_tx),
.TxD_busy(uart_tx_status)
);
wire uart_rx_stb, rx_idle, rx_end;
wire [7:0] rx_data;
reg uart_rx_status, uart_rx_ack;
reg [7:0] uart_rx_byte;
async_receiver #(ClkFrequency, Baud, Oversampling) my_rx(
.clk(clk),
.rst(rst),
.RxD(uart_rx),
.RxD_data_ready(uart_rx_stb),
.RxD_data(rx_data),
.RxD_idle(rx_idle),
.RxD_endofpacket(rx_end)
);
always @(posedge clk or posedge rst)
begin
if (rst)
begin
uart_rx_status <= 'b0;
uart_rx_byte <= 8'd0;
end
else
begin
if (uart_rx_stb && ~uart_rx_status)
begin
uart_rx_status <= 'b1;
uart_rx_byte <= rx_data;
end
if (uart_rx_ack)
uart_rx_status <= 'b0;
end
end
assign uart_cts = ~rx_idle || uart_rx_status;
localparam UART_RX = 2'b00;
localparam UART_RXCR = 2'b01;
localparam UART_TX = 2'b10;
localparam UART_TXCR = 2'b11;
always @(posedge clk or posedge rst)
begin
if (rst)
begin
dout <= 8'd0;
uart_tx_init <= 0;
uart_tx_stb <= 0;
uart_tx_byte <= 8'd0;
uart_rx_ack <= 0;
end
else
begin
uart_tx_stb <= 0;
uart_rx_ack <= 0;
case (address)
UART_RX:
begin
dout <= {1'b1, uart_rx_byte[6:0]};
if (~w_en && ~uart_rx_ack && uart_rx_status && enable)
uart_rx_ack <= 1'b1;
end
UART_RXCR:
begin
dout <= {uart_rx_status, 7'b0};
end
UART_TX:
begin
dout <= {uart_tx_status, 7'd0};
if (w_en)
begin
if (~uart_tx_status && uart_tx_init)
begin
uart_tx_byte <= {1'b0, din[6:0]};
uart_tx_stb <= 1;
end
else if (~uart_tx_init)
uart_tx_init <= 1 && enable;
end
end
UART_TXCR:
begin
dout <= 8'b0;
end
endcase
end
end
endmodule | module uart(
input clk,
input enable,
input rst,
input [1:0] address,
input w_en,
input [7:0] din,
output reg [7:0] dout,
input uart_rx,
output uart_tx,
output uart_cts
); |
parameter ClkFrequency = 25000000;
parameter Baud = 115200;
parameter Oversampling = 16;
reg uart_tx_stb, uart_tx_init;
reg [7:0] uart_tx_byte;
wire uart_tx_status;
async_transmitter #(ClkFrequency, Baud) my_tx (
.clk(clk),
.rst(rst),
.TxD_start(uart_tx_stb),
.TxD_data(uart_tx_byte),
.TxD(uart_tx),
.TxD_busy(uart_tx_status)
);
wire uart_rx_stb, rx_idle, rx_end;
wire [7:0] rx_data;
reg uart_rx_status, uart_rx_ack;
reg [7:0] uart_rx_byte;
async_receiver #(ClkFrequency, Baud, Oversampling) my_rx(
.clk(clk),
.rst(rst),
.RxD(uart_rx),
.RxD_data_ready(uart_rx_stb),
.RxD_data(rx_data),
.RxD_idle(rx_idle),
.RxD_endofpacket(rx_end)
);
always @(posedge clk or posedge rst)
begin
if (rst)
begin
uart_rx_status <= 'b0;
uart_rx_byte <= 8'd0;
end
else
begin
if (uart_rx_stb && ~uart_rx_status)
begin
uart_rx_status <= 'b1;
uart_rx_byte <= rx_data;
end
if (uart_rx_ack)
uart_rx_status <= 'b0;
end
end
assign uart_cts = ~rx_idle || uart_rx_status;
localparam UART_RX = 2'b00;
localparam UART_RXCR = 2'b01;
localparam UART_TX = 2'b10;
localparam UART_TXCR = 2'b11;
always @(posedge clk or posedge rst)
begin
if (rst)
begin
dout <= 8'd0;
uart_tx_init <= 0;
uart_tx_stb <= 0;
uart_tx_byte <= 8'd0;
uart_rx_ack <= 0;
end
else
begin
uart_tx_stb <= 0;
uart_rx_ack <= 0;
case (address)
UART_RX:
begin
dout <= {1'b1, uart_rx_byte[6:0]};
if (~w_en && ~uart_rx_ack && uart_rx_status && enable)
uart_rx_ack <= 1'b1;
end
UART_RXCR:
begin
dout <= {uart_rx_status, 7'b0};
end
UART_TX:
begin
dout <= {uart_tx_status, 7'd0};
if (w_en)
begin
if (~uart_tx_status && uart_tx_init)
begin
uart_tx_byte <= {1'b0, din[6:0]};
uart_tx_stb <= 1;
end
else if (~uart_tx_init)
uart_tx_init <= 1 && enable;
end
end
UART_TXCR:
begin
dout <= 8'b0;
end
endcase
end
end
endmodule | 106 |
6,370 | data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v | 115,920,613 | apple1_tb.v | v | 92 | 79 | [] | ['apache license'] | [] | null | line:65: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #40 rst_n = 1\'b1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:48: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("apple1_top_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:49: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #180000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #400\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #400\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #400\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #800\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #1600\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #1000000 $display("Stopping...");\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #20 clk25 = !clk25;\n ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,287 | module | module apple1_tb #(
parameter BASIC_FILENAME = "../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../roms/ram.hex",
parameter VRAM_FILENAME = "../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../roms/wozmon.hex"
);
reg clk25, uart_rx, rst_n;
wire uart_tx, uart_cts;
initial begin
clk25 = 1'b0;
uart_rx = 1'b1;
rst_n = 1'b0;
#40 rst_n = 1'b1;
$display("Starting...");
$dumpfile("apple1_top_tb.vcd");
$dumpvars;
#180000
uart_rx = 1'b0;
#400
uart_rx = 1'b1;
#400
uart_rx = 1'b0;
#400
uart_rx = 1'b1;
#800
uart_rx = 1'b0;
#1600
uart_rx = 1'b1;
#1000000 $display("Stopping...");
$finish;
end
always
#20 clk25 = !clk25;
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) core_top (
.clk25(clk25),
.rst_n(rst_n),
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.uart_cts(uart_cts)
);
endmodule | module apple1_tb #(
parameter BASIC_FILENAME = "../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../roms/ram.hex",
parameter VRAM_FILENAME = "../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../roms/wozmon.hex"
); |
reg clk25, uart_rx, rst_n;
wire uart_tx, uart_cts;
initial begin
clk25 = 1'b0;
uart_rx = 1'b1;
rst_n = 1'b0;
#40 rst_n = 1'b1;
$display("Starting...");
$dumpfile("apple1_top_tb.vcd");
$dumpvars;
#180000
uart_rx = 1'b0;
#400
uart_rx = 1'b1;
#400
uart_rx = 1'b0;
#400
uart_rx = 1'b1;
#800
uart_rx = 1'b0;
#1600
uart_rx = 1'b1;
#1000000 $display("Stopping...");
$finish;
end
always
#20 clk25 = !clk25;
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) core_top (
.clk25(clk25),
.rst_n(rst_n),
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.uart_cts(uart_cts)
);
endmodule | 106 |
6,372 | data/full_repos/permissive/115920613/tools/iverilog/vga_tb.v | 115,920,613 | vga_tb.v | v | 95 | 79 | [] | ['apache license'] | [] | null | line:68: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/vga_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/vga_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Error: data/full_repos/permissive/115920613/tools/iverilog/vga_tb.v:51: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("vga_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115920613/tools/iverilog/vga_tb.v:52: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/vga_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #50000000 $display("Stopping...");\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/vga_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #20 clk25 = !clk25;\n ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,289 | module | module vga_tb;
reg clk25, rst, address, w_en, blink_clken;
reg [7:0] din;
wire vga_h_sync, vga_v_sync, vga_red, vga_grn, vga_blu;
initial begin
clk25 = 1'b0;
rst = 1'b0;
address = 1'b0;
w_en = 1'b0;
blink_clken = 1'b0;
din = 8'd0;
#5
rst = 1'b1;
#5
rst = 1'b0;
$display("Starting...");
$dumpfile("vga_tb.vcd");
$dumpvars;
#50000000 $display("Stopping...");
$finish;
end
always
#20 clk25 = !clk25;
vga my_vga (
.clk25(clk25),
.enable(1'b1),
.rst(rst),
.vga_h_sync(vga_h_sync),
.vga_v_sync(vga_v_sync),
.vga_red(vga_red),
.vga_grn(vga_grn),
.vga_blu(vga_blu),
.address(address),
.w_en(w_en),
.din(din)
);
endmodule | module vga_tb; |
reg clk25, rst, address, w_en, blink_clken;
reg [7:0] din;
wire vga_h_sync, vga_v_sync, vga_red, vga_grn, vga_blu;
initial begin
clk25 = 1'b0;
rst = 1'b0;
address = 1'b0;
w_en = 1'b0;
blink_clken = 1'b0;
din = 8'd0;
#5
rst = 1'b1;
#5
rst = 1'b0;
$display("Starting...");
$dumpfile("vga_tb.vcd");
$dumpvars;
#50000000 $display("Stopping...");
$finish;
end
always
#20 clk25 = !clk25;
vga my_vga (
.clk25(clk25),
.enable(1'b1),
.rst(rst),
.vga_h_sync(vga_h_sync),
.vga_v_sync(vga_v_sync),
.vga_red(vga_red),
.vga_grn(vga_grn),
.vga_blu(vga_blu),
.address(address),
.w_en(w_en),
.din(din)
);
endmodule | 106 |
6,373 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/Add16Bit.v | 116,048,589 | Add16Bit.v | v | 30 | 83 | [] | [] | [] | [(21, 29)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/Add16Bit.v\n%Error: Exiting due to 4 error(s)\n' | 7,291 | module | module Add16Bit(
input [15:0] PC,
input [15:0] Immediate,
output [15:0] PCPlusImm
);
assign PCPlusImm = PC + Immediate;
endmodule | module Add16Bit(
input [15:0] PC,
input [15:0] Immediate,
output [15:0] PCPlusImm
); |
assign PCPlusImm = PC + Immediate;
endmodule | 0 |
6,374 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/AddOne.v | 116,048,589 | AddOne.v | v | 28 | 83 | [] | [] | [] | [(21, 28)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/AddOne.v\n%Error: Exiting due to 4 error(s)\n' | 7,292 | module | module AddOne(
input [15:0] PC,
output [15:0] PCPlusOne
);
assign PCPlusOne = PC + 1;
endmodule | module AddOne(
input [15:0] PC,
output [15:0] PCPlusOne
); |
assign PCPlusOne = PC + 1;
endmodule | 0 |
6,375 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/AddTwo.v | 116,048,589 | AddTwo.v | v | 30 | 83 | [] | [] | [] | [(21, 28)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/AddTwo.v\n%Error: Exiting due to 4 error(s)\n' | 7,293 | module | module AddTwo(
input [15:0] PC,
output [15:0] PCPlusTwo
);
assign PCPlusTwo = PC + 1;
endmodule | module AddTwo(
input [15:0] PC,
output [15:0] PCPlusTwo
); |
assign PCPlusTwo = PC + 1;
endmodule | 0 |
6,376 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/ALU.v | 116,048,589 | ALU.v | v | 159 | 106 | [] | [] | [] | [(21, 158)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/ALU.v\n%Error: Exiting due to 4 error(s)\n' | 7,294 | module | module ALU(
input [15:0] aInput,
input [15:0] bInput,
input [2:0] opCode,
input sub,
input aInvert,
input bInvert,
input ShiftImm,
output [15:0] res,
output [4:0] CLFZN
);
reg [15:0] A;
reg [15:0] B;
reg [15:0] aluResult;
assign res = aluResult;
assign CLFZN[0] = ($signed(A) < $signed(B));
assign CLFZN[1] = (A == B);
assign CLFZN[2] = (A[15] == B[15]) && (aluResult[15] != A[15]);
assign CLFZN[3] = (A < B);
assign CLFZN[4] = (A[15] && B[15]) || (!aluResult[15] && ( (!A[15] && B[15]) || (A[15] && !B[15])));
always @(*) begin
if (aInvert) A = ~aInput;
else A = aInput;
if (bInvert) B = ~bInput;
else B = bInput;
end
always@(*) begin
case (opCode)
3'b000:
begin
aluResult = A + B + sub;
end
3'b001:
begin
aluResult = A & B;
end
3'b010:
begin
aluResult = A | B;
end
3'b011:
begin
aluResult = A ^ B;
end
3'b101:
begin
if (!ShiftImm && B>=15)
aluResult = A <<< 15;
else
case(B[3:0])
0: aluResult = A <<< 0;
1: aluResult = A <<< 1;
2: aluResult = A <<< 2;
3: aluResult = A <<< 3;
4: aluResult = A <<< 4;
5: aluResult = A <<< 5;
6: aluResult = A <<< 6;
7: aluResult = A <<< 7;
8: aluResult = A <<< 8;
9: aluResult = A <<< 9;
10: aluResult = A <<< 10;
11: aluResult = A <<< 11;
12: aluResult = A <<< 12;
13: aluResult = A <<< 13;
14: aluResult = A <<< 14;
15: aluResult = A <<< 15;
default: aluResult = A <<< 0;
endcase
end
3'b110:
begin
if (!ShiftImm && B>=15)
aluResult = A >>> 15;
else
case(B[3:0])
0: aluResult = A >>> 0;
1: aluResult = A >>> 1;
2: aluResult = A >>> 2;
3: aluResult = A >>> 3;
4: aluResult = A >>> 4;
5: aluResult = A >>> 5;
6: aluResult = A >>> 6;
7: aluResult = A >>> 7;
8: aluResult = A >>> 8;
9: aluResult = A >>> 9;
10: aluResult = A >>> 10;
11: aluResult = A >>> 11;
12: aluResult = A >>> 12;
13: aluResult = A >>> 13;
14: aluResult = A >>> 14;
15: aluResult = A >>> 15;
default: aluResult = A >>> 0;
endcase
end
3'b111:
begin
if (!ShiftImm && B>=15)
aluResult = A >> 15;
else
case(B[3:0])
0: aluResult = A >> 0;
1: aluResult = A >> 1;
2: aluResult = A >> 2;
3: aluResult = A >> 3;
4: aluResult = A >> 4;
5: aluResult = A >> 5;
6: aluResult = A >> 6;
7: aluResult = A >> 7;
8: aluResult = A >> 8;
9: aluResult = A >> 9;
10: aluResult = A>> 10;
11: aluResult = A >> 11;
12: aluResult = A >> 12;
13: aluResult = A >> 13;
14: aluResult = A >> 14;
15: aluResult = A >> 15;
default: aluResult = A >> 0;
endcase
end
default:
begin
aluResult = 0;
end
endcase
end
endmodule | module ALU(
input [15:0] aInput,
input [15:0] bInput,
input [2:0] opCode,
input sub,
input aInvert,
input bInvert,
input ShiftImm,
output [15:0] res,
output [4:0] CLFZN
); |
reg [15:0] A;
reg [15:0] B;
reg [15:0] aluResult;
assign res = aluResult;
assign CLFZN[0] = ($signed(A) < $signed(B));
assign CLFZN[1] = (A == B);
assign CLFZN[2] = (A[15] == B[15]) && (aluResult[15] != A[15]);
assign CLFZN[3] = (A < B);
assign CLFZN[4] = (A[15] && B[15]) || (!aluResult[15] && ( (!A[15] && B[15]) || (A[15] && !B[15])));
always @(*) begin
if (aInvert) A = ~aInput;
else A = aInput;
if (bInvert) B = ~bInput;
else B = bInput;
end
always@(*) begin
case (opCode)
3'b000:
begin
aluResult = A + B + sub;
end
3'b001:
begin
aluResult = A & B;
end
3'b010:
begin
aluResult = A | B;
end
3'b011:
begin
aluResult = A ^ B;
end
3'b101:
begin
if (!ShiftImm && B>=15)
aluResult = A <<< 15;
else
case(B[3:0])
0: aluResult = A <<< 0;
1: aluResult = A <<< 1;
2: aluResult = A <<< 2;
3: aluResult = A <<< 3;
4: aluResult = A <<< 4;
5: aluResult = A <<< 5;
6: aluResult = A <<< 6;
7: aluResult = A <<< 7;
8: aluResult = A <<< 8;
9: aluResult = A <<< 9;
10: aluResult = A <<< 10;
11: aluResult = A <<< 11;
12: aluResult = A <<< 12;
13: aluResult = A <<< 13;
14: aluResult = A <<< 14;
15: aluResult = A <<< 15;
default: aluResult = A <<< 0;
endcase
end
3'b110:
begin
if (!ShiftImm && B>=15)
aluResult = A >>> 15;
else
case(B[3:0])
0: aluResult = A >>> 0;
1: aluResult = A >>> 1;
2: aluResult = A >>> 2;
3: aluResult = A >>> 3;
4: aluResult = A >>> 4;
5: aluResult = A >>> 5;
6: aluResult = A >>> 6;
7: aluResult = A >>> 7;
8: aluResult = A >>> 8;
9: aluResult = A >>> 9;
10: aluResult = A >>> 10;
11: aluResult = A >>> 11;
12: aluResult = A >>> 12;
13: aluResult = A >>> 13;
14: aluResult = A >>> 14;
15: aluResult = A >>> 15;
default: aluResult = A >>> 0;
endcase
end
3'b111:
begin
if (!ShiftImm && B>=15)
aluResult = A >> 15;
else
case(B[3:0])
0: aluResult = A >> 0;
1: aluResult = A >> 1;
2: aluResult = A >> 2;
3: aluResult = A >> 3;
4: aluResult = A >> 4;
5: aluResult = A >> 5;
6: aluResult = A >> 6;
7: aluResult = A >> 7;
8: aluResult = A >> 8;
9: aluResult = A >> 9;
10: aluResult = A>> 10;
11: aluResult = A >> 11;
12: aluResult = A >> 12;
13: aluResult = A >> 13;
14: aluResult = A >> 14;
15: aluResult = A >> 15;
default: aluResult = A >> 0;
endcase
end
default:
begin
aluResult = 0;
end
endcase
end
endmodule | 0 |
6,377 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/ALUctrl.v | 116,048,589 | ALUctrl.v | v | 189 | 83 | [] | [] | [] | [(21, 188)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/ALUctrl.v\n%Error: Exiting due to 4 error(s)\n' | 7,295 | module | module ALUctrl(
input [1:0] ALUop,
input [3:0] OPCodeExtension,
input [3:0] OPCode,
output reg [2:0] ALUcontrol,
output reg Ainv,
output reg Binv,
output reg Sub,
output reg ShiftImm
);
parameter RTYP = 2'b00;
parameter ITYP = 2'b01;
parameter SHFT = 2'b10;
parameter ADD = 4'b0101;
parameter ADDU = 4'b0110;
parameter ADDC = 4'b0111;
parameter SUB = 4'b1001;
parameter SUBC = 4'b1010;
parameter CMP = 4'b1011;
parameter AND = 4'b0001;
parameter OR = 4'b0010;
parameter XOR = 4'b0011;
always@(*) begin
Ainv <= 0;
ALUcontrol <= 3'b000;
Binv <= 0;
Sub <= 0;
ShiftImm <= 0;
case(ALUop)
RTYP:
case(OPCodeExtension)
ADD:
begin
ALUcontrol <= 3'b000;
end
ADDU:
begin
ALUcontrol <= 3'b000;
end
ADDC:
begin
ALUcontrol <= 3'b000;
end
SUB:
begin
ALUcontrol <= 3'b000;
Binv <= 1;
Sub <= 1;
end
SUBC:
begin
ALUcontrol <= 3'b000;
Binv <= 1;
Sub <= 1;
end
CMP:
begin
ALUcontrol <= 3'b000;
end
AND:
begin
ALUcontrol <= 3'b001;
end
OR:
begin
ALUcontrol <= 3'b010;
end
XOR:
begin
ALUcontrol <= 3'b011;
end
default:
begin
ALUcontrol <= 3'b000;
end
endcase
ITYP:
case(OPCode)
ADD:
begin
ALUcontrol <= 3'b000;
end
ADDU:
begin
ALUcontrol <= 3'b000;
end
ADDC:
begin
ALUcontrol <= 3'b000;
end
SUB:
begin
ALUcontrol <= 3'b000;
Binv <= 1;
Sub <= 1;
end
SUBC:
begin
ALUcontrol <= 3'b000;
Binv <= 1;
Sub <= 1;
end
CMP:
begin
ALUcontrol <= 3'b000;
end
AND:
begin
ALUcontrol <= 3'b001;
end
OR:
begin
ALUcontrol <= 3'b010;
end
XOR:
begin
ALUcontrol <= 3'b011;
end
default:
begin
ALUcontrol <= 3'b000;
end
endcase
SHFT:
case(OPCodeExtension)
4'b0100:
begin
ALUcontrol <= 3'b101;
end
4'b0000:
begin
ALUcontrol <= 3'b101;
ShiftImm <= 1;
end
4'b0001:
begin
ALUcontrol <= 3'b111;
ShiftImm <= 1;
end
4'b0110:
begin
ALUcontrol <= 3'b101;
end
4'b0010:
begin
ALUcontrol <= 3'b101;
ShiftImm <= 1;
end
4'b0011:
begin
ALUcontrol <= 3'b110;
ShiftImm <= 1;
end
default:
ALUcontrol <= 3'b000;
endcase
default:
ALUcontrol <= 3'b000;
endcase
end
endmodule | module ALUctrl(
input [1:0] ALUop,
input [3:0] OPCodeExtension,
input [3:0] OPCode,
output reg [2:0] ALUcontrol,
output reg Ainv,
output reg Binv,
output reg Sub,
output reg ShiftImm
); |
parameter RTYP = 2'b00;
parameter ITYP = 2'b01;
parameter SHFT = 2'b10;
parameter ADD = 4'b0101;
parameter ADDU = 4'b0110;
parameter ADDC = 4'b0111;
parameter SUB = 4'b1001;
parameter SUBC = 4'b1010;
parameter CMP = 4'b1011;
parameter AND = 4'b0001;
parameter OR = 4'b0010;
parameter XOR = 4'b0011;
always@(*) begin
Ainv <= 0;
ALUcontrol <= 3'b000;
Binv <= 0;
Sub <= 0;
ShiftImm <= 0;
case(ALUop)
RTYP:
case(OPCodeExtension)
ADD:
begin
ALUcontrol <= 3'b000;
end
ADDU:
begin
ALUcontrol <= 3'b000;
end
ADDC:
begin
ALUcontrol <= 3'b000;
end
SUB:
begin
ALUcontrol <= 3'b000;
Binv <= 1;
Sub <= 1;
end
SUBC:
begin
ALUcontrol <= 3'b000;
Binv <= 1;
Sub <= 1;
end
CMP:
begin
ALUcontrol <= 3'b000;
end
AND:
begin
ALUcontrol <= 3'b001;
end
OR:
begin
ALUcontrol <= 3'b010;
end
XOR:
begin
ALUcontrol <= 3'b011;
end
default:
begin
ALUcontrol <= 3'b000;
end
endcase
ITYP:
case(OPCode)
ADD:
begin
ALUcontrol <= 3'b000;
end
ADDU:
begin
ALUcontrol <= 3'b000;
end
ADDC:
begin
ALUcontrol <= 3'b000;
end
SUB:
begin
ALUcontrol <= 3'b000;
Binv <= 1;
Sub <= 1;
end
SUBC:
begin
ALUcontrol <= 3'b000;
Binv <= 1;
Sub <= 1;
end
CMP:
begin
ALUcontrol <= 3'b000;
end
AND:
begin
ALUcontrol <= 3'b001;
end
OR:
begin
ALUcontrol <= 3'b010;
end
XOR:
begin
ALUcontrol <= 3'b011;
end
default:
begin
ALUcontrol <= 3'b000;
end
endcase
SHFT:
case(OPCodeExtension)
4'b0100:
begin
ALUcontrol <= 3'b101;
end
4'b0000:
begin
ALUcontrol <= 3'b101;
ShiftImm <= 1;
end
4'b0001:
begin
ALUcontrol <= 3'b111;
ShiftImm <= 1;
end
4'b0110:
begin
ALUcontrol <= 3'b101;
end
4'b0010:
begin
ALUcontrol <= 3'b101;
ShiftImm <= 1;
end
4'b0011:
begin
ALUcontrol <= 3'b110;
ShiftImm <= 1;
end
default:
ALUcontrol <= 3'b000;
endcase
default:
ALUcontrol <= 3'b000;
endcase
end
endmodule | 0 |
6,378 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/ALU_ALU_Cont_TF.v | 116,048,589 | ALU_ALU_Cont_TF.v | v | 483 | 134 | [] | [] | [] | null | line:65: before: "$" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/ALU_ALU_Cont_TF.v\n%Error: Exiting due to 4 error(s)\n' | 7,296 | module | module ALU_ALUCont_test_schematic_ALU_ALUCont_test_schematic_sch_tb();
reg [2:0] ALUop;
reg [3:0] OpCodeExtention;
reg [15:0] A;
reg [15:0] B;
wire [15:0] ALUResult;
wire [4:0] CLFZN;
ALU_ALUCont_test_schematic UUT (
.ALUop(ALUop),
.OpCodeExtention(OpCodeExtention),
.A(A),
.B(B),
.ALUResult(ALUResult),
.CLFZN(CLFZN)
);
integer errorCount, i, k;
initial begin
ALUop = 0;
OpCodeExtention = 0;
Op_errorCount = 0;
Flag_errorCount = 0;
A = 0;
B = 0;
CLFZN = 0;
#100;
$display("Testing Add");
for(i = 0; i < 512; i = i + 1)
begin
#10;
A = i;
for(k = 0; k < 512; k = k + 1)
begin
#10
B = k;
#10;
if( (A + B) != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A + B);
Op_errorCount = Op_errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
end
$display("Testing subtract");
ALUop = 4;
#100
for(i = 0; i< 1024; i = i + 1)
begin
#10;
{A, B} = i;
#10;
if( A - B != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A - B);
Op_errorCount = Op_errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
$display("Testing AND");
ALUop = 1;
#100
for(i = 0; i< 1024; i = i + 1)
begin
#10;
{A, B} = i;
#10;
if( A & B != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A & B);
Op_errorCount = Op_errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
$display("Testing OR");
ALUop = 2;
#100
for(i = 0; i< 1024; i = i + 1)
begin
#10;
{A, B} = i;
#10;
if( A | B != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A | B);
Op_errorCount = Op_errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
$display("Testing XOR");
ALUop = 3;
#100
for(i = 0; i< 1024; i = i + 1)
begin
#10;
{A, B} = i;
#10;
if( A ^ B != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A ^ B);
Op_errorCount = Op_errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
$display("Testing SLL");
ALUop = 5;
#100
for(i = 0; i< 1024; i = i + 1)
begin
#10;
{A, B} = i;
#10;
if( A << B != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A << B);
Op_errorCount = Op_errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
$display("Testing SRA");
ALUop = 5;
#100
for(i = 0; i< 1024; i = i + 1)
begin
#10;
{A, B} = i;
#10;
if( A >>> B != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A >>> B);
Op_errorCount = Op_errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
$display("Testing SRL");
ALUop = 7;
#100
for(i = 0; i< 2^32-1 ; i = i + 1)
begin
#10;
{A, B} = i;
#10;
if( A >> B != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A >> B);
errorCount = errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
$display("Testing finished. Operation error count is %d, & Flag Error Count is %d", Op_errorCount, FLag_errorCount);
end
endmodule | module ALU_ALUCont_test_schematic_ALU_ALUCont_test_schematic_sch_tb(); |
reg [2:0] ALUop;
reg [3:0] OpCodeExtention;
reg [15:0] A;
reg [15:0] B;
wire [15:0] ALUResult;
wire [4:0] CLFZN;
ALU_ALUCont_test_schematic UUT (
.ALUop(ALUop),
.OpCodeExtention(OpCodeExtention),
.A(A),
.B(B),
.ALUResult(ALUResult),
.CLFZN(CLFZN)
);
integer errorCount, i, k;
initial begin
ALUop = 0;
OpCodeExtention = 0;
Op_errorCount = 0;
Flag_errorCount = 0;
A = 0;
B = 0;
CLFZN = 0;
#100;
$display("Testing Add");
for(i = 0; i < 512; i = i + 1)
begin
#10;
A = i;
for(k = 0; k < 512; k = k + 1)
begin
#10
B = k;
#10;
if( (A + B) != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A + B);
Op_errorCount = Op_errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
end
$display("Testing subtract");
ALUop = 4;
#100
for(i = 0; i< 1024; i = i + 1)
begin
#10;
{A, B} = i;
#10;
if( A - B != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A - B);
Op_errorCount = Op_errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
$display("Testing AND");
ALUop = 1;
#100
for(i = 0; i< 1024; i = i + 1)
begin
#10;
{A, B} = i;
#10;
if( A & B != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A & B);
Op_errorCount = Op_errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
$display("Testing OR");
ALUop = 2;
#100
for(i = 0; i< 1024; i = i + 1)
begin
#10;
{A, B} = i;
#10;
if( A | B != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A | B);
Op_errorCount = Op_errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
$display("Testing XOR");
ALUop = 3;
#100
for(i = 0; i< 1024; i = i + 1)
begin
#10;
{A, B} = i;
#10;
if( A ^ B != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A ^ B);
Op_errorCount = Op_errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
$display("Testing SLL");
ALUop = 5;
#100
for(i = 0; i< 1024; i = i + 1)
begin
#10;
{A, B} = i;
#10;
if( A << B != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A << B);
Op_errorCount = Op_errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
$display("Testing SRA");
ALUop = 5;
#100
for(i = 0; i< 1024; i = i + 1)
begin
#10;
{A, B} = i;
#10;
if( A >>> B != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A >>> B);
Op_errorCount = Op_errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
$display("Testing SRL");
ALUop = 7;
#100
for(i = 0; i< 2^32-1 ; i = i + 1)
begin
#10;
{A, B} = i;
#10;
if( A >> B != ALUResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", A, B, ALUResult, A >> B);
errorCount = errorCount + 1;
end
if(CLFZN[0] != ($signed(A) > $signed(B)))
begin
#10
$display("There was an error. N is %d. N should be %d.", CLFZN[0], $signed(A) > $signed(B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[1] != (A == B))
begin
#10
$display("There was an error. Z is %d. Z should be %d.", CLFZN[1], (A == B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[2] != (A[15] == B[15]) && (aluResult[15] != A[15]))
begin
#10
$display("There was an error. F is %d. F should be %d.", CLFZN[2], (A[15] == B[15]) && (aluResult[15] != A[15]));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[3] != (A > B))
begin
#10
$display("There was an error. L is %d. L should be %d.", CLFZN[3], (A > B));
Flag_errorCount = Flag_errorCount + 1;
end
if(CLFZN[4] != (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]))
begin
#10
$display("There was an error. C is %d. C should be %d.", CLFZN[4], (A[15] & B[15]) || ((A[15] | B[15]) && ~aluResult[15]));
Flag_errorCount = Flag_errorCount + 1;
end
end
$display("Testing finished. Operation error count is %d, & Flag Error Count is %d", Op_errorCount, FLag_errorCount);
end
endmodule | 0 |
6,379 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/ALU_TF.v | 116,048,589 | ALU_TF.v | v | 140 | 125 | [] | [] | [] | null | line:60: before: ")" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/ALU_TF.v\n%Error: Exiting due to 4 error(s)\n' | 7,297 | module | module ALU_TF;
reg [15:0] aInput;
reg [15:0] bInput;
reg [2:0] ALUop;
reg [3:0] OPCodeExtention;
wire [15:0] aluResult;
wire C;
wire L;
wire F;
wire Z;
wire N;
ALU uut (
.aInput(aInput),
.bInput(bInput),
.aluResult(aluResult),
.C(C),
.L(L),
.F(F),
.Z(Z),
.N(N)
);
ALUctrl uut (
.ALUop(ALUop),
.OPCodeExtention(OPCodeExtention),
);
integer i;
integer errorCount, k;
initial begin
aInput = 0;
bInput = 0;
ALUop = 0;
OPCodeExtention = 0;
errorCount = 0;
#100
$display("testing add");
ALUOp = 0;
for(i = 0; i < 512; i = i + 1)
begin
#10;
aInput = i;
for(k = 0; k < 512; k = k + 1)
begin
#10
bInput = k;
#10;
if( (aInput + bInput) != aluResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", aInput, bInput, aluResult, aInput + bInput);
errorCount = errorCount + 1;
end
end
end
#10;
ALUOp = 4;
#10
$display("testing subtract");
for(i = 0; i < 512; i = i + 1)
begin
#10
{aInput, bInput} = i;
#10
if( (aInput - bInput) != aluResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", aInput, bInput, aluResult, aInput - bInput);
errorCount = errorCount + 1;
end
#10;
end
$display("testing carry");
for(i = 0; i < 512; i = i + 1)
begin
#10
{aInput, bInput} = i;
#10
if( (aInput+ bInput) && CLFZN[4])
begin
#10;
$display("A is %d. B is %d, F is %d.", aInput, bInput, aluResult);
end
end
$display("Testing finished. Error count is %d.", errorCount);
end
endmodule | module ALU_TF; |
reg [15:0] aInput;
reg [15:0] bInput;
reg [2:0] ALUop;
reg [3:0] OPCodeExtention;
wire [15:0] aluResult;
wire C;
wire L;
wire F;
wire Z;
wire N;
ALU uut (
.aInput(aInput),
.bInput(bInput),
.aluResult(aluResult),
.C(C),
.L(L),
.F(F),
.Z(Z),
.N(N)
);
ALUctrl uut (
.ALUop(ALUop),
.OPCodeExtention(OPCodeExtention),
);
integer i;
integer errorCount, k;
initial begin
aInput = 0;
bInput = 0;
ALUop = 0;
OPCodeExtention = 0;
errorCount = 0;
#100
$display("testing add");
ALUOp = 0;
for(i = 0; i < 512; i = i + 1)
begin
#10;
aInput = i;
for(k = 0; k < 512; k = k + 1)
begin
#10
bInput = k;
#10;
if( (aInput + bInput) != aluResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", aInput, bInput, aluResult, aInput + bInput);
errorCount = errorCount + 1;
end
end
end
#10;
ALUOp = 4;
#10
$display("testing subtract");
for(i = 0; i < 512; i = i + 1)
begin
#10
{aInput, bInput} = i;
#10
if( (aInput - bInput) != aluResult)
begin
#10;
$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", aInput, bInput, aluResult, aInput - bInput);
errorCount = errorCount + 1;
end
#10;
end
$display("testing carry");
for(i = 0; i < 512; i = i + 1)
begin
#10
{aInput, bInput} = i;
#10
if( (aInput+ bInput) && CLFZN[4])
begin
#10;
$display("A is %d. B is %d, F is %d.", aInput, bInput, aluResult);
end
end
$display("Testing finished. Error count is %d.", errorCount);
end
endmodule | 0 |
6,380 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/BitGen.v | 116,048,589 | BitGen.v | v | 56 | 97 | [] | [] | [] | [(23, 55)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/BitGen.v\n%Error: Exiting due to 4 error(s)\n' | 7,298 | module | module BitGen(
input [3:0] glyphCol,
input [11:0] glyphR,
input [11:0] glyphG,
input [11:0] glyphB,
input [10:0] hCount,
input bright,
output reg red,
output reg green,
output reg blue
);
always@(*)
begin
red <= 0;
green <= 0;
blue <= 0;
if(bright)
if(636 <= hCount)
begin
red <= 0;
green <= 0;
blue <= 0;
end
else
begin
red <= glyphR[11 - glyphCol];
green <= glyphG[11 - glyphCol];
blue <= glyphB[11 - glyphCol];
end
end
endmodule | module BitGen(
input [3:0] glyphCol,
input [11:0] glyphR,
input [11:0] glyphG,
input [11:0] glyphB,
input [10:0] hCount,
input bright,
output reg red,
output reg green,
output reg blue
); |
always@(*)
begin
red <= 0;
green <= 0;
blue <= 0;
if(bright)
if(636 <= hCount)
begin
red <= 0;
green <= 0;
blue <= 0;
end
else
begin
red <= glyphR[11 - glyphCol];
green <= glyphG[11 - glyphCol];
blue <= glyphB[11 - glyphCol];
end
end
endmodule | 0 |
6,381 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/bitshift.v | 116,048,589 | bitshift.v | v | 57 | 83 | [] | [] | [] | [(21, 56)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/bitshift.v\n%Error: Exiting due to 4 error(s)\n' | 7,299 | module | module bitshift(
input reset,
input clk,
input [15:0] word1,
input [15:0] word2,
output SPI_MOSI,
output reg DAC_CS,
output DAC_CLK
);
reg [31:0] bits;
reg [5:0] cnt;
assign DAC_CLK = clk;
assign SPI_MOSI = bits[31];
always@(posedge DAC_CLK) begin
DAC_CS <= 0;
if (reset) begin
cnt <= 0;
bits <= 0;
end
else begin
if (cnt == 0)
bits <= {word1,word2};
if (cnt == 32) begin
cnt <= 0;
DAC_CS <= 1;
end
else bits <= bits << 1;
cnt <= cnt + 1;
end
end
endmodule | module bitshift(
input reset,
input clk,
input [15:0] word1,
input [15:0] word2,
output SPI_MOSI,
output reg DAC_CS,
output DAC_CLK
); |
reg [31:0] bits;
reg [5:0] cnt;
assign DAC_CLK = clk;
assign SPI_MOSI = bits[31];
always@(posedge DAC_CLK) begin
DAC_CS <= 0;
if (reset) begin
cnt <= 0;
bits <= 0;
end
else begin
if (cnt == 0)
bits <= {word1,word2};
if (cnt == 32) begin
cnt <= 0;
DAC_CS <= 1;
end
else bits <= bits << 1;
cnt <= cnt + 1;
end
end
endmodule | 0 |
6,382 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/blah_Tf.v | 116,048,589 | blah_Tf.v | v | 56 | 81 | [] | [] | [] | [(25, 54)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/blah_Tf.v\n%Error: Exiting due to 4 error(s)\n' | 7,300 | module | module blah_Tf;
reg [2:0] ALUop;
reg [3:0] OPCodeExtention;
wire [2:0] ALUcontrol;
wire Ainv;
wire Binv;
wire Sub;
ALUctrl uut (
.ALUop(ALUop),
.OPCodeExtention(OPCodeExtention),
.ALUcontrol(ALUcontrol),
.Ainv(Ainv),
.Binv(Binv),
.Sub(Sub)
);
integer errorCount, i;
initial begin
end
endmodule | module blah_Tf; |
reg [2:0] ALUop;
reg [3:0] OPCodeExtention;
wire [2:0] ALUcontrol;
wire Ainv;
wire Binv;
wire Sub;
ALUctrl uut (
.ALUop(ALUop),
.OPCodeExtention(OPCodeExtention),
.ALUcontrol(ALUcontrol),
.Ainv(Ainv),
.Binv(Binv),
.Sub(Sub)
);
integer errorCount, i;
initial begin
end
endmodule | 0 |
6,383 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/ClockDivider_50Mhz_to_30Hz.v | 116,048,589 | ClockDivider_50Mhz_to_30Hz.v | v | 50 | 83 | [] | [] | [] | [(21, 49)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/ClockDivider_50Mhz_to_30Hz.v\n%Error: Exiting due to 4 error(s)\n' | 7,301 | module | module ClockDivider_50Mhz_to_30Hz(
input clock,
input reset,
output reg enable
);
reg [24:0] count;
always@(posedge clock) begin
count <= 0;
enable <= 1;
if(reset) begin
enable <= 1;
count <= 0;
end
else if(count == 1666670) begin
enable <= 1;
count <= 0;
end
else begin
enable <= 0;
count <= count + 1;
end
end
endmodule | module ClockDivider_50Mhz_to_30Hz(
input clock,
input reset,
output reg enable
); |
reg [24:0] count;
always@(posedge clock) begin
count <= 0;
enable <= 1;
if(reset) begin
enable <= 1;
count <= 0;
end
else if(count == 1666670) begin
enable <= 1;
count <= 0;
end
else begin
enable <= 0;
count <= count + 1;
end
end
endmodule | 0 |
6,384 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/ClockDivider_50MHz_To_60Hz.v | 116,048,589 | ClockDivider_50MHz_To_60Hz.v | v | 51 | 93 | [] | [] | [] | [(22, 50)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/ClockDivider_50MHz_To_60Hz.v\n%Error: Exiting due to 4 error(s)\n' | 7,302 | module | module ClockDivider_50MHz_To_60Hz(
input clock,
input reset,
output reg enable
);
reg [19:0] count;
always@(posedge clock) begin
count <= 0;
enable <= 1;
if(reset) begin
enable <= 1;
count <= 0;
end
else if(count == 833332) begin
enable <= 1;
count <= 0;
end
else begin
enable <= 0;
count <= count + 1;
end
end
endmodule | module ClockDivider_50MHz_To_60Hz(
input clock,
input reset,
output reg enable
); |
reg [19:0] count;
always@(posedge clock) begin
count <= 0;
enable <= 1;
if(reset) begin
enable <= 1;
count <= 0;
end
else if(count == 833332) begin
enable <= 1;
count <= 0;
end
else begin
enable <= 0;
count <= count + 1;
end
end
endmodule | 0 |
6,385 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/ControlLogic.v | 116,048,589 | ControlLogic.v | v | 436 | 110 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/ControlLogic.v\n%Error: Exiting due to 4 error(s)\n' | 7,303 | module | module ControlLogic(
input [3:0] OPCode,
input [3:0] OPCodeExtension,
input [3:0] JCond,
input [3:0] cond,
input reset,
input Clk,
output reg PCWrite,
output reg InstrWrite,
output reg RegWrite,
output reg [1:0] ALUop,
output reg [2:0] RegDataSRC,
output reg [1:0] ALUSrcB,
output reg MemWrite,
output reg SignExtend,
output reg SetF,
output reg SetL,
output reg SetC,
output reg SetN,
output reg SetZ,
output reg [1:0] PCSource,
output reg [15:0] SCond,
input [4:0] PSR_Value
);
reg [4:0] CurState;
reg [4:0] NextState;
reg SCond_Valid;
reg Cond_Valid;
wire C;
wire L;
wire F;
wire Z;
wire N;
assign C = PSR_Value[4];
assign L = PSR_Value[3];
assign F = PSR_Value[2];
assign Z = PSR_Value[1];
assign N = PSR_Value[0];
parameter IFETCH = 5'b00000;
parameter RFETCH = 5'b00001;
parameter RTYPEX = 5'b00010;
parameter ITYPEX = 5'b00011;
parameter MOVEX = 5'b00100;
parameter MOVIEX = 5'b00101;
parameter LUIEX = 5'b00110;
parameter LOADEX = 5'b00111;
parameter STOREX = 5'b01000;
parameter CMPEX = 5'b01001;
parameter CMPIEX = 5'b01010;
parameter BRANEX = 5'b01011;
parameter JUMPEX = 5'b01100;
parameter JALEX = 5'b01101;
parameter RETEX = 5'b01110;
parameter SEX = 5'b01111;
parameter MULEX = 5'b10000;
parameter MULIEX = 5'b10010;
parameter NOPEX = 5'b11111;
parameter RINSTR = 4'b0000;
parameter ADDI = 4'b0101;
parameter ADDUI = 4'b0110;
parameter ADDCI = 4'b0111;
parameter SUBI = 4'b1001;
parameter SUBCI = 4'b1010;
parameter CMPI = 4'b1011;
parameter ANDI = 4'b0001;
parameter ORI = 4'b0010;
parameter XORI = 4'b0011;
parameter MULI = 4'b1110;
parameter MOVI = 4'b1101;
parameter LUI = 4'b1111;
parameter LDSTORJ = 4'b0100;
parameter BRAN = 4'b1100;
parameter EQ = 4'b0000;
parameter NE = 4'b0001;
parameter GE = 4'b1101;
parameter CS = 4'b0010;
parameter CC = 4'b0011;
parameter HI = 4'b0100;
parameter LS = 4'b0101;
parameter LO = 4'b1010;
parameter HS = 4'b1011;
parameter Gt = 4'b0110;
parameter LE = 4'b0111;
parameter FS = 4'b1000;
parameter FC = 4'b1001;
parameter LT = 4'b1100;
parameter UC = 4'b1110;
parameter NJ = 4'b1111;
always@(*) begin
Cond_Valid = 0;
case(JCond)
EQ: if (Z) Cond_Valid = 1;
NE: if (!Z) Cond_Valid = 1;
GE: if (N || Z) Cond_Valid = 1;
CS: if (C) Cond_Valid = 1;
CC: if (!C) Cond_Valid = 1;
HI: if (L) Cond_Valid = 1;
LS: if (!L) Cond_Valid = 1;
LO: if (!L && !Z) Cond_Valid = 1;
HS: if (L || Z) Cond_Valid = 1;
Gt: if (N) Cond_Valid = 1;
LE: if (!N) Cond_Valid = 1;
FS: if (F) Cond_Valid = 1;
FC: if (!F) Cond_Valid = 1;
LT: if (!N && !Z) Cond_Valid = 1;
UC: Cond_Valid = 1;
default: Cond_Valid = 0;
endcase
end
always@(*) begin
SCond_Valid = 0;
case(cond)
EQ: if (Z) SCond_Valid = 1;
NE: if (!Z) SCond_Valid = 1;
GE: if (N || Z) SCond_Valid = 1;
CS: if (C) SCond_Valid = 1;
CC: if (!C) SCond_Valid = 1;
HI: if (L) SCond_Valid = 1;
LS: if (!L) SCond_Valid = 1;
LO: if (!L && !Z) SCond_Valid = 1;
HS: if (L || Z) SCond_Valid = 1;
Gt: if (N) SCond_Valid = 1;
LE: if (!N) SCond_Valid = 1;
FS: if (F) SCond_Valid = 1;
FC: if (!F) SCond_Valid = 1;
LT: if (!N && !Z) SCond_Valid = 1;
UC: SCond_Valid = 1;
default: SCond_Valid = 0;
endcase
end
always@(posedge Clk) begin
if (reset) CurState <= IFETCH;
else CurState <= NextState;
end
always@(*) begin
InstrWrite = 0;
ALUSrcB = 2;
RegDataSRC = 0;
RegWrite = 0;
PCWrite = 0;
ALUop = 2'b00;
MemWrite = 0;
SignExtend = 0;
SetC = 0;
SetL = 0;
SetF = 0;
SetZ = 0;
SetN = 0;
PCSource = 0;
SCond = 0;
case (CurState)
IFETCH:
begin
InstrWrite = 1;
ALUSrcB = 2;
end
RFETCH:
begin
end
RTYPEX:
begin
RegDataSRC = 0;
ALUSrcB = 1;
ALUop = 2'b00;
RegWrite = 1;
PCWrite = 1;
case(OPCodeExtension)
ADDI:
begin
SetC = 1;
SetF = 1;
end
ADDCI:
begin
SetF = 1;
end
SUBI:
begin
SetC = 1;
SetF = 1;
end
SUBCI:
begin
SetF = 1;
end
default:
begin
end
endcase
end
ITYPEX:
begin
RegDataSRC = 0;
ALUSrcB = 0;
ALUop = 2'b01;
RegWrite = 1;
PCWrite =1;
case (OPCode)
ADDI:
begin
SignExtend = 1;
SetC = 1;
SetF = 1;
end
ADDUI:
begin
SignExtend = 1;
end
ADDCI:
begin
SignExtend = 1;
SetF = 1;
end
SUBI:
begin
SignExtend = 1;
SetC = 1;
SetF = 1;
end
SUBCI:
begin
SignExtend = 1;
SetF = 1;
end
default:
begin
SignExtend = 0;
end
endcase
end
MOVEX:
begin
RegDataSRC = 4;
RegWrite = 1;
PCWrite = 1;
end
MOVIEX:
begin
RegDataSRC = 2;
RegWrite = 1;
PCWrite =1;
end
LUIEX:
begin
RegDataSRC = 3;
RegWrite = 1;
PCWrite = 1;
end
LOADEX:
begin
ALUSrcB = 1;
RegDataSRC = 1;
RegWrite = 1;
PCWrite = 1;
end
STOREX:
begin
ALUSrcB = 1;
MemWrite = 1;
PCWrite = 1;
end
NOPEX:
begin
PCWrite = 1;
end
CMPEX:
begin
PCWrite = 1;
ALUSrcB = 1;
SetZ = 1;
SetL = 1;
SetN = 1;
end
CMPIEX:
begin
PCWrite = 1;
ALUSrcB = 0;
SignExtend = 1;
SetZ = 1;
SetL = 1;
SetN = 1;
end
BRANEX:
begin
PCWrite = 1;
if (Cond_Valid) begin
PCSource = 2;
SignExtend = 1;
end
end
JUMPEX:
begin
PCWrite = 1;
if (Cond_Valid) PCSource = 1;
end
JALEX:
begin
PCWrite = 1;
RegWrite = 1;
RegDataSRC = 5;
PCSource = 1;
end
RETEX:
begin
PCWrite = 1;
PCSource = 1;
end
SEX:
begin
PCWrite = 1;
RegWrite = 1;
RegDataSRC = 7;
if (SCond_Valid)
SCond = 1;
else
SCond = 0;
end
MULEX:
begin
ALUSrcB = 1;
PCWrite = 1;
RegWrite = 1;
RegDataSRC = 6;
end
MULIEX:
begin
ALUSrcB = 0;
SignExtend = 1;
PCWrite = 1;
RegWrite = 1;
RegDataSRC = 6;
end
default: begin end
endcase
end
always @(*) begin
case (CurState)
IFETCH: NextState <= RFETCH;
RFETCH:
case(OPCode)
RINSTR:
case(OPCodeExtension)
4'b1101:
NextState <= MOVEX;
4'b1110:
NextState <= MULEX;
4'b0000:
NextState <= NOPEX;
4'b1011:
NextState <= CMPEX;
default:
NextState <= RTYPEX;
endcase
ADDI: NextState <= ITYPEX;
ADDUI: NextState <= ITYPEX;
ADDCI: NextState <= ITYPEX;
SUBI: NextState <= ITYPEX;
SUBCI: NextState <= ITYPEX;
CMPI: NextState <= CMPIEX;
ANDI: NextState <= ITYPEX;
ORI: NextState <= ITYPEX;
XORI: NextState <= ITYPEX;
MOVI: NextState <= MOVIEX;
LUI: NextState <= LUIEX;
MULI: NextState <= MULIEX;
LDSTORJ:
case(OPCodeExtension)
4'b0000:
NextState <= LOADEX;
4'b0100:
NextState <= STOREX;
4'b1100:
NextState <= JUMPEX;
4'b1000:
NextState <= JALEX;
4'b1001:
NextState <= RETEX;
4'b1101:
NextState <= SEX;
default:
NextState <= IFETCH;
endcase
BRAN: NextState <= BRANEX;
default: NextState <= IFETCH;
endcase
default: NextState <= IFETCH;
endcase
end
endmodule | module ControlLogic(
input [3:0] OPCode,
input [3:0] OPCodeExtension,
input [3:0] JCond,
input [3:0] cond,
input reset,
input Clk,
output reg PCWrite,
output reg InstrWrite,
output reg RegWrite,
output reg [1:0] ALUop,
output reg [2:0] RegDataSRC,
output reg [1:0] ALUSrcB,
output reg MemWrite,
output reg SignExtend,
output reg SetF,
output reg SetL,
output reg SetC,
output reg SetN,
output reg SetZ,
output reg [1:0] PCSource,
output reg [15:0] SCond,
input [4:0] PSR_Value
); |
reg [4:0] CurState;
reg [4:0] NextState;
reg SCond_Valid;
reg Cond_Valid;
wire C;
wire L;
wire F;
wire Z;
wire N;
assign C = PSR_Value[4];
assign L = PSR_Value[3];
assign F = PSR_Value[2];
assign Z = PSR_Value[1];
assign N = PSR_Value[0];
parameter IFETCH = 5'b00000;
parameter RFETCH = 5'b00001;
parameter RTYPEX = 5'b00010;
parameter ITYPEX = 5'b00011;
parameter MOVEX = 5'b00100;
parameter MOVIEX = 5'b00101;
parameter LUIEX = 5'b00110;
parameter LOADEX = 5'b00111;
parameter STOREX = 5'b01000;
parameter CMPEX = 5'b01001;
parameter CMPIEX = 5'b01010;
parameter BRANEX = 5'b01011;
parameter JUMPEX = 5'b01100;
parameter JALEX = 5'b01101;
parameter RETEX = 5'b01110;
parameter SEX = 5'b01111;
parameter MULEX = 5'b10000;
parameter MULIEX = 5'b10010;
parameter NOPEX = 5'b11111;
parameter RINSTR = 4'b0000;
parameter ADDI = 4'b0101;
parameter ADDUI = 4'b0110;
parameter ADDCI = 4'b0111;
parameter SUBI = 4'b1001;
parameter SUBCI = 4'b1010;
parameter CMPI = 4'b1011;
parameter ANDI = 4'b0001;
parameter ORI = 4'b0010;
parameter XORI = 4'b0011;
parameter MULI = 4'b1110;
parameter MOVI = 4'b1101;
parameter LUI = 4'b1111;
parameter LDSTORJ = 4'b0100;
parameter BRAN = 4'b1100;
parameter EQ = 4'b0000;
parameter NE = 4'b0001;
parameter GE = 4'b1101;
parameter CS = 4'b0010;
parameter CC = 4'b0011;
parameter HI = 4'b0100;
parameter LS = 4'b0101;
parameter LO = 4'b1010;
parameter HS = 4'b1011;
parameter Gt = 4'b0110;
parameter LE = 4'b0111;
parameter FS = 4'b1000;
parameter FC = 4'b1001;
parameter LT = 4'b1100;
parameter UC = 4'b1110;
parameter NJ = 4'b1111;
always@(*) begin
Cond_Valid = 0;
case(JCond)
EQ: if (Z) Cond_Valid = 1;
NE: if (!Z) Cond_Valid = 1;
GE: if (N || Z) Cond_Valid = 1;
CS: if (C) Cond_Valid = 1;
CC: if (!C) Cond_Valid = 1;
HI: if (L) Cond_Valid = 1;
LS: if (!L) Cond_Valid = 1;
LO: if (!L && !Z) Cond_Valid = 1;
HS: if (L || Z) Cond_Valid = 1;
Gt: if (N) Cond_Valid = 1;
LE: if (!N) Cond_Valid = 1;
FS: if (F) Cond_Valid = 1;
FC: if (!F) Cond_Valid = 1;
LT: if (!N && !Z) Cond_Valid = 1;
UC: Cond_Valid = 1;
default: Cond_Valid = 0;
endcase
end
always@(*) begin
SCond_Valid = 0;
case(cond)
EQ: if (Z) SCond_Valid = 1;
NE: if (!Z) SCond_Valid = 1;
GE: if (N || Z) SCond_Valid = 1;
CS: if (C) SCond_Valid = 1;
CC: if (!C) SCond_Valid = 1;
HI: if (L) SCond_Valid = 1;
LS: if (!L) SCond_Valid = 1;
LO: if (!L && !Z) SCond_Valid = 1;
HS: if (L || Z) SCond_Valid = 1;
Gt: if (N) SCond_Valid = 1;
LE: if (!N) SCond_Valid = 1;
FS: if (F) SCond_Valid = 1;
FC: if (!F) SCond_Valid = 1;
LT: if (!N && !Z) SCond_Valid = 1;
UC: SCond_Valid = 1;
default: SCond_Valid = 0;
endcase
end
always@(posedge Clk) begin
if (reset) CurState <= IFETCH;
else CurState <= NextState;
end
always@(*) begin
InstrWrite = 0;
ALUSrcB = 2;
RegDataSRC = 0;
RegWrite = 0;
PCWrite = 0;
ALUop = 2'b00;
MemWrite = 0;
SignExtend = 0;
SetC = 0;
SetL = 0;
SetF = 0;
SetZ = 0;
SetN = 0;
PCSource = 0;
SCond = 0;
case (CurState)
IFETCH:
begin
InstrWrite = 1;
ALUSrcB = 2;
end
RFETCH:
begin
end
RTYPEX:
begin
RegDataSRC = 0;
ALUSrcB = 1;
ALUop = 2'b00;
RegWrite = 1;
PCWrite = 1;
case(OPCodeExtension)
ADDI:
begin
SetC = 1;
SetF = 1;
end
ADDCI:
begin
SetF = 1;
end
SUBI:
begin
SetC = 1;
SetF = 1;
end
SUBCI:
begin
SetF = 1;
end
default:
begin
end
endcase
end
ITYPEX:
begin
RegDataSRC = 0;
ALUSrcB = 0;
ALUop = 2'b01;
RegWrite = 1;
PCWrite =1;
case (OPCode)
ADDI:
begin
SignExtend = 1;
SetC = 1;
SetF = 1;
end
ADDUI:
begin
SignExtend = 1;
end
ADDCI:
begin
SignExtend = 1;
SetF = 1;
end
SUBI:
begin
SignExtend = 1;
SetC = 1;
SetF = 1;
end
SUBCI:
begin
SignExtend = 1;
SetF = 1;
end
default:
begin
SignExtend = 0;
end
endcase
end
MOVEX:
begin
RegDataSRC = 4;
RegWrite = 1;
PCWrite = 1;
end
MOVIEX:
begin
RegDataSRC = 2;
RegWrite = 1;
PCWrite =1;
end
LUIEX:
begin
RegDataSRC = 3;
RegWrite = 1;
PCWrite = 1;
end
LOADEX:
begin
ALUSrcB = 1;
RegDataSRC = 1;
RegWrite = 1;
PCWrite = 1;
end
STOREX:
begin
ALUSrcB = 1;
MemWrite = 1;
PCWrite = 1;
end
NOPEX:
begin
PCWrite = 1;
end
CMPEX:
begin
PCWrite = 1;
ALUSrcB = 1;
SetZ = 1;
SetL = 1;
SetN = 1;
end
CMPIEX:
begin
PCWrite = 1;
ALUSrcB = 0;
SignExtend = 1;
SetZ = 1;
SetL = 1;
SetN = 1;
end
BRANEX:
begin
PCWrite = 1;
if (Cond_Valid) begin
PCSource = 2;
SignExtend = 1;
end
end
JUMPEX:
begin
PCWrite = 1;
if (Cond_Valid) PCSource = 1;
end
JALEX:
begin
PCWrite = 1;
RegWrite = 1;
RegDataSRC = 5;
PCSource = 1;
end
RETEX:
begin
PCWrite = 1;
PCSource = 1;
end
SEX:
begin
PCWrite = 1;
RegWrite = 1;
RegDataSRC = 7;
if (SCond_Valid)
SCond = 1;
else
SCond = 0;
end
MULEX:
begin
ALUSrcB = 1;
PCWrite = 1;
RegWrite = 1;
RegDataSRC = 6;
end
MULIEX:
begin
ALUSrcB = 0;
SignExtend = 1;
PCWrite = 1;
RegWrite = 1;
RegDataSRC = 6;
end
default: begin end
endcase
end
always @(*) begin
case (CurState)
IFETCH: NextState <= RFETCH;
RFETCH:
case(OPCode)
RINSTR:
case(OPCodeExtension)
4'b1101:
NextState <= MOVEX;
4'b1110:
NextState <= MULEX;
4'b0000:
NextState <= NOPEX;
4'b1011:
NextState <= CMPEX;
default:
NextState <= RTYPEX;
endcase
ADDI: NextState <= ITYPEX;
ADDUI: NextState <= ITYPEX;
ADDCI: NextState <= ITYPEX;
SUBI: NextState <= ITYPEX;
SUBCI: NextState <= ITYPEX;
CMPI: NextState <= CMPIEX;
ANDI: NextState <= ITYPEX;
ORI: NextState <= ITYPEX;
XORI: NextState <= ITYPEX;
MOVI: NextState <= MOVIEX;
LUI: NextState <= LUIEX;
MULI: NextState <= MULIEX;
LDSTORJ:
case(OPCodeExtension)
4'b0000:
NextState <= LOADEX;
4'b0100:
NextState <= STOREX;
4'b1100:
NextState <= JUMPEX;
4'b1000:
NextState <= JALEX;
4'b1001:
NextState <= RETEX;
4'b1101:
NextState <= SEX;
default:
NextState <= IFETCH;
endcase
BRAN: NextState <= BRANEX;
default: NextState <= IFETCH;
endcase
default: NextState <= IFETCH;
endcase
end
endmodule | 0 |
6,386 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/CounterMax3.v | 116,048,589 | CounterMax3.v | v | 38 | 96 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/CounterMax3.v\n%Error: Exiting due to 4 error(s)\n' | 7,304 | module | module CounterMax3(
input Clock,
output reg [2:0] count
);
reg [2:0] toCount = 0;
always@(posedge Clock)
toCount = toCount + 1;
always@(posedge Clock)
count = toCount;
endmodule | module CounterMax3(
input Clock,
output reg [2:0] count
); |
reg [2:0] toCount = 0;
always@(posedge Clock)
toCount = toCount + 1;
always@(posedge Clock)
count = toCount;
endmodule | 0 |
6,387 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/exmem.v | 116,048,589 | exmem.v | v | 65 | 83 | [] | [] | [] | null | line:42: before: "input" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/exmem.v\n%Error: Exiting due to 4 error(s)\n' | 7,305 | module | module exmem #(parameter WIDTH = 16, RAM_ADDR_BITS = 14)
(input clk, en,
input memwrite,
input [RAM_ADDR_BITS-1:0] adr,
input [WIDTH-1:0] writedata,
output reg [WIDTH-1:0] memdata,
input pxlClk,
input [13:0] glyphAdd,
output reg [15:0] glyphData
);
reg [WIDTH-1:0] mips_ram [(2**RAM_ADDR_BITS)-1:0];
initial
$readmemb("testInitLevel.bin", mips_ram);
always @(posedge clk)
if (en) begin
if (memwrite)
mips_ram[adr] <= writedata;
memdata <= mips_ram[adr];
end
always @(posedge pxlClk)
if (en) begin
glyphData <= mips_ram[glyphAdd];
end
endmodule | module exmem #(parameter WIDTH = 16, RAM_ADDR_BITS = 14)
(input clk, en,
input memwrite,
input [RAM_ADDR_BITS-1:0] adr,
input [WIDTH-1:0] writedata,
output reg [WIDTH-1:0] memdata,
input pxlClk,
input [13:0] glyphAdd,
output reg [15:0] glyphData
); |
reg [WIDTH-1:0] mips_ram [(2**RAM_ADDR_BITS)-1:0];
initial
$readmemb("testInitLevel.bin", mips_ram);
always @(posedge clk)
if (en) begin
if (memwrite)
mips_ram[adr] <= writedata;
memdata <= mips_ram[adr];
end
always @(posedge pxlClk)
if (en) begin
glyphData <= mips_ram[glyphAdd];
end
endmodule | 0 |
6,388 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/GlyphMap.v | 116,048,589 | GlyphMap.v | v | 290 | 97 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/GlyphMap.v\n%Error: Exiting due to 4 error(s)\n' | 7,308 | module | module GlyphMap(
input [10:0] hCount,
input [10:0] vCount,
input clock,
input enable,
output reg [3:0] glyphRow,
output reg [3:0] glyphCol,
output [13:0] address
);
reg [5:0] col;
reg [5:0] row;
always@(*)
begin
col = 0;
row = 0;
if(0 <= hCount && hCount < 12)
col = 0;
else if(12 <= hCount && hCount < 24)
col = 1;
else if(24 <= hCount && hCount < 36)
col = 2;
else if(36 <= hCount && hCount < 48)
col = 3;
else if(48 <= hCount && hCount < 60)
col = 4;
else if(60 <= hCount && hCount < 72)
col = 5;
else if(72 <= hCount && hCount < 84)
col = 6;
else if(84 <= hCount && hCount < 96)
col = 7;
else if(96 <= hCount && hCount < 108)
col = 8;
else if(108 <= hCount && hCount < 120)
col = 9;
else if(120 <= hCount && hCount < 132)
col = 10;
else if(132 <= hCount && hCount < 144)
col = 11;
else if(144 <= hCount && hCount < 156)
col = 12;
else if(156 <= hCount && hCount < 168)
col = 13;
else if(168 <= hCount && hCount < 180)
col = 14;
else if(180 <= hCount && hCount < 192)
col = 15;
else if(192 <= hCount && hCount < 204)
col = 16;
else if(204 <= hCount && hCount < 216)
col = 17;
else if(216 <= hCount && hCount < 228)
col = 18;
else if(228 <= hCount && hCount < 240)
col = 19;
else if(240 <= hCount && hCount < 252)
col = 20;
else if(252 <= hCount && hCount < 264)
col = 21;
else if(264 <= hCount && hCount < 276)
col = 22;
else if(276 <= hCount && hCount < 288)
col = 23;
else if(288 <= hCount && hCount < 300)
col = 24;
else if(300 <= hCount && hCount < 312)
col = 25;
else if(312 <= hCount && hCount < 324)
col = 26;
else if(324 <= hCount && hCount < 336)
col = 27;
else if(336 <= hCount && hCount < 348)
col = 28;
else if(348 <= hCount && hCount < 360)
col = 29;
else if(360 <= hCount && hCount < 372)
col = 30;
else if(372 <= hCount && hCount < 384)
col = 31;
else if(384 <= hCount && hCount < 396)
col = 32;
else if(396 <= hCount && hCount < 408)
col = 33;
else if(408 <= hCount && hCount < 420)
col = 34;
else if(420 <= hCount && hCount < 432)
col = 35;
else if(432 <= hCount && hCount < 444)
col = 36;
else if(444 <= hCount && hCount < 456)
col = 37;
else if(456 <= hCount && hCount < 468)
col = 38;
else if(468 <= hCount && hCount < 480)
col = 39;
else if(480 <= hCount && hCount < 492)
col = 40;
else if(492 <= hCount && hCount < 504)
col = 41;
else if(504 <= hCount && hCount < 516)
col = 42;
else if(516 <= hCount && hCount < 528)
col = 43;
else if(528 <= hCount && hCount < 540)
col = 44;
else if(540 <= hCount && hCount < 552)
col = 45;
else if(552 <= hCount && hCount < 564)
col = 46;
else if(564 <= hCount && hCount < 576)
col = 47;
else if(576 <= hCount && hCount < 588)
col = 48;
else if(588 <= hCount && hCount < 600)
col = 49;
else if(590 <= hCount && hCount < 612)
col = 50;
else if(612 <= hCount && hCount < 624)
col = 51;
else if(624 <= hCount && hCount < 636)
col = 52;
if(0 <= vCount && vCount < 12)
row = 0;
else if(12 <= vCount && vCount < 24)
row = 1;
else if(24 <= vCount && vCount < 36)
row = 2;
else if(36 <= vCount && vCount < 48)
row = 3;
else if(48 <= vCount && vCount < 60)
row = 4;
else if(60 <= vCount && vCount < 72)
row = 5;
else if(72 <= vCount && vCount < 84)
row = 6;
else if(84 <= vCount && vCount < 96)
row = 7;
else if(96 <= vCount && vCount < 108)
row = 8;
else if(108 <= vCount && vCount < 120)
row = 9;
else if(120 <= vCount && vCount < 132)
row = 10;
else if(132 <= vCount && vCount < 144)
row = 11;
else if(144 <= vCount && vCount < 156)
row = 12;
else if(156 <= vCount && vCount < 168)
row = 13;
else if(168 <= vCount && vCount < 180)
row = 14;
else if(180 <= vCount && vCount < 192)
row = 15;
else if(192 <= vCount && vCount < 204)
row = 16;
else if(204 <= vCount && vCount < 216)
row = 17;
else if(216 <= vCount && vCount < 228)
row = 18;
else if(228 <= vCount && vCount < 240)
row = 19;
else if(240 <= vCount && vCount < 252)
row = 20;
else if(252 <= vCount && vCount < 264)
row = 21;
else if(264 <= vCount && vCount < 276)
row = 22;
else if(276 <= vCount && vCount < 288)
row = 23;
else if(288 <= vCount && vCount < 300)
row = 24;
else if(300 <= vCount && vCount < 312)
row = 25;
else if(312 <= vCount && vCount < 324)
row = 26;
else if(324 <= vCount && vCount < 336)
row = 27;
else if(336 <= vCount && vCount < 348)
row = 28;
else if(348 <= vCount && vCount < 360)
row = 29;
else if(360 <= vCount && vCount < 372)
row = 30;
else if(372 <= vCount && vCount < 384)
row = 31;
else if(384 <= vCount && vCount < 396)
row = 32;
else if(396 <= vCount && vCount < 408)
row = 33;
else if(408 <= vCount && vCount < 420)
row = 34;
else if(420 <= vCount && vCount < 432)
row = 35;
else if(432 <= vCount && vCount < 444)
row = 36;
else if(444 <= vCount && vCount < 456)
row = 37;
else if(456 <= vCount && vCount < 468)
row = 38;
else if(468 <= vCount && vCount < 480)
row = 39;
end
always@(posedge clock)
begin
if (enable)
begin
if(vCount == 0 && hCount != 0)
glyphRow <= 0;
if(hCount == 639)
begin
if(glyphRow < 11)
glyphRow <= glyphRow + 1;
else
glyphRow <= 0;
end
end
end
always@(posedge clock)
begin
if(enable)
begin
glyphCol <= 0;
if(hCount > 0)
begin
if( hCount >= (53 * 12))
glyphCol <= 0;
else if ( glyphCol >= 11)
glyphCol <= 0;
else
glyphCol <= glyphCol + 1;
end
end
end
assign address = 16383 - (row * 53 + col);
endmodule | module GlyphMap(
input [10:0] hCount,
input [10:0] vCount,
input clock,
input enable,
output reg [3:0] glyphRow,
output reg [3:0] glyphCol,
output [13:0] address
); |
reg [5:0] col;
reg [5:0] row;
always@(*)
begin
col = 0;
row = 0;
if(0 <= hCount && hCount < 12)
col = 0;
else if(12 <= hCount && hCount < 24)
col = 1;
else if(24 <= hCount && hCount < 36)
col = 2;
else if(36 <= hCount && hCount < 48)
col = 3;
else if(48 <= hCount && hCount < 60)
col = 4;
else if(60 <= hCount && hCount < 72)
col = 5;
else if(72 <= hCount && hCount < 84)
col = 6;
else if(84 <= hCount && hCount < 96)
col = 7;
else if(96 <= hCount && hCount < 108)
col = 8;
else if(108 <= hCount && hCount < 120)
col = 9;
else if(120 <= hCount && hCount < 132)
col = 10;
else if(132 <= hCount && hCount < 144)
col = 11;
else if(144 <= hCount && hCount < 156)
col = 12;
else if(156 <= hCount && hCount < 168)
col = 13;
else if(168 <= hCount && hCount < 180)
col = 14;
else if(180 <= hCount && hCount < 192)
col = 15;
else if(192 <= hCount && hCount < 204)
col = 16;
else if(204 <= hCount && hCount < 216)
col = 17;
else if(216 <= hCount && hCount < 228)
col = 18;
else if(228 <= hCount && hCount < 240)
col = 19;
else if(240 <= hCount && hCount < 252)
col = 20;
else if(252 <= hCount && hCount < 264)
col = 21;
else if(264 <= hCount && hCount < 276)
col = 22;
else if(276 <= hCount && hCount < 288)
col = 23;
else if(288 <= hCount && hCount < 300)
col = 24;
else if(300 <= hCount && hCount < 312)
col = 25;
else if(312 <= hCount && hCount < 324)
col = 26;
else if(324 <= hCount && hCount < 336)
col = 27;
else if(336 <= hCount && hCount < 348)
col = 28;
else if(348 <= hCount && hCount < 360)
col = 29;
else if(360 <= hCount && hCount < 372)
col = 30;
else if(372 <= hCount && hCount < 384)
col = 31;
else if(384 <= hCount && hCount < 396)
col = 32;
else if(396 <= hCount && hCount < 408)
col = 33;
else if(408 <= hCount && hCount < 420)
col = 34;
else if(420 <= hCount && hCount < 432)
col = 35;
else if(432 <= hCount && hCount < 444)
col = 36;
else if(444 <= hCount && hCount < 456)
col = 37;
else if(456 <= hCount && hCount < 468)
col = 38;
else if(468 <= hCount && hCount < 480)
col = 39;
else if(480 <= hCount && hCount < 492)
col = 40;
else if(492 <= hCount && hCount < 504)
col = 41;
else if(504 <= hCount && hCount < 516)
col = 42;
else if(516 <= hCount && hCount < 528)
col = 43;
else if(528 <= hCount && hCount < 540)
col = 44;
else if(540 <= hCount && hCount < 552)
col = 45;
else if(552 <= hCount && hCount < 564)
col = 46;
else if(564 <= hCount && hCount < 576)
col = 47;
else if(576 <= hCount && hCount < 588)
col = 48;
else if(588 <= hCount && hCount < 600)
col = 49;
else if(590 <= hCount && hCount < 612)
col = 50;
else if(612 <= hCount && hCount < 624)
col = 51;
else if(624 <= hCount && hCount < 636)
col = 52;
if(0 <= vCount && vCount < 12)
row = 0;
else if(12 <= vCount && vCount < 24)
row = 1;
else if(24 <= vCount && vCount < 36)
row = 2;
else if(36 <= vCount && vCount < 48)
row = 3;
else if(48 <= vCount && vCount < 60)
row = 4;
else if(60 <= vCount && vCount < 72)
row = 5;
else if(72 <= vCount && vCount < 84)
row = 6;
else if(84 <= vCount && vCount < 96)
row = 7;
else if(96 <= vCount && vCount < 108)
row = 8;
else if(108 <= vCount && vCount < 120)
row = 9;
else if(120 <= vCount && vCount < 132)
row = 10;
else if(132 <= vCount && vCount < 144)
row = 11;
else if(144 <= vCount && vCount < 156)
row = 12;
else if(156 <= vCount && vCount < 168)
row = 13;
else if(168 <= vCount && vCount < 180)
row = 14;
else if(180 <= vCount && vCount < 192)
row = 15;
else if(192 <= vCount && vCount < 204)
row = 16;
else if(204 <= vCount && vCount < 216)
row = 17;
else if(216 <= vCount && vCount < 228)
row = 18;
else if(228 <= vCount && vCount < 240)
row = 19;
else if(240 <= vCount && vCount < 252)
row = 20;
else if(252 <= vCount && vCount < 264)
row = 21;
else if(264 <= vCount && vCount < 276)
row = 22;
else if(276 <= vCount && vCount < 288)
row = 23;
else if(288 <= vCount && vCount < 300)
row = 24;
else if(300 <= vCount && vCount < 312)
row = 25;
else if(312 <= vCount && vCount < 324)
row = 26;
else if(324 <= vCount && vCount < 336)
row = 27;
else if(336 <= vCount && vCount < 348)
row = 28;
else if(348 <= vCount && vCount < 360)
row = 29;
else if(360 <= vCount && vCount < 372)
row = 30;
else if(372 <= vCount && vCount < 384)
row = 31;
else if(384 <= vCount && vCount < 396)
row = 32;
else if(396 <= vCount && vCount < 408)
row = 33;
else if(408 <= vCount && vCount < 420)
row = 34;
else if(420 <= vCount && vCount < 432)
row = 35;
else if(432 <= vCount && vCount < 444)
row = 36;
else if(444 <= vCount && vCount < 456)
row = 37;
else if(456 <= vCount && vCount < 468)
row = 38;
else if(468 <= vCount && vCount < 480)
row = 39;
end
always@(posedge clock)
begin
if (enable)
begin
if(vCount == 0 && hCount != 0)
glyphRow <= 0;
if(hCount == 639)
begin
if(glyphRow < 11)
glyphRow <= glyphRow + 1;
else
glyphRow <= 0;
end
end
end
always@(posedge clock)
begin
if(enable)
begin
glyphCol <= 0;
if(hCount > 0)
begin
if( hCount >= (53 * 12))
glyphCol <= 0;
else if ( glyphCol >= 11)
glyphCol <= 0;
else
glyphCol <= glyphCol + 1;
end
end
end
assign address = 16383 - (row * 53 + col);
endmodule | 0 |
6,389 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/hgv.v | 116,048,589 | hgv.v | v | 39 | 104 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/hgv.v\n%Error: Exiting due to 4 error(s)\n' | 7,309 | module | module Processor_Processor_sch_tb();
reg Clk;
reg Reset;
reg [15:0] MULT;
reg [15:0] ALUB_input3;
reg [15:0] PCSource3;
Processor UUT (
.Clk(Clk),
.Reset(Reset),
.ALUB_input3(ALUB_input3),
.PCSource3(PCSource3)
);
initial begin
Clk = 0;
ALUB_input3 = 0;
Reset = 1;
#50;
Reset = 0;
end
always #10 Clk = ~Clk;
endmodule | module Processor_Processor_sch_tb(); |
reg Clk;
reg Reset;
reg [15:0] MULT;
reg [15:0] ALUB_input3;
reg [15:0] PCSource3;
Processor UUT (
.Clk(Clk),
.Reset(Reset),
.ALUB_input3(ALUB_input3),
.PCSource3(PCSource3)
);
initial begin
Clk = 0;
ALUB_input3 = 0;
Reset = 1;
#50;
Reset = 0;
end
always #10 Clk = ~Clk;
endmodule | 0 |
6,390 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/InstructionRegister.v | 116,048,589 | InstructionRegister.v | v | 36 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/InstructionRegister.v\n%Error: Exiting due to 4 error(s)\n' | 7,310 | module | module InstructionRegister(
input [15:0] Instruction_In,
input Clk,
input InstrWrite,
output reg [15:0] Instruction_Out
);
always@(posedge Clk) begin
if (InstrWrite)
Instruction_Out <= Instruction_In;
end
endmodule | module InstructionRegister(
input [15:0] Instruction_In,
input Clk,
input InstrWrite,
output reg [15:0] Instruction_Out
); |
always@(posedge Clk) begin
if (InstrWrite)
Instruction_Out <= Instruction_In;
end
endmodule | 0 |
6,391 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/IO_Mem_Controller.v | 116,048,589 | IO_Mem_Controller.v | v | 270 | 90 | [] | [] | [] | [(23, 269)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/IO_Mem_Controller.v\n%Error: Exiting due to 4 error(s)\n' | 7,312 | module | module IO_Mem_Controller(
input clk,
input MemWrite_IN,
input [15:0] ADDR_IN,
input [15:0] DATA_IN,
input [15:0] ReadData_IN,
input PacmanCountRdy,
input Ghost1CountRdy,
input Ghost2CountRdy,
input Ghost3CountRdy,
input Ghost4CountRdy,
input DrawTimerCountRdy,
input MouthTimerCountRdy,
input GhostFlashCountRdy,
input ScatterModeCountRdy,
output reg MemWrite_OUT,
output reg [13:0] ADDR_OUT,
output reg [15:0] DATA_OUT,
output reg [15:0] ReadData_OUT,
output reg [15:0] PacmanToCount,
output reg [15:0] Ghost1ToCount,
output reg [15:0] Ghost2ToCount,
output reg [15:0] Ghost3ToCount,
output reg [15:0] Ghost4ToCount,
output reg [15:0] DrawTimerToCount,
output reg [15:0] MouthTimerToCount,
output reg [15:0] GhostFlashToCount,
output reg [15:0] ScatterModeToCount,
input [7:0] NES_IN,
input [7:0] NES_IN2,
input [2:0] count3,
output reg [5:0] MP3Trig_OUT,
output reg [11:0] DACA_OUT,
output reg [11:0] DACB_OUT,
output reg [11:0] DACC_OUT,
output reg [7:0] led7Seg_OUT
);
reg [7:0] led7Seg;
reg [5:0] MP3Trig;
always@(*)
begin
led7Seg <= 0;
MemWrite_OUT <= 0;
ADDR_OUT <= 0;
DATA_OUT <= 0;
MemWrite_OUT <= 0;
ReadData_OUT <= 0;
MP3Trig <= 0;
DACA_OUT <= 0;
DACB_OUT <= 0;
DACC_OUT <= 0;
PacmanToCount <= 0;
Ghost1ToCount <= 0;
Ghost2ToCount <= 0;
Ghost3ToCount <= 0;
Ghost4ToCount <= 0;
DrawTimerToCount <= 0;
MouthTimerToCount <= 0;
GhostFlashToCount <= 0;
ScatterModeToCount <= 0;
case(ADDR_IN)
65535 : begin
ReadData_OUT <= {{15'b0},{NES_IN[0]}};
end
65534 : begin
ReadData_OUT <= {{15'b0},{NES_IN[1]}};
end
65533 : begin
ReadData_OUT <= {{15'b0},{NES_IN[2]}};
end
65532 : begin
ReadData_OUT <= {{15'b0},{NES_IN[3]}};
end
65531 : begin
ReadData_OUT <= {{15'b0},{NES_IN[4]}};
end
65530 : begin
ReadData_OUT <= {{15'b0},{NES_IN[5]}};
end
65529 : begin
ReadData_OUT <= {{15'b0},{NES_IN[6]}};
end
65528 : begin
ReadData_OUT <= {{15'b0},{NES_IN[7]}};
end
65527 : begin
if(MemWrite_IN)
MP3Trig <= DATA_IN;
end
65526 : begin
if(MemWrite_IN)
DACA_OUT <= DATA_IN;
end
65525 : begin
if(MemWrite_IN)
DACB_OUT <= DATA_IN;
end
65524 : begin
if(MemWrite_IN)
DACC_OUT <= DATA_IN;
end
65523 : begin
if(MemWrite_IN)
PacmanToCount <= DATA_IN;
end
65522 : begin
ReadData_OUT <= PacmanCountRdy;
end
65521 : begin
if(MemWrite_IN)
Ghost1ToCount <= DATA_IN;
end
65520 : begin
ReadData_OUT <= Ghost1CountRdy;
end
65519 : begin
if(MemWrite_IN)
Ghost2ToCount <= DATA_IN;
end
65518 : begin
ReadData_OUT <= Ghost2CountRdy;
end
65517 : begin
if(MemWrite_IN)
Ghost3ToCount <= DATA_IN;
end
65516 : begin
ReadData_OUT <= Ghost3CountRdy;
end
65515 : begin
if(MemWrite_IN)
Ghost4ToCount <= DATA_IN;
end
65514 : begin
ReadData_OUT <= Ghost4CountRdy;
end
65513 : begin
if(MemWrite_IN)
DrawTimerToCount <= DATA_IN;
end
65512 : begin
ReadData_OUT <= DrawTimerCountRdy;
end
65511 : begin
if(MemWrite_IN)
MouthTimerToCount <= DATA_IN;
end
65510 : begin
ReadData_OUT <= MouthTimerCountRdy;
end
65509 : begin
if(MemWrite_IN)
GhostFlashToCount <= DATA_IN;
end
65508 : begin
ReadData_OUT <= GhostFlashCountRdy;
end
65507 : begin
if(MemWrite_IN)
ScatterModeToCount <= DATA_IN;
end
65506 : begin
ReadData_OUT <= ScatterModeCountRdy;
end
13201 : begin
led7Seg <= DATA_IN[7:0];
MemWrite_OUT <= MemWrite_IN;
ADDR_OUT <= ADDR_IN;
DATA_OUT <= DATA_IN;
MemWrite_OUT <= MemWrite_IN;
ReadData_OUT <= ReadData_IN;
end
65505 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[0]}};
end
65504 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[1]}};
end
65503 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[2]}};
end
65502 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[3]}};
end
65501 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[4]}};
end
65500 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[5]}};
end
65499 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[6]}};
end
65498 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[7]}};
end
65497 : begin
ReadData_OUT <= count3;
end
default : begin
MemWrite_OUT <= MemWrite_IN;
ADDR_OUT <= ADDR_IN;
DATA_OUT <= DATA_IN;
MemWrite_OUT <= MemWrite_IN;
ReadData_OUT <= ReadData_IN;
end
endcase
end
always@(posedge clk)
begin
if(MemWrite_IN && ADDR_IN == 13201)
led7Seg_OUT <= led7Seg;
end
always@(posedge clk)
begin
if(MemWrite_IN && ADDR_IN == 65527)
MP3Trig_OUT <= MP3Trig;
end
endmodule | module IO_Mem_Controller(
input clk,
input MemWrite_IN,
input [15:0] ADDR_IN,
input [15:0] DATA_IN,
input [15:0] ReadData_IN,
input PacmanCountRdy,
input Ghost1CountRdy,
input Ghost2CountRdy,
input Ghost3CountRdy,
input Ghost4CountRdy,
input DrawTimerCountRdy,
input MouthTimerCountRdy,
input GhostFlashCountRdy,
input ScatterModeCountRdy,
output reg MemWrite_OUT,
output reg [13:0] ADDR_OUT,
output reg [15:0] DATA_OUT,
output reg [15:0] ReadData_OUT,
output reg [15:0] PacmanToCount,
output reg [15:0] Ghost1ToCount,
output reg [15:0] Ghost2ToCount,
output reg [15:0] Ghost3ToCount,
output reg [15:0] Ghost4ToCount,
output reg [15:0] DrawTimerToCount,
output reg [15:0] MouthTimerToCount,
output reg [15:0] GhostFlashToCount,
output reg [15:0] ScatterModeToCount,
input [7:0] NES_IN,
input [7:0] NES_IN2,
input [2:0] count3,
output reg [5:0] MP3Trig_OUT,
output reg [11:0] DACA_OUT,
output reg [11:0] DACB_OUT,
output reg [11:0] DACC_OUT,
output reg [7:0] led7Seg_OUT
); |
reg [7:0] led7Seg;
reg [5:0] MP3Trig;
always@(*)
begin
led7Seg <= 0;
MemWrite_OUT <= 0;
ADDR_OUT <= 0;
DATA_OUT <= 0;
MemWrite_OUT <= 0;
ReadData_OUT <= 0;
MP3Trig <= 0;
DACA_OUT <= 0;
DACB_OUT <= 0;
DACC_OUT <= 0;
PacmanToCount <= 0;
Ghost1ToCount <= 0;
Ghost2ToCount <= 0;
Ghost3ToCount <= 0;
Ghost4ToCount <= 0;
DrawTimerToCount <= 0;
MouthTimerToCount <= 0;
GhostFlashToCount <= 0;
ScatterModeToCount <= 0;
case(ADDR_IN)
65535 : begin
ReadData_OUT <= {{15'b0},{NES_IN[0]}};
end
65534 : begin
ReadData_OUT <= {{15'b0},{NES_IN[1]}};
end
65533 : begin
ReadData_OUT <= {{15'b0},{NES_IN[2]}};
end
65532 : begin
ReadData_OUT <= {{15'b0},{NES_IN[3]}};
end
65531 : begin
ReadData_OUT <= {{15'b0},{NES_IN[4]}};
end
65530 : begin
ReadData_OUT <= {{15'b0},{NES_IN[5]}};
end
65529 : begin
ReadData_OUT <= {{15'b0},{NES_IN[6]}};
end
65528 : begin
ReadData_OUT <= {{15'b0},{NES_IN[7]}};
end
65527 : begin
if(MemWrite_IN)
MP3Trig <= DATA_IN;
end
65526 : begin
if(MemWrite_IN)
DACA_OUT <= DATA_IN;
end
65525 : begin
if(MemWrite_IN)
DACB_OUT <= DATA_IN;
end
65524 : begin
if(MemWrite_IN)
DACC_OUT <= DATA_IN;
end
65523 : begin
if(MemWrite_IN)
PacmanToCount <= DATA_IN;
end
65522 : begin
ReadData_OUT <= PacmanCountRdy;
end
65521 : begin
if(MemWrite_IN)
Ghost1ToCount <= DATA_IN;
end
65520 : begin
ReadData_OUT <= Ghost1CountRdy;
end
65519 : begin
if(MemWrite_IN)
Ghost2ToCount <= DATA_IN;
end
65518 : begin
ReadData_OUT <= Ghost2CountRdy;
end
65517 : begin
if(MemWrite_IN)
Ghost3ToCount <= DATA_IN;
end
65516 : begin
ReadData_OUT <= Ghost3CountRdy;
end
65515 : begin
if(MemWrite_IN)
Ghost4ToCount <= DATA_IN;
end
65514 : begin
ReadData_OUT <= Ghost4CountRdy;
end
65513 : begin
if(MemWrite_IN)
DrawTimerToCount <= DATA_IN;
end
65512 : begin
ReadData_OUT <= DrawTimerCountRdy;
end
65511 : begin
if(MemWrite_IN)
MouthTimerToCount <= DATA_IN;
end
65510 : begin
ReadData_OUT <= MouthTimerCountRdy;
end
65509 : begin
if(MemWrite_IN)
GhostFlashToCount <= DATA_IN;
end
65508 : begin
ReadData_OUT <= GhostFlashCountRdy;
end
65507 : begin
if(MemWrite_IN)
ScatterModeToCount <= DATA_IN;
end
65506 : begin
ReadData_OUT <= ScatterModeCountRdy;
end
13201 : begin
led7Seg <= DATA_IN[7:0];
MemWrite_OUT <= MemWrite_IN;
ADDR_OUT <= ADDR_IN;
DATA_OUT <= DATA_IN;
MemWrite_OUT <= MemWrite_IN;
ReadData_OUT <= ReadData_IN;
end
65505 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[0]}};
end
65504 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[1]}};
end
65503 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[2]}};
end
65502 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[3]}};
end
65501 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[4]}};
end
65500 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[5]}};
end
65499 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[6]}};
end
65498 : begin
ReadData_OUT <= {{15'b0},{NES_IN2[7]}};
end
65497 : begin
ReadData_OUT <= count3;
end
default : begin
MemWrite_OUT <= MemWrite_IN;
ADDR_OUT <= ADDR_IN;
DATA_OUT <= DATA_IN;
MemWrite_OUT <= MemWrite_IN;
ReadData_OUT <= ReadData_IN;
end
endcase
end
always@(posedge clk)
begin
if(MemWrite_IN && ADDR_IN == 13201)
led7Seg_OUT <= led7Seg;
end
always@(posedge clk)
begin
if(MemWrite_IN && ADDR_IN == 65527)
MP3Trig_OUT <= MP3Trig;
end
endmodule | 0 |
6,392 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/Memory.v | 116,048,589 | Memory.v | v | 38 | 83 | [] | [] | [] | [(21, 37)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/Memory.v\n%Error: Exiting due to 4 error(s)\n' | 7,313 | module | module Memory(
input [13:0] ADDR,
input [15:0] DATA,
input MemWrite,
input clk,
input pxlClk,
input [13:0] glyphAdd,
output [15:0] ReadData,
output [15:0] glyphData
);
wire enable;
assign enable = 1;
exmem mem(~clk,enable,MemWrite,ADDR,DATA,ReadData, pxlClk, glyphAdd, glyphData);
endmodule | module Memory(
input [13:0] ADDR,
input [15:0] DATA,
input MemWrite,
input clk,
input pxlClk,
input [13:0] glyphAdd,
output [15:0] ReadData,
output [15:0] glyphData
); |
wire enable;
assign enable = 1;
exmem mem(~clk,enable,MemWrite,ADDR,DATA,ReadData, pxlClk, glyphAdd, glyphData);
endmodule | 0 |
6,393 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/milliSecondCounter.v | 116,048,589 | milliSecondCounter.v | v | 138 | 92 | [] | [] | [] | [(24, 137)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/milliSecondCounter.v\n%Error: Exiting due to 4 error(s)\n' | 7,314 | module | module milliSecondCounter(
input clock,
input reset,
input [15:0] toCount,
output reg countRdy
);
parameter idle = 0;
parameter latchData = 1;
parameter startCount = 2;
parameter countingState = 3;
parameter displayState = 4;
reg[2:0] NS = 0;
reg[2:0] PS = 0;
reg[31:0] count = 0;
always@(posedge clock)
begin
if(reset)
PS <= idle;
else
PS <= NS;
end
always@(*)
begin
NS <= 0;
case(PS)
idle : NS <= (toCount != 0) ? latchData : idle;
latchData : NS <= startCount;
startCount : NS <= countingState;
countingState : NS <= (count <= 1) ? displayState : countingState;
displayState : NS <= (toCount != 0) ? startCount : displayState;
default : NS <= idle;
endcase
end
always@(posedge clock)
begin
if (reset)
begin
count <= 0;
countRdy <= 0;
end
else
begin
countRdy <= 0;
case(PS)
idle : begin
count <= 0;
countRdy <= 0;
count <= toCount;
end
latchData : begin
countRdy <=0;
if(toCount > 0)
count <= toCount;
end
startCount : begin
count <= count * 50000 - 3;
countRdy <= 0;
end
countingState : begin
count <= count - 1;
countRdy <= 0;
end
displayState : begin
count <= toCount;
countRdy <= 1;
end
default : begin
count <= 0;
countRdy <= 0;
end
endcase
end
end
endmodule | module milliSecondCounter(
input clock,
input reset,
input [15:0] toCount,
output reg countRdy
); |
parameter idle = 0;
parameter latchData = 1;
parameter startCount = 2;
parameter countingState = 3;
parameter displayState = 4;
reg[2:0] NS = 0;
reg[2:0] PS = 0;
reg[31:0] count = 0;
always@(posedge clock)
begin
if(reset)
PS <= idle;
else
PS <= NS;
end
always@(*)
begin
NS <= 0;
case(PS)
idle : NS <= (toCount != 0) ? latchData : idle;
latchData : NS <= startCount;
startCount : NS <= countingState;
countingState : NS <= (count <= 1) ? displayState : countingState;
displayState : NS <= (toCount != 0) ? startCount : displayState;
default : NS <= idle;
endcase
end
always@(posedge clock)
begin
if (reset)
begin
count <= 0;
countRdy <= 0;
end
else
begin
countRdy <= 0;
case(PS)
idle : begin
count <= 0;
countRdy <= 0;
count <= toCount;
end
latchData : begin
countRdy <=0;
if(toCount > 0)
count <= toCount;
end
startCount : begin
count <= count * 50000 - 3;
countRdy <= 0;
end
countingState : begin
count <= count - 1;
countRdy <= 0;
end
displayState : begin
count <= toCount;
countRdy <= 1;
end
default : begin
count <= 0;
countRdy <= 0;
end
endcase
end
end
endmodule | 0 |
6,394 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mips.v | 116,048,589 | mips.v | v | 379 | 92 | [] | [] | [] | null | line:206: before: "begin" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mips.v\n%Error: Exiting due to 4 error(s)\n' | 7,315 | module | module mips #(parameter WIDTH = 8, REGBITS = 3)
(input clk, reset,
input [WIDTH-1:0] memdata,
output memread, memwrite,
output [WIDTH-1:0] adr, writedata);
wire [31:0] instr;
wire zero, alusrca, memtoreg, iord, pcen, regwrite, regdst;
wire [1:0] aluop,pcsource,alusrcb;
wire [3:0] irwrite;
wire [2:0] alucont;
controller cont(clk, reset, instr[31:26], zero, memread, memwrite,
alusrca, memtoreg, iord, pcen, regwrite, regdst,
pcsource, alusrcb, aluop, irwrite);
alucontrol ac(aluop, instr[5:0], alucont);
datapath #(WIDTH, REGBITS)
dp(clk, reset, memdata, alusrca, memtoreg, iord, pcen,
regwrite, regdst, pcsource, alusrcb, irwrite, alucont,
zero, instr, adr, writedata);
endmodule | module mips #(parameter WIDTH = 8, REGBITS = 3)
(input clk, reset,
input [WIDTH-1:0] memdata,
output memread, memwrite,
output [WIDTH-1:0] adr, writedata); |
wire [31:0] instr;
wire zero, alusrca, memtoreg, iord, pcen, regwrite, regdst;
wire [1:0] aluop,pcsource,alusrcb;
wire [3:0] irwrite;
wire [2:0] alucont;
controller cont(clk, reset, instr[31:26], zero, memread, memwrite,
alusrca, memtoreg, iord, pcen, regwrite, regdst,
pcsource, alusrcb, aluop, irwrite);
alucontrol ac(aluop, instr[5:0], alucont);
datapath #(WIDTH, REGBITS)
dp(clk, reset, memdata, alusrca, memtoreg, iord, pcen,
regwrite, regdst, pcsource, alusrcb, irwrite, alucont,
zero, instr, adr, writedata);
endmodule | 0 |
6,395 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mips.v | 116,048,589 | mips.v | v | 379 | 92 | [] | [] | [] | null | line:206: before: "begin" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mips.v\n%Error: Exiting due to 4 error(s)\n' | 7,315 | module | module controller(input clk, reset,
input [5:0] op,
input zero,
output reg memread, memwrite, alusrca, memtoreg, iord,
output pcen,
output reg regwrite, regdst,
output reg [1:0] pcsource, alusrcb, aluop,
output reg [3:0] irwrite);
parameter FETCH1 = 4'b0001;
parameter FETCH2 = 4'b0010;
parameter FETCH3 = 4'b0011;
parameter FETCH4 = 4'b0100;
parameter DECODE = 4'b0101;
parameter MEMADR = 4'b0110;
parameter LBRD = 4'b0111;
parameter LBWR = 4'b1000;
parameter SBWR = 4'b1001;
parameter RTYPEEX = 4'b1010;
parameter RTYPEWR = 4'b1011;
parameter BEQEX = 4'b1100;
parameter JEX = 4'b1101;
parameter ADDIEX = 4'b1110;
parameter ADDIWR = 4'b1111;
parameter LB = 6'b100000;
parameter SB = 6'b101000;
parameter RTYPE = 6'b000000;
parameter BEQ = 6'b000100;
parameter J = 6'b000010;
parameter ADDI = 6'b001000;
reg [3:0] state, nextstate;
reg pcwrite, pcwritecond;
always @(posedge clk)
if(reset) state <= FETCH1;
else state <= nextstate;
always @(*)
begin
case(state)
FETCH1: nextstate <= FETCH2;
FETCH2: nextstate <= FETCH3;
FETCH3: nextstate <= FETCH4;
FETCH4: nextstate <= DECODE;
DECODE: case(op)
LB: nextstate <= MEMADR;
SB: nextstate <= MEMADR;
RTYPE: nextstate <= RTYPEEX;
BEQ: nextstate <= BEQEX;
J: nextstate <= JEX;
ADDI: nextstate <= ADDIEX;
default: nextstate <= FETCH1;
endcase
MEMADR: case(op)
LB: nextstate <= LBRD;
SB: nextstate <= SBWR;
default: nextstate <= FETCH1;
endcase
LBRD: nextstate <= LBWR;
LBWR: nextstate <= FETCH1;
SBWR: nextstate <= FETCH1;
RTYPEEX: nextstate <= RTYPEWR;
RTYPEWR: nextstate <= FETCH1;
BEQEX: nextstate <= FETCH1;
JEX: nextstate <= FETCH1;
ADDIEX: nextstate <= ADDIWR;
ADDIWR: nextstate <= FETCH1;
default: nextstate <= FETCH1;
endcase
end
always @(*)
begin
irwrite <= 4'b0000;
pcwrite <= 0; pcwritecond <= 0;
regwrite <= 0; regdst <= 0;
memread <= 0; memwrite <= 0;
alusrca <= 0; alusrcb <= 2'b00; aluop <= 2'b00;
pcsource <= 2'b00;
iord <= 0; memtoreg <= 0;
case(state)
FETCH1:
begin
memread <= 1;
irwrite <= 4'b0001;
alusrcb <= 2'b01;
pcwrite <= 1;
end
FETCH2:
begin
memread <= 1;
irwrite <= 4'b0010;
alusrcb <= 2'b01;
pcwrite <= 1;
end
FETCH3:
begin
memread <= 1;
irwrite <= 4'b0100;
alusrcb <= 2'b01;
pcwrite <= 1;
end
FETCH4:
begin
memread <= 1;
irwrite <= 4'b1000;
alusrcb <= 2'b01;
pcwrite <= 1;
end
DECODE: alusrcb <= 2'b11;
MEMADR:
begin
alusrca <= 1;
alusrcb <= 2'b10;
end
LBRD:
begin
memread <= 1;
iord <= 1;
end
LBWR:
begin
regwrite <= 1;
memtoreg <= 1;
end
SBWR:
begin
memwrite <= 1;
iord <= 1;
end
RTYPEEX:
begin
alusrca <= 1;
aluop <= 2'b10;
end
RTYPEWR:
begin
regdst <= 1;
regwrite <= 1;
end
BEQEX:
begin
alusrca <= 1;
aluop <= 2'b01;
pcwritecond <= 1;
pcsource <= 2'b01;
end
JEX:
begin
pcwrite <= 1;
pcsource <= 2'b10;
end
ADDIEX:
begin
alusrca <= 1;
aluop <= 2'b00;
alusrcb <= 2'b10;
end
ADDIWR:
begin
regwrite <= 1;
end
default
begin
end
endcase
end
assign pcen = pcwrite | (pcwritecond & zero);
endmodule | module controller(input clk, reset,
input [5:0] op,
input zero,
output reg memread, memwrite, alusrca, memtoreg, iord,
output pcen,
output reg regwrite, regdst,
output reg [1:0] pcsource, alusrcb, aluop,
output reg [3:0] irwrite); |
parameter FETCH1 = 4'b0001;
parameter FETCH2 = 4'b0010;
parameter FETCH3 = 4'b0011;
parameter FETCH4 = 4'b0100;
parameter DECODE = 4'b0101;
parameter MEMADR = 4'b0110;
parameter LBRD = 4'b0111;
parameter LBWR = 4'b1000;
parameter SBWR = 4'b1001;
parameter RTYPEEX = 4'b1010;
parameter RTYPEWR = 4'b1011;
parameter BEQEX = 4'b1100;
parameter JEX = 4'b1101;
parameter ADDIEX = 4'b1110;
parameter ADDIWR = 4'b1111;
parameter LB = 6'b100000;
parameter SB = 6'b101000;
parameter RTYPE = 6'b000000;
parameter BEQ = 6'b000100;
parameter J = 6'b000010;
parameter ADDI = 6'b001000;
reg [3:0] state, nextstate;
reg pcwrite, pcwritecond;
always @(posedge clk)
if(reset) state <= FETCH1;
else state <= nextstate;
always @(*)
begin
case(state)
FETCH1: nextstate <= FETCH2;
FETCH2: nextstate <= FETCH3;
FETCH3: nextstate <= FETCH4;
FETCH4: nextstate <= DECODE;
DECODE: case(op)
LB: nextstate <= MEMADR;
SB: nextstate <= MEMADR;
RTYPE: nextstate <= RTYPEEX;
BEQ: nextstate <= BEQEX;
J: nextstate <= JEX;
ADDI: nextstate <= ADDIEX;
default: nextstate <= FETCH1;
endcase
MEMADR: case(op)
LB: nextstate <= LBRD;
SB: nextstate <= SBWR;
default: nextstate <= FETCH1;
endcase
LBRD: nextstate <= LBWR;
LBWR: nextstate <= FETCH1;
SBWR: nextstate <= FETCH1;
RTYPEEX: nextstate <= RTYPEWR;
RTYPEWR: nextstate <= FETCH1;
BEQEX: nextstate <= FETCH1;
JEX: nextstate <= FETCH1;
ADDIEX: nextstate <= ADDIWR;
ADDIWR: nextstate <= FETCH1;
default: nextstate <= FETCH1;
endcase
end
always @(*)
begin
irwrite <= 4'b0000;
pcwrite <= 0; pcwritecond <= 0;
regwrite <= 0; regdst <= 0;
memread <= 0; memwrite <= 0;
alusrca <= 0; alusrcb <= 2'b00; aluop <= 2'b00;
pcsource <= 2'b00;
iord <= 0; memtoreg <= 0;
case(state)
FETCH1:
begin
memread <= 1;
irwrite <= 4'b0001;
alusrcb <= 2'b01;
pcwrite <= 1;
end
FETCH2:
begin
memread <= 1;
irwrite <= 4'b0010;
alusrcb <= 2'b01;
pcwrite <= 1;
end
FETCH3:
begin
memread <= 1;
irwrite <= 4'b0100;
alusrcb <= 2'b01;
pcwrite <= 1;
end
FETCH4:
begin
memread <= 1;
irwrite <= 4'b1000;
alusrcb <= 2'b01;
pcwrite <= 1;
end
DECODE: alusrcb <= 2'b11;
MEMADR:
begin
alusrca <= 1;
alusrcb <= 2'b10;
end
LBRD:
begin
memread <= 1;
iord <= 1;
end
LBWR:
begin
regwrite <= 1;
memtoreg <= 1;
end
SBWR:
begin
memwrite <= 1;
iord <= 1;
end
RTYPEEX:
begin
alusrca <= 1;
aluop <= 2'b10;
end
RTYPEWR:
begin
regdst <= 1;
regwrite <= 1;
end
BEQEX:
begin
alusrca <= 1;
aluop <= 2'b01;
pcwritecond <= 1;
pcsource <= 2'b01;
end
JEX:
begin
pcwrite <= 1;
pcsource <= 2'b10;
end
ADDIEX:
begin
alusrca <= 1;
aluop <= 2'b00;
alusrcb <= 2'b10;
end
ADDIWR:
begin
regwrite <= 1;
end
default
begin
end
endcase
end
assign pcen = pcwrite | (pcwritecond & zero);
endmodule | 0 |
6,396 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mips.v | 116,048,589 | mips.v | v | 379 | 92 | [] | [] | [] | null | line:206: before: "begin" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mips.v\n%Error: Exiting due to 4 error(s)\n' | 7,315 | module | module alucontrol(input [1:0] aluop,
input [5:0] funct,
output reg [2:0] alucont);
always @(*)
case(aluop)
2'b00: alucont <= 3'b010;
2'b01: alucont <= 3'b110;
default: case(funct)
6'b100000: alucont <= 3'b010;
6'b100010: alucont <= 3'b110;
6'b100100: alucont <= 3'b000;
6'b100101: alucont <= 3'b001;
6'b101010: alucont <= 3'b111;
default: alucont <= 3'b101;
endcase
endcase
endmodule | module alucontrol(input [1:0] aluop,
input [5:0] funct,
output reg [2:0] alucont); |
always @(*)
case(aluop)
2'b00: alucont <= 3'b010;
2'b01: alucont <= 3'b110;
default: case(funct)
6'b100000: alucont <= 3'b010;
6'b100010: alucont <= 3'b110;
6'b100100: alucont <= 3'b000;
6'b100101: alucont <= 3'b001;
6'b101010: alucont <= 3'b111;
default: alucont <= 3'b101;
endcase
endcase
endmodule | 0 |
6,397 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mips.v | 116,048,589 | mips.v | v | 379 | 92 | [] | [] | [] | null | line:206: before: "begin" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mips.v\n%Error: Exiting due to 4 error(s)\n' | 7,315 | module | module datapath #(parameter WIDTH = 8, REGBITS = 3)
(input clk, reset,
input [WIDTH-1:0] memdata,
input alusrca, memtoreg, iord, pcen, regwrite, regdst,
input [1:0] pcsource, alusrcb,
input [3:0] irwrite,
input [2:0] alucont,
output zero,
output [31:0] instr,
output [WIDTH-1:0] adr, writedata);
localparam CONST_ZERO = 8'b0;
localparam CONST_ONE = 8'b1;
wire [REGBITS-1:0] ra1, ra2, wa;
wire [WIDTH-1:0] pc, nextpc, md, rd1, rd2, wd, a, src1, src2, aluresult,
aluout, constx4;
assign constx4 = {instr[WIDTH-3:0],2'b00};
assign ra1 = instr[REGBITS+20:21];
assign ra2 = instr[REGBITS+15:16];
mux2 #(REGBITS) regmux(instr[REGBITS+15:16], instr[REGBITS+10:11], regdst, wa);
flopen #(8) ir0(clk, irwrite[0], memdata[7:0], instr[7:0]);
flopen #(8) ir1(clk, irwrite[1], memdata[7:0], instr[15:8]);
flopen #(8) ir2(clk, irwrite[2], memdata[7:0], instr[23:16]);
flopen #(8) ir3(clk, irwrite[3], memdata[7:0], instr[31:24]);
flopenr #(WIDTH) pcreg(clk, reset, pcen, nextpc, pc);
flop #(WIDTH) mdr(clk, memdata, md);
flop #(WIDTH) areg(clk, rd1, a);
flop #(WIDTH) wrd(clk, rd2, writedata);
flop #(WIDTH) res(clk, aluresult, aluout);
mux2 #(WIDTH) adrmux(pc, aluout, iord, adr);
mux2 #(WIDTH) src1mux(pc, a, alusrca, src1);
mux4 #(WIDTH) src2mux(writedata, CONST_ONE, instr[WIDTH-1:0],
constx4, alusrcb, src2);
mux4 #(WIDTH) pcmux(aluresult, aluout, constx4, CONST_ZERO, pcsource, nextpc);
mux2 #(WIDTH) wdmux(aluout, md, memtoreg, wd);
regfile #(WIDTH,REGBITS) rf(clk, regwrite, ra1, ra2, wa, wd, rd1, rd2);
alu #(WIDTH) alunit(src1, src2, alucont, aluresult);
zerodetect #(WIDTH) zd(aluresult, zero);
endmodule | module datapath #(parameter WIDTH = 8, REGBITS = 3)
(input clk, reset,
input [WIDTH-1:0] memdata,
input alusrca, memtoreg, iord, pcen, regwrite, regdst,
input [1:0] pcsource, alusrcb,
input [3:0] irwrite,
input [2:0] alucont,
output zero,
output [31:0] instr,
output [WIDTH-1:0] adr, writedata); |
localparam CONST_ZERO = 8'b0;
localparam CONST_ONE = 8'b1;
wire [REGBITS-1:0] ra1, ra2, wa;
wire [WIDTH-1:0] pc, nextpc, md, rd1, rd2, wd, a, src1, src2, aluresult,
aluout, constx4;
assign constx4 = {instr[WIDTH-3:0],2'b00};
assign ra1 = instr[REGBITS+20:21];
assign ra2 = instr[REGBITS+15:16];
mux2 #(REGBITS) regmux(instr[REGBITS+15:16], instr[REGBITS+10:11], regdst, wa);
flopen #(8) ir0(clk, irwrite[0], memdata[7:0], instr[7:0]);
flopen #(8) ir1(clk, irwrite[1], memdata[7:0], instr[15:8]);
flopen #(8) ir2(clk, irwrite[2], memdata[7:0], instr[23:16]);
flopen #(8) ir3(clk, irwrite[3], memdata[7:0], instr[31:24]);
flopenr #(WIDTH) pcreg(clk, reset, pcen, nextpc, pc);
flop #(WIDTH) mdr(clk, memdata, md);
flop #(WIDTH) areg(clk, rd1, a);
flop #(WIDTH) wrd(clk, rd2, writedata);
flop #(WIDTH) res(clk, aluresult, aluout);
mux2 #(WIDTH) adrmux(pc, aluout, iord, adr);
mux2 #(WIDTH) src1mux(pc, a, alusrca, src1);
mux4 #(WIDTH) src2mux(writedata, CONST_ONE, instr[WIDTH-1:0],
constx4, alusrcb, src2);
mux4 #(WIDTH) pcmux(aluresult, aluout, constx4, CONST_ZERO, pcsource, nextpc);
mux2 #(WIDTH) wdmux(aluout, md, memtoreg, wd);
regfile #(WIDTH,REGBITS) rf(clk, regwrite, ra1, ra2, wa, wd, rd1, rd2);
alu #(WIDTH) alunit(src1, src2, alucont, aluresult);
zerodetect #(WIDTH) zd(aluresult, zero);
endmodule | 0 |
6,398 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mips.v | 116,048,589 | mips.v | v | 379 | 92 | [] | [] | [] | null | line:206: before: "begin" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mips.v\n%Error: Exiting due to 4 error(s)\n' | 7,315 | module | module alu #(parameter WIDTH = 8)
(input [WIDTH-1:0] a, b,
input [2:0] alucont,
output reg [WIDTH-1:0] result);
wire [WIDTH-1:0] b2, sum, slt;
assign b2 = alucont[2] ? ~b:b;
assign sum = a + b2 + alucont[2];
assign slt = sum[WIDTH-1];
always@(*)
case(alucont[1:0])
2'b00: result <= a & b;
2'b01: result <= a | b;
2'b10: result <= sum;
2'b11: result <= slt;
endcase
endmodule | module alu #(parameter WIDTH = 8)
(input [WIDTH-1:0] a, b,
input [2:0] alucont,
output reg [WIDTH-1:0] result); |
wire [WIDTH-1:0] b2, sum, slt;
assign b2 = alucont[2] ? ~b:b;
assign sum = a + b2 + alucont[2];
assign slt = sum[WIDTH-1];
always@(*)
case(alucont[1:0])
2'b00: result <= a & b;
2'b01: result <= a | b;
2'b10: result <= sum;
2'b11: result <= slt;
endcase
endmodule | 0 |
6,399 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mips.v | 116,048,589 | mips.v | v | 379 | 92 | [] | [] | [] | null | line:206: before: "begin" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mips.v\n%Error: Exiting due to 4 error(s)\n' | 7,315 | module | module regfile #(parameter WIDTH = 8, REGBITS = 3)
(input clk,
input regwrite,
input [REGBITS-1:0] ra1, ra2, wa,
input [WIDTH-1:0] wd,
output [WIDTH-1:0] rd1, rd2);
reg [WIDTH-1:0] RAM [(1<<REGBITS)-1:0];
always @(posedge clk)
if (regwrite) RAM[wa] <= wd;
assign rd1 = ra1 ? RAM[ra1] : 0;
assign rd2 = ra2 ? RAM[ra2] : 0;
endmodule | module regfile #(parameter WIDTH = 8, REGBITS = 3)
(input clk,
input regwrite,
input [REGBITS-1:0] ra1, ra2, wa,
input [WIDTH-1:0] wd,
output [WIDTH-1:0] rd1, rd2); |
reg [WIDTH-1:0] RAM [(1<<REGBITS)-1:0];
always @(posedge clk)
if (regwrite) RAM[wa] <= wd;
assign rd1 = ra1 ? RAM[ra1] : 0;
assign rd2 = ra2 ? RAM[ra2] : 0;
endmodule | 0 |
6,400 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mips.v | 116,048,589 | mips.v | v | 379 | 92 | [] | [] | [] | null | line:206: before: "begin" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mips.v\n%Error: Exiting due to 4 error(s)\n' | 7,315 | module | module zerodetect #(parameter WIDTH = 8)
(input [WIDTH-1:0] a,
output y);
assign y = (a==0);
endmodule | module zerodetect #(parameter WIDTH = 8)
(input [WIDTH-1:0] a,
output y); |
assign y = (a==0);
endmodule | 0 |
6,401 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mips.v | 116,048,589 | mips.v | v | 379 | 92 | [] | [] | [] | null | line:206: before: "begin" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mips.v\n%Error: Exiting due to 4 error(s)\n' | 7,315 | module | module flop #(parameter WIDTH = 8)
(input clk,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
always @(posedge clk)
q <= d;
endmodule | module flop #(parameter WIDTH = 8)
(input clk,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q); |
always @(posedge clk)
q <= d;
endmodule | 0 |
6,402 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mips.v | 116,048,589 | mips.v | v | 379 | 92 | [] | [] | [] | null | line:206: before: "begin" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mips.v\n%Error: Exiting due to 4 error(s)\n' | 7,315 | module | module flopen #(parameter WIDTH = 8)
(input clk, en,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
always @(posedge clk)
if (en) q <= d;
endmodule | module flopen #(parameter WIDTH = 8)
(input clk, en,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q); |
always @(posedge clk)
if (en) q <= d;
endmodule | 0 |
6,403 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mips.v | 116,048,589 | mips.v | v | 379 | 92 | [] | [] | [] | null | line:206: before: "begin" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mips.v\n%Error: Exiting due to 4 error(s)\n' | 7,315 | module | module flopenr #(parameter WIDTH = 8)
(input clk, reset, en,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
always @(posedge clk)
if (reset) q <= 0;
else if (en) q <= d;
endmodule | module flopenr #(parameter WIDTH = 8)
(input clk, reset, en,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q); |
always @(posedge clk)
if (reset) q <= 0;
else if (en) q <= d;
endmodule | 0 |
6,404 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mips.v | 116,048,589 | mips.v | v | 379 | 92 | [] | [] | [] | null | line:206: before: "begin" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mips.v\n%Error: Exiting due to 4 error(s)\n' | 7,315 | module | module mux2 #(parameter WIDTH = 8)
(input [WIDTH-1:0] d0, d1,
input s,
output [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule | module mux2 #(parameter WIDTH = 8)
(input [WIDTH-1:0] d0, d1,
input s,
output [WIDTH-1:0] y); |
assign y = s ? d1 : d0;
endmodule | 0 |
6,405 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mips.v | 116,048,589 | mips.v | v | 379 | 92 | [] | [] | [] | null | line:206: before: "begin" | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mips.v\n%Error: Exiting due to 4 error(s)\n' | 7,315 | module | module mux4 #(parameter WIDTH = 8)
(input [WIDTH-1:0] d0, d1, d2, d3,
input [1:0] s,
output reg [WIDTH-1:0] y);
always @(*)
case(s)
2'b00: y <= d0;
2'b01: y <= d1;
2'b10: y <= d2;
2'b11: y <= d3;
endcase
endmodule | module mux4 #(parameter WIDTH = 8)
(input [WIDTH-1:0] d0, d1, d2, d3,
input [1:0] s,
output reg [WIDTH-1:0] y); |
always @(*)
case(s)
2'b00: y <= d0;
2'b01: y <= d1;
2'b10: y <= d2;
2'b11: y <= d3;
endcase
endmodule | 0 |
6,406 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/MP3_Controller.v | 116,048,589 | MP3_Controller.v | v | 71 | 140 | [] | [] | [] | [(23, 70)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/MP3_Controller.v\n%Error: Exiting due to 4 error(s)\n' | 7,316 | module | module MP3_Controller(
input [5:0] Number_to_Play,
input clock,
input enable,
output reg [18:1] trigger_out
);
reg [18:1] trigger = 0;
always@(*)
begin
trigger = 18'b111111111111111111;
case(Number_to_Play)
1 : trigger[1] = 0;
2 : trigger[2] = 0;
3 : trigger[3] = 0;
4 : trigger[4] = 0;
5 : trigger[5] = 0;
6 : trigger[6] = 0;
7 : trigger[7] = 0;
8 : trigger[8] = 0;
9 : trigger[9] = 0;
10 : trigger[10] = 0;
11 : trigger[11] = 0;
12 : trigger[12] = 0;
13 : trigger[13] = 0;
14 : trigger[14] = 0;
15 : trigger[15] = 0;
16 : trigger[16] = 0;
17 : trigger[17] = 0;
18 : trigger[18] = 0;
default : trigger = 18'b111111111111111111;
endcase
end
always@(posedge clock)
begin
if(enable)
trigger_out <= trigger;
end
endmodule | module MP3_Controller(
input [5:0] Number_to_Play,
input clock,
input enable,
output reg [18:1] trigger_out
); |
reg [18:1] trigger = 0;
always@(*)
begin
trigger = 18'b111111111111111111;
case(Number_to_Play)
1 : trigger[1] = 0;
2 : trigger[2] = 0;
3 : trigger[3] = 0;
4 : trigger[4] = 0;
5 : trigger[5] = 0;
6 : trigger[6] = 0;
7 : trigger[7] = 0;
8 : trigger[8] = 0;
9 : trigger[9] = 0;
10 : trigger[10] = 0;
11 : trigger[11] = 0;
12 : trigger[12] = 0;
13 : trigger[13] = 0;
14 : trigger[14] = 0;
15 : trigger[15] = 0;
16 : trigger[16] = 0;
17 : trigger[17] = 0;
18 : trigger[18] = 0;
default : trigger = 18'b111111111111111111;
endcase
end
always@(posedge clock)
begin
if(enable)
trigger_out <= trigger;
end
endmodule | 0 |
6,407 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/Multiply.v | 116,048,589 | Multiply.v | v | 30 | 83 | [] | [] | [] | [(21, 29)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/Multiply.v\n%Error: Exiting due to 4 error(s)\n' | 7,317 | module | module Multiply(
input [15:0] Ainput,
input [15:0] Binput,
output [15:0] Result
);
assign Result = ($signed(Ainput) * $signed(Binput));
endmodule | module Multiply(
input [15:0] Ainput,
input [15:0] Binput,
output [15:0] Result
); |
assign Result = ($signed(Ainput) * $signed(Binput));
endmodule | 0 |
6,408 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mux2_4bit.v | 116,048,589 | mux2_4bit.v | v | 29 | 83 | [] | [] | [] | [(21, 27)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mux2_4bit.v\n%Error: Exiting due to 4 error(s)\n' | 7,319 | module | module mux2_4bit #(parameter WIDTH = 4)
(input [WIDTH-1:0] d0, d1,
input s,
output [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule | module mux2_4bit #(parameter WIDTH = 4)
(input [WIDTH-1:0] d0, d1,
input s,
output [WIDTH-1:0] y); |
assign y = s ? d1 : d0;
endmodule | 0 |
6,409 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mux4.v | 116,048,589 | mux4.v | v | 33 | 83 | [] | [] | [] | [(21, 33)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mux4.v\n%Error: Exiting due to 4 error(s)\n' | 7,320 | module | module mux4 #(parameter WIDTH = 16)
(input [WIDTH-1:0] d0, d1, d2, d3,
input [1:0] s,
output reg [WIDTH-1:0] y);
always @(*)
case(s)
2'b00: y <= d0;
2'b01: y <= d1;
2'b10: y <= d2;
2'b11: y <= d3;
endcase
endmodule | module mux4 #(parameter WIDTH = 16)
(input [WIDTH-1:0] d0, d1, d2, d3,
input [1:0] s,
output reg [WIDTH-1:0] y); |
always @(*)
case(s)
2'b00: y <= d0;
2'b01: y <= d1;
2'b10: y <= d2;
2'b11: y <= d3;
endcase
endmodule | 0 |
6,410 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mux8.v | 116,048,589 | mux8.v | v | 38 | 83 | [] | [] | [] | [(21, 38)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mux8.v\n%Error: Exiting due to 4 error(s)\n' | 7,321 | module | module mux8 #(parameter WIDTH = 16)
(input [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
input [2:0] s,
output reg [WIDTH-1:0] y);
always @(*)
case(s)
3'b000: y <= d0;
3'b001: y <= d1;
3'b010: y <= d2;
3'b011: y <= d3;
3'b100: y <= d4;
3'b101: y <= d5;
3'b110: y <= d6;
3'b111: y <= d7;
endcase
endmodule | module mux8 #(parameter WIDTH = 16)
(input [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
input [2:0] s,
output reg [WIDTH-1:0] y); |
always @(*)
case(s)
3'b000: y <= d0;
3'b001: y <= d1;
3'b010: y <= d2;
3'b011: y <= d3;
3'b100: y <= d4;
3'b101: y <= d5;
3'b110: y <= d6;
3'b111: y <= d7;
endcase
endmodule | 0 |
6,411 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/NESController.v | 116,048,589 | NESController.v | v | 252 | 93 | [] | [] | [] | [(29, 251)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/NESController.v\n%Error: Exiting due to 4 error(s)\n' | 7,322 | module | module NESController(
input clock,
input enable,
input data,
input reset,
output reg latch,
output reg pulse,
output reg [7:0] playerInput
);
reg a, b, start, select, up, down, left, right;
reg [19:0] count;
reg [5:0] NS, PS;
parameter IDLE = 0;
parameter LATCH = 1;
parameter PULSE_OFF0 = 2;
parameter PULSE_ON0 = 3;
parameter PULSE_OFF1 = 4;
parameter PULSE_ON1 = 5;
parameter PULSE_OFF2 = 6;
parameter PULSE_ON2 = 7;
parameter PULSE_OFF3 = 8;
parameter PULSE_ON3 = 9;
parameter PULSE_OFF4 = 10;
parameter PULSE_ON4 = 11;
parameter PULSE_OFF5 = 12;
parameter PULSE_ON5 = 13;
parameter PULSE_OFF6 = 14;
parameter PULSE_ON6 = 15;
parameter PULSE_OFF7 = 16;
always@(posedge clock) begin
if(reset)begin
count <= 0;
end
else if(enable) begin
count <= 0;
end
else begin
count <= count + 1;
end
end
always@(posedge clock) begin
if(reset)
PS <= IDLE;
else
PS <= NS;
end
always@(*) begin
NS = IDLE;
case(PS)
IDLE : NS = (enable) ? LATCH : IDLE;
LATCH : NS = (count >= 600) ? PULSE_OFF0 : LATCH;
PULSE_OFF0 : NS = (count >= 900) ? PULSE_ON0 : PULSE_OFF0;
PULSE_ON0 : NS = (count >= 1200) ? PULSE_OFF1 : PULSE_ON0;
PULSE_OFF1 : NS = (count >= 1500) ? PULSE_ON1 : PULSE_OFF1;
PULSE_ON1 : NS = (count >= 1800) ? PULSE_OFF2 : PULSE_ON1;
PULSE_OFF2 : NS = (count >= 2100) ? PULSE_ON2 : PULSE_OFF2;
PULSE_ON2 : NS = (count >= 2400) ? PULSE_OFF3 : PULSE_ON2;
PULSE_OFF3 : NS = (count >= 2700) ? PULSE_ON3 : PULSE_OFF3;
PULSE_ON3 : NS = (count >= 3000) ? PULSE_OFF4 : PULSE_ON3;
PULSE_OFF4 : NS = (count >= 3300) ? PULSE_ON4 : PULSE_OFF4;
PULSE_ON4 : NS = (count >= 3600) ? PULSE_OFF5 : PULSE_ON4;
PULSE_OFF5 : NS = (count >= 3900) ? PULSE_ON5 : PULSE_OFF5;
PULSE_ON5 : NS = (count >= 4200) ? PULSE_OFF6 : PULSE_ON5;
PULSE_OFF6 : NS = (count >= 4500) ? PULSE_ON6 : PULSE_OFF6;
PULSE_ON6 : NS = (count >= 4800) ? PULSE_OFF7 : PULSE_ON6;
PULSE_OFF7 : NS = (count >= 5100)? IDLE : PULSE_OFF7;
default : NS = IDLE;
endcase
end
always@(*) begin
latch <= 0;
pulse <= 0;
a <= 0;
b <= 0;
start <= 0;
select <= 0;
up <= 0;
down <= 0;
left <= 0;
right <= 0;
case(PS)
IDLE : begin
latch <= 0;
pulse <= 0;
end
LATCH : begin
latch <= 1;
pulse <= 0;
a <= ~data;
end
PULSE_OFF0 : begin
latch <= 0;
pulse <= 0;
a <= ~data;
end
PULSE_ON0 : begin
latch <= 0;
pulse <= 1;
b <= ~data;
end
PULSE_OFF1 : begin
latch <= 0;
pulse <= 0;
b <= ~data;
end
PULSE_ON1 : begin
latch <= 0;
pulse <= 1;
select <= ~data;
end
PULSE_OFF2 : begin
latch <= 0;
pulse <= 0;
select <= ~data;
end
PULSE_ON2 : begin
latch <= 0;
pulse <= 1;
start <= ~data;
end
PULSE_OFF3 : begin
latch <= 0;
pulse <= 0;
start <= ~data;
end
PULSE_ON3 : begin
latch <= 0;
pulse <= 1;
up <= ~data;
end
PULSE_OFF4 : begin
latch <= 0;
pulse <= 0;
up <= ~data;
end
PULSE_ON4 : begin
latch <= 0;
pulse <= 1;
down <= ~data;
end
PULSE_OFF5 : begin
latch <= 0;
pulse <= 0;
down <= ~data;
end
PULSE_ON5 : begin
latch <= 0;
pulse <= 1;
left <= ~data;
end
PULSE_OFF6 : begin
latch <= 0;
pulse <= 0;
left <= ~data;
end
PULSE_ON6 : begin
latch <= 0;
pulse <= 1;
right <= ~data;
end
PULSE_OFF7 : begin
latch <= 0;
pulse <= 0;
right <= ~data;
end
default : begin
latch <= 0;
pulse <= 0;
end
endcase
end
always@(posedge clock) begin
if(0 <= count && count < 900)
playerInput[0] = a;
if(900 <= count && count < 1500)
playerInput[1] = b;
if(1500 <= count && count < 2100)
playerInput[2] = select;
if(2100 <= count && count < 2700)
playerInput[3] = start;
if(2700 <= count && count < 3300)
playerInput[4] = up;
if(3300 <= count && count < 3900)
playerInput[5] = down;
if(3900 <= count && count < 4500)
playerInput[6] = left;
if(4500 <= count && count < 5100)
playerInput[7] = right;
end
endmodule | module NESController(
input clock,
input enable,
input data,
input reset,
output reg latch,
output reg pulse,
output reg [7:0] playerInput
); |
reg a, b, start, select, up, down, left, right;
reg [19:0] count;
reg [5:0] NS, PS;
parameter IDLE = 0;
parameter LATCH = 1;
parameter PULSE_OFF0 = 2;
parameter PULSE_ON0 = 3;
parameter PULSE_OFF1 = 4;
parameter PULSE_ON1 = 5;
parameter PULSE_OFF2 = 6;
parameter PULSE_ON2 = 7;
parameter PULSE_OFF3 = 8;
parameter PULSE_ON3 = 9;
parameter PULSE_OFF4 = 10;
parameter PULSE_ON4 = 11;
parameter PULSE_OFF5 = 12;
parameter PULSE_ON5 = 13;
parameter PULSE_OFF6 = 14;
parameter PULSE_ON6 = 15;
parameter PULSE_OFF7 = 16;
always@(posedge clock) begin
if(reset)begin
count <= 0;
end
else if(enable) begin
count <= 0;
end
else begin
count <= count + 1;
end
end
always@(posedge clock) begin
if(reset)
PS <= IDLE;
else
PS <= NS;
end
always@(*) begin
NS = IDLE;
case(PS)
IDLE : NS = (enable) ? LATCH : IDLE;
LATCH : NS = (count >= 600) ? PULSE_OFF0 : LATCH;
PULSE_OFF0 : NS = (count >= 900) ? PULSE_ON0 : PULSE_OFF0;
PULSE_ON0 : NS = (count >= 1200) ? PULSE_OFF1 : PULSE_ON0;
PULSE_OFF1 : NS = (count >= 1500) ? PULSE_ON1 : PULSE_OFF1;
PULSE_ON1 : NS = (count >= 1800) ? PULSE_OFF2 : PULSE_ON1;
PULSE_OFF2 : NS = (count >= 2100) ? PULSE_ON2 : PULSE_OFF2;
PULSE_ON2 : NS = (count >= 2400) ? PULSE_OFF3 : PULSE_ON2;
PULSE_OFF3 : NS = (count >= 2700) ? PULSE_ON3 : PULSE_OFF3;
PULSE_ON3 : NS = (count >= 3000) ? PULSE_OFF4 : PULSE_ON3;
PULSE_OFF4 : NS = (count >= 3300) ? PULSE_ON4 : PULSE_OFF4;
PULSE_ON4 : NS = (count >= 3600) ? PULSE_OFF5 : PULSE_ON4;
PULSE_OFF5 : NS = (count >= 3900) ? PULSE_ON5 : PULSE_OFF5;
PULSE_ON5 : NS = (count >= 4200) ? PULSE_OFF6 : PULSE_ON5;
PULSE_OFF6 : NS = (count >= 4500) ? PULSE_ON6 : PULSE_OFF6;
PULSE_ON6 : NS = (count >= 4800) ? PULSE_OFF7 : PULSE_ON6;
PULSE_OFF7 : NS = (count >= 5100)? IDLE : PULSE_OFF7;
default : NS = IDLE;
endcase
end
always@(*) begin
latch <= 0;
pulse <= 0;
a <= 0;
b <= 0;
start <= 0;
select <= 0;
up <= 0;
down <= 0;
left <= 0;
right <= 0;
case(PS)
IDLE : begin
latch <= 0;
pulse <= 0;
end
LATCH : begin
latch <= 1;
pulse <= 0;
a <= ~data;
end
PULSE_OFF0 : begin
latch <= 0;
pulse <= 0;
a <= ~data;
end
PULSE_ON0 : begin
latch <= 0;
pulse <= 1;
b <= ~data;
end
PULSE_OFF1 : begin
latch <= 0;
pulse <= 0;
b <= ~data;
end
PULSE_ON1 : begin
latch <= 0;
pulse <= 1;
select <= ~data;
end
PULSE_OFF2 : begin
latch <= 0;
pulse <= 0;
select <= ~data;
end
PULSE_ON2 : begin
latch <= 0;
pulse <= 1;
start <= ~data;
end
PULSE_OFF3 : begin
latch <= 0;
pulse <= 0;
start <= ~data;
end
PULSE_ON3 : begin
latch <= 0;
pulse <= 1;
up <= ~data;
end
PULSE_OFF4 : begin
latch <= 0;
pulse <= 0;
up <= ~data;
end
PULSE_ON4 : begin
latch <= 0;
pulse <= 1;
down <= ~data;
end
PULSE_OFF5 : begin
latch <= 0;
pulse <= 0;
down <= ~data;
end
PULSE_ON5 : begin
latch <= 0;
pulse <= 1;
left <= ~data;
end
PULSE_OFF6 : begin
latch <= 0;
pulse <= 0;
left <= ~data;
end
PULSE_ON6 : begin
latch <= 0;
pulse <= 1;
right <= ~data;
end
PULSE_OFF7 : begin
latch <= 0;
pulse <= 0;
right <= ~data;
end
default : begin
latch <= 0;
pulse <= 0;
end
endcase
end
always@(posedge clock) begin
if(0 <= count && count < 900)
playerInput[0] = a;
if(900 <= count && count < 1500)
playerInput[1] = b;
if(1500 <= count && count < 2100)
playerInput[2] = select;
if(2100 <= count && count < 2700)
playerInput[3] = start;
if(2700 <= count && count < 3300)
playerInput[4] = up;
if(3300 <= count && count < 3900)
playerInput[5] = down;
if(3900 <= count && count < 4500)
playerInput[6] = left;
if(4500 <= count && count < 5100)
playerInput[7] = right;
end
endmodule | 0 |
6,412 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/NESControllerControllerTester.v | 116,048,589 | NESControllerControllerTester.v | v | 42 | 114 | [] | [] | [] | [(5, 41)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/NESControllerControllerTester.v\n%Error: Exiting due to 4 error(s)\n' | 7,323 | module | module NES_To_LED_NES_To_LED_sch_tb();
reg clock;
reg reset;
reg From_Controller;
wire latch;
wire pulse;
wire [7:0] Buttons;
NES_To_LED UUT (
.clock(clock),
.latch(latch),
.pulse(pulse),
.Buttons(Buttons),
.reset(reset),
.From_Controller(From_Controller)
);
always #10 clock = ~clock;
initial begin
clock = 0;
reset = 1;
From_Controller = 0;
#20;
reset = 0;
end
endmodule | module NES_To_LED_NES_To_LED_sch_tb(); |
reg clock;
reg reset;
reg From_Controller;
wire latch;
wire pulse;
wire [7:0] Buttons;
NES_To_LED UUT (
.clock(clock),
.latch(latch),
.pulse(pulse),
.Buttons(Buttons),
.reset(reset),
.From_Controller(From_Controller)
);
always #10 clock = ~clock;
initial begin
clock = 0;
reset = 1;
From_Controller = 0;
#20;
reset = 0;
end
endmodule | 0 |
6,413 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/NES_to_LED_TF.v | 116,048,589 | NES_to_LED_TF.v | v | 41 | 142 | [] | [] | [] | [(5, 39)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/NES_to_LED_TF.v\n%Error: Exiting due to 4 error(s)\n' | 7,324 | module | module NES_To_LED_NES_To_LED_sch_tb();
reg clock;
reg reset;
reg data;
wire latch;
wire pulse;
wire [7:0] LED;
NES_To_LED UUT (
.clock(clock),
.latch(latch),
.pulse(pulse),
.LED(LED),
.reset(reset),
.data(data)
);
initial begin
#10 clock = 0;
#10 reset = 0;
#10 reset = 1;
#10 reset = 0;
#10 data = 1;
#100 data = 0;
end
always#2 clock = ~clock;
endmodule | module NES_To_LED_NES_To_LED_sch_tb(); |
reg clock;
reg reset;
reg data;
wire latch;
wire pulse;
wire [7:0] LED;
NES_To_LED UUT (
.clock(clock),
.latch(latch),
.pulse(pulse),
.LED(LED),
.reset(reset),
.data(data)
);
initial begin
#10 clock = 0;
#10 reset = 0;
#10 reset = 1;
#10 reset = 0;
#10 data = 1;
#100 data = 0;
end
always#2 clock = ~clock;
endmodule | 0 |
6,414 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/PCRegister.v | 116,048,589 | PCRegister.v | v | 38 | 83 | [] | [] | [] | [(21, 38)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/PCRegister.v\n%Error: Exiting due to 4 error(s)\n' | 7,325 | module | module PCRegister(
input [15:0] PCin,
input PCWrite,
input Clk,
input Reset,
output reg [15:0] PCout
);
always@(posedge Clk) begin
if (Reset)
PCout <= 0;
else if (PCWrite)
PCout <= PCin;
end
endmodule | module PCRegister(
input [15:0] PCin,
input PCWrite,
input Clk,
input Reset,
output reg [15:0] PCout
); |
always@(posedge Clk) begin
if (Reset)
PCout <= 0;
else if (PCWrite)
PCout <= PCin;
end
endmodule | 0 |
6,415 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/PmodSSDcontroller.v | 116,048,589 | PmodSSDcontroller.v | v | 101 | 83 | [] | [] | [] | [(21, 100)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/PmodSSDcontroller.v\n%Error: Exiting due to 4 error(s)\n' | 7,326 | module | module PmodSSDcontroller(
input clk,
input reset,
input [7:0] value,
output reg [6:0] hex,
output cat
);
reg [16:0] counter;
wire slowclock;
parameter zero = 7'b1111110;
parameter one = 7'b0000110;
parameter two = 7'b1101101;
parameter three = 7'b1001111;
parameter four = 7'b0010111;
parameter five = 7'b1011011;
parameter six = 7'b1111011;
parameter seven = 7'b0001110;
parameter eight = 7'b1111111;
parameter nine = 7'b0011111;
parameter A = 7'b0111111;
parameter b = 7'b1110011;
parameter c = 7'b1100001;
parameter d = 7'b1100111;
parameter E = 7'b1111001;
parameter F = 7'b0111001;
assign slowclock = counter[16];
assign cat = slowclock;
always@(posedge clk) begin
if (reset) counter <= 0;
else counter <= counter + 1;
end
always@(posedge slowclock, negedge slowclock) begin
if (slowclock) begin
case(value[3:0])
4'b0000: hex = zero;
4'b0001: hex = one;
4'b0010: hex = two;
4'b0011: hex = three;
4'b0100: hex = four;
4'b0101: hex = five;
4'b0110: hex = six;
4'b0111: hex = seven;
4'b1000: hex = eight;
4'b1001: hex = nine;
4'b1010: hex = A;
4'b1011: hex = b;
4'b1100: hex = c;
4'b1101: hex = d;
4'b1110: hex = E;
4'b1111: hex = F;
endcase
end
else begin
case(value[7:4])
4'b0000: hex = zero;
4'b0001: hex = one;
4'b0010: hex = two;
4'b0011: hex = three;
4'b0100: hex = four;
4'b0101: hex = five;
4'b0110: hex = six;
4'b0111: hex = seven;
4'b1000: hex = eight;
4'b1001: hex = nine;
4'b1010: hex = A;
4'b1011: hex = b;
4'b1100: hex = c;
4'b1101: hex = d;
4'b1110: hex = E;
4'b1111: hex = F;
endcase
end
end
endmodule | module PmodSSDcontroller(
input clk,
input reset,
input [7:0] value,
output reg [6:0] hex,
output cat
); |
reg [16:0] counter;
wire slowclock;
parameter zero = 7'b1111110;
parameter one = 7'b0000110;
parameter two = 7'b1101101;
parameter three = 7'b1001111;
parameter four = 7'b0010111;
parameter five = 7'b1011011;
parameter six = 7'b1111011;
parameter seven = 7'b0001110;
parameter eight = 7'b1111111;
parameter nine = 7'b0011111;
parameter A = 7'b0111111;
parameter b = 7'b1110011;
parameter c = 7'b1100001;
parameter d = 7'b1100111;
parameter E = 7'b1111001;
parameter F = 7'b0111001;
assign slowclock = counter[16];
assign cat = slowclock;
always@(posedge clk) begin
if (reset) counter <= 0;
else counter <= counter + 1;
end
always@(posedge slowclock, negedge slowclock) begin
if (slowclock) begin
case(value[3:0])
4'b0000: hex = zero;
4'b0001: hex = one;
4'b0010: hex = two;
4'b0011: hex = three;
4'b0100: hex = four;
4'b0101: hex = five;
4'b0110: hex = six;
4'b0111: hex = seven;
4'b1000: hex = eight;
4'b1001: hex = nine;
4'b1010: hex = A;
4'b1011: hex = b;
4'b1100: hex = c;
4'b1101: hex = d;
4'b1110: hex = E;
4'b1111: hex = F;
endcase
end
else begin
case(value[7:4])
4'b0000: hex = zero;
4'b0001: hex = one;
4'b0010: hex = two;
4'b0011: hex = three;
4'b0100: hex = four;
4'b0101: hex = five;
4'b0110: hex = six;
4'b0111: hex = seven;
4'b1000: hex = eight;
4'b1001: hex = nine;
4'b1010: hex = A;
4'b1011: hex = b;
4'b1100: hex = c;
4'b1101: hex = d;
4'b1110: hex = E;
4'b1111: hex = F;
endcase
end
end
endmodule | 0 |
6,416 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/ProcessorTestFixture.v | 116,048,589 | ProcessorTestFixture.v | v | 45 | 108 | [] | [] | [] | [(5, 44)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/ProcessorTestFixture.v\n%Error: Exiting due to 4 error(s)\n' | 7,327 | module | module Processor_Processor_sch_tb();
reg Clk;
reg Reset;
reg [15:0] ALUAinput3;
wire C;
wire L;
wire F;
wire Z;
wire N;
Processor UUT (
.C(C),
.L(L),
.F(F),
.Z(Z),
.N(N),
.Clk(Clk),
.Reset(Reset),
.ALUAinput3(ALUAinput3)
);
initial begin
Clk = 0;
ALUAinput3 = 0;
Reset = 1;
#50;
Reset = 0;
end
always #10 Clk = ~Clk;
endmodule | module Processor_Processor_sch_tb(); |
reg Clk;
reg Reset;
reg [15:0] ALUAinput3;
wire C;
wire L;
wire F;
wire Z;
wire N;
Processor UUT (
.C(C),
.L(L),
.F(F),
.Z(Z),
.N(N),
.Clk(Clk),
.Reset(Reset),
.ALUAinput3(ALUAinput3)
);
initial begin
Clk = 0;
ALUAinput3 = 0;
Reset = 1;
#50;
Reset = 0;
end
always #10 Clk = ~Clk;
endmodule | 0 |
6,417 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/PSR.v | 116,048,589 | PSR.v | v | 49 | 83 | [] | [] | [] | [(21, 48)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/PSR.v\n%Error: Exiting due to 4 error(s)\n' | 7,328 | module | module PSR(
input SetC,
input SetL,
input SetF,
input SetZ,
input SetN,
input [4:0] CLFZN,
output reg [4:0] PState_CLFZN,
input clk,
input reset
);
always@(posedge clk)
if (reset) PState_CLFZN <= 0;
else begin
if (SetC)
PState_CLFZN[4] <= CLFZN[4];
if (SetL)
PState_CLFZN[3] <= CLFZN[3];
if (SetF)
PState_CLFZN[2] <= CLFZN[2];
if (SetZ)
PState_CLFZN[1] <= CLFZN[1];
if (SetN)
PState_CLFZN[0] <= CLFZN[0];
end
endmodule | module PSR(
input SetC,
input SetL,
input SetF,
input SetZ,
input SetN,
input [4:0] CLFZN,
output reg [4:0] PState_CLFZN,
input clk,
input reset
); |
always@(posedge clk)
if (reset) PState_CLFZN <= 0;
else begin
if (SetC)
PState_CLFZN[4] <= CLFZN[4];
if (SetL)
PState_CLFZN[3] <= CLFZN[3];
if (SetF)
PState_CLFZN[2] <= CLFZN[2];
if (SetZ)
PState_CLFZN[1] <= CLFZN[1];
if (SetN)
PState_CLFZN[0] <= CLFZN[0];
end
endmodule | 0 |
6,418 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/regFile.v | 116,048,589 | regFile.v | v | 42 | 83 | [] | [] | [] | [(21, 41)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/regFile.v\n%Error: Exiting due to 4 error(s)\n' | 7,329 | module | module regfile #(parameter WIDTH = 16, REGBITS = 4)
(input clk,
input regwrite,
input [REGBITS-1:0] ra1, ra2, wa,
input [WIDTH-1:0] wd,
output [WIDTH-1:0] rd1, rd2);
reg [WIDTH-1:0] RAM [(1<<REGBITS)-1:0];
always @(posedge clk)
if (regwrite) RAM[wa] <= wd;
assign rd1 = RAM[ra1];
assign rd2 = RAM[ra2];
endmodule | module regfile #(parameter WIDTH = 16, REGBITS = 4)
(input clk,
input regwrite,
input [REGBITS-1:0] ra1, ra2, wa,
input [WIDTH-1:0] wd,
output [WIDTH-1:0] rd1, rd2); |
reg [WIDTH-1:0] RAM [(1<<REGBITS)-1:0];
always @(posedge clk)
if (regwrite) RAM[wa] <= wd;
assign rd1 = RAM[ra1];
assign rd2 = RAM[ra2];
endmodule | 0 |
6,419 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/ShiftLeft8.v | 116,048,589 | ShiftLeft8.v | v | 29 | 83 | [] | [] | [] | [(21, 28)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/ShiftLeft8.v\n%Error: Exiting due to 4 error(s)\n' | 7,330 | module | module ShiftLeft8(
input [7:0] inData,
output [15:0] outData
);
assign outData = {{inData[7:0]},{8{1'b0}}};
endmodule | module ShiftLeft8(
input [7:0] inData,
output [15:0] outData
); |
assign outData = {{inData[7:0]},{8{1'b0}}};
endmodule | 0 |
6,420 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/SignExtender.v | 116,048,589 | SignExtender.v | v | 30 | 83 | [] | [] | [] | [(21, 29)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/SignExtender.v\n%Error: Exiting due to 4 error(s)\n' | 7,331 | module | module SignExtender(
input [7:0] inData,
input SignExtend,
output [15:0] outData
);
assign outData = { {8{inData[7] & SignExtend}} , inData };
endmodule | module SignExtender(
input [7:0] inData,
input SignExtend,
output [15:0] outData
); |
assign outData = { {8{inData[7] & SignExtend}} , inData };
endmodule | 0 |
6,421 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/ValGen.v | 116,048,589 | ValGen.v | v | 44 | 83 | [] | [] | [] | [(21, 43)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/ValGen.v\n%Error: Exiting due to 4 error(s)\n' | 7,332 | module | module ValGen(
input clk,
input reset,
output [15:0] value,
output [15:0] command
);
reg [11:0] cnt;
reg [4:0] clkCnt;
assign tick = (clkCnt == 31);
assign value = {{4{0}},cnt};
assign command = 16'b0000110000000000;
always@(posedge clk)
if (reset) cnt = 0;
else if (tick) cnt = cnt + 1;
always@(posedge clk)
if (reset) clkCnt = 0;
else clkCnt = clkCnt +1;
endmodule | module ValGen(
input clk,
input reset,
output [15:0] value,
output [15:0] command
); |
reg [11:0] cnt;
reg [4:0] clkCnt;
assign tick = (clkCnt == 31);
assign value = {{4{0}},cnt};
assign command = 16'b0000110000000000;
always@(posedge clk)
if (reset) cnt = 0;
else if (tick) cnt = cnt + 1;
always@(posedge clk)
if (reset) clkCnt = 0;
else clkCnt = clkCnt +1;
endmodule | 0 |
6,422 | data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/vgaControl.v | 116,048,589 | vgaControl.v | v | 138 | 89 | [] | [] | [] | [(30, 137)] | null | null | 1: b'%Error: Cannot find file containing module: Xilinx\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n Xilinx\n Xilinx.v\n Xilinx.sv\n obj_dir/Xilinx\n obj_dir/Xilinx.v\n obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/vgaControl.v\n%Error: Exiting due to 4 error(s)\n' | 7,333 | module | module vgaControl(
input clk, clear,
output hSync,
output vSync,
output bright,
output reg enable,
output reg [10:0] hCount, vCount
);
reg count = 0;
reg [11:0] XCount;
reg [11:0] YCount;
always@(posedge clk) begin
if(clear) begin
count <= 0;
enable <= 0;
end
else begin
if (count == 1) begin
count <= 0;
enable <= 1;
end
else begin
count <= 1;
enable <= 0;
end
end
end
always@(posedge clk) begin
if (clear) begin
XCount <= 799;
YCount <= 520;
end
else if(enable) begin
XCount <= XCount + 1;
if(XCount >= 799) begin
XCount <= 0;
YCount <= YCount + 1;
end
if(YCount >= 520 && XCount == 799)
YCount <= 0;
end
end
always@(posedge clk) begin
if(enable) begin
hCount <= 0;
if(143 <= XCount && XCount < 783)
hCount <= XCount - 143;
end
end
always@(posedge clk) begin
if(enable) begin
vCount <= 0;
if(31 <= YCount && YCount < 510)
vCount <= YCount - 31;
end
end
assign hSync = !(0 <= XCount && XCount < 96);
assign vSync = !(YCount == 0 || YCount == 1);
assign bright = (144 <= XCount && XCount < 784 && 31 <= YCount && YCount < 511);
endmodule | module vgaControl(
input clk, clear,
output hSync,
output vSync,
output bright,
output reg enable,
output reg [10:0] hCount, vCount
); |
reg count = 0;
reg [11:0] XCount;
reg [11:0] YCount;
always@(posedge clk) begin
if(clear) begin
count <= 0;
enable <= 0;
end
else begin
if (count == 1) begin
count <= 0;
enable <= 1;
end
else begin
count <= 1;
enable <= 0;
end
end
end
always@(posedge clk) begin
if (clear) begin
XCount <= 799;
YCount <= 520;
end
else if(enable) begin
XCount <= XCount + 1;
if(XCount >= 799) begin
XCount <= 0;
YCount <= YCount + 1;
end
if(YCount >= 520 && XCount == 799)
YCount <= 0;
end
end
always@(posedge clk) begin
if(enable) begin
hCount <= 0;
if(143 <= XCount && XCount < 783)
hCount <= XCount - 143;
end
end
always@(posedge clk) begin
if(enable) begin
vCount <= 0;
if(31 <= YCount && YCount < 510)
vCount <= YCount - 31;
end
end
assign hSync = !(0 <= XCount && XCount < 96);
assign vSync = !(YCount == 0 || YCount == 1);
assign bright = (144 <= XCount && XCount < 784 && 31 <= YCount && YCount < 511);
endmodule | 0 |
6,423 | data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/dac_gen_TF.v | 116,048,589 | dac_gen_TF.v | v | 65 | 81 | [] | [] | [] | [(25, 63)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/dac_gen_TF.v:46: Unsupported: Ignoring delay on this delayed statement.\nalways #2 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/dac_gen_TF.v:52: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/dac_gen_TF.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/dac_gen_TF.v:57: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/dac_gen_TF.v:38: Cannot find file containing module: \'DAC_TEST\'\n DAC_TEST uut (\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/DAC_TEST\n data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/DAC_TEST.v\n data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/DAC_TEST.sv\n DAC_TEST\n DAC_TEST.v\n DAC_TEST.sv\n obj_dir/DAC_TEST\n obj_dir/DAC_TEST.v\n obj_dir/DAC_TEST.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,334 | module | module dac_gen_TF;
reg clk;
reg count_test;
reg reset;
wire [31:0] toSPI;
wire toEnable;
wire toReset;
DAC_TEST uut (
.clk(clk),
.reset(reset),
.toSPI(toSPI),
.toEnable(toEnable),
.toReset(toReset)
);
always #2 clk = ~clk;
initial begin
clk = 0;
count_test = 0;
reset = 0;
#10;
reset = 1;
#10;
reset = 0;
#100;
end
endmodule | module dac_gen_TF; |
reg clk;
reg count_test;
reg reset;
wire [31:0] toSPI;
wire toEnable;
wire toReset;
DAC_TEST uut (
.clk(clk),
.reset(reset),
.toSPI(toSPI),
.toEnable(toEnable),
.toReset(toReset)
);
always #2 clk = ~clk;
initial begin
clk = 0;
count_test = 0;
reset = 0;
#10;
reset = 1;
#10;
reset = 0;
#100;
end
endmodule | 0 |
6,424 | data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/DAC_TEST.v | 116,048,589 | DAC_TEST.v | v | 86 | 88 | [] | [] | [] | [(22, 85)] | null | data/verilator_xmls/694d7ee2-0596-4597-8317-78b838865e18.xml | null | 7,335 | module | module DAC_TEST(
input clk,
input count_test,
input reset,
output [31:0] toSPI,
output reg toEnable,
output toReset
);
reg [1:0] PS, NS;
parameter idle = 0;
parameter sendEnable = 1;
parameter doNothing = 2;
reg [11:0] DAC_Count = 0;
always@(posedge clk)
begin
if(reset)
PS <= idle;
else
PS <= NS;
end
always@(*)
begin
NS <= idle;
case(PS)
idle : NS <= sendEnable;
sendEnable : NS <= doNothing;
doNothing : NS <= (count_test) ? idle : doNothing;
default : NS <= idle;
endcase
end
always@(*)
begin
toEnable <= 0;
case(PS)
sendEnable : toEnable <= 1;
default : toEnable <= 0;
endcase
end
always@(posedge clk)
if(count_test)
begin
DAC_Count <= DAC_Count + 1;
end
assign toSPI = {8'b11111111, 4'b0011,4'b0000,DAC_Count,4'b1111};
assign toReset = ~reset;
endmodule | module DAC_TEST(
input clk,
input count_test,
input reset,
output [31:0] toSPI,
output reg toEnable,
output toReset
); |
reg [1:0] PS, NS;
parameter idle = 0;
parameter sendEnable = 1;
parameter doNothing = 2;
reg [11:0] DAC_Count = 0;
always@(posedge clk)
begin
if(reset)
PS <= idle;
else
PS <= NS;
end
always@(*)
begin
NS <= idle;
case(PS)
idle : NS <= sendEnable;
sendEnable : NS <= doNothing;
doNothing : NS <= (count_test) ? idle : doNothing;
default : NS <= idle;
endcase
end
always@(*)
begin
toEnable <= 0;
case(PS)
sendEnable : toEnable <= 1;
default : toEnable <= 0;
endcase
end
always@(posedge clk)
if(count_test)
begin
DAC_Count <= DAC_Count + 1;
end
assign toSPI = {8'b11111111, 4'b0011,4'b0000,DAC_Count,4'b1111};
assign toReset = ~reset;
endmodule | 0 |
6,425 | data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/SPI_Master_TF.v | 116,048,589 | SPI_Master_TF.v | v | 69 | 81 | [] | [] | [] | [(25, 67)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/SPI_Master_TF.v:55: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/SPI_Master_TF.v:57: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/SPI_Master_TF.v:59: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/SPI_Master_TF.v:66: Unsupported: Ignoring delay on this delayed statement.\nalways#2 clk = ~clk; \n ^\n%Error: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/SPI_Master_TF.v:39: Cannot find file containing module: \'SPI_Master\'\n SPI_Master uut (\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/SPI_Master\n data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/SPI_Master.v\n data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/SPI_Master.sv\n SPI_Master\n SPI_Master.v\n SPI_Master.sv\n obj_dir/SPI_Master\n obj_dir/SPI_Master.v\n obj_dir/SPI_Master.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,337 | module | module SPI_Master_TF;
reg clk;
reg [31:0] ToSPI;
reg enable;
reg reset;
wire MOSI;
wire SPI_CS;
wire sClk;
SPI_Master uut (
.clk(clk),
.sClk(sClk),
.ToSPI(ToSPI),
.enable(enable),
.reset(reset),
.MOSI(MOSI),
.SPI_CS(SPI_CS)
);
initial begin
clk = 0;
ToSPI = 0;
enable = 0;
reset = 1;
#5
reset = 0;
#5;
reset = 1;
#5;
enable =1;
ToSPI = 32'b10110011100011110000111110000010;
end
always#2 clk = ~clk;
endmodule | module SPI_Master_TF; |
reg clk;
reg [31:0] ToSPI;
reg enable;
reg reset;
wire MOSI;
wire SPI_CS;
wire sClk;
SPI_Master uut (
.clk(clk),
.sClk(sClk),
.ToSPI(ToSPI),
.enable(enable),
.reset(reset),
.MOSI(MOSI),
.SPI_CS(SPI_CS)
);
initial begin
clk = 0;
ToSPI = 0;
enable = 0;
reset = 1;
#5
reset = 0;
#5;
reset = 1;
#5;
enable =1;
ToSPI = 32'b10110011100011110000111110000010;
end
always#2 clk = ~clk;
endmodule | 0 |
6,426 | data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/SPI_Master_v2.v | 116,048,589 | SPI_Master_v2.v | v | 116 | 84 | [] | [] | [] | [(6, 158)] | null | data/verilator_xmls/815a2a21-3d52-41e6-a4be-650a5ce813a9.xml | null | 7,338 | module | module SPI_Master(
input clk,
input [31:0]ToSPI,
input enable,
input reset,
output reg MOSI,
output sClk,
output reg SPI_CS
);
reg [1:0] NS = 0;
reg [1:0] PS = 0;
reg [31:0]sendOut = 0;
parameter idle = 0;
parameter latchData = 1;
parameter send = 2;
reg [5:0] count = 0;
assign sClk = ~clk;
always@(posedge clk)
begin
if(~reset)
PS <= idle;
else
PS <= NS;
end
always@(*)
begin
NS <= idle;
case(PS)
idle : NS <= (enable) ? latchData : idle;
latchData : NS <= send;
send : NS <= (count == 31) ? idle : send;
default : NS <= idle;
endcase
end
always@(posedge clk)
begin
count <= 0;
sendOut <= 0;
MOSI <= 0;
case(PS)
latchData : begin
sendOut <= ToSPI;
SPI_CS <= 0;
count <= count + 1;
MOSI <= ToSPI[31];
end
send : begin
sendOut <= sendOut << 1;
count <= count + 1;
SPI_CS <= 0;
MOSI <= sendOut[30];
end
default : begin
count <= 0;
SPI_CS <= 1;
MOSI <= 0;
end
endcase
end
endmodule | module SPI_Master(
input clk,
input [31:0]ToSPI,
input enable,
input reset,
output reg MOSI,
output sClk,
output reg SPI_CS
); |
reg [1:0] NS = 0;
reg [1:0] PS = 0;
reg [31:0]sendOut = 0;
parameter idle = 0;
parameter latchData = 1;
parameter send = 2;
reg [5:0] count = 0;
assign sClk = ~clk;
always@(posedge clk)
begin
if(~reset)
PS <= idle;
else
PS <= NS;
end
always@(*)
begin
NS <= idle;
case(PS)
idle : NS <= (enable) ? latchData : idle;
latchData : NS <= send;
send : NS <= (count == 31) ? idle : send;
default : NS <= idle;
endcase
end
always@(posedge clk)
begin
count <= 0;
sendOut <= 0;
MOSI <= 0;
case(PS)
latchData : begin
sendOut <= ToSPI;
SPI_CS <= 0;
count <= count + 1;
MOSI <= ToSPI[31];
end
send : begin
sendOut <= sendOut << 1;
count <= count + 1;
SPI_CS <= 0;
MOSI <= sendOut[30];
end
default : begin
count <= 0;
SPI_CS <= 1;
MOSI <= 0;
end
endcase
end
endmodule | 0 |
6,427 | data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/to_dac_TF.v | 116,048,589 | to_dac_TF.v | v | 44 | 123 | [] | [] | [] | [(5, 44)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/to_dac_TF.v:28: Unsupported: Ignoring delay on this delayed statement.\nalways #2 clock = ~clock;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/to_dac_TF.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/to_dac_TF.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/to_dac_TF.v:38: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/to_dac_TF.v:20: Cannot find file containing module: \'to_dac_test\'\n to_dac_test UUT (\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/to_dac_test\n data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/to_dac_test.v\n data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/to_dac_test.sv\n to_dac_test\n to_dac_test.v\n to_dac_test.sv\n obj_dir/to_dac_test\n obj_dir/to_dac_test.v\n obj_dir/to_dac_test.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,339 | module | module to_dac_test_to_dac_test_sch_tb();
reg clock;
reg reset;
wire MOSI;
wire sClk;
wire SPI_CS;
wire resetDac;
to_dac_test UUT (
.MOSI(MOSI),
.sClk(sClk),
.clock(clock),
.SPI_CS(SPI_CS),
.reset(reset),
.resetDac(resetDac)
);
always #2 clock = ~clock;
initial begin
clock = 0;
reset = 0;
#10;
reset = 1;
#10;
reset = 0;
#100;
end
endmodule | module to_dac_test_to_dac_test_sch_tb(); |
reg clock;
reg reset;
wire MOSI;
wire sClk;
wire SPI_CS;
wire resetDac;
to_dac_test UUT (
.MOSI(MOSI),
.sClk(sClk),
.clock(clock),
.SPI_CS(SPI_CS),
.reset(reset),
.resetDac(resetDac)
);
always #2 clock = ~clock;
initial begin
clock = 0;
reset = 0;
#10;
reset = 1;
#10;
reset = 0;
#100;
end
endmodule | 0 |
6,428 | data/full_repos/permissive/116168206/rtl/snes_dejitter.v | 116,168,206 | snes_dejitter.v | v | 96 | 113 | [] | ['mit license'] | [] | null | None: at end of input | data/verilator_xmls/3fbfdcba-1d6f-4e75-bed9-3e5ae3f52e87.xml | null | 7,340 | module | module snes_dejitter(
input MCLK_XTAL_i,
input MCLK_EXT_i,
input MCLK_SEL_i,
input CSYNC_i,
output MCLK_XTAL_o,
output GCLK_o,
output CSYNC_o,
output reg SC_o
);
wire mclk_ntsc = MCLK_XTAL_i;
wire mclk_ntsc_dejitter = mclk_ntsc & gclk_en;
wire mclk_pal = MCLK_EXT_i;
assign GCLK_o = MCLK_SEL_i ? mclk_pal : mclk_ntsc_dejitter;
assign CSYNC_o = MCLK_SEL_i ? CSYNC_i : csync_dejitter;
assign MCLK_XTAL_o = ~MCLK_XTAL_i;
reg [10:0] h_cnt;
reg [2:0] g_cyc;
reg csync_prev;
reg csync_dejitter;
reg gclk_en;
reg [1:0] sc_ctr;
always @(posedge mclk_ntsc) begin
if ((h_cnt >= 1024) && (csync_prev==1'b1) && (CSYNC_i==1'b0)) begin
h_cnt <= 0;
if (h_cnt == 340*4-1)
g_cyc <= 4;
else
csync_dejitter <= CSYNC_i;
end else begin
h_cnt <= h_cnt + 1'b1;
if (g_cyc > 0)
g_cyc <= g_cyc - 1'b1;
if (g_cyc <= 1)
csync_dejitter <= CSYNC_i;
end
csync_prev <= CSYNC_i;
end
always @(posedge mclk_ntsc) begin
if (sc_ctr == 2'h2) begin
sc_ctr <= 2'h0;
SC_o <= ~SC_o;
end else begin
sc_ctr <= sc_ctr + 2'h1;
end
end
`ifdef EDGE_SENSITIVE_CLKEN
always @(negedge mclk_ntsc) begin
gclk_en <= (g_cyc == 0);
end
`else
always @(*) begin
if (!mclk_ntsc)
gclk_en <= (g_cyc == 0);
end
`endif
endmodule | module snes_dejitter(
input MCLK_XTAL_i,
input MCLK_EXT_i,
input MCLK_SEL_i,
input CSYNC_i,
output MCLK_XTAL_o,
output GCLK_o,
output CSYNC_o,
output reg SC_o
); |
wire mclk_ntsc = MCLK_XTAL_i;
wire mclk_ntsc_dejitter = mclk_ntsc & gclk_en;
wire mclk_pal = MCLK_EXT_i;
assign GCLK_o = MCLK_SEL_i ? mclk_pal : mclk_ntsc_dejitter;
assign CSYNC_o = MCLK_SEL_i ? CSYNC_i : csync_dejitter;
assign MCLK_XTAL_o = ~MCLK_XTAL_i;
reg [10:0] h_cnt;
reg [2:0] g_cyc;
reg csync_prev;
reg csync_dejitter;
reg gclk_en;
reg [1:0] sc_ctr;
always @(posedge mclk_ntsc) begin
if ((h_cnt >= 1024) && (csync_prev==1'b1) && (CSYNC_i==1'b0)) begin
h_cnt <= 0;
if (h_cnt == 340*4-1)
g_cyc <= 4;
else
csync_dejitter <= CSYNC_i;
end else begin
h_cnt <= h_cnt + 1'b1;
if (g_cyc > 0)
g_cyc <= g_cyc - 1'b1;
if (g_cyc <= 1)
csync_dejitter <= CSYNC_i;
end
csync_prev <= CSYNC_i;
end
always @(posedge mclk_ntsc) begin
if (sc_ctr == 2'h2) begin
sc_ctr <= 2'h0;
SC_o <= ~SC_o;
end else begin
sc_ctr <= sc_ctr + 2'h1;
end
end
`ifdef EDGE_SENSITIVE_CLKEN
always @(negedge mclk_ntsc) begin
gclk_en <= (g_cyc == 0);
end
`else
always @(*) begin
if (!mclk_ntsc)
gclk_en <= (g_cyc == 0);
end
`endif
endmodule | 32 |
6,429 | data/full_repos/permissive/116266634/ALU.v | 116,266,634 | ALU.v | v | 62 | 100 | [] | [] | [] | [(15, 61)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/116266634/ALU.v:42: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n : ... In instance ALU\n 4\'b0111: result = (data1 < data2);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/116266634/ALU.v:43: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n : ... In instance ALU\n 4\'b0110: result = (data1 < data2);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 7,341 | module | module ALU
(
input [31:0] data1, data2,
input [3:0] ALUOp,
input [4:0] shamt,
output reg [31:0] result,
output reg zero,
output reg overflow
);
always @ (*) begin
case (ALUOp)
`ADD:
begin
result = $signed(data1) + $signed(data2);
overflow = (data1[31] && data2[31] && ~result[31]) || (~data1[31] && ~data2[31] && result[31]);
end
`ADDU: begin
result = $unsigned(data1) + $unsigned(data2);
end
`AND: result = data1 & data2;
`NOR: result = ~(data1 | data2);
`OR: result = data1 | data2;
`SLL: result = data2 << shamt;
`SRL: result = data2 >> shamt;
`SLT: result = (data1 < data2);
`SLTU: result = (data1 < data2);
`SUB: begin
result = $signed(data1) - $signed(data2);
overflow = (data1[31] && data2[31] && ~result[31]) || (~data1[31] && ~data2[31] && result[31]);
end
`SUBU: result = $unsigned(data1) - $unsigned(data2);
`SRA: result = data2 >>> shamt;
`LUI: begin
result[31:16] = data1[15:0];
result[15:0] = 16'b0000000000000000;
end
endcase
zero = (result == 32'b0) && (~overflow);
end
endmodule | module ALU
(
input [31:0] data1, data2,
input [3:0] ALUOp,
input [4:0] shamt,
output reg [31:0] result,
output reg zero,
output reg overflow
); |
always @ (*) begin
case (ALUOp)
`ADD:
begin
result = $signed(data1) + $signed(data2);
overflow = (data1[31] && data2[31] && ~result[31]) || (~data1[31] && ~data2[31] && result[31]);
end
`ADDU: begin
result = $unsigned(data1) + $unsigned(data2);
end
`AND: result = data1 & data2;
`NOR: result = ~(data1 | data2);
`OR: result = data1 | data2;
`SLL: result = data2 << shamt;
`SRL: result = data2 >> shamt;
`SLT: result = (data1 < data2);
`SLTU: result = (data1 < data2);
`SUB: begin
result = $signed(data1) - $signed(data2);
overflow = (data1[31] && data2[31] && ~result[31]) || (~data1[31] && ~data2[31] && result[31]);
end
`SUBU: result = $unsigned(data1) - $unsigned(data2);
`SRA: result = data2 >>> shamt;
`LUI: begin
result[31:16] = data1[15:0];
result[15:0] = 16'b0000000000000000;
end
endcase
zero = (result == 32'b0) && (~overflow);
end
endmodule | 1 |
6,430 | data/full_repos/permissive/116266634/ALU_testbench.v | 116,266,634 | ALU_testbench.v | v | 62 | 111 | [] | [] | [] | null | None: at end of input | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b0001; shamt = 5\'b00000; #20;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b0010; shamt = 5\'b00000; #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b0011; shamt = 5\'b00000; #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b0100; shamt = 5\'b00000; #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b0101; shamt = 5\'b00010; #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b0110; shamt = 5\'b00011; #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b0111; shamt = 5\'b00011; #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b1000; shamt = 5\'b00011; #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b1001; shamt = 5\'b00011; #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b1010; shamt = 5\'b00011; #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b1001; shamt = 5\'b00011; #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b1010; shamt = 5\'b00011; #20;\n ^\n%Error: data/full_repos/permissive/116266634/ALU_testbench.v:56: Unsupported or unknown PLI call: $monitor\n $monitor("time = %2d\\nALUOp = %4b\\nshamt = %5b\\ndata1 = %32b\\ndata2 = %32b\\nresult = %32b\\nzero = %1b\\n\\n",\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,342 | module | module ALU_testbench();
reg [31:0] data1, data2;
reg [3:0] ALUOp;
reg [4:0] shamt;
wire [31:0] result;
wire zero;
ALU opeartionresult(data1, data2, ALUOp, shamt, result, zero);
initial begin
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0001; shamt = 5'b00000; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0010; shamt = 5'b00000; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0011; shamt = 5'b00000; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0100; shamt = 5'b00000; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0101; shamt = 5'b00010; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0110; shamt = 5'b00011; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0111; shamt = 5'b00011; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1000; shamt = 5'b00011; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1001; shamt = 5'b00011; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1010; shamt = 5'b00011; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b10000001010101010101111111001101;
ALUOp = 4'b1001; shamt = 5'b00011; #20;
data1 = 32'b00000000000000111111111111110000; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1010; shamt = 5'b00011; #20;
end
initial begin
$monitor("time = %2d\nALUOp = %4b\nshamt = %5b\ndata1 = %32b\ndata2 = %32b\nresult = %32b\nzero = %1b\n\n",
$time, ALUOp, shamt, data1, data2, result, zero);
end
endmodule | module ALU_testbench(); |
reg [31:0] data1, data2;
reg [3:0] ALUOp;
reg [4:0] shamt;
wire [31:0] result;
wire zero;
ALU opeartionresult(data1, data2, ALUOp, shamt, result, zero);
initial begin
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0001; shamt = 5'b00000; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0010; shamt = 5'b00000; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0011; shamt = 5'b00000; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0100; shamt = 5'b00000; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0101; shamt = 5'b00010; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0110; shamt = 5'b00011; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0111; shamt = 5'b00011; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1000; shamt = 5'b00011; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1001; shamt = 5'b00011; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1010; shamt = 5'b00011; #20;
data1 = 32'b10000001010101010101111111001101; data2 = 32'b10000001010101010101111111001101;
ALUOp = 4'b1001; shamt = 5'b00011; #20;
data1 = 32'b00000000000000111111111111110000; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1010; shamt = 5'b00011; #20;
end
initial begin
$monitor("time = %2d\nALUOp = %4b\nshamt = %5b\ndata1 = %32b\ndata2 = %32b\nresult = %32b\nzero = %1b\n\n",
$time, ALUOp, shamt, data1, data2, result, zero);
end
endmodule | 1 |
6,431 | data/full_repos/permissive/116266634/control_unit.v | 116,266,634 | control_unit.v | v | 267 | 93 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/a873aa13-baac-405f-9d14-dbf64382e856.xml | null | 7,343 | module | module control_unit
(
input [5:0] opcode, func,
output reg branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, RegDest, jump, jal, bneq,
output reg [3:0] ALUOp
);
always @ (*) begin
if (opcode == 6'b000000) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b1;
RegDest = 1'b1;
bneq = 1'b0;
jal = 1'b0;
if (func == 6'b100000)
ALUOp = 4'b0001;
else if (func == 6'b100001)
ALUOp = 4'b0010;
else if (func == 6'b100100)
ALUOp = 4'b0011;
else if (func == 6'b001000)
ALUOp = 4'b00000;
else if (func == 6'b100111)
ALUOp = 4'b0101;
else if (func == 6'b100101)
ALUOp = 4'b0100;
else if (func == 6'b101010)
ALUOp = 4'b0111;
else if (func == 6'b101011)
ALUOp = 4'b0110;
else if (func == 6'b000000)
ALUOp = 4'b1000;
else if (func == 6'b000010)
ALUOp = 4'b1001;
else if (func == 6'b100010)
ALUOp = 4'b1010;
else if (func == 6'b100011)
ALUOp = 4'b1011;
else if (func == 6'b000011)
ALUOp = 4'b1100;
end
else if (opcode == 6'b000010) begin
jump = 1'b1;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b0;
RegDest = 1'b0;
ALUOp = 4'b0000;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b000011) begin
jump = 1'b1;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b0;
RegDest = 1'b0;
ALUOp = 4'b0000;
bneq = 1'b0;
jal = 1'b1;
end
else if (opcode == 6'b001000) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b0001;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b001001) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b0010;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b001100) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b0011;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b000100) begin
jump = 1'b0;
branch = 1'b1;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b0;
RegDest = 1'b0;
ALUOp = 4'b1010;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b000101) begin
jump = 1'b0;
branch = 1'b1;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b0;
RegDest = 1'b0;
ALUOp = 4'b1010;
bneq = 1'b1;
jal = 1'b0;
end
else if (opcode == 6'b110000) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b1001;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b001111) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b1101;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b100011) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b1;
MemtoReg = 1'b1;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b0001;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b001101) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b0100;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b001010) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b0111;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b001011) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b0110;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b101011) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b1;
ALUSrc = 1'b1;
RegWrite = 1'b0;
RegDest = 1'b0;
ALUOp = 4'b0001;
bneq = 1'b0;
jal = 1'b0;
end
end
endmodule | module control_unit
(
input [5:0] opcode, func,
output reg branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, RegDest, jump, jal, bneq,
output reg [3:0] ALUOp
); |
always @ (*) begin
if (opcode == 6'b000000) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b1;
RegDest = 1'b1;
bneq = 1'b0;
jal = 1'b0;
if (func == 6'b100000)
ALUOp = 4'b0001;
else if (func == 6'b100001)
ALUOp = 4'b0010;
else if (func == 6'b100100)
ALUOp = 4'b0011;
else if (func == 6'b001000)
ALUOp = 4'b00000;
else if (func == 6'b100111)
ALUOp = 4'b0101;
else if (func == 6'b100101)
ALUOp = 4'b0100;
else if (func == 6'b101010)
ALUOp = 4'b0111;
else if (func == 6'b101011)
ALUOp = 4'b0110;
else if (func == 6'b000000)
ALUOp = 4'b1000;
else if (func == 6'b000010)
ALUOp = 4'b1001;
else if (func == 6'b100010)
ALUOp = 4'b1010;
else if (func == 6'b100011)
ALUOp = 4'b1011;
else if (func == 6'b000011)
ALUOp = 4'b1100;
end
else if (opcode == 6'b000010) begin
jump = 1'b1;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b0;
RegDest = 1'b0;
ALUOp = 4'b0000;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b000011) begin
jump = 1'b1;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b0;
RegDest = 1'b0;
ALUOp = 4'b0000;
bneq = 1'b0;
jal = 1'b1;
end
else if (opcode == 6'b001000) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b0001;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b001001) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b0010;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b001100) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b0011;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b000100) begin
jump = 1'b0;
branch = 1'b1;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b0;
RegWrite = 1'b0;
RegDest = 1'b0;
ALUOp = 4'b1010;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b000101) begin
jump = 1'b0;
branch = 1'b1;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b0;
RegDest = 1'b0;
ALUOp = 4'b1010;
bneq = 1'b1;
jal = 1'b0;
end
else if (opcode == 6'b110000) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b1001;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b001111) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b1101;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b100011) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b1;
MemtoReg = 1'b1;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b0001;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b001101) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b0100;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b001010) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b0111;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b001011) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b0;
ALUSrc = 1'b1;
RegWrite = 1'b1;
RegDest = 1'b0;
ALUOp = 4'b0110;
bneq = 1'b0;
jal = 1'b0;
end
else if (opcode == 6'b101011) begin
jump = 1'b0;
branch = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
MemWrite = 1'b1;
ALUSrc = 1'b1;
RegWrite = 1'b0;
RegDest = 1'b0;
ALUOp = 4'b0001;
bneq = 1'b0;
jal = 1'b0;
end
end
endmodule | 1 |
6,432 | data/full_repos/permissive/116266634/mips_core.v | 116,266,634 | mips_core.v | v | 103 | 128 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/116266634/mips_core.v:99: Unsupported or unknown PLI call: $monitor\n$monitor("Instruction: %32b, opcode: %6b, PC: %32b",instruction, opcode, PC);\n^~~~~~~~\n%Error: Exiting due to 1 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,344 | module | module mips_core(clock);
input clock;
wire [31:0] instruction;
wire [31:0] write_data,read_data_1,read_data_2, writeToReg;
wire [31:0] read_data_from_memory;
wire [31:0] pcWriteAdress;
wire [4:0] write_reg, read_reg_1, read_reg_2,shamt;
wire [4:0] destReg;
wire [5:0] func;
wire [15:0] immed;
wire [25:0] address;
wire branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, RegDest, jump, jal, bneq;
wire [5:0] opcode;
wire [3:0] ALUOp;
wire [31:0] extendValue, ALUInput, ALUResult;
wire zero;
wire overflow = 1'b0;
assign opcode = instruction[31:26];
assign read_reg_1 = instruction[25:21];
assign read_reg_2 = instruction[20:16];
assign write_reg = instruction[15:11];
assign shamt = instruction[10:6];
assign func = instruction[5:0];
assign address = instruction[25:0];
assign immed = instruction[15:0];
reg[31:0] PC = 32'b0;
control_unit controlunit(opcode, func, branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, RegDest, jump, jal, bneq, ALUOp);
mips_instr_mem instructionmem(instruction, PC);
mux_for_destination_register selectDestReg(destReg, RegDest, read_reg_2, write_reg);
sign_extender_16_to_32 signextend(immed, extendValue);
mips_registers registers(read_data_1,read_data_2,writeToReg,read_reg_1,read_reg_2,destReg,RegWrite,jal,clock,PC);
mux_2_1_32bit selectALUsrc(ALUInput, ALUSrc, read_data_1, extendValue);
ALU aluresult(read_data_2, ALUInput, ALUOp, shamt, ALUResult, zero, overflow);
mips_data_mem readwritememory(read_data_from_memory, ALUResult, read_data_2, MemRead, MemWrite);
mux_2_1_32bit selectregisterwritedata(writeToReg, MemtoReg, ALUResult, read_data_from_memory);
sign_extender_26_to_32 extendjumpadress(address, pcWriteAdress);
always @(posedge clock)
begin
if (branch && zero && ~bneq)
PC = PC + extendValue + 1;
else if (jump && opcode == 6'b000000)
PC = read_data_1;
else if (jump)
PC = pcWriteAdress;
else
PC = PC+1;
end
initial begin
$monitor("Instruction: %32b, opcode: %6b, PC: %32b",instruction, opcode, PC);
end
endmodule | module mips_core(clock); |
input clock;
wire [31:0] instruction;
wire [31:0] write_data,read_data_1,read_data_2, writeToReg;
wire [31:0] read_data_from_memory;
wire [31:0] pcWriteAdress;
wire [4:0] write_reg, read_reg_1, read_reg_2,shamt;
wire [4:0] destReg;
wire [5:0] func;
wire [15:0] immed;
wire [25:0] address;
wire branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, RegDest, jump, jal, bneq;
wire [5:0] opcode;
wire [3:0] ALUOp;
wire [31:0] extendValue, ALUInput, ALUResult;
wire zero;
wire overflow = 1'b0;
assign opcode = instruction[31:26];
assign read_reg_1 = instruction[25:21];
assign read_reg_2 = instruction[20:16];
assign write_reg = instruction[15:11];
assign shamt = instruction[10:6];
assign func = instruction[5:0];
assign address = instruction[25:0];
assign immed = instruction[15:0];
reg[31:0] PC = 32'b0;
control_unit controlunit(opcode, func, branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, RegDest, jump, jal, bneq, ALUOp);
mips_instr_mem instructionmem(instruction, PC);
mux_for_destination_register selectDestReg(destReg, RegDest, read_reg_2, write_reg);
sign_extender_16_to_32 signextend(immed, extendValue);
mips_registers registers(read_data_1,read_data_2,writeToReg,read_reg_1,read_reg_2,destReg,RegWrite,jal,clock,PC);
mux_2_1_32bit selectALUsrc(ALUInput, ALUSrc, read_data_1, extendValue);
ALU aluresult(read_data_2, ALUInput, ALUOp, shamt, ALUResult, zero, overflow);
mips_data_mem readwritememory(read_data_from_memory, ALUResult, read_data_2, MemRead, MemWrite);
mux_2_1_32bit selectregisterwritedata(writeToReg, MemtoReg, ALUResult, read_data_from_memory);
sign_extender_26_to_32 extendjumpadress(address, pcWriteAdress);
always @(posedge clock)
begin
if (branch && zero && ~bneq)
PC = PC + extendValue + 1;
else if (jump && opcode == 6'b000000)
PC = read_data_1;
else if (jump)
PC = pcWriteAdress;
else
PC = PC+1;
end
initial begin
$monitor("Instruction: %32b, opcode: %6b, PC: %32b",instruction, opcode, PC);
end
endmodule | 1 |
6,434 | data/full_repos/permissive/116266634/mips_instr_mem.v | 116,266,634 | mips_instr_mem.v | v | 14 | 53 | [] | [] | [] | null | line:84: before: "integer" | data/verilator_xmls/6a8281fc-7fdf-4c1b-be44-8b96d2c42ede.xml | null | 7,346 | module | module mips_instr_mem(instruction, program_counter);
input [31:0] program_counter;
output [31:0] instruction;
reg [31:0] instr_mem [255:0];
initial begin
$readmemb(".\\instruction.mem", instr_mem);
end
assign instruction = instr_mem[program_counter];
endmodule | module mips_instr_mem(instruction, program_counter); |
input [31:0] program_counter;
output [31:0] instruction;
reg [31:0] instr_mem [255:0];
initial begin
$readmemb(".\\instruction.mem", instr_mem);
end
assign instruction = instr_mem[program_counter];
endmodule | 1 |
6,436 | data/full_repos/permissive/116266634/mips_testbench.v | 116,266,634 | mips_testbench.v | v | 23 | 60 | [] | [] | [] | null | line:13: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116266634/mips_testbench.v:10: Unsupported: Ignoring delay on this delayed statement.\n #50 clock=~clock;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116266634/mips_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n #3200 $finish;\n ^\n%Error: data/full_repos/permissive/116266634/mips_testbench.v:19: Unsupported or unknown PLI call: $writememb\n $writememb("res_registers.mem", test.registers.registers);\n ^~~~~~~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,348 | module | module mips_testbench ();
reg clock;
wire result;
mips_core test(clock);
initial clock = 0;
always
#50 clock=~clock;
initial begin
#3200 $finish;
end
always @ (*) begin
$writememb("res_registers.mem", test.registers.registers);
end
endmodule | module mips_testbench (); |
reg clock;
wire result;
mips_core test(clock);
initial clock = 0;
always
#50 clock=~clock;
initial begin
#3200 $finish;
end
always @ (*) begin
$writememb("res_registers.mem", test.registers.registers);
end
endmodule | 1 |
6,437 | data/full_repos/permissive/116266634/mip_data_mem_testnebch.v | 116,266,634 | mip_data_mem_testnebch.v | v | 40 | 153 | [] | [] | [] | [(1, 39)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116266634/mip_data_mem_testnebch.v:14: Unsupported: Ignoring delay on this delayed statement.\nmem_write = 1\'b1; #50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116266634/mip_data_mem_testnebch.v:19: Unsupported: Ignoring delay on this delayed statement.\nmem_write = 1\'b0; #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/mip_data_mem_testnebch.v:24: Unsupported: Ignoring delay on this delayed statement.\nmem_write = 1\'b1; #50\n ^\n%Error: data/full_repos/permissive/116266634/mip_data_mem_testnebch.v:35: Unsupported or unknown PLI call: $monitor\n$monitor("MEMADRESS: %32b----WRITEDATA: %32b\\nMEMREAD: %1b--MEMWRITE: %1b------READDATA: %32b\\n\\n",mem_address,write_data,mem_read,mem_write,read_data);\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,349 | module | module mip_data_mem_testnebch();
wire [31:0] read_data;
reg [31:0] mem_address, write_data;
reg mem_read, mem_write;
mips_data_mem test(read_data, mem_address, write_data, mem_read, mem_write);
initial begin
mem_address = 32'b00000000000000000000000000010101;
write_data = 32'b11111101111111111111111111111111;
mem_read = 1'b0;
mem_write = 1'b1; #50;
mem_address = 32'b00000000000000000000000000010101;
write_data = 32'b11111101111111111111111111111111;
mem_read = 1'b1;
mem_write = 1'b0; #50;
mem_address = 32'b00000000000000000000000000010101;
write_data = 32'b11111101111111111111111111111111;
mem_read = 1'b1;
mem_write = 1'b1; #50
mem_address = 32'b00000000000000000000000000010101;
write_data = 32'b11111101111111111111111111111111;
mem_read = 1'b0;
mem_write = 1'b0;
end
initial begin
$monitor("MEMADRESS: %32b----WRITEDATA: %32b\nMEMREAD: %1b--MEMWRITE: %1b------READDATA: %32b\n\n",mem_address,write_data,mem_read,mem_write,read_data);
end
endmodule | module mip_data_mem_testnebch(); |
wire [31:0] read_data;
reg [31:0] mem_address, write_data;
reg mem_read, mem_write;
mips_data_mem test(read_data, mem_address, write_data, mem_read, mem_write);
initial begin
mem_address = 32'b00000000000000000000000000010101;
write_data = 32'b11111101111111111111111111111111;
mem_read = 1'b0;
mem_write = 1'b1; #50;
mem_address = 32'b00000000000000000000000000010101;
write_data = 32'b11111101111111111111111111111111;
mem_read = 1'b1;
mem_write = 1'b0; #50;
mem_address = 32'b00000000000000000000000000010101;
write_data = 32'b11111101111111111111111111111111;
mem_read = 1'b1;
mem_write = 1'b1; #50
mem_address = 32'b00000000000000000000000000010101;
write_data = 32'b11111101111111111111111111111111;
mem_read = 1'b0;
mem_write = 1'b0;
end
initial begin
$monitor("MEMADRESS: %32b----WRITEDATA: %32b\nMEMREAD: %1b--MEMWRITE: %1b------READDATA: %32b\n\n",mem_address,write_data,mem_read,mem_write,read_data);
end
endmodule | 1 |
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