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6,008 | data/full_repos/permissive/115035459/verilog/src/lib/easypll.v | 115,035,459 | easypll.v | v | 96 | 196 | [] | [] | [] | [(10, 63), (66, 94)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/easypll.v:66: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'easypll\'\nmodule easypll #(\n ^~~~~~~\n : ... Top module \'pll_pad\'\nmodule pll_pad #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/easypll.v:76: Cannot find file containing module: \'SB_PLL40_PAD\'\n SB_PLL40_PAD #(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/SB_PLL40_PAD\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/SB_PLL40_PAD.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/SB_PLL40_PAD.sv\n SB_PLL40_PAD\n SB_PLL40_PAD.v\n SB_PLL40_PAD.sv\n obj_dir/SB_PLL40_PAD\n obj_dir/SB_PLL40_PAD.v\n obj_dir/SB_PLL40_PAD.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/easypll.v:23: Cannot find file containing module: \'SB_PLL40_CORE\'\n SB_PLL40_CORE #(\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 6,810 | module | module easypll #(
parameter DIVR=0,
parameter DIVF=63,
parameter DIVQ=3,
parameter FILTER_RANGE=1
) (
input clock_input,
input reset_active_low,
output global_clock_output,
output pll_is_locked
);
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(DIVR),
.DIVF(DIVF),
.DIVQ(DIVQ),
.FILTER_RANGE(FILTER_RANGE)
) my_pll_instance (
.REFERENCECLK(clock_input),
.PLLOUTGLOBAL(global_clock_output),
.RESETB(reset_active_low),
.LOCK(pll_is_locked)
);
endmodule | module easypll #(
parameter DIVR=0,
parameter DIVF=63,
parameter DIVQ=3,
parameter FILTER_RANGE=1
) (
input clock_input,
input reset_active_low,
output global_clock_output,
output pll_is_locked
); |
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(DIVR),
.DIVF(DIVF),
.DIVQ(DIVQ),
.FILTER_RANGE(FILTER_RANGE)
) my_pll_instance (
.REFERENCECLK(clock_input),
.PLLOUTGLOBAL(global_clock_output),
.RESETB(reset_active_low),
.LOCK(pll_is_locked)
);
endmodule | 2 |
6,009 | data/full_repos/permissive/115035459/verilog/src/lib/easypll.v | 115,035,459 | easypll.v | v | 96 | 196 | [] | [] | [] | [(10, 63), (66, 94)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/easypll.v:66: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'easypll\'\nmodule easypll #(\n ^~~~~~~\n : ... Top module \'pll_pad\'\nmodule pll_pad #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/easypll.v:76: Cannot find file containing module: \'SB_PLL40_PAD\'\n SB_PLL40_PAD #(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/SB_PLL40_PAD\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/SB_PLL40_PAD.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/SB_PLL40_PAD.sv\n SB_PLL40_PAD\n SB_PLL40_PAD.v\n SB_PLL40_PAD.sv\n obj_dir/SB_PLL40_PAD\n obj_dir/SB_PLL40_PAD.v\n obj_dir/SB_PLL40_PAD.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/easypll.v:23: Cannot find file containing module: \'SB_PLL40_CORE\'\n SB_PLL40_CORE #(\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 6,810 | module | module pll_pad #(
parameter DIVR = 4'd3,
parameter DIVF = 7'd40,
parameter DIVQ = 3'd6
) (
input clock_input_pad,
input reset,
output global_clock_output,
output pll_is_locked
);
SB_PLL40_PAD #(
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.PLLOUT_SELECT("GENCLK"),
.FDA_FEEDBACK(4'b1111),
.FDA_RELATIVE(4'b1111),
.DIVR(4'b0011),
.DIVF(7'b0101000),
.DIVQ(3'b110),
.FILTER_RANGE(3'b010)
) pll (
.PACKAGEPIN (clock_input_pad),
.PLLOUTGLOBAL (global_clock_output),
.LOCK (pll_is_locked),
.BYPASS (1'b0),
.RESETB (~reset)
);
endmodule | module pll_pad #(
parameter DIVR = 4'd3,
parameter DIVF = 7'd40,
parameter DIVQ = 3'd6
) (
input clock_input_pad,
input reset,
output global_clock_output,
output pll_is_locked
); |
SB_PLL40_PAD #(
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.PLLOUT_SELECT("GENCLK"),
.FDA_FEEDBACK(4'b1111),
.FDA_RELATIVE(4'b1111),
.DIVR(4'b0011),
.DIVF(7'b0101000),
.DIVQ(3'b110),
.FILTER_RANGE(3'b010)
) pll (
.PACKAGEPIN (clock_input_pad),
.PLLOUTGLOBAL (global_clock_output),
.LOCK (pll_is_locked),
.BYPASS (1'b0),
.RESETB (~reset)
);
endmodule | 2 |
6,010 | data/full_repos/permissive/115035459/verilog/src/lib/edge_to_pulse.v | 115,035,459 | edge_to_pulse.v | v | 27 | 89 | [] | [] | [] | null | line:10: before: "=" | data/verilator_xmls/08ee9971-e836-4154-82ab-5759bfc204c9.xml | null | 6,811 | module | module edge_to_pulse #(
parameter polarity = 1
) (
input clock,
input i,
output reg o = 0
);
reg state = 0;
always @(posedge clock) begin
o <= ~polarity;
if (i==polarity) begin
if (state!=polarity) begin
o <= polarity;
state <= polarity;
end
end else begin
state <= ~polarity;
end
end
endmodule | module edge_to_pulse #(
parameter polarity = 1
) (
input clock,
input i,
output reg o = 0
); |
reg state = 0;
always @(posedge clock) begin
o <= ~polarity;
if (i==polarity) begin
if (state!=polarity) begin
o <= polarity;
state <= polarity;
end
end else begin
state <= ~polarity;
end
end
endmodule | 2 |
6,011 | data/full_repos/permissive/115035459/verilog/src/lib/fifo.v | 115,035,459 | fifo.v | v | 277 | 144 | [] | [] | [] | null | line:304: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:6: Cannot find include file: generic.v\n`include "generic.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/generic.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/generic.v.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/generic.v.sv\n generic.v\n generic.v.v\n generic.v.sv\n obj_dir/generic.v\n obj_dir/generic.v.v\n obj_dir/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:7: Cannot find include file: RAM8.v\n`include "RAM8.v" \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:158: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:161: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:164: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d00; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:164: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d00; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:165: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d01; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:165: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d01; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:166: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d02; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:166: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d02; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:167: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d03; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:167: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d03; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:168: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d04; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:168: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d04; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:169: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d05; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:169: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d05; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:170: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d06; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:170: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d06; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:171: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d07; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:171: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d07; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:172: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:173: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d08; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:173: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d08; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:174: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d09; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:174: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d09; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:175: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d10; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:175: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d10; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:176: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d11; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:176: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d11; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:177: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d12; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:177: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d12; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:178: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d13; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:178: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d13; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:179: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d14; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:179: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d14; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:180: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d15; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:180: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d15; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:181: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:183: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d16; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:183: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d16; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:184: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:186: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d17; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:186: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d17; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:187: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:189: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:189: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:190: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:190: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:191: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:191: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:192: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:192: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:193: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:193: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:194: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:194: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:195: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:195: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:196: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:196: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:197: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:198: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:198: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:199: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:199: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:200: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:200: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:201: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:201: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:202: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:202: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:203: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:203: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:204: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:204: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:205: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:205: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:206: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:208: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:208: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:209: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:211: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d18; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:211: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d18; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:212: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d19; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:212: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d19; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:213: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d20; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:213: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d20; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:214: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d21; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:214: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d21; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:215: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:217: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:217: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:218: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:218: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:219: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:219: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:220: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:220: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:221: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:223: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d22; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:223: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d22; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:224: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d23; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:224: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d23; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d24; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d24; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:226: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d25; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:226: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d25; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:227: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d26; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:227: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d26; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:228: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d27; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:228: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d27; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:229: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d28; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:229: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d28; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:230: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d29; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:230: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d29; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:231: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:232: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d31; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:232: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d31; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:233: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d32; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:233: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d32; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:234: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d33; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:234: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d33; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:235: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d34; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:235: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d34; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:236: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d35; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:236: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d35; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:237: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d36; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:237: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d36; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:238: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d37; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:238: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d37; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:239: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d38; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:239: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d38; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:240: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:241: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d39; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:241: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d39; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:242: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d40; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:242: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d40; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:243: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d41; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:243: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d41; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:244: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d42; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:244: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d42; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:245: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:247: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:247: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:248: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:250: Unsupported: Ignoring delay on this delayed statement.\n #100; $fclose(r); $fclose(w);\n ^\n%Error: Exiting due to 2 error(s), 144 warning(s)\n' | 6,812 | module | module fifo_single_clock_using_single_bram #(
parameter DATA_WIDTH = 8,
parameter LOG2_OF_DEPTH = 4,
parameter PRIMITIVE_ADDRESS_DEPTH = 14,
parameter RAM_ADDRESS_DEPTH = PRIMITIVE_ADDRESS_DEPTH - $clog2(DATA_WIDTH),
parameter DEPTH = 1<<LOG2_OF_DEPTH
) (
input clock, reset,
output almost_full, full, full_or_almost_full,
input [DATA_WIDTH-1:0] data_in,
input write_enable,
output almost_empty, empty, empty_or_almost_empty,
input read_enable,
output [DATA_WIDTH-1:0] data_out,
output [31:0] error_count
);
reg [RAM_ADDRESS_DEPTH-1:0] write_address = 0;
reg [RAM_ADDRESS_DEPTH-1:0] read_address = 0;
localparam MIN_COUNT = 1;
localparam MAX_COUNT = MIN_COUNT + DEPTH;
reg [LOG2_OF_DEPTH:0] count = MIN_COUNT;
reg [31:0] write_error_count = 0;
reg [31:0] read_error_count = 0;
reg [31:0] other_error_count = 0;
assign error_count = { 8'd0, write_error_count[7:0], read_error_count[7:0], other_error_count[7:0] };
wire [3:0] rwef = {read_enable, write_enable, empty, full};
wire ram_write_enable = write_enable && ((~full) || (read_enable && full));
RAM_s6_primitive #(.DATA_WIDTH_A(DATA_WIDTH), .DATA_WIDTH_B(DATA_WIDTH)) mem (.reset(reset),
.write_clock(clock), .write_address(write_address), .data_in(data_in), .write_enable(ram_write_enable),
.read_clock(clock), .read_address(read_address), .read_enable(1'b1), .data_out(data_out));
always @(posedge clock) begin
if (reset) begin
write_address <= 0;
read_address <= 0;
count <= MIN_COUNT;
write_error_count <= 0;
read_error_count <= 0;
other_error_count <= 0;
end else begin
casez (rwef)
4'b100? : begin read_address <= read_address + 1'd1; count <= count - 1'd1; end
4'b101? : begin read_error_count <= read_error_count + 1'd1; end
4'b01?0 : begin write_address <= write_address + 1'd1; count <= count + 1'd1; end
4'b01?1 : begin write_error_count <= write_error_count + 1'd1; end
4'b1100 : begin write_address <= write_address + 1'd1; read_address <= read_address + 1'd1; end
4'b1110 : begin write_address <= write_address + 1'd1; count <= count + 1'd1; end
4'b1101 : begin read_address <= read_address + 1'd1; count <= count - 1'd1; end
4'b00?? : begin end
default : begin other_error_count <= other_error_count + 1'd1; end
endcase
end
end
assign full = (count == MAX_COUNT) ? 1'b1 : 1'b0;
assign empty = (count == MIN_COUNT) ? 1'b1 : 1'b0;
assign almost_full = (count == MAX_COUNT-1) ? 1'b1 : 1'b0;
assign almost_empty = (count == MIN_COUNT+1) ? 1'b1 : 1'b0;
assign full_or_almost_full = full || almost_full;
assign empty_or_almost_empty = empty || almost_empty;
endmodule | module fifo_single_clock_using_single_bram #(
parameter DATA_WIDTH = 8,
parameter LOG2_OF_DEPTH = 4,
parameter PRIMITIVE_ADDRESS_DEPTH = 14,
parameter RAM_ADDRESS_DEPTH = PRIMITIVE_ADDRESS_DEPTH - $clog2(DATA_WIDTH),
parameter DEPTH = 1<<LOG2_OF_DEPTH
) (
input clock, reset,
output almost_full, full, full_or_almost_full,
input [DATA_WIDTH-1:0] data_in,
input write_enable,
output almost_empty, empty, empty_or_almost_empty,
input read_enable,
output [DATA_WIDTH-1:0] data_out,
output [31:0] error_count
); |
reg [RAM_ADDRESS_DEPTH-1:0] write_address = 0;
reg [RAM_ADDRESS_DEPTH-1:0] read_address = 0;
localparam MIN_COUNT = 1;
localparam MAX_COUNT = MIN_COUNT + DEPTH;
reg [LOG2_OF_DEPTH:0] count = MIN_COUNT;
reg [31:0] write_error_count = 0;
reg [31:0] read_error_count = 0;
reg [31:0] other_error_count = 0;
assign error_count = { 8'd0, write_error_count[7:0], read_error_count[7:0], other_error_count[7:0] };
wire [3:0] rwef = {read_enable, write_enable, empty, full};
wire ram_write_enable = write_enable && ((~full) || (read_enable && full));
RAM_s6_primitive #(.DATA_WIDTH_A(DATA_WIDTH), .DATA_WIDTH_B(DATA_WIDTH)) mem (.reset(reset),
.write_clock(clock), .write_address(write_address), .data_in(data_in), .write_enable(ram_write_enable),
.read_clock(clock), .read_address(read_address), .read_enable(1'b1), .data_out(data_out));
always @(posedge clock) begin
if (reset) begin
write_address <= 0;
read_address <= 0;
count <= MIN_COUNT;
write_error_count <= 0;
read_error_count <= 0;
other_error_count <= 0;
end else begin
casez (rwef)
4'b100? : begin read_address <= read_address + 1'd1; count <= count - 1'd1; end
4'b101? : begin read_error_count <= read_error_count + 1'd1; end
4'b01?0 : begin write_address <= write_address + 1'd1; count <= count + 1'd1; end
4'b01?1 : begin write_error_count <= write_error_count + 1'd1; end
4'b1100 : begin write_address <= write_address + 1'd1; read_address <= read_address + 1'd1; end
4'b1110 : begin write_address <= write_address + 1'd1; count <= count + 1'd1; end
4'b1101 : begin read_address <= read_address + 1'd1; count <= count - 1'd1; end
4'b00?? : begin end
default : begin other_error_count <= other_error_count + 1'd1; end
endcase
end
end
assign full = (count == MAX_COUNT) ? 1'b1 : 1'b0;
assign empty = (count == MIN_COUNT) ? 1'b1 : 1'b0;
assign almost_full = (count == MAX_COUNT-1) ? 1'b1 : 1'b0;
assign almost_empty = (count == MIN_COUNT+1) ? 1'b1 : 1'b0;
assign full_or_almost_full = full || almost_full;
assign empty_or_almost_empty = empty || almost_empty;
endmodule | 2 |
6,012 | data/full_repos/permissive/115035459/verilog/src/lib/fifo.v | 115,035,459 | fifo.v | v | 277 | 144 | [] | [] | [] | null | line:304: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:6: Cannot find include file: generic.v\n`include "generic.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/generic.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/generic.v.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/generic.v.sv\n generic.v\n generic.v.v\n generic.v.sv\n obj_dir/generic.v\n obj_dir/generic.v.v\n obj_dir/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:7: Cannot find include file: RAM8.v\n`include "RAM8.v" \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:158: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:161: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:164: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d00; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:164: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d00; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:165: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d01; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:165: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d01; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:166: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d02; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:166: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d02; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:167: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d03; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:167: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d03; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:168: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d04; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:168: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d04; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:169: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d05; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:169: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d05; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:170: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d06; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:170: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d06; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:171: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d07; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:171: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d07; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:172: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:173: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d08; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:173: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d08; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:174: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d09; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:174: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d09; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:175: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d10; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:175: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d10; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:176: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d11; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:176: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d11; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:177: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d12; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:177: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d12; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:178: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d13; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:178: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d13; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:179: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d14; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:179: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d14; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:180: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d15; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:180: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d15; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:181: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:183: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d16; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:183: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d16; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:184: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:186: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d17; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:186: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d17; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:187: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:189: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:189: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:190: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:190: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:191: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:191: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:192: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:192: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:193: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:193: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:194: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:194: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:195: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:195: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:196: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:196: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:197: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:198: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:198: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:199: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:199: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:200: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:200: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:201: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:201: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:202: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:202: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:203: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:203: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:204: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:204: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:205: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:205: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:206: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:208: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:208: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:209: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:211: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d18; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:211: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d18; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:212: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d19; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:212: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d19; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:213: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d20; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:213: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d20; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:214: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d21; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:214: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d21; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:215: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:217: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:217: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:218: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:218: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:219: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:219: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:220: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:220: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:221: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:223: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d22; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:223: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d22; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:224: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d23; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:224: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d23; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d24; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d24; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:226: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d25; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:226: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d25; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:227: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d26; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:227: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d26; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:228: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d27; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:228: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d27; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:229: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d28; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:229: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d28; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:230: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d29; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:230: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d29; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:231: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:232: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d31; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:232: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d31; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:233: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d32; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:233: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d32; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:234: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d33; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:234: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d33; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:235: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d34; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:235: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d34; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:236: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d35; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:236: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d35; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:237: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d36; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:237: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d36; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:238: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d37; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:238: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d37; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:239: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d38; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:239: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d38; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:240: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:241: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d39; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:241: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d39; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:242: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d40; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:242: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d40; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:243: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d41; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:243: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d41; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:244: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d42; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:244: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d42; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:245: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:247: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:247: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:248: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:250: Unsupported: Ignoring delay on this delayed statement.\n #100; $fclose(r); $fclose(w);\n ^\n%Error: Exiting due to 2 error(s), 144 warning(s)\n' | 6,812 | module | module fifo_single_clock #(
parameter DATA_WIDTH = 8,
parameter LOG2_OF_DEPTH = 4,
parameter DEPTH = 1<<LOG2_OF_DEPTH
) (
input clock, reset,
output almost_full, full, full_or_almost_full,
input [DATA_WIDTH-1:0] data_in,
input write_enable,
output almost_empty, empty, empty_or_almost_empty,
input read_enable,
output [DATA_WIDTH-1:0] data_out
);
reg [LOG2_OF_DEPTH-1:0] write_address = 0;
reg [LOG2_OF_DEPTH-1:0] read_address = 0;
reg [DATA_WIDTH-1:0] mem [DEPTH-1:0];
localparam MIN_COUNT = 1;
localparam MAX_COUNT = MIN_COUNT + DEPTH;
reg [LOG2_OF_DEPTH:0] count = MIN_COUNT;
reg [31:0] write_error_count = 0;
reg [31:0] read_error_count = 0;
wire [3:0] rwef = {read_enable, write_enable, empty, full};
always @(posedge clock) begin
if (reset) begin
write_address <= 0;
read_address <= 0;
count <= MIN_COUNT;
write_error_count <= 0;
read_error_count <= 0;
end else begin
casez (rwef)
4'b100? : begin read_address <= read_address + 1'd1; count <= count - 1'd1; end
4'b101? : begin end
4'b01?0 : begin mem[write_address] <= data_in; write_address <= write_address + 1'd1; count <= count + 1'd1; end
4'b01?1 : begin end
4'b1100 : begin mem[write_address] <= data_in; write_address <= write_address + 1'd1; read_address <= read_address + 1'd1; end
4'b1110 : begin mem[write_address] <= data_in; write_address <= write_address + 1'd1; count <= count + 1'd1; end
4'b1101 : begin read_address <= read_address + 1'd1; count <= count - 1'd1; end
default : begin end
endcase
end
end
assign data_out = mem[read_address];
assign full = (count == MAX_COUNT) ? 1'b1 : 1'b0;
assign empty = (count == MIN_COUNT) ? 1'b1 : 1'b0;
assign almost_full = (count == MAX_COUNT-1) ? 1'b1 : 1'b0;
assign almost_empty = (count == MIN_COUNT+1) ? 1'b1 : 1'b0;
assign full_or_almost_full = full || almost_full;
assign empty_or_almost_empty = empty || almost_empty;
endmodule | module fifo_single_clock #(
parameter DATA_WIDTH = 8,
parameter LOG2_OF_DEPTH = 4,
parameter DEPTH = 1<<LOG2_OF_DEPTH
) (
input clock, reset,
output almost_full, full, full_or_almost_full,
input [DATA_WIDTH-1:0] data_in,
input write_enable,
output almost_empty, empty, empty_or_almost_empty,
input read_enable,
output [DATA_WIDTH-1:0] data_out
); |
reg [LOG2_OF_DEPTH-1:0] write_address = 0;
reg [LOG2_OF_DEPTH-1:0] read_address = 0;
reg [DATA_WIDTH-1:0] mem [DEPTH-1:0];
localparam MIN_COUNT = 1;
localparam MAX_COUNT = MIN_COUNT + DEPTH;
reg [LOG2_OF_DEPTH:0] count = MIN_COUNT;
reg [31:0] write_error_count = 0;
reg [31:0] read_error_count = 0;
wire [3:0] rwef = {read_enable, write_enable, empty, full};
always @(posedge clock) begin
if (reset) begin
write_address <= 0;
read_address <= 0;
count <= MIN_COUNT;
write_error_count <= 0;
read_error_count <= 0;
end else begin
casez (rwef)
4'b100? : begin read_address <= read_address + 1'd1; count <= count - 1'd1; end
4'b101? : begin end
4'b01?0 : begin mem[write_address] <= data_in; write_address <= write_address + 1'd1; count <= count + 1'd1; end
4'b01?1 : begin end
4'b1100 : begin mem[write_address] <= data_in; write_address <= write_address + 1'd1; read_address <= read_address + 1'd1; end
4'b1110 : begin mem[write_address] <= data_in; write_address <= write_address + 1'd1; count <= count + 1'd1; end
4'b1101 : begin read_address <= read_address + 1'd1; count <= count - 1'd1; end
default : begin end
endcase
end
end
assign data_out = mem[read_address];
assign full = (count == MAX_COUNT) ? 1'b1 : 1'b0;
assign empty = (count == MIN_COUNT) ? 1'b1 : 1'b0;
assign almost_full = (count == MAX_COUNT-1) ? 1'b1 : 1'b0;
assign almost_empty = (count == MIN_COUNT+1) ? 1'b1 : 1'b0;
assign full_or_almost_full = full || almost_full;
assign empty_or_almost_empty = empty || almost_empty;
endmodule | 2 |
6,013 | data/full_repos/permissive/115035459/verilog/src/lib/fifo.v | 115,035,459 | fifo.v | v | 277 | 144 | [] | [] | [] | null | line:304: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:6: Cannot find include file: generic.v\n`include "generic.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/generic.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/generic.v.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/generic.v.sv\n generic.v\n generic.v.v\n generic.v.sv\n obj_dir/generic.v\n obj_dir/generic.v.v\n obj_dir/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:7: Cannot find include file: RAM8.v\n`include "RAM8.v" \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:158: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:161: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:164: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d00; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:164: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d00; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:165: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d01; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:165: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d01; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:166: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d02; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:166: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d02; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:167: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d03; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:167: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d03; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:168: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d04; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:168: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d04; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:169: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d05; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:169: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d05; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:170: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d06; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:170: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d06; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:171: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d07; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:171: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d07; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:172: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:173: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d08; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:173: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d08; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:174: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d09; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:174: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d09; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:175: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d10; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:175: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d10; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:176: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d11; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:176: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d11; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:177: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d12; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:177: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d12; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:178: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d13; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:178: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d13; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:179: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d14; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:179: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d14; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:180: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d15; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:180: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d15; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:181: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:183: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d16; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:183: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d16; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:184: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:186: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d17; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:186: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d17; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:187: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:189: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:189: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:190: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:190: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:191: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:191: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:192: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:192: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:193: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:193: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:194: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:194: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:195: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:195: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:196: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:196: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:197: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:198: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:198: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:199: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:199: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:200: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:200: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:201: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:201: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:202: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:202: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:203: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:203: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:204: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:204: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:205: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:205: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:206: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:208: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:208: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:209: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:211: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d18; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:211: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d18; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:212: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d19; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:212: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d19; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:213: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d20; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:213: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d20; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:214: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d21; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:214: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d21; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:215: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:217: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:217: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:218: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:218: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:219: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:219: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:220: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:220: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:221: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:223: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d22; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:223: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d22; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:224: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d23; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:224: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d23; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d24; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d24; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:226: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d25; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:226: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d25; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:227: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d26; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:227: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d26; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:228: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d27; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:228: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d27; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:229: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d28; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:229: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d28; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:230: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d29; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:230: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d29; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:231: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:232: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d31; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:232: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d31; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:233: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d32; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:233: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d32; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:234: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d33; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:234: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d33; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:235: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d34; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:235: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d34; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:236: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d35; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:236: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d35; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:237: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d36; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:237: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d36; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:238: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d37; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:238: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d37; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:239: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d38; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:239: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d38; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:240: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:241: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d39; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:241: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d39; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:242: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d40; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:242: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d40; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:243: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d41; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:243: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d41; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:244: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d42; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:244: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_data_in <= 8\'d42; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:245: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:247: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:247: Unsupported: Ignoring delay on this delayed statement.\n #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:248: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:250: Unsupported: Ignoring delay on this delayed statement.\n #100; $fclose(r); $fclose(w);\n ^\n%Error: Exiting due to 2 error(s), 144 warning(s)\n' | 6,812 | module | module fifo_single_clock_tb;
localparam DATA_WIDTH = 8;
localparam LOG2_OF_DEPTH = 4;
wire clock;
wire full;
wire empty;
wire almost_full;
wire almost_empty;
wire full_or_almost_full;
wire empty_or_almost_empty;
wire [DATA_WIDTH-1:0] data_out;
reg pre_reset = 1;
reg reset = 1;
reg [DATA_WIDTH-1:0] pre_data_in = 0;
reg [DATA_WIDTH-1:0] data_in = 0;
reg pre_write_enable = 0;
reg write_enable = 0;
reg pre_read_enable = 0;
reg read_enable = 0;
if (0) begin
fifo_single_clock #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_DEPTH(LOG2_OF_DEPTH)) fsc (.clock(clock), .reset(reset),
.data_in(data_in), .write_enable(write_enable), .full(full), .almost_full(almost_full), .full_or_almost_full(full_or_almost_full),
.data_out(data_out), .read_enable(read_enable), .empty(empty), .almost_empty(almost_empty), .empty_or_almost_empty(empty_or_almost_empty));
end else begin
fifo_single_clock_using_single_bram #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_DEPTH(LOG2_OF_DEPTH)) fsc (.clock(clock), .reset(reset),
.data_in(data_in), .write_enable(write_enable), .full(full), .almost_full(almost_full), .full_or_almost_full(full_or_almost_full),
.data_out(data_out), .read_enable(read_enable), .empty(empty), .almost_empty(almost_empty), .empty_or_almost_empty(empty_or_almost_empty));
end
integer r;
integer w;
initial begin
#40;
r = $fopen("fifo-reads", "w");
w = $fopen("fifo-writes", "w");
#40;
pre_reset <= 0;
#40; pre_data_in <= 8'd00; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd01; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd02; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd03; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd04; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd05; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd06; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd07; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40;
#40; pre_data_in <= 8'd08; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd09; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd10; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd11; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd12; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd13; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd14; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd15; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40;
#40; pre_data_in <= 8'd16; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40;
#40; pre_data_in <= 8'd17; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40;
#40; pre_data_in <= 8'd18; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd19; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd20; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd21; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40;
#40; pre_data_in <= 8'd22; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd23; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd24; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd25; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd26; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd27; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd28; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd29; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40;
#40; pre_data_in <= 8'd31; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd32; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd33; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd34; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd35; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd36; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd37; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd38; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40;
#40; pre_data_in <= 8'd39; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd40; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd41; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd42; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40;
#100; $fclose(r); $fclose(w);
end
clock #(.FREQUENCY_OF_CLOCK_HZ(250000000)) c (.clock(clock));
reg [31:0] write_counter = 0;
reg [31:0] read_counter = 0;
localparam CHECK_MEM_DEPTH = 256;
reg [DATA_WIDTH-1:0] mem [CHECK_MEM_DEPTH-1:0];
always @(posedge clock) begin
if (write_enable && ~full) begin
$display("[%4d] %d (write)", write_counter, data_in);
$fwrite(w, "%d\n", data_in);
write_counter <= write_counter + 1'd1;
end
if (read_enable && ~empty) begin
$display("[%4d] %d (read)", read_counter, data_out);
$fwrite(r, "%d\n", data_out);
read_counter <= read_counter + 1'd1;
end
data_in <= pre_data_in;
write_enable <= pre_write_enable;
read_enable <= pre_read_enable;
reset <= pre_reset;
end
endmodule | module fifo_single_clock_tb; |
localparam DATA_WIDTH = 8;
localparam LOG2_OF_DEPTH = 4;
wire clock;
wire full;
wire empty;
wire almost_full;
wire almost_empty;
wire full_or_almost_full;
wire empty_or_almost_empty;
wire [DATA_WIDTH-1:0] data_out;
reg pre_reset = 1;
reg reset = 1;
reg [DATA_WIDTH-1:0] pre_data_in = 0;
reg [DATA_WIDTH-1:0] data_in = 0;
reg pre_write_enable = 0;
reg write_enable = 0;
reg pre_read_enable = 0;
reg read_enable = 0;
if (0) begin
fifo_single_clock #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_DEPTH(LOG2_OF_DEPTH)) fsc (.clock(clock), .reset(reset),
.data_in(data_in), .write_enable(write_enable), .full(full), .almost_full(almost_full), .full_or_almost_full(full_or_almost_full),
.data_out(data_out), .read_enable(read_enable), .empty(empty), .almost_empty(almost_empty), .empty_or_almost_empty(empty_or_almost_empty));
end else begin
fifo_single_clock_using_single_bram #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_DEPTH(LOG2_OF_DEPTH)) fsc (.clock(clock), .reset(reset),
.data_in(data_in), .write_enable(write_enable), .full(full), .almost_full(almost_full), .full_or_almost_full(full_or_almost_full),
.data_out(data_out), .read_enable(read_enable), .empty(empty), .almost_empty(almost_empty), .empty_or_almost_empty(empty_or_almost_empty));
end
integer r;
integer w;
initial begin
#40;
r = $fopen("fifo-reads", "w");
w = $fopen("fifo-writes", "w");
#40;
pre_reset <= 0;
#40; pre_data_in <= 8'd00; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd01; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd02; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd03; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd04; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd05; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd06; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd07; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40;
#40; pre_data_in <= 8'd08; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd09; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd10; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd11; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd12; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd13; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd14; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd15; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40;
#40; pre_data_in <= 8'd16; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40;
#40; pre_data_in <= 8'd17; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40;
#40; pre_data_in <= 8'd18; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd19; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd20; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40; pre_data_in <= 8'd21; pre_write_enable <= 1; #4; pre_write_enable <= 0;
#40;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40;
#40; pre_data_in <= 8'd22; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd23; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd24; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd25; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd26; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd27; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd28; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd29; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40;
#40; pre_data_in <= 8'd31; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd32; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd33; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd34; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd35; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd36; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd37; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd38; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40;
#40; pre_data_in <= 8'd39; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd40; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd41; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40; pre_data_in <= 8'd42; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
#40;
#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
#40;
#100; $fclose(r); $fclose(w);
end
clock #(.FREQUENCY_OF_CLOCK_HZ(250000000)) c (.clock(clock));
reg [31:0] write_counter = 0;
reg [31:0] read_counter = 0;
localparam CHECK_MEM_DEPTH = 256;
reg [DATA_WIDTH-1:0] mem [CHECK_MEM_DEPTH-1:0];
always @(posedge clock) begin
if (write_enable && ~full) begin
$display("[%4d] %d (write)", write_counter, data_in);
$fwrite(w, "%d\n", data_in);
write_counter <= write_counter + 1'd1;
end
if (read_enable && ~empty) begin
$display("[%4d] %d (read)", read_counter, data_out);
$fwrite(r, "%d\n", data_out);
read_counter <= read_counter + 1'd1;
end
data_in <= pre_data_in;
write_enable <= pre_write_enable;
read_enable <= pre_read_enable;
reset <= pre_reset;
end
endmodule | 2 |
6,016 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module mux #(
parameter WIDTH = 1
) (
input S,
input [WIDTH-1:0] I0, I1,
output [WIDTH-1:0] O
);
assign O = S ? I1 : I0;
endmodule | module mux #(
parameter WIDTH = 1
) (
input S,
input [WIDTH-1:0] I0, I1,
output [WIDTH-1:0] O
); |
assign O = S ? I1 : I0;
endmodule | 2 |
6,017 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module mux_2to1 #(
parameter WIDTH = 1
) (
input sel,
input [WIDTH-1:0] in0, in1,
output [WIDTH-1:0] out
);
assign out = sel ? in1 : in0;
endmodule | module mux_2to1 #(
parameter WIDTH = 1
) (
input sel,
input [WIDTH-1:0] in0, in1,
output [WIDTH-1:0] out
); |
assign out = sel ? in1 : in0;
endmodule | 2 |
6,018 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module mux_4to1 #(
parameter WIDTH = 1
) (
input [WIDTH-1:0] in0, in1, in2, in3,
input [1:0] sel,
output [WIDTH-1:0] out
);
assign out =
(sel==2'd0) ? in0 :
(sel==2'd1) ? in1 :
(sel==2'd2) ? in2 :
in3 ;
endmodule | module mux_4to1 #(
parameter WIDTH = 1
) (
input [WIDTH-1:0] in0, in1, in2, in3,
input [1:0] sel,
output [WIDTH-1:0] out
); |
assign out =
(sel==2'd0) ? in0 :
(sel==2'd1) ? in1 :
(sel==2'd2) ? in2 :
in3 ;
endmodule | 2 |
6,019 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module mux_8to1 #(
parameter WIDTH = 1
) (
input [WIDTH-1:0] in0, in1, in2, in3, in4, in5, in6, in7,
input [2:0] sel,
output [WIDTH-1:0] out
);
assign out =
(sel==3'd0) ? in0 :
(sel==3'd1) ? in1 :
(sel==3'd2) ? in2 :
(sel==3'd3) ? in3 :
(sel==3'd4) ? in4 :
(sel==3'd5) ? in5 :
(sel==3'd6) ? in6 :
in7;
endmodule | module mux_8to1 #(
parameter WIDTH = 1
) (
input [WIDTH-1:0] in0, in1, in2, in3, in4, in5, in6, in7,
input [2:0] sel,
output [WIDTH-1:0] out
); |
assign out =
(sel==3'd0) ? in0 :
(sel==3'd1) ? in1 :
(sel==3'd2) ? in2 :
(sel==3'd3) ? in3 :
(sel==3'd4) ? in4 :
(sel==3'd5) ? in5 :
(sel==3'd6) ? in6 :
in7;
endmodule | 2 |
6,020 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module mux_16to1 #(
parameter WIDTH = 1
) (
input [WIDTH-1:0]
in00, in01, in02, in03, in04, in05, in06, in07,
in08, in09, in10, in11, in12, in13, in14, in15,
input [3:0] sel,
output [WIDTH-1:0] out
);
assign out =
(sel==4'd00) ? in00 :
(sel==4'd01) ? in01 :
(sel==4'd02) ? in02 :
(sel==4'd03) ? in03 :
(sel==4'd04) ? in04 :
(sel==4'd05) ? in05 :
(sel==4'd06) ? in06 :
(sel==4'd07) ? in07 :
(sel==4'd08) ? in08 :
(sel==4'd09) ? in09 :
(sel==4'd10) ? in10 :
(sel==4'd11) ? in11 :
(sel==4'd12) ? in12 :
(sel==4'd13) ? in13 :
(sel==4'd14) ? in14 :
in15;
endmodule | module mux_16to1 #(
parameter WIDTH = 1
) (
input [WIDTH-1:0]
in00, in01, in02, in03, in04, in05, in06, in07,
in08, in09, in10, in11, in12, in13, in14, in15,
input [3:0] sel,
output [WIDTH-1:0] out
); |
assign out =
(sel==4'd00) ? in00 :
(sel==4'd01) ? in01 :
(sel==4'd02) ? in02 :
(sel==4'd03) ? in03 :
(sel==4'd04) ? in04 :
(sel==4'd05) ? in05 :
(sel==4'd06) ? in06 :
(sel==4'd07) ? in07 :
(sel==4'd08) ? in08 :
(sel==4'd09) ? in09 :
(sel==4'd10) ? in10 :
(sel==4'd11) ? in11 :
(sel==4'd12) ? in12 :
(sel==4'd13) ? in13 :
(sel==4'd14) ? in14 :
in15;
endmodule | 2 |
6,021 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module mux_32to1 #(
parameter WIDTH = 1
) (
input [WIDTH-1:0]
in00, in01, in02, in03, in04, in05, in06, in07,
in08, in09, in10, in11, in12, in13, in14, in15,
in16, in17, in18, in19, in20, in21, in22, in23,
in24, in25, in26, in27, in28, in29, in30, in31,
input [4:0] sel,
output [WIDTH-1:0] out
);
assign out =
(sel==5'd00) ? in00 :
(sel==5'd01) ? in01 :
(sel==5'd02) ? in02 :
(sel==5'd03) ? in03 :
(sel==5'd04) ? in04 :
(sel==5'd05) ? in05 :
(sel==5'd06) ? in06 :
(sel==5'd07) ? in07 :
(sel==5'd08) ? in08 :
(sel==5'd09) ? in09 :
(sel==5'd10) ? in10 :
(sel==5'd11) ? in11 :
(sel==5'd12) ? in12 :
(sel==5'd13) ? in13 :
(sel==5'd14) ? in14 :
(sel==5'd15) ? in15 :
(sel==5'd16) ? in16 :
(sel==5'd17) ? in17 :
(sel==5'd18) ? in18 :
(sel==5'd19) ? in19 :
(sel==5'd20) ? in20 :
(sel==5'd21) ? in21 :
(sel==5'd22) ? in22 :
(sel==5'd23) ? in23 :
(sel==5'd24) ? in24 :
(sel==5'd25) ? in25 :
(sel==5'd26) ? in26 :
(sel==5'd27) ? in27 :
(sel==5'd28) ? in28 :
(sel==5'd29) ? in29 :
(sel==5'd30) ? in30 :
in31;
endmodule | module mux_32to1 #(
parameter WIDTH = 1
) (
input [WIDTH-1:0]
in00, in01, in02, in03, in04, in05, in06, in07,
in08, in09, in10, in11, in12, in13, in14, in15,
in16, in17, in18, in19, in20, in21, in22, in23,
in24, in25, in26, in27, in28, in29, in30, in31,
input [4:0] sel,
output [WIDTH-1:0] out
); |
assign out =
(sel==5'd00) ? in00 :
(sel==5'd01) ? in01 :
(sel==5'd02) ? in02 :
(sel==5'd03) ? in03 :
(sel==5'd04) ? in04 :
(sel==5'd05) ? in05 :
(sel==5'd06) ? in06 :
(sel==5'd07) ? in07 :
(sel==5'd08) ? in08 :
(sel==5'd09) ? in09 :
(sel==5'd10) ? in10 :
(sel==5'd11) ? in11 :
(sel==5'd12) ? in12 :
(sel==5'd13) ? in13 :
(sel==5'd14) ? in14 :
(sel==5'd15) ? in15 :
(sel==5'd16) ? in16 :
(sel==5'd17) ? in17 :
(sel==5'd18) ? in18 :
(sel==5'd19) ? in19 :
(sel==5'd20) ? in20 :
(sel==5'd21) ? in21 :
(sel==5'd22) ? in22 :
(sel==5'd23) ? in23 :
(sel==5'd24) ? in24 :
(sel==5'd25) ? in25 :
(sel==5'd26) ? in26 :
(sel==5'd27) ? in27 :
(sel==5'd28) ? in28 :
(sel==5'd29) ? in29 :
(sel==5'd30) ? in30 :
in31;
endmodule | 2 |
6,022 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module demux_1to8 #(
parameter WIDTH = 1,
parameter [WIDTH-1:0] default_value = 0
) (
input [WIDTH-1:0] in,
input [2:0] sel,
output [WIDTH-1:0] out0, out1, out2, out3, out4, out5, out6, out7
);
assign out0 = (sel==3'd0) ? in : default_value;
assign out1 = (sel==3'd1) ? in : default_value;
assign out2 = (sel==3'd2) ? in : default_value;
assign out3 = (sel==3'd3) ? in : default_value;
assign out4 = (sel==3'd4) ? in : default_value;
assign out5 = (sel==3'd5) ? in : default_value;
assign out6 = (sel==3'd6) ? in : default_value;
assign out7 = (sel==3'd7) ? in : default_value;
endmodule | module demux_1to8 #(
parameter WIDTH = 1,
parameter [WIDTH-1:0] default_value = 0
) (
input [WIDTH-1:0] in,
input [2:0] sel,
output [WIDTH-1:0] out0, out1, out2, out3, out4, out5, out6, out7
); |
assign out0 = (sel==3'd0) ? in : default_value;
assign out1 = (sel==3'd1) ? in : default_value;
assign out2 = (sel==3'd2) ? in : default_value;
assign out3 = (sel==3'd3) ? in : default_value;
assign out4 = (sel==3'd4) ? in : default_value;
assign out5 = (sel==3'd5) ? in : default_value;
assign out6 = (sel==3'd6) ? in : default_value;
assign out7 = (sel==3'd7) ? in : default_value;
endmodule | 2 |
6,023 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module mux_8to1_tb;
wire out;
reg a, b, c, d, e, f, g, h;
reg [2:0] sel = 3'd0;
initial begin
#1; sel <= 3'd0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;
#1; sel <= 3'd0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;
#1; sel <= 3'd1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;
#1; sel <= 3'd2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;
#1; sel <= 3'd3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;
#1; sel <= 3'd4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;
#1; sel <= 3'd5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;
#1; sel <= 3'd6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;
#1; sel <= 3'd7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;
#1; sel <= 3'd0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;
#1; sel <= 3'd1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;
#1; sel <= 3'd2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;
#1; sel <= 3'd3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;
#1; sel <= 3'd4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;
#1; sel <= 3'd5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;
#1; sel <= 3'd6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;
#1; sel <= 3'd7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;
end
mux_8to1 tst (.in0(a), .in1(b), .in2(c), .in3(d), .in4(e), .in5(f), .in6(g), .in7(h), .sel(sel), .out(out));
endmodule | module mux_8to1_tb; |
wire out;
reg a, b, c, d, e, f, g, h;
reg [2:0] sel = 3'd0;
initial begin
#1; sel <= 3'd0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;
#1; sel <= 3'd0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;
#1; sel <= 3'd1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;
#1; sel <= 3'd2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;
#1; sel <= 3'd3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;
#1; sel <= 3'd4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;
#1; sel <= 3'd5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;
#1; sel <= 3'd6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;
#1; sel <= 3'd7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;
#1; sel <= 3'd0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;
#1; sel <= 3'd1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;
#1; sel <= 3'd2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;
#1; sel <= 3'd3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;
#1; sel <= 3'd4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;
#1; sel <= 3'd5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;
#1; sel <= 3'd6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;
#1; sel <= 3'd7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;
end
mux_8to1 tst (.in0(a), .in1(b), .in2(c), .in3(d), .in4(e), .in5(f), .in6(g), .in7(h), .sel(sel), .out(out));
endmodule | 2 |
6,024 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module demux_1to16 #(
parameter WIDTH = 1,
parameter [WIDTH-1:0] default_value = 0
) (
input [WIDTH-1:0] in,
input [3:0] sel,
output [WIDTH-1:0]
out00, out01, out02, out03, out04, out05, out06, out07,
out08, out09, out10, out11, out12, out13, out14, out15
);
assign out00 = (sel==4'd00) ? in : default_value;
assign out01 = (sel==4'd01) ? in : default_value;
assign out02 = (sel==4'd02) ? in : default_value;
assign out03 = (sel==4'd03) ? in : default_value;
assign out04 = (sel==4'd04) ? in : default_value;
assign out05 = (sel==4'd05) ? in : default_value;
assign out06 = (sel==4'd06) ? in : default_value;
assign out07 = (sel==4'd07) ? in : default_value;
assign out08 = (sel==4'd08) ? in : default_value;
assign out09 = (sel==4'd09) ? in : default_value;
assign out10 = (sel==4'd10) ? in : default_value;
assign out11 = (sel==4'd11) ? in : default_value;
assign out12 = (sel==4'd12) ? in : default_value;
assign out13 = (sel==4'd13) ? in : default_value;
assign out14 = (sel==4'd14) ? in : default_value;
assign out15 = (sel==4'd15) ? in : default_value;
endmodule | module demux_1to16 #(
parameter WIDTH = 1,
parameter [WIDTH-1:0] default_value = 0
) (
input [WIDTH-1:0] in,
input [3:0] sel,
output [WIDTH-1:0]
out00, out01, out02, out03, out04, out05, out06, out07,
out08, out09, out10, out11, out12, out13, out14, out15
); |
assign out00 = (sel==4'd00) ? in : default_value;
assign out01 = (sel==4'd01) ? in : default_value;
assign out02 = (sel==4'd02) ? in : default_value;
assign out03 = (sel==4'd03) ? in : default_value;
assign out04 = (sel==4'd04) ? in : default_value;
assign out05 = (sel==4'd05) ? in : default_value;
assign out06 = (sel==4'd06) ? in : default_value;
assign out07 = (sel==4'd07) ? in : default_value;
assign out08 = (sel==4'd08) ? in : default_value;
assign out09 = (sel==4'd09) ? in : default_value;
assign out10 = (sel==4'd10) ? in : default_value;
assign out11 = (sel==4'd11) ? in : default_value;
assign out12 = (sel==4'd12) ? in : default_value;
assign out13 = (sel==4'd13) ? in : default_value;
assign out14 = (sel==4'd14) ? in : default_value;
assign out15 = (sel==4'd15) ? in : default_value;
endmodule | 2 |
6,025 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module demux_1to32 #(
parameter WIDTH = 1,
parameter [WIDTH-1:0] default_value = 0
) (
input [WIDTH-1:0] in,
input [4:0] sel,
output [WIDTH-1:0]
out00, out01, out02, out03, out04, out05, out06, out07,
out08, out09, out10, out11, out12, out13, out14, out15,
out16, out17, out18, out19, out20, out21, out22, out23,
out24, out25, out26, out27, out28, out29, out30, out31
);
assign out00 = (sel==5'd00) ? in : default_value;
assign out01 = (sel==5'd01) ? in : default_value;
assign out02 = (sel==5'd02) ? in : default_value;
assign out03 = (sel==5'd03) ? in : default_value;
assign out04 = (sel==5'd04) ? in : default_value;
assign out05 = (sel==5'd05) ? in : default_value;
assign out06 = (sel==5'd06) ? in : default_value;
assign out07 = (sel==5'd07) ? in : default_value;
assign out08 = (sel==5'd08) ? in : default_value;
assign out09 = (sel==5'd09) ? in : default_value;
assign out10 = (sel==5'd10) ? in : default_value;
assign out11 = (sel==5'd11) ? in : default_value;
assign out12 = (sel==5'd12) ? in : default_value;
assign out13 = (sel==5'd13) ? in : default_value;
assign out14 = (sel==5'd14) ? in : default_value;
assign out15 = (sel==5'd15) ? in : default_value;
assign out16 = (sel==5'd16) ? in : default_value;
assign out17 = (sel==5'd17) ? in : default_value;
assign out18 = (sel==5'd18) ? in : default_value;
assign out19 = (sel==5'd19) ? in : default_value;
assign out20 = (sel==5'd20) ? in : default_value;
assign out21 = (sel==5'd21) ? in : default_value;
assign out22 = (sel==5'd22) ? in : default_value;
assign out23 = (sel==5'd23) ? in : default_value;
assign out24 = (sel==5'd24) ? in : default_value;
assign out25 = (sel==5'd25) ? in : default_value;
assign out26 = (sel==5'd26) ? in : default_value;
assign out27 = (sel==5'd27) ? in : default_value;
assign out28 = (sel==5'd28) ? in : default_value;
assign out29 = (sel==5'd29) ? in : default_value;
assign out30 = (sel==5'd30) ? in : default_value;
assign out31 = (sel==5'd31) ? in : default_value;
endmodule | module demux_1to32 #(
parameter WIDTH = 1,
parameter [WIDTH-1:0] default_value = 0
) (
input [WIDTH-1:0] in,
input [4:0] sel,
output [WIDTH-1:0]
out00, out01, out02, out03, out04, out05, out06, out07,
out08, out09, out10, out11, out12, out13, out14, out15,
out16, out17, out18, out19, out20, out21, out22, out23,
out24, out25, out26, out27, out28, out29, out30, out31
); |
assign out00 = (sel==5'd00) ? in : default_value;
assign out01 = (sel==5'd01) ? in : default_value;
assign out02 = (sel==5'd02) ? in : default_value;
assign out03 = (sel==5'd03) ? in : default_value;
assign out04 = (sel==5'd04) ? in : default_value;
assign out05 = (sel==5'd05) ? in : default_value;
assign out06 = (sel==5'd06) ? in : default_value;
assign out07 = (sel==5'd07) ? in : default_value;
assign out08 = (sel==5'd08) ? in : default_value;
assign out09 = (sel==5'd09) ? in : default_value;
assign out10 = (sel==5'd10) ? in : default_value;
assign out11 = (sel==5'd11) ? in : default_value;
assign out12 = (sel==5'd12) ? in : default_value;
assign out13 = (sel==5'd13) ? in : default_value;
assign out14 = (sel==5'd14) ? in : default_value;
assign out15 = (sel==5'd15) ? in : default_value;
assign out16 = (sel==5'd16) ? in : default_value;
assign out17 = (sel==5'd17) ? in : default_value;
assign out18 = (sel==5'd18) ? in : default_value;
assign out19 = (sel==5'd19) ? in : default_value;
assign out20 = (sel==5'd20) ? in : default_value;
assign out21 = (sel==5'd21) ? in : default_value;
assign out22 = (sel==5'd22) ? in : default_value;
assign out23 = (sel==5'd23) ? in : default_value;
assign out24 = (sel==5'd24) ? in : default_value;
assign out25 = (sel==5'd25) ? in : default_value;
assign out26 = (sel==5'd26) ? in : default_value;
assign out27 = (sel==5'd27) ? in : default_value;
assign out28 = (sel==5'd28) ? in : default_value;
assign out29 = (sel==5'd29) ? in : default_value;
assign out30 = (sel==5'd30) ? in : default_value;
assign out31 = (sel==5'd31) ? in : default_value;
endmodule | 2 |
6,026 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module demux_1to8_tb;
reg [2:0] in;
wire [2:0] a, b, c, d, e, f, g, h;
reg [2:0] sel = 3'd0;
initial begin
in <= 0;
#1; sel <= 3'd0;
#1; sel <= 3'd1;
#1; sel <= 3'd2;
#1; sel <= 3'd3;
#1; sel <= 3'd4;
#1; sel <= 3'd5;
#1; sel <= 3'd6;
#1; sel <= 3'd7;
#1; sel <= 3'd7;
#1; sel <= 3'd6;
#1; sel <= 3'd5;
#1; sel <= 3'd4;
#1; sel <= 3'd3;
#1; sel <= 3'd2;
#1; sel <= 3'd1;
#1; sel <= 3'd0;
end
always begin
#1;
in <= in + 1;
end
demux_1to8 #(.WIDTH(3)) tst (
.in(in), .sel(sel),
.out0(a), .out1(b), .out2(c), .out3(d),
.out4(e), .out5(f), .out6(g), .out7(h));
endmodule | module demux_1to8_tb; |
reg [2:0] in;
wire [2:0] a, b, c, d, e, f, g, h;
reg [2:0] sel = 3'd0;
initial begin
in <= 0;
#1; sel <= 3'd0;
#1; sel <= 3'd1;
#1; sel <= 3'd2;
#1; sel <= 3'd3;
#1; sel <= 3'd4;
#1; sel <= 3'd5;
#1; sel <= 3'd6;
#1; sel <= 3'd7;
#1; sel <= 3'd7;
#1; sel <= 3'd6;
#1; sel <= 3'd5;
#1; sel <= 3'd4;
#1; sel <= 3'd3;
#1; sel <= 3'd2;
#1; sel <= 3'd1;
#1; sel <= 3'd0;
end
always begin
#1;
in <= in + 1;
end
demux_1to8 #(.WIDTH(3)) tst (
.in(in), .sel(sel),
.out0(a), .out1(b), .out2(c), .out3(d),
.out4(e), .out5(f), .out6(g), .out7(h));
endmodule | 2 |
6,027 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module and_gate #(
parameter DELAY_RISE = 0.5,
parameter DELAY_FALL = 0.5,
parameter TESTBENCH = 0
) (
input I0,
input I1,
output O
);
wire O0;
if (TESTBENCH) begin
reg O0_prev = 0;
reg O1 = 0;
always begin
case ({ O0_prev, O0 })
2'b00: begin #DELAY_RISE; O0_prev <= O0; end
2'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end
2'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end
default: begin #DELAY_RISE; O0_prev <= O0; end
endcase
end
assign O = O1;
end else begin
assign O = O0;
end
`ifdef XILINX
LUT5 #(
.INIT(32'b00000000000000000000000000001000)
) LUT5_inst (
.O(O0),
.I0(I0),
.I1(I1),
.I2(1'b0),
.I3(1'b0),
.I4(1'b0)
);
`endif
endmodule | module and_gate #(
parameter DELAY_RISE = 0.5,
parameter DELAY_FALL = 0.5,
parameter TESTBENCH = 0
) (
input I0,
input I1,
output O
); |
wire O0;
if (TESTBENCH) begin
reg O0_prev = 0;
reg O1 = 0;
always begin
case ({ O0_prev, O0 })
2'b00: begin #DELAY_RISE; O0_prev <= O0; end
2'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end
2'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end
default: begin #DELAY_RISE; O0_prev <= O0; end
endcase
end
assign O = O1;
end else begin
assign O = O0;
end
`ifdef XILINX
LUT5 #(
.INIT(32'b00000000000000000000000000001000)
) LUT5_inst (
.O(O0),
.I0(I0),
.I1(I1),
.I2(1'b0),
.I3(1'b0),
.I4(1'b0)
);
`endif
endmodule | 2 |
6,028 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module ring_oscillator #(
parameter number_of_bits_for_coarse_stages = 3,
parameter number_of_bits_for_medium_stages = 3,
parameter number_of_bits_for_fine_stages = 3,
parameter number_of_bits = number_of_bits_for_coarse_stages + number_of_bits_for_medium_stages + number_of_bits_for_fine_stages,
parameter TESTBENCH = 0
) (
input enable,
input [number_of_bits-1:0] select,
output clock_out
);
localparam number_of_coarse_stages = 2**number_of_bits_for_coarse_stages;
localparam number_of_medium_stages = 2**number_of_bits_for_medium_stages;
localparam number_of_fine_stages = 2**number_of_bits_for_fine_stages;
localparam number_of_stages = number_of_coarse_stages + number_of_medium_stages + number_of_fine_stages;
wire [number_of_stages-1:0] stage;
genvar i;
localparam COARSE_DELAY = 10.0;
localparam MEDIUM_DELAY = 2.0;
localparam FINE_DELAY = 0.5;
wire [number_of_bits_for_coarse_stages-1:0] select_coarse = select[number_of_bits-1:number_of_bits_for_medium_stages+number_of_bits_for_fine_stages];
wire [number_of_bits_for_medium_stages-1:0] select_medium = select[number_of_bits-number_of_bits_for_coarse_stages-1:number_of_bits_for_fine_stages];
wire [number_of_bits_for_fine_stages-1:0] select_fine = select[number_of_bits_for_fine_stages-1:0];
for (i=0; i<number_of_coarse_stages-1; i=i+2) begin : coarse_feedback_even
and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse (.I0(stage[i]), .I1(enable), .O(stage[i+1]));
end
for (i=1; i<number_of_coarse_stages-1; i=i+2) begin : coarse_feedback_odd
and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse (.I0(stage[i]), .I1(enable), .O(stage[i+1]));
end
and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));
wire aftercoarse = stage[number_of_coarse_stages];
for (i=number_of_coarse_stages; i<number_of_coarse_stages+number_of_medium_stages-1; i=i+2) begin : medium_feedback_even
and_gate #(.DELAY_RISE(MEDIUM_DELAY), .DELAY_FALL(MEDIUM_DELAY), .TESTBENCH(TESTBENCH)) mediumm (.I0(stage[i]), .I1(enable), .O(stage[i+1]));
end
for (i=number_of_coarse_stages+1; i<number_of_coarse_stages+number_of_medium_stages-1; i=i+2) begin : medium_feedback_odd
and_gate #(.DELAY_RISE(MEDIUM_DELAY), .DELAY_FALL(MEDIUM_DELAY), .TESTBENCH(TESTBENCH)) mediumm (.I0(stage[i]), .I1(enable), .O(stage[i+1]));
end
and_gate #(.DELAY_RISE(MEDIUM_DELAY), .DELAY_FALL(MEDIUM_DELAY), .TESTBENCH(TESTBENCH)) mediumm_bride (.I0(stage[number_of_coarse_stages+select_medium]), .I1(enable), .O(stage[number_of_coarse_stages+number_of_medium_stages]));
wire aftermedium = stage[number_of_coarse_stages+number_of_medium_stages];
for (i=number_of_coarse_stages+number_of_medium_stages; i<number_of_stages-1; i=i+2) begin : fine_feedback_even
and_gate #(.DELAY_RISE(FINE_DELAY), .DELAY_FALL(FINE_DELAY), .TESTBENCH(TESTBENCH)) fine (.I0(stage[i]), .I1(enable), .O(stage[i+1]));
end
for (i=number_of_coarse_stages+number_of_medium_stages+1; i<number_of_stages-1; i=i+2) begin : fine_feedback_odd
and_gate #(.DELAY_RISE(FINE_DELAY), .DELAY_FALL(FINE_DELAY), .TESTBENCH(TESTBENCH)) fine (.I0(stage[i]), .I1(enable), .O(stage[i+1]));
end
and_gate #(.DELAY_RISE(FINE_DELAY), .DELAY_FALL(FINE_DELAY), .TESTBENCH(TESTBENCH)) fine_bride (.I0(~stage[number_of_coarse_stages+number_of_medium_stages+select_fine]), .I1(enable), .O(stage[0]));
wire afterfine = stage[0];
assign clock_out = stage[0];
endmodule | module ring_oscillator #(
parameter number_of_bits_for_coarse_stages = 3,
parameter number_of_bits_for_medium_stages = 3,
parameter number_of_bits_for_fine_stages = 3,
parameter number_of_bits = number_of_bits_for_coarse_stages + number_of_bits_for_medium_stages + number_of_bits_for_fine_stages,
parameter TESTBENCH = 0
) (
input enable,
input [number_of_bits-1:0] select,
output clock_out
); |
localparam number_of_coarse_stages = 2**number_of_bits_for_coarse_stages;
localparam number_of_medium_stages = 2**number_of_bits_for_medium_stages;
localparam number_of_fine_stages = 2**number_of_bits_for_fine_stages;
localparam number_of_stages = number_of_coarse_stages + number_of_medium_stages + number_of_fine_stages;
wire [number_of_stages-1:0] stage;
genvar i;
localparam COARSE_DELAY = 10.0;
localparam MEDIUM_DELAY = 2.0;
localparam FINE_DELAY = 0.5;
wire [number_of_bits_for_coarse_stages-1:0] select_coarse = select[number_of_bits-1:number_of_bits_for_medium_stages+number_of_bits_for_fine_stages];
wire [number_of_bits_for_medium_stages-1:0] select_medium = select[number_of_bits-number_of_bits_for_coarse_stages-1:number_of_bits_for_fine_stages];
wire [number_of_bits_for_fine_stages-1:0] select_fine = select[number_of_bits_for_fine_stages-1:0];
for (i=0; i<number_of_coarse_stages-1; i=i+2) begin : coarse_feedback_even
and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse (.I0(stage[i]), .I1(enable), .O(stage[i+1]));
end
for (i=1; i<number_of_coarse_stages-1; i=i+2) begin : coarse_feedback_odd
and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse (.I0(stage[i]), .I1(enable), .O(stage[i+1]));
end
and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));
wire aftercoarse = stage[number_of_coarse_stages];
for (i=number_of_coarse_stages; i<number_of_coarse_stages+number_of_medium_stages-1; i=i+2) begin : medium_feedback_even
and_gate #(.DELAY_RISE(MEDIUM_DELAY), .DELAY_FALL(MEDIUM_DELAY), .TESTBENCH(TESTBENCH)) mediumm (.I0(stage[i]), .I1(enable), .O(stage[i+1]));
end
for (i=number_of_coarse_stages+1; i<number_of_coarse_stages+number_of_medium_stages-1; i=i+2) begin : medium_feedback_odd
and_gate #(.DELAY_RISE(MEDIUM_DELAY), .DELAY_FALL(MEDIUM_DELAY), .TESTBENCH(TESTBENCH)) mediumm (.I0(stage[i]), .I1(enable), .O(stage[i+1]));
end
and_gate #(.DELAY_RISE(MEDIUM_DELAY), .DELAY_FALL(MEDIUM_DELAY), .TESTBENCH(TESTBENCH)) mediumm_bride (.I0(stage[number_of_coarse_stages+select_medium]), .I1(enable), .O(stage[number_of_coarse_stages+number_of_medium_stages]));
wire aftermedium = stage[number_of_coarse_stages+number_of_medium_stages];
for (i=number_of_coarse_stages+number_of_medium_stages; i<number_of_stages-1; i=i+2) begin : fine_feedback_even
and_gate #(.DELAY_RISE(FINE_DELAY), .DELAY_FALL(FINE_DELAY), .TESTBENCH(TESTBENCH)) fine (.I0(stage[i]), .I1(enable), .O(stage[i+1]));
end
for (i=number_of_coarse_stages+number_of_medium_stages+1; i<number_of_stages-1; i=i+2) begin : fine_feedback_odd
and_gate #(.DELAY_RISE(FINE_DELAY), .DELAY_FALL(FINE_DELAY), .TESTBENCH(TESTBENCH)) fine (.I0(stage[i]), .I1(enable), .O(stage[i+1]));
end
and_gate #(.DELAY_RISE(FINE_DELAY), .DELAY_FALL(FINE_DELAY), .TESTBENCH(TESTBENCH)) fine_bride (.I0(~stage[number_of_coarse_stages+number_of_medium_stages+select_fine]), .I1(enable), .O(stage[0]));
wire afterfine = stage[0];
assign clock_out = stage[0];
endmodule | 2 |
6,029 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module ring_oscillator_tb;
wire clock;
reg enable = 0;
reg [3:0] select_coarse = 4'd0;
reg [1:0] select_medium = 2'd0;
reg [1:0] select_fine = 2'd0;
wire [7:0] select = { select_coarse, select_medium, select_fine };
ring_oscillator #(.number_of_bits_for_coarse_stages(4), .number_of_bits_for_medium_stages(2), .number_of_bits_for_fine_stages(2), .TESTBENCH(1)) ro (.enable(enable), .select(select), .clock_out(clock));
initial begin
#20;
enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd00; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd01; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd02; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd03; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd04; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd05; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd06; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd07; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd08; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd09; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd10; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd11; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd12; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd13; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd14; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd15; #100; enable <= 1;
#4000;
#2000; enable <= 0; select_medium <= 2'd0; #100; enable <= 1;
#2000; enable <= 0; select_medium <= 2'd1; #100; enable <= 1;
#2000; enable <= 0; select_medium <= 2'd2; #100; enable <= 1;
#2000; enable <= 0; select_medium <= 2'd3; #100; enable <= 1;
#4000;
#2000; enable <= 0; select_fine <= 2'd0; #100; enable <= 1;
#2000; enable <= 0; select_fine <= 2'd1; #100; enable <= 1;
#2000; enable <= 0; select_fine <= 2'd2; #100; enable <= 1;
#2000; enable <= 0; select_fine <= 2'd3; #100; enable <= 1;
#4000;
enable <= 0;
#20;
$finish;
end
endmodule | module ring_oscillator_tb; |
wire clock;
reg enable = 0;
reg [3:0] select_coarse = 4'd0;
reg [1:0] select_medium = 2'd0;
reg [1:0] select_fine = 2'd0;
wire [7:0] select = { select_coarse, select_medium, select_fine };
ring_oscillator #(.number_of_bits_for_coarse_stages(4), .number_of_bits_for_medium_stages(2), .number_of_bits_for_fine_stages(2), .TESTBENCH(1)) ro (.enable(enable), .select(select), .clock_out(clock));
initial begin
#20;
enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd00; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd01; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd02; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd03; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd04; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd05; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd06; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd07; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd08; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd09; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd10; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd11; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd12; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd13; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd14; #100; enable <= 1;
#2000; enable <= 0; select_coarse <= 4'd15; #100; enable <= 1;
#4000;
#2000; enable <= 0; select_medium <= 2'd0; #100; enable <= 1;
#2000; enable <= 0; select_medium <= 2'd1; #100; enable <= 1;
#2000; enable <= 0; select_medium <= 2'd2; #100; enable <= 1;
#2000; enable <= 0; select_medium <= 2'd3; #100; enable <= 1;
#4000;
#2000; enable <= 0; select_fine <= 2'd0; #100; enable <= 1;
#2000; enable <= 0; select_fine <= 2'd1; #100; enable <= 1;
#2000; enable <= 0; select_fine <= 2'd2; #100; enable <= 1;
#2000; enable <= 0; select_fine <= 2'd3; #100; enable <= 1;
#4000;
enable <= 0;
#20;
$finish;
end
endmodule | 2 |
6,030 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module bus_entry_3state #(
parameter WIDTH = 8
) (
input [WIDTH-1:0] I,
input T,
inout [WIDTH-1:0] O
);
assign O = T ? I : {WIDTH{1'bz}};
endmodule | module bus_entry_3state #(
parameter WIDTH = 8
) (
input [WIDTH-1:0] I,
input T,
inout [WIDTH-1:0] O
); |
assign O = T ? I : {WIDTH{1'bz}};
endmodule | 2 |
6,031 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module clock #(
parameter FREQUENCY_OF_CLOCK_HZ = 10000000.0,
parameter PERIOD_OF_CLOCK_NS = 1000000000.0/FREQUENCY_OF_CLOCK_HZ,
parameter HALF_PERIOD_OF_CLOCK_NS = PERIOD_OF_CLOCK_NS / 2.0
) (
output reg clock = 0
);
initial begin
$display("creating clock with half period of %f ns", HALF_PERIOD_OF_CLOCK_NS);
end
always begin
#HALF_PERIOD_OF_CLOCK_NS;
clock = ~clock;
end
endmodule | module clock #(
parameter FREQUENCY_OF_CLOCK_HZ = 10000000.0,
parameter PERIOD_OF_CLOCK_NS = 1000000000.0/FREQUENCY_OF_CLOCK_HZ,
parameter HALF_PERIOD_OF_CLOCK_NS = PERIOD_OF_CLOCK_NS / 2.0
) (
output reg clock = 0
); |
initial begin
$display("creating clock with half period of %f ns", HALF_PERIOD_OF_CLOCK_NS);
end
always begin
#HALF_PERIOD_OF_CLOCK_NS;
clock = ~clock;
end
endmodule | 2 |
6,032 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module ddr (
input clock,
input reset,
input data0_in, data1_in,
output data_out
);
wire clock0, clock180;
assign clock0 = clock;
assign clock180 = ~clock;
ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1'b0), .Q(data_out));
endmodule | module ddr (
input clock,
input reset,
input data0_in, data1_in,
output data_out
); |
wire clock0, clock180;
assign clock0 = clock;
assign clock180 = ~clock;
ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1'b0), .Q(data_out));
endmodule | 2 |
6,033 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module pipeline #(
parameter WIDTH = 8,
parameter DEPTH = 4
) (
input clock,
input [WIDTH-1:0] in,
output [WIDTH-1:0] out
);
reg [WIDTH-1:0] middle [DEPTH-1:0];
integer i;
always @(posedge clock) begin
for (i=1; i<DEPTH; i=i+1) begin
middle[i] <= middle[i-1];
end
middle[0] <= in;
end
assign out = middle[DEPTH-1];
endmodule | module pipeline #(
parameter WIDTH = 8,
parameter DEPTH = 4
) (
input clock,
input [WIDTH-1:0] in,
output [WIDTH-1:0] out
); |
reg [WIDTH-1:0] middle [DEPTH-1:0];
integer i;
always @(posedge clock) begin
for (i=1; i<DEPTH; i=i+1) begin
middle[i] <= middle[i-1];
end
middle[0] <= in;
end
assign out = middle[DEPTH-1];
endmodule | 2 |
6,034 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module arithmetic_pipeline #(
parameter WIDTH = 8,
parameter DEPTH = 4
) (
input clock,
input [WIDTH-1:0] minuend, subtrahend,
output [WIDTH-1:0] difference
);
reg [WIDTH-1:0] middle [DEPTH-1:0];
reg [WIDTH-1:0] previous_subtrahend;
integer i;
always @(posedge clock) begin
for (i=2; i<DEPTH; i=i+1) begin
middle[i] <= middle[i-1];
end
middle[1] <= middle[0] - previous_subtrahend;
middle[0] <= minuend;
previous_subtrahend <= subtrahend;
end
assign difference = middle[DEPTH-1];
endmodule | module arithmetic_pipeline #(
parameter WIDTH = 8,
parameter DEPTH = 4
) (
input clock,
input [WIDTH-1:0] minuend, subtrahend,
output [WIDTH-1:0] difference
); |
reg [WIDTH-1:0] middle [DEPTH-1:0];
reg [WIDTH-1:0] previous_subtrahend;
integer i;
always @(posedge clock) begin
for (i=2; i<DEPTH; i=i+1) begin
middle[i] <= middle[i-1];
end
middle[1] <= middle[0] - previous_subtrahend;
middle[0] <= minuend;
previous_subtrahend <= subtrahend;
end
assign difference = middle[DEPTH-1];
endmodule | 2 |
6,035 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module arithmetic_pipeline_tb();
localparam WIDTH = 8;
localparam DEPTH = 3;
localparam FREQUENCY_OF_CLOCK_HZ = 1000000000;
localparam STEP_DURATION = 4;
wire clock;
clock #(.FREQUENCY_OF_CLOCK_HZ(FREQUENCY_OF_CLOCK_HZ)) c (.clock(clock));
reg [WIDTH-1:0] minuend = 0;
reg [WIDTH-1:0] subtrahend = 0;
wire [WIDTH-1:0] difference;
initial begin
#100; minuend <= 47;
#STEP_DURATION; subtrahend <= 11;
#STEP_DURATION; subtrahend <= 17;
#STEP_DURATION; subtrahend <= 27;
#STEP_DURATION; subtrahend <= 37;
#STEP_DURATION; subtrahend <= 47;
#STEP_DURATION; subtrahend <= 48;
#STEP_DURATION; subtrahend <= 49;
#100;
#STEP_DURATION; minuend <= 53;
#100;
end
arithmetic_pipeline #(.WIDTH(WIDTH), .DEPTH(DEPTH)) ap (.clock(clock), .minuend(minuend), .subtrahend(subtrahend), .difference(difference));
endmodule | module arithmetic_pipeline_tb(); |
localparam WIDTH = 8;
localparam DEPTH = 3;
localparam FREQUENCY_OF_CLOCK_HZ = 1000000000;
localparam STEP_DURATION = 4;
wire clock;
clock #(.FREQUENCY_OF_CLOCK_HZ(FREQUENCY_OF_CLOCK_HZ)) c (.clock(clock));
reg [WIDTH-1:0] minuend = 0;
reg [WIDTH-1:0] subtrahend = 0;
wire [WIDTH-1:0] difference;
initial begin
#100; minuend <= 47;
#STEP_DURATION; subtrahend <= 11;
#STEP_DURATION; subtrahend <= 17;
#STEP_DURATION; subtrahend <= 27;
#STEP_DURATION; subtrahend <= 37;
#STEP_DURATION; subtrahend <= 47;
#STEP_DURATION; subtrahend <= 48;
#STEP_DURATION; subtrahend <= 49;
#100;
#STEP_DURATION; minuend <= 53;
#100;
end
arithmetic_pipeline #(.WIDTH(WIDTH), .DEPTH(DEPTH)) ap (.clock(clock), .minuend(minuend), .subtrahend(subtrahend), .difference(difference));
endmodule | 2 |
6,036 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module cdc_pipeline #(
parameter WIDTH = 8,
parameter DEPTH = 4
) (
input clock,
input [WIDTH-1:0] in,
output [WIDTH-1:0] out
);
(* KEEP = "TRUE" *) wire [WIDTH-1:0] pipeline_cdc;
assign pipeline_cdc = in;
reg [WIDTH-1:0] middle [DEPTH-1:0];
integer i;
always @(posedge clock) begin
for (i=1; i<DEPTH; i=i+1) begin
middle[i] <= middle[i-1];
end
middle[0] <= pipeline_cdc;
end
assign out = middle[DEPTH-1];
endmodule | module cdc_pipeline #(
parameter WIDTH = 8,
parameter DEPTH = 4
) (
input clock,
input [WIDTH-1:0] in,
output [WIDTH-1:0] out
); |
(* KEEP = "TRUE" *) wire [WIDTH-1:0] pipeline_cdc;
assign pipeline_cdc = in;
reg [WIDTH-1:0] middle [DEPTH-1:0];
integer i;
always @(posedge clock) begin
for (i=1; i<DEPTH; i=i+1) begin
middle[i] <= middle[i-1];
end
middle[0] <= pipeline_cdc;
end
assign out = middle[DEPTH-1];
endmodule | 2 |
6,037 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module resync #(
parameter WIDTH = 1
) (
input clock,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out = 0
);
always @(posedge clock) begin
out <= in;
end
endmodule | module resync #(
parameter WIDTH = 1
) (
input clock,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out = 0
); |
always @(posedge clock) begin
out <= in;
end
endmodule | 2 |
6,038 | data/full_repos/permissive/115035459/verilog/src/lib/generic.v | 115,035,459 | generic.v | v | 633 | 229 | [] | [] | [] | null | line:299: before: "if" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n #1; sel <= 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n 2\'b00: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n 2\'b01: begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n 2\'b10: begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n default: begin #DELAY_RISE; O0_prev <= O0; end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n #100; minuend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 17;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 27;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 37;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 47;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 48;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; subtrahend <= 49;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n #STEP_DURATION; minuend <= 53;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mux\'\nmodule mux #(\n ^~~\n : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n ^~~~~~~~\n : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n ^~~~~~~~\n : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n ^~~~~~~~~\n : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n ^~~~~~~~~~~\n : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n ^~~~~~~~~~~\n : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n ^~~~~~~~~~~~~\n : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n ^~~~~~~~~~~~~~~~~~\n : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'ddr\'\nmodule ddr (\n ^~~\n : ... Top module \'pipeline\'\nmodule pipeline #(\n ^~~~~~~~\n : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n ^~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n ^~~~~~~~~~~~\n : ... Top module \'resync\'\nmodule resync #(\n ^~~~~~\n : ... Top module \'bitslip\'\nmodule bitslip #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,814 | module | module bitslip #(
parameter WIDTH = 8,
parameter LOG2_WIDTH = $clog2(WIDTH)
) (
input clock,
input [WIDTH-1:0] data_in,
input [LOG2_WIDTH-1:0] bitslip,
output reg [WIDTH-1:0] data_out
);
reg [2*WIDTH-1:0] long;
always @(posedge clock) begin
data_out <= long[WIDTH+bitslip -: WIDTH];
long <= { long[WIDTH-1:0], data_in };
end
endmodule | module bitslip #(
parameter WIDTH = 8,
parameter LOG2_WIDTH = $clog2(WIDTH)
) (
input clock,
input [WIDTH-1:0] data_in,
input [LOG2_WIDTH-1:0] bitslip,
output reg [WIDTH-1:0] data_out
); |
reg [2*WIDTH-1:0] long;
always @(posedge clock) begin
data_out <= long[WIDTH+bitslip -: WIDTH];
long <= { long[WIDTH-1:0], data_in };
end
endmodule | 2 |
6,039 | data/full_repos/permissive/115035459/verilog/src/lib/half_duplex_rpi_bus.v | 115,035,459 | half_duplex_rpi_bus.v | v | 256 | 161 | [] | [] | [] | null | line:27: before: "=" | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/115035459/verilog/src/lib/half_duplex_rpi_bus.v:27: Little bit endian vector: MSB < LSB of bit range: -1:0\n output reg [LOG2_OF_NUMBER_OF_BANKS-1:0] write_strobe = 0,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/115035459/verilog/src/lib/half_duplex_rpi_bus.v:34: Little bit endian vector: MSB < LSB of bit range: -1:0\n output [LOG2_OF_NUMBER_OF_BANKS-1:0] bank\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/115035459/verilog/src/lib/half_duplex_rpi_bus.v:54: Little bit endian vector: MSB < LSB of bit range: -1:0\n reg [LOG2_OF_TRANSACTIONS_PER_ADDRESS_WORD-1:0] aword = TRANSACTIONS_PER_ADDRESS_WORD-1; \n ^\n%Error: Internal Error: data/full_repos/permissive/115035459/verilog/src/lib/half_duplex_rpi_bus.v:55: ../V3Width.cpp:3809: Under node SEL has no expected width?? Missing Visitor func?\n : ... In instance half_duplex_rpi_bus\n assign bank = address_word_reg[BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD-1 -: LOG2_OF_NUMBER_OF_BANKS];\n ^\n' | 6,815 | module | module half_duplex_rpi_bus #(
parameter BUS_WIDTH = 16,
parameter LOG2_OF_BUS_WIDTH = $clog2(BUS_WIDTH),
parameter TRANSACTIONS_PER_DATA_WORD = 2,
parameter LOG2_OF_TRANSACTIONS_PER_DATA_WORD = $clog2(TRANSACTIONS_PER_DATA_WORD),
parameter TRANSACTIONS_PER_ADDRESS_WORD = 1,
parameter LOG2_OF_TRANSACTIONS_PER_ADDRESS_WORD = $clog2(TRANSACTIONS_PER_ADDRESS_WORD),
parameter BANK_ADDRESS_DEPTH = BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD,
parameter LOG2_OF_NUMBER_OF_BANKS = BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD - BANK_ADDRESS_DEPTH,
parameter ADDRESS_AUTOINCREMENT_MODE = 1,
parameter ERROR_COUNT_PICKOFF = 7,
parameter ANTI_META = 3,
parameter GAP = 0,
parameter EXTRA_PICKOFF = 0
) (
input clock,
input reset,
inout [BUS_WIDTH-1:0] bus,
input read,
input register_select,
input enable,
output ack_valid,
output reg [LOG2_OF_NUMBER_OF_BANKS-1:0] write_strobe = 0,
output [BUS_WIDTH*TRANSACTIONS_PER_DATA_WORD-1:0] write_data_word,
input [BUS_WIDTH*TRANSACTIONS_PER_DATA_WORD-1:0] read_data_word,
output reg [BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD-1:0] address_word_reg = 0,
output reg [ERROR_COUNT_PICKOFF:0] read_errors = 0,
output reg [ERROR_COUNT_PICKOFF:0] write_errors = 0,
output reg [ERROR_COUNT_PICKOFF:0] address_errors = 0,
output [LOG2_OF_NUMBER_OF_BANKS-1:0] bank
);
localparam OTHER_PICKOFF = ANTI_META + EXTRA_PICKOFF;
localparam ENABLE_PIPELINE_PICKOFF = OTHER_PICKOFF + GAP;
localparam REGISTER_SELECT_PIPELINE_PICKOFF = OTHER_PICKOFF;
localparam READ_PIPELINE_PICKOFF = OTHER_PICKOFF;
localparam BUS_PIPELINE_PICKOFF = OTHER_PICKOFF;
genvar i;
integer j;
reg pre_ack_valid = 0;
reg [REGISTER_SELECT_PIPELINE_PICKOFF:0] register_select_pipeline = 0;
reg [READ_PIPELINE_PICKOFF:0] read_pipeline = 0;
reg [ENABLE_PIPELINE_PICKOFF:0] enable_pipeline = 0;
reg [BUS_WIDTH-1:0] bus_pipeline [BUS_PIPELINE_PICKOFF:0];
reg [1:0] astate = 0;
wire [TRANSACTIONS_PER_ADDRESS_WORD*BUS_WIDTH-1:0] address_word;
reg [BUS_WIDTH-1:0] address [TRANSACTIONS_PER_ADDRESS_WORD-1:0];
for (i=0; i<TRANSACTIONS_PER_ADDRESS_WORD; i=i+1) begin : address_array
assign address_word[(i+1)*BUS_WIDTH-1:i*BUS_WIDTH] = address[i];
end
reg [LOG2_OF_TRANSACTIONS_PER_ADDRESS_WORD-1:0] aword = TRANSACTIONS_PER_ADDRESS_WORD-1;
assign bank = address_word_reg[BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD-1 -: LOG2_OF_NUMBER_OF_BANKS];
reg [1:0] wstate = 0;
reg [BUS_WIDTH-1:0] write_data [TRANSACTIONS_PER_DATA_WORD-1:0];
for (i=0; i<TRANSACTIONS_PER_DATA_WORD; i=i+1) begin : write_data_array
assign write_data_word[(i+1)*BUS_WIDTH-1:i*BUS_WIDTH] = write_data[i];
end
reg [LOG2_OF_TRANSACTIONS_PER_DATA_WORD-1:0] wword = TRANSACTIONS_PER_DATA_WORD-1;
reg ready_for_new_read_data_word = 0;
`define READ_DATA_IS_REGTYPE
`ifndef READ_DATA_IS_REGTYPE
wire [BUS_WIDTH-1:0] read_data [TRANSACTIONS_PER_DATA_WORD-1:0];
for (i=0; i<TRANSACTIONS_PER_DATA_WORD; i=i+1) begin : read_data_array
assign read_data[i] = read_data_word[(i+1)*BUS_WIDTH-1:i*BUS_WIDTH];
end
`endif
`ifdef READ_DATA_IS_REGTYPE
reg [BUS_WIDTH-1:0] read_data [TRANSACTIONS_PER_DATA_WORD-1:0];
for (i=0; i<TRANSACTIONS_PER_DATA_WORD; i=i+1) begin : read_data_array
always @(posedge clock) begin
if (reset) begin
read_data[i] <= 0;
end else begin
if (enable_pipeline[ENABLE_PIPELINE_PICKOFF:ENABLE_PIPELINE_PICKOFF-1]==2'b00) begin
if (ready_for_new_read_data_word) begin
read_data[i] <= read_data_word[(i+1)*BUS_WIDTH-1:i*BUS_WIDTH];
end
end
end
end
end
`endif
reg [1:0] rstate = 0;
reg [LOG2_OF_TRANSACTIONS_PER_DATA_WORD-1:0] rword = TRANSACTIONS_PER_DATA_WORD-1;
reg [BUS_WIDTH-1:0] pre_bus = 0;
always @(posedge clock) begin
pre_ack_valid <= 0;
write_strobe <= 0;
if (reset) begin
ready_for_new_read_data_word <= 0;
register_select_pipeline <= 0;
read_pipeline <= 0;
enable_pipeline <= 0;
bus_pipeline[0] <= 0;
astate <= 0;
address_word_reg <= 0;
for (j=0; j<TRANSACTIONS_PER_ADDRESS_WORD; j=j+1) begin : address_clear
address[j] <= 0;
end
aword <= TRANSACTIONS_PER_ADDRESS_WORD-1;
wstate <= 0;
for (j=0; j<TRANSACTIONS_PER_DATA_WORD; j=j+1) begin : write_data_clear
write_data[j] <= 0;
end
wword <= TRANSACTIONS_PER_DATA_WORD-1;
rstate <= 0;
rword <= TRANSACTIONS_PER_DATA_WORD-1;
read_errors <= 0;
write_errors <= 0;
address_errors <= 0;
pre_bus <= 0;
end else begin
if (enable_pipeline[ENABLE_PIPELINE_PICKOFF:ENABLE_PIPELINE_PICKOFF-1]==2'b01) begin
ready_for_new_read_data_word <= 0;
end
if (enable_pipeline[ENABLE_PIPELINE_PICKOFF:ENABLE_PIPELINE_PICKOFF-1]==2'b11) begin
if (read_pipeline[READ_PIPELINE_PICKOFF:READ_PIPELINE_PICKOFF-1]==2'b11) begin
pre_ack_valid <= 1;
if (rstate[1]==0) begin
if (rstate[0]==0) begin
rstate[0] <= 1;
pre_bus <= read_data[rword];
end
end
end else if (read_pipeline[READ_PIPELINE_PICKOFF:READ_PIPELINE_PICKOFF-1]==2'b00) begin
if (register_select_pipeline[REGISTER_SELECT_PIPELINE_PICKOFF:REGISTER_SELECT_PIPELINE_PICKOFF-1]==2'b11) begin
pre_ack_valid <= 1;
if (wstate[1]==0) begin
if (wstate[0]==0) begin
wstate[0] <= 1;
write_data[wword] <= bus_pipeline[BUS_PIPELINE_PICKOFF];
end
end
end else if (register_select_pipeline[REGISTER_SELECT_PIPELINE_PICKOFF:REGISTER_SELECT_PIPELINE_PICKOFF-1]==2'b00) begin
pre_ack_valid <= 1;
if (astate[1]==0) begin
if (astate[0]==0) begin
astate[0] <= 1;
address[aword] <= bus_pipeline[BUS_PIPELINE_PICKOFF];
end
end
end
end
end else if (enable_pipeline[ENABLE_PIPELINE_PICKOFF:ENABLE_PIPELINE_PICKOFF-1]==2'b00) begin
if (ADDRESS_AUTOINCREMENT_MODE) begin
if (rstate[1] || wstate[1]) begin
address_word_reg <= address_word_reg + 1'b1;
end
end
if (wstate) begin
if (rstate || rword!=TRANSACTIONS_PER_DATA_WORD-1) begin
rstate <= 0;
read_errors <= read_errors + 1'b1;
rword <= TRANSACTIONS_PER_DATA_WORD-1;
end
if (astate || aword!=TRANSACTIONS_PER_ADDRESS_WORD-1) begin
astate <= 0;
address_errors <= address_errors + 1'b1;
aword <= TRANSACTIONS_PER_ADDRESS_WORD-1;
end
if (wstate[1]) begin
ready_for_new_read_data_word <= 1;
wstate <= 0;
wword <= TRANSACTIONS_PER_DATA_WORD-1;
end else begin
wstate[0] <= 0;
if (|wword) begin
wword <= wword - 1'b1;
end else begin
wstate[1] <= 1;
write_strobe[bank] <= 1;
end
end
end
if (rstate) begin
if (wstate || wword!=TRANSACTIONS_PER_DATA_WORD-1) begin
wstate <= 0;
write_errors <= write_errors + 1'b1;
wword <= TRANSACTIONS_PER_DATA_WORD-1;
end
if (astate || aword!=TRANSACTIONS_PER_ADDRESS_WORD-1) begin
astate <= 0;
address_errors <= address_errors + 1'b1;
aword <= TRANSACTIONS_PER_ADDRESS_WORD-1;
end
if (rstate[1]) begin
ready_for_new_read_data_word <= 1;
rstate <= 0;
rword <= TRANSACTIONS_PER_DATA_WORD-1;
end else begin
rstate[0] <= 0;
if (|rword) begin
rword <= rword - 1'b1;
end else begin
rstate[1] <= 1;
end
end
end
if (astate) begin
if (wstate || wword!=TRANSACTIONS_PER_DATA_WORD-1) begin
wstate <= 0;
write_errors <= write_errors + 1'b1;
wword <= TRANSACTIONS_PER_DATA_WORD-1;
end
if (rstate || rword!=TRANSACTIONS_PER_DATA_WORD-1) begin
rstate <= 0;
read_errors <= read_errors + 1'b1;
rword <= TRANSACTIONS_PER_DATA_WORD-1;
end
if (astate[1]) begin
ready_for_new_read_data_word <= 1;
astate <= 0;
aword <= TRANSACTIONS_PER_ADDRESS_WORD-1;
address_word_reg <= address_word;
end else begin
astate[0] <= 0;
if (|aword) begin
aword <= aword - 1'b1;
end else begin
astate[1] <= 1;
end
end
end
end
register_select_pipeline <= { register_select_pipeline[REGISTER_SELECT_PIPELINE_PICKOFF-1:0], register_select };
read_pipeline <= { read_pipeline[READ_PIPELINE_PICKOFF-1:0], read };
enable_pipeline <= { enable_pipeline[ENABLE_PIPELINE_PICKOFF-1:0], enable };
bus_pipeline[0] <= bus;
end
end
for (i=1; i<BUS_PIPELINE_PICKOFF+1; i=i+1) begin : bus_pipeline_thing
always @(posedge clock) begin
if (reset) begin
bus_pipeline[i] <= 0;
end else begin
bus_pipeline[i] <= bus_pipeline[i-1];
end
end
end
assign ack_valid = pre_ack_valid;
bus_entry_3state #(.WIDTH(BUS_WIDTH)) my3sbe (.I(pre_bus), .O(bus), .T(read));
endmodule | module half_duplex_rpi_bus #(
parameter BUS_WIDTH = 16,
parameter LOG2_OF_BUS_WIDTH = $clog2(BUS_WIDTH),
parameter TRANSACTIONS_PER_DATA_WORD = 2,
parameter LOG2_OF_TRANSACTIONS_PER_DATA_WORD = $clog2(TRANSACTIONS_PER_DATA_WORD),
parameter TRANSACTIONS_PER_ADDRESS_WORD = 1,
parameter LOG2_OF_TRANSACTIONS_PER_ADDRESS_WORD = $clog2(TRANSACTIONS_PER_ADDRESS_WORD),
parameter BANK_ADDRESS_DEPTH = BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD,
parameter LOG2_OF_NUMBER_OF_BANKS = BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD - BANK_ADDRESS_DEPTH,
parameter ADDRESS_AUTOINCREMENT_MODE = 1,
parameter ERROR_COUNT_PICKOFF = 7,
parameter ANTI_META = 3,
parameter GAP = 0,
parameter EXTRA_PICKOFF = 0
) (
input clock,
input reset,
inout [BUS_WIDTH-1:0] bus,
input read,
input register_select,
input enable,
output ack_valid,
output reg [LOG2_OF_NUMBER_OF_BANKS-1:0] write_strobe = 0,
output [BUS_WIDTH*TRANSACTIONS_PER_DATA_WORD-1:0] write_data_word,
input [BUS_WIDTH*TRANSACTIONS_PER_DATA_WORD-1:0] read_data_word,
output reg [BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD-1:0] address_word_reg = 0,
output reg [ERROR_COUNT_PICKOFF:0] read_errors = 0,
output reg [ERROR_COUNT_PICKOFF:0] write_errors = 0,
output reg [ERROR_COUNT_PICKOFF:0] address_errors = 0,
output [LOG2_OF_NUMBER_OF_BANKS-1:0] bank
); |
localparam OTHER_PICKOFF = ANTI_META + EXTRA_PICKOFF;
localparam ENABLE_PIPELINE_PICKOFF = OTHER_PICKOFF + GAP;
localparam REGISTER_SELECT_PIPELINE_PICKOFF = OTHER_PICKOFF;
localparam READ_PIPELINE_PICKOFF = OTHER_PICKOFF;
localparam BUS_PIPELINE_PICKOFF = OTHER_PICKOFF;
genvar i;
integer j;
reg pre_ack_valid = 0;
reg [REGISTER_SELECT_PIPELINE_PICKOFF:0] register_select_pipeline = 0;
reg [READ_PIPELINE_PICKOFF:0] read_pipeline = 0;
reg [ENABLE_PIPELINE_PICKOFF:0] enable_pipeline = 0;
reg [BUS_WIDTH-1:0] bus_pipeline [BUS_PIPELINE_PICKOFF:0];
reg [1:0] astate = 0;
wire [TRANSACTIONS_PER_ADDRESS_WORD*BUS_WIDTH-1:0] address_word;
reg [BUS_WIDTH-1:0] address [TRANSACTIONS_PER_ADDRESS_WORD-1:0];
for (i=0; i<TRANSACTIONS_PER_ADDRESS_WORD; i=i+1) begin : address_array
assign address_word[(i+1)*BUS_WIDTH-1:i*BUS_WIDTH] = address[i];
end
reg [LOG2_OF_TRANSACTIONS_PER_ADDRESS_WORD-1:0] aword = TRANSACTIONS_PER_ADDRESS_WORD-1;
assign bank = address_word_reg[BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD-1 -: LOG2_OF_NUMBER_OF_BANKS];
reg [1:0] wstate = 0;
reg [BUS_WIDTH-1:0] write_data [TRANSACTIONS_PER_DATA_WORD-1:0];
for (i=0; i<TRANSACTIONS_PER_DATA_WORD; i=i+1) begin : write_data_array
assign write_data_word[(i+1)*BUS_WIDTH-1:i*BUS_WIDTH] = write_data[i];
end
reg [LOG2_OF_TRANSACTIONS_PER_DATA_WORD-1:0] wword = TRANSACTIONS_PER_DATA_WORD-1;
reg ready_for_new_read_data_word = 0;
`define READ_DATA_IS_REGTYPE
`ifndef READ_DATA_IS_REGTYPE
wire [BUS_WIDTH-1:0] read_data [TRANSACTIONS_PER_DATA_WORD-1:0];
for (i=0; i<TRANSACTIONS_PER_DATA_WORD; i=i+1) begin : read_data_array
assign read_data[i] = read_data_word[(i+1)*BUS_WIDTH-1:i*BUS_WIDTH];
end
`endif
`ifdef READ_DATA_IS_REGTYPE
reg [BUS_WIDTH-1:0] read_data [TRANSACTIONS_PER_DATA_WORD-1:0];
for (i=0; i<TRANSACTIONS_PER_DATA_WORD; i=i+1) begin : read_data_array
always @(posedge clock) begin
if (reset) begin
read_data[i] <= 0;
end else begin
if (enable_pipeline[ENABLE_PIPELINE_PICKOFF:ENABLE_PIPELINE_PICKOFF-1]==2'b00) begin
if (ready_for_new_read_data_word) begin
read_data[i] <= read_data_word[(i+1)*BUS_WIDTH-1:i*BUS_WIDTH];
end
end
end
end
end
`endif
reg [1:0] rstate = 0;
reg [LOG2_OF_TRANSACTIONS_PER_DATA_WORD-1:0] rword = TRANSACTIONS_PER_DATA_WORD-1;
reg [BUS_WIDTH-1:0] pre_bus = 0;
always @(posedge clock) begin
pre_ack_valid <= 0;
write_strobe <= 0;
if (reset) begin
ready_for_new_read_data_word <= 0;
register_select_pipeline <= 0;
read_pipeline <= 0;
enable_pipeline <= 0;
bus_pipeline[0] <= 0;
astate <= 0;
address_word_reg <= 0;
for (j=0; j<TRANSACTIONS_PER_ADDRESS_WORD; j=j+1) begin : address_clear
address[j] <= 0;
end
aword <= TRANSACTIONS_PER_ADDRESS_WORD-1;
wstate <= 0;
for (j=0; j<TRANSACTIONS_PER_DATA_WORD; j=j+1) begin : write_data_clear
write_data[j] <= 0;
end
wword <= TRANSACTIONS_PER_DATA_WORD-1;
rstate <= 0;
rword <= TRANSACTIONS_PER_DATA_WORD-1;
read_errors <= 0;
write_errors <= 0;
address_errors <= 0;
pre_bus <= 0;
end else begin
if (enable_pipeline[ENABLE_PIPELINE_PICKOFF:ENABLE_PIPELINE_PICKOFF-1]==2'b01) begin
ready_for_new_read_data_word <= 0;
end
if (enable_pipeline[ENABLE_PIPELINE_PICKOFF:ENABLE_PIPELINE_PICKOFF-1]==2'b11) begin
if (read_pipeline[READ_PIPELINE_PICKOFF:READ_PIPELINE_PICKOFF-1]==2'b11) begin
pre_ack_valid <= 1;
if (rstate[1]==0) begin
if (rstate[0]==0) begin
rstate[0] <= 1;
pre_bus <= read_data[rword];
end
end
end else if (read_pipeline[READ_PIPELINE_PICKOFF:READ_PIPELINE_PICKOFF-1]==2'b00) begin
if (register_select_pipeline[REGISTER_SELECT_PIPELINE_PICKOFF:REGISTER_SELECT_PIPELINE_PICKOFF-1]==2'b11) begin
pre_ack_valid <= 1;
if (wstate[1]==0) begin
if (wstate[0]==0) begin
wstate[0] <= 1;
write_data[wword] <= bus_pipeline[BUS_PIPELINE_PICKOFF];
end
end
end else if (register_select_pipeline[REGISTER_SELECT_PIPELINE_PICKOFF:REGISTER_SELECT_PIPELINE_PICKOFF-1]==2'b00) begin
pre_ack_valid <= 1;
if (astate[1]==0) begin
if (astate[0]==0) begin
astate[0] <= 1;
address[aword] <= bus_pipeline[BUS_PIPELINE_PICKOFF];
end
end
end
end
end else if (enable_pipeline[ENABLE_PIPELINE_PICKOFF:ENABLE_PIPELINE_PICKOFF-1]==2'b00) begin
if (ADDRESS_AUTOINCREMENT_MODE) begin
if (rstate[1] || wstate[1]) begin
address_word_reg <= address_word_reg + 1'b1;
end
end
if (wstate) begin
if (rstate || rword!=TRANSACTIONS_PER_DATA_WORD-1) begin
rstate <= 0;
read_errors <= read_errors + 1'b1;
rword <= TRANSACTIONS_PER_DATA_WORD-1;
end
if (astate || aword!=TRANSACTIONS_PER_ADDRESS_WORD-1) begin
astate <= 0;
address_errors <= address_errors + 1'b1;
aword <= TRANSACTIONS_PER_ADDRESS_WORD-1;
end
if (wstate[1]) begin
ready_for_new_read_data_word <= 1;
wstate <= 0;
wword <= TRANSACTIONS_PER_DATA_WORD-1;
end else begin
wstate[0] <= 0;
if (|wword) begin
wword <= wword - 1'b1;
end else begin
wstate[1] <= 1;
write_strobe[bank] <= 1;
end
end
end
if (rstate) begin
if (wstate || wword!=TRANSACTIONS_PER_DATA_WORD-1) begin
wstate <= 0;
write_errors <= write_errors + 1'b1;
wword <= TRANSACTIONS_PER_DATA_WORD-1;
end
if (astate || aword!=TRANSACTIONS_PER_ADDRESS_WORD-1) begin
astate <= 0;
address_errors <= address_errors + 1'b1;
aword <= TRANSACTIONS_PER_ADDRESS_WORD-1;
end
if (rstate[1]) begin
ready_for_new_read_data_word <= 1;
rstate <= 0;
rword <= TRANSACTIONS_PER_DATA_WORD-1;
end else begin
rstate[0] <= 0;
if (|rword) begin
rword <= rword - 1'b1;
end else begin
rstate[1] <= 1;
end
end
end
if (astate) begin
if (wstate || wword!=TRANSACTIONS_PER_DATA_WORD-1) begin
wstate <= 0;
write_errors <= write_errors + 1'b1;
wword <= TRANSACTIONS_PER_DATA_WORD-1;
end
if (rstate || rword!=TRANSACTIONS_PER_DATA_WORD-1) begin
rstate <= 0;
read_errors <= read_errors + 1'b1;
rword <= TRANSACTIONS_PER_DATA_WORD-1;
end
if (astate[1]) begin
ready_for_new_read_data_word <= 1;
astate <= 0;
aword <= TRANSACTIONS_PER_ADDRESS_WORD-1;
address_word_reg <= address_word;
end else begin
astate[0] <= 0;
if (|aword) begin
aword <= aword - 1'b1;
end else begin
astate[1] <= 1;
end
end
end
end
register_select_pipeline <= { register_select_pipeline[REGISTER_SELECT_PIPELINE_PICKOFF-1:0], register_select };
read_pipeline <= { read_pipeline[READ_PIPELINE_PICKOFF-1:0], read };
enable_pipeline <= { enable_pipeline[ENABLE_PIPELINE_PICKOFF-1:0], enable };
bus_pipeline[0] <= bus;
end
end
for (i=1; i<BUS_PIPELINE_PICKOFF+1; i=i+1) begin : bus_pipeline_thing
always @(posedge clock) begin
if (reset) begin
bus_pipeline[i] <= 0;
end else begin
bus_pipeline[i] <= bus_pipeline[i-1];
end
end
end
assign ack_valid = pre_ack_valid;
bus_entry_3state #(.WIDTH(BUS_WIDTH)) my3sbe (.I(pre_bus), .O(bus), .T(read));
endmodule | 2 |
6,042 | data/full_repos/permissive/115035459/verilog/src/lib/histogram.v | 115,035,459 | histogram.v | v | 515 | 191 | [] | [] | [] | null | line:313: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:7: Cannot find include file: RAM8.v\n`include "RAM8.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/RAM8.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/RAM8.v.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/RAM8.v.sv\n RAM8.v\n RAM8.v.v\n RAM8.v.sv\n obj_dir/RAM8.v\n obj_dir/RAM8.v.v\n obj_dir/RAM8.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:8: Cannot find include file: fifo.v\n`include "fifo.v" \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:9: Cannot find include file: generic.v\n`include "generic.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:22: Define or directive not defined: \'`LOG2_OF_BASE_BLOCK_MEMORY_SIZE\'\n parameter PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + $clog2(DATA_WIDTH) - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:22: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n parameter PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + $clog2(DATA_WIDTH) - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE,\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:24: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST = LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE - LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:25: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter USE_BLOCK_MEMORY = 1\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:26: syntax error, unexpected \')\', expecting \';\'\n) (\n^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:40: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg partial_count_reached = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:41: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg max_count_reached = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:42: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg adding_finished = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:43: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg result_valid = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:44: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output [31:0] error_count\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:77: syntax error, unexpected assign\n assign ram_read_address = { {RAM_ADDRESS_DEPTH-DATA_WIDTH{1\'b0}}, adding_not_comparing ? data_out_from_fifo : j };\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:92: syntax error, unexpected always\n always @(posedge clock) begin\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:414: Unsupported: Ignoring delay on this delayed statement.\n #100; reset <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:415: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:415: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:415: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:416: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:416: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:416: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:417: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:417: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:417: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:418: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:418: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:418: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:419: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:419: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:419: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:420: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:420: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:420: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:421: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:421: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:421: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:422: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:422: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:422: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:423: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:423: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:423: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:424: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:424: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:424: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:426: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:426: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:426: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:427: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:427: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:427: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:428: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:428: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:428: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:429: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:429: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:429: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:430: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h22; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:430: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h22; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:430: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h22; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:431: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:431: syntax error, unexpected \'@\'\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:431: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:432: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:432: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:432: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:433: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:433: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:433: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:434: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:434: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:434: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:435: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:435: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:435: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:436: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:436: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:436: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:437: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:437: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:437: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:438: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:438: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:438: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:439: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:439: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:439: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:440: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:440: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:440: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:441: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:441: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:441: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:442: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:442: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:442: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:443: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:443: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:443: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:444: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:444: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:444: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:445: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:445: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:445: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:446: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:446: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:446: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:447: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:447: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:447: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:448: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:448: syntax error, unexpected \'@\'\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:448: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:451: Unsupported: Ignoring delay on this delayed statement.\n #(4*13);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:453: Unsupported: Ignoring delay on this delayed statement.\n #(4*3);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:455: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:455: syntax error, unexpected \'@\'\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:455: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:456: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:456: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:456: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:457: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:457: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:457: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:458: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:458: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:458: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:459: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:459: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:459: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:460: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:460: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:460: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:461: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:461: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:461: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:462: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:462: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:462: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:463: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:463: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:463: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:464: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:464: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:464: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:465: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:465: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:465: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:466: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:466: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:466: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:467: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:467: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:467: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:468: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:468: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:468: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:469: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:469: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:469: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:470: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:470: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:470: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:471: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:471: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:471: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:472: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:472: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:472: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:473: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:473: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:473: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:474: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:474: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:474: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:475: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:475: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:475: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:476: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:476: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:476: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:477: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:477: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:477: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:478: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:478: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:478: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:479: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:479: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:479: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:480: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:481: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d23; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:481: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d23; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:481: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d23; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:482: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d29; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:482: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d29; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:482: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d29; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:483: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d31; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:483: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d31; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:483: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d31; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:484: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d37; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:484: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d37; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:484: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d37; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:485: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d41; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:485: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d41; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:485: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d41; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:486: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d43; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:486: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d43; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:486: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d43; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:487: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d47; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:487: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d47; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:487: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d47; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:488: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d53; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:488: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d53; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:488: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d53; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:489: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d59; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:489: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d59; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:489: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d59; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:490: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d61; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:490: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d61; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:490: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d61; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:491: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d67; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:491: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d67; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:491: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d67; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:492: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d71; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:492: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d71; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:492: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d71; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:493: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d73; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:493: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d73; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:493: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d73; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:494: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d79; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:494: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d79; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:494: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d79; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:495: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:495: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:495: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:496: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d89; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:496: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d89; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:496: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d89; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:497: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d97; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:497: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d97; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:497: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d97; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:498: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:499: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h84; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:499: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h84; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:499: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h84; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:500: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h85; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:500: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h85; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:500: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h85; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:501: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h86; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:501: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h86; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:501: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h86; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:502: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h87; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:502: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h87; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:502: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h87; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:503: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:504: Unsupported: Ignoring delay on this delayed statement.\n #20; @(posedge result_valid);\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:504: syntax error, unexpected \'@\'\n #20; @(posedge result_valid);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:505: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:506: Unsupported: Ignoring delay on this delayed statement.\n #1000; clear_results <= 1; #4; clear_results <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:506: Unsupported: Ignoring delay on this delayed statement.\n #1000; clear_results <= 1; #4; clear_results <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:507: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:508: Unsupported: Ignoring delay on this delayed statement.\n #100; $finish;\n ^\n%Error: Exiting due to 19 error(s), 249 warning(s)\n' | 6,817 | module | module histogram #(
parameter DATA_WIDTH = 4,
parameter LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE = 4,
parameter TESTBENCH = 0,
parameter PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + $clog2(DATA_WIDTH) - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE,
parameter LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO < 0 ? 0 : PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO,
parameter LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST = LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE - LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO,
parameter USE_BLOCK_MEMORY = 1
) (
input reset, clock,
input sample,
input clear_results,
input [DATA_WIDTH-1:0] data_in,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count00,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count01,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count02,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count03,
output [DATA_WIDTH-1:0] result00,
output [DATA_WIDTH-1:0] result01,
output [DATA_WIDTH-1:0] result02,
output [DATA_WIDTH-1:0] result03,
output reg [LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO-1:0] capture_completion = 0,
output reg partial_count_reached = 0,
output reg max_count_reached = 0,
output reg adding_finished = 0,
output reg result_valid = 0,
output [31:0] error_count
);
localparam MAX_INDEX = (1<<DATA_WIDTH) - 1;
localparam MAXIMUM_SAMPLE_NUMBER = (1<<LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST) - 1;
localparam LOG2_OF_NUMBER_OF_RESULTS = 2;
localparam LAST_RESULT = (1<<LOG2_OF_NUMBER_OF_RESULTS) - 1;
localparam RAM_DATA_WIDTH = USE_BLOCK_MEMORY ? 32 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE;
localparam RAM_ADDRESS_DEPTH = USE_BLOCK_MEMORY ? 9 : DATA_WIDTH;
localparam LAST_FIFO_FILL_NUMBER = (1<<LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO) - 1;
reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count_copy [LAST_RESULT:0];
reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST-1:0] sample_counter = 0;
reg [LAST_RESULT:0] i = 0;
reg [RAM_DATA_WIDTH-1:0] max_so_far = 0;
reg [DATA_WIDTH-1:0] j = 0;
reg [DATA_WIDTH-1:0] index [LAST_RESULT:0];
reg fifo_read_enable = 0;
reg [DATA_WIDTH-1:0] previous_data_out_from_fifo = 0;
wire [DATA_WIDTH-1:0] data_out_from_fifo;
wire [RAM_ADDRESS_DEPTH-1:0] ram_read_address;
wire [RAM_ADDRESS_DEPTH-1:0] ram_write_address;
reg adding_ram_write_enable = 0;
reg comparing_ram_write_enable = 0;
wire ram_write_enable;
wire fifo_full;
wire should_keep_sampling = sample && (~partial_count_reached);
wire [RAM_DATA_WIDTH-1:0] ram_data_in;
wire [RAM_DATA_WIDTH-1:0] data_out_from_ram;
reg [2:0] adding_state = 0;
reg [2:0] comparing_state = 0;
reg [RAM_DATA_WIDTH-1:0] count = 0;
reg adding_not_comparing = 0;
reg comparing_write_enable = 0;
assign ram_read_address = { {RAM_ADDRESS_DEPTH-DATA_WIDTH{1'b0}}, adding_not_comparing ? data_out_from_fifo : j };
assign ram_write_address = { {RAM_ADDRESS_DEPTH-DATA_WIDTH{1'b0}}, adding_not_comparing ? previous_data_out_from_fifo : j };
assign ram_write_enable = adding_not_comparing ? adding_ram_write_enable : comparing_write_enable;
assign ram_data_in = adding_not_comparing ? count : {RAM_DATA_WIDTH{1'b0}} ;
fifo_single_clock_using_single_bram #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_DEPTH(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST)) fsc (
.clock(clock), .reset(reset), .error_count(error_count),
.data_in(data_in), .write_enable(should_keep_sampling), .full(), .almost_full(), .full_or_almost_full(fifo_full),
.data_out(data_out_from_fifo), .read_enable(fifo_read_enable), .empty(), .almost_empty(), .empty_or_almost_empty());
if (USE_BLOCK_MEMORY) begin
RAM_s6_primitive #(.DATA_WIDTH_A(RAM_DATA_WIDTH), .DATA_WIDTH_B(RAM_DATA_WIDTH)) mem (.reset(reset),
.write_clock(clock), .write_address(ram_write_address), .data_in(ram_data_in), .write_enable(ram_write_enable),
.read_clock(clock), .read_address(ram_read_address), .read_enable(1'b1), .data_out(data_out_from_ram));
end else begin
reg [RAM_ADDRESS_DEPTH-1:0] mem [(1<<RAM_ADDRESS_DEPTH)-1:0];
always @(posedge clock) begin
if (reset || clear_results) begin
end else begin
if (ram_write_enable) begin
mem[ram_write_address] <= ram_data_in;
end
end
end
assign data_out_from_ram = mem[ram_read_address];
end
always @(posedge clock) begin
if (reset || clear_results) begin
fifo_read_enable <= 0;
sample_counter <= 0;
adding_ram_write_enable <= 0;
adding_state <= 3'd0;
count <= 0;
max_count_reached <= 0;
previous_data_out_from_fifo <= 0;
adding_finished <= 0;
partial_count_reached <= 0;
capture_completion <= 0;
end else begin
if (~result_valid) begin
if (~adding_finished) begin
if (partial_count_reached) begin
case (adding_state)
3'd0 : begin
if (adding_not_comparing) begin
adding_state <= 3'd1;
end
end
3'd1 : begin
fifo_read_enable <= 1;
adding_state <= 3'd2;
end
3'd2 : begin
fifo_read_enable <= 0;
count <= data_out_from_ram;
previous_data_out_from_fifo <= data_out_from_fifo;
adding_state <= 3'd3;
end
3'd3 : begin
count <= count + 3'd1;
adding_ram_write_enable <= 1;
adding_state <= 3'd4;
end
3'd4 : begin
adding_ram_write_enable <= 0;
adding_state <= 3'd5;
end
default : begin
if (sample_counter!=MAXIMUM_SAMPLE_NUMBER) begin
sample_counter <= sample_counter + 1'd1;
end else begin
if (max_count_reached) begin
adding_finished <= 1;
end else begin
partial_count_reached <= 0;
sample_counter <= 0;
end
fifo_read_enable <= 0;
end
adding_state <= 3'd1;
end
endcase
end
if (fifo_full && ~partial_count_reached) begin
partial_count_reached <= 1;
if (capture_completion!=LAST_FIFO_FILL_NUMBER) begin
capture_completion <= capture_completion + 1'd1;
end else begin
max_count_reached <= 1;
end
end
end
end
end
end
always @(posedge clock) begin
if (reset || clear_results) begin
i <= 0;
j <= 0;
max_so_far <= 0;
index[0] <= 0;
index[1] <= 0;
index[2] <= 0;
index[3] <= 0;
count_copy[0] <= 0;
count_copy[1] <= 0;
count_copy[2] <= 0;
count_copy[3] <= 0;
result_valid <= 0;
comparing_state <= 0;
comparing_write_enable <= 0;
adding_not_comparing <= 0;
end else begin
if (~result_valid) begin
if ((~adding_not_comparing) && adding_state==3'd0) begin
comparing_write_enable <= 1;
if (j!=MAX_INDEX) begin
j <= j + 1'd1;
end else begin
j <= 0;
comparing_write_enable <= 0;
adding_not_comparing <= 1;
end
end
if (max_count_reached && adding_finished) begin
adding_not_comparing <= 0;
case (comparing_state)
3'd0 : begin
comparing_write_enable <= 0;
comparing_state <= 3'd1;
end
3'd1 : begin
j <= 1'd1;
comparing_state <= 3'd2;
end
3'd2 : begin
max_so_far <= data_out_from_ram;
comparing_state <= 3'd3;
end
3'd3 : begin
comparing_state <= 3'd4;
end
3'd4 : begin
if (max_so_far<data_out_from_ram) begin
index[i] <= j;
max_so_far <= data_out_from_ram;
end
if (j!=MAX_INDEX) begin
j <= j + 1'd1;
comparing_state <= 3'd3;
end else begin
j <= index[i];
comparing_state <= 3'd5;
end
end
3'd5 : begin
count_copy[i] <= max_so_far[LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
comparing_write_enable <= 1;
comparing_state <= 3'd6;
end
default : begin
comparing_write_enable <= 0;
if (i!=LAST_RESULT) begin
i <= i + 1'd1;
j <= 0;
end else begin
result_valid <= 1;
end
comparing_state <= 3'd1;
end
endcase
end
end
end
end
assign result00 = index[0];
assign result01 = index[1];
assign result02 = index[2];
assign result03 = index[3];
assign count00 = count_copy[0][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
assign count01 = count_copy[1][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
assign count02 = count_copy[2][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
assign count03 = count_copy[3][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
endmodule | module histogram #(
parameter DATA_WIDTH = 4,
parameter LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE = 4,
parameter TESTBENCH = 0,
parameter PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + $clog2(DATA_WIDTH) - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE,
parameter LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO < 0 ? 0 : PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO,
parameter LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST = LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE - LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO,
parameter USE_BLOCK_MEMORY = 1
) (
input reset, clock,
input sample,
input clear_results,
input [DATA_WIDTH-1:0] data_in,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count00,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count01,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count02,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count03,
output [DATA_WIDTH-1:0] result00,
output [DATA_WIDTH-1:0] result01,
output [DATA_WIDTH-1:0] result02,
output [DATA_WIDTH-1:0] result03,
output reg [LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO-1:0] capture_completion = 0,
output reg partial_count_reached = 0,
output reg max_count_reached = 0,
output reg adding_finished = 0,
output reg result_valid = 0,
output [31:0] error_count
); |
localparam MAX_INDEX = (1<<DATA_WIDTH) - 1;
localparam MAXIMUM_SAMPLE_NUMBER = (1<<LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST) - 1;
localparam LOG2_OF_NUMBER_OF_RESULTS = 2;
localparam LAST_RESULT = (1<<LOG2_OF_NUMBER_OF_RESULTS) - 1;
localparam RAM_DATA_WIDTH = USE_BLOCK_MEMORY ? 32 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE;
localparam RAM_ADDRESS_DEPTH = USE_BLOCK_MEMORY ? 9 : DATA_WIDTH;
localparam LAST_FIFO_FILL_NUMBER = (1<<LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO) - 1;
reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count_copy [LAST_RESULT:0];
reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST-1:0] sample_counter = 0;
reg [LAST_RESULT:0] i = 0;
reg [RAM_DATA_WIDTH-1:0] max_so_far = 0;
reg [DATA_WIDTH-1:0] j = 0;
reg [DATA_WIDTH-1:0] index [LAST_RESULT:0];
reg fifo_read_enable = 0;
reg [DATA_WIDTH-1:0] previous_data_out_from_fifo = 0;
wire [DATA_WIDTH-1:0] data_out_from_fifo;
wire [RAM_ADDRESS_DEPTH-1:0] ram_read_address;
wire [RAM_ADDRESS_DEPTH-1:0] ram_write_address;
reg adding_ram_write_enable = 0;
reg comparing_ram_write_enable = 0;
wire ram_write_enable;
wire fifo_full;
wire should_keep_sampling = sample && (~partial_count_reached);
wire [RAM_DATA_WIDTH-1:0] ram_data_in;
wire [RAM_DATA_WIDTH-1:0] data_out_from_ram;
reg [2:0] adding_state = 0;
reg [2:0] comparing_state = 0;
reg [RAM_DATA_WIDTH-1:0] count = 0;
reg adding_not_comparing = 0;
reg comparing_write_enable = 0;
assign ram_read_address = { {RAM_ADDRESS_DEPTH-DATA_WIDTH{1'b0}}, adding_not_comparing ? data_out_from_fifo : j };
assign ram_write_address = { {RAM_ADDRESS_DEPTH-DATA_WIDTH{1'b0}}, adding_not_comparing ? previous_data_out_from_fifo : j };
assign ram_write_enable = adding_not_comparing ? adding_ram_write_enable : comparing_write_enable;
assign ram_data_in = adding_not_comparing ? count : {RAM_DATA_WIDTH{1'b0}} ;
fifo_single_clock_using_single_bram #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_DEPTH(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST)) fsc (
.clock(clock), .reset(reset), .error_count(error_count),
.data_in(data_in), .write_enable(should_keep_sampling), .full(), .almost_full(), .full_or_almost_full(fifo_full),
.data_out(data_out_from_fifo), .read_enable(fifo_read_enable), .empty(), .almost_empty(), .empty_or_almost_empty());
if (USE_BLOCK_MEMORY) begin
RAM_s6_primitive #(.DATA_WIDTH_A(RAM_DATA_WIDTH), .DATA_WIDTH_B(RAM_DATA_WIDTH)) mem (.reset(reset),
.write_clock(clock), .write_address(ram_write_address), .data_in(ram_data_in), .write_enable(ram_write_enable),
.read_clock(clock), .read_address(ram_read_address), .read_enable(1'b1), .data_out(data_out_from_ram));
end else begin
reg [RAM_ADDRESS_DEPTH-1:0] mem [(1<<RAM_ADDRESS_DEPTH)-1:0];
always @(posedge clock) begin
if (reset || clear_results) begin
end else begin
if (ram_write_enable) begin
mem[ram_write_address] <= ram_data_in;
end
end
end
assign data_out_from_ram = mem[ram_read_address];
end
always @(posedge clock) begin
if (reset || clear_results) begin
fifo_read_enable <= 0;
sample_counter <= 0;
adding_ram_write_enable <= 0;
adding_state <= 3'd0;
count <= 0;
max_count_reached <= 0;
previous_data_out_from_fifo <= 0;
adding_finished <= 0;
partial_count_reached <= 0;
capture_completion <= 0;
end else begin
if (~result_valid) begin
if (~adding_finished) begin
if (partial_count_reached) begin
case (adding_state)
3'd0 : begin
if (adding_not_comparing) begin
adding_state <= 3'd1;
end
end
3'd1 : begin
fifo_read_enable <= 1;
adding_state <= 3'd2;
end
3'd2 : begin
fifo_read_enable <= 0;
count <= data_out_from_ram;
previous_data_out_from_fifo <= data_out_from_fifo;
adding_state <= 3'd3;
end
3'd3 : begin
count <= count + 3'd1;
adding_ram_write_enable <= 1;
adding_state <= 3'd4;
end
3'd4 : begin
adding_ram_write_enable <= 0;
adding_state <= 3'd5;
end
default : begin
if (sample_counter!=MAXIMUM_SAMPLE_NUMBER) begin
sample_counter <= sample_counter + 1'd1;
end else begin
if (max_count_reached) begin
adding_finished <= 1;
end else begin
partial_count_reached <= 0;
sample_counter <= 0;
end
fifo_read_enable <= 0;
end
adding_state <= 3'd1;
end
endcase
end
if (fifo_full && ~partial_count_reached) begin
partial_count_reached <= 1;
if (capture_completion!=LAST_FIFO_FILL_NUMBER) begin
capture_completion <= capture_completion + 1'd1;
end else begin
max_count_reached <= 1;
end
end
end
end
end
end
always @(posedge clock) begin
if (reset || clear_results) begin
i <= 0;
j <= 0;
max_so_far <= 0;
index[0] <= 0;
index[1] <= 0;
index[2] <= 0;
index[3] <= 0;
count_copy[0] <= 0;
count_copy[1] <= 0;
count_copy[2] <= 0;
count_copy[3] <= 0;
result_valid <= 0;
comparing_state <= 0;
comparing_write_enable <= 0;
adding_not_comparing <= 0;
end else begin
if (~result_valid) begin
if ((~adding_not_comparing) && adding_state==3'd0) begin
comparing_write_enable <= 1;
if (j!=MAX_INDEX) begin
j <= j + 1'd1;
end else begin
j <= 0;
comparing_write_enable <= 0;
adding_not_comparing <= 1;
end
end
if (max_count_reached && adding_finished) begin
adding_not_comparing <= 0;
case (comparing_state)
3'd0 : begin
comparing_write_enable <= 0;
comparing_state <= 3'd1;
end
3'd1 : begin
j <= 1'd1;
comparing_state <= 3'd2;
end
3'd2 : begin
max_so_far <= data_out_from_ram;
comparing_state <= 3'd3;
end
3'd3 : begin
comparing_state <= 3'd4;
end
3'd4 : begin
if (max_so_far<data_out_from_ram) begin
index[i] <= j;
max_so_far <= data_out_from_ram;
end
if (j!=MAX_INDEX) begin
j <= j + 1'd1;
comparing_state <= 3'd3;
end else begin
j <= index[i];
comparing_state <= 3'd5;
end
end
3'd5 : begin
count_copy[i] <= max_so_far[LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
comparing_write_enable <= 1;
comparing_state <= 3'd6;
end
default : begin
comparing_write_enable <= 0;
if (i!=LAST_RESULT) begin
i <= i + 1'd1;
j <= 0;
end else begin
result_valid <= 1;
end
comparing_state <= 3'd1;
end
endcase
end
end
end
end
assign result00 = index[0];
assign result01 = index[1];
assign result02 = index[2];
assign result03 = index[3];
assign count00 = count_copy[0][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
assign count01 = count_copy[1][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
assign count02 = count_copy[2][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
assign count03 = count_copy[3][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
endmodule | 2 |
6,043 | data/full_repos/permissive/115035459/verilog/src/lib/histogram.v | 115,035,459 | histogram.v | v | 515 | 191 | [] | [] | [] | null | line:313: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:7: Cannot find include file: RAM8.v\n`include "RAM8.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/RAM8.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/RAM8.v.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/RAM8.v.sv\n RAM8.v\n RAM8.v.v\n RAM8.v.sv\n obj_dir/RAM8.v\n obj_dir/RAM8.v.v\n obj_dir/RAM8.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:8: Cannot find include file: fifo.v\n`include "fifo.v" \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:9: Cannot find include file: generic.v\n`include "generic.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:22: Define or directive not defined: \'`LOG2_OF_BASE_BLOCK_MEMORY_SIZE\'\n parameter PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + $clog2(DATA_WIDTH) - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:22: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n parameter PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + $clog2(DATA_WIDTH) - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE,\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:24: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST = LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE - LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:25: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter USE_BLOCK_MEMORY = 1\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:26: syntax error, unexpected \')\', expecting \';\'\n) (\n^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:40: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg partial_count_reached = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:41: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg max_count_reached = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:42: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg adding_finished = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:43: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg result_valid = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:44: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output [31:0] error_count\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:77: syntax error, unexpected assign\n assign ram_read_address = { {RAM_ADDRESS_DEPTH-DATA_WIDTH{1\'b0}}, adding_not_comparing ? data_out_from_fifo : j };\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:92: syntax error, unexpected always\n always @(posedge clock) begin\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:414: Unsupported: Ignoring delay on this delayed statement.\n #100; reset <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:415: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:415: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:415: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:416: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:416: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:416: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:417: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:417: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:417: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:418: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:418: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:418: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:419: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:419: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:419: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:420: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:420: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:420: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:421: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:421: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:421: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:422: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:422: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:422: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:423: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:423: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:423: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:424: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:424: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:424: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:426: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:426: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:426: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:427: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:427: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:427: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:428: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:428: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:428: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:429: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:429: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:429: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:430: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h22; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:430: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h22; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:430: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h22; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:431: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:431: syntax error, unexpected \'@\'\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:431: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:432: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:432: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:432: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:433: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:433: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:433: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:434: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:434: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:434: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:435: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:435: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:435: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:436: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:436: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:436: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:437: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:437: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:437: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:438: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:438: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:438: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:439: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:439: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:439: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:440: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:440: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:440: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:441: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:441: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:441: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:442: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:442: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:442: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:443: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:443: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:443: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:444: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:444: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:444: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:445: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:445: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:445: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:446: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:446: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:446: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:447: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:447: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:447: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:448: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:448: syntax error, unexpected \'@\'\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:448: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:451: Unsupported: Ignoring delay on this delayed statement.\n #(4*13);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:453: Unsupported: Ignoring delay on this delayed statement.\n #(4*3);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:455: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:455: syntax error, unexpected \'@\'\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:455: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:456: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:456: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:456: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:457: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:457: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:457: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:458: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:458: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:458: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:459: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:459: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:459: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:460: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:460: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:460: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:461: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:461: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:461: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:462: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:462: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:462: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:463: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:463: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:463: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:464: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:464: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:464: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:465: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:465: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:465: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:466: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:466: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:466: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:467: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:467: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:467: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:468: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:468: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:468: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:469: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:469: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:469: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:470: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:470: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:470: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:471: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:471: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:471: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:472: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:472: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:472: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:473: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:473: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:473: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:474: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:474: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:474: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:475: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:475: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:475: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:476: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:476: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:476: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:477: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:477: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:477: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:478: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:478: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:478: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:479: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:479: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:479: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:480: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:481: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d23; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:481: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d23; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:481: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d23; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:482: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d29; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:482: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d29; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:482: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d29; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:483: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d31; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:483: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d31; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:483: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d31; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:484: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d37; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:484: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d37; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:484: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d37; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:485: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d41; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:485: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d41; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:485: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d41; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:486: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d43; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:486: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d43; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:486: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d43; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:487: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d47; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:487: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d47; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:487: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d47; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:488: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d53; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:488: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d53; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:488: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d53; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:489: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d59; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:489: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d59; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:489: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d59; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:490: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d61; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:490: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d61; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:490: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d61; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:491: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d67; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:491: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d67; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:491: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d67; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:492: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d71; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:492: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d71; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:492: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d71; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:493: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d73; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:493: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d73; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:493: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d73; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:494: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d79; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:494: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d79; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:494: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d79; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:495: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:495: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:495: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:496: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d89; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:496: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d89; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:496: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d89; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:497: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d97; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:497: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d97; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:497: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d97; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:498: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:499: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h84; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:499: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h84; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:499: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h84; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:500: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h85; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:500: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h85; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:500: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h85; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:501: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h86; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:501: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h86; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:501: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h86; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:502: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h87; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:502: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h87; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:502: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h87; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:503: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:504: Unsupported: Ignoring delay on this delayed statement.\n #20; @(posedge result_valid);\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:504: syntax error, unexpected \'@\'\n #20; @(posedge result_valid);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:505: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:506: Unsupported: Ignoring delay on this delayed statement.\n #1000; clear_results <= 1; #4; clear_results <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:506: Unsupported: Ignoring delay on this delayed statement.\n #1000; clear_results <= 1; #4; clear_results <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:507: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:508: Unsupported: Ignoring delay on this delayed statement.\n #100; $finish;\n ^\n%Error: Exiting due to 19 error(s), 249 warning(s)\n' | 6,817 | module | module histogram_original #(
parameter DATA_WIDTH = 4,
parameter LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE = 4
) (
input reset, clock,
input sample,
input clear_results,
input [DATA_WIDTH-1:0] data_in,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count00,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count01,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count02,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count03,
output [DATA_WIDTH-1:0] result00,
output [DATA_WIDTH-1:0] result01,
output [DATA_WIDTH-1:0] result02,
output [DATA_WIDTH-1:0] result03,
output reg max_count_reached = 0,
output reg adding_finished = 0,
output reg result_valid = 0
);
localparam MAX_INDEX = (1<<DATA_WIDTH) - 1;
localparam MAXIMUM_SAMPLE_NUMBER = (1<<LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE) - 1;
localparam LOG2_OF_NUMBER_OF_RESULTS = 2;
localparam LAST_RESULT = (1<<LOG2_OF_NUMBER_OF_RESULTS) - 1;
reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count [MAX_INDEX:0];
reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count_copy [LAST_RESULT:0];
reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] sample_counter = 0;
reg [LAST_RESULT:0] i = 0;
reg [DATA_WIDTH-1:0] j = 0;
reg [DATA_WIDTH-1:0] index [LAST_RESULT:0];
reg clear_count_already_found = 0;
genvar k;
for (k=0; k<=MAX_INDEX; k=k+1) begin : accumulate
always @(posedge clock) begin
if (reset || clear_results) begin
count[k] <= 0;
end else begin
if (max_count_reached) begin
if (clear_count_already_found) begin
if (k==index[i]) begin
count[k] <= 0;
end
end
end else begin
if (sample) begin
if (k==data_in) begin
count[k] <= count[k] + 1'd1;
end
end
end
end
end
end
always @(posedge clock) begin
if (reset || clear_results) begin
sample_counter <= 0;
max_count_reached <= 0;
i <= 0;
j <= 1;
index[0] <= 0;
index[1] <= 0;
index[2] <= 0;
index[3] <= 0;
count_copy[0] <= 0;
count_copy[1] <= 0;
count_copy[2] <= 0;
count_copy[3] <= 0;
clear_count_already_found <= 0;
result_valid <= 0;
end else begin
if (~max_count_reached) begin
if (sample) begin
if (sample_counter<MAXIMUM_SAMPLE_NUMBER) begin
sample_counter <= sample_counter + 1'b1;
end else begin
max_count_reached <= 1;
end
end
end else begin
if (~result_valid) begin
if (clear_count_already_found) begin
count_copy[i] <= count[index[i]];
clear_count_already_found <= 0;
if (i!=LAST_RESULT) begin
i <= i + 1'd1;
j <= 1;
end else begin
result_valid <= 1;
end
end else begin
if (count[index[i]]<count[j]) begin
index[i] <= j;
end
if (j!=MAX_INDEX) begin
j <= j + 1'd1;
end else begin
clear_count_already_found <= 1;
end
end
end
end
end
end
assign result00 = index[0];
assign result01 = index[1];
assign result02 = index[2];
assign result03 = index[3];
assign count00 = count_copy[0];
assign count01 = count_copy[1];
assign count02 = count_copy[2];
assign count03 = count_copy[3];
endmodule | module histogram_original #(
parameter DATA_WIDTH = 4,
parameter LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE = 4
) (
input reset, clock,
input sample,
input clear_results,
input [DATA_WIDTH-1:0] data_in,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count00,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count01,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count02,
output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count03,
output [DATA_WIDTH-1:0] result00,
output [DATA_WIDTH-1:0] result01,
output [DATA_WIDTH-1:0] result02,
output [DATA_WIDTH-1:0] result03,
output reg max_count_reached = 0,
output reg adding_finished = 0,
output reg result_valid = 0
); |
localparam MAX_INDEX = (1<<DATA_WIDTH) - 1;
localparam MAXIMUM_SAMPLE_NUMBER = (1<<LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE) - 1;
localparam LOG2_OF_NUMBER_OF_RESULTS = 2;
localparam LAST_RESULT = (1<<LOG2_OF_NUMBER_OF_RESULTS) - 1;
reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count [MAX_INDEX:0];
reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count_copy [LAST_RESULT:0];
reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] sample_counter = 0;
reg [LAST_RESULT:0] i = 0;
reg [DATA_WIDTH-1:0] j = 0;
reg [DATA_WIDTH-1:0] index [LAST_RESULT:0];
reg clear_count_already_found = 0;
genvar k;
for (k=0; k<=MAX_INDEX; k=k+1) begin : accumulate
always @(posedge clock) begin
if (reset || clear_results) begin
count[k] <= 0;
end else begin
if (max_count_reached) begin
if (clear_count_already_found) begin
if (k==index[i]) begin
count[k] <= 0;
end
end
end else begin
if (sample) begin
if (k==data_in) begin
count[k] <= count[k] + 1'd1;
end
end
end
end
end
end
always @(posedge clock) begin
if (reset || clear_results) begin
sample_counter <= 0;
max_count_reached <= 0;
i <= 0;
j <= 1;
index[0] <= 0;
index[1] <= 0;
index[2] <= 0;
index[3] <= 0;
count_copy[0] <= 0;
count_copy[1] <= 0;
count_copy[2] <= 0;
count_copy[3] <= 0;
clear_count_already_found <= 0;
result_valid <= 0;
end else begin
if (~max_count_reached) begin
if (sample) begin
if (sample_counter<MAXIMUM_SAMPLE_NUMBER) begin
sample_counter <= sample_counter + 1'b1;
end else begin
max_count_reached <= 1;
end
end
end else begin
if (~result_valid) begin
if (clear_count_already_found) begin
count_copy[i] <= count[index[i]];
clear_count_already_found <= 0;
if (i!=LAST_RESULT) begin
i <= i + 1'd1;
j <= 1;
end else begin
result_valid <= 1;
end
end else begin
if (count[index[i]]<count[j]) begin
index[i] <= j;
end
if (j!=MAX_INDEX) begin
j <= j + 1'd1;
end else begin
clear_count_already_found <= 1;
end
end
end
end
end
end
assign result00 = index[0];
assign result01 = index[1];
assign result02 = index[2];
assign result03 = index[3];
assign count00 = count_copy[0];
assign count01 = count_copy[1];
assign count02 = count_copy[2];
assign count03 = count_copy[3];
endmodule | 2 |
6,044 | data/full_repos/permissive/115035459/verilog/src/lib/histogram.v | 115,035,459 | histogram.v | v | 515 | 191 | [] | [] | [] | null | line:313: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:7: Cannot find include file: RAM8.v\n`include "RAM8.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/RAM8.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/RAM8.v.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/RAM8.v.sv\n RAM8.v\n RAM8.v.v\n RAM8.v.sv\n obj_dir/RAM8.v\n obj_dir/RAM8.v.v\n obj_dir/RAM8.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:8: Cannot find include file: fifo.v\n`include "fifo.v" \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:9: Cannot find include file: generic.v\n`include "generic.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:22: Define or directive not defined: \'`LOG2_OF_BASE_BLOCK_MEMORY_SIZE\'\n parameter PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + $clog2(DATA_WIDTH) - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:22: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n parameter PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + $clog2(DATA_WIDTH) - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE,\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:24: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST = LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE - LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:25: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter USE_BLOCK_MEMORY = 1\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:26: syntax error, unexpected \')\', expecting \';\'\n) (\n^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:40: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg partial_count_reached = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:41: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg max_count_reached = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:42: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg adding_finished = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:43: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg result_valid = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:44: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output [31:0] error_count\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:77: syntax error, unexpected assign\n assign ram_read_address = { {RAM_ADDRESS_DEPTH-DATA_WIDTH{1\'b0}}, adding_not_comparing ? data_out_from_fifo : j };\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:92: syntax error, unexpected always\n always @(posedge clock) begin\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:414: Unsupported: Ignoring delay on this delayed statement.\n #100; reset <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:415: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:415: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:415: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:416: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:416: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:416: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:417: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:417: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:417: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:418: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:418: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:418: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:419: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:419: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:419: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:420: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:420: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:420: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:421: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:421: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:421: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:422: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:422: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:422: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:423: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:423: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:423: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:424: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:424: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:424: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:425: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:426: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:426: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:426: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:427: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:427: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:427: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:428: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:428: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:428: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:429: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:429: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:429: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:430: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h22; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:430: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h22; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:430: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h22; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:431: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:431: syntax error, unexpected \'@\'\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:431: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:432: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:432: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:432: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:433: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:433: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:433: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:434: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:434: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:434: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:435: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:435: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:435: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:436: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:436: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:436: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:437: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:437: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:437: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:438: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:438: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:438: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:439: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:439: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:439: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:440: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:440: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:440: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:441: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:441: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:441: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:442: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:442: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:442: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:443: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:443: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:443: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:444: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:444: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:444: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:445: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:445: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:445: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:446: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:446: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:446: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:447: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:447: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:447: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:448: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:448: syntax error, unexpected \'@\'\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:448: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:451: Unsupported: Ignoring delay on this delayed statement.\n #(4*13);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:453: Unsupported: Ignoring delay on this delayed statement.\n #(4*3);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:455: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:455: syntax error, unexpected \'@\'\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:455: Unsupported: Ignoring delay on this delayed statement.\n #80; @(negedge partial_count_reached); #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:456: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:456: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:456: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:457: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:457: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:457: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:458: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:458: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:458: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:459: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:459: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:459: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:460: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:460: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:460: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:461: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:461: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:461: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:462: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:462: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:462: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:463: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:463: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:463: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:464: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:464: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:464: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:465: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:465: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:465: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:466: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:466: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:466: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:467: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:467: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:467: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:468: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:468: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:468: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:469: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:469: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:469: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:470: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:470: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:470: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:471: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:471: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:471: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:472: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:472: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:472: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:473: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:473: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:473: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:474: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:474: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:474: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:475: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:475: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:475: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:476: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:476: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:476: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:477: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:477: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:477: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:478: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:478: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:478: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:479: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:479: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:479: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:480: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:481: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d23; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:481: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d23; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:481: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d23; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:482: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d29; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:482: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d29; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:482: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d29; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:483: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d31; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:483: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d31; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:483: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d31; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:484: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d37; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:484: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d37; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:484: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d37; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:485: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d41; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:485: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d41; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:485: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d41; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:486: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d43; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:486: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d43; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:486: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d43; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:487: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d47; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:487: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d47; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:487: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d47; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:488: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d53; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:488: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d53; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:488: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d53; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:489: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d59; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:489: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d59; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:489: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d59; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:490: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d61; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:490: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d61; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:490: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d61; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:491: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d67; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:491: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d67; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:491: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d67; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:492: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d71; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:492: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d71; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:492: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d71; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:493: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d73; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:493: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d73; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:493: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d73; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:494: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d79; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:494: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d79; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:494: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d79; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:495: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:495: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:495: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d83; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:496: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d89; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:496: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d89; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:496: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d89; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:497: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d97; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:497: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d97; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:497: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'d97; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:498: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:499: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h84; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:499: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h84; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:499: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h84; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:500: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h85; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:500: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h85; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:500: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h85; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:501: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h86; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:501: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h86; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:501: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h86; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:502: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h87; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:502: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h87; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:502: Unsupported: Ignoring delay on this delayed statement.\n #20; data_in <= 8\'h87; #4; sample <= 1; #4; sample <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:503: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:504: Unsupported: Ignoring delay on this delayed statement.\n #20; @(posedge result_valid);\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:504: syntax error, unexpected \'@\'\n #20; @(posedge result_valid);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:505: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:506: Unsupported: Ignoring delay on this delayed statement.\n #1000; clear_results <= 1; #4; clear_results <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:506: Unsupported: Ignoring delay on this delayed statement.\n #1000; clear_results <= 1; #4; clear_results <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:507: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:508: Unsupported: Ignoring delay on this delayed statement.\n #100; $finish;\n ^\n%Error: Exiting due to 19 error(s), 249 warning(s)\n' | 6,817 | module | module histogram_tb;
localparam DATA_WIDTH = 8;
localparam LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE = 4;
wire clock;
reg reset = 1;
reg clear_results = 0;
reg [DATA_WIDTH-1:0] data_in = 0;
reg sample = 0;
wire [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count00;
wire [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count01;
wire [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count02;
wire [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count03;
wire [DATA_WIDTH-1:0] result00;
wire [DATA_WIDTH-1:0] result01;
wire [DATA_WIDTH-1:0] result02;
wire [DATA_WIDTH-1:0] result03;
wire partial_count_reached;
wire max_count_reached;
wire adding_finished;
wire result_valid;
wire [31:0] histogram_error_count;
if (0) begin
histogram_original #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE)) h1n1 (
.clock(clock), .reset(reset), .clear_results(clear_results), .data_in(data_in), .sample(sample),
.result00(result00), .result01(result01), .result02(result02), .result03(result03),
.count00(count00), .count01(count01), .count02(count02), .count03(count03),
.max_count_reached(max_count_reached), .adding_finished(adding_finished), .result_valid(result_valid));
end else begin
histogram #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE), .USE_BLOCK_MEMORY(0), .TESTBENCH(1)) h1n1 (
.clock(clock), .reset(reset), .clear_results(clear_results), .data_in(data_in), .sample(sample),
.result00(result00), .result01(result01), .result02(result02), .result03(result03),
.count00(count00), .count01(count01), .count02(count02), .count03(count03),
.partial_count_reached(partial_count_reached), .max_count_reached(max_count_reached), .adding_finished(adding_finished), .result_valid(result_valid), .error_count(histogram_error_count));
end
initial begin
#100; reset <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h22; #4; sample <= 1; #4; sample <= 0;
#80; @(negedge partial_count_reached); #80;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h06; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h06; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h06; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h06; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h06; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h06; #4; sample <= 1; #4; sample <= 0;
#80; @(negedge partial_count_reached); #80;
sample <= 1;
data_in <= 8'h13;
#(4*13);
data_in <= 8'h93;
#(4*3);
sample <= 0;
#80; @(negedge partial_count_reached); #80;
#20; data_in <= 8'h55; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'haa; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h99; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h44; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h11; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h11; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h51; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h83; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h55; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'haa; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h38; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h44; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h51; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h38; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h83; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h55; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'haa; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h99; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h44; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h11; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h99; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h51; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h38; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h83; #4; sample <= 1; #4; sample <= 0;
#20;
#20; data_in <= 8'd23; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd29; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd31; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd37; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd41; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd43; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd47; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd53; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd59; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd61; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd67; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd71; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd73; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd79; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd83; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd89; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd97; #4; sample <= 1; #4; sample <= 0;
#20;
#20; data_in <= 8'h84; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h85; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h86; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h87; #4; sample <= 1; #4; sample <= 0;
#20;
#20; @(posedge result_valid);
#20;
#1000; clear_results <= 1; #4; clear_results <= 0;
#1000;
#100; $finish;
end
clock #(.FREQUENCY_OF_CLOCK_HZ(250000000)) c (.clock(clock));
endmodule | module histogram_tb; |
localparam DATA_WIDTH = 8;
localparam LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE = 4;
wire clock;
reg reset = 1;
reg clear_results = 0;
reg [DATA_WIDTH-1:0] data_in = 0;
reg sample = 0;
wire [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count00;
wire [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count01;
wire [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count02;
wire [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count03;
wire [DATA_WIDTH-1:0] result00;
wire [DATA_WIDTH-1:0] result01;
wire [DATA_WIDTH-1:0] result02;
wire [DATA_WIDTH-1:0] result03;
wire partial_count_reached;
wire max_count_reached;
wire adding_finished;
wire result_valid;
wire [31:0] histogram_error_count;
if (0) begin
histogram_original #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE)) h1n1 (
.clock(clock), .reset(reset), .clear_results(clear_results), .data_in(data_in), .sample(sample),
.result00(result00), .result01(result01), .result02(result02), .result03(result03),
.count00(count00), .count01(count01), .count02(count02), .count03(count03),
.max_count_reached(max_count_reached), .adding_finished(adding_finished), .result_valid(result_valid));
end else begin
histogram #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE), .USE_BLOCK_MEMORY(0), .TESTBENCH(1)) h1n1 (
.clock(clock), .reset(reset), .clear_results(clear_results), .data_in(data_in), .sample(sample),
.result00(result00), .result01(result01), .result02(result02), .result03(result03),
.count00(count00), .count01(count01), .count02(count02), .count03(count03),
.partial_count_reached(partial_count_reached), .max_count_reached(max_count_reached), .adding_finished(adding_finished), .result_valid(result_valid), .error_count(histogram_error_count));
end
initial begin
#100; reset <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h15; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h22; #4; sample <= 1; #4; sample <= 0;
#80; @(negedge partial_count_reached); #80;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h10; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h06; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h06; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h06; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h06; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h06; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h06; #4; sample <= 1; #4; sample <= 0;
#80; @(negedge partial_count_reached); #80;
sample <= 1;
data_in <= 8'h13;
#(4*13);
data_in <= 8'h93;
#(4*3);
sample <= 0;
#80; @(negedge partial_count_reached); #80;
#20; data_in <= 8'h55; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'haa; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h99; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h44; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h11; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h11; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h51; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h83; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h55; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'haa; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h38; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h44; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h51; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h38; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h83; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h55; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'haa; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h99; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h44; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h11; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h99; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h51; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h38; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h83; #4; sample <= 1; #4; sample <= 0;
#20;
#20; data_in <= 8'd23; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd29; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd31; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd37; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd41; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd43; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd47; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd53; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd59; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd61; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd67; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd71; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd73; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd79; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd83; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd89; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'd97; #4; sample <= 1; #4; sample <= 0;
#20;
#20; data_in <= 8'h84; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h85; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h86; #4; sample <= 1; #4; sample <= 0;
#20; data_in <= 8'h87; #4; sample <= 1; #4; sample <= 0;
#20;
#20; @(posedge result_valid);
#20;
#1000; clear_results <= 1; #4; clear_results <= 0;
#1000;
#100; $finish;
end
clock #(.FREQUENCY_OF_CLOCK_HZ(250000000)) c (.clock(clock));
endmodule | 2 |
6,046 | data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v | 115,035,459 | plldcm.v | v | 400 | 381 | [] | [] | [] | [(8, 22), (26, 97), (100, 171), (180, 241), (249, 296), (301, 355), (358, 381), (383, 396)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:375: Cell has missing pin: \'alt_clockout\'\n simpledcm_SP #(.MULTIPLY(DCMMULTIPLY), .DIVIDE(DCMDIVIDE), .PERIOD(DCMPERIOD)) mydcm (\n ^~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:100: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'dummy_dcm_diff_input\'\nmodule dummy_dcm_diff_input #(\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'simplepll_ADV\'\nmodule simplepll_ADV #(\n ^~~~~~~~~~~~~\n : ... Top module \'simplepll_BASE\'\nmodule simplepll_BASE #(\n ^~~~~~~~~~~~~~\n : ... Top module \'plldcm\'\nmodule plldcm #(parameter OVERALL_DIVIDE=1, PLLMULTIPLY=1, PLLDIVIDE=1, PLLPERIOD=10.0, DCMMULTIPLY=1, DCMDIVIDE=1, DCMPERIOD="10.0") (\n ^~~~~~\n : ... Top module \'clock_select\'\nmodule clock_select #(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:319: Cannot find file containing module: \'DCM_SP\'\n DCM_SP #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.sv\n DCM_SP\n DCM_SP.v\n DCM_SP.sv\n obj_dir/DCM_SP\n obj_dir/DCM_SP.v\n obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:256: Cannot find file containing module: \'DCM_CLKGEN\'\n DCM_CLKGEN #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:39: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:393: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_0s (.I0(clock[0]), .I1(clock[1]), .S(select[0]), .O(clock_0s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:394: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_1s (.I0(clock[2]), .I1(clock[3]), .S(select[0]), .O(clock_1s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:395: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_sx (.I0(clock_0s), .I1(clock_1s), .S(select[1]), .O(clock_out));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:200: Cannot find file containing module: \'PLL_BASE\'\n PLL_BASE #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:113: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:18: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS mybuf_raw1 (.I(clock_p), .IB(clock_n), .O(clock_raw1));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:21: Cannot find file containing module: \'BUFG\'\n BUFG mybuf_raw2 (.I(clock_raw2), .O(clock_out));\n ^~~~\n%Error: Exiting due to 10 error(s), 2 warning(s)\n' | 6,819 | module | module dummy_dcm_diff_input #(
parameter MULT_DIV = 10,
parameter PERIOD = 10.0
) (
input clock_p, clock_n,
input reset,
output clock_out,
output clock_locked
);
wire clock_raw1;
IBUFGDS mybuf_raw1 (.I(clock_p), .IB(clock_n), .O(clock_raw1));
wire clock_raw2;
simpledcm_CLKGEN #(.MULTIPLY(MULT_DIV), .DIVIDE(MULT_DIV), .PERIOD(PERIOD)) mydcm (.clockin(clock_raw1), .reset(reset), .clockout(clock_raw2), .clockout180(), .locked(clock_locked));
BUFG mybuf_raw2 (.I(clock_raw2), .O(clock_out));
endmodule | module dummy_dcm_diff_input #(
parameter MULT_DIV = 10,
parameter PERIOD = 10.0
) (
input clock_p, clock_n,
input reset,
output clock_out,
output clock_locked
); |
wire clock_raw1;
IBUFGDS mybuf_raw1 (.I(clock_p), .IB(clock_n), .O(clock_raw1));
wire clock_raw2;
simpledcm_CLKGEN #(.MULTIPLY(MULT_DIV), .DIVIDE(MULT_DIV), .PERIOD(PERIOD)) mydcm (.clockin(clock_raw1), .reset(reset), .clockout(clock_raw2), .clockout180(), .locked(clock_locked));
BUFG mybuf_raw2 (.I(clock_raw2), .O(clock_out));
endmodule | 2 |
6,047 | data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v | 115,035,459 | plldcm.v | v | 400 | 381 | [] | [] | [] | [(8, 22), (26, 97), (100, 171), (180, 241), (249, 296), (301, 355), (358, 381), (383, 396)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:375: Cell has missing pin: \'alt_clockout\'\n simpledcm_SP #(.MULTIPLY(DCMMULTIPLY), .DIVIDE(DCMDIVIDE), .PERIOD(DCMPERIOD)) mydcm (\n ^~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:100: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'dummy_dcm_diff_input\'\nmodule dummy_dcm_diff_input #(\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'simplepll_ADV\'\nmodule simplepll_ADV #(\n ^~~~~~~~~~~~~\n : ... Top module \'simplepll_BASE\'\nmodule simplepll_BASE #(\n ^~~~~~~~~~~~~~\n : ... Top module \'plldcm\'\nmodule plldcm #(parameter OVERALL_DIVIDE=1, PLLMULTIPLY=1, PLLDIVIDE=1, PLLPERIOD=10.0, DCMMULTIPLY=1, DCMDIVIDE=1, DCMPERIOD="10.0") (\n ^~~~~~\n : ... Top module \'clock_select\'\nmodule clock_select #(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:319: Cannot find file containing module: \'DCM_SP\'\n DCM_SP #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.sv\n DCM_SP\n DCM_SP.v\n DCM_SP.sv\n obj_dir/DCM_SP\n obj_dir/DCM_SP.v\n obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:256: Cannot find file containing module: \'DCM_CLKGEN\'\n DCM_CLKGEN #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:39: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:393: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_0s (.I0(clock[0]), .I1(clock[1]), .S(select[0]), .O(clock_0s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:394: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_1s (.I0(clock[2]), .I1(clock[3]), .S(select[0]), .O(clock_1s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:395: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_sx (.I0(clock_0s), .I1(clock_1s), .S(select[1]), .O(clock_out));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:200: Cannot find file containing module: \'PLL_BASE\'\n PLL_BASE #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:113: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:18: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS mybuf_raw1 (.I(clock_p), .IB(clock_n), .O(clock_raw1));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:21: Cannot find file containing module: \'BUFG\'\n BUFG mybuf_raw2 (.I(clock_raw2), .O(clock_out));\n ^~~~\n%Error: Exiting due to 10 error(s), 2 warning(s)\n' | 6,819 | module | module simplepll_ADV_2DCM #(
parameter OVERALL_DIVIDE = 1,
parameter MULTIPLY = 4,
parameter DIVIDE = 1,
parameter PERIOD = 10.0,
parameter COMPENSATION = "PLL2DCM"
) (
input clockin,
input reset,
output clockout,
output locked
);
wire fbdcm;
PLL_ADV #(
.SIM_DEVICE("SPARTAN6"),
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(PERIOD),
.CLKIN2_PERIOD(PERIOD),
.DIVCLK_DIVIDE(OVERALL_DIVIDE),
.CLKFBOUT_MULT(MULTIPLY),
.CLKOUT0_DIVIDE(DIVIDE),
.CLKOUT1_DIVIDE(1),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.COMPENSATION(COMPENSATION),
.REF_JITTER(0.100)
) pll_adv_inst (
.RST(reset),
.LOCKED(locked),
.CLKFBIN(fbdcm),
.CLKFBOUT(),
.CLKIN1(clockin),
.CLKOUT0(),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBDCM(fbdcm),
.CLKOUTDCM0(clockout),
.CLKOUTDCM1(),
.CLKOUTDCM2(),
.CLKOUTDCM3(),
.CLKOUTDCM4(),
.CLKOUTDCM5(),
.DO(),
.DRDY(),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(5'b00000),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'h0000),
.DWE(1'b0),
.REL(1'b0)
);
endmodule | module simplepll_ADV_2DCM #(
parameter OVERALL_DIVIDE = 1,
parameter MULTIPLY = 4,
parameter DIVIDE = 1,
parameter PERIOD = 10.0,
parameter COMPENSATION = "PLL2DCM"
) (
input clockin,
input reset,
output clockout,
output locked
); |
wire fbdcm;
PLL_ADV #(
.SIM_DEVICE("SPARTAN6"),
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(PERIOD),
.CLKIN2_PERIOD(PERIOD),
.DIVCLK_DIVIDE(OVERALL_DIVIDE),
.CLKFBOUT_MULT(MULTIPLY),
.CLKOUT0_DIVIDE(DIVIDE),
.CLKOUT1_DIVIDE(1),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.COMPENSATION(COMPENSATION),
.REF_JITTER(0.100)
) pll_adv_inst (
.RST(reset),
.LOCKED(locked),
.CLKFBIN(fbdcm),
.CLKFBOUT(),
.CLKIN1(clockin),
.CLKOUT0(),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBDCM(fbdcm),
.CLKOUTDCM0(clockout),
.CLKOUTDCM1(),
.CLKOUTDCM2(),
.CLKOUTDCM3(),
.CLKOUTDCM4(),
.CLKOUTDCM5(),
.DO(),
.DRDY(),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(5'b00000),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'h0000),
.DWE(1'b0),
.REL(1'b0)
);
endmodule | 2 |
6,048 | data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v | 115,035,459 | plldcm.v | v | 400 | 381 | [] | [] | [] | [(8, 22), (26, 97), (100, 171), (180, 241), (249, 296), (301, 355), (358, 381), (383, 396)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:375: Cell has missing pin: \'alt_clockout\'\n simpledcm_SP #(.MULTIPLY(DCMMULTIPLY), .DIVIDE(DCMDIVIDE), .PERIOD(DCMPERIOD)) mydcm (\n ^~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:100: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'dummy_dcm_diff_input\'\nmodule dummy_dcm_diff_input #(\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'simplepll_ADV\'\nmodule simplepll_ADV #(\n ^~~~~~~~~~~~~\n : ... Top module \'simplepll_BASE\'\nmodule simplepll_BASE #(\n ^~~~~~~~~~~~~~\n : ... Top module \'plldcm\'\nmodule plldcm #(parameter OVERALL_DIVIDE=1, PLLMULTIPLY=1, PLLDIVIDE=1, PLLPERIOD=10.0, DCMMULTIPLY=1, DCMDIVIDE=1, DCMPERIOD="10.0") (\n ^~~~~~\n : ... Top module \'clock_select\'\nmodule clock_select #(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:319: Cannot find file containing module: \'DCM_SP\'\n DCM_SP #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.sv\n DCM_SP\n DCM_SP.v\n DCM_SP.sv\n obj_dir/DCM_SP\n obj_dir/DCM_SP.v\n obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:256: Cannot find file containing module: \'DCM_CLKGEN\'\n DCM_CLKGEN #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:39: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:393: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_0s (.I0(clock[0]), .I1(clock[1]), .S(select[0]), .O(clock_0s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:394: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_1s (.I0(clock[2]), .I1(clock[3]), .S(select[0]), .O(clock_1s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:395: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_sx (.I0(clock_0s), .I1(clock_1s), .S(select[1]), .O(clock_out));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:200: Cannot find file containing module: \'PLL_BASE\'\n PLL_BASE #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:113: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:18: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS mybuf_raw1 (.I(clock_p), .IB(clock_n), .O(clock_raw1));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:21: Cannot find file containing module: \'BUFG\'\n BUFG mybuf_raw2 (.I(clock_raw2), .O(clock_out));\n ^~~~\n%Error: Exiting due to 10 error(s), 2 warning(s)\n' | 6,819 | module | module simplepll_ADV #(
parameter OVERALL_DIVIDE = 1,
parameter MULTIPLY = 4,
parameter DIVIDE = 1,
parameter PERIOD = 10.0,
parameter COMPENSATION = "INTERNAL"
) (
input clockin,
input reset,
output clockout,
output locked
);
wire fb;
PLL_ADV #(
.SIM_DEVICE("SPARTAN6"),
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(PERIOD),
.CLKIN2_PERIOD(PERIOD),
.DIVCLK_DIVIDE(OVERALL_DIVIDE),
.CLKFBOUT_MULT(MULTIPLY),
.CLKOUT0_DIVIDE(DIVIDE),
.CLKOUT1_DIVIDE(1),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.COMPENSATION(COMPENSATION),
.REF_JITTER(0.100)
) pll_adv_inst (
.RST(reset),
.LOCKED(locked),
.CLKFBIN(fb),
.CLKFBOUT(fb),
.CLKIN1(clockin),
.CLKOUT0(clockout),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBDCM(),
.CLKOUTDCM0(),
.CLKOUTDCM1(),
.CLKOUTDCM2(),
.CLKOUTDCM3(),
.CLKOUTDCM4(),
.CLKOUTDCM5(),
.DO(),
.DRDY(),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(5'b00000),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'h0000),
.DWE(1'b0),
.REL(1'b0)
);
endmodule | module simplepll_ADV #(
parameter OVERALL_DIVIDE = 1,
parameter MULTIPLY = 4,
parameter DIVIDE = 1,
parameter PERIOD = 10.0,
parameter COMPENSATION = "INTERNAL"
) (
input clockin,
input reset,
output clockout,
output locked
); |
wire fb;
PLL_ADV #(
.SIM_DEVICE("SPARTAN6"),
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(PERIOD),
.CLKIN2_PERIOD(PERIOD),
.DIVCLK_DIVIDE(OVERALL_DIVIDE),
.CLKFBOUT_MULT(MULTIPLY),
.CLKOUT0_DIVIDE(DIVIDE),
.CLKOUT1_DIVIDE(1),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.COMPENSATION(COMPENSATION),
.REF_JITTER(0.100)
) pll_adv_inst (
.RST(reset),
.LOCKED(locked),
.CLKFBIN(fb),
.CLKFBOUT(fb),
.CLKIN1(clockin),
.CLKOUT0(clockout),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBDCM(),
.CLKOUTDCM0(),
.CLKOUTDCM1(),
.CLKOUTDCM2(),
.CLKOUTDCM3(),
.CLKOUTDCM4(),
.CLKOUTDCM5(),
.DO(),
.DRDY(),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(5'b00000),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'h0000),
.DWE(1'b0),
.REL(1'b0)
);
endmodule | 2 |
6,049 | data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v | 115,035,459 | plldcm.v | v | 400 | 381 | [] | [] | [] | [(8, 22), (26, 97), (100, 171), (180, 241), (249, 296), (301, 355), (358, 381), (383, 396)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:375: Cell has missing pin: \'alt_clockout\'\n simpledcm_SP #(.MULTIPLY(DCMMULTIPLY), .DIVIDE(DCMDIVIDE), .PERIOD(DCMPERIOD)) mydcm (\n ^~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:100: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'dummy_dcm_diff_input\'\nmodule dummy_dcm_diff_input #(\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'simplepll_ADV\'\nmodule simplepll_ADV #(\n ^~~~~~~~~~~~~\n : ... Top module \'simplepll_BASE\'\nmodule simplepll_BASE #(\n ^~~~~~~~~~~~~~\n : ... Top module \'plldcm\'\nmodule plldcm #(parameter OVERALL_DIVIDE=1, PLLMULTIPLY=1, PLLDIVIDE=1, PLLPERIOD=10.0, DCMMULTIPLY=1, DCMDIVIDE=1, DCMPERIOD="10.0") (\n ^~~~~~\n : ... Top module \'clock_select\'\nmodule clock_select #(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:319: Cannot find file containing module: \'DCM_SP\'\n DCM_SP #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.sv\n DCM_SP\n DCM_SP.v\n DCM_SP.sv\n obj_dir/DCM_SP\n obj_dir/DCM_SP.v\n obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:256: Cannot find file containing module: \'DCM_CLKGEN\'\n DCM_CLKGEN #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:39: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:393: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_0s (.I0(clock[0]), .I1(clock[1]), .S(select[0]), .O(clock_0s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:394: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_1s (.I0(clock[2]), .I1(clock[3]), .S(select[0]), .O(clock_1s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:395: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_sx (.I0(clock_0s), .I1(clock_1s), .S(select[1]), .O(clock_out));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:200: Cannot find file containing module: \'PLL_BASE\'\n PLL_BASE #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:113: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:18: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS mybuf_raw1 (.I(clock_p), .IB(clock_n), .O(clock_raw1));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:21: Cannot find file containing module: \'BUFG\'\n BUFG mybuf_raw2 (.I(clock_raw2), .O(clock_out));\n ^~~~\n%Error: Exiting due to 10 error(s), 2 warning(s)\n' | 6,819 | module | module simplepll_BASE #(
parameter
PERIOD=10.0,
OVERALL_DIVIDE=1,
MULTIPLY=4,
DIVIDE0=1, DIVIDE1=2, DIVIDE2=4, DIVIDE3=8, DIVIDE4=16, DIVIDE5=32,
PHASE0=0.0, PHASE1=0.0, PHASE2=0.0, PHASE3=0.0, PHASE4=0.0, PHASE5=0.0,
COMPENSATION="SYSTEM_SYNCHRONOUS"
) (
input clockin,
input reset,
output clock0out,
output clock1out,
output clock2out,
output clock3out,
output clock4out,
output clock5out,
output locked
);
wire fb;
PLL_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(MULTIPLY),
.CLKFBOUT_PHASE(0.0),
.CLKIN_PERIOD(PERIOD),
.CLKOUT0_DIVIDE(DIVIDE0),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(PHASE0),
.CLKOUT1_DIVIDE(DIVIDE1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(PHASE1),
.CLKOUT2_DIVIDE(DIVIDE2),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(PHASE2),
.CLKOUT3_DIVIDE(DIVIDE3),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(PHASE3),
.CLKOUT4_DIVIDE(DIVIDE4),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(PHASE4),
.CLKOUT5_DIVIDE(DIVIDE5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(PHASE5),
.COMPENSATION(COMPENSATION),
.DIVCLK_DIVIDE(OVERALL_DIVIDE),
.REF_JITTER(0.100)
) PLL_BASE_inst (
.CLKFBOUT(fb),
.CLKOUT0(clock0out),
.CLKOUT1(clock1out),
.CLKOUT2(clock2out),
.CLKOUT3(clock3out),
.CLKOUT4(clock4out),
.CLKOUT5(clock5out),
.LOCKED(locked),
.CLKFBIN(fb),
.CLKIN(clockin),
.RST(reset)
);
endmodule | module simplepll_BASE #(
parameter
PERIOD=10.0,
OVERALL_DIVIDE=1,
MULTIPLY=4,
DIVIDE0=1, DIVIDE1=2, DIVIDE2=4, DIVIDE3=8, DIVIDE4=16, DIVIDE5=32,
PHASE0=0.0, PHASE1=0.0, PHASE2=0.0, PHASE3=0.0, PHASE4=0.0, PHASE5=0.0,
COMPENSATION="SYSTEM_SYNCHRONOUS"
) (
input clockin,
input reset,
output clock0out,
output clock1out,
output clock2out,
output clock3out,
output clock4out,
output clock5out,
output locked
); |
wire fb;
PLL_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(MULTIPLY),
.CLKFBOUT_PHASE(0.0),
.CLKIN_PERIOD(PERIOD),
.CLKOUT0_DIVIDE(DIVIDE0),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(PHASE0),
.CLKOUT1_DIVIDE(DIVIDE1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(PHASE1),
.CLKOUT2_DIVIDE(DIVIDE2),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(PHASE2),
.CLKOUT3_DIVIDE(DIVIDE3),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(PHASE3),
.CLKOUT4_DIVIDE(DIVIDE4),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(PHASE4),
.CLKOUT5_DIVIDE(DIVIDE5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(PHASE5),
.COMPENSATION(COMPENSATION),
.DIVCLK_DIVIDE(OVERALL_DIVIDE),
.REF_JITTER(0.100)
) PLL_BASE_inst (
.CLKFBOUT(fb),
.CLKOUT0(clock0out),
.CLKOUT1(clock1out),
.CLKOUT2(clock2out),
.CLKOUT3(clock3out),
.CLKOUT4(clock4out),
.CLKOUT5(clock5out),
.LOCKED(locked),
.CLKFBIN(fb),
.CLKIN(clockin),
.RST(reset)
);
endmodule | 2 |
6,050 | data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v | 115,035,459 | plldcm.v | v | 400 | 381 | [] | [] | [] | [(8, 22), (26, 97), (100, 171), (180, 241), (249, 296), (301, 355), (358, 381), (383, 396)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:375: Cell has missing pin: \'alt_clockout\'\n simpledcm_SP #(.MULTIPLY(DCMMULTIPLY), .DIVIDE(DCMDIVIDE), .PERIOD(DCMPERIOD)) mydcm (\n ^~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:100: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'dummy_dcm_diff_input\'\nmodule dummy_dcm_diff_input #(\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'simplepll_ADV\'\nmodule simplepll_ADV #(\n ^~~~~~~~~~~~~\n : ... Top module \'simplepll_BASE\'\nmodule simplepll_BASE #(\n ^~~~~~~~~~~~~~\n : ... Top module \'plldcm\'\nmodule plldcm #(parameter OVERALL_DIVIDE=1, PLLMULTIPLY=1, PLLDIVIDE=1, PLLPERIOD=10.0, DCMMULTIPLY=1, DCMDIVIDE=1, DCMPERIOD="10.0") (\n ^~~~~~\n : ... Top module \'clock_select\'\nmodule clock_select #(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:319: Cannot find file containing module: \'DCM_SP\'\n DCM_SP #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.sv\n DCM_SP\n DCM_SP.v\n DCM_SP.sv\n obj_dir/DCM_SP\n obj_dir/DCM_SP.v\n obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:256: Cannot find file containing module: \'DCM_CLKGEN\'\n DCM_CLKGEN #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:39: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:393: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_0s (.I0(clock[0]), .I1(clock[1]), .S(select[0]), .O(clock_0s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:394: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_1s (.I0(clock[2]), .I1(clock[3]), .S(select[0]), .O(clock_1s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:395: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_sx (.I0(clock_0s), .I1(clock_1s), .S(select[1]), .O(clock_out));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:200: Cannot find file containing module: \'PLL_BASE\'\n PLL_BASE #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:113: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:18: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS mybuf_raw1 (.I(clock_p), .IB(clock_n), .O(clock_raw1));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:21: Cannot find file containing module: \'BUFG\'\n BUFG mybuf_raw2 (.I(clock_raw2), .O(clock_out));\n ^~~~\n%Error: Exiting due to 10 error(s), 2 warning(s)\n' | 6,819 | module | module simpledcm_CLKGEN #(parameter MULTIPLY=4, DIVIDE=1, PERIOD="10.0") (
input clockin,
input reset,
output clockout,
output clockout180,
output locked
);
DCM_CLKGEN #(
.CLKFXDV_DIVIDE(2),
.CLKFX_DIVIDE(DIVIDE),
.CLKFX_MD_MAX(0.0),
.CLKFX_MULTIPLY(MULTIPLY),
.CLKIN_PERIOD(PERIOD),
.STARTUP_WAIT("FALSE")
)
DCM_CLKGEN_inst (
.CLKFX(clockout),
.CLKFX180(clockout180),
.CLKFXDV(),
.LOCKED(locked),
.PROGDONE(),
.STATUS(),
.CLKIN(clockin),
.FREEZEDCM(1'b0),
.PROGCLK(1'b0),
.PROGDATA(1'b0),
.PROGEN(1'b0),
.RST(reset)
);
endmodule | module simpledcm_CLKGEN #(parameter MULTIPLY=4, DIVIDE=1, PERIOD="10.0") (
input clockin,
input reset,
output clockout,
output clockout180,
output locked
); |
DCM_CLKGEN #(
.CLKFXDV_DIVIDE(2),
.CLKFX_DIVIDE(DIVIDE),
.CLKFX_MD_MAX(0.0),
.CLKFX_MULTIPLY(MULTIPLY),
.CLKIN_PERIOD(PERIOD),
.STARTUP_WAIT("FALSE")
)
DCM_CLKGEN_inst (
.CLKFX(clockout),
.CLKFX180(clockout180),
.CLKFXDV(),
.LOCKED(locked),
.PROGDONE(),
.STATUS(),
.CLKIN(clockin),
.FREEZEDCM(1'b0),
.PROGCLK(1'b0),
.PROGDATA(1'b0),
.PROGEN(1'b0),
.RST(reset)
);
endmodule | 2 |
6,051 | data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v | 115,035,459 | plldcm.v | v | 400 | 381 | [] | [] | [] | [(8, 22), (26, 97), (100, 171), (180, 241), (249, 296), (301, 355), (358, 381), (383, 396)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:375: Cell has missing pin: \'alt_clockout\'\n simpledcm_SP #(.MULTIPLY(DCMMULTIPLY), .DIVIDE(DCMDIVIDE), .PERIOD(DCMPERIOD)) mydcm (\n ^~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:100: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'dummy_dcm_diff_input\'\nmodule dummy_dcm_diff_input #(\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'simplepll_ADV\'\nmodule simplepll_ADV #(\n ^~~~~~~~~~~~~\n : ... Top module \'simplepll_BASE\'\nmodule simplepll_BASE #(\n ^~~~~~~~~~~~~~\n : ... Top module \'plldcm\'\nmodule plldcm #(parameter OVERALL_DIVIDE=1, PLLMULTIPLY=1, PLLDIVIDE=1, PLLPERIOD=10.0, DCMMULTIPLY=1, DCMDIVIDE=1, DCMPERIOD="10.0") (\n ^~~~~~\n : ... Top module \'clock_select\'\nmodule clock_select #(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:319: Cannot find file containing module: \'DCM_SP\'\n DCM_SP #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.sv\n DCM_SP\n DCM_SP.v\n DCM_SP.sv\n obj_dir/DCM_SP\n obj_dir/DCM_SP.v\n obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:256: Cannot find file containing module: \'DCM_CLKGEN\'\n DCM_CLKGEN #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:39: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:393: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_0s (.I0(clock[0]), .I1(clock[1]), .S(select[0]), .O(clock_0s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:394: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_1s (.I0(clock[2]), .I1(clock[3]), .S(select[0]), .O(clock_1s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:395: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_sx (.I0(clock_0s), .I1(clock_1s), .S(select[1]), .O(clock_out));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:200: Cannot find file containing module: \'PLL_BASE\'\n PLL_BASE #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:113: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:18: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS mybuf_raw1 (.I(clock_p), .IB(clock_n), .O(clock_raw1));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:21: Cannot find file containing module: \'BUFG\'\n BUFG mybuf_raw2 (.I(clock_raw2), .O(clock_out));\n ^~~~\n%Error: Exiting due to 10 error(s), 2 warning(s)\n' | 6,819 | module | module simpledcm_SP #(
parameter ALT_CLOCKOUT_DIVIDE=2.0,
parameter MULTIPLY=4,
parameter DIVIDE=1,
parameter PERIOD=10.0,
parameter CLKIN_DIVIDE_BY_2 = "FALSE"
) (
input clockin,
input reset,
output clockout,
output clockout180,
output alt_clockout,
output locked
);
wire fb;
DCM_SP #(
.CLKDV_DIVIDE(ALT_CLOCKOUT_DIVIDE),
.CLKFX_DIVIDE(DIVIDE),
.CLKFX_MULTIPLY(MULTIPLY),
.CLKIN_DIVIDE_BY_2(CLKIN_DIVIDE_BY_2),
.CLKIN_PERIOD(PERIOD),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
) DCM_SP_inst (
.CLK0(fb),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLKDV(alt_clockout),
.CLKFX(clockout),
.CLKFX180(clockout180),
.LOCKED(locked),
.PSDONE(),
.STATUS(),
.CLKFB(fb),
.CLKIN(clockin),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.DSSEN(1'b0),
.RST(reset)
);
endmodule | module simpledcm_SP #(
parameter ALT_CLOCKOUT_DIVIDE=2.0,
parameter MULTIPLY=4,
parameter DIVIDE=1,
parameter PERIOD=10.0,
parameter CLKIN_DIVIDE_BY_2 = "FALSE"
) (
input clockin,
input reset,
output clockout,
output clockout180,
output alt_clockout,
output locked
); |
wire fb;
DCM_SP #(
.CLKDV_DIVIDE(ALT_CLOCKOUT_DIVIDE),
.CLKFX_DIVIDE(DIVIDE),
.CLKFX_MULTIPLY(MULTIPLY),
.CLKIN_DIVIDE_BY_2(CLKIN_DIVIDE_BY_2),
.CLKIN_PERIOD(PERIOD),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
) DCM_SP_inst (
.CLK0(fb),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLKDV(alt_clockout),
.CLKFX(clockout),
.CLKFX180(clockout180),
.LOCKED(locked),
.PSDONE(),
.STATUS(),
.CLKFB(fb),
.CLKIN(clockin),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.DSSEN(1'b0),
.RST(reset)
);
endmodule | 2 |
6,052 | data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v | 115,035,459 | plldcm.v | v | 400 | 381 | [] | [] | [] | [(8, 22), (26, 97), (100, 171), (180, 241), (249, 296), (301, 355), (358, 381), (383, 396)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:375: Cell has missing pin: \'alt_clockout\'\n simpledcm_SP #(.MULTIPLY(DCMMULTIPLY), .DIVIDE(DCMDIVIDE), .PERIOD(DCMPERIOD)) mydcm (\n ^~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:100: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'dummy_dcm_diff_input\'\nmodule dummy_dcm_diff_input #(\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'simplepll_ADV\'\nmodule simplepll_ADV #(\n ^~~~~~~~~~~~~\n : ... Top module \'simplepll_BASE\'\nmodule simplepll_BASE #(\n ^~~~~~~~~~~~~~\n : ... Top module \'plldcm\'\nmodule plldcm #(parameter OVERALL_DIVIDE=1, PLLMULTIPLY=1, PLLDIVIDE=1, PLLPERIOD=10.0, DCMMULTIPLY=1, DCMDIVIDE=1, DCMPERIOD="10.0") (\n ^~~~~~\n : ... Top module \'clock_select\'\nmodule clock_select #(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:319: Cannot find file containing module: \'DCM_SP\'\n DCM_SP #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.sv\n DCM_SP\n DCM_SP.v\n DCM_SP.sv\n obj_dir/DCM_SP\n obj_dir/DCM_SP.v\n obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:256: Cannot find file containing module: \'DCM_CLKGEN\'\n DCM_CLKGEN #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:39: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:393: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_0s (.I0(clock[0]), .I1(clock[1]), .S(select[0]), .O(clock_0s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:394: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_1s (.I0(clock[2]), .I1(clock[3]), .S(select[0]), .O(clock_1s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:395: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_sx (.I0(clock_0s), .I1(clock_1s), .S(select[1]), .O(clock_out));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:200: Cannot find file containing module: \'PLL_BASE\'\n PLL_BASE #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:113: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:18: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS mybuf_raw1 (.I(clock_p), .IB(clock_n), .O(clock_raw1));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:21: Cannot find file containing module: \'BUFG\'\n BUFG mybuf_raw2 (.I(clock_raw2), .O(clock_out));\n ^~~~\n%Error: Exiting due to 10 error(s), 2 warning(s)\n' | 6,819 | module | module plldcm #(parameter OVERALL_DIVIDE=1, PLLMULTIPLY=1, PLLDIVIDE=1, PLLPERIOD=10.0, DCMMULTIPLY=1, DCMDIVIDE=1, DCMPERIOD="10.0") (
input clockin,
input reset,
output clockout,
output clockout180,
output locked
);
wire clockintermediate;
wire dcmlocked;
wire plllocked;
assign locked = dcmlocked & plllocked;
simplepll_ADV_2DCM #(.OVERALL_DIVIDE(OVERALL_DIVIDE), .MULTIPLY(PLLMULTIPLY), .DIVIDE(PLLDIVIDE), .PERIOD(PLLPERIOD), .COMPENSATION("PLL2DCM")) mypll (
.clockin(clockin),
.reset(reset),
.clockout(clockintermediate),
.locked(plllocked));
simpledcm_SP #(.MULTIPLY(DCMMULTIPLY), .DIVIDE(DCMDIVIDE), .PERIOD(DCMPERIOD)) mydcm (
.clockin(clockintermediate),
.reset(reset),
.clockout(clockout),
.clockout180(clockout180),
.locked(dcmlocked));
endmodule | module plldcm #(parameter OVERALL_DIVIDE=1, PLLMULTIPLY=1, PLLDIVIDE=1, PLLPERIOD=10.0, DCMMULTIPLY=1, DCMDIVIDE=1, DCMPERIOD="10.0") (
input clockin,
input reset,
output clockout,
output clockout180,
output locked
); |
wire clockintermediate;
wire dcmlocked;
wire plllocked;
assign locked = dcmlocked & plllocked;
simplepll_ADV_2DCM #(.OVERALL_DIVIDE(OVERALL_DIVIDE), .MULTIPLY(PLLMULTIPLY), .DIVIDE(PLLDIVIDE), .PERIOD(PLLPERIOD), .COMPENSATION("PLL2DCM")) mypll (
.clockin(clockin),
.reset(reset),
.clockout(clockintermediate),
.locked(plllocked));
simpledcm_SP #(.MULTIPLY(DCMMULTIPLY), .DIVIDE(DCMDIVIDE), .PERIOD(DCMPERIOD)) mydcm (
.clockin(clockintermediate),
.reset(reset),
.clockout(clockout),
.clockout180(clockout180),
.locked(dcmlocked));
endmodule | 2 |
6,053 | data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v | 115,035,459 | plldcm.v | v | 400 | 381 | [] | [] | [] | [(8, 22), (26, 97), (100, 171), (180, 241), (249, 296), (301, 355), (358, 381), (383, 396)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:375: Cell has missing pin: \'alt_clockout\'\n simpledcm_SP #(.MULTIPLY(DCMMULTIPLY), .DIVIDE(DCMDIVIDE), .PERIOD(DCMPERIOD)) mydcm (\n ^~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:100: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'dummy_dcm_diff_input\'\nmodule dummy_dcm_diff_input #(\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'simplepll_ADV\'\nmodule simplepll_ADV #(\n ^~~~~~~~~~~~~\n : ... Top module \'simplepll_BASE\'\nmodule simplepll_BASE #(\n ^~~~~~~~~~~~~~\n : ... Top module \'plldcm\'\nmodule plldcm #(parameter OVERALL_DIVIDE=1, PLLMULTIPLY=1, PLLDIVIDE=1, PLLPERIOD=10.0, DCMMULTIPLY=1, DCMDIVIDE=1, DCMPERIOD="10.0") (\n ^~~~~~\n : ... Top module \'clock_select\'\nmodule clock_select #(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:319: Cannot find file containing module: \'DCM_SP\'\n DCM_SP #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.sv\n DCM_SP\n DCM_SP.v\n DCM_SP.sv\n obj_dir/DCM_SP\n obj_dir/DCM_SP.v\n obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:256: Cannot find file containing module: \'DCM_CLKGEN\'\n DCM_CLKGEN #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:39: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:393: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_0s (.I0(clock[0]), .I1(clock[1]), .S(select[0]), .O(clock_0s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:394: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_1s (.I0(clock[2]), .I1(clock[3]), .S(select[0]), .O(clock_1s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:395: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_sx (.I0(clock_0s), .I1(clock_1s), .S(select[1]), .O(clock_out));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:200: Cannot find file containing module: \'PLL_BASE\'\n PLL_BASE #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:113: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:18: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS mybuf_raw1 (.I(clock_p), .IB(clock_n), .O(clock_raw1));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:21: Cannot find file containing module: \'BUFG\'\n BUFG mybuf_raw2 (.I(clock_raw2), .O(clock_out));\n ^~~~\n%Error: Exiting due to 10 error(s), 2 warning(s)\n' | 6,819 | module | module clock_select #(
parameter N = 4,
parameter log2_N = $clog2(N)
) (
input [N-1:0] clock,
input [log2_N-1:0] select,
output clock_out
);
wire clock_0s;
wire clock_1s;
BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_0s (.I0(clock[0]), .I1(clock[1]), .S(select[0]), .O(clock_0s));
BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_1s (.I0(clock[2]), .I1(clock[3]), .S(select[0]), .O(clock_1s));
BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_sx (.I0(clock_0s), .I1(clock_1s), .S(select[1]), .O(clock_out));
endmodule | module clock_select #(
parameter N = 4,
parameter log2_N = $clog2(N)
) (
input [N-1:0] clock,
input [log2_N-1:0] select,
output clock_out
); |
wire clock_0s;
wire clock_1s;
BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_0s (.I0(clock[0]), .I1(clock[1]), .S(select[0]), .O(clock_0s));
BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_1s (.I0(clock[2]), .I1(clock[3]), .S(select[0]), .O(clock_1s));
BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_sx (.I0(clock_0s), .I1(clock_1s), .S(select[1]), .O(clock_out));
endmodule | 2 |
6,055 | data/full_repos/permissive/115035459/verilog/src/lib/RAM.sv | 115,035,459 | RAM.sv | sv | 214 | 88 | [] | [] | [] | null | line:18: before: "=" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/RAM.sv:37: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'RAM_inferred_with_register_outputs\'\nmodule RAM_inferred_with_register_outputs #(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'RAM_inferred_with_register_inputs\'\nmodule RAM_inferred_with_register_inputs #(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 6,821 | module | module RAM_inferred_with_register_outputs #(
parameter ADDR_WIDTH = 4,
parameter NUMBER_OF_ADDRESSES = 1<<ADDR_WIDTH,
parameter DATA_WIDTH = 32
) (
input reset,
input [ADDR_WIDTH-1:0] waddr, raddr,
input [DATA_WIDTH-1:0] din,
input write_en, wclk, rclk,
output reg [DATA_WIDTH-1:0] dout = 0,
output reg [DATA_WIDTH-1:0] mem [NUMBER_OF_ADDRESSES-1:0]
);
always @(posedge wclk) begin
if (~reset) begin
if (write_en) begin
mem[waddr] <= din;
end
end
end
always @(posedge rclk) begin
if (~reset) begin
dout <= mem[raddr];
end
end
endmodule | module RAM_inferred_with_register_outputs #(
parameter ADDR_WIDTH = 4,
parameter NUMBER_OF_ADDRESSES = 1<<ADDR_WIDTH,
parameter DATA_WIDTH = 32
) (
input reset,
input [ADDR_WIDTH-1:0] waddr, raddr,
input [DATA_WIDTH-1:0] din,
input write_en, wclk, rclk,
output reg [DATA_WIDTH-1:0] dout = 0,
output reg [DATA_WIDTH-1:0] mem [NUMBER_OF_ADDRESSES-1:0]
); |
always @(posedge wclk) begin
if (~reset) begin
if (write_en) begin
mem[waddr] <= din;
end
end
end
always @(posedge rclk) begin
if (~reset) begin
dout <= mem[raddr];
end
end
endmodule | 2 |
6,056 | data/full_repos/permissive/115035459/verilog/src/lib/RAM.sv | 115,035,459 | RAM.sv | sv | 214 | 88 | [] | [] | [] | null | line:18: before: "=" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/RAM.sv:37: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'RAM_inferred_with_register_outputs\'\nmodule RAM_inferred_with_register_outputs #(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'RAM_inferred_with_register_inputs\'\nmodule RAM_inferred_with_register_inputs #(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 6,821 | module | module RAM_inferred_with_register_inputs #(
parameter ADDR_WIDTH = 4,
parameter NUMBER_OF_ADDRESSES = 1<<ADDR_WIDTH,
parameter DATA_WIDTH = 32
) (
input reset,
input [ADDR_WIDTH-1:0] waddr, raddr,
input [DATA_WIDTH-1:0] din,
input write_en, wclk, rclk,
output reg [DATA_WIDTH-1:0] dout = 0,
input [DATA_WIDTH-1:0] mem_in [NUMBER_OF_ADDRESSES-1:0]
);
reg [DATA_WIDTH-1:0] mem [NUMBER_OF_ADDRESSES-1:0];
genvar i;
always @(posedge wclk) begin
if (~reset) begin
if (write_en) begin
mem[waddr] <= din;
end else begin
for (i=0; i<NUMBER_OF_ADDRESSES; i=i+1) begin : write_block
mem[i] <= mem_in[i];
end
end
end
end
always @(posedge rclk) begin
if (~reset) begin
dout <= mem[raddr];
end
end
endmodule | module RAM_inferred_with_register_inputs #(
parameter ADDR_WIDTH = 4,
parameter NUMBER_OF_ADDRESSES = 1<<ADDR_WIDTH,
parameter DATA_WIDTH = 32
) (
input reset,
input [ADDR_WIDTH-1:0] waddr, raddr,
input [DATA_WIDTH-1:0] din,
input write_en, wclk, rclk,
output reg [DATA_WIDTH-1:0] dout = 0,
input [DATA_WIDTH-1:0] mem_in [NUMBER_OF_ADDRESSES-1:0]
); |
reg [DATA_WIDTH-1:0] mem [NUMBER_OF_ADDRESSES-1:0];
genvar i;
always @(posedge wclk) begin
if (~reset) begin
if (write_en) begin
mem[waddr] <= din;
end else begin
for (i=0; i<NUMBER_OF_ADDRESSES; i=i+1) begin : write_block
mem[i] <= mem_in[i];
end
end
end
end
always @(posedge rclk) begin
if (~reset) begin
dout <= mem[raddr];
end
end
endmodule | 2 |
6,081 | data/full_repos/permissive/115035459/verilog/src/lib/reset.v | 115,035,459 | reset.v | v | 203 | 395 | [] | [] | [] | null | line:43: before: "20" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:174: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:178: Unsupported: Ignoring delay on this delayed statement.\n #20; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:179: Unsupported: Ignoring delay on this delayed statement.\n #100; upstream_reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:180: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:181: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:183: Unsupported: Ignoring delay on this delayed statement.\n #100; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:184: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:185: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:186: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:187: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:189: Unsupported: Ignoring delay on this delayed statement.\n #100; clock_enabled <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:190: Unsupported: Ignoring delay on this delayed statement.\n #100; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:191: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:192: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:196: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:53: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'reset3_wait4plls\'\nmodule reset3_wait4plls #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'reset_promulgator\'\nmodule reset_promulgator #(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'reset_tb\'\nmodule reset_tb();\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:48: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:48: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:49: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:49: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:50: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:50: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,823 | module | module reset_wait4pll #(
parameter COUNTER_BIT_PICKOFF = 20,
parameter PIPELINE_PICKOFF = 6
) (
input reset_input,
input pll_locked_input,
input clock_input,
output reg reset_output = 1
);
reg [COUNTER_BIT_PICKOFF:0] counter = 0;
(* KEEP = "TRUE" *) wire should_be_in_reset_cdc = ~pll_locked_input || reset_input;
wire should_be_in_reset_pipeline;
pipeline #(.WIDTH(1), .DEPTH(PIPELINE_PICKOFF)) z (.clock(clock_input), .in(should_be_in_reset_cdc), .out(should_be_in_reset_pipeline));
always @(posedge clock_input) begin
if (should_be_in_reset_pipeline) begin
counter <= 0;
reset_output <= 1;
end else if (reset_output) begin
if (counter[COUNTER_BIT_PICKOFF]) begin
reset_output <= 0;
end
counter <= counter + 1'b1;
end
end
endmodule | module reset_wait4pll #(
parameter COUNTER_BIT_PICKOFF = 20,
parameter PIPELINE_PICKOFF = 6
) (
input reset_input,
input pll_locked_input,
input clock_input,
output reg reset_output = 1
); |
reg [COUNTER_BIT_PICKOFF:0] counter = 0;
(* KEEP = "TRUE" *) wire should_be_in_reset_cdc = ~pll_locked_input || reset_input;
wire should_be_in_reset_pipeline;
pipeline #(.WIDTH(1), .DEPTH(PIPELINE_PICKOFF)) z (.clock(clock_input), .in(should_be_in_reset_cdc), .out(should_be_in_reset_pipeline));
always @(posedge clock_input) begin
if (should_be_in_reset_pipeline) begin
counter <= 0;
reset_output <= 1;
end else if (reset_output) begin
if (counter[COUNTER_BIT_PICKOFF]) begin
reset_output <= 0;
end
counter <= counter + 1'b1;
end
end
endmodule | 2 |
6,082 | data/full_repos/permissive/115035459/verilog/src/lib/reset.v | 115,035,459 | reset.v | v | 203 | 395 | [] | [] | [] | null | line:43: before: "20" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:174: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:178: Unsupported: Ignoring delay on this delayed statement.\n #20; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:179: Unsupported: Ignoring delay on this delayed statement.\n #100; upstream_reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:180: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:181: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:183: Unsupported: Ignoring delay on this delayed statement.\n #100; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:184: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:185: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:186: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:187: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:189: Unsupported: Ignoring delay on this delayed statement.\n #100; clock_enabled <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:190: Unsupported: Ignoring delay on this delayed statement.\n #100; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:191: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:192: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:196: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:53: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'reset3_wait4plls\'\nmodule reset3_wait4plls #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'reset_promulgator\'\nmodule reset_promulgator #(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'reset_tb\'\nmodule reset_tb();\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:48: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:48: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:49: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:49: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:50: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:50: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,823 | module | module reset3_wait4plls #(
parameter CLOCK1_BIT_PICKOFF = 20,
parameter CLOCK2_BIT_PICKOFF = 20,
parameter CLOCK3_BIT_PICKOFF = 20,
parameter RESET_PIPELINE_PICKOFF = 5,
parameter PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF = 10,
parameter PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF = 10,
parameter PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF = 10
) (
input reset_input,
input pll_locked1_input, pll_locked2_input, pll_locked3_input,
input clock1_input, clock2_input, clock3_input,
output reset1_output,
output reset2_output,
output reset3_output
);
reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));
reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));
reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));
endmodule | module reset3_wait4plls #(
parameter CLOCK1_BIT_PICKOFF = 20,
parameter CLOCK2_BIT_PICKOFF = 20,
parameter CLOCK3_BIT_PICKOFF = 20,
parameter RESET_PIPELINE_PICKOFF = 5,
parameter PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF = 10,
parameter PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF = 10,
parameter PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF = 10
) (
input reset_input,
input pll_locked1_input, pll_locked2_input, pll_locked3_input,
input clock1_input, clock2_input, clock3_input,
output reset1_output,
output reset2_output,
output reset3_output
); |
reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));
reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));
reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));
endmodule | 2 |
6,083 | data/full_repos/permissive/115035459/verilog/src/lib/reset.v | 115,035,459 | reset.v | v | 203 | 395 | [] | [] | [] | null | line:43: before: "20" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:174: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:178: Unsupported: Ignoring delay on this delayed statement.\n #20; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:179: Unsupported: Ignoring delay on this delayed statement.\n #100; upstream_reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:180: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:181: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:183: Unsupported: Ignoring delay on this delayed statement.\n #100; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:184: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:185: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:186: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:187: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:189: Unsupported: Ignoring delay on this delayed statement.\n #100; clock_enabled <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:190: Unsupported: Ignoring delay on this delayed statement.\n #100; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:191: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:192: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:196: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:53: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'reset3_wait4plls\'\nmodule reset3_wait4plls #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'reset_promulgator\'\nmodule reset_promulgator #(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'reset_tb\'\nmodule reset_tb();\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:48: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:48: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:49: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:49: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:50: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:50: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,823 | module | module reset_promulgator #(
parameter CLOCK1_BIT_PICKOFF = 20,
parameter CLOCK2_BIT_PICKOFF = 20,
parameter RESET_PIPELINE_PICKOFF = 5,
parameter PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF = 2
) (
input reset_input,
input clock1, clock2,
input pll_locked_input,
output reg reset1 = 1,
output reg reset2 = 1,
output reg pll_locked_output = 0
);
reg [RESET_PIPELINE_PICKOFF:0] reset_pipeline_clock1 = 0;
reg [RESET_PIPELINE_PICKOFF:0] reset_pipeline_clock2 = 0;
reg [3:0] reset_counter = 0;
reg [CLOCK1_BIT_PICKOFF:0] counter_clock1 = 0;
always @(posedge clock1) begin
if (reset_pipeline_clock1[RESET_PIPELINE_PICKOFF:RESET_PIPELINE_PICKOFF-3]==4'b0011) begin
reset_counter <= reset_counter + 1'b1;
end else if (reset_pipeline_clock1[RESET_PIPELINE_PICKOFF]) begin
counter_clock1 <= 0;
reset1 <= 1;
end else if (reset1) begin
if (counter_clock1[CLOCK1_BIT_PICKOFF]) begin
reset1 <= 0;
end
counter_clock1 <= counter_clock1 + 1'b1;
end
reset_pipeline_clock1 <= { reset_pipeline_clock1[RESET_PIPELINE_PICKOFF-1:0], reset_input };
end
reg [2:0] reset_clock1_pipeline_clock2 = 0;
reg [PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF:0] pll_locked_pipeline_clock2 = 0;
integer j;
always @(posedge clock2) begin
if (~pll_locked_pipeline_clock2[PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF]) begin
reset_clock1_pipeline_clock2 <= 0;
reset_pipeline_clock2 <= 0;
end else begin
reset_clock1_pipeline_clock2 <= { reset_clock1_pipeline_clock2[1:0], reset1 };
reset_pipeline_clock2 <= { reset_pipeline_clock2[RESET_PIPELINE_PICKOFF-1:0], reset_input };
end
pll_locked_output <= pll_locked_pipeline_clock2[PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF];
pll_locked_pipeline_clock2 <= { pll_locked_pipeline_clock2[PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF-1:0], pll_locked_input };
end
reg [CLOCK2_BIT_PICKOFF:0] counter_clock2 = 0;
always @(posedge clock2) begin
if (reset_pipeline_clock2[RESET_PIPELINE_PICKOFF] || reset_clock1_pipeline_clock2[2] || ~pll_locked_pipeline_clock2[PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF]) begin
counter_clock2 <= 0;
reset2 <= 1;
end else if (reset2) begin
if (counter_clock2[CLOCK2_BIT_PICKOFF]) begin
reset2 <= 0;
end
counter_clock2 <= counter_clock2 + 1'b1;
end
end
endmodule | module reset_promulgator #(
parameter CLOCK1_BIT_PICKOFF = 20,
parameter CLOCK2_BIT_PICKOFF = 20,
parameter RESET_PIPELINE_PICKOFF = 5,
parameter PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF = 2
) (
input reset_input,
input clock1, clock2,
input pll_locked_input,
output reg reset1 = 1,
output reg reset2 = 1,
output reg pll_locked_output = 0
); |
reg [RESET_PIPELINE_PICKOFF:0] reset_pipeline_clock1 = 0;
reg [RESET_PIPELINE_PICKOFF:0] reset_pipeline_clock2 = 0;
reg [3:0] reset_counter = 0;
reg [CLOCK1_BIT_PICKOFF:0] counter_clock1 = 0;
always @(posedge clock1) begin
if (reset_pipeline_clock1[RESET_PIPELINE_PICKOFF:RESET_PIPELINE_PICKOFF-3]==4'b0011) begin
reset_counter <= reset_counter + 1'b1;
end else if (reset_pipeline_clock1[RESET_PIPELINE_PICKOFF]) begin
counter_clock1 <= 0;
reset1 <= 1;
end else if (reset1) begin
if (counter_clock1[CLOCK1_BIT_PICKOFF]) begin
reset1 <= 0;
end
counter_clock1 <= counter_clock1 + 1'b1;
end
reset_pipeline_clock1 <= { reset_pipeline_clock1[RESET_PIPELINE_PICKOFF-1:0], reset_input };
end
reg [2:0] reset_clock1_pipeline_clock2 = 0;
reg [PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF:0] pll_locked_pipeline_clock2 = 0;
integer j;
always @(posedge clock2) begin
if (~pll_locked_pipeline_clock2[PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF]) begin
reset_clock1_pipeline_clock2 <= 0;
reset_pipeline_clock2 <= 0;
end else begin
reset_clock1_pipeline_clock2 <= { reset_clock1_pipeline_clock2[1:0], reset1 };
reset_pipeline_clock2 <= { reset_pipeline_clock2[RESET_PIPELINE_PICKOFF-1:0], reset_input };
end
pll_locked_output <= pll_locked_pipeline_clock2[PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF];
pll_locked_pipeline_clock2 <= { pll_locked_pipeline_clock2[PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF-1:0], pll_locked_input };
end
reg [CLOCK2_BIT_PICKOFF:0] counter_clock2 = 0;
always @(posedge clock2) begin
if (reset_pipeline_clock2[RESET_PIPELINE_PICKOFF] || reset_clock1_pipeline_clock2[2] || ~pll_locked_pipeline_clock2[PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF]) begin
counter_clock2 <= 0;
reset2 <= 1;
end else if (reset2) begin
if (counter_clock2[CLOCK2_BIT_PICKOFF]) begin
reset2 <= 0;
end
counter_clock2 <= counter_clock2 + 1'b1;
end
end
endmodule | 2 |
6,084 | data/full_repos/permissive/115035459/verilog/src/lib/reset.v | 115,035,459 | reset.v | v | 203 | 395 | [] | [] | [] | null | line:43: before: "20" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:174: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:178: Unsupported: Ignoring delay on this delayed statement.\n #20; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:179: Unsupported: Ignoring delay on this delayed statement.\n #100; upstream_reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:180: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:181: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:183: Unsupported: Ignoring delay on this delayed statement.\n #100; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:184: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:185: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:186: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:187: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:189: Unsupported: Ignoring delay on this delayed statement.\n #100; clock_enabled <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:190: Unsupported: Ignoring delay on this delayed statement.\n #100; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:191: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:192: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:196: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:53: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'reset3_wait4plls\'\nmodule reset3_wait4plls #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'reset_promulgator\'\nmodule reset_promulgator #(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'reset_tb\'\nmodule reset_tb();\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:48: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:48: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:49: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:49: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:50: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:50: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,823 | module | module reset #(
parameter FREQUENCY = 10000000.0,
parameter PLL_LOCK_TIME = 0.05,
parameter SYNCHRONOUS_ONLY = 1,
parameter SIGNIFICANT_BIT_NUMBER_B = $clog2(FREQUENCY*PLL_LOCK_TIME) + 1,
parameter SIGNIFICANT_BIT_NUMBER_A = SIGNIFICANT_BIT_NUMBER_B/4
) (
input upstream_clock,
input upstream_reset,
input downstream_pll_locked,
output downstream_reset
);
reg [SIGNIFICANT_BIT_NUMBER_A:0] counterA = 0;
reg [SIGNIFICANT_BIT_NUMBER_B:0] counterB = 0;
reg internal_reset_state = 1;
reg sychronous_reset_source = 1;
if (SYNCHRONOUS_ONLY) begin
assign downstream_reset = sychronous_reset_source;
end else begin
wire asychronous_reset_source;
assign asychronous_reset_source = upstream_reset || (counterB[SIGNIFICANT_BIT_NUMBER_B]&&(~downstream_pll_locked));
assign downstream_reset = asychronous_reset_source || sychronous_reset_source;
end
always @(posedge upstream_clock) begin
if (upstream_reset) begin
counterA <= 0;
sychronous_reset_source <= 1;
counterB <= 0;
internal_reset_state <= 1;
end else if (internal_reset_state) begin
if (counterA[SIGNIFICANT_BIT_NUMBER_A]) begin
sychronous_reset_source <= 0;
if (counterB[SIGNIFICANT_BIT_NUMBER_B]) begin
internal_reset_state <= 0;
end else begin
counterB <= counterB + 1'b1;
end
end else begin
counterA <= counterA + 1'b1;
end
end else if (~downstream_pll_locked) begin
counterA <= 0;
sychronous_reset_source <= 1;
counterB <= 0;
internal_reset_state <= 1;
end
end
endmodule | module reset #(
parameter FREQUENCY = 10000000.0,
parameter PLL_LOCK_TIME = 0.05,
parameter SYNCHRONOUS_ONLY = 1,
parameter SIGNIFICANT_BIT_NUMBER_B = $clog2(FREQUENCY*PLL_LOCK_TIME) + 1,
parameter SIGNIFICANT_BIT_NUMBER_A = SIGNIFICANT_BIT_NUMBER_B/4
) (
input upstream_clock,
input upstream_reset,
input downstream_pll_locked,
output downstream_reset
); |
reg [SIGNIFICANT_BIT_NUMBER_A:0] counterA = 0;
reg [SIGNIFICANT_BIT_NUMBER_B:0] counterB = 0;
reg internal_reset_state = 1;
reg sychronous_reset_source = 1;
if (SYNCHRONOUS_ONLY) begin
assign downstream_reset = sychronous_reset_source;
end else begin
wire asychronous_reset_source;
assign asychronous_reset_source = upstream_reset || (counterB[SIGNIFICANT_BIT_NUMBER_B]&&(~downstream_pll_locked));
assign downstream_reset = asychronous_reset_source || sychronous_reset_source;
end
always @(posedge upstream_clock) begin
if (upstream_reset) begin
counterA <= 0;
sychronous_reset_source <= 1;
counterB <= 0;
internal_reset_state <= 1;
end else if (internal_reset_state) begin
if (counterA[SIGNIFICANT_BIT_NUMBER_A]) begin
sychronous_reset_source <= 0;
if (counterB[SIGNIFICANT_BIT_NUMBER_B]) begin
internal_reset_state <= 0;
end else begin
counterB <= counterB + 1'b1;
end
end else begin
counterA <= counterA + 1'b1;
end
end else if (~downstream_pll_locked) begin
counterA <= 0;
sychronous_reset_source <= 1;
counterB <= 0;
internal_reset_state <= 1;
end
end
endmodule | 2 |
6,085 | data/full_repos/permissive/115035459/verilog/src/lib/reset.v | 115,035,459 | reset.v | v | 203 | 395 | [] | [] | [] | null | line:43: before: "20" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:174: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:178: Unsupported: Ignoring delay on this delayed statement.\n #20; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:179: Unsupported: Ignoring delay on this delayed statement.\n #100; upstream_reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:180: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:181: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:183: Unsupported: Ignoring delay on this delayed statement.\n #100; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:184: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:185: Unsupported: Ignoring delay on this delayed statement.\n #200; downstream_pll_locked <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:186: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:187: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:189: Unsupported: Ignoring delay on this delayed statement.\n #100; clock_enabled <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:190: Unsupported: Ignoring delay on this delayed statement.\n #100; downstream_pll_locked <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:191: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:192: Unsupported: Ignoring delay on this delayed statement.\n #1000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:196: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:53: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'reset3_wait4plls\'\nmodule reset3_wait4plls #(\n ^~~~~~~~~~~~~~~~\n : ... Top module \'reset_promulgator\'\nmodule reset_promulgator #(\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'reset_tb\'\nmodule reset_tb();\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:48: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:48: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:49: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:49: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:50: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:50: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,823 | module | module reset_tb();
reg clock_enabled = 1;
reg upstream_clock = 0;
reg upstream_reset = 0;
reg downstream_pll_locked = 0;
wire downstream_reset;
reset #(.FREQUENCY(10000000), .SIGNIFICANT_BIT_NUMBER_B(5)) myr (.upstream_clock(upstream_clock), .upstream_reset(upstream_reset), .downstream_pll_locked(downstream_pll_locked), .downstream_reset(downstream_reset));
initial begin
#200; downstream_pll_locked <= 1;
#1000;
upstream_reset <= 1;
#20; downstream_pll_locked <= 0;
#100; upstream_reset <= 0;
#200; downstream_pll_locked <= 1;
#1000;
#100; downstream_pll_locked <= 0;
#1000;
#200; downstream_pll_locked <= 1;
#1000;
#1000;
#100; clock_enabled <= 0;
#100; downstream_pll_locked <= 0;
#100;
#1000;
$finish;
end
always begin
#10;
if (clock_enabled) begin
upstream_clock <= ~upstream_clock;
end
end
endmodule | module reset_tb(); |
reg clock_enabled = 1;
reg upstream_clock = 0;
reg upstream_reset = 0;
reg downstream_pll_locked = 0;
wire downstream_reset;
reset #(.FREQUENCY(10000000), .SIGNIFICANT_BIT_NUMBER_B(5)) myr (.upstream_clock(upstream_clock), .upstream_reset(upstream_reset), .downstream_pll_locked(downstream_pll_locked), .downstream_reset(downstream_reset));
initial begin
#200; downstream_pll_locked <= 1;
#1000;
upstream_reset <= 1;
#20; downstream_pll_locked <= 0;
#100; upstream_reset <= 0;
#200; downstream_pll_locked <= 1;
#1000;
#100; downstream_pll_locked <= 0;
#1000;
#200; downstream_pll_locked <= 1;
#1000;
#1000;
#100; clock_enabled <= 0;
#100; downstream_pll_locked <= 0;
#100;
#1000;
$finish;
end
always begin
#10;
if (clock_enabled) begin
upstream_clock <= ~upstream_clock;
end
end
endmodule | 2 |
6,088 | data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v | 115,035,459 | sequencer.v | v | 188 | 243 | [] | [] | [] | null | line:14: before: "=" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:146: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:148: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:160: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:162: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:164: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:183: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'write_clock\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'read_clock\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'sync_read_address\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'channel\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'start_read_address\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'end_read_address\'\n ) fg (\n ^~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:111: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'sequencer_sync\'\nmodule sequencer_sync #(\n ^~~~~~~~~~~~~~\n : ... Top module \'function_generator_tb\'\nmodule function_generator_tb;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:129: Pin not found: \'clock\'\n .clock(clock),\n ^~~~~\n%Error: Exiting due to 1 error(s), 13 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,825 | module | module sequencer_sync #(
parameter ADDRESS_DEPTH_OSERDES = 16,
parameter LOG2_OF_OSERDES_DATA_WIDTH = 3,
parameter SYNC_OUT_STREAM_PICKOFF = 2
) (
input clock, reset,
input sync_read_address,
input [31:0] start_sample,
input [31:0] end_sample,
output reg [ADDRESS_DEPTH_OSERDES-1:0] read_address = 0,
output reg [SYNC_OUT_STREAM_PICKOFF:0] sync_out_stream = 0,
output [7:0] sync_out_word
);
reg [ADDRESS_DEPTH_OSERDES-1:0] last_read_address = 14'd4095;
reg sync_out_raw = 0;
always @(posedge clock) begin
sync_out_raw <= 0;
if (reset) begin
read_address <= start_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH];
last_read_address <= end_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH] - 1'b1;
sync_out_stream <= 0;
end else begin
if (read_address==last_read_address || sync_read_address) begin
read_address <= start_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH];
last_read_address <= end_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH] - 1'b1;
sync_out_raw <= 1;
end else begin
read_address <= read_address + 1'b1;
end
sync_out_stream <= { sync_out_stream[SYNC_OUT_STREAM_PICKOFF-1:0], sync_out_raw };
end
end
assign sync_out_word = { sync_out_stream[1], 7'b0 };
endmodule | module sequencer_sync #(
parameter ADDRESS_DEPTH_OSERDES = 16,
parameter LOG2_OF_OSERDES_DATA_WIDTH = 3,
parameter SYNC_OUT_STREAM_PICKOFF = 2
) (
input clock, reset,
input sync_read_address,
input [31:0] start_sample,
input [31:0] end_sample,
output reg [ADDRESS_DEPTH_OSERDES-1:0] read_address = 0,
output reg [SYNC_OUT_STREAM_PICKOFF:0] sync_out_stream = 0,
output [7:0] sync_out_word
); |
reg [ADDRESS_DEPTH_OSERDES-1:0] last_read_address = 14'd4095;
reg sync_out_raw = 0;
always @(posedge clock) begin
sync_out_raw <= 0;
if (reset) begin
read_address <= start_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH];
last_read_address <= end_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH] - 1'b1;
sync_out_stream <= 0;
end else begin
if (read_address==last_read_address || sync_read_address) begin
read_address <= start_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH];
last_read_address <= end_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH] - 1'b1;
sync_out_raw <= 1;
end else begin
read_address <= read_address + 1'b1;
end
sync_out_stream <= { sync_out_stream[SYNC_OUT_STREAM_PICKOFF-1:0], sync_out_raw };
end
end
assign sync_out_word = { sync_out_stream[1], 7'b0 };
endmodule | 2 |
6,089 | data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v | 115,035,459 | sequencer.v | v | 188 | 243 | [] | [] | [] | null | line:14: before: "=" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:146: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:148: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:160: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:162: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:164: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:183: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'write_clock\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'read_clock\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'sync_read_address\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'channel\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'start_read_address\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'end_read_address\'\n ) fg (\n ^~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:111: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'sequencer_sync\'\nmodule sequencer_sync #(\n ^~~~~~~~~~~~~~\n : ... Top module \'function_generator_tb\'\nmodule function_generator_tb;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:129: Pin not found: \'clock\'\n .clock(clock),\n ^~~~~\n%Error: Exiting due to 1 error(s), 13 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,825 | module | module function_generator #(
parameter DATA_BUS_WIDTH = 8,
parameter ADDRESS_BUS_DEPTH = 11,
parameter NUMBER_OF_CHANNELS = 1
) (
input write_clock,
input read_clock,
input reset,
input sync_read_address,
input [$clog2(NUMBER_OF_CHANNELS)-1:0] channel,
input [DATA_BUS_WIDTH-1:0] data_in,
input [ADDRESS_BUS_DEPTH-1:0] write_address,
input [ADDRESS_BUS_DEPTH-1:0] start_read_address,
input [ADDRESS_BUS_DEPTH-1:0] end_read_address,
input write_enable,
output [DATA_BUS_WIDTH-1:0] data_out
);
reg [ADDRESS_BUS_DEPTH-1:0] read_address = 0;
reg [ADDRESS_BUS_DEPTH-1:0] last_read_address = ADDRESS_BUS_DEPTH*{1'b1};
genvar ch;
for (ch=0; ch<NUMBER_OF_CHANNELS; ch=ch+1) begin : chan
RAM_s6_primitive #(.DATA_WIDTH_A(DATA_BUS_WIDTH), .DATA_WIDTH_B(DATA_BUS_WIDTH)) mem (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .data_in(data_in), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_enable(1'b1), .data_out(data_out));
always @(posedge read_clock) begin
if (reset || sync_read_address) begin
read_address <= 0;
end else begin
if (read_address==last_read_address) begin
read_address <= start_read_address;
last_read_address <= end_read_address - 1'b1;
end else begin
read_address <= read_address + 1'b1;
end
end
end
end
endmodule | module function_generator #(
parameter DATA_BUS_WIDTH = 8,
parameter ADDRESS_BUS_DEPTH = 11,
parameter NUMBER_OF_CHANNELS = 1
) (
input write_clock,
input read_clock,
input reset,
input sync_read_address,
input [$clog2(NUMBER_OF_CHANNELS)-1:0] channel,
input [DATA_BUS_WIDTH-1:0] data_in,
input [ADDRESS_BUS_DEPTH-1:0] write_address,
input [ADDRESS_BUS_DEPTH-1:0] start_read_address,
input [ADDRESS_BUS_DEPTH-1:0] end_read_address,
input write_enable,
output [DATA_BUS_WIDTH-1:0] data_out
); |
reg [ADDRESS_BUS_DEPTH-1:0] read_address = 0;
reg [ADDRESS_BUS_DEPTH-1:0] last_read_address = ADDRESS_BUS_DEPTH*{1'b1};
genvar ch;
for (ch=0; ch<NUMBER_OF_CHANNELS; ch=ch+1) begin : chan
RAM_s6_primitive #(.DATA_WIDTH_A(DATA_BUS_WIDTH), .DATA_WIDTH_B(DATA_BUS_WIDTH)) mem (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .data_in(data_in), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_enable(1'b1), .data_out(data_out));
always @(posedge read_clock) begin
if (reset || sync_read_address) begin
read_address <= 0;
end else begin
if (read_address==last_read_address) begin
read_address <= start_read_address;
last_read_address <= end_read_address - 1'b1;
end else begin
read_address <= read_address + 1'b1;
end
end
end
end
endmodule | 2 |
6,090 | data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v | 115,035,459 | sequencer.v | v | 188 | 243 | [] | [] | [] | null | line:14: before: "=" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:146: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:148: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:160: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:162: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:164: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:183: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'write_clock\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'read_clock\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'sync_read_address\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'channel\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'start_read_address\'\n ) fg (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'end_read_address\'\n ) fg (\n ^~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:111: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'sequencer_sync\'\nmodule sequencer_sync #(\n ^~~~~~~~~~~~~~\n : ... Top module \'function_generator_tb\'\nmodule function_generator_tb;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:129: Pin not found: \'clock\'\n .clock(clock),\n ^~~~~\n%Error: Exiting due to 1 error(s), 13 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,825 | module | module function_generator_tb;
parameter DATA_BUS_WIDTH = 8;
parameter ADDRESS_BUS_DEPTH = 11;
parameter NUMBER_OF_CHANNELS = 1;
parameter ADDRESS_MAX = (2**ADDRESS_BUS_DEPTH)-1;
reg clock = 0;
reg reset = 1;
reg [DATA_BUS_WIDTH-1:0] data_in = 0;
reg [ADDRESS_BUS_DEPTH-1:0] write_address = 0;
reg write_enable = 0;
wire [DATA_BUS_WIDTH-1:0] data_out;
function_generator #(
.DATA_BUS_WIDTH(DATA_BUS_WIDTH),
.ADDRESS_BUS_DEPTH(ADDRESS_BUS_DEPTH),
.NUMBER_OF_CHANNELS(NUMBER_OF_CHANNELS)
) fg (
.clock(clock),
.reset(reset),
.write_address(write_address),
.data_in(data_in),
.write_enable(write_enable),
.data_out(data_out)
);
reg [ADDRESS_BUS_DEPTH-1:0] ad;
initial begin
clock <= 0;
reset <= 1;
data_in <= 0;
write_address <= 0;
write_enable <= 0;
#8;
reset <= 0;
#8;
for (ad=0; ad<=ADDRESS_MAX; ad=ad+1) begin : ramp
write_address <= ad;
if (0) begin
if (write_address==123) begin
data_in <= 1;
end else begin
data_in <= 0;
end
end else begin
data_in <= ad[7:0];
end
#8;
write_enable <= 1;
#8;
write_enable <= 0;
#8;
end
end
always begin
#4;
clock = ~clock;
end
endmodule | module function_generator_tb; |
parameter DATA_BUS_WIDTH = 8;
parameter ADDRESS_BUS_DEPTH = 11;
parameter NUMBER_OF_CHANNELS = 1;
parameter ADDRESS_MAX = (2**ADDRESS_BUS_DEPTH)-1;
reg clock = 0;
reg reset = 1;
reg [DATA_BUS_WIDTH-1:0] data_in = 0;
reg [ADDRESS_BUS_DEPTH-1:0] write_address = 0;
reg write_enable = 0;
wire [DATA_BUS_WIDTH-1:0] data_out;
function_generator #(
.DATA_BUS_WIDTH(DATA_BUS_WIDTH),
.ADDRESS_BUS_DEPTH(ADDRESS_BUS_DEPTH),
.NUMBER_OF_CHANNELS(NUMBER_OF_CHANNELS)
) fg (
.clock(clock),
.reset(reset),
.write_address(write_address),
.data_in(data_in),
.write_enable(write_enable),
.data_out(data_out)
);
reg [ADDRESS_BUS_DEPTH-1:0] ad;
initial begin
clock <= 0;
reset <= 1;
data_in <= 0;
write_address <= 0;
write_enable <= 0;
#8;
reset <= 0;
#8;
for (ad=0; ad<=ADDRESS_MAX; ad=ad+1) begin : ramp
write_address <= ad;
if (0) begin
if (write_address==123) begin
data_in <= 1;
end else begin
data_in <= 0;
end
end else begin
data_in <= ad[7:0];
end
#8;
write_enable <= 1;
#8;
write_enable <= 0;
#8;
end
end
always begin
#4;
clock = ~clock;
end
endmodule | 2 |
6,098 | data/full_repos/permissive/115042397/vga_hex_display.v | 115,042,397 | vga_hex_display.v | v | 90 | 104 | [] | [] | [] | [(1, 89)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/115042397/vga_hex_display.v:64: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'y_start\' generates 8 bits.\n : ... In instance vga_hex_display\n y <= y_start;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115042397/vga_hex_display.v:66: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance vga_hex_display\n curr_pixel <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115042397/vga_hex_display.v:70: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance vga_hex_display\n curr_pixel <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115042397/vga_hex_display.v:71: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance vga_hex_display\n curr_index <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115042397/vga_hex_display.v:72: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance vga_hex_display\n x_start <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115042397/vga_hex_display.v:73: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance vga_hex_display\n x <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115042397/vga_hex_display.v:74: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance vga_hex_display\n y <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115042397/vga_hex_display.v:57: Operator LT expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'y\' generates 7 bits.\n : ... In instance vga_hex_display\n else if (y < y_start+height-1\'b1) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/115042397/vga_hex_display.v:86: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 4 bits.\n : ... In instance vga_hex_display\n colour = image[curr_pixel+(curr_num*width*height)];\n ^\n%Error: Exiting due to 9 warning(s)\n' | 6,832 | module | module vga_hex_display(clk, enable, resetn, num, x, y, colour, writeEn);
input clk;
input enable;
input resetn;
input [31:0] num;
output reg [7:0] x;
output reg [6:0] y;
output reg [2:0] colour;
output reg writeEn;
localparam width = 20;
localparam height = 30;
localparam num_length = 32;
localparam num_width = 4;
reg [7:0] x_start;
reg [7:0] y_start;
reg [9:0] curr_pixel;
reg [3:0] curr_num;
reg [6:0] curr_index;
reg [3:0] image [0 : width*height*16];
always @(posedge clk) begin
if (~resetn) begin
x_start <= 0;
y_start <= 0;
curr_pixel <= 0;
curr_index <= 0;
x <= 0;
y <= 0;
writeEn <= 0;
$readmemh ("images/0.list", image, 0, width*height-1);
$readmemh ("images/1.list", image, width*height, (width*height*2)-1);
$readmemh ("images/2.list", image, width*height*2, (width*height*3)-1);
$readmemh ("images/3.list", image, width*height*3, (width*height*4)-1);
$readmemh ("images/4.list", image, width*height*4, (width*height*5)-1);
$readmemh ("images/5.list", image, width*height*5, (width*height*6)-1);
$readmemh ("images/6.list", image, width*height*6, (width*height*7)-1);
$readmemh ("images/7.list", image, width*height*7, (width*height*8)-1);
$readmemh ("images/8.list", image, width*height*8, (width*height*9)-1);
$readmemh ("images/9.list", image, width*height*9, (width*height*10)-1);
$readmemh ("images/A.list", image, width*height*10, (width*height*11)-1);
$readmemh ("images/B.list", image, width*height*11, (width*height*12)-1);
$readmemh ("images/C.list", image, width*height*12, (width*height*13)-1);
$readmemh ("images/D.list", image, width*height*13, (width*height*14)-1);
$readmemh ("images/E.list", image, width*height*14, (width*height*15)-1);
$readmemh ("images/F.list", image, width*height*15, (width*height*16)-1);
end
else if (enable) begin
writeEn <= 1;
if (x < x_start+width-1'b1) begin
x <= x + 1'b1;
curr_pixel <= curr_pixel + 1'b1;
end
else if (y < y_start+height-1'b1) begin
x <= x_start;
y <= y + 1'b1;
curr_pixel <= curr_pixel + 1'b1;
end
else if (curr_index < (num_length-num_width)) begin
x <= x_start + width;
y <= y_start;
x_start <= x_start + width;
curr_pixel <= 1'b0;
curr_index <= curr_index + num_width;
end
else begin
curr_pixel <= 1'b0;
curr_index <= 1'b0;
x_start <= 1'b0;
x <= 1'b0;
y <= 1'b0;
end
end
end
always @(*)
begin
curr_num[3] = num[(num_length-curr_index)-1];
curr_num[2] = num[(num_length-curr_index)-2];
curr_num[1] = num[(num_length-curr_index)-3];
curr_num[0] = num[(num_length-curr_index)-4];
colour = image[curr_pixel+(curr_num*width*height)];
end
endmodule | module vga_hex_display(clk, enable, resetn, num, x, y, colour, writeEn); |
input clk;
input enable;
input resetn;
input [31:0] num;
output reg [7:0] x;
output reg [6:0] y;
output reg [2:0] colour;
output reg writeEn;
localparam width = 20;
localparam height = 30;
localparam num_length = 32;
localparam num_width = 4;
reg [7:0] x_start;
reg [7:0] y_start;
reg [9:0] curr_pixel;
reg [3:0] curr_num;
reg [6:0] curr_index;
reg [3:0] image [0 : width*height*16];
always @(posedge clk) begin
if (~resetn) begin
x_start <= 0;
y_start <= 0;
curr_pixel <= 0;
curr_index <= 0;
x <= 0;
y <= 0;
writeEn <= 0;
$readmemh ("images/0.list", image, 0, width*height-1);
$readmemh ("images/1.list", image, width*height, (width*height*2)-1);
$readmemh ("images/2.list", image, width*height*2, (width*height*3)-1);
$readmemh ("images/3.list", image, width*height*3, (width*height*4)-1);
$readmemh ("images/4.list", image, width*height*4, (width*height*5)-1);
$readmemh ("images/5.list", image, width*height*5, (width*height*6)-1);
$readmemh ("images/6.list", image, width*height*6, (width*height*7)-1);
$readmemh ("images/7.list", image, width*height*7, (width*height*8)-1);
$readmemh ("images/8.list", image, width*height*8, (width*height*9)-1);
$readmemh ("images/9.list", image, width*height*9, (width*height*10)-1);
$readmemh ("images/A.list", image, width*height*10, (width*height*11)-1);
$readmemh ("images/B.list", image, width*height*11, (width*height*12)-1);
$readmemh ("images/C.list", image, width*height*12, (width*height*13)-1);
$readmemh ("images/D.list", image, width*height*13, (width*height*14)-1);
$readmemh ("images/E.list", image, width*height*14, (width*height*15)-1);
$readmemh ("images/F.list", image, width*height*15, (width*height*16)-1);
end
else if (enable) begin
writeEn <= 1;
if (x < x_start+width-1'b1) begin
x <= x + 1'b1;
curr_pixel <= curr_pixel + 1'b1;
end
else if (y < y_start+height-1'b1) begin
x <= x_start;
y <= y + 1'b1;
curr_pixel <= curr_pixel + 1'b1;
end
else if (curr_index < (num_length-num_width)) begin
x <= x_start + width;
y <= y_start;
x_start <= x_start + width;
curr_pixel <= 1'b0;
curr_index <= curr_index + num_width;
end
else begin
curr_pixel <= 1'b0;
curr_index <= 1'b0;
x_start <= 1'b0;
x <= 1'b0;
y <= 1'b0;
end
end
end
always @(*)
begin
curr_num[3] = num[(num_length-curr_index)-1];
curr_num[2] = num[(num_length-curr_index)-2];
curr_num[1] = num[(num_length-curr_index)-3];
curr_num[0] = num[(num_length-curr_index)-4];
colour = image[curr_pixel+(curr_num*width*height)];
end
endmodule | 0 |
6,100 | data/full_repos/permissive/115074071/src/main/run.v | 115,074,071 | run.v | v | 17 | 27 | [] | [] | [] | [(1, 16)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115074071/src/main/run.v:7: Unsupported: Ignoring delay on this delayed statement.\n #12 rst = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115074071/src/main/run.v:10: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/115074071/src/main/run.v:12: Cannot find file containing module: \'mips\'\n mips mips(\n ^~~~\n ... Looked in:\n data/full_repos/permissive/115074071/src/main,data/full_repos/permissive/115074071/mips\n data/full_repos/permissive/115074071/src/main,data/full_repos/permissive/115074071/mips.v\n data/full_repos/permissive/115074071/src/main,data/full_repos/permissive/115074071/mips.sv\n mips\n mips.v\n mips.sv\n obj_dir/mips\n obj_dir/mips.v\n obj_dir/mips.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,834 | module | module run();
reg clk, rst;
initial begin
clk = 0;
rst = 1;
#12 rst = 0;
end
always #10 clk = ~clk;
mips mips(
.clk(clk),
.rst(rst)
);
endmodule | module run(); |
reg clk, rst;
initial begin
clk = 0;
rst = 1;
#12 rst = 0;
end
always #10 clk = ~clk;
mips mips(
.clk(clk),
.rst(rst)
);
endmodule | 7 |
6,101 | data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v | 115,074,071 | ALUCtrl.v | v | 71 | 80 | [] | [] | [] | [(73, 138)] | null | null | 1: b'%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:1: Cannot find include file: src/main/Define/signal_def.v\n`include "src/main/Define/signal_def.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115074071/src/main/Controller,data/full_repos/permissive/115074071/src/main/Define/signal_def.v\n data/full_repos/permissive/115074071/src/main/Controller,data/full_repos/permissive/115074071/src/main/Define/signal_def.v.v\n data/full_repos/permissive/115074071/src/main/Controller,data/full_repos/permissive/115074071/src/main/Define/signal_def.v.sv\n src/main/Define/signal_def.v\n src/main/Define/signal_def.v.v\n src/main/Define/signal_def.v.sv\n obj_dir/src/main/Define/signal_def.v\n obj_dir/src/main/Define/signal_def.v.v\n obj_dir/src/main/Define/signal_def.v.sv\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:2: Cannot find include file: src/main/Define/aluop_def.v\n`include "src/main/Define/aluop_def.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:3: Cannot find include file: src/main/Define/op_def.v\n`include "src/main/Define/op_def.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:16: Define or directive not defined: \'`ALUCTRL_ADD\'\n `ALUCTRL_ADD: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:16: syntax error, unexpected \':\', expecting endcase\n `ALUCTRL_ADD: begin\n ^\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:17: Define or directive not defined: \'`EXTOP_SIGNED\'\n EXTOp = `EXTOP_SIGNED;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:18: Define or directive not defined: \'`ALUOP_ADD\'\n ALUOp = `ALUOP_ADD;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:18: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ALUOp = `ALUOP_ADD;\n ^\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:20: Define or directive not defined: \'`ALUCTRL_ADDU\'\n `ALUCTRL_ADDU: begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:20: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ALUCTRL_ADDU: begin\n ^~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:21: Define or directive not defined: \'`EXTOP_UNSIGNED\'\n EXTOp = `EXTOP_UNSIGNED;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:22: Define or directive not defined: \'`ALUOP_ADD\'\n ALUOp = `ALUOP_ADD;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:22: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ALUOp = `ALUOP_ADD;\n ^\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:24: Define or directive not defined: \'`ALUCTRL_RTYPE\'\n `ALUCTRL_RTYPE: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:24: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ALUCTRL_RTYPE: begin\n ^~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:27: Define or directive not defined: \'`ALUCTRL_ITYPE\'\n `ALUCTRL_ITYPE: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:27: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ALUCTRL_ITYPE: begin\n ^~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:29: Define or directive not defined: \'`OP_ADDI\'\n `OP_ADDI: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:30: Define or directive not defined: \'`EXTOP_SIGNED\'\n EXTOp = `EXTOP_SIGNED;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:31: Define or directive not defined: \'`ALUOP_ADD\'\n ALUOp = `ALUOP_ADD;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:31: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ALUOp = `ALUOP_ADD;\n ^\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:33: Define or directive not defined: \'`OP_ADDIU\'\n `OP_ADDIU: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:33: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `OP_ADDIU: begin\n ^~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:34: Define or directive not defined: \'`EXTOP_UNSIGNED\'\n EXTOp = `EXTOP_UNSIGNED;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:35: Define or directive not defined: \'`ALUOP_ADDU\'\n ALUOp = `ALUOP_ADDU;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:35: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ALUOp = `ALUOP_ADDU;\n ^\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:37: Define or directive not defined: \'`OP_ANDI\'\n `OP_ANDI: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:37: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `OP_ANDI: begin\n ^~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:38: Define or directive not defined: \'`EXTOP_UNSIGNED\'\n EXTOp = `EXTOP_UNSIGNED;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:39: Define or directive not defined: \'`ALUOP_ANDI\'\n ALUOp = `ALUOP_ANDI;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:39: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ALUOp = `ALUOP_ANDI;\n ^\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:41: Define or directive not defined: \'`OP_ORI\'\n `OP_ORI: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:41: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `OP_ORI: begin\n ^~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:42: Define or directive not defined: \'`EXTOP_UNSIGNED\'\n EXTOp = `EXTOP_UNSIGNED;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:43: Define or directive not defined: \'`ALUOP_ORI\'\n ALUOp = `ALUOP_ORI;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ALUOp = `ALUOP_ORI;\n ^\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:45: Define or directive not defined: \'`OP_XORI\'\n `OP_XORI: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:45: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `OP_XORI: begin\n ^~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:46: Define or directive not defined: \'`EXTOP_UNSIGNED\'\n EXTOp = `EXTOP_UNSIGNED;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:47: Define or directive not defined: \'`ALUOP_XORI\'\n ALUOp = `ALUOP_XORI;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:47: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ALUOp = `ALUOP_XORI;\n ^\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:49: Define or directive not defined: \'`OP_LUI\'\n `OP_LUI: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:49: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `OP_LUI: begin\n ^~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:50: Define or directive not defined: \'`EXTOP_UNSIGNED\'\n EXTOp = `EXTOP_UNSIGNED;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:51: Define or directive not defined: \'`ALUOP_LUI\'\n ALUOp = `ALUOP_LUI;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:51: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ALUOp = `ALUOP_LUI;\n ^\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:53: Define or directive not defined: \'`OP_SLTI\'\n `OP_SLTI: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:53: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `OP_SLTI: begin\n ^~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:54: Define or directive not defined: \'`EXTOP_SIGNED\'\n EXTOp = `EXTOP_SIGNED;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/ALUCtrl.v:55: Define or directive not defined: \'`ALUOP_SLT\'\n ALUOp = `ALUOP_SLT;\n ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,835 | module | module ALUCtrl(
input [5:0] OP,
input [5:0] funct,
input [1:0] ALUCtrlOp,
output reg[5:0] ALUOp,
output reg[1:0] EXTOp
);
always@(*) begin
case(ALUCtrlOp)
`ALUCTRL_ADD: begin
EXTOp = `EXTOP_SIGNED;
ALUOp = `ALUOP_ADD;
end
`ALUCTRL_ADDU: begin
EXTOp = `EXTOP_UNSIGNED;
ALUOp = `ALUOP_ADD;
end
`ALUCTRL_RTYPE: begin
ALUOp = funct;
end
`ALUCTRL_ITYPE: begin
case(OP)
`OP_ADDI: begin
EXTOp = `EXTOP_SIGNED;
ALUOp = `ALUOP_ADD;
end
`OP_ADDIU: begin
EXTOp = `EXTOP_UNSIGNED;
ALUOp = `ALUOP_ADDU;
end
`OP_ANDI: begin
EXTOp = `EXTOP_UNSIGNED;
ALUOp = `ALUOP_ANDI;
end
`OP_ORI: begin
EXTOp = `EXTOP_UNSIGNED;
ALUOp = `ALUOP_ORI;
end
`OP_XORI: begin
EXTOp = `EXTOP_UNSIGNED;
ALUOp = `ALUOP_XORI;
end
`OP_LUI: begin
EXTOp = `EXTOP_UNSIGNED;
ALUOp = `ALUOP_LUI;
end
`OP_SLTI: begin
EXTOp = `EXTOP_SIGNED;
ALUOp = `ALUOP_SLT;
end
`OP_SLTIU: begin
EXTOp = `EXTOP_UNSIGNED;
ALUOp = `ALUOP_SLTU;
end
default: ALUOp = 2'b000000;
endcase
end
default:
ALUOp = 0;
endcase
end
endmodule | module ALUCtrl(
input [5:0] OP,
input [5:0] funct,
input [1:0] ALUCtrlOp,
output reg[5:0] ALUOp,
output reg[1:0] EXTOp
); |
always@(*) begin
case(ALUCtrlOp)
`ALUCTRL_ADD: begin
EXTOp = `EXTOP_SIGNED;
ALUOp = `ALUOP_ADD;
end
`ALUCTRL_ADDU: begin
EXTOp = `EXTOP_UNSIGNED;
ALUOp = `ALUOP_ADD;
end
`ALUCTRL_RTYPE: begin
ALUOp = funct;
end
`ALUCTRL_ITYPE: begin
case(OP)
`OP_ADDI: begin
EXTOp = `EXTOP_SIGNED;
ALUOp = `ALUOP_ADD;
end
`OP_ADDIU: begin
EXTOp = `EXTOP_UNSIGNED;
ALUOp = `ALUOP_ADDU;
end
`OP_ANDI: begin
EXTOp = `EXTOP_UNSIGNED;
ALUOp = `ALUOP_ANDI;
end
`OP_ORI: begin
EXTOp = `EXTOP_UNSIGNED;
ALUOp = `ALUOP_ORI;
end
`OP_XORI: begin
EXTOp = `EXTOP_UNSIGNED;
ALUOp = `ALUOP_XORI;
end
`OP_LUI: begin
EXTOp = `EXTOP_UNSIGNED;
ALUOp = `ALUOP_LUI;
end
`OP_SLTI: begin
EXTOp = `EXTOP_SIGNED;
ALUOp = `ALUOP_SLT;
end
`OP_SLTIU: begin
EXTOp = `EXTOP_UNSIGNED;
ALUOp = `ALUOP_SLTU;
end
default: ALUOp = 2'b000000;
endcase
end
default:
ALUOp = 0;
endcase
end
endmodule | 7 |
6,102 | data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v | 115,074,071 | BECtrl.v | v | 54 | 59 | [] | [] | [] | [(38, 89)] | null | null | 1: b'%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:1: Cannot find include file: src/main/Define/op_def.v\n`include "src/main/Define/op_def.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115074071/src/main/Controller,data/full_repos/permissive/115074071/src/main/Define/op_def.v\n data/full_repos/permissive/115074071/src/main/Controller,data/full_repos/permissive/115074071/src/main/Define/op_def.v.v\n data/full_repos/permissive/115074071/src/main/Controller,data/full_repos/permissive/115074071/src/main/Define/op_def.v.sv\n src/main/Define/op_def.v\n src/main/Define/op_def.v.v\n src/main/Define/op_def.v.sv\n obj_dir/src/main/Define/op_def.v\n obj_dir/src/main/Define/op_def.v.v\n obj_dir/src/main/Define/op_def.v.sv\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:16: Define or directive not defined: \'`OP_LBU\'\n `OP_LBU, `OP_LHU:\n ^~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:16: syntax error, unexpected \',\', expecting endcase\n `OP_LBU, `OP_LHU:\n ^\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:16: Define or directive not defined: \'`OP_LHU\'\n `OP_LBU, `OP_LHU:\n ^~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:23: Define or directive not defined: \'`OP_LB\'\n `OP_LB, `OP_LBU, `OP_SB:\n ^~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:23: Define or directive not defined: \'`OP_LBU\'\n `OP_LB, `OP_LBU, `OP_SB:\n ^~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:23: Define or directive not defined: \'`OP_SB\'\n `OP_LB, `OP_LBU, `OP_SB:\n ^~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:36: Define or directive not defined: \'`OP_LH\'\n `OP_LH, `OP_LHU, `OP_SH:\n ^~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:36: Define or directive not defined: \'`OP_LHU\'\n `OP_LH, `OP_LHU, `OP_SH:\n ^~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:36: Define or directive not defined: \'`OP_SH\'\n `OP_LH, `OP_LHU, `OP_SH:\n ^~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:45: Define or directive not defined: \'`OP_LW\'\n `OP_LW, `OP_SW:\n ^~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:45: Define or directive not defined: \'`OP_SW\'\n `OP_LW, `OP_SW:\n ^~~~~~\n%Error: Cannot continue\n' | 6,836 | module | module BECtrl(
input [5:0] OP,
input [31:0] addr,
output reg[3:0] BE,
output reg[11:0] fakeAddr,
output reg MemReadSigned
);
always@(*) begin
fakeAddr = addr[11:0];
case(OP)
`OP_LBU, `OP_LHU:
MemReadSigned = 0;
default:
MemReadSigned = 1;
endcase
case(OP)
`OP_LB, `OP_LBU, `OP_SB:
case(addr[1:0])
2'b00:
BE = 4'b0001;
2'b01:
BE = 4'b0010;
2'b10:
BE = 4'b0100;
2'b11:
BE = 4'b1000;
default:
BE = 4'b0001;
endcase
`OP_LH, `OP_LHU, `OP_SH:
case(addr[1:0])
2'b00:
BE = 4'b0011;
2'b10:
BE = 4'b1100;
default:
BE = 4'b0011;
endcase
`OP_LW, `OP_SW:
BE = 4'b1111;
default:
BE = 4'b1111;
endcase
end
endmodule | module BECtrl(
input [5:0] OP,
input [31:0] addr,
output reg[3:0] BE,
output reg[11:0] fakeAddr,
output reg MemReadSigned
); |
always@(*) begin
fakeAddr = addr[11:0];
case(OP)
`OP_LBU, `OP_LHU:
MemReadSigned = 0;
default:
MemReadSigned = 1;
endcase
case(OP)
`OP_LB, `OP_LBU, `OP_SB:
case(addr[1:0])
2'b00:
BE = 4'b0001;
2'b01:
BE = 4'b0010;
2'b10:
BE = 4'b0100;
2'b11:
BE = 4'b1000;
default:
BE = 4'b0001;
endcase
`OP_LH, `OP_LHU, `OP_SH:
case(addr[1:0])
2'b00:
BE = 4'b0011;
2'b10:
BE = 4'b1100;
default:
BE = 4'b0011;
endcase
`OP_LW, `OP_SW:
BE = 4'b1111;
default:
BE = 4'b1111;
endcase
end
endmodule | 7 |
6,105 | data/full_repos/permissive/115074071/src/main/Datapath/Branch.v | 115,074,071 | Branch.v | v | 35 | 97 | [] | [] | [] | [(37, 69)] | null | null | 1: b'%Error: data/full_repos/permissive/115074071/src/main/Datapath/Branch.v:1: Cannot find include file: src/main/Define/op_def.v\n`include "src/main/Define/op_def.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115074071/src/main/Datapath,data/full_repos/permissive/115074071/src/main/Define/op_def.v\n data/full_repos/permissive/115074071/src/main/Datapath,data/full_repos/permissive/115074071/src/main/Define/op_def.v.v\n data/full_repos/permissive/115074071/src/main/Datapath,data/full_repos/permissive/115074071/src/main/Define/op_def.v.sv\n src/main/Define/op_def.v\n src/main/Define/op_def.v.v\n src/main/Define/op_def.v.sv\n obj_dir/src/main/Define/op_def.v\n obj_dir/src/main/Define/op_def.v.v\n obj_dir/src/main/Define/op_def.v.sv\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/Branch.v:18: Define or directive not defined: \'`OP_BEQ\'\n `OP_BEQ : BranchSucceed = SrcA == SrcB ? 1 : 0;\n ^~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/Branch.v:18: syntax error, unexpected \':\', expecting endcase\n `OP_BEQ : BranchSucceed = SrcA == SrcB ? 1 : 0;\n ^\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/Branch.v:19: Define or directive not defined: \'`OP_BNE\'\n `OP_BNE : BranchSucceed = SrcA != SrcB ? 1 : 0;\n ^~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/Branch.v:20: Define or directive not defined: \'`OP_BLEZ\'\n `OP_BLEZ : BranchSucceed = $signed(SrcA) <= 0 ? 1 : 0;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/Branch.v:21: Define or directive not defined: \'`OP_BGTZ\'\n `OP_BGTZ : BranchSucceed = $signed(SrcA) > 0 ? 1 : 0;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/Branch.v:22: Define or directive not defined: \'`OP_BLTZ\'\n `OP_BLTZ, `OP_BGEZ : begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/Branch.v:22: Define or directive not defined: \'`OP_BGEZ\'\n `OP_BLTZ, `OP_BGEZ : begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/Branch.v:28: syntax error, unexpected \':\', expecting clocking\n default: BranchSucceed = 0;\n ^\n%Error: Cannot continue\n' | 6,839 | module | module Branch(
input clk,
input [31:0] SrcA,
input [31:0] SrcB,
input [5:0] OP,
input [4:0] Branch_funct,
output reg BranchSucceed
);
initial begin
BranchSucceed = 0;
end
always@(negedge clk) begin
$display("Branch ------ SrcA: %x", SrcA);
case (OP)
`OP_BEQ : BranchSucceed = SrcA == SrcB ? 1 : 0;
`OP_BNE : BranchSucceed = SrcA != SrcB ? 1 : 0;
`OP_BLEZ : BranchSucceed = $signed(SrcA) <= 0 ? 1 : 0;
`OP_BGTZ : BranchSucceed = $signed(SrcA) > 0 ? 1 : 0;
`OP_BLTZ, `OP_BGEZ : begin
if (Branch_funct == 5'b00000)
BranchSucceed = $signed(SrcA) < 0 ? 1 : 0;
else
BranchSucceed = $signed(SrcA) >= 0 ? 1 : 0;
end
default: BranchSucceed = 0;
endcase
if(BranchSucceed)
$display("JUMPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
end
endmodule | module Branch(
input clk,
input [31:0] SrcA,
input [31:0] SrcB,
input [5:0] OP,
input [4:0] Branch_funct,
output reg BranchSucceed
); |
initial begin
BranchSucceed = 0;
end
always@(negedge clk) begin
$display("Branch ------ SrcA: %x", SrcA);
case (OP)
`OP_BEQ : BranchSucceed = SrcA == SrcB ? 1 : 0;
`OP_BNE : BranchSucceed = SrcA != SrcB ? 1 : 0;
`OP_BLEZ : BranchSucceed = $signed(SrcA) <= 0 ? 1 : 0;
`OP_BGTZ : BranchSucceed = $signed(SrcA) > 0 ? 1 : 0;
`OP_BLTZ, `OP_BGEZ : begin
if (Branch_funct == 5'b00000)
BranchSucceed = $signed(SrcA) < 0 ? 1 : 0;
else
BranchSucceed = $signed(SrcA) >= 0 ? 1 : 0;
end
default: BranchSucceed = 0;
endcase
if(BranchSucceed)
$display("JUMPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
end
endmodule | 7 |
6,106 | data/full_repos/permissive/115074071/src/main/Datapath/im.v | 115,074,071 | im.v | v | 29 | 97 | [] | [] | [] | [(1, 28)] | null | data/verilator_xmls/c200219c-8689-46bd-a951-dad4150ae5a5.xml | null | 6,841 | module | module im(
input clk,
input [11:2] addr,
output reg[31:0] dout
);
reg [31:0] instrMem[1023:0];
integer fd, pointer;
reg [31:0] temp_instr;
initial begin
fd=$fopen("src/instr.txt","r");
$display("----------------------- IM start read interuction... ----------------------");
for (pointer = 0; !$feof(fd); pointer = pointer + 1) begin
$fscanf(fd, "%b\t", temp_instr);
instrMem[pointer] = temp_instr;
$display("IM read interuction %d: 0x%x", pointer, temp_instr);
end
$display("----------------------- Read interuction complete. ----------------------");
end
always @(posedge clk) begin
dout = instrMem[addr[11:2]][31:0];
end
endmodule | module im(
input clk,
input [11:2] addr,
output reg[31:0] dout
); |
reg [31:0] instrMem[1023:0];
integer fd, pointer;
reg [31:0] temp_instr;
initial begin
fd=$fopen("src/instr.txt","r");
$display("----------------------- IM start read interuction... ----------------------");
for (pointer = 0; !$feof(fd); pointer = pointer + 1) begin
$fscanf(fd, "%b\t", temp_instr);
instrMem[pointer] = temp_instr;
$display("IM read interuction %d: 0x%x", pointer, temp_instr);
end
$display("----------------------- Read interuction complete. ----------------------");
end
always @(posedge clk) begin
dout = instrMem[addr[11:2]][31:0];
end
endmodule | 7 |
6,107 | data/full_repos/permissive/115074071/src/main/Datapath/RF.v | 115,074,071 | RF.v | v | 41 | 100 | [] | [] | [] | [(1, 40)] | null | data/verilator_xmls/40831005-2362-4d84-9904-52dfc71c4ec8.xml | null | 6,842 | module | module RF(
input clk,
input RegWrite,
input [4:0] ReadAddr1,
input [4:0] ReadAddr2,
input [4:0] WriteAddr,
input [31:0] WriteData,
output [31:0] ReadData1,
output [31:0] ReadData2
);
reg[31:0] register[31:0];
integer i;
initial begin
for(i = 0; i < 32; i = i + 1)
register[i] = 0;
end
always@(negedge clk) begin
if (WriteAddr != 0 && RegWrite) begin
register[WriteAddr] = WriteData[31:0];
$display("RF Write: %x to %d", WriteData[31:0], WriteAddr);
end
$display("----------------------------------- RF Start ---------------------------------");
for(i = 0; i < 32; i = i + 1)
if (register[i] != 0) begin
$display("RF %d: %x", i, register[i]);
end
$display("----------------------------------- RF fin -----------------------------------");
end
assign ReadData1 = register[ReadAddr1];
assign ReadData2 = register[ReadAddr2];
endmodule | module RF(
input clk,
input RegWrite,
input [4:0] ReadAddr1,
input [4:0] ReadAddr2,
input [4:0] WriteAddr,
input [31:0] WriteData,
output [31:0] ReadData1,
output [31:0] ReadData2
); |
reg[31:0] register[31:0];
integer i;
initial begin
for(i = 0; i < 32; i = i + 1)
register[i] = 0;
end
always@(negedge clk) begin
if (WriteAddr != 0 && RegWrite) begin
register[WriteAddr] = WriteData[31:0];
$display("RF Write: %x to %d", WriteData[31:0], WriteAddr);
end
$display("----------------------------------- RF Start ---------------------------------");
for(i = 0; i < 32; i = i + 1)
if (register[i] != 0) begin
$display("RF %d: %x", i, register[i]);
end
$display("----------------------------------- RF fin -----------------------------------");
end
assign ReadData1 = register[ReadAddr1];
assign ReadData2 = register[ReadAddr2];
endmodule | 7 |
6,108 | data/full_repos/permissive/115074071/src/main/Datapath/SignExt.v | 115,074,071 | SignExt.v | v | 23 | 85 | [] | [] | [] | [(9, 29)] | null | null | 1: b'%Error: data/full_repos/permissive/115074071/src/main/Datapath/SignExt.v:1: Cannot find include file: src/main/Define/signal_def.v\n`include "src/main/Define/signal_def.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115074071/src/main/Datapath,data/full_repos/permissive/115074071/src/main/Define/signal_def.v\n data/full_repos/permissive/115074071/src/main/Datapath,data/full_repos/permissive/115074071/src/main/Define/signal_def.v.v\n data/full_repos/permissive/115074071/src/main/Datapath,data/full_repos/permissive/115074071/src/main/Define/signal_def.v.sv\n src/main/Define/signal_def.v\n src/main/Define/signal_def.v.v\n src/main/Define/signal_def.v.sv\n obj_dir/src/main/Define/signal_def.v\n obj_dir/src/main/Define/signal_def.v.v\n obj_dir/src/main/Define/signal_def.v.sv\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/SignExt.v:15: Define or directive not defined: \'`EXTOP_UNSIGNED\'\n `EXTOP_UNSIGNED: Immediate32 = {{16\'b0}, Immediate16[15:0]};\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/SignExt.v:15: syntax error, unexpected \':\', expecting endcase\n `EXTOP_UNSIGNED: Immediate32 = {{16\'b0}, Immediate16[15:0]};\n ^\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/SignExt.v:16: Define or directive not defined: \'`EXTOP_SIGNED\'\n `EXTOP_SIGNED: Immediate32 = {{16{Immediate16[15]}}, Immediate16[15:0]};\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/SignExt.v:17: Define or directive not defined: \'`EXTOP_INST\'\n `EXTOP_INST: Immediate32 = 32\'b0;\n ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n' | 6,843 | module | module EXT(
input clk,
input [15:0] Immediate16,
input [1:0] EXTOp,
output reg[31:0] Immediate32
);
initial begin
Immediate32 = 32'b00;
end
always @(negedge clk) begin
case(EXTOp)
`EXTOP_UNSIGNED: Immediate32 = {{16'b0}, Immediate16[15:0]};
`EXTOP_SIGNED: Immediate32 = {{16{Immediate16[15]}}, Immediate16[15:0]};
`EXTOP_INST: Immediate32 = 32'b0;
default: Immediate32 = {{16'b0}, Immediate16[15:0]};
endcase
$display("EXTOp: %b, EXT in: %x, out: %x", EXTOp, Immediate16, Immediate32);
end
endmodule | module EXT(
input clk,
input [15:0] Immediate16,
input [1:0] EXTOp,
output reg[31:0] Immediate32
); |
initial begin
Immediate32 = 32'b00;
end
always @(negedge clk) begin
case(EXTOp)
`EXTOP_UNSIGNED: Immediate32 = {{16'b0}, Immediate16[15:0]};
`EXTOP_SIGNED: Immediate32 = {{16{Immediate16[15]}}, Immediate16[15:0]};
`EXTOP_INST: Immediate32 = 32'b0;
default: Immediate32 = {{16'b0}, Immediate16[15:0]};
endcase
$display("EXTOp: %b, EXT in: %x, out: %x", EXTOp, Immediate16, Immediate32);
end
endmodule | 7 |
6,112 | data/full_repos/permissive/115141190/ClockCounterGenerator_w1s.v | 115,141,190 | ClockCounterGenerator_w1s.v | v | 27 | 63 | [] | [] | [] | [(1, 26)] | null | data/verilator_xmls/708c9274-53d1-45b2-a251-8a64340c5ee3.xml | null | 6,852 | module | module ClockCounterGenerator_w1s(clk, reset, enable, clk_cnt);
input wire clk, reset, enable;
output wire [25:0]clk_cnt;
reg [25:0]next_clk_cnt;
assign clk_cnt = next_clk_cnt;
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
next_clk_cnt <= 26'b0;
end
else begin
if (enable == 1) begin
next_clk_cnt <= clk_cnt + 26'd1;
if (clk_cnt == 26'd50000000) begin
next_clk_cnt <= 26'd0;
end
end
else begin
next_clk_cnt <= 26'd0;
end
end
end
endmodule | module ClockCounterGenerator_w1s(clk, reset, enable, clk_cnt); |
input wire clk, reset, enable;
output wire [25:0]clk_cnt;
reg [25:0]next_clk_cnt;
assign clk_cnt = next_clk_cnt;
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
next_clk_cnt <= 26'b0;
end
else begin
if (enable == 1) begin
next_clk_cnt <= clk_cnt + 26'd1;
if (clk_cnt == 26'd50000000) begin
next_clk_cnt <= 26'd0;
end
end
else begin
next_clk_cnt <= 26'd0;
end
end
end
endmodule | 0 |
6,113 | data/full_repos/permissive/115141190/ClockCounterGenerator_w1_64ms.v | 115,141,190 | ClockCounterGenerator_w1_64ms.v | v | 27 | 67 | [] | [] | [] | [(1, 26)] | null | data/verilator_xmls/1efb5cc5-0a2c-4997-bb04-e6cb0d90dac7.xml | null | 6,853 | module | module ClockCounterGenerator_w1_64ms(clk, reset, enable, clk_cnt);
input wire clk, reset, enable;
output wire [16:0]clk_cnt;
reg [16:0]next_clk_cnt;
assign clk_cnt = next_clk_cnt;
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
next_clk_cnt <= 17'b0;
end
else begin
if (enable == 1) begin
next_clk_cnt <= clk_cnt + 17'd1;
if (clk_cnt == 17'd82000) begin
next_clk_cnt <= 17'd0;
end
end
else begin
next_clk_cnt <= 17'd0;
end
end
end
endmodule | module ClockCounterGenerator_w1_64ms(clk, reset, enable, clk_cnt); |
input wire clk, reset, enable;
output wire [16:0]clk_cnt;
reg [16:0]next_clk_cnt;
assign clk_cnt = next_clk_cnt;
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
next_clk_cnt <= 17'b0;
end
else begin
if (enable == 1) begin
next_clk_cnt <= clk_cnt + 17'd1;
if (clk_cnt == 17'd82000) begin
next_clk_cnt <= 17'd0;
end
end
else begin
next_clk_cnt <= 17'd0;
end
end
end
endmodule | 0 |
6,114 | data/full_repos/permissive/115141190/Configure_FSM.v | 115,141,190 | Configure_FSM.v | v | 322 | 119 | [] | [] | [] | [(1, 321)] | null | data/verilator_xmls/48d20c91-e276-40e1-9e21-9e4098cb125f.xml | null | 6,854 | module | module Configure_FSM (clk, reset, enable, done, cnt_1s, cnt_1_64ms, next_instruction, db, enable_w1s, enable_w1_64ms);
input wire clk, reset;
input wire enable, done;
input wire [25:0]cnt_1s;
input wire [16:0]cnt_1_64ms;
output reg next_instruction;
output reg [9:0]db;
output reg enable_w1s, enable_w1_64ms;
parameter IDLE = 4'b0;
parameter FUNCTION_SET = 4'd1;
parameter ENTRY_MODE_SET = 4'd2;
parameter DISPLAY_ON_OFF = 4'd3;
parameter CLEAR_DISPLAY = 4'd4;
parameter WAIT_1_64MS = 4'd5;
parameter SET_DDRAM_ADDRESS_1 = 4'd6;
parameter WRITE_DATA_TO_DDRAM_1 = 4'd7;
parameter SET_DDRAM_ADDRESS_2 = 4'd8;
parameter WRITE_DATA_TO_DDRAM_2 = 4'd9;
parameter WAIT_1SEC = 4'd10;
wire [3:0]state;
reg [3:0]next_state;
reg [3:0]counter;
reg cursor_flag;
reg [7:0]line_1 [15:0];
reg [7:0]line_2 [15:0];
always @ (posedge clk) begin
line_1[0] <= 8'b0100_0011;
line_1[1] <= 8'b0110_1000;
line_1[2] <= 8'b0111_0010;
line_1[3] <= 8'b0110_1001;
line_1[4] <= 8'b0111_0011;
line_1[5] <= 8'b0010_0000;
line_1[6] <= 8'b0100_1010;
line_1[7] <= 8'b0110_1111;
line_1[8] <= 8'b0110_1000;
line_1[9] <= 8'b0110_1110;
line_1[10] <= 8'b0010_0000;
line_1[11] <= 8'b0011_0001;
line_1[12] <= 8'b0011_0010;
line_1[13] <= 8'b0011_0011;
line_1[14] <= 8'b0010_0000;
line_1[15] <= 8'b0010_0000;
line_2[0] <= 8'b0100_1000;
line_2[1] <= 8'b0110_0101;
line_2[2] <= 8'b0110_1100;
line_2[3] <= 8'b0110_1100;
line_2[4] <= 8'b0110_1111;
line_2[5] <= 8'b0010_0000;
line_2[6] <= 8'b0101_0111;
line_2[7] <= 8'b0110_1111;
line_2[8] <= 8'b0111_0010;
line_2[9] <= 8'b0110_1100;
line_2[10] <= 8'b0110_0100;
line_2[11] <= 8'b0010_0001;
line_2[12] <= 8'b0010_0001;
line_2[13] <= 8'b0010_0001;
if (cursor_flag == 1) begin
line_2[14] <= 8'b0010_0011;
end
else begin
line_2[14] <= 8'b0010_0000;
end
line_2[15] <= 8'b0010_0000;
end
assign state = next_state;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
next_state <= IDLE;
cursor_flag <= 1'b1;
end
else begin
case (state)
IDLE: begin
if (enable == 1'b1) begin
next_state <= FUNCTION_SET;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= IDLE;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
FUNCTION_SET: begin
if (done == 1'b1) begin
next_state <= ENTRY_MODE_SET;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= FUNCTION_SET;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
ENTRY_MODE_SET: begin
if (done == 1'b1) begin
next_state <= DISPLAY_ON_OFF;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= ENTRY_MODE_SET;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
DISPLAY_ON_OFF: begin
if (done == 1'b1) begin
next_state <= CLEAR_DISPLAY;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= DISPLAY_ON_OFF;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
CLEAR_DISPLAY: begin
if (done == 1'b1) begin
next_state <= WAIT_1_64MS;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b1;
end
else begin
next_state <= CLEAR_DISPLAY;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
WAIT_1_64MS: begin
if (cnt_1_64ms == 17'd82000) begin
next_state <= SET_DDRAM_ADDRESS_1;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= WAIT_1_64MS;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b1;
end
end
SET_DDRAM_ADDRESS_1: begin
if (done == 1'b1) begin
next_state <= WRITE_DATA_TO_DDRAM_1;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= SET_DDRAM_ADDRESS_1;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
WRITE_DATA_TO_DDRAM_1: begin
if (counter == 4'd15 && done == 1'b1) begin
next_state <= SET_DDRAM_ADDRESS_2;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
if (done == 1'b1) begin
next_state <= WRITE_DATA_TO_DDRAM_1;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= WRITE_DATA_TO_DDRAM_1;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
end
SET_DDRAM_ADDRESS_2: begin
if (done == 1'b1) begin
next_state <= WRITE_DATA_TO_DDRAM_2;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= SET_DDRAM_ADDRESS_2;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
WRITE_DATA_TO_DDRAM_2: begin
if (counter == 4'd15 && done == 1'b1) begin
next_state <= WAIT_1SEC;
next_instruction <= 1'b0;
enable_w1s <= 1'b1;
enable_w1_64ms <= 1'b0;
end
else begin
if (done == 1'b1) begin
next_state <= WRITE_DATA_TO_DDRAM_2;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= WRITE_DATA_TO_DDRAM_2;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
end
WAIT_1SEC: begin
if (cnt_1s == 26'd50000000) begin
next_state <= FUNCTION_SET;
cursor_flag <= ~cursor_flag;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= WAIT_1SEC;
next_instruction <= 1'b0;
enable_w1s <= 1'b1;
enable_w1_64ms <= 1'b0;
end
end
default: begin
next_state <= IDLE;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
endcase
end
end
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
db <= 10'b00_0000_0000;
counter <= 4'b0;
end
else begin
case (state)
IDLE: begin
db <= 10'b00_0000_0000;
end
FUNCTION_SET: begin
db <= 10'b00_0010_1000;
end
ENTRY_MODE_SET: begin
db <= 10'b00_0000_0110;
end
DISPLAY_ON_OFF: begin
db <= 10'b00_0000_1100;
end
CLEAR_DISPLAY: begin
db <= 10'b00_0000_0001;
end
WAIT_1_64MS: begin
db <= 10'b00_0000_0000;
end
SET_DDRAM_ADDRESS_1: begin
db <= 10'b00_1000_0000;
end
WRITE_DATA_TO_DDRAM_1: begin
db <= {2'b10, line_1[counter]};
if (done == 1) begin
counter <= counter + 1;
end
end
SET_DDRAM_ADDRESS_2: begin
db <= 10'b00_1100_0000;
end
WRITE_DATA_TO_DDRAM_2: begin
db <= {2'b10, line_2[counter]};
if (done == 1) begin
counter <= counter + 1;
end
end
WAIT_1SEC: begin
db <= 10'b00_0000_0000;
end
default: begin
db <= 10'b11_1111_1111;
end
endcase
end
end
endmodule | module Configure_FSM (clk, reset, enable, done, cnt_1s, cnt_1_64ms, next_instruction, db, enable_w1s, enable_w1_64ms); |
input wire clk, reset;
input wire enable, done;
input wire [25:0]cnt_1s;
input wire [16:0]cnt_1_64ms;
output reg next_instruction;
output reg [9:0]db;
output reg enable_w1s, enable_w1_64ms;
parameter IDLE = 4'b0;
parameter FUNCTION_SET = 4'd1;
parameter ENTRY_MODE_SET = 4'd2;
parameter DISPLAY_ON_OFF = 4'd3;
parameter CLEAR_DISPLAY = 4'd4;
parameter WAIT_1_64MS = 4'd5;
parameter SET_DDRAM_ADDRESS_1 = 4'd6;
parameter WRITE_DATA_TO_DDRAM_1 = 4'd7;
parameter SET_DDRAM_ADDRESS_2 = 4'd8;
parameter WRITE_DATA_TO_DDRAM_2 = 4'd9;
parameter WAIT_1SEC = 4'd10;
wire [3:0]state;
reg [3:0]next_state;
reg [3:0]counter;
reg cursor_flag;
reg [7:0]line_1 [15:0];
reg [7:0]line_2 [15:0];
always @ (posedge clk) begin
line_1[0] <= 8'b0100_0011;
line_1[1] <= 8'b0110_1000;
line_1[2] <= 8'b0111_0010;
line_1[3] <= 8'b0110_1001;
line_1[4] <= 8'b0111_0011;
line_1[5] <= 8'b0010_0000;
line_1[6] <= 8'b0100_1010;
line_1[7] <= 8'b0110_1111;
line_1[8] <= 8'b0110_1000;
line_1[9] <= 8'b0110_1110;
line_1[10] <= 8'b0010_0000;
line_1[11] <= 8'b0011_0001;
line_1[12] <= 8'b0011_0010;
line_1[13] <= 8'b0011_0011;
line_1[14] <= 8'b0010_0000;
line_1[15] <= 8'b0010_0000;
line_2[0] <= 8'b0100_1000;
line_2[1] <= 8'b0110_0101;
line_2[2] <= 8'b0110_1100;
line_2[3] <= 8'b0110_1100;
line_2[4] <= 8'b0110_1111;
line_2[5] <= 8'b0010_0000;
line_2[6] <= 8'b0101_0111;
line_2[7] <= 8'b0110_1111;
line_2[8] <= 8'b0111_0010;
line_2[9] <= 8'b0110_1100;
line_2[10] <= 8'b0110_0100;
line_2[11] <= 8'b0010_0001;
line_2[12] <= 8'b0010_0001;
line_2[13] <= 8'b0010_0001;
if (cursor_flag == 1) begin
line_2[14] <= 8'b0010_0011;
end
else begin
line_2[14] <= 8'b0010_0000;
end
line_2[15] <= 8'b0010_0000;
end
assign state = next_state;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
next_state <= IDLE;
cursor_flag <= 1'b1;
end
else begin
case (state)
IDLE: begin
if (enable == 1'b1) begin
next_state <= FUNCTION_SET;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= IDLE;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
FUNCTION_SET: begin
if (done == 1'b1) begin
next_state <= ENTRY_MODE_SET;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= FUNCTION_SET;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
ENTRY_MODE_SET: begin
if (done == 1'b1) begin
next_state <= DISPLAY_ON_OFF;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= ENTRY_MODE_SET;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
DISPLAY_ON_OFF: begin
if (done == 1'b1) begin
next_state <= CLEAR_DISPLAY;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= DISPLAY_ON_OFF;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
CLEAR_DISPLAY: begin
if (done == 1'b1) begin
next_state <= WAIT_1_64MS;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b1;
end
else begin
next_state <= CLEAR_DISPLAY;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
WAIT_1_64MS: begin
if (cnt_1_64ms == 17'd82000) begin
next_state <= SET_DDRAM_ADDRESS_1;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= WAIT_1_64MS;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b1;
end
end
SET_DDRAM_ADDRESS_1: begin
if (done == 1'b1) begin
next_state <= WRITE_DATA_TO_DDRAM_1;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= SET_DDRAM_ADDRESS_1;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
WRITE_DATA_TO_DDRAM_1: begin
if (counter == 4'd15 && done == 1'b1) begin
next_state <= SET_DDRAM_ADDRESS_2;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
if (done == 1'b1) begin
next_state <= WRITE_DATA_TO_DDRAM_1;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= WRITE_DATA_TO_DDRAM_1;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
end
SET_DDRAM_ADDRESS_2: begin
if (done == 1'b1) begin
next_state <= WRITE_DATA_TO_DDRAM_2;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= SET_DDRAM_ADDRESS_2;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
WRITE_DATA_TO_DDRAM_2: begin
if (counter == 4'd15 && done == 1'b1) begin
next_state <= WAIT_1SEC;
next_instruction <= 1'b0;
enable_w1s <= 1'b1;
enable_w1_64ms <= 1'b0;
end
else begin
if (done == 1'b1) begin
next_state <= WRITE_DATA_TO_DDRAM_2;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= WRITE_DATA_TO_DDRAM_2;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
end
end
WAIT_1SEC: begin
if (cnt_1s == 26'd50000000) begin
next_state <= FUNCTION_SET;
cursor_flag <= ~cursor_flag;
next_instruction <= 1'b1;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
else begin
next_state <= WAIT_1SEC;
next_instruction <= 1'b0;
enable_w1s <= 1'b1;
enable_w1_64ms <= 1'b0;
end
end
default: begin
next_state <= IDLE;
next_instruction <= 1'b0;
enable_w1s <= 1'b0;
enable_w1_64ms <= 1'b0;
end
endcase
end
end
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
db <= 10'b00_0000_0000;
counter <= 4'b0;
end
else begin
case (state)
IDLE: begin
db <= 10'b00_0000_0000;
end
FUNCTION_SET: begin
db <= 10'b00_0010_1000;
end
ENTRY_MODE_SET: begin
db <= 10'b00_0000_0110;
end
DISPLAY_ON_OFF: begin
db <= 10'b00_0000_1100;
end
CLEAR_DISPLAY: begin
db <= 10'b00_0000_0001;
end
WAIT_1_64MS: begin
db <= 10'b00_0000_0000;
end
SET_DDRAM_ADDRESS_1: begin
db <= 10'b00_1000_0000;
end
WRITE_DATA_TO_DDRAM_1: begin
db <= {2'b10, line_1[counter]};
if (done == 1) begin
counter <= counter + 1;
end
end
SET_DDRAM_ADDRESS_2: begin
db <= 10'b00_1100_0000;
end
WRITE_DATA_TO_DDRAM_2: begin
db <= {2'b10, line_2[counter]};
if (done == 1) begin
counter <= counter + 1;
end
end
WAIT_1SEC: begin
db <= 10'b00_0000_0000;
end
default: begin
db <= 10'b11_1111_1111;
end
endcase
end
end
endmodule | 0 |
6,115 | data/full_repos/permissive/115141190/Initialize_FSM.v | 115,141,190 | Initialize_FSM.v | v | 191 | 66 | [] | [] | [] | [(1, 190)] | null | data/verilator_xmls/d81387f0-f6cb-497c-ac30-07fce811945a.xml | null | 6,855 | module | module Initialize_FSM (clk, reset, clk_cnt, enable, SF_D, LCD_E);
input wire clk, reset;
input wire [19:0]clk_cnt;
output reg enable, LCD_E;
output reg [11:0]SF_D;
reg [3:0]next_state;
wire [3:0]state;
parameter OFF = 4'd0;
parameter STATE1 = 4'd1;
parameter STATE2 = 4'd2;
parameter STATE3 = 4'd3;
parameter STATE4 = 4'd4;
parameter STATE5 = 4'd5;
parameter STATE6 = 4'd6;
parameter STATE7 = 4'd7;
parameter STATE8 = 4'd8;
parameter STATE9 = 4'd9;
parameter DONE = 4'd10;
assign state = next_state;
always @ (posedge clk or posedge reset)
begin
if (reset == 1) begin
next_state <= OFF;
end
else begin
case (state)
OFF: begin
next_state <= STATE1;
end
STATE1: begin
if (clk_cnt == 20'd750000) begin
next_state <= STATE2;
end
else begin
next_state <= STATE1;
end
end
STATE2: begin
if (clk_cnt == 20'd750012) begin
next_state <= STATE3;
end
else begin
next_state <= STATE2;
end
end
STATE3: begin
if (clk_cnt == 20'd955012) begin
next_state <= STATE4;
end
else begin
next_state <= STATE3;
end
end
STATE4: begin
if (clk_cnt == 20'd955024) begin
next_state <= STATE5;
end
else begin
next_state <= STATE4;
end
end
STATE5: begin
if (clk_cnt == 20'd960024) begin
next_state <= STATE6;
end
else begin
next_state <= STATE5;
end
end
STATE6: begin
if (clk_cnt == 20'd960036) begin
next_state <= STATE7;
end
else begin
next_state <= STATE6;
end
end
STATE7: begin
if (clk_cnt == 20'd962036) begin
next_state <= STATE8;
end
else begin
next_state <= STATE7;
end
end
STATE8: begin
if (clk_cnt == 20'd962048) begin
next_state <= STATE9;
end
else begin
next_state <= STATE8;
end
end
STATE9: begin
if (clk_cnt == 20'd964048) begin
next_state <= DONE;
end
else begin
next_state <= STATE9;
end
end
DONE: begin
next_state <= DONE;
end
default: begin
next_state <= STATE1;
end
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1) begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:0] <= 12'd0;
end
else begin
case (state)
OFF: begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
STATE1: begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
STATE2: begin
enable <= 1'b0;
LCD_E <= 1'b1;
SF_D[11:8] <= 4'b0011;
end
STATE3: begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
STATE4: begin
enable <= 1'b0;
LCD_E <= 1'b1;
SF_D[11:8] <= 4'b0011;
end
STATE5: begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
STATE6: begin
enable <= 1'b0;
LCD_E <= 1'b1;
SF_D[11:8] <= 4'b0011;
end
STATE7: begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
STATE8: begin
enable <= 1'b0;
LCD_E <= 1'b1;
SF_D[11:8] <= 4'b0010;
end
STATE9: begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
DONE: begin
enable <= 1'b1;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
default: begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
endcase
end
end
endmodule | module Initialize_FSM (clk, reset, clk_cnt, enable, SF_D, LCD_E); |
input wire clk, reset;
input wire [19:0]clk_cnt;
output reg enable, LCD_E;
output reg [11:0]SF_D;
reg [3:0]next_state;
wire [3:0]state;
parameter OFF = 4'd0;
parameter STATE1 = 4'd1;
parameter STATE2 = 4'd2;
parameter STATE3 = 4'd3;
parameter STATE4 = 4'd4;
parameter STATE5 = 4'd5;
parameter STATE6 = 4'd6;
parameter STATE7 = 4'd7;
parameter STATE8 = 4'd8;
parameter STATE9 = 4'd9;
parameter DONE = 4'd10;
assign state = next_state;
always @ (posedge clk or posedge reset)
begin
if (reset == 1) begin
next_state <= OFF;
end
else begin
case (state)
OFF: begin
next_state <= STATE1;
end
STATE1: begin
if (clk_cnt == 20'd750000) begin
next_state <= STATE2;
end
else begin
next_state <= STATE1;
end
end
STATE2: begin
if (clk_cnt == 20'd750012) begin
next_state <= STATE3;
end
else begin
next_state <= STATE2;
end
end
STATE3: begin
if (clk_cnt == 20'd955012) begin
next_state <= STATE4;
end
else begin
next_state <= STATE3;
end
end
STATE4: begin
if (clk_cnt == 20'd955024) begin
next_state <= STATE5;
end
else begin
next_state <= STATE4;
end
end
STATE5: begin
if (clk_cnt == 20'd960024) begin
next_state <= STATE6;
end
else begin
next_state <= STATE5;
end
end
STATE6: begin
if (clk_cnt == 20'd960036) begin
next_state <= STATE7;
end
else begin
next_state <= STATE6;
end
end
STATE7: begin
if (clk_cnt == 20'd962036) begin
next_state <= STATE8;
end
else begin
next_state <= STATE7;
end
end
STATE8: begin
if (clk_cnt == 20'd962048) begin
next_state <= STATE9;
end
else begin
next_state <= STATE8;
end
end
STATE9: begin
if (clk_cnt == 20'd964048) begin
next_state <= DONE;
end
else begin
next_state <= STATE9;
end
end
DONE: begin
next_state <= DONE;
end
default: begin
next_state <= STATE1;
end
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1) begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:0] <= 12'd0;
end
else begin
case (state)
OFF: begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
STATE1: begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
STATE2: begin
enable <= 1'b0;
LCD_E <= 1'b1;
SF_D[11:8] <= 4'b0011;
end
STATE3: begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
STATE4: begin
enable <= 1'b0;
LCD_E <= 1'b1;
SF_D[11:8] <= 4'b0011;
end
STATE5: begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
STATE6: begin
enable <= 1'b0;
LCD_E <= 1'b1;
SF_D[11:8] <= 4'b0011;
end
STATE7: begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
STATE8: begin
enable <= 1'b0;
LCD_E <= 1'b1;
SF_D[11:8] <= 4'b0010;
end
STATE9: begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
DONE: begin
enable <= 1'b1;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
default: begin
enable <= 1'b0;
LCD_E <= 1'b0;
SF_D[11:8] <= 4'b0000;
end
endcase
end
end
endmodule | 0 |
6,116 | data/full_repos/permissive/115141190/Init_counter_generator.v | 115,141,190 | Init_counter_generator.v | v | 22 | 53 | [] | [] | [] | [(1, 21)] | null | data/verilator_xmls/55b59727-e06a-4ed6-9894-6745a7dd4728.xml | null | 6,856 | module | module Init_counter_generator (clk, reset, clk_cnt);
input wire clk, reset;
output wire [19:0]clk_cnt;
reg [19:0]next_clk_cnt;
assign clk_cnt = next_clk_cnt;
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
next_clk_cnt <= 20'b0;
end
else begin
next_clk_cnt <= clk_cnt + 20'd1;
if (clk_cnt == 20'd964048) begin
next_clk_cnt <= 20'd0;
end
end
end
endmodule | module Init_counter_generator (clk, reset, clk_cnt); |
input wire clk, reset;
output wire [19:0]clk_cnt;
reg [19:0]next_clk_cnt;
assign clk_cnt = next_clk_cnt;
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
next_clk_cnt <= 20'b0;
end
else begin
next_clk_cnt <= clk_cnt + 20'd1;
if (clk_cnt == 20'd964048) begin
next_clk_cnt <= 20'd0;
end
end
end
endmodule | 0 |
6,117 | data/full_repos/permissive/115141190/Instruction_ClockCounterGenerator.v | 115,141,190 | Instruction_ClockCounterGenerator.v | v | 24 | 71 | [] | [] | [] | [(1, 23)] | null | data/verilator_xmls/b2b598c6-eb5a-41b7-a8ca-400b75271a9e.xml | null | 6,857 | module | module Instruction_ClockCounterGenerator(clk, reset, clk_cnt, enable);
input wire clk, reset, enable;
output wire [11:0]clk_cnt;
reg [11:0]next_clk_cnt;
assign clk_cnt = next_clk_cnt;
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
next_clk_cnt <= 12'b0;
end
else begin
if (enable == 1) begin
next_clk_cnt <= clk_cnt + 12'd1;
if (clk_cnt == 12'd2080) begin
next_clk_cnt <= 12'd0;
end
end
end
end
endmodule | module Instruction_ClockCounterGenerator(clk, reset, clk_cnt, enable); |
input wire clk, reset, enable;
output wire [11:0]clk_cnt;
reg [11:0]next_clk_cnt;
assign clk_cnt = next_clk_cnt;
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
next_clk_cnt <= 12'b0;
end
else begin
if (enable == 1) begin
next_clk_cnt <= clk_cnt + 12'd1;
if (clk_cnt == 12'd2080) begin
next_clk_cnt <= 12'd0;
end
end
end
end
endmodule | 0 |
6,118 | data/full_repos/permissive/115141190/LCD_controller.v | 115,141,190 | LCD_controller.v | v | 122 | 89 | [] | [] | [] | [(1, 121)] | null | null | 1: b"%Error: data/full_repos/permissive/115141190/LCD_controller.v:51: Cannot find file containing module: 'Initialize_FSM'\nInitialize_FSM Initialize_FSM (\n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115141190,data/full_repos/permissive/115141190/Initialize_FSM\n data/full_repos/permissive/115141190,data/full_repos/permissive/115141190/Initialize_FSM.v\n data/full_repos/permissive/115141190,data/full_repos/permissive/115141190/Initialize_FSM.sv\n Initialize_FSM\n Initialize_FSM.v\n Initialize_FSM.sv\n obj_dir/Initialize_FSM\n obj_dir/Initialize_FSM.v\n obj_dir/Initialize_FSM.sv\n%Error: data/full_repos/permissive/115141190/LCD_controller.v:60: Cannot find file containing module: 'Init_counter_generator'\nInit_counter_generator Init_counter_generator (\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115141190/LCD_controller.v:69: Cannot find file containing module: 'Configure_FSM'\nConfigure_FSM Configure_FSM (\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115141190/LCD_controller.v:82: Cannot find file containing module: 'ClockCounterGenerator_w1_64ms'\nClockCounterGenerator_w1_64ms ClockCounterGenerator_w1_64ms (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115141190/LCD_controller.v:89: Cannot find file containing module: 'ClockCounterGenerator_w1s'\nClockCounterGenerator_w1s ClockCounterGenerator_w1s(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115141190/LCD_controller.v:99: Cannot find file containing module: 'Instruction_FSM'\nInstruction_FSM Instruction_FSM (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115141190/LCD_controller.v:113: Cannot find file containing module: 'Instruction_ClockCounterGenerator'\nInstruction_ClockCounterGenerator Instruction_ClockCounterGenerator (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n" | 6,859 | module | module LCD_controller (clk, reset, LCD_E, SF_D11, SF_D10, SF_D9, SF_D8, LCD_RS, LCD_RW);
input wire clk, reset;
output reg LCD_E;
output wire LCD_RS, LCD_RW;
output reg SF_D11, SF_D10, SF_D9, SF_D8;
wire [11:0]init_sfd;
wire [11:0]instr_sfd;
wire init_lcd_e, instr_lcd_e;
wire enable, done, next_instruction, enable_w1s, enable_w1_64ms, enable_instr_cnt;
wire [19:0]init_clk_cnt;
wire [11:0]instruction_clk_cnt;
wire [25:0]cnt_1s;
wire [16:0]cnt_1_64ms;
wire [9:0]db;
always @ (posedge clk or posedge reset) begin
if(reset) begin
SF_D11 <= 1'b0;
SF_D10 <= 1'b0;
SF_D9 <= 1'b0;
SF_D8 <= 1'b0;
LCD_E <= 1'b1;
end
else begin
if (enable == 1'b1) begin
SF_D11 <= instr_sfd[11];
SF_D10 <= instr_sfd[10];
SF_D9 <= instr_sfd[9];
SF_D8 <= instr_sfd[8];
LCD_E <= instr_lcd_e;
end
else begin
SF_D11 <= init_sfd[11];
SF_D10 <= init_sfd[10];
SF_D9 <= init_sfd[9];
SF_D8 <= init_sfd[8];
LCD_E <= init_lcd_e;
end
end
end
Initialize_FSM Initialize_FSM (
.clk (clk),
.reset (reset),
.clk_cnt (init_clk_cnt),
.enable (enable),
.SF_D (init_sfd),
.LCD_E (init_lcd_e)
);
Init_counter_generator Init_counter_generator (
.clk (clk),
.reset (reset),
.clk_cnt (init_clk_cnt)
);
Configure_FSM Configure_FSM (
.clk (clk),
.reset (reset),
.enable (enable),
.done (done),
.cnt_1s (cnt_1s),
.cnt_1_64ms (cnt_1_64ms),
.next_instruction (next_instruction),
.db (db),
.enable_w1s (enable_w1s),
.enable_w1_64ms (enable_w1_64ms)
);
ClockCounterGenerator_w1_64ms ClockCounterGenerator_w1_64ms (
.clk (clk),
.reset (reset),
.enable (enable_w1_64ms),
.clk_cnt (cnt_1_64ms)
);
ClockCounterGenerator_w1s ClockCounterGenerator_w1s(
.clk (clk),
.reset (reset),
.enable (enable_w1s),
.clk_cnt (cnt_1s)
);
Instruction_FSM Instruction_FSM (
.clk (clk),
.reset (reset),
.next_instruction (next_instruction),
.clk_cnt (instruction_clk_cnt),
.db (db),
.LCD_RS (LCD_RS),
.SF_D (instr_sfd),
.LCD_RW (LCD_RW),
.LCD_E (instr_lcd_e),
.done (done),
.enable (enable_instr_cnt)
);
Instruction_ClockCounterGenerator Instruction_ClockCounterGenerator (
.clk (clk),
.reset (reset),
.clk_cnt (instruction_clk_cnt),
.enable (enable_instr_cnt)
);
endmodule | module LCD_controller (clk, reset, LCD_E, SF_D11, SF_D10, SF_D9, SF_D8, LCD_RS, LCD_RW); |
input wire clk, reset;
output reg LCD_E;
output wire LCD_RS, LCD_RW;
output reg SF_D11, SF_D10, SF_D9, SF_D8;
wire [11:0]init_sfd;
wire [11:0]instr_sfd;
wire init_lcd_e, instr_lcd_e;
wire enable, done, next_instruction, enable_w1s, enable_w1_64ms, enable_instr_cnt;
wire [19:0]init_clk_cnt;
wire [11:0]instruction_clk_cnt;
wire [25:0]cnt_1s;
wire [16:0]cnt_1_64ms;
wire [9:0]db;
always @ (posedge clk or posedge reset) begin
if(reset) begin
SF_D11 <= 1'b0;
SF_D10 <= 1'b0;
SF_D9 <= 1'b0;
SF_D8 <= 1'b0;
LCD_E <= 1'b1;
end
else begin
if (enable == 1'b1) begin
SF_D11 <= instr_sfd[11];
SF_D10 <= instr_sfd[10];
SF_D9 <= instr_sfd[9];
SF_D8 <= instr_sfd[8];
LCD_E <= instr_lcd_e;
end
else begin
SF_D11 <= init_sfd[11];
SF_D10 <= init_sfd[10];
SF_D9 <= init_sfd[9];
SF_D8 <= init_sfd[8];
LCD_E <= init_lcd_e;
end
end
end
Initialize_FSM Initialize_FSM (
.clk (clk),
.reset (reset),
.clk_cnt (init_clk_cnt),
.enable (enable),
.SF_D (init_sfd),
.LCD_E (init_lcd_e)
);
Init_counter_generator Init_counter_generator (
.clk (clk),
.reset (reset),
.clk_cnt (init_clk_cnt)
);
Configure_FSM Configure_FSM (
.clk (clk),
.reset (reset),
.enable (enable),
.done (done),
.cnt_1s (cnt_1s),
.cnt_1_64ms (cnt_1_64ms),
.next_instruction (next_instruction),
.db (db),
.enable_w1s (enable_w1s),
.enable_w1_64ms (enable_w1_64ms)
);
ClockCounterGenerator_w1_64ms ClockCounterGenerator_w1_64ms (
.clk (clk),
.reset (reset),
.enable (enable_w1_64ms),
.clk_cnt (cnt_1_64ms)
);
ClockCounterGenerator_w1s ClockCounterGenerator_w1s(
.clk (clk),
.reset (reset),
.enable (enable_w1s),
.clk_cnt (cnt_1s)
);
Instruction_FSM Instruction_FSM (
.clk (clk),
.reset (reset),
.next_instruction (next_instruction),
.clk_cnt (instruction_clk_cnt),
.db (db),
.LCD_RS (LCD_RS),
.SF_D (instr_sfd),
.LCD_RW (LCD_RW),
.LCD_E (instr_lcd_e),
.done (done),
.enable (enable_instr_cnt)
);
Instruction_ClockCounterGenerator Instruction_ClockCounterGenerator (
.clk (clk),
.reset (reset),
.clk_cnt (instruction_clk_cnt),
.enable (enable_instr_cnt)
);
endmodule | 0 |
6,119 | data/full_repos/permissive/115141190/LCD_tb.v | 115,141,190 | LCD_tb.v | v | 31 | 35 | [] | [] | [] | [(1, 30)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115141190/LCD_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115141190/LCD_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #10 clk <= ~clk;\n ^\n%Error: data/full_repos/permissive/115141190/LCD_tb.v:8: Cannot find file containing module: \'LCD_controller\'\nLCD_controller LCD_controller (\n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115141190,data/full_repos/permissive/115141190/LCD_controller\n data/full_repos/permissive/115141190,data/full_repos/permissive/115141190/LCD_controller.v\n data/full_repos/permissive/115141190,data/full_repos/permissive/115141190/LCD_controller.sv\n LCD_controller\n LCD_controller.v\n LCD_controller.sv\n obj_dir/LCD_controller\n obj_dir/LCD_controller.v\n obj_dir/LCD_controller.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,860 | module | module LCD_tb ();
reg clk, reset;
wire LCD_E;
wire LCD_RS, LCD_RW;
wire SF_D11, SF_D10, SF_D9, SF_D8;
LCD_controller LCD_controller (
.clk (clk),
.reset (reset),
.LCD_E (LCD_E),
.LCD_RS (LCD_RS),
.LCD_RW (LCD_RW),
.SF_D11 (SF_D11),
.SF_D10 (SF_D10),
.SF_D9 (SF_D9),
.SF_D8 (SF_D8)
);
initial begin
clk = 0;
reset = 1;
#500 reset = 0;
end
always begin
#10 clk <= ~clk;
end
endmodule | module LCD_tb (); |
reg clk, reset;
wire LCD_E;
wire LCD_RS, LCD_RW;
wire SF_D11, SF_D10, SF_D9, SF_D8;
LCD_controller LCD_controller (
.clk (clk),
.reset (reset),
.LCD_E (LCD_E),
.LCD_RS (LCD_RS),
.LCD_RW (LCD_RW),
.SF_D11 (SF_D11),
.SF_D10 (SF_D10),
.SF_D9 (SF_D9),
.SF_D8 (SF_D8)
);
initial begin
clk = 0;
reset = 1;
#500 reset = 0;
end
always begin
#10 clk <= ~clk;
end
endmodule | 0 |
6,120 | data/full_repos/permissive/115141190/Part_A/Instruction.v | 115,141,190 | Instruction.v | v | 35 | 90 | [] | [] | [] | [(1, 34)] | null | null | 1: b"%Error: data/full_repos/permissive/115141190/Part_A/Instruction.v:13: Cannot find file containing module: 'Instruction_FSM'\nInstruction_FSM Instruction_FSM (\n^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115141190/Part_A,data/full_repos/permissive/115141190/Instruction_FSM\n data/full_repos/permissive/115141190/Part_A,data/full_repos/permissive/115141190/Instruction_FSM.v\n data/full_repos/permissive/115141190/Part_A,data/full_repos/permissive/115141190/Instruction_FSM.sv\n Instruction_FSM\n Instruction_FSM.v\n Instruction_FSM.sv\n obj_dir/Instruction_FSM\n obj_dir/Instruction_FSM.v\n obj_dir/Instruction_FSM.sv\n%Error: data/full_repos/permissive/115141190/Part_A/Instruction.v:27: Cannot find file containing module: 'Instruction_ClockCounterGenerator'\nInstruction_ClockCounterGenerator Instruction_ClockCounterGenerator (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 6,861 | module | module Instruction (clk, reset, next_instruction, db, LCD_RS, LCD_RW, LCD_E, SF_D, done);
input wire clk, reset;
input wire next_instruction;
input wire [9:0]db;
output wire LCD_RS, LCD_RW, LCD_E;
output wire [3:0]SF_D;
output wire done;
wire [11:0] clk_cnt;
wire enable;
Instruction_FSM Instruction_FSM (
.clk (clk),
.reset (reset),
.next_instruction (next_instruction),
.clk_cnt (clk_cnt),
.db (db),
.LCD_RS (LCD_RS),
.SF_D (SF_D),
.LCD_RW (LCD_RW),
.LCD_E (LCD_E),
.done (done),
.enable (enable)
);
Instruction_ClockCounterGenerator Instruction_ClockCounterGenerator (
.clk (clk),
.reset (reset),
.clk_cnt (clk_cnt),
.enable (enable)
);
endmodule | module Instruction (clk, reset, next_instruction, db, LCD_RS, LCD_RW, LCD_E, SF_D, done); |
input wire clk, reset;
input wire next_instruction;
input wire [9:0]db;
output wire LCD_RS, LCD_RW, LCD_E;
output wire [3:0]SF_D;
output wire done;
wire [11:0] clk_cnt;
wire enable;
Instruction_FSM Instruction_FSM (
.clk (clk),
.reset (reset),
.next_instruction (next_instruction),
.clk_cnt (clk_cnt),
.db (db),
.LCD_RS (LCD_RS),
.SF_D (SF_D),
.LCD_RW (LCD_RW),
.LCD_E (LCD_E),
.done (done),
.enable (enable)
);
Instruction_ClockCounterGenerator Instruction_ClockCounterGenerator (
.clk (clk),
.reset (reset),
.clk_cnt (clk_cnt),
.enable (enable)
);
endmodule | 0 |
6,121 | data/full_repos/permissive/115141190/Part_A/Instruction_FSM.v | 115,141,190 | Instruction_FSM.v | v | 230 | 111 | [] | [] | [] | [(1, 229)] | null | data/verilator_xmls/3fc57ad1-3269-4ec2-9322-9fe3ead75425.xml | null | 6,863 | module | module Instruction_FSM (clk, reset, next_instruction, clk_cnt, db, LCD_RS, SF_D, LCD_RW, LCD_E, done, enable);
input wire clk, reset;
input wire next_instruction;
input wire [11:0]clk_cnt;
input wire [9:0]db;
output reg LCD_RS, LCD_RW, LCD_E;
output reg [3:0]SF_D;
output reg done, enable;
parameter IDLE = 4'd0;
parameter SETUP_HIGH = 4'd1;
parameter ACTIVE_HIGH = 4'd2;
parameter HOLD_HIGH = 4'd3;
parameter WAIT = 4'd4;
parameter SETUP_LOW = 4'd5;
parameter ACTIVE_LOW = 4'd6;
parameter HOLD_LOW = 4'd7;
parameter DONE = 4'd8;
wire [3:0]state;
reg [3:0]next_state;
assign state = next_state;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
next_state <= IDLE;
end
else begin
case (state)
IDLE: begin
if (next_instruction == 1'b1) begin
next_state <= SETUP_HIGH;
end
else begin
next_state <= IDLE;
end
end
SETUP_HIGH: begin
if (clk_cnt == 12'd2) begin
next_state <= ACTIVE_HIGH;
end
else begin
next_state <= SETUP_HIGH;
end
end
ACTIVE_HIGH: begin
if (clk_cnt == 12'd14) begin
next_state <= HOLD_HIGH;
end
else begin
next_state <= ACTIVE_HIGH;
end
end
HOLD_HIGH: begin
if (clk_cnt == 12'd15) begin
next_state <= WAIT;
end
else begin
next_state <= HOLD_HIGH;
end
end
WAIT: begin
if (clk_cnt == 12'd65) begin
next_state <= SETUP_LOW;
end
else begin
next_state <= WAIT;
end
end
SETUP_LOW: begin
if (clk_cnt == 12'd67) begin
next_state <= ACTIVE_LOW;
end
else begin
next_state <= SETUP_LOW;
end
end
ACTIVE_LOW: begin
if (clk_cnt == 12'd79) begin
next_state <= HOLD_LOW;
end
else begin
next_state <= ACTIVE_LOW;
end
end
HOLD_LOW: begin
if (clk_cnt == 12'd80) begin
next_state <= DONE;
end
else begin
next_state <= HOLD_LOW;
end
end
DONE: begin
if (clk_cnt == 12'd2080) begin
next_state <= IDLE;
end
else begin
next_state <= DONE;
end
end
default: begin
next_state <= IDLE;
end
endcase
end
end
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= 4'b0;
end
else begin
case (state)
IDLE: begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= 4'b0;
enable <= 1'b0;
end
SETUP_HIGH: begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= db[7:4];
enable <= 1'b1;
end
ACTIVE_HIGH: begin
LCD_E <= 1'b1;
LCD_RS <= db[9];
LCD_RW <= db[8];
SF_D <= db[7:4];
enable <= 1'b1;
end
HOLD_HIGH: begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= db[7:4];
enable <= 1'b1;
end
WAIT: begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= db[7:4];
enable <= 1'b1;
end
SETUP_LOW: begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= db[3:0];
enable <= 1'b1;
end
ACTIVE_LOW: begin
done <= 1'b0;
LCD_E <= 1'b1;
LCD_RS <= db[9];
LCD_RW <= db[8];
SF_D <= db[3:0];
enable <= 1'b1;
end
HOLD_LOW: begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= db[3:0];
enable <= 1'b1;
end
DONE: begin
if (clk_cnt == 12'd2080) begin
done <= 1'b1;
enable <= 1'b0;
end
else begin
enable <= 1'b1;
done <= 1'b0;
end
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= db[3:0];
end
default: begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= 4'b0;
enable <= 1'b0;
end
endcase
end
end
endmodule | module Instruction_FSM (clk, reset, next_instruction, clk_cnt, db, LCD_RS, SF_D, LCD_RW, LCD_E, done, enable); |
input wire clk, reset;
input wire next_instruction;
input wire [11:0]clk_cnt;
input wire [9:0]db;
output reg LCD_RS, LCD_RW, LCD_E;
output reg [3:0]SF_D;
output reg done, enable;
parameter IDLE = 4'd0;
parameter SETUP_HIGH = 4'd1;
parameter ACTIVE_HIGH = 4'd2;
parameter HOLD_HIGH = 4'd3;
parameter WAIT = 4'd4;
parameter SETUP_LOW = 4'd5;
parameter ACTIVE_LOW = 4'd6;
parameter HOLD_LOW = 4'd7;
parameter DONE = 4'd8;
wire [3:0]state;
reg [3:0]next_state;
assign state = next_state;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
next_state <= IDLE;
end
else begin
case (state)
IDLE: begin
if (next_instruction == 1'b1) begin
next_state <= SETUP_HIGH;
end
else begin
next_state <= IDLE;
end
end
SETUP_HIGH: begin
if (clk_cnt == 12'd2) begin
next_state <= ACTIVE_HIGH;
end
else begin
next_state <= SETUP_HIGH;
end
end
ACTIVE_HIGH: begin
if (clk_cnt == 12'd14) begin
next_state <= HOLD_HIGH;
end
else begin
next_state <= ACTIVE_HIGH;
end
end
HOLD_HIGH: begin
if (clk_cnt == 12'd15) begin
next_state <= WAIT;
end
else begin
next_state <= HOLD_HIGH;
end
end
WAIT: begin
if (clk_cnt == 12'd65) begin
next_state <= SETUP_LOW;
end
else begin
next_state <= WAIT;
end
end
SETUP_LOW: begin
if (clk_cnt == 12'd67) begin
next_state <= ACTIVE_LOW;
end
else begin
next_state <= SETUP_LOW;
end
end
ACTIVE_LOW: begin
if (clk_cnt == 12'd79) begin
next_state <= HOLD_LOW;
end
else begin
next_state <= ACTIVE_LOW;
end
end
HOLD_LOW: begin
if (clk_cnt == 12'd80) begin
next_state <= DONE;
end
else begin
next_state <= HOLD_LOW;
end
end
DONE: begin
if (clk_cnt == 12'd2080) begin
next_state <= IDLE;
end
else begin
next_state <= DONE;
end
end
default: begin
next_state <= IDLE;
end
endcase
end
end
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= 4'b0;
end
else begin
case (state)
IDLE: begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= 4'b0;
enable <= 1'b0;
end
SETUP_HIGH: begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= db[7:4];
enable <= 1'b1;
end
ACTIVE_HIGH: begin
LCD_E <= 1'b1;
LCD_RS <= db[9];
LCD_RW <= db[8];
SF_D <= db[7:4];
enable <= 1'b1;
end
HOLD_HIGH: begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= db[7:4];
enable <= 1'b1;
end
WAIT: begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= db[7:4];
enable <= 1'b1;
end
SETUP_LOW: begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= db[3:0];
enable <= 1'b1;
end
ACTIVE_LOW: begin
done <= 1'b0;
LCD_E <= 1'b1;
LCD_RS <= db[9];
LCD_RW <= db[8];
SF_D <= db[3:0];
enable <= 1'b1;
end
HOLD_LOW: begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= db[3:0];
enable <= 1'b1;
end
DONE: begin
if (clk_cnt == 12'd2080) begin
done <= 1'b1;
enable <= 1'b0;
end
else begin
enable <= 1'b1;
done <= 1'b0;
end
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= db[3:0];
end
default: begin
done <= 1'b0;
LCD_E <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
SF_D <= 4'b0;
enable <= 1'b0;
end
endcase
end
end
endmodule | 0 |
6,122 | data/full_repos/permissive/115141190/Part_A/Instruction_tb.v | 115,141,190 | Instruction_tb.v | v | 40 | 65 | [] | [] | [] | [(1, 39)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115141190/Part_A/Instruction_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #100 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115141190/Part_A/Instruction_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #20 next_instruction <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115141190/Part_A/Instruction_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #50000 next_instruction <= 1\'b1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115141190/Part_A/Instruction_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #20 next_instruction <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115141190/Part_A/Instruction_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10 clk <= ~clk;\n ^\n%Error: data/full_repos/permissive/115141190/Part_A/Instruction_tb.v:8: Cannot find file containing module: \'Instruction\'\n Instruction Instruction (\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115141190/Part_A,data/full_repos/permissive/115141190/Instruction\n data/full_repos/permissive/115141190/Part_A,data/full_repos/permissive/115141190/Instruction.v\n data/full_repos/permissive/115141190/Part_A,data/full_repos/permissive/115141190/Instruction.sv\n Instruction\n Instruction.v\n Instruction.sv\n obj_dir/Instruction\n obj_dir/Instruction.v\n obj_dir/Instruction.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,864 | module | module Instruction_tb ();
reg clk, reset, next_instruction;
reg [9:0]db;
wire LCD_RS, LCD_RW, LCD_E, done;
wire [3:0]SF_D;
Instruction Instruction (
.clk (clk),
.reset (reset),
.next_instruction (next_instruction),
.db (db),
.LCD_RS (LCD_RS),
.LCD_RW (LCD_RW),
.LCD_E (LCD_E),
.SF_D (SF_D),
.done (done)
);
initial begin
next_instruction <= 1'b0;
clk = 0;
reset = 1;
#100 reset = 0;
next_instruction <= 1'b1;
db <= 10'b00_1010_0101;
#20 next_instruction <= 1'b0;
#50000 next_instruction <= 1'b1;
db <= 10'b00_1111_0000;
#20 next_instruction <= 1'b0;
end
always begin
#10 clk <= ~clk;
end
endmodule | module Instruction_tb (); |
reg clk, reset, next_instruction;
reg [9:0]db;
wire LCD_RS, LCD_RW, LCD_E, done;
wire [3:0]SF_D;
Instruction Instruction (
.clk (clk),
.reset (reset),
.next_instruction (next_instruction),
.db (db),
.LCD_RS (LCD_RS),
.LCD_RW (LCD_RW),
.LCD_E (LCD_E),
.SF_D (SF_D),
.done (done)
);
initial begin
next_instruction <= 1'b0;
clk = 0;
reset = 1;
#100 reset = 0;
next_instruction <= 1'b1;
db <= 10'b00_1010_0101;
#20 next_instruction <= 1'b0;
#50000 next_instruction <= 1'b1;
db <= 10'b00_1111_0000;
#20 next_instruction <= 1'b0;
end
always begin
#10 clk <= ~clk;
end
endmodule | 0 |
6,123 | data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v | 115,162,999 | data_ram.v | v | 66 | 50 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 25: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:2: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.v\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:9: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] addr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`DataAddrBus] addr,\n ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`DataBus] data_i,\n ^~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:11: Define or directive not defined: \'`DataBus\'\n input wire[`DataBus] data_i,\n ^~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:12: Define or directive not defined: \'`DataBus\'\n output reg[`DataBus] data_o\n ^~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:19: Define or directive not defined: \'`DataMemNum\'\n reg[7 : 0] data_mem[0: `DataMemNum - 1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:21: syntax error, unexpected always\n always @ (posedge clk) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:22: Define or directive not defined: \'`ChipDisable\'\n if (ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:24: Define or directive not defined: \'`WriteEnable\'\n end else if(we == `WriteEnable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:49: Define or directive not defined: \'`ChipDisable\'\n if (ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:50: Define or directive not defined: \'`ZeroWord\'\n data_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:51: Define or directive not defined: \'`WriteDisable\'\n end else if(we == `WriteDisable) begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:61: Define or directive not defined: \'`ZeroWord\'\n data_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: Exiting due to 14 error(s)\n' | 6,867 | module | module data_ram(
input wire clk,
input wire ce,
input wire we,
input wire[`DataAddrBus] addr,
input wire[3:0] sel,
input wire[`DataBus] data_i,
output reg[`DataBus] data_o
);
reg[7 : 0] data_mem[0: `DataMemNum - 1];
always @ (posedge clk) begin
if (ce == `ChipDisable) begin
end else if(we == `WriteEnable) begin
if (sel == 4'b0100) begin
{data_mem[addr + 3],
data_mem[addr + 2],
data_mem[addr + 1],
data_mem[addr]} <= data_i[31:0];
end
else if (sel == 4'b0010) begin
{data_mem[addr + 1],
data_mem[addr]} <= data_i[15:0];
end
else if (sel == 4'b0001) begin
{data_mem[addr]} <= data_i[7:0];
end
end
end
always @ (*) begin
if (ce == `ChipDisable) begin
data_o <= `ZeroWord;
end else if(we == `WriteDisable) begin
data_o <= {data_mem[addr + 3],
data_mem[addr + 2],
data_mem[addr + 1],
data_mem[addr]};
end else begin
data_o <= `ZeroWord;
end
end
endmodule | module data_ram(
input wire clk,
input wire ce,
input wire we,
input wire[`DataAddrBus] addr,
input wire[3:0] sel,
input wire[`DataBus] data_i,
output reg[`DataBus] data_o
); |
reg[7 : 0] data_mem[0: `DataMemNum - 1];
always @ (posedge clk) begin
if (ce == `ChipDisable) begin
end else if(we == `WriteEnable) begin
if (sel == 4'b0100) begin
{data_mem[addr + 3],
data_mem[addr + 2],
data_mem[addr + 1],
data_mem[addr]} <= data_i[31:0];
end
else if (sel == 4'b0010) begin
{data_mem[addr + 1],
data_mem[addr]} <= data_i[15:0];
end
else if (sel == 4'b0001) begin
{data_mem[addr]} <= data_i[7:0];
end
end
end
always @ (*) begin
if (ce == `ChipDisable) begin
data_o <= `ZeroWord;
end else if(we == `WriteDisable) begin
data_o <= {data_mem[addr + 3],
data_mem[addr + 2],
data_mem[addr + 1],
data_mem[addr]};
end else begin
data_o <= `ZeroWord;
end
end
endmodule | 3 |
6,125 | data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v | 115,162,999 | id.v | v | 520 | 122 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 6: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:3: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.v\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:9: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] pc_i,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] pc_i,\n ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:10: Define or directive not defined: \'`InstBus\'\n input wire[`InstBus] inst_i,\n ^~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:13: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus] ex_aluop_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] ex_wdata_i,\n ^~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:17: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] ex_wdata_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:18: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] ex_wd_i,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] mem_wdata_i,\n ^~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:22: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] mem_wdata_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:23: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] mem_wd_i,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:28: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg1_data_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:29: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg2_data_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:33: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg reg2_read_o,\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:34: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] reg1_addr_o,\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:34: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] reg1_addr_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:35: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] reg2_addr_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:38: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus] aluop_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:39: Define or directive not defined: \'`AluSelBus\'\n output reg[`AluSelBus] alusel_o,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:40: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] reg1_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:41: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] reg2_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:42: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:44: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output wire[`RegBus] inst_o,\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:44: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus] inst_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:48: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] branch_target_address_o,\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:48: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] branch_target_address_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:49: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] link_addr_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:58: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] imm;\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:58: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] imm;\n ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:60: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] pc_plus_8;\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:60: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] pc_plus_8;\n ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:61: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] pc_plus_4;\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:61: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] pc_plus_4;\n ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:62: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] imm_sll2_signedext;\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:62: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] imm_sll2_signedext;\n ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:69: syntax error, unexpected assign\n assign pc_plus_8 = pc_i + 8;\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:75: Define or directive not defined: \'`EXE_LB_OP\'\n assign pre_inst_is_load = ((ex_aluop_i == `EXE_LB_OP) ||\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:76: Define or directive not defined: \'`EXE_LBU_OP\'\n (ex_aluop_i == `EXE_LBU_OP)||\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:77: Define or directive not defined: \'`EXE_LH_OP\'\n (ex_aluop_i == `EXE_LH_OP) ||\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:78: Define or directive not defined: \'`EXE_LHU_OP\'\n (ex_aluop_i == `EXE_LHU_OP)||\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:79: Define or directive not defined: \'`EXE_LW_OP\'\n (ex_aluop_i == `EXE_LW_OP))? 1\'b1 : 1\'b0;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:86: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:87: Define or directive not defined: \'`EXE_NOP_OP\'\n aluop_o <= `EXE_NOP_OP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:88: Define or directive not defined: \'`EXE_RES_NOP\'\n alusel_o <= `EXE_RES_NOP;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:89: Define or directive not defined: \'`NOPRegAddr\'\n wd_o <= `NOPRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:90: Define or directive not defined: \'`WriteDisable\'\n wreg_o <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:91: Define or directive not defined: \'`InstValid\'\n instvalid <= `InstValid;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:93: Define or directive not defined: \'`NOPRegAddr\'\n reg1_addr_o <= `NOPRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:94: Define or directive not defined: \'`NOPRegAddr\'\n reg2_addr_o <= `NOPRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/id.v:96: Define or directive not defined: \'`ZeroWord\'\n link_addr_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,871 | module | module id(
input wire rst,
input wire[`InstAddrBus] pc_i,
input wire[`InstBus] inst_i,
input wire[`AluOpBus] ex_aluop_i,
input wire ex_wreg_i,
input wire[`RegBus] ex_wdata_i,
input wire[`RegAddrBus] ex_wd_i,
input wire mem_wreg_i,
input wire[`RegBus] mem_wdata_i,
input wire[`RegAddrBus] mem_wd_i,
input wire[`RegBus] reg1_data_i,
input wire[`RegBus] reg2_data_i,
output reg reg1_read_o,
output reg reg2_read_o,
output reg[`RegAddrBus] reg1_addr_o,
output reg[`RegAddrBus] reg2_addr_o,
output reg[`AluOpBus] aluop_o,
output reg[`AluSelBus] alusel_o,
output reg[`RegBus] reg1_o,
output reg[`RegBus] reg2_o,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output wire[`RegBus] inst_o,
output reg branch_flag_o,
output reg[`RegBus] branch_target_address_o,
output reg[`RegBus] link_addr_o,
output reg stallreq
);
wire[6:0] op = inst_i[6:0];
wire[2:0] op2 = inst_i[14:12];
wire[6:0] op3 = inst_i[31:25];
reg[`RegBus] imm;
reg instvalid;
wire[`RegBus] pc_plus_8;
wire[`RegBus] pc_plus_4;
reg[`RegBus] imm_sll2_signedext;
reg stallreq_for_reg1_loadrelate;
reg stallreq_for_reg2_loadrelate;
wire pre_inst_is_load;
wire stallreq_tmp;
assign pc_plus_8 = pc_i + 8;
assign pc_plus_4 = pc_i +4;
assign stallreq_tmp = stallreq_for_reg1_loadrelate | stallreq_for_reg2_loadrelate;
assign pre_inst_is_load = ((ex_aluop_i == `EXE_LB_OP) ||
(ex_aluop_i == `EXE_LBU_OP)||
(ex_aluop_i == `EXE_LH_OP) ||
(ex_aluop_i == `EXE_LHU_OP)||
(ex_aluop_i == `EXE_LW_OP))? 1'b1 : 1'b0;
assign inst_o = inst_i;
always @ ( * ) begin
stallreq <= stallreq_tmp;
end
always @ (*) begin
if (rst == `RstEnable) begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
instvalid <= `InstValid;
reg2_read_o <= 1'b0;
reg1_addr_o <= `NOPRegAddr;
reg2_addr_o <= `NOPRegAddr;
imm <= 32'h0;
link_addr_o <= `ZeroWord;
branch_target_address_o <= `ZeroWord;
branch_flag_o <= `NotBranch;
stallreq <= `NoStop;
end else begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= inst_i[11:7];
wreg_o <= `WriteDisable;
instvalid <= `InstInvalid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= inst_i[19:15];
reg2_addr_o <= inst_i[24:20];
imm <= `ZeroWord;
link_addr_o <= `ZeroWord;
branch_target_address_o <= `ZeroWord;
branch_flag_o <= `NotBranch;
stallreq <= `NoStop;
case (op)
`EXE_OP_IMM:
begin
case(op2)
`EXE_ORI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{21{inst_i[31]}}, inst_i[30:20]}; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_ANDI:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{21{inst_i[31]}}, inst_i[30:20]};
wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_XORI:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{21{inst_i[31]}}, inst_i[30:20]};
wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_SLTI:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{21{inst_i[31]}}, inst_i[30:20]}; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_SLTIU:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{21{inst_i[31]}}, inst_i[30:20]}; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_ADDI:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{21{inst_i[31]}}, inst_i[30:20]}; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_SLLI:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= inst_i[24:20]; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
3'b101:
begin
case(op3)
`EXE_SRLI:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= inst_i[24:20]; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_SRAI:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= inst_i[24:20]; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
endcase
end
default: begin
end
endcase
end
`EXE_OP:
begin
case (op2)
`EXE_OR:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_AND:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_XOR:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SLL:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SLT:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SLTU:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
3'b000:
begin
case(op3)
`EXE_ADD:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SUB:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SUB_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
endcase
end
3'b101:
begin
case(op3)
`EXE_SRL:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SRA:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
endcase
end
default:
begin
end
endcase
end
`EXE_JAL:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_JAL_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
link_addr_o <= pc_plus_4;
wd_o <= inst_i[11:7];
branch_target_address_o <= {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:25], inst_i[24:21], 1'b0} + pc_i;
branch_flag_o <= `Branch;
stallreq <= `Stop;
instvalid <= `InstValid;
end
`EXE_JALR:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_JALR_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
wd_o <= inst_i[11:7];
link_addr_o <= pc_plus_4;
imm_sll2_signedext <= {{21{inst_i[21]}}, inst_i[30:20]} + reg1_o;
branch_target_address_o <= ( {{21{inst_i[31]}}, inst_i[30:20]} + reg1_o) & (-1 ^ 1);
branch_flag_o <= `Branch;
stallreq <= `Stop;
instvalid <= `InstValid;
end
`EXE_LUI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_LUI_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b0; reg2_read_o <= 1'b0;
imm <= {inst_i[31:12], 12'b0}; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_AUIPC:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_AUIPC_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b0; reg2_read_o <= 1'b0;
imm <= {inst_i[31:12], 12'b0} + pc_i; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_LOAD:
begin
case(op2)
`EXE_LB: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_LB_OP;
alusel_o <= `EXE_RES_LOAD_STORE; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
wd_o <= inst_i[11:7]; instvalid <= `InstValid;
end
`EXE_LBU: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_LBU_OP;
alusel_o <= `EXE_RES_LOAD_STORE; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
wd_o <= inst_i[11:7]; instvalid <= `InstValid;
end
`EXE_LH: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_LH_OP;
alusel_o <= `EXE_RES_LOAD_STORE; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
wd_o <= inst_i[11:7]; instvalid <= `InstValid;
end
`EXE_LHU: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_LHU_OP;
alusel_o <= `EXE_RES_LOAD_STORE; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
wd_o <= inst_i[11:7]; instvalid <= `InstValid;
end
`EXE_LW: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_LW_OP;
alusel_o <= `EXE_RES_LOAD_STORE; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
wd_o <= inst_i[11:7]; instvalid <= `InstValid;
end
endcase
end
`EXE_STORE:
begin
case(op2)
`EXE_SB: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_SB_OP;
reg1_read_o <= 1'b1; reg2_read_o <= 1'b1; instvalid <= `InstValid;
alusel_o <= `EXE_RES_LOAD_STORE;
end
`EXE_SH: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_SH_OP;
reg1_read_o <= 1'b1; reg2_read_o <= 1'b1; instvalid <= `InstValid;
alusel_o <= `EXE_RES_LOAD_STORE;
end
`EXE_SW: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_SW_OP;
reg1_read_o <= 1'b1; reg2_read_o <= 1'b1; instvalid <= `InstValid;
alusel_o <= `EXE_RES_LOAD_STORE;
end
endcase
end
`EXE_BRANCH:
begin
case(op2)
`EXE_BEQ:
begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_BEQ_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
imm_sll2_signedext <= {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
if($signed(reg1_o) == $signed(reg2_o))
begin
branch_target_address_o <= pc_i + {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
branch_flag_o <= `Branch;
stallreq <= `Stop;
end
end
`EXE_BNE:
begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_BNE_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
imm_sll2_signedext <= {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
if($signed(reg1_o) != $signed(reg2_o))
begin
branch_target_address_o <= pc_i + {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
branch_flag_o <= `Branch;
stallreq <= `Stop;
end
end
`EXE_BGE:
begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_BGE_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
imm_sll2_signedext <={{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
if($signed(reg1_o) >= $signed(reg2_o))
begin
branch_target_address_o <= pc_i + {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
branch_flag_o <= `Branch;
stallreq <= `Stop;
end
end
`EXE_BGEU:
begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_BGEU_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
imm_sll2_signedext <= {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
if(reg1_o >= reg2_o)
begin
branch_target_address_o <= pc_i + {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
branch_flag_o <= `Branch;
stallreq <= `Stop;
end
end
`EXE_BLT:
begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_BLT_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
imm_sll2_signedext <={{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
if($signed(reg1_o) <= $signed(reg2_o))
begin
branch_target_address_o <= pc_i + {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
branch_flag_o <= `Branch;
stallreq <= `Stop;
end
end
`EXE_BLTU:
begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_BLTU_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
imm_sll2_signedext <={{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
if(reg1_o <= reg2_o)
begin
branch_target_address_o <= pc_i + {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
branch_flag_o <= `Branch;
stallreq <= `Stop;
end
end
endcase
end
default: begin
end
endcase
end
end
always @ (*) begin
stallreq_for_reg1_loadrelate <= `NoStop;
if(rst == `RstEnable) begin
reg1_o <= `ZeroWord;
end
else if (reg1_addr_o == 0) begin
reg1_o <= 0;
end
else if(pre_inst_is_load == 1'b1 && ex_wd_i == reg1_addr_o
&& reg1_read_o == 1'b1 ) begin
stallreq_for_reg1_loadrelate <= `Stop;
end
<<<<<<< HEAD
else if (aluop_o == `EXE_JALR_OP) begin
reg1_o <= link_addr_o;
end else if((reg1_read_o == 1'b1) && (ex_wreg_i == 1'b1)
=======
else if((reg1_read_o == 1'b1) && (ex_wreg_i == 1'b1)
>>>>>>> dev
&& (ex_wd_i == reg1_addr_o) && (reg1_addr_o != 5'h0)) begin
reg1_o <= ex_wdata_i;
end else if((reg1_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg1_addr_o) && (reg1_addr_o != 5'h0)) begin
reg1_o <= mem_wdata_i;
end else if(reg1_read_o == 1'b1) begin
reg1_o <= reg1_data_i;
end else if(reg1_read_o == 1'b0) begin
reg1_o <= imm;
end else begin
reg1_o <= `ZeroWord;
end
end
always @ (*) begin
stallreq_for_reg2_loadrelate <= `NoStop;
if(rst == `RstEnable) begin
reg2_o <= `ZeroWord;
end
else if((reg2_read_o == 1'b1) && (ex_wreg_i == 1'b1)
&& (ex_wd_i == reg2_addr_o) && (reg2_addr_o != 5'h0)) begin
reg2_o <= ex_wdata_i;
end
else if(pre_inst_is_load == 1'b1 && ex_wd_i == reg2_addr_o
&& reg2_read_o == 1'b1 ) begin
stallreq_for_reg2_loadrelate <= `Stop;
end else if((reg2_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg2_addr_o) && (reg2_addr_o != 5'h0)) begin
reg2_o <= mem_wdata_i;
end else if(reg2_read_o == 1'b1) begin
reg2_o <= reg2_data_i;
end else if(reg2_read_o == 1'b0) begin
reg2_o <= imm;
end else begin
reg2_o <= `ZeroWord;
end
end
endmodule | module id(
input wire rst,
input wire[`InstAddrBus] pc_i,
input wire[`InstBus] inst_i,
input wire[`AluOpBus] ex_aluop_i,
input wire ex_wreg_i,
input wire[`RegBus] ex_wdata_i,
input wire[`RegAddrBus] ex_wd_i,
input wire mem_wreg_i,
input wire[`RegBus] mem_wdata_i,
input wire[`RegAddrBus] mem_wd_i,
input wire[`RegBus] reg1_data_i,
input wire[`RegBus] reg2_data_i,
output reg reg1_read_o,
output reg reg2_read_o,
output reg[`RegAddrBus] reg1_addr_o,
output reg[`RegAddrBus] reg2_addr_o,
output reg[`AluOpBus] aluop_o,
output reg[`AluSelBus] alusel_o,
output reg[`RegBus] reg1_o,
output reg[`RegBus] reg2_o,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output wire[`RegBus] inst_o,
output reg branch_flag_o,
output reg[`RegBus] branch_target_address_o,
output reg[`RegBus] link_addr_o,
output reg stallreq
); |
wire[6:0] op = inst_i[6:0];
wire[2:0] op2 = inst_i[14:12];
wire[6:0] op3 = inst_i[31:25];
reg[`RegBus] imm;
reg instvalid;
wire[`RegBus] pc_plus_8;
wire[`RegBus] pc_plus_4;
reg[`RegBus] imm_sll2_signedext;
reg stallreq_for_reg1_loadrelate;
reg stallreq_for_reg2_loadrelate;
wire pre_inst_is_load;
wire stallreq_tmp;
assign pc_plus_8 = pc_i + 8;
assign pc_plus_4 = pc_i +4;
assign stallreq_tmp = stallreq_for_reg1_loadrelate | stallreq_for_reg2_loadrelate;
assign pre_inst_is_load = ((ex_aluop_i == `EXE_LB_OP) ||
(ex_aluop_i == `EXE_LBU_OP)||
(ex_aluop_i == `EXE_LH_OP) ||
(ex_aluop_i == `EXE_LHU_OP)||
(ex_aluop_i == `EXE_LW_OP))? 1'b1 : 1'b0;
assign inst_o = inst_i;
always @ ( * ) begin
stallreq <= stallreq_tmp;
end
always @ (*) begin
if (rst == `RstEnable) begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
instvalid <= `InstValid;
reg2_read_o <= 1'b0;
reg1_addr_o <= `NOPRegAddr;
reg2_addr_o <= `NOPRegAddr;
imm <= 32'h0;
link_addr_o <= `ZeroWord;
branch_target_address_o <= `ZeroWord;
branch_flag_o <= `NotBranch;
stallreq <= `NoStop;
end else begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= inst_i[11:7];
wreg_o <= `WriteDisable;
instvalid <= `InstInvalid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= inst_i[19:15];
reg2_addr_o <= inst_i[24:20];
imm <= `ZeroWord;
link_addr_o <= `ZeroWord;
branch_target_address_o <= `ZeroWord;
branch_flag_o <= `NotBranch;
stallreq <= `NoStop;
case (op)
`EXE_OP_IMM:
begin
case(op2)
`EXE_ORI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{21{inst_i[31]}}, inst_i[30:20]}; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_ANDI:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{21{inst_i[31]}}, inst_i[30:20]};
wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_XORI:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{21{inst_i[31]}}, inst_i[30:20]};
wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_SLTI:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{21{inst_i[31]}}, inst_i[30:20]}; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_SLTIU:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{21{inst_i[31]}}, inst_i[30:20]}; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_ADDI:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{21{inst_i[31]}}, inst_i[30:20]}; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_SLLI:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= inst_i[24:20]; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
3'b101:
begin
case(op3)
`EXE_SRLI:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= inst_i[24:20]; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_SRAI:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= inst_i[24:20]; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
endcase
end
default: begin
end
endcase
end
`EXE_OP:
begin
case (op2)
`EXE_OR:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_AND:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_XOR:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SLL:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SLT:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SLTU:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
3'b000:
begin
case(op3)
`EXE_ADD:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SUB:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SUB_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
endcase
end
3'b101:
begin
case(op3)
`EXE_SRL:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SRA:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
endcase
end
default:
begin
end
endcase
end
`EXE_JAL:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_JAL_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
link_addr_o <= pc_plus_4;
wd_o <= inst_i[11:7];
branch_target_address_o <= {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:25], inst_i[24:21], 1'b0} + pc_i;
branch_flag_o <= `Branch;
stallreq <= `Stop;
instvalid <= `InstValid;
end
`EXE_JALR:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_JALR_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
wd_o <= inst_i[11:7];
link_addr_o <= pc_plus_4;
imm_sll2_signedext <= {{21{inst_i[21]}}, inst_i[30:20]} + reg1_o;
branch_target_address_o <= ( {{21{inst_i[31]}}, inst_i[30:20]} + reg1_o) & (-1 ^ 1);
branch_flag_o <= `Branch;
stallreq <= `Stop;
instvalid <= `InstValid;
end
`EXE_LUI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_LUI_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b0; reg2_read_o <= 1'b0;
imm <= {inst_i[31:12], 12'b0}; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_AUIPC:
begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_AUIPC_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b0; reg2_read_o <= 1'b0;
imm <= {inst_i[31:12], 12'b0} + pc_i; wd_o <= inst_i[11:7];
instvalid <= `InstValid;
end
`EXE_LOAD:
begin
case(op2)
`EXE_LB: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_LB_OP;
alusel_o <= `EXE_RES_LOAD_STORE; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
wd_o <= inst_i[11:7]; instvalid <= `InstValid;
end
`EXE_LBU: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_LBU_OP;
alusel_o <= `EXE_RES_LOAD_STORE; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
wd_o <= inst_i[11:7]; instvalid <= `InstValid;
end
`EXE_LH: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_LH_OP;
alusel_o <= `EXE_RES_LOAD_STORE; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
wd_o <= inst_i[11:7]; instvalid <= `InstValid;
end
`EXE_LHU: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_LHU_OP;
alusel_o <= `EXE_RES_LOAD_STORE; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
wd_o <= inst_i[11:7]; instvalid <= `InstValid;
end
`EXE_LW: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_LW_OP;
alusel_o <= `EXE_RES_LOAD_STORE; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
wd_o <= inst_i[11:7]; instvalid <= `InstValid;
end
endcase
end
`EXE_STORE:
begin
case(op2)
`EXE_SB: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_SB_OP;
reg1_read_o <= 1'b1; reg2_read_o <= 1'b1; instvalid <= `InstValid;
alusel_o <= `EXE_RES_LOAD_STORE;
end
`EXE_SH: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_SH_OP;
reg1_read_o <= 1'b1; reg2_read_o <= 1'b1; instvalid <= `InstValid;
alusel_o <= `EXE_RES_LOAD_STORE;
end
`EXE_SW: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_SW_OP;
reg1_read_o <= 1'b1; reg2_read_o <= 1'b1; instvalid <= `InstValid;
alusel_o <= `EXE_RES_LOAD_STORE;
end
endcase
end
`EXE_BRANCH:
begin
case(op2)
`EXE_BEQ:
begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_BEQ_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
imm_sll2_signedext <= {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
if($signed(reg1_o) == $signed(reg2_o))
begin
branch_target_address_o <= pc_i + {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
branch_flag_o <= `Branch;
stallreq <= `Stop;
end
end
`EXE_BNE:
begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_BNE_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
imm_sll2_signedext <= {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
if($signed(reg1_o) != $signed(reg2_o))
begin
branch_target_address_o <= pc_i + {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
branch_flag_o <= `Branch;
stallreq <= `Stop;
end
end
`EXE_BGE:
begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_BGE_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
imm_sll2_signedext <={{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
if($signed(reg1_o) >= $signed(reg2_o))
begin
branch_target_address_o <= pc_i + {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
branch_flag_o <= `Branch;
stallreq <= `Stop;
end
end
`EXE_BGEU:
begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_BGEU_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
imm_sll2_signedext <= {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
if(reg1_o >= reg2_o)
begin
branch_target_address_o <= pc_i + {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
branch_flag_o <= `Branch;
stallreq <= `Stop;
end
end
`EXE_BLT:
begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_BLT_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
imm_sll2_signedext <={{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
if($signed(reg1_o) <= $signed(reg2_o))
begin
branch_target_address_o <= pc_i + {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
branch_flag_o <= `Branch;
stallreq <= `Stop;
end
end
`EXE_BLTU:
begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_BLTU_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
imm_sll2_signedext <={{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
if(reg1_o <= reg2_o)
begin
branch_target_address_o <= pc_i + {{21{inst_i[31]}}, inst_i[7],inst_i[30:25], inst_i[11:8], 1'b0};
branch_flag_o <= `Branch;
stallreq <= `Stop;
end
end
endcase
end
default: begin
end
endcase
end
end
always @ (*) begin
stallreq_for_reg1_loadrelate <= `NoStop;
if(rst == `RstEnable) begin
reg1_o <= `ZeroWord;
end
else if (reg1_addr_o == 0) begin
reg1_o <= 0;
end
else if(pre_inst_is_load == 1'b1 && ex_wd_i == reg1_addr_o
&& reg1_read_o == 1'b1 ) begin
stallreq_for_reg1_loadrelate <= `Stop;
end
<<<<<<< HEAD
else if (aluop_o == `EXE_JALR_OP) begin
reg1_o <= link_addr_o;
end else if((reg1_read_o == 1'b1) && (ex_wreg_i == 1'b1)
=======
else if((reg1_read_o == 1'b1) && (ex_wreg_i == 1'b1)
>>>>>>> dev
&& (ex_wd_i == reg1_addr_o) && (reg1_addr_o != 5'h0)) begin
reg1_o <= ex_wdata_i;
end else if((reg1_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg1_addr_o) && (reg1_addr_o != 5'h0)) begin
reg1_o <= mem_wdata_i;
end else if(reg1_read_o == 1'b1) begin
reg1_o <= reg1_data_i;
end else if(reg1_read_o == 1'b0) begin
reg1_o <= imm;
end else begin
reg1_o <= `ZeroWord;
end
end
always @ (*) begin
stallreq_for_reg2_loadrelate <= `NoStop;
if(rst == `RstEnable) begin
reg2_o <= `ZeroWord;
end
else if((reg2_read_o == 1'b1) && (ex_wreg_i == 1'b1)
&& (ex_wd_i == reg2_addr_o) && (reg2_addr_o != 5'h0)) begin
reg2_o <= ex_wdata_i;
end
else if(pre_inst_is_load == 1'b1 && ex_wd_i == reg2_addr_o
&& reg2_read_o == 1'b1 ) begin
stallreq_for_reg2_loadrelate <= `Stop;
end else if((reg2_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg2_addr_o) && (reg2_addr_o != 5'h0)) begin
reg2_o <= mem_wdata_i;
end else if(reg2_read_o == 1'b1) begin
reg2_o <= reg2_data_i;
end else if(reg2_read_o == 1'b0) begin
reg2_o <= imm;
end else begin
reg2_o <= `ZeroWord;
end
end
endmodule | 3 |
6,126 | data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/if.v | 115,162,999 | if.v | v | 27 | 83 | [] | [] | [] | null | line:23: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/if.v:23: syntax error, unexpected if, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule if(\n ^~\n%Error: Exiting due to 1 error(s)\n' | 6,873 | module | module if(
);
endmodule | module if(
); |
endmodule | 3 |
6,127 | data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v | 115,162,999 | inst_rom.v | v | 26 | 108 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 6: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:3: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.v\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:9: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] addr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] addr,\n ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:10: Define or directive not defined: \'`InstBus\'\n output reg[`InstBus] inst\n ^~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:14: Define or directive not defined: \'`InstMemNum\'\n reg[7:0] inst_mem[0:`InstMemNum-1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:16: syntax error, unexpected initial\n initial $readmemh ( "ori.mem", inst_mem );\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:19: Define or directive not defined: \'`ChipDisable\'\n if (ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:20: Define or directive not defined: \'`ZeroWord\'\n inst <= `ZeroWord;\n ^~~~~~~~~\n%Error: Exiting due to 8 error(s)\n' | 6,875 | module | module inst_rom(
input wire ce,
input wire[`InstAddrBus] addr,
output reg[`InstBus] inst
);
reg[7:0] inst_mem[0:`InstMemNum-1];
initial $readmemh ( "ori.mem", inst_mem );
always @ (*) begin
if (ce == `ChipDisable) begin
inst <= `ZeroWord;
end else begin
inst <= {inst_mem[addr[31:0]+3], inst_mem[addr[31:0]+2], inst_mem[addr[31:0]+1], inst_mem[addr[31:0]]};
end
end
endmodule | module inst_rom(
input wire ce,
input wire[`InstAddrBus] addr,
output reg[`InstBus] inst
); |
reg[7:0] inst_mem[0:`InstMemNum-1];
initial $readmemh ( "ori.mem", inst_mem );
always @ (*) begin
if (ce == `ChipDisable) begin
inst <= `ZeroWord;
end else begin
inst <= {inst_mem[addr[31:0]+3], inst_mem[addr[31:0]+2], inst_mem[addr[31:0]+1], inst_mem[addr[31:0]]};
end
end
endmodule | 3 |
6,128 | data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v | 115,162,999 | mem.v | v | 122 | 58 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 5: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:2: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.v\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:9: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] wd_i,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegAddrBus] wd_i,\n ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] wdata_i,\n ^~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:11: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] wdata_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:13: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus] aluop_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:14: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] mem_addr_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:15: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg2_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:18: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] mem_data_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:21: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] wdata_o,\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:23: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wdata_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:26: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] mem_addr_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg[3:0] mem_sel_o,\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] mem_data_o,\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:29: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] mem_data_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:34: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] zero32;\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] zero32;\n ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:36: syntax error, unexpected assign\n assign mem_we_o = mem_we ;\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:37: Define or directive not defined: \'`ZeroWord\'\n assign zero32 = `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:42: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:43: Define or directive not defined: \'`NOPRegAddr\'\n wd_o <= `NOPRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:44: Define or directive not defined: \'`WriteDisable\'\n wreg_o <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:45: Define or directive not defined: \'`ZeroWord\'\n wdata_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:46: Define or directive not defined: \'`ZeroWord\'\n mem_addr_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:47: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:49: Define or directive not defined: \'`ZeroWord\'\n mem_data_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:50: Define or directive not defined: \'`ChipDisable\'\n mem_ce_o <= `ChipDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:55: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:56: Define or directive not defined: \'`ZeroWord\'\n mem_addr_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:58: Define or directive not defined: \'`ChipDisable\'\n mem_ce_o <= `ChipDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:60: Define or directive not defined: \'`EXE_LB_OP\'\n `EXE_LB_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:62: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:63: Define or directive not defined: \'`ChipEnable\'\n mem_ce_o <= `ChipEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:67: Define or directive not defined: \'`EXE_LBU_OP\'\n `EXE_LBU_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:69: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:70: Define or directive not defined: \'`ChipEnable\'\n mem_ce_o <= `ChipEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:74: Define or directive not defined: \'`EXE_LH_OP\'\n `EXE_LH_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:76: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:77: Define or directive not defined: \'`ChipEnable\'\n mem_ce_o <= `ChipEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:81: Define or directive not defined: \'`EXE_LHU_OP\'\n `EXE_LHU_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:83: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:84: Define or directive not defined: \'`ChipEnable\'\n mem_ce_o <= `ChipEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:88: Define or directive not defined: \'`EXE_LW_OP\'\n `EXE_LW_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:90: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:91: Define or directive not defined: \'`ChipEnable\'\n mem_ce_o <= `ChipEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:95: Define or directive not defined: \'`EXE_SB_OP\'\n `EXE_SB_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:97: Define or directive not defined: \'`WriteEnable\'\n mem_we <= `WriteEnable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:99: Define or directive not defined: \'`ChipEnable\'\n mem_ce_o <= `ChipEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:102: Define or directive not defined: \'`EXE_SH_OP\'\n `EXE_SH_OP: begin\n ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,876 | module | module mem(
input wire rst,
input wire[`RegAddrBus] wd_i,
input wire wreg_i,
input wire[`RegBus] wdata_i,
input wire[`AluOpBus] aluop_i,
input wire[`RegBus] mem_addr_i,
input wire[`RegBus] reg2_i,
input wire[`RegBus] mem_data_i,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output reg[`RegBus] wdata_o,
output reg[`RegBus] mem_addr_o,
output wire mem_we_o,
output reg[3:0] mem_sel_o,
output reg[`RegBus] mem_data_o,
output reg mem_ce_o
);
wire[`RegBus] zero32;
reg mem_we;
assign mem_we_o = mem_we ;
assign zero32 = `ZeroWord;
always @ (*) begin
if(rst == `RstEnable) begin
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
wdata_o <= `ZeroWord;
mem_addr_o <= `ZeroWord;
mem_we <= `WriteDisable;
mem_sel_o <= 4'b0000;
mem_data_o <= `ZeroWord;
mem_ce_o <= `ChipDisable;
end else begin
wd_o <= wd_i;
wreg_o <= wreg_i;
wdata_o <= wdata_i;
mem_we <= `WriteDisable;
mem_addr_o <= `ZeroWord;
mem_ce_o <= `ChipDisable;
case (aluop_i)
`EXE_LB_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteDisable;
mem_ce_o <= `ChipEnable;
wdata_o <= {{24{mem_data_i[7]}}, mem_data_i[7:0]};
end
`EXE_LBU_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteDisable;
mem_ce_o <= `ChipEnable;
wdata_o <= {{24{1'b0}}, mem_data_i[7:0]};
end
`EXE_LH_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteDisable;
mem_ce_o <= `ChipEnable;
wdata_o <= {{16{mem_data_i[15]}}, mem_data_i[15:0]};
end
`EXE_LHU_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteDisable;
mem_ce_o <= `ChipEnable;
wdata_o <= {{16{1'b0}}, mem_data_i[15:0]};
end
`EXE_LW_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteDisable;
mem_ce_o <= `ChipEnable;
wdata_o <= mem_data_i;
end
`EXE_SB_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteEnable;
mem_data_o <= {{24{1'b0}},reg2_i[7:0]};
mem_ce_o <= `ChipEnable;
mem_sel_o <= 4'b0001;
end
`EXE_SH_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteEnable;
mem_data_o <= {{16{1'b0}},reg2_i[15:0]};
mem_ce_o <= `ChipEnable;
mem_sel_o <= 4'b0010;
end
`EXE_SW_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteEnable;
mem_data_o <= reg2_i;
mem_ce_o <= `ChipEnable;
mem_sel_o <= 4'b0100;
end
endcase
end
end
endmodule | module mem(
input wire rst,
input wire[`RegAddrBus] wd_i,
input wire wreg_i,
input wire[`RegBus] wdata_i,
input wire[`AluOpBus] aluop_i,
input wire[`RegBus] mem_addr_i,
input wire[`RegBus] reg2_i,
input wire[`RegBus] mem_data_i,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output reg[`RegBus] wdata_o,
output reg[`RegBus] mem_addr_o,
output wire mem_we_o,
output reg[3:0] mem_sel_o,
output reg[`RegBus] mem_data_o,
output reg mem_ce_o
); |
wire[`RegBus] zero32;
reg mem_we;
assign mem_we_o = mem_we ;
assign zero32 = `ZeroWord;
always @ (*) begin
if(rst == `RstEnable) begin
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
wdata_o <= `ZeroWord;
mem_addr_o <= `ZeroWord;
mem_we <= `WriteDisable;
mem_sel_o <= 4'b0000;
mem_data_o <= `ZeroWord;
mem_ce_o <= `ChipDisable;
end else begin
wd_o <= wd_i;
wreg_o <= wreg_i;
wdata_o <= wdata_i;
mem_we <= `WriteDisable;
mem_addr_o <= `ZeroWord;
mem_ce_o <= `ChipDisable;
case (aluop_i)
`EXE_LB_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteDisable;
mem_ce_o <= `ChipEnable;
wdata_o <= {{24{mem_data_i[7]}}, mem_data_i[7:0]};
end
`EXE_LBU_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteDisable;
mem_ce_o <= `ChipEnable;
wdata_o <= {{24{1'b0}}, mem_data_i[7:0]};
end
`EXE_LH_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteDisable;
mem_ce_o <= `ChipEnable;
wdata_o <= {{16{mem_data_i[15]}}, mem_data_i[15:0]};
end
`EXE_LHU_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteDisable;
mem_ce_o <= `ChipEnable;
wdata_o <= {{16{1'b0}}, mem_data_i[15:0]};
end
`EXE_LW_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteDisable;
mem_ce_o <= `ChipEnable;
wdata_o <= mem_data_i;
end
`EXE_SB_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteEnable;
mem_data_o <= {{24{1'b0}},reg2_i[7:0]};
mem_ce_o <= `ChipEnable;
mem_sel_o <= 4'b0001;
end
`EXE_SH_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteEnable;
mem_data_o <= {{16{1'b0}},reg2_i[15:0]};
mem_ce_o <= `ChipEnable;
mem_sel_o <= 4'b0010;
end
`EXE_SW_OP: begin
mem_addr_o <= mem_addr_i;
mem_we <= `WriteEnable;
mem_data_o <= reg2_i;
mem_ce_o <= `ChipEnable;
mem_sel_o <= 4'b0100;
end
endcase
end
end
endmodule | 3 |
6,131 | data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v | 115,162,999 | test0.v | v | 77 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 25: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:2: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.v\n data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:43: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n if(stopFlag == `False) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:43: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(stopFlag == `False) begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:45: Unsupported: Ignoring delay on this delayed statement.\n #50 clk = 1\'b0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:46: syntax error, unexpected else\n end else begin\n ^~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:55: Define or directive not defined: \'`True\'\n if (rst == `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:55: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `True) begin\n ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:63: syntax error, unexpected $display\n $display("regs[%d] = %d",i ,top.cpu.regFile.regs[i]);\n ^~~~~~~~\n%Error: Cannot continue\n' | 6,883 | module | module test0();
reg clk,rst;
reg stopFlag;
Top top(
.clk(clk),
.rst(rst));
initial begin
$readmemh("insts.mem", top.cpu.iCache.inst);
clk = 1'b0;
stopFlag = 1'b0;
forever begin
if(stopFlag == `False) begin
#50 clk = 1'b1;
#50 clk = 1'b0;
end else begin
#50;
end
end
end
reg [31:0] count;
reg [31:0] i;
always @( posedge clk ) begin
$display("newCLK");
if (rst == `True) begin
count <= 0;
end else begin
if(count == 50) begin
stopFlag = 1'b1;
$display("end");
#200;
for(i=0;i<32;i=i+1) begin
$display("regs[%d] = %d",i ,top.cpu.regFile.regs[i]);
end
$stop;
end
$display("[Clock]: %d",count );
count <= count + 1;
end
end
initial begin
rst = 1'b1;
#200 rst = 1'b0;
end
endmodule | module test0(); |
reg clk,rst;
reg stopFlag;
Top top(
.clk(clk),
.rst(rst));
initial begin
$readmemh("insts.mem", top.cpu.iCache.inst);
clk = 1'b0;
stopFlag = 1'b0;
forever begin
if(stopFlag == `False) begin
#50 clk = 1'b1;
#50 clk = 1'b0;
end else begin
#50;
end
end
end
reg [31:0] count;
reg [31:0] i;
always @( posedge clk ) begin
$display("newCLK");
if (rst == `True) begin
count <= 0;
end else begin
if(count == 50) begin
stopFlag = 1'b1;
$display("end");
#200;
for(i=0;i<32;i=i+1) begin
$display("regs[%d] = %d",i ,top.cpu.regFile.regs[i]);
end
$stop;
end
$display("[Clock]: %d",count );
count <= count + 1;
end
end
initial begin
rst = 1'b1;
#200 rst = 1'b0;
end
endmodule | 3 |
6,132 | data/full_repos/permissive/115201418/src/I2C_master.v | 115,201,418 | I2C_master.v | v | 82 | 73 | [] | [] | [] | [(1, 82)] | null | data/verilator_xmls/10031b13-a46f-4236-9587-2cec19e604cc.xml | null | 6,885 | module | module I2C_master
(
input wire clk,
input wire rst_n,
input wire valid,
input wire [6:0] id,
input wire [7:0] data,
output reg scl,
output reg sda
);
reg valid_i2c;
integer cnt;
integer cnt_cnt;
integer cnt_data;
always @(posedge clk)
begin
if (rst_n)
begin
scl <= 1'b1;
sda <= 1'b1;
valid_i2c <= 1'b0;
cnt_cnt <= 0;
cnt_data <= 0;
cnt <= 0;
end
if (valid && cnt == 0)
valid_i2c <= 1'b1;
if (valid_i2c && cnt == 2)
scl <= ~scl;
if (valid_i2c && cnt < 2)
begin
sda <= 1'b0;
cnt <= cnt + 1;
if (sda == 1'b0 && cnt == 1)
begin
scl <= 1'b0;
cnt <= cnt + 1;
end
end
if (valid_i2c && cnt == 2)
begin
if (cnt_cnt == 0 && scl == 1'b1)
begin
sda <= id [cnt_data];
if (cnt_data < 6)
cnt_data <= cnt_data + 1;
else
begin
cnt_data <= 0;
cnt_cnt <= cnt_cnt + 1;
end
end
if (cnt_cnt == 1 && scl == 1'b1)
begin
sda <= data [cnt_data];
if (cnt_data < 7)
cnt_data <= cnt_data + 1;
else
begin
cnt_data <= 0;
cnt_cnt <= 2;
cnt <= cnt + 1;
end
end
end
if (valid_i2c && cnt == 3)
begin
scl <= 1'b1;
valid_i2c <= 1'b0;
sda <= 1'b0;
cnt <= 4;
end
if (valid_i2c == 1'b0 && scl == 1'b1 && cnt == 4)
sda <= 1'b1;
end
endmodule | module I2C_master
(
input wire clk,
input wire rst_n,
input wire valid,
input wire [6:0] id,
input wire [7:0] data,
output reg scl,
output reg sda
); |
reg valid_i2c;
integer cnt;
integer cnt_cnt;
integer cnt_data;
always @(posedge clk)
begin
if (rst_n)
begin
scl <= 1'b1;
sda <= 1'b1;
valid_i2c <= 1'b0;
cnt_cnt <= 0;
cnt_data <= 0;
cnt <= 0;
end
if (valid && cnt == 0)
valid_i2c <= 1'b1;
if (valid_i2c && cnt == 2)
scl <= ~scl;
if (valid_i2c && cnt < 2)
begin
sda <= 1'b0;
cnt <= cnt + 1;
if (sda == 1'b0 && cnt == 1)
begin
scl <= 1'b0;
cnt <= cnt + 1;
end
end
if (valid_i2c && cnt == 2)
begin
if (cnt_cnt == 0 && scl == 1'b1)
begin
sda <= id [cnt_data];
if (cnt_data < 6)
cnt_data <= cnt_data + 1;
else
begin
cnt_data <= 0;
cnt_cnt <= cnt_cnt + 1;
end
end
if (cnt_cnt == 1 && scl == 1'b1)
begin
sda <= data [cnt_data];
if (cnt_data < 7)
cnt_data <= cnt_data + 1;
else
begin
cnt_data <= 0;
cnt_cnt <= 2;
cnt <= cnt + 1;
end
end
end
if (valid_i2c && cnt == 3)
begin
scl <= 1'b1;
valid_i2c <= 1'b0;
sda <= 1'b0;
cnt <= 4;
end
if (valid_i2c == 1'b0 && scl == 1'b1 && cnt == 4)
sda <= 1'b1;
end
endmodule | 2 |
6,137 | data/full_repos/permissive/115223038/Assignment 1/mux2x1.v | 115,223,038 | mux2x1.v | v | 51 | 60 | [] | [] | [] | [(8, 18), (20, 51)] | null | null | 1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/115223038\n ... Looked in:\n data/full_repos/permissive/115223038/Assignment/1,data/full_repos/permissive/115223038\n data/full_repos/permissive/115223038/Assignment/1,data/full_repos/permissive/115223038.v\n data/full_repos/permissive/115223038/Assignment/1,data/full_repos/permissive/115223038.sv\n 1,data/full_repos/permissive/115223038\n 1,data/full_repos/permissive/115223038.v\n 1,data/full_repos/permissive/115223038.sv\n obj_dir/1,data/full_repos/permissive/115223038\n obj_dir/1,data/full_repos/permissive/115223038.v\n obj_dir/1,data/full_repos/permissive/115223038.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/115223038/Assignment\n%Error: Cannot find file containing module: 1/mux2x1.v\n%Error: Exiting due to 3 error(s)\n' | 6,888 | module | module MuxMod(s, d0, d1, o);
input s, d0, d1;
output o;
wire s_inv, and0, and1;
not(s_inv, s);
and(and0, d0, s_inv);
and(and1, d1, s);
or(o, and0, and1);
endmodule | module MuxMod(s, d0, d1, o); |
input s, d0, d1;
output o;
wire s_inv, and0, and1;
not(s_inv, s);
and(and0, d0, s_inv);
and(and1, d1, s);
or(o, and0, and1);
endmodule | 1 |
6,138 | data/full_repos/permissive/115223038/Assignment 1/mux2x1.v | 115,223,038 | mux2x1.v | v | 51 | 60 | [] | [] | [] | [(8, 18), (20, 51)] | null | null | 1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/115223038\n ... Looked in:\n data/full_repos/permissive/115223038/Assignment/1,data/full_repos/permissive/115223038\n data/full_repos/permissive/115223038/Assignment/1,data/full_repos/permissive/115223038.v\n data/full_repos/permissive/115223038/Assignment/1,data/full_repos/permissive/115223038.sv\n 1,data/full_repos/permissive/115223038\n 1,data/full_repos/permissive/115223038.v\n 1,data/full_repos/permissive/115223038.sv\n obj_dir/1,data/full_repos/permissive/115223038\n obj_dir/1,data/full_repos/permissive/115223038.v\n obj_dir/1,data/full_repos/permissive/115223038.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/115223038/Assignment\n%Error: Cannot find file containing module: 1/mux2x1.v\n%Error: Exiting due to 3 error(s)\n' | 6,888 | module | module TestMod;
reg s, d0, d1;
wire o;
MuxMod my_mux(s, d0, d1, o);
initial begin
$display("Time\ts\td0\td1\to");
$display("---------------------------------");
$monitor("%0d\t%b\t%b\t%b\t%b", $time, s, d0, d1, o);
end
initial begin
s = 0; d0 = 0; d1 = 0;
#1;
s = 0; d0 = 0; d1 = 1;
#1;
s = 0; d0 = 1; d1 = 0;
#1;
s = 0; d0 = 1; d1 = 1;
#1;
s = 1; d0 = 0; d1 = 0;
#1;
s = 1; d0 = 0; d1 = 1;
#1;
s = 1; d0 = 1; d1 = 0;
#1;
s = 1; d0 = 1; d1 = 1;
end
endmodule | module TestMod; |
reg s, d0, d1;
wire o;
MuxMod my_mux(s, d0, d1, o);
initial begin
$display("Time\ts\td0\td1\to");
$display("---------------------------------");
$monitor("%0d\t%b\t%b\t%b\t%b", $time, s, d0, d1, o);
end
initial begin
s = 0; d0 = 0; d1 = 0;
#1;
s = 0; d0 = 0; d1 = 1;
#1;
s = 0; d0 = 1; d1 = 0;
#1;
s = 0; d0 = 1; d1 = 1;
#1;
s = 1; d0 = 0; d1 = 0;
#1;
s = 1; d0 = 0; d1 = 1;
#1;
s = 1; d0 = 1; d1 = 0;
#1;
s = 1; d0 = 1; d1 = 1;
end
endmodule | 1 |
6,141 | data/full_repos/permissive/11525292/fpga/fpga.v | 11,525,292 | fpga.v | v | 155 | 174 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/11525292/fpga/fpga.v:34: Cannot find file containing module: 'dcm'\n dcm dcm(.CLK_IN(input_clk), .CLK_OUT(clk)); \n ^~~\n ... Looked in:\n data/full_repos/permissive/11525292/fpga,data/full_repos/permissive/11525292/dcm\n data/full_repos/permissive/11525292/fpga,data/full_repos/permissive/11525292/dcm.v\n data/full_repos/permissive/11525292/fpga,data/full_repos/permissive/11525292/dcm.sv\n dcm\n dcm.v\n dcm.sv\n obj_dir/dcm\n obj_dir/dcm.v\n obj_dir/dcm.sv\n%Error: data/full_repos/permissive/11525292/fpga/fpga.v:48: Cannot find file containing module: 'debounce'\n debounce btn_db(.clk(clk), .in(btn_sync2[idx]), .out(btn_debounced[idx]));\n ^~~~~~~~\n%Error: data/full_repos/permissive/11525292/fpga/fpga.v:56: Cannot find file containing module: 'sseg'\n sseg #(.N(16)) sseg(.clk(clk), .in(sseg_data), .c(seg), .an(an));\n ^~~~\n%Error: data/full_repos/permissive/11525292/fpga/fpga.v:72: Cannot find file containing module: 'uart_multibyte_transmitter'\n uart_multibyte_transmitter #(.CLK_CYCLES(694), .MSG_LOG_WIDTH(5)) uart_mbtx(.clk(clk), .data(uart_tx_data), .req(uart_tx_req), .uart_tx(RsTx));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11525292/fpga/fpga.v:93: Cannot find file containing module: 'uart_multibyte_receiver'\n uart_multibyte_receiver #(.CLK_CYCLES(694), .MSG_LOG_WIDTH(6)) uart_mbrx(.clk(clk), .data(uart_rx_data), .valid(uart_rx_valid), .ack(1'b0), .uart_rx(RsRx2));\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11525292/fpga/fpga.v:106: Cannot find file containing module: 'dsha_finisher'\n dsha_finisher #(.START_ROUND(idx)) dsha(.clk(clk), .X(X), .Y(Y), .in_nonce(in_nonce), .hash(_out_hash[idx]), .out_nonce(_out_nonce[idx]), .accepted(_dsha_accepted[idx]));\n ^~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n" | 6,890 | module | module fpga(
input wire input_clk,
input wire [7:0] sw,
input wire [4:0] btn,
output wire [7:0] led,
output wire [7:0] seg,
output wire [3:0] an,
output wire RsTx,
input wire RsRx
);
wire clk;
dcm dcm(.CLK_IN(input_clk), .CLK_OUT(clk));
assign led = sw;
reg [4:0] btn_sync, btn_sync2;
always @(posedge clk) begin
{btn_sync, btn_sync2} <= {btn, btn_sync};
end
wire [4:0] btn_debounced;
genvar idx;
generate
for (idx=0; idx<5; idx=idx+1) begin: debounce_btn
debounce btn_db(.clk(clk), .in(btn_sync2[idx]), .out(btn_debounced[idx]));
end
endgenerate
reg [4:0] btn_prev;
wire [15:0] sseg_data;
assign sseg_data = in_nonce[31:16];
sseg #(.N(16)) sseg(.clk(clk), .in(sseg_data), .c(seg), .an(an));
wire uart_tx_req, uart_tx_ready;
wire [255:0] uart_tx_data;
assign uart_tx_data[7:0] = 8'haa;
assign uart_tx_data[39:8] = out_nonce;
assign uart_tx_data[47:40] = 8'haa;
assign uart_tx_data[255:192] = 64'hdead432987beefaa;
assign uart_tx_req = success;
uart_multibyte_transmitter #(.CLK_CYCLES(694), .MSG_LOG_WIDTH(5)) uart_mbtx(.clk(clk), .data(uart_tx_data), .req(uart_tx_req), .uart_tx(RsTx));
reg RsRx1=1, RsRx2=1;
always @(posedge clk) begin
{RsRx1, RsRx2} <= {RsRx, RsRx1};
end
wire uart_rx_valid;
wire [511:0] uart_rx_data;
wire [255:0] X;
wire [95:0] Y;
assign X = uart_rx_data[255:0];
assign Y = uart_rx_data[351:256];
reg [31:0] in_nonce = 32'h0;
always @(posedge clk) begin
if (accepted) in_nonce <= in_nonce + 1;
end
uart_multibyte_receiver #(.CLK_CYCLES(694), .MSG_LOG_WIDTH(6)) uart_mbrx(.clk(clk), .data(uart_rx_data), .valid(uart_rx_valid), .ack(1'b0), .uart_rx(RsRx2));
reg [31:0] out_nonce;
wire accepted, success;
localparam NUM_COPIES = 4;
wire [255:0] _out_hash[NUM_COPIES-1:0];
wire [31:0] _out_nonce[NUM_COPIES-1:0];
wire [NUM_COPIES-1:0] _dsha_accepted, _dsha_success;
generate
for (idx = 0; idx < NUM_COPIES; idx = idx + 1) begin: block_dsha
assign _dsha_success[idx] = (_out_hash[idx][255:224+8] == 0) && (sw[0] || (_out_hash[idx][231:224] == 0));
dsha_finisher #(.START_ROUND(idx)) dsha(.clk(clk), .X(X), .Y(Y), .in_nonce(in_nonce), .hash(_out_hash[idx]), .out_nonce(_out_nonce[idx]), .accepted(_dsha_accepted[idx]));
end
endgenerate
integer i;
always @(*) begin
out_nonce = _out_nonce[0];
for (i = 1; i < NUM_COPIES; i = i + 1) begin
if (_dsha_success[i]) begin
out_nonce = _out_nonce[i];
end
end
end
assign accepted = (_dsha_accepted != 0);
assign success = (_dsha_success != 0);
always @(posedge clk) begin
btn_prev <= btn_debounced;
end
endmodule | module fpga(
input wire input_clk,
input wire [7:0] sw,
input wire [4:0] btn,
output wire [7:0] led,
output wire [7:0] seg,
output wire [3:0] an,
output wire RsTx,
input wire RsRx
); |
wire clk;
dcm dcm(.CLK_IN(input_clk), .CLK_OUT(clk));
assign led = sw;
reg [4:0] btn_sync, btn_sync2;
always @(posedge clk) begin
{btn_sync, btn_sync2} <= {btn, btn_sync};
end
wire [4:0] btn_debounced;
genvar idx;
generate
for (idx=0; idx<5; idx=idx+1) begin: debounce_btn
debounce btn_db(.clk(clk), .in(btn_sync2[idx]), .out(btn_debounced[idx]));
end
endgenerate
reg [4:0] btn_prev;
wire [15:0] sseg_data;
assign sseg_data = in_nonce[31:16];
sseg #(.N(16)) sseg(.clk(clk), .in(sseg_data), .c(seg), .an(an));
wire uart_tx_req, uart_tx_ready;
wire [255:0] uart_tx_data;
assign uart_tx_data[7:0] = 8'haa;
assign uart_tx_data[39:8] = out_nonce;
assign uart_tx_data[47:40] = 8'haa;
assign uart_tx_data[255:192] = 64'hdead432987beefaa;
assign uart_tx_req = success;
uart_multibyte_transmitter #(.CLK_CYCLES(694), .MSG_LOG_WIDTH(5)) uart_mbtx(.clk(clk), .data(uart_tx_data), .req(uart_tx_req), .uart_tx(RsTx));
reg RsRx1=1, RsRx2=1;
always @(posedge clk) begin
{RsRx1, RsRx2} <= {RsRx, RsRx1};
end
wire uart_rx_valid;
wire [511:0] uart_rx_data;
wire [255:0] X;
wire [95:0] Y;
assign X = uart_rx_data[255:0];
assign Y = uart_rx_data[351:256];
reg [31:0] in_nonce = 32'h0;
always @(posedge clk) begin
if (accepted) in_nonce <= in_nonce + 1;
end
uart_multibyte_receiver #(.CLK_CYCLES(694), .MSG_LOG_WIDTH(6)) uart_mbrx(.clk(clk), .data(uart_rx_data), .valid(uart_rx_valid), .ack(1'b0), .uart_rx(RsRx2));
reg [31:0] out_nonce;
wire accepted, success;
localparam NUM_COPIES = 4;
wire [255:0] _out_hash[NUM_COPIES-1:0];
wire [31:0] _out_nonce[NUM_COPIES-1:0];
wire [NUM_COPIES-1:0] _dsha_accepted, _dsha_success;
generate
for (idx = 0; idx < NUM_COPIES; idx = idx + 1) begin: block_dsha
assign _dsha_success[idx] = (_out_hash[idx][255:224+8] == 0) && (sw[0] || (_out_hash[idx][231:224] == 0));
dsha_finisher #(.START_ROUND(idx)) dsha(.clk(clk), .X(X), .Y(Y), .in_nonce(in_nonce), .hash(_out_hash[idx]), .out_nonce(_out_nonce[idx]), .accepted(_dsha_accepted[idx]));
end
endgenerate
integer i;
always @(*) begin
out_nonce = _out_nonce[0];
for (i = 1; i < NUM_COPIES; i = i + 1) begin
if (_dsha_success[i]) begin
out_nonce = _out_nonce[i];
end
end
end
assign accepted = (_dsha_accepted != 0);
assign success = (_dsha_success != 0);
always @(posedge clk) begin
btn_prev <= btn_debounced;
end
endmodule | 20 |
6,142 | data/full_repos/permissive/11525292/fpga/test/dsha_finisher.v | 11,525,292 | dsha_finisher.v | v | 66 | 81 | [] | [] | [] | [(25, 64)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/11525292/fpga/test/dsha_finisher.v:48: Unsupported: Ignoring delay on this delayed statement.\n always #(P/2) clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11525292/fpga/test/dsha_finisher.v:60: Unsupported: Ignoring delay on this delayed statement.\n #(135*P);\n ^\n%Error: data/full_repos/permissive/11525292/fpga/test/dsha_finisher.v:57: Can\'t find definition of \'chunk1\' in dotted scope/variable: \'uut.chunk1\'\n uut.chunk1.roundnum = 6\'h3e;\n ^~~~~~\n ... Known scopes under \'uut\': <no cells found>\n%Error: data/full_repos/permissive/11525292/fpga/test/dsha_finisher.v:58: Can\'t find definition of \'chunk2\' in dotted scope/variable: \'uut.chunk2\'\n uut.chunk2.roundnum = 6\'h3e;\n ^~~~~~\n ... Known scopes under \'uut\': <no cells found>\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,898 | module | module dsha_finisher_test;
reg clk;
reg [255:0] X;
reg [95:0] Y;
reg [31:0] in_nonce;
wire [255:0] hash;
wire [31:0] out_nonce;
dsha_finisher uut (
.clk(clk),
.X(X),
.Y(Y),
.in_nonce(in_nonce),
.hash(hash),
.out_nonce(out_nonce)
);
parameter P=10;
always #(P/2) clk = ~clk;
initial begin
clk = 0;
X = 256'h356d66244c73b9f1e1a328b2c6615412a965a72218c5c19eb5c5d4073db86a04;
Y = 96'h1c2ac4af504e86edec9d69b1;
in_nonce = 32'hb2957c02;
uut.chunk1.roundnum = 6'h3e;
uut.chunk2.roundnum = 6'h3e;
#(135*P);
$finish();
end
endmodule | module dsha_finisher_test; |
reg clk;
reg [255:0] X;
reg [95:0] Y;
reg [31:0] in_nonce;
wire [255:0] hash;
wire [31:0] out_nonce;
dsha_finisher uut (
.clk(clk),
.X(X),
.Y(Y),
.in_nonce(in_nonce),
.hash(hash),
.out_nonce(out_nonce)
);
parameter P=10;
always #(P/2) clk = ~clk;
initial begin
clk = 0;
X = 256'h356d66244c73b9f1e1a328b2c6615412a965a72218c5c19eb5c5d4073db86a04;
Y = 96'h1c2ac4af504e86edec9d69b1;
in_nonce = 32'hb2957c02;
uut.chunk1.roundnum = 6'h3e;
uut.chunk2.roundnum = 6'h3e;
#(135*P);
$finish();
end
endmodule | 20 |
6,146 | data/full_repos/permissive/115351337/uart/reciever.v | 115,351,337 | reciever.v | v | 106 | 73 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:41: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n : ... In instance uart_rx\n reg [1:0] state = IDLE;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:69: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'RECIEVE\' generates 3 bits.\n : ... In instance uart_rx\n state <= RECIEVE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:72: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n : ... In instance uart_rx\n state <= IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:84: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'DONE\' generates 3 bits.\n : ... In instance uart_rx\n state <= DONE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:86: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'RECIEVE\' generates 3 bits.\n : ... In instance uart_rx\n state <= RECIEVE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:80: Operator LT expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'bit_recieved\' generates 3 bits.\n : ... In instance uart_rx\n if (bit_recieved < 8 && count == SAMPLE) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:94: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n : ... In instance uart_rx\n state <= IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:97: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'DONE\' generates 3 bits.\n : ... In instance uart_rx\n state <= DONE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:102: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n : ... In instance uart_rx\n state <= IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:66: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 2 bits.\n : ... In instance uart_rx\n case (state)\n ^~~~\n%Error: Exiting due to 10 warning(s)\n' | 6,904 | module | module uart_rx (
input clk,
input rx,
input clear,
output reg [7:0] data,
output done
);
parameter LIMIT = 104;
parameter SAMPLE = LIMIT/2;
parameter IDLE = 3'b00;
parameter RECIEVE = 3'b01;
parameter DONE = 3'b10;
reg [1:0] state = IDLE;
reg [31:0] count = 0;
reg [1:0] stop_bits = 0;
reg [2:0] bit_recieved = 0;
reg op_complete = 0;
always @(posedge clk) begin
if (count == LIMIT) begin
count <= 0;
end else begin
count <= count + 1;
end
end
always @(posedge clk) begin
if (clear == 1'b1) begin
done <= 1'b0;
end else if (op_complete == 1'b1) begin
done <= op_complete;
end else begin
done <= done;
end
end
always @(posedge clk) begin
case (state)
IDLE: begin
if (rx == 1'b0 && count == SAMPLE && done == 1'b0) begin
state <= RECIEVE;
data <= 0;
end else begin
state <= IDLE;
bit_recieved <= 0;
stop_bits <= 0;
op_complete <= 1'b0;
end
end
RECIEVE: begin
if (bit_recieved < 8 && count == SAMPLE) begin
data[bit_recieved] <= rx;
bit_recieved <= bit_recieved + 1;
end else if (bit_recieved == 7) begin
state <= DONE;
end else begin
state <= RECIEVE;
end
end
DONE: begin
if (stop_bits < 3 && count == SAMPLE) begin
stop_bits <= stop_bits + 1;
end else if (stop_bits == 3) begin
state <= IDLE;
op_complete <= 1'b1;
end else begin
state <= DONE;
end
end
default: begin
state <= IDLE;
end
endcase
end
endmodule | module uart_rx (
input clk,
input rx,
input clear,
output reg [7:0] data,
output done
); |
parameter LIMIT = 104;
parameter SAMPLE = LIMIT/2;
parameter IDLE = 3'b00;
parameter RECIEVE = 3'b01;
parameter DONE = 3'b10;
reg [1:0] state = IDLE;
reg [31:0] count = 0;
reg [1:0] stop_bits = 0;
reg [2:0] bit_recieved = 0;
reg op_complete = 0;
always @(posedge clk) begin
if (count == LIMIT) begin
count <= 0;
end else begin
count <= count + 1;
end
end
always @(posedge clk) begin
if (clear == 1'b1) begin
done <= 1'b0;
end else if (op_complete == 1'b1) begin
done <= op_complete;
end else begin
done <= done;
end
end
always @(posedge clk) begin
case (state)
IDLE: begin
if (rx == 1'b0 && count == SAMPLE && done == 1'b0) begin
state <= RECIEVE;
data <= 0;
end else begin
state <= IDLE;
bit_recieved <= 0;
stop_bits <= 0;
op_complete <= 1'b0;
end
end
RECIEVE: begin
if (bit_recieved < 8 && count == SAMPLE) begin
data[bit_recieved] <= rx;
bit_recieved <= bit_recieved + 1;
end else if (bit_recieved == 7) begin
state <= DONE;
end else begin
state <= RECIEVE;
end
end
DONE: begin
if (stop_bits < 3 && count == SAMPLE) begin
stop_bits <= stop_bits + 1;
end else if (stop_bits == 3) begin
state <= IDLE;
op_complete <= 1'b1;
end else begin
state <= DONE;
end
end
default: begin
state <= IDLE;
end
endcase
end
endmodule | 1 |
6,147 | data/full_repos/permissive/115351337/uart/reciever_tb.v | 115,351,337 | reciever_tb.v | v | 79 | 59 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/115351337/uart/reciever_tb.v:42: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("reciever_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115351337/uart/reciever_tb.v:43: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,reciever_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #100 clear = 1\'b0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #1248 clear = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #100 clear = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #100 rx = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #1248 rx = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #2496 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #6 clk = ~clk;\n ^\n%Error: Exiting due to 2 error(s), 26 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,905 | module | module reciever_tb;
reg clk;
wire [7:0] data;
reg [7:0] stored_data;
wire flag;
reg clear;
reg rx;
uart_rx reciever(clk, rx, clear, data, flag);
initial begin
$dumpfile("reciever_tb.vcd");
$dumpvars(0,reciever_tb);
rx = 1'b1;
clk = 1'b0;
clear = 1'b1;
#100 clear = 1'b0;
rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b1;
#1248 clear = 1'b1;
#100 clear = 1'b0;
#100 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b1;
#2496 $finish;
end
always begin
#6 clk = ~clk;
stored_data <= data;
end
endmodule | module reciever_tb; |
reg clk;
wire [7:0] data;
reg [7:0] stored_data;
wire flag;
reg clear;
reg rx;
uart_rx reciever(clk, rx, clear, data, flag);
initial begin
$dumpfile("reciever_tb.vcd");
$dumpvars(0,reciever_tb);
rx = 1'b1;
clk = 1'b0;
clear = 1'b1;
#100 clear = 1'b0;
rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b1;
#1248 clear = 1'b1;
#100 clear = 1'b0;
#100 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b0;
#1248 rx = 1'b1;
#1248 rx = 1'b1;
#2496 $finish;
end
always begin
#6 clk = ~clk;
stored_data <= data;
end
endmodule | 1 |
6,148 | data/full_repos/permissive/115351337/uart/transmitter.v | 115,351,337 | transmitter.v | v | 84 | 60 | [] | [] | [] | [(28, 84)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:40: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n : ... In instance uart_tx\n reg [1:0] state = IDLE;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:51: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'TRANSMIT\' generates 3 bits.\n : ... In instance uart_tx\n state <= TRANSMIT;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:53: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance uart_tx\n buffer <= data[7:0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:55: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n : ... In instance uart_tx\n state <= IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:64: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'DONE\' generates 3 bits.\n : ... In instance uart_tx\n state <= DONE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:76: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n : ... In instance uart_tx\n state <= IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:80: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n : ... In instance uart_tx\n state <= IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:46: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 2 bits.\n : ... In instance uart_tx\n case (state)\n ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/115351337/uart/transmitter.v:49: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'tx\'\n : ... In instance uart_tx\n tx <= 1\'b0;\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/115351337/uart/transmitter.v:52: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'in_progress\'\n : ... In instance uart_tx\n in_progress <= 1\'b1;\n ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/115351337/uart/transmitter.v:56: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'tx\'\n : ... In instance uart_tx\n tx <= 1\'b1;\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/115351337/uart/transmitter.v:57: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'in_progress\'\n : ... In instance uart_tx\n in_progress <= 1\'b0;\n ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/115351337/uart/transmitter.v:67: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'tx\'\n : ... In instance uart_tx\n tx <= buffer[bit_transmitted];\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/115351337/uart/transmitter.v:70: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'tx\'\n : ... In instance uart_tx\n tx <= tx;\n ^~\n%Error: Exiting due to 6 error(s), 8 warning(s)\n' | 6,906 | module | module uart_tx (
input clk,
input [7:0] data,
input start,
output in_progress,
output tx
);
parameter LIMIT = 104;
parameter IDLE = 3'b00;
parameter TRANSMIT = 3'b01;
parameter DONE = 3'b10;
reg [1:0] state = IDLE;
reg [31:0] count = 0;
reg [3:0] bit_transmitted = 0;
reg [8:0] buffer;
always @(posedge clk) begin
case (state)
IDLE: begin
if (start == 1'b1) begin
tx <= 1'b0;
count <= 0;
state <= TRANSMIT;
in_progress <= 1'b1;
buffer <= data[7:0];
end else begin
state <= IDLE;
tx <= 1'b1;
in_progress <= 1'b0;
bit_transmitted <= 0;
end
end
TRANSMIT: begin
if ( bit_transmitted == 9 ) begin
state <= DONE;
end else if (count == LIMIT) begin
count <= 0;
tx <= buffer[bit_transmitted];
bit_transmitted <= bit_transmitted + 1;
end else begin
tx <= tx;
count <= count + 1;
end
end
DONE: begin
state <= IDLE;
end
default: begin
state <= IDLE;
end
endcase
end
endmodule | module uart_tx (
input clk,
input [7:0] data,
input start,
output in_progress,
output tx
); |
parameter LIMIT = 104;
parameter IDLE = 3'b00;
parameter TRANSMIT = 3'b01;
parameter DONE = 3'b10;
reg [1:0] state = IDLE;
reg [31:0] count = 0;
reg [3:0] bit_transmitted = 0;
reg [8:0] buffer;
always @(posedge clk) begin
case (state)
IDLE: begin
if (start == 1'b1) begin
tx <= 1'b0;
count <= 0;
state <= TRANSMIT;
in_progress <= 1'b1;
buffer <= data[7:0];
end else begin
state <= IDLE;
tx <= 1'b1;
in_progress <= 1'b0;
bit_transmitted <= 0;
end
end
TRANSMIT: begin
if ( bit_transmitted == 9 ) begin
state <= DONE;
end else if (count == LIMIT) begin
count <= 0;
tx <= buffer[bit_transmitted];
bit_transmitted <= bit_transmitted + 1;
end else begin
tx <= tx;
count <= count + 1;
end
end
DONE: begin
state <= IDLE;
end
default: begin
state <= IDLE;
end
endcase
end
endmodule | 1 |
6,149 | data/full_repos/permissive/115351337/uart/transmitter_tb.v | 115,351,337 | transmitter_tb.v | v | 58 | 60 | [] | [] | [] | null | line:52: before: "$" | null | 1: b'%Error: data/full_repos/permissive/115351337/uart/transmitter_tb.v:41: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("transmitter_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115351337/uart/transmitter_tb.v:42: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,transmitter_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/transmitter_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #20 start = 1\'b0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/transmitter_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #12480 data = 8\'b01010101;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/transmitter_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #1248 start = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/transmitter_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #20 start = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/transmitter_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #12480 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/transmitter_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #6 clk = ~clk;\n ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,907 | module | module transmitter_tb;
reg clk;
reg [7:0] data;
wire in_progress;
reg start;
wire tx;
uart_tx transmitter(clk, data, start, in_progress, tx);
initial begin
$dumpfile("transmitter_tb.vcd");
$dumpvars(0,transmitter_tb);
clk = 1'b0;
data = 8'b01010101;
start = 1'b1;
#20 start = 1'b0;
#12480 data = 8'b01010101;
#1248 start = 1'b1;
#20 start = 1'b0;
#12480 $finish;
end
always begin
#6 clk = ~clk;
end
endmodule | module transmitter_tb; |
reg clk;
reg [7:0] data;
wire in_progress;
reg start;
wire tx;
uart_tx transmitter(clk, data, start, in_progress, tx);
initial begin
$dumpfile("transmitter_tb.vcd");
$dumpvars(0,transmitter_tb);
clk = 1'b0;
data = 8'b01010101;
start = 1'b1;
#20 start = 1'b0;
#12480 data = 8'b01010101;
#1248 start = 1'b1;
#20 start = 1'b0;
#12480 $finish;
end
always begin
#6 clk = ~clk;
end
endmodule | 1 |
6,150 | data/full_repos/permissive/115351337/uart/uart.v | 115,351,337 | uart.v | v | 46 | 68 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/115351337/uart/uart.v:32: Cannot find include file: transmitter.v\n `include "transmitter.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115351337/uart,data/full_repos/permissive/115351337/transmitter.v\n data/full_repos/permissive/115351337/uart,data/full_repos/permissive/115351337/transmitter.v.v\n data/full_repos/permissive/115351337/uart,data/full_repos/permissive/115351337/transmitter.v.sv\n transmitter.v\n transmitter.v.v\n transmitter.v.sv\n obj_dir/transmitter.v\n obj_dir/transmitter.v.v\n obj_dir/transmitter.v.sv\n%Error: data/full_repos/permissive/115351337/uart/uart.v:33: Cannot find include file: reciever.v\n `include "reciever.v" \n ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 6,908 | module | module top(
input clk,
input rx,
output tx,
output flag,
output in_progress
);
reg [7:0] buffer;
uart_rx reciever(clk, rx, in_progress, buffer, flag);
uart_tx transmitter(clk, buffer, flag, in_progress, tx);
endmodule | module top(
input clk,
input rx,
output tx,
output flag,
output in_progress
); |
reg [7:0] buffer;
uart_rx reciever(clk, rx, in_progress, buffer, flag);
uart_tx transmitter(clk, buffer, flag, in_progress, tx);
endmodule | 1 |
6,151 | data/full_repos/permissive/115403704/src/ALU.v | 115,403,704 | ALU.v | v | 36 | 72 | [] | [] | [] | [(17, 51)] | null | null | 1: b'%Error: data/full_repos/permissive/115403704/src/ALU.v:1: Cannot find include file: ./alu_def.v\n`include "./alu_def.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/./alu_def.v\n data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/./alu_def.v.v\n data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/./alu_def.v.sv\n ./alu_def.v\n ./alu_def.v.v\n ./alu_def.v.sv\n obj_dir/./alu_def.v\n obj_dir/./alu_def.v.v\n obj_dir/./alu_def.v.sv\n%Error: data/full_repos/permissive/115403704/src/ALU.v:22: Define or directive not defined: \'`ALU_ADD\'\n `ALU_ADD : C = A + B;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:22: syntax error, unexpected \':\', expecting endcase\n `ALU_ADD : C = A + B;\n ^\n%Error: data/full_repos/permissive/115403704/src/ALU.v:23: Define or directive not defined: \'`ALU_SUB\'\n `ALU_SUB : C = A - B;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:24: Define or directive not defined: \'`ALU_SLT\'\n `ALU_SLT : C = $signed(A) < $signed(B) ? 1 : 0;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:25: Define or directive not defined: \'`ALU_SLTU\'\n `ALU_SLTU: C = A < B ? 1 : 0;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:26: Define or directive not defined: \'`ALU_XOR\'\n `ALU_XOR : C = A ^ B;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:27: Define or directive not defined: \'`ALU_AND\'\n `ALU_AND : C = A & B;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:28: Define or directive not defined: \'`ALU_OR\'\n `ALU_OR : C = A | B;\n ^~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:29: Define or directive not defined: \'`ALU_NOR\'\n `ALU_NOR : C = ~(A | B);\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:30: Define or directive not defined: \'`ALU_LUI\'\n `ALU_LUI : C = {B[15:0] , 16\'d0};\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:31: Define or directive not defined: \'`ALU_SLL\'\n `ALU_SLL : C = B << A[4:0];\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:32: Define or directive not defined: \'`ALU_SRL\'\n `ALU_SRL : C = B >> A[4:0];\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:33: Define or directive not defined: \'`ALU_SRA\'\n `ALU_SRA : C = (B >> A[4:0]) | ({32{B[31]}}<<(6\'d32-{1\'b0,A[4:0]}));\n ^~~~~~~~\n%Error: Cannot continue\n' | 6,909 | module | module ALU(C,Zero,A,B,ALUOp,A_First,A_Zero);
input [31:0] A;
input [31:0] B;
input [3:0] ALUOp;
output reg[31:0] C;
output Zero;
output A_First;
output A_Zero;
initial
begin
C = 0;
end
assign Zero = (C==0) ? 1 : 0;
assign A_First = A[31];
assign A_Zero = (A==0)? 1 : 0;
always@(A or B or ALUOp)
begin
case (ALUOp)
`ALU_ADD : C = A + B;
`ALU_SUB : C = A - B;
`ALU_SLT : C = $signed(A) < $signed(B) ? 1 : 0;
`ALU_SLTU: C = A < B ? 1 : 0;
`ALU_XOR : C = A ^ B;
`ALU_AND : C = A & B;
`ALU_OR : C = A | B;
`ALU_NOR : C = ~(A | B);
`ALU_LUI : C = {B[15:0] , 16'd0};
`ALU_SLL : C = B << A[4:0];
`ALU_SRL : C = B >> A[4:0];
`ALU_SRA : C = (B >> A[4:0]) | ({32{B[31]}}<<(6'd32-{1'b0,A[4:0]}));
endcase
end
endmodule | module ALU(C,Zero,A,B,ALUOp,A_First,A_Zero); |
input [31:0] A;
input [31:0] B;
input [3:0] ALUOp;
output reg[31:0] C;
output Zero;
output A_First;
output A_Zero;
initial
begin
C = 0;
end
assign Zero = (C==0) ? 1 : 0;
assign A_First = A[31];
assign A_Zero = (A==0)? 1 : 0;
always@(A or B or ALUOp)
begin
case (ALUOp)
`ALU_ADD : C = A + B;
`ALU_SUB : C = A - B;
`ALU_SLT : C = $signed(A) < $signed(B) ? 1 : 0;
`ALU_SLTU: C = A < B ? 1 : 0;
`ALU_XOR : C = A ^ B;
`ALU_AND : C = A & B;
`ALU_OR : C = A | B;
`ALU_NOR : C = ~(A | B);
`ALU_LUI : C = {B[15:0] , 16'd0};
`ALU_SLL : C = B << A[4:0];
`ALU_SRL : C = B >> A[4:0];
`ALU_SRA : C = (B >> A[4:0]) | ({32{B[31]}}<<(6'd32-{1'b0,A[4:0]}));
endcase
end
endmodule | 0 |
6,152 | data/full_repos/permissive/115403704/src/B.v | 115,403,704 | B.v | v | 22 | 48 | [] | [] | [] | [(1, 22)] | null | data/verilator_xmls/32e99cd1-954e-41b9-8072-7c3881192fca.xml | null | 6,911 | module | module B(A_First,A_Zero,Zero,BFlag,instr,addr);
input A_First;
input A_Zero;
input Zero;
output reg BFlag;
input [31:26]instr;
input [4:0]addr;
always@(*)
begin
case(instr)
4:BFlag <= Zero;
5:BFlag <= ~Zero;
6:BFlag <= A_First||A_Zero;
7:BFlag <= (~A_First)&&(~A_Zero);
1:if (addr==5'b1)
BFlag <= ~A_First;
else
BFlag <= A_First;
endcase
end
endmodule | module B(A_First,A_Zero,Zero,BFlag,instr,addr); |
input A_First;
input A_Zero;
input Zero;
output reg BFlag;
input [31:26]instr;
input [4:0]addr;
always@(*)
begin
case(instr)
4:BFlag <= Zero;
5:BFlag <= ~Zero;
6:BFlag <= A_First||A_Zero;
7:BFlag <= (~A_First)&&(~A_Zero);
1:if (addr==5'b1)
BFlag <= ~A_First;
else
BFlag <= A_First;
endcase
end
endmodule | 0 |
6,153 | data/full_repos/permissive/115403704/src/BE.v | 115,403,704 | BE.v | v | 12 | 99 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/4330f8df-3fd5-43ff-8b4e-00a95c264e82.xml | null | 6,912 | module | module BEUnit(addr,instr,beout);
input [1:0]addr;
input [5:0]instr;
output [3:0]beout;
assign beout[3] = (instr==6'h2b) || (instr==6'h29&&addr[1]==1) || (instr==6'h28&&addr==2'b11);
assign beout[2] = (instr==6'h2b) || (instr==6'h29&&addr[1]==1) || (instr==6'h28&&addr==2'b10);
assign beout[1] = (instr==6'h2b) || (instr==6'h29&&addr[1]==0) || (instr==6'h28&&addr==2'b01);
assign beout[0] = (instr==6'h2b) || (instr==6'h29&&addr[1]==0) || (instr==6'h28&&addr==2'b00);
endmodule | module BEUnit(addr,instr,beout); |
input [1:0]addr;
input [5:0]instr;
output [3:0]beout;
assign beout[3] = (instr==6'h2b) || (instr==6'h29&&addr[1]==1) || (instr==6'h28&&addr==2'b11);
assign beout[2] = (instr==6'h2b) || (instr==6'h29&&addr[1]==1) || (instr==6'h28&&addr==2'b10);
assign beout[1] = (instr==6'h2b) || (instr==6'h29&&addr[1]==0) || (instr==6'h28&&addr==2'b01);
assign beout[0] = (instr==6'h2b) || (instr==6'h29&&addr[1]==0) || (instr==6'h28&&addr==2'b00);
endmodule | 0 |
6,154 | data/full_repos/permissive/115403704/src/ctrl.v | 115,403,704 | ctrl.v | v | 241 | 117 | [] | [] | [] | null | line:243: before: "$" | null | 1: b'%Error: data/full_repos/permissive/115403704/src/ctrl.v:1: Cannot find include file: ./alu_def.v\n`include "./alu_def.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/./alu_def.v\n data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/./alu_def.v.v\n data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/./alu_def.v.sv\n ./alu_def.v\n ./alu_def.v.v\n ./alu_def.v.sv\n obj_dir/./alu_def.v\n obj_dir/./alu_def.v.v\n obj_dir/./alu_def.v.sv\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:73: Define or directive not defined: \'`ALU_ADD\'\n ALUOp <= `ALU_ADD;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:73: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ALUOp <= `ALU_ADD;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:79: Define or directive not defined: \'`ALU_ADD\'\n ALUOp <= `ALU_ADD;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ALUOp <= `ALU_ADD;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:106: Define or directive not defined: \'`ALU_ADD\'\n 6\'h20,6\'h8,6\'h9:ALUOp <= `ALU_ADD;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:106: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h20,6\'h8,6\'h9:ALUOp <= `ALU_ADD;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:107: Define or directive not defined: \'`ALU_ADD\'\n 6\'h21:ALUOp <= `ALU_ADD;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:107: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h21:ALUOp <= `ALU_ADD;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:108: Define or directive not defined: \'`ALU_SUB\'\n 6\'h22:ALUOp <= `ALU_SUB;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h22:ALUOp <= `ALU_SUB;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:109: Define or directive not defined: \'`ALU_SUB\'\n 6\'h23:ALUOp <= `ALU_SUB;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:109: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h23:ALUOp <= `ALU_SUB;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:110: Define or directive not defined: \'`ALU_SLL\'\n 6\'h0 :ALUOp <= `ALU_SLL;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:110: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h0 :ALUOp <= `ALU_SLL;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:111: Define or directive not defined: \'`ALU_SRL\'\n 6\'h2 :ALUOp <= `ALU_SRL;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:111: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h2 :ALUOp <= `ALU_SRL;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:112: Define or directive not defined: \'`ALU_SRA\'\n 6\'h3 :ALUOp <= `ALU_SRA;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:112: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h3 :ALUOp <= `ALU_SRA;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:113: Define or directive not defined: \'`ALU_SLL\'\n 6\'h4 :ALUOp <= `ALU_SLL;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:113: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h4 :ALUOp <= `ALU_SLL;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:114: Define or directive not defined: \'`ALU_SRL\'\n 6\'h6 :ALUOp <= `ALU_SRL;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:114: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h6 :ALUOp <= `ALU_SRL;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:115: Define or directive not defined: \'`ALU_SRA\'\n 6\'h7 :ALUOp <= `ALU_SRA;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:115: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h7 :ALUOp <= `ALU_SRA;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:116: Define or directive not defined: \'`ALU_AND\'\n 6\'h24:ALUOp <= `ALU_AND;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:116: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h24:ALUOp <= `ALU_AND;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:117: Define or directive not defined: \'`ALU_OR\'\n 6\'h25:ALUOp <= `ALU_OR;\n ^~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:117: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h25:ALUOp <= `ALU_OR;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:118: Define or directive not defined: \'`ALU_XOR\'\n 6\'h26:ALUOp <= `ALU_XOR;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:118: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h26:ALUOp <= `ALU_XOR;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:119: Define or directive not defined: \'`ALU_NOR\'\n 6\'h27:ALUOp <= `ALU_NOR;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:119: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h27:ALUOp <= `ALU_NOR;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:120: Define or directive not defined: \'`ALU_SLT\'\n 6\'h2a:ALUOp <= `ALU_SLT;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:120: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h2a:ALUOp <= `ALU_SLT;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:121: Define or directive not defined: \'`ALU_SLTU\'\n 6\'h2b:ALUOp <= `ALU_SLTU;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:121: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h2b:ALUOp <= `ALU_SLTU;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:122: Define or directive not defined: \'`ALU_NOP\'\n default:ALUOp <= `ALU_NOP;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:122: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n default:ALUOp <= `ALU_NOP;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:124: Define or directive not defined: \'`ALU_ADD\'\n 6\'h8:ALUOp <= `ALU_ADD;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:124: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h8:ALUOp <= `ALU_ADD;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:125: Define or directive not defined: \'`ALU_ADD\'\n 6\'h9:ALUOp <= `ALU_ADD;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:125: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'h9:ALUOp <= `ALU_ADD;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:126: Define or directive not defined: \'`ALU_AND\'\n 6\'hc:ALUOp <= `ALU_AND;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:126: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'hc:ALUOp <= `ALU_AND;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:127: Define or directive not defined: \'`ALU_OR\'\n 6\'hd:ALUOp <= `ALU_OR;\n ^~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:127: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'hd:ALUOp <= `ALU_OR;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:128: Define or directive not defined: \'`ALU_XOR\'\n 6\'he:ALUOp <= `ALU_XOR;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:128: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 6\'he:ALUOp <= `ALU_XOR;\n ^\n%Error: data/full_repos/permissive/115403704/src/ctrl.v:129: Define or directive not defined: \'`ALU_LUI\'\n 6\'hf:ALUOp <= `ALU_LUI;\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,913 | module | module ctrl(clk, instruction, IRWr, RegWAd, DMWr, PCWrite, PCWriteCond,
PCSource, ALUOp, ALUSrcA, ALUSrcB, RFWr, RegWDa
);
input clk;
input [31:0] instruction;
output reg IRWr;
output reg [1:0]RegWAd;
output reg DMWr;
output reg PCWrite;
output reg PCWriteCond;
output reg [1:0] PCSource;
output reg [3:0] ALUOp;
output reg [1:0] ALUSrcA;
output reg [2:0] ALUSrcB;
output reg RFWr;
output reg [1:0]RegWDa;
integer i;
initial
begin
i = 0;
end
always @(posedge clk)
begin
case (i)
0:i=1;
1:i=2;
2:case(instruction[31:26])
6'h0,6'h8,6'h9,6'ha,6'hb,6'hc,6'hd,6'he,6'hf:i = 3;
6'h28,6'h29,6'h2b,6'h20,6'h21,6'h23,6'h24,6'h25:i=5;
6'h4,6'h5,6'h6,6'h7,6'h1:i=9;
6'h2,6'h3:i=10;
endcase
3:case(instruction[5:0])
6'h8,6'h9:if(instruction[31:26]==0)i=11;else i=4;
default:i=4;
endcase
4:i=1;
5:case(instruction[31:26])
6'h28,6'h29,6'h2b:i=6;
6'h20,6'h21,6'h23,6'h24,6'h25:i=7;
endcase
6:i=1;
7:i=8;
8:i=1;
9:i=1;
10:i=1;
11:i=1;
endcase
end
always @(negedge clk)
begin
case (i)
0:begin
PCWrite <= 0;
IRWr <=0;
DMWr <=0;
RFWr <=0;
PCWriteCond <= 0;
end
1:begin
RFWr <= 0;
IRWr <= 1;
DMWr <= 0;
PCWriteCond <= 0;
ALUSrcA <= 0;
ALUSrcB <= 1;
PCSource <= 0;
ALUOp <= `ALU_ADD;
PCWrite <= 1;
end
2:begin
ALUSrcA <= 0;
ALUSrcB <= 3;
ALUOp <= `ALU_ADD;
PCWriteCond <= 0;
IRWr <= 0;
RFWr <=0;
PCWrite <= 0;
DMWr <=0;
end
3:begin
IRWr <= 0;
RFWr <=0;
PCWrite <= 0;
DMWr <=0;
if ((instruction[5:0]==6'h0 || instruction[5:0]==6'h2 || instruction[5:0]==6'h3)&&instruction[31:26]==0)
ALUSrcA <= 2;
else
ALUSrcA <= 1;
if (instruction[31:26]==0)
ALUSrcB <= 0;
else
case(instruction[5:0])
6'hc,6'hd,6'he,6'hf,0'hb:ALUSrcB<=4;
default:ALUSrcB<=2;
endcase
PCWriteCond <= 0;
case(instruction[31:26])
6'h0:
case(instruction[5:0])
6'h20,6'h8,6'h9:ALUOp <= `ALU_ADD;
6'h21:ALUOp <= `ALU_ADD;
6'h22:ALUOp <= `ALU_SUB;
6'h23:ALUOp <= `ALU_SUB;
6'h0 :ALUOp <= `ALU_SLL;
6'h2 :ALUOp <= `ALU_SRL;
6'h3 :ALUOp <= `ALU_SRA;
6'h4 :ALUOp <= `ALU_SLL;
6'h6 :ALUOp <= `ALU_SRL;
6'h7 :ALUOp <= `ALU_SRA;
6'h24:ALUOp <= `ALU_AND;
6'h25:ALUOp <= `ALU_OR;
6'h26:ALUOp <= `ALU_XOR;
6'h27:ALUOp <= `ALU_NOR;
6'h2a:ALUOp <= `ALU_SLT;
6'h2b:ALUOp <= `ALU_SLTU;
default:ALUOp <= `ALU_NOP;
endcase
6'h8:ALUOp <= `ALU_ADD;
6'h9:ALUOp <= `ALU_ADD;
6'hc:ALUOp <= `ALU_AND;
6'hd:ALUOp <= `ALU_OR;
6'he:ALUOp <= `ALU_XOR;
6'hf:ALUOp <= `ALU_LUI;
6'ha:ALUOp <= `ALU_SLT;
6'hb:ALUOp <= `ALU_SLTU;
endcase
end
4:begin
IRWr <= 0;
PCWrite <= 0;
DMWr <=0;
RegWDa <= 0;
if (instruction[31:26]==0)
RegWAd <= 1;
else
RegWAd <= 0;
RFWr <= 1;
PCWriteCond <= 0;
end
5:begin
IRWr <= 0;
PCWrite <= 0;
DMWr <=0;
RegWDa <= 0;
PCWriteCond <= 0;
RFWr <=0;
ALUOp <= `ALU_ADD;
ALUSrcA <= 1;
ALUSrcB <= 2;
end
6:begin
DMWr<=1;
IRWr <= 0;
PCWrite <= 0;
RegWDa <= 0;
PCWriteCond <= 0;
RFWr <=0;
end
7:begin
IRWr <= 0;
PCWrite <= 0;
DMWr <=0;
RegWDa <= 0;
PCWriteCond <= 0;
RFWr <=0;
end
8:begin
IRWr <= 0;
PCWrite <= 0;
DMWr <=0;
RegWDa <= 0;
PCWriteCond <= 0;
RegWDa <= 1;
RegWAd <= 0;
RFWr <=1;
end
9:begin
IRWr <= 0;
PCWrite <= 0;
DMWr <=0;
RFWr <=0;
PCWriteCond <= 1;
ALUSrcA<=1;
ALUSrcB<=0;
ALUOp<=`ALU_SUB;
PCSource<=1;
end
10:begin
PCSource <=2;
PCWrite <= 1;
IRWr <= 0;
DMWr <=0;
PCWriteCond <= 0;
if(instruction[31:26]==2)
begin
RFWr <=0;
end
else if (instruction[31:26]==3)
begin
RFWr <=1;
RegWAd <= 2;
RegWDa <= 2;
end
end
11:begin
PCSource <=0;
PCWrite <= 1;
IRWr <= 0;
DMWr <=0;
PCWriteCond <= 0;
case(instruction[5:0])
0'h8:RFWr <=0;
0'h9:begin
RFWr <=1;
RegWAd <= 1;
RegWDa <= 2;
end
endcase
end
endcase
#2
$display("state:%d",i);
$display("IRWr:%d",IRWr);
$display("RFWr:%d",RFWr);
$display("DMWr:%d",DMWr);
$display("PCWrite:%d",PCWrite);
$display("PCWriteCond:%d",PCWriteCond);
$display("RegWAd:%d",RegWAd);
$display("RegWDa:%d",RegWDa);
$display("PCSource:%d",PCSource);
$display("ALUOp:%b",ALUOp);
$display("ALUSrcA:%d",ALUSrcA);
$display("ALUSrcB:%d",ALUSrcB);
end
endmodule | module ctrl(clk, instruction, IRWr, RegWAd, DMWr, PCWrite, PCWriteCond,
PCSource, ALUOp, ALUSrcA, ALUSrcB, RFWr, RegWDa
); |
input clk;
input [31:0] instruction;
output reg IRWr;
output reg [1:0]RegWAd;
output reg DMWr;
output reg PCWrite;
output reg PCWriteCond;
output reg [1:0] PCSource;
output reg [3:0] ALUOp;
output reg [1:0] ALUSrcA;
output reg [2:0] ALUSrcB;
output reg RFWr;
output reg [1:0]RegWDa;
integer i;
initial
begin
i = 0;
end
always @(posedge clk)
begin
case (i)
0:i=1;
1:i=2;
2:case(instruction[31:26])
6'h0,6'h8,6'h9,6'ha,6'hb,6'hc,6'hd,6'he,6'hf:i = 3;
6'h28,6'h29,6'h2b,6'h20,6'h21,6'h23,6'h24,6'h25:i=5;
6'h4,6'h5,6'h6,6'h7,6'h1:i=9;
6'h2,6'h3:i=10;
endcase
3:case(instruction[5:0])
6'h8,6'h9:if(instruction[31:26]==0)i=11;else i=4;
default:i=4;
endcase
4:i=1;
5:case(instruction[31:26])
6'h28,6'h29,6'h2b:i=6;
6'h20,6'h21,6'h23,6'h24,6'h25:i=7;
endcase
6:i=1;
7:i=8;
8:i=1;
9:i=1;
10:i=1;
11:i=1;
endcase
end
always @(negedge clk)
begin
case (i)
0:begin
PCWrite <= 0;
IRWr <=0;
DMWr <=0;
RFWr <=0;
PCWriteCond <= 0;
end
1:begin
RFWr <= 0;
IRWr <= 1;
DMWr <= 0;
PCWriteCond <= 0;
ALUSrcA <= 0;
ALUSrcB <= 1;
PCSource <= 0;
ALUOp <= `ALU_ADD;
PCWrite <= 1;
end
2:begin
ALUSrcA <= 0;
ALUSrcB <= 3;
ALUOp <= `ALU_ADD;
PCWriteCond <= 0;
IRWr <= 0;
RFWr <=0;
PCWrite <= 0;
DMWr <=0;
end
3:begin
IRWr <= 0;
RFWr <=0;
PCWrite <= 0;
DMWr <=0;
if ((instruction[5:0]==6'h0 || instruction[5:0]==6'h2 || instruction[5:0]==6'h3)&&instruction[31:26]==0)
ALUSrcA <= 2;
else
ALUSrcA <= 1;
if (instruction[31:26]==0)
ALUSrcB <= 0;
else
case(instruction[5:0])
6'hc,6'hd,6'he,6'hf,0'hb:ALUSrcB<=4;
default:ALUSrcB<=2;
endcase
PCWriteCond <= 0;
case(instruction[31:26])
6'h0:
case(instruction[5:0])
6'h20,6'h8,6'h9:ALUOp <= `ALU_ADD;
6'h21:ALUOp <= `ALU_ADD;
6'h22:ALUOp <= `ALU_SUB;
6'h23:ALUOp <= `ALU_SUB;
6'h0 :ALUOp <= `ALU_SLL;
6'h2 :ALUOp <= `ALU_SRL;
6'h3 :ALUOp <= `ALU_SRA;
6'h4 :ALUOp <= `ALU_SLL;
6'h6 :ALUOp <= `ALU_SRL;
6'h7 :ALUOp <= `ALU_SRA;
6'h24:ALUOp <= `ALU_AND;
6'h25:ALUOp <= `ALU_OR;
6'h26:ALUOp <= `ALU_XOR;
6'h27:ALUOp <= `ALU_NOR;
6'h2a:ALUOp <= `ALU_SLT;
6'h2b:ALUOp <= `ALU_SLTU;
default:ALUOp <= `ALU_NOP;
endcase
6'h8:ALUOp <= `ALU_ADD;
6'h9:ALUOp <= `ALU_ADD;
6'hc:ALUOp <= `ALU_AND;
6'hd:ALUOp <= `ALU_OR;
6'he:ALUOp <= `ALU_XOR;
6'hf:ALUOp <= `ALU_LUI;
6'ha:ALUOp <= `ALU_SLT;
6'hb:ALUOp <= `ALU_SLTU;
endcase
end
4:begin
IRWr <= 0;
PCWrite <= 0;
DMWr <=0;
RegWDa <= 0;
if (instruction[31:26]==0)
RegWAd <= 1;
else
RegWAd <= 0;
RFWr <= 1;
PCWriteCond <= 0;
end
5:begin
IRWr <= 0;
PCWrite <= 0;
DMWr <=0;
RegWDa <= 0;
PCWriteCond <= 0;
RFWr <=0;
ALUOp <= `ALU_ADD;
ALUSrcA <= 1;
ALUSrcB <= 2;
end
6:begin
DMWr<=1;
IRWr <= 0;
PCWrite <= 0;
RegWDa <= 0;
PCWriteCond <= 0;
RFWr <=0;
end
7:begin
IRWr <= 0;
PCWrite <= 0;
DMWr <=0;
RegWDa <= 0;
PCWriteCond <= 0;
RFWr <=0;
end
8:begin
IRWr <= 0;
PCWrite <= 0;
DMWr <=0;
RegWDa <= 0;
PCWriteCond <= 0;
RegWDa <= 1;
RegWAd <= 0;
RFWr <=1;
end
9:begin
IRWr <= 0;
PCWrite <= 0;
DMWr <=0;
RFWr <=0;
PCWriteCond <= 1;
ALUSrcA<=1;
ALUSrcB<=0;
ALUOp<=`ALU_SUB;
PCSource<=1;
end
10:begin
PCSource <=2;
PCWrite <= 1;
IRWr <= 0;
DMWr <=0;
PCWriteCond <= 0;
if(instruction[31:26]==2)
begin
RFWr <=0;
end
else if (instruction[31:26]==3)
begin
RFWr <=1;
RegWAd <= 2;
RegWDa <= 2;
end
end
11:begin
PCSource <=0;
PCWrite <= 1;
IRWr <= 0;
DMWr <=0;
PCWriteCond <= 0;
case(instruction[5:0])
0'h8:RFWr <=0;
0'h9:begin
RFWr <=1;
RegWAd <= 1;
RegWDa <= 2;
end
endcase
end
endcase
#2
$display("state:%d",i);
$display("IRWr:%d",IRWr);
$display("RFWr:%d",RFWr);
$display("DMWr:%d",DMWr);
$display("PCWrite:%d",PCWrite);
$display("PCWriteCond:%d",PCWriteCond);
$display("RegWAd:%d",RegWAd);
$display("RegWDa:%d",RegWDa);
$display("PCSource:%d",PCSource);
$display("ALUOp:%b",ALUOp);
$display("ALUSrcA:%d",ALUSrcA);
$display("ALUSrcB:%d",ALUSrcB);
end
endmodule | 0 |
6,155 | data/full_repos/permissive/115403704/src/im.v | 115,403,704 | im.v | v | 23 | 38 | [] | [] | [] | [(1, 22)] | null | data/verilator_xmls/99def31a-7c2f-4a90-bef5-40350e2c7419.xml | null | 6,916 | module | module im_4k(addr,dout);
input [11:2] addr;
output [31:0] dout;
reg [31:0] IMem[1023:0];
integer fp,count,reger,num;
initial
begin
fp=$fopen("test.txt","r");
num = 0;
while (!$feof(fp))
begin
count=$fscanf(fp,"%h",reger);
if(count==1)
begin
IMem[num]=reger;
num=num+1;
end
end
$fclose(fp);
end
assign dout = IMem[addr];
endmodule | module im_4k(addr,dout); |
input [11:2] addr;
output [31:0] dout;
reg [31:0] IMem[1023:0];
integer fp,count,reger,num;
initial
begin
fp=$fopen("test.txt","r");
num = 0;
while (!$feof(fp))
begin
count=$fscanf(fp,"%h",reger);
if(count==1)
begin
IMem[num]=reger;
num=num+1;
end
end
$fclose(fp);
end
assign dout = IMem[addr];
endmodule | 0 |
6,156 | data/full_repos/permissive/115403704/src/LHANDLE.v | 115,403,704 | LHANDLE.v | v | 33 | 57 | [] | [] | [] | [(1, 33)] | null | data/verilator_xmls/11f5c435-50ae-4437-8aff-11459c003af3.xml | null | 6,917 | module | module LHandle(instr,addr,in,out);
input [5:0]instr;
input [1:0]addr;
input [31:0]in;
output reg [31:0]out;
always@(*)
begin
case(instr)
6'h20:case(addr)
2'b00:out<={{24{in[7]}},in[7:0]};
2'b01:out<={{24{in[15]}},in[15:8]};
2'b10:out<={{24{in[23]}},in[23:16]};
2'b11:out<={{24{in[31]}},in[31:24]};
endcase
6'h24:case(addr)
2'b00:out<={24'b0,in[7:0]};
2'b01:out<={24'b0,in[15:8]};
2'b10:out<={24'b0,in[23:16]};
2'b11:out<={24'b0,in[31:24]};
endcase
6'h21:case(addr)
2'b00:out<={{16{in[15]}},in[15:0]};
2'b10:out<={{16{in[31]}},in[31:16]};
endcase
6'h25:case(addr)
2'b00:out<={16'b0,in[15:0]};
2'b10:out<={16'b0,in[31:16]};
endcase
6'h23:out<=in;
endcase
end
endmodule | module LHandle(instr,addr,in,out); |
input [5:0]instr;
input [1:0]addr;
input [31:0]in;
output reg [31:0]out;
always@(*)
begin
case(instr)
6'h20:case(addr)
2'b00:out<={{24{in[7]}},in[7:0]};
2'b01:out<={{24{in[15]}},in[15:8]};
2'b10:out<={{24{in[23]}},in[23:16]};
2'b11:out<={{24{in[31]}},in[31:24]};
endcase
6'h24:case(addr)
2'b00:out<={24'b0,in[7:0]};
2'b01:out<={24'b0,in[15:8]};
2'b10:out<={24'b0,in[23:16]};
2'b11:out<={24'b0,in[31:24]};
endcase
6'h21:case(addr)
2'b00:out<={{16{in[15]}},in[15:0]};
2'b10:out<={{16{in[31]}},in[31:16]};
endcase
6'h25:case(addr)
2'b00:out<={16'b0,in[15:0]};
2'b10:out<={16'b0,in[31:16]};
endcase
6'h23:out<=in;
endcase
end
endmodule | 0 |
6,157 | data/full_repos/permissive/115403704/src/mips.v | 115,403,704 | mips.v | v | 72 | 106 | [] | [] | [] | [(1, 71)] | null | null | 1: b"%Error: data/full_repos/permissive/115403704/src/mips.v:8: Cannot find file containing module: 'PCUnit'\n PCUnit my_pc(PCnex,PC,clk,PCin);\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/PCUnit\n data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/PCUnit.v\n data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/PCUnit.sv\n PCUnit\n PCUnit.v\n PCUnit.sv\n obj_dir/PCUnit\n obj_dir/PCUnit.v\n obj_dir/PCUnit.sv\n%Error: data/full_repos/permissive/115403704/src/mips.v:20: Cannot find file containing module: 'im_4k'\n im_4k my_im (PC[11:2],im_out);\n ^~~~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:21: Cannot find file containing module: 'dm_4k'\n dm_4k my_dm (ALUout_out[11:2],be,B_out,DMWr,clk,dm_out);\n ^~~~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:22: Cannot find file containing module: 'flopr'\n flopr #(32) IR(clk, IRWr, im_out,Instruction);\n ^~~~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:23: Cannot find file containing module: 'flopr'\n flopr #(32) MDR(clk, 1, MDR_in, MDR_out);\n ^~~~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:29: Cannot find file containing module: 'mux'\n mux #(4,2,5) WR_Ad_Sel(RegWAd,Write_Addr,Instruction[20:16],Instruction[15:11],5'b11111);\n ^~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:30: Cannot find file containing module: 'mux'\n mux #(4,2,32) WR_D_Sel(RegWDa,Write_Data,ALUout_out,MDR_out,PC);\n ^~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:36: Cannot find file containing module: 'RF'\n RF my_RF(Instruction[25:21],Instruction[20:16],Write_Addr,Write_Data,RFWr,clk,Read_Data1,Read_Data2);\n ^~\n%Error: data/full_repos/permissive/115403704/src/mips.v:37: Cannot find file containing module: 'flopr'\n flopr #(32) A(clk,1,Read_Data1,A_out);\n ^~~~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:38: Cannot find file containing module: 'flopr'\n flopr #(32) B(clk,1,Read_Data2,B_out);\n ^~~~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:51: Cannot find file containing module: 'mux'\n mux #(4,2,32) ALUAmux(ALUSrcA,ALU_A,PC,A_out,{27'b0,Instruction[10:6]});\n ^~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:52: Cannot find file containing module: 'mux'\n mux #(8,3,32) ALUBmux(ALUSrcB,ALU_B,B_out,32'd4,SE_out,{SE_out,2'b0},UE_out);\n ^~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:53: Cannot find file containing module: 'ALU'\n ALU my_alu(ALU_C,Zero,ALU_A,ALU_B,ALUOp,A_First,A_Zero);\n ^~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:54: Cannot find file containing module: 'flopr'\n flopr #(32) ALUout(clk,1,ALU_C,ALUout_out);\n ^~~~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:57: Cannot find file containing module: 'mux'\n mux #(4,2,32) PCsel(PCSource,PCnex,ALU_C,ALUout_out,{PC[31:28],Instruction[25:0],2'b0});\n ^~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:58: Cannot find file containing module: 'SE'\n SE my_SE(Instruction[15:0],SE_out);\n ^~\n%Error: data/full_repos/permissive/115403704/src/mips.v:59: Cannot find file containing module: 'UE'\n UE my_UE(Instruction[15:0],UE_out);\n ^~\n%Error: data/full_repos/permissive/115403704/src/mips.v:64: Cannot find file containing module: 'ctrl'\n ctrl my_ctrl(clk, Instruction, IRWr, RegWAd, DMWr, PCWrite, PCWriteCond, \n ^~~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:67: Cannot find file containing module: 'BEUnit'\n BEUnit my_BEUnit(ALUout_out[1:0],Instruction[31:26],be);\n ^~~~~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:68: Cannot find file containing module: 'LHandle'\n LHandle my_LHandle(Instruction[31:26],ALUout_out[1:0],dm_out,MDR_in);\n ^~~~~~~\n%Error: data/full_repos/permissive/115403704/src/mips.v:69: Cannot find file containing module: 'B'\n B my_B(A_First,A_Zero,Zero,BFlag,Instruction[31:26],Instruction[20:16]);\n ^\n%Error: Exiting due to 21 error(s)\n" | 6,918 | module | module mips(clk,rst);
input clk;
input rst;
wire [31:0] PCnex;
wire [31:0] PC;
wire PCin;
PCUnit my_pc(PCnex,PC,clk,PCin);
wire [31:0] im_out;
wire [31:0] ALUout_out;
wire [3:0] be;
wire [31:0] B_out;
wire DMWr;
wire [31:0] dm_out;
wire [31:0] MDR_in;
wire IRWr;
wire [31:0]Instruction;
wire [31:0] MDR_out;
im_4k my_im (PC[11:2],im_out);
dm_4k my_dm (ALUout_out[11:2],be,B_out,DMWr,clk,dm_out);
flopr #(32) IR(clk, IRWr, im_out,Instruction);
flopr #(32) MDR(clk, 1, MDR_in, MDR_out);
wire [1:0]RegWAd;
wire [1:0]RegWDa;
wire [4:0] Write_Addr;
wire [31:0] Write_Data;
mux #(4,2,5) WR_Ad_Sel(RegWAd,Write_Addr,Instruction[20:16],Instruction[15:11],5'b11111);
mux #(4,2,32) WR_D_Sel(RegWDa,Write_Data,ALUout_out,MDR_out,PC);
wire RFWr;
wire [31:0] Read_Data1;
wire [31:0] Read_Data2;
wire [31:0] A_out;
RF my_RF(Instruction[25:21],Instruction[20:16],Write_Addr,Write_Data,RFWr,clk,Read_Data1,Read_Data2);
flopr #(32) A(clk,1,Read_Data1,A_out);
flopr #(32) B(clk,1,Read_Data2,B_out);
wire [1:0]ALUSrcA;
wire [2:0] ALUSrcB;
wire [31:0] ALU_A;
wire [31:0] ALU_B;
wire [31:0] ALU_C;
wire [31:0] SE_out;
wire [31:0] UE_out;
wire Zero;
wire A_First;
wire A_Zero;
wire [3:0] ALUOp;
mux #(4,2,32) ALUAmux(ALUSrcA,ALU_A,PC,A_out,{27'b0,Instruction[10:6]});
mux #(8,3,32) ALUBmux(ALUSrcB,ALU_B,B_out,32'd4,SE_out,{SE_out,2'b0},UE_out);
ALU my_alu(ALU_C,Zero,ALU_A,ALU_B,ALUOp,A_First,A_Zero);
flopr #(32) ALUout(clk,1,ALU_C,ALUout_out);
wire [1:0] PCSource;
mux #(4,2,32) PCsel(PCSource,PCnex,ALU_C,ALUout_out,{PC[31:28],Instruction[25:0],2'b0});
SE my_SE(Instruction[15:0],SE_out);
UE my_UE(Instruction[15:0],UE_out);
wire PCWrite;
wire PCWriteCond;
wire BFlag;
ctrl my_ctrl(clk, Instruction, IRWr, RegWAd, DMWr, PCWrite, PCWriteCond,
PCSource, ALUOp, ALUSrcA, ALUSrcB, RFWr, RegWDa);
BEUnit my_BEUnit(ALUout_out[1:0],Instruction[31:26],be);
LHandle my_LHandle(Instruction[31:26],ALUout_out[1:0],dm_out,MDR_in);
B my_B(A_First,A_Zero,Zero,BFlag,Instruction[31:26],Instruction[20:16]);
assign PCin = (PCWrite) || (PCWriteCond&&BFlag);
endmodule | module mips(clk,rst); |
input clk;
input rst;
wire [31:0] PCnex;
wire [31:0] PC;
wire PCin;
PCUnit my_pc(PCnex,PC,clk,PCin);
wire [31:0] im_out;
wire [31:0] ALUout_out;
wire [3:0] be;
wire [31:0] B_out;
wire DMWr;
wire [31:0] dm_out;
wire [31:0] MDR_in;
wire IRWr;
wire [31:0]Instruction;
wire [31:0] MDR_out;
im_4k my_im (PC[11:2],im_out);
dm_4k my_dm (ALUout_out[11:2],be,B_out,DMWr,clk,dm_out);
flopr #(32) IR(clk, IRWr, im_out,Instruction);
flopr #(32) MDR(clk, 1, MDR_in, MDR_out);
wire [1:0]RegWAd;
wire [1:0]RegWDa;
wire [4:0] Write_Addr;
wire [31:0] Write_Data;
mux #(4,2,5) WR_Ad_Sel(RegWAd,Write_Addr,Instruction[20:16],Instruction[15:11],5'b11111);
mux #(4,2,32) WR_D_Sel(RegWDa,Write_Data,ALUout_out,MDR_out,PC);
wire RFWr;
wire [31:0] Read_Data1;
wire [31:0] Read_Data2;
wire [31:0] A_out;
RF my_RF(Instruction[25:21],Instruction[20:16],Write_Addr,Write_Data,RFWr,clk,Read_Data1,Read_Data2);
flopr #(32) A(clk,1,Read_Data1,A_out);
flopr #(32) B(clk,1,Read_Data2,B_out);
wire [1:0]ALUSrcA;
wire [2:0] ALUSrcB;
wire [31:0] ALU_A;
wire [31:0] ALU_B;
wire [31:0] ALU_C;
wire [31:0] SE_out;
wire [31:0] UE_out;
wire Zero;
wire A_First;
wire A_Zero;
wire [3:0] ALUOp;
mux #(4,2,32) ALUAmux(ALUSrcA,ALU_A,PC,A_out,{27'b0,Instruction[10:6]});
mux #(8,3,32) ALUBmux(ALUSrcB,ALU_B,B_out,32'd4,SE_out,{SE_out,2'b0},UE_out);
ALU my_alu(ALU_C,Zero,ALU_A,ALU_B,ALUOp,A_First,A_Zero);
flopr #(32) ALUout(clk,1,ALU_C,ALUout_out);
wire [1:0] PCSource;
mux #(4,2,32) PCsel(PCSource,PCnex,ALU_C,ALUout_out,{PC[31:28],Instruction[25:0],2'b0});
SE my_SE(Instruction[15:0],SE_out);
UE my_UE(Instruction[15:0],UE_out);
wire PCWrite;
wire PCWriteCond;
wire BFlag;
ctrl my_ctrl(clk, Instruction, IRWr, RegWAd, DMWr, PCWrite, PCWriteCond,
PCSource, ALUOp, ALUSrcA, ALUSrcB, RFWr, RegWDa);
BEUnit my_BEUnit(ALUout_out[1:0],Instruction[31:26],be);
LHandle my_LHandle(Instruction[31:26],ALUout_out[1:0],dm_out,MDR_in);
B my_B(A_First,A_Zero,Zero,BFlag,Instruction[31:26],Instruction[20:16]);
assign PCin = (PCWrite) || (PCWriteCond&&BFlag);
endmodule | 0 |
6,158 | data/full_repos/permissive/115403704/src/mips_tb.v | 115,403,704 | mips_tb.v | v | 16 | 27 | [] | [] | [] | [(1, 15)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115403704/src/mips_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n #20 clk<=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115403704/src/mips_tb.v:14: Cannot find file containing module: \'mips\'\n mips my_mips(clk,rst);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/mips\n data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/mips.v\n data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/mips.sv\n mips\n mips.v\n mips.sv\n obj_dir/mips\n obj_dir/mips.v\n obj_dir/mips.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,919 | module | module mips_tb();
`timescale 1ns/1ps
reg clk;
reg rst;
initial
begin
clk=1;
clk=0;
end
always
begin
#20 clk<=~clk;
end
mips my_mips(clk,rst);
endmodule | module mips_tb(); |
`timescale 1ns/1ps
reg clk;
reg rst;
initial
begin
clk=1;
clk=0;
end
always
begin
#20 clk<=~clk;
end
mips my_mips(clk,rst);
endmodule | 0 |
6,159 | data/full_repos/permissive/115403704/src/PC.v | 115,403,704 | PC.v | v | 21 | 39 | [] | [] | [] | [(1, 21)] | null | data/verilator_xmls/d9287cda-43d4-4343-a81b-95f74e60833d.xml | null | 6,921 | module | module PCUnit(in,PC,clk,sig);
output reg [31:0] PC;
input [31:0] in;
input clk;
input sig;
initial
begin
PC = 32'h0000_3000;
$display("PC: %h",PC);
end
always@(negedge clk)
begin
if (sig)
begin
PC = in;
$display("PC: %h",PC);
end
end
endmodule | module PCUnit(in,PC,clk,sig); |
output reg [31:0] PC;
input [31:0] in;
input clk;
input sig;
initial
begin
PC = 32'h0000_3000;
$display("PC: %h",PC);
end
always@(negedge clk)
begin
if (sig)
begin
PC = in;
$display("PC: %h",PC);
end
end
endmodule | 0 |
6,160 | data/full_repos/permissive/115403704/src/SE.v | 115,403,704 | SE.v | v | 7 | 36 | [] | [] | [] | [(1, 6)] | null | data/verilator_xmls/4b85209b-3efb-40ae-8d23-eecf82abdcca.xml | null | 6,923 | module | module SE(in,out);
input [15:0] in;
output [31:0] out;
assign out = {{16{in[15]}},in};
endmodule | module SE(in,out); |
input [15:0] in;
output [31:0] out;
assign out = {{16{in[15]}},in};
endmodule | 0 |
6,161 | data/full_repos/permissive/115403704/src/UE.v | 115,403,704 | UE.v | v | 8 | 29 | [] | [] | [] | [(1, 6)] | null | data/verilator_xmls/48c9dc4c-0c3c-46d8-a41b-1236c6b3fd0f.xml | null | 6,924 | module | module UE(in,out);
input [15:0] in;
output [31:0] out;
assign out = {16'b0,in};
endmodule | module UE(in,out); |
input [15:0] in;
output [31:0] out;
assign out = {16'b0,in};
endmodule | 0 |
6,162 | data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/ALU_MUXER.v | 115,487,336 | ALU_MUXER.v | v | 63 | 83 | [] | [] | [] | [(21, 62)] | null | data/verilator_xmls/2594bffd-ca5f-4127-9605-fe0b2e55fa95.xml | null | 6,926 | module | module ALU_MUXER(
input [31:0] regop1,
input [31:0] regop2,
input [15:0] imm,
input [25:0] jtypeImm,
input [1:0] optype,
output [31:0] aluip1,
output reg [31:0] aluip2
);
assign aluip1=regop1;
always@(*)
begin
if(optype==2'h0)
aluip2=regop2;
else if(optype==2'h1)
begin
if(imm[15]==0)
aluip2[31:16]=16'b0;
else
aluip2[31:16]=16'hFFFF;
aluip2[15:0]=imm;
end
else if(optype==2'h2)
begin
if(jtypeImm[25]==0)
aluip2[31:26]=6'b0;
else
aluip2[31:26]=6'b111111;
aluip2[25:0]=jtypeImm;
end
else
aluip2=32'b0;
end
endmodule | module ALU_MUXER(
input [31:0] regop1,
input [31:0] regop2,
input [15:0] imm,
input [25:0] jtypeImm,
input [1:0] optype,
output [31:0] aluip1,
output reg [31:0] aluip2
); |
assign aluip1=regop1;
always@(*)
begin
if(optype==2'h0)
aluip2=regop2;
else if(optype==2'h1)
begin
if(imm[15]==0)
aluip2[31:16]=16'b0;
else
aluip2[31:16]=16'hFFFF;
aluip2[15:0]=imm;
end
else if(optype==2'h2)
begin
if(jtypeImm[25]==0)
aluip2[31:26]=6'b0;
else
aluip2[31:26]=6'b111111;
aluip2[25:0]=jtypeImm;
end
else
aluip2=32'b0;
end
endmodule | 0 |
6,163 | data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/branch.v | 115,487,336 | branch.v | v | 62 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/2b64b359-869a-4fcf-8df1-10bf38eab6a3.xml | null | 6,927 | module | module branch(
input [31:0] now_addr,
input br,
input j_or_b,
input regnzp,
input [31:0] offset,
output reg pcmux,
output reg [31:0] addr
);
reg [31:0] tpof;
always@(*)
begin
if(br==0)
begin
pcmux=0;
end
else
begin
tpof=offset<<2;
if(j_or_b==1)
begin
addr=tpof;
pcmux=1;
end
else
begin
if(regnzp)
begin
addr=now_addr+tpof+32'h4;
pcmux=1;
end
else
pcmux=0;
end
end
end
endmodule | module branch(
input [31:0] now_addr,
input br,
input j_or_b,
input regnzp,
input [31:0] offset,
output reg pcmux,
output reg [31:0] addr
); |
reg [31:0] tpof;
always@(*)
begin
if(br==0)
begin
pcmux=0;
end
else
begin
tpof=offset<<2;
if(j_or_b==1)
begin
addr=tpof;
pcmux=1;
end
else
begin
if(regnzp)
begin
addr=now_addr+tpof+32'h4;
pcmux=1;
end
else
pcmux=0;
end
end
end
endmodule | 0 |
6,164 | data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/control.v | 115,487,336 | control.v | v | 154 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/bd616dbf-0564-49ae-a81a-3b49ad3d8479.xml | null | 6,928 | module | module control(
input clk,
input rst_n,
input [31:0] instruction,
output reg [1:0] optype,
output reg [4:0] aluop,
output reg reg_AOM,
output reg regwe,
output reg Wr,
output reg memwe,
output reg br,
output reg j_or_b
);
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
end
else
begin
end
end
reg [31:0] inter_instruct;
always@(*)
begin
inter_instruct=instruction;
aluop=5'b1;
case(inter_instruct[31:26])
6'b000000:
begin
if(inter_instruct[10:0]==11'h20)
begin
optype=2'h0;
reg_AOM=1;
regwe=1;
memwe=0;
Wr=0;
br=0;
end
end
6'b001000:
begin
optype=2'h1;
reg_AOM=1;
regwe=1;
memwe=0;
Wr=0;
br=0;
end
6'b100011:
begin
optype=2'h1;
regwe=1;
reg_AOM=0;
memwe=0;
Wr=0;
br=0;
end
6'b101011:
begin
optype=2'h1;
regwe=0;
reg_AOM=0;
memwe=1;
Wr=1;
br=0;
end
6'b000111:
begin
optype=2'h1;
regwe=0;
reg_AOM=0;
memwe=0;
Wr=0;
br=1;
j_or_b=0;
aluop=5'h7;
end
6'b000010:
begin
optype=2'h2;
regwe=0;
reg_AOM=0;
memwe=0;
Wr=0;
br=1;
j_or_b=1;
end
default:
begin
optype=2'h3;
regwe=0;
reg_AOM=0;
memwe=0;
Wr=0;
br=0;
end
endcase
end
endmodule | module control(
input clk,
input rst_n,
input [31:0] instruction,
output reg [1:0] optype,
output reg [4:0] aluop,
output reg reg_AOM,
output reg regwe,
output reg Wr,
output reg memwe,
output reg br,
output reg j_or_b
); |
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
end
else
begin
end
end
reg [31:0] inter_instruct;
always@(*)
begin
inter_instruct=instruction;
aluop=5'b1;
case(inter_instruct[31:26])
6'b000000:
begin
if(inter_instruct[10:0]==11'h20)
begin
optype=2'h0;
reg_AOM=1;
regwe=1;
memwe=0;
Wr=0;
br=0;
end
end
6'b001000:
begin
optype=2'h1;
reg_AOM=1;
regwe=1;
memwe=0;
Wr=0;
br=0;
end
6'b100011:
begin
optype=2'h1;
regwe=1;
reg_AOM=0;
memwe=0;
Wr=0;
br=0;
end
6'b101011:
begin
optype=2'h1;
regwe=0;
reg_AOM=0;
memwe=1;
Wr=1;
br=0;
end
6'b000111:
begin
optype=2'h1;
regwe=0;
reg_AOM=0;
memwe=0;
Wr=0;
br=1;
j_or_b=0;
aluop=5'h7;
end
6'b000010:
begin
optype=2'h2;
regwe=0;
reg_AOM=0;
memwe=0;
Wr=0;
br=1;
j_or_b=1;
end
default:
begin
optype=2'h3;
regwe=0;
reg_AOM=0;
memwe=0;
Wr=0;
br=0;
end
endcase
end
endmodule | 0 |
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