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6,438 | data/full_repos/permissive/116266634/mux32bit_testbench.v | 116,266,634 | mux32bit_testbench.v | v | 29 | 82 | [] | [] | [] | [(1, 28)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116266634/mux32bit_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\nselect = 1\'b0; #50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/116266634/mux32bit_testbench.v:24: Unsupported or unknown PLI call: $monitor\n$monitor(" n1 = %5b--in2 = %5b\\nout = %5b--select = %1b", in1, in2, out, select);\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,350 | module | module mux32bit_testbench();
reg[31:0] in1;
reg[31:0] in2;
reg select;
wire [31:0] out;
mux_2_1_32bit test(out, select, in1, in2);
initial begin
in1 = 32'b01010101010101010101011010101010;
in2 = 32'b11111111111111111111111111111111;
select = 1'b0; #50;
in1 = 32'b01010101010101010101011010101010;
in2 = 32'b11111111111111111111111111111111;
select = 1'b1;
end
initial begin
$monitor("İn1 = %5b--in2 = %5b\nout = %5b--select = %1b", in1, in2, out, select);
end
endmodule | module mux32bit_testbench(); |
reg[31:0] in1;
reg[31:0] in2;
reg select;
wire [31:0] out;
mux_2_1_32bit test(out, select, in1, in2);
initial begin
in1 = 32'b01010101010101010101011010101010;
in2 = 32'b11111111111111111111111111111111;
select = 1'b0; #50;
in1 = 32'b01010101010101010101011010101010;
in2 = 32'b11111111111111111111111111111111;
select = 1'b1;
end
initial begin
$monitor("İn1 = %5b--in2 = %5b\nout = %5b--select = %1b", in1, in2, out, select);
end
endmodule | 1 |
6,439 | data/full_repos/permissive/116266634/mux5bit_testbench.v | 116,266,634 | mux5bit_testbench.v | v | 29 | 82 | [] | [] | [] | [(1, 28)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116266634/mux5bit_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\nselect = 1\'b0; #50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/116266634/mux5bit_testbench.v:24: Unsupported or unknown PLI call: $monitor\n$monitor(" n1 = %5b--in2 = %5b\\nout = %5b--select = %1b", in1, in2, out, select);\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,351 | module | module mux5bit_testbench();
reg[4:0] in1;
reg[4:0] in2;
reg select;
wire [4:0] out;
mux_for_destination_register test(out, select, in1, in2);
initial begin
in1 = 32'b01010;
in2 = 32'b11111;
select = 1'b0; #50;
in1 = 32'b01010;
in2 = 32'b11111;
select = 1'b1;
end
initial begin
$monitor("İn1 = %5b--in2 = %5b\nout = %5b--select = %1b", in1, in2, out, select);
end
endmodule | module mux5bit_testbench(); |
reg[4:0] in1;
reg[4:0] in2;
reg select;
wire [4:0] out;
mux_for_destination_register test(out, select, in1, in2);
initial begin
in1 = 32'b01010;
in2 = 32'b11111;
select = 1'b0; #50;
in1 = 32'b01010;
in2 = 32'b11111;
select = 1'b1;
end
initial begin
$monitor("İn1 = %5b--in2 = %5b\nout = %5b--select = %1b", in1, in2, out, select);
end
endmodule | 1 |
6,442 | data/full_repos/permissive/116266634/sign_extender_26_to_32.v | 116,266,634 | sign_extender_26_to_32.v | v | 19 | 30 | [] | [] | [] | [(1, 18)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/116266634/sign_extender_26_to_32.v:12: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h3f\' generates 16 bits.\n : ... In instance sign_extender_26_to_32\n out[31:26] = 16\'b111111;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/116266634/sign_extender_26_to_32.v:14: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n : ... In instance sign_extender_26_to_32\n out[31:26] = 16\'b000000;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 7,355 | module | module sign_extender_26_to_32
(
input [25:0] in,
output reg [31:0] out
);
always @ (in) begin
out[25:0] = in[25:0];
if (in[15] == 1'b1)
out[31:26] = 16'b111111;
else
out[31:26] = 16'b000000;
end
endmodule | module sign_extender_26_to_32
(
input [25:0] in,
output reg [31:0] out
); |
always @ (in) begin
out[25:0] = in[25:0];
if (in[15] == 1'b1)
out[31:26] = 16'b111111;
else
out[31:26] = 16'b000000;
end
endmodule | 1 |
6,448 | data/full_repos/permissive/11630667/hdl/sha1.v | 11,630,667 | sha1.v | v | 138 | 121 | [] | [] | [] | [(28, 89), (94, 136)] | null | data/verilator_xmls/5c871fbc-6a54-4482-8aff-65318429aff4.xml | null | 7,360 | module | module sha1 (
input clk,
input [511:0] rx_data,
output reg [159:0] tx_hash
);
reg [31:0] pre_temp;
reg [511:0] delay_data;
always @ (posedge clk)
begin
pre_temp <= 32'hC3D2E1F0 + 32'h5A827999 + rx_data[`IDX(0)];
delay_data <= rx_data;
end
genvar i;
generate
for (i = 0; i < 80; i=i+1) begin : R
wire [511:0] data, tx_data;
wire [31:0] a, b, c, d, presum;
wire [31:0] tx_a, tx_b, tx_c, tx_d, tx_presum;
if (i == 0)
begin
assign data = delay_data;
assign {a, b, c, d, presum} = {32'h67452301, 32'hEFCDAB89, 32'h98BADCFE, 32'h10325476, pre_temp};
end
else
begin
assign data = R[i-1].tx_data;
assign {a, b, c, d, presum} = {R[i-1].tx_a, R[i-1].tx_b, R[i-1].tx_c, R[i-1].tx_d, R[i-1].tx_presum};
end
sha1_round # (.ROUND (i)) round (
.clk (clk),
.rx_w (data),
.rx_a (a), .rx_b (b), .rx_c (c), .rx_d (d), .rx_presum (presum),
.tx_w (tx_data),
.tx_a (tx_a), .tx_b (tx_b), .tx_c (tx_c), .tx_d (tx_d), .tx_presum (tx_presum)
);
end
endgenerate
reg [31:0] e_delay;
always @ (posedge clk)
begin
e_delay <= R[78].tx_d;
tx_hash[`IDX(4)] <= R[79].tx_a + 32'h67452301;
tx_hash[`IDX(3)] <= R[79].tx_b + 32'hEFCDAB89;
tx_hash[`IDX(2)] <= R[79].tx_c + 32'h98BADCFE;
tx_hash[`IDX(1)] <= R[79].tx_d + 32'h10325476;
tx_hash[`IDX(0)] <= e_delay + 32'hC3D2E1F0;
end
endmodule | module sha1 (
input clk,
input [511:0] rx_data,
output reg [159:0] tx_hash
); |
reg [31:0] pre_temp;
reg [511:0] delay_data;
always @ (posedge clk)
begin
pre_temp <= 32'hC3D2E1F0 + 32'h5A827999 + rx_data[`IDX(0)];
delay_data <= rx_data;
end
genvar i;
generate
for (i = 0; i < 80; i=i+1) begin : R
wire [511:0] data, tx_data;
wire [31:0] a, b, c, d, presum;
wire [31:0] tx_a, tx_b, tx_c, tx_d, tx_presum;
if (i == 0)
begin
assign data = delay_data;
assign {a, b, c, d, presum} = {32'h67452301, 32'hEFCDAB89, 32'h98BADCFE, 32'h10325476, pre_temp};
end
else
begin
assign data = R[i-1].tx_data;
assign {a, b, c, d, presum} = {R[i-1].tx_a, R[i-1].tx_b, R[i-1].tx_c, R[i-1].tx_d, R[i-1].tx_presum};
end
sha1_round # (.ROUND (i)) round (
.clk (clk),
.rx_w (data),
.rx_a (a), .rx_b (b), .rx_c (c), .rx_d (d), .rx_presum (presum),
.tx_w (tx_data),
.tx_a (tx_a), .tx_b (tx_b), .tx_c (tx_c), .tx_d (tx_d), .tx_presum (tx_presum)
);
end
endgenerate
reg [31:0] e_delay;
always @ (posedge clk)
begin
e_delay <= R[78].tx_d;
tx_hash[`IDX(4)] <= R[79].tx_a + 32'h67452301;
tx_hash[`IDX(3)] <= R[79].tx_b + 32'hEFCDAB89;
tx_hash[`IDX(2)] <= R[79].tx_c + 32'h98BADCFE;
tx_hash[`IDX(1)] <= R[79].tx_d + 32'h10325476;
tx_hash[`IDX(0)] <= e_delay + 32'hC3D2E1F0;
end
endmodule | 6 |
6,449 | data/full_repos/permissive/11630667/hdl/sha1.v | 11,630,667 | sha1.v | v | 138 | 121 | [] | [] | [] | [(28, 89), (94, 136)] | null | data/verilator_xmls/5c871fbc-6a54-4482-8aff-65318429aff4.xml | null | 7,360 | module | module sha1_round # (
parameter ROUND = 0
) (
input clk,
input [511:0] rx_w,
input [31:0] rx_a, rx_b, rx_c, rx_d, rx_presum,
output reg [511:0] tx_w,
output reg [31:0] tx_a, tx_b, tx_c, tx_d, tx_presum
);
generate
wire [31:0] k = (ROUND < 19) ? 32'h5A827999 : (ROUND < 39) ? 32'h6ED9EBA1 : (ROUND < 59) ? 32'h8F1BBCDC : 32'hCA62C1D6;
wire [31:0] f;
if (ROUND <= 19)
assign f = (rx_b & rx_c) | ((~rx_b) & rx_d);
else if (ROUND <= 39)
assign f = rx_b ^ rx_c ^ rx_d;
else if (ROUND <= 59)
assign f = (rx_b & rx_c) | (rx_b & rx_d) | (rx_c & rx_d);
else
assign f = rx_b ^ rx_c ^ rx_d;
endgenerate
wire [31:0] new_w = rx_w[`IDX(0)] ^ rx_w[`IDX(2)] ^ rx_w[`IDX(8)] ^ rx_w[`IDX(13)];
always @ (posedge clk)
begin
tx_w[`IDX(15)] <= {new_w[30:0], new_w[31]};
tx_w[479:0] <= rx_w[511:32];
tx_a <= {rx_a[26:0], rx_a[31:27]} + f + rx_presum;
tx_b <= rx_a;
tx_c <= {rx_b[1:0], rx_b[31:2]};
tx_d <= rx_c;
tx_presum <= rx_d + rx_w[`IDX(1)] + k;
end
endmodule | module sha1_round # (
parameter ROUND = 0
) (
input clk,
input [511:0] rx_w,
input [31:0] rx_a, rx_b, rx_c, rx_d, rx_presum,
output reg [511:0] tx_w,
output reg [31:0] tx_a, tx_b, tx_c, tx_d, tx_presum
); |
generate
wire [31:0] k = (ROUND < 19) ? 32'h5A827999 : (ROUND < 39) ? 32'h6ED9EBA1 : (ROUND < 59) ? 32'h8F1BBCDC : 32'hCA62C1D6;
wire [31:0] f;
if (ROUND <= 19)
assign f = (rx_b & rx_c) | ((~rx_b) & rx_d);
else if (ROUND <= 39)
assign f = rx_b ^ rx_c ^ rx_d;
else if (ROUND <= 59)
assign f = (rx_b & rx_c) | (rx_b & rx_d) | (rx_c & rx_d);
else
assign f = rx_b ^ rx_c ^ rx_d;
endgenerate
wire [31:0] new_w = rx_w[`IDX(0)] ^ rx_w[`IDX(2)] ^ rx_w[`IDX(8)] ^ rx_w[`IDX(13)];
always @ (posedge clk)
begin
tx_w[`IDX(15)] <= {new_w[30:0], new_w[31]};
tx_w[479:0] <= rx_w[511:32];
tx_a <= {rx_a[26:0], rx_a[31:27]} + f + rx_presum;
tx_b <= rx_a;
tx_c <= {rx_b[1:0], rx_b[31:2]};
tx_d <= rx_c;
tx_presum <= rx_d + rx_w[`IDX(1)] + k;
end
endmodule | 6 |
6,452 | data/full_repos/permissive/116308238/hdl/axilite_control.v | 116,308,238 | axilite_control.v | v | 620 | 118 | [] | [] | [] | [(6, 619)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/116308238/hdl/axilite_control.v:415: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance axilite_control\n axi_araddr <= 32\'b0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/116308238/hdl/axilite_control.v:554: Cannot find file containing module: \'wordalign\'\n wordalign align(\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116308238/hdl,data/full_repos/permissive/116308238/wordalign\n data/full_repos/permissive/116308238/hdl,data/full_repos/permissive/116308238/wordalign.v\n data/full_repos/permissive/116308238/hdl,data/full_repos/permissive/116308238/wordalign.sv\n wordalign\n wordalign.v\n wordalign.sv\n obj_dir/wordalign\n obj_dir/wordalign.v\n obj_dir/wordalign.sv\n%Error: data/full_repos/permissive/116308238/hdl/axilite_control.v:565: Cannot find file containing module: \'pckthandler\'\n pckthandler depacket(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/116308238/hdl/axilite_control.v:577: Cannot find file containing module: \'raw10_decoder\'\n raw10_decoder unpack(\n ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 7,362 | module | module axilite_control #
(
parameter integer N_DATA_LANES = 2,
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 5
)
(
output wire csi_intr,
input wire rxbyteclkhs_resetn,
input wire cl_stopstate,
output wire cl_enable,
input wire rxbyteclkhs,
input wire dl0_rxactivehs,
input wire dl0_rxsynchs,
output wire dl0_enable,
output wire dl0_forcerxmode,
input wire dl0_rxvalidhs,
input wire [7:0] dl0_rxdatahs,
input wire dl1_rxactivehs,
input wire dl1_rxsynchs,
output wire dl1_enable,
output wire dl1_forcerxmode,
input wire dl1_rxvalidhs,
input wire [7:0] dl1_rxdatahs,
output wire m_axis_tvalid,
output wire [63:0] m_axis_tdata,
output wire [7:0] m_axis_tstrb,
output wire m_axis_tlast,
input wire m_axis_tready,
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
input wire [2 : 0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [1 : 0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
input wire [2 : 0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
output wire [1 : 0] S_AXI_RRESP,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
localparam NUM_INTRS = 2;
localparam SOF_REG_BIT = 2;
localparam SOF_INTR_BIT = 0;
localparam EOF_REG_BIT = 3;
localparam OUTPUT_EN_BIT = 4;
localparam EOF_INTR_BIT = 1;
localparam GLOBALINT_BIT= 1;
localparam RS_REG_BIT = 0;
reg [(NUM_INTRS-1):0] irqs_posted, irqs_acked;
reg frame_active_new, frame_active_last;
reg RS_flag;
reg RS_new, RS_last;
reg enable_output;
wire reset;
wire [(N_DATA_LANES*8)-1:0] aligned_word_out;
wire aligned_word_valid;
wire frame_active;
wire frame_valid;
wire [(N_DATA_LANES*8)-1:0] frame_out;
wire [63:0] unpacked_out;
wire unpacked_out_valid;
wire unpacked_last;
wire last_packet;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 2;
reg [C_S_AXI_DATA_WIDTH-1:0] CSI_CONFIG_REG;
reg [C_S_AXI_DATA_WIDTH-1:0] CSI_CTRL_SET_REG;
reg [C_S_AXI_DATA_WIDTH-1:0] CSI_CTRL_CLEAR_REG;
reg [C_S_AXI_DATA_WIDTH-1:0] CSI_STATUS_REG;
reg [C_S_AXI_DATA_WIDTH-1:0] CSI_FR_LINES_REG;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (S_AXI_BREADY && axi_bvalid)
begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
axi_awaddr <= S_AXI_AWADDR;
end
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
begin
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
CSI_CONFIG_REG <= 0;
CSI_CTRL_SET_REG <= 0;
CSI_CTRL_CLEAR_REG <= 0;
CSI_STATUS_REG <= 0;
CSI_FR_LINES_REG <= 0;
slv_reg5 <= 0;
slv_reg6 <= 0;
slv_reg7 <= 0;
irqs_acked <= 0;
RS_new <= 0;
RS_last <= 0;
end
else begin
irqs_acked <= 0;
RS_last <= RS_new;
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
3'h0: begin
CSI_CONFIG_REG <= S_AXI_WDATA;
end
3'h1: begin
irqs_acked <= {2{S_AXI_WDATA[GLOBALINT_BIT]}} | {S_AXI_WDATA[EOF_REG_BIT], S_AXI_WDATA[SOF_REG_BIT]};
if(S_AXI_WDATA[0] & ~RS_flag) begin
RS_new <= 1'b1;
RS_last <= 1'b0;
end
end
3'h2: begin
if(S_AXI_WDATA[0] == 1'b1) begin
RS_new <= 1'b0;
end
end
3'h3: begin
CSI_STATUS_REG <= CSI_STATUS_REG;
end
3'h4: begin
CSI_FR_LINES_REG <= S_AXI_WDATA;
end
3'h5:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h6:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h7:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
CSI_CONFIG_REG <= CSI_CONFIG_REG;
CSI_CTRL_SET_REG <= CSI_CTRL_SET_REG;
CSI_CTRL_CLEAR_REG <= CSI_CTRL_CLEAR_REG;
CSI_STATUS_REG <= CSI_STATUS_REG;
CSI_FR_LINES_REG <= CSI_FR_LINES_REG;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end
endcase
end
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0;
end
else
begin
if (S_AXI_BREADY && axi_bvalid)
begin
axi_bvalid <= 1'b0;
end
end
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
axi_arready <= 1'b1;
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0;
end
else if (axi_rvalid && S_AXI_RREADY)
begin
axi_rvalid <= 1'b0;
end
end
end
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
3'h0 : reg_data_out <= CSI_CONFIG_REG;
3'h1 : reg_data_out <= 0;
3'h2 : reg_data_out <= 0;
3'h3 : begin
reg_data_out[31:4] <= 0;
reg_data_out[3] <= irqs_posted[EOF_INTR_BIT];
reg_data_out[2] <= irqs_posted[SOF_INTR_BIT];
reg_data_out[1] <= (| irqs_posted);
reg_data_out[0] <= RS_flag;
end
3'h4 : reg_data_out <= CSI_FR_LINES_REG;
3'h5 : reg_data_out <= 32'hDEADBEEF;
3'h6 : reg_data_out <= 32'hDEADBEEF;
3'h7 : reg_data_out <= 32'hDEADBEEF;
default : reg_data_out <= 0;
endcase
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out;
end
end
end
assign reset = ~rxbyteclkhs_resetn | ~RS_flag;
assign csi_intr = CSI_CONFIG_REG[GLOBALINT_BIT] & (| (irqs_posted & CSI_CONFIG_REG[EOF_REG_BIT:SOF_REG_BIT]));
always @(posedge S_AXI_ACLK)
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
irqs_posted <= 0;
frame_active_new <= 0;
frame_active_last <= 0;
end
else begin
frame_active_new <= frame_active;
frame_active_last <= frame_active_new;
if(~frame_active_last & frame_active_new) irqs_posted[SOF_INTR_BIT] <= 1'b1;
else if(frame_active_last & ~frame_active_new) irqs_posted[EOF_INTR_BIT] <= 1'b1;
else begin
irqs_posted[SOF_INTR_BIT] <= irqs_posted[SOF_INTR_BIT] & ~irqs_acked[SOF_INTR_BIT];
irqs_posted[EOF_INTR_BIT] <= irqs_posted[EOF_INTR_BIT] & ~irqs_acked[EOF_INTR_BIT];
end
end
end
always @(posedge S_AXI_ACLK)
begin
if ( S_AXI_ARESETN == 1'b0 ) RS_flag <= 0;
else begin
if(RS_last & ~RS_new) RS_flag <= 1'b0;
else if(~RS_last & RS_new) RS_flag <= 1'b1;
else if(~CSI_CONFIG_REG[RS_REG_BIT] & ~frame_active_new & frame_active_last) RS_flag <= 1'b0;
else RS_flag <= RS_flag;
end
end
wordalign align(
.clk(rxbyteclkhs),
.resetn(rxbyteclkhs_resetn),
.dl0_rxvalidhs(dl0_rxvalidhs),
.dl0_rxdatahs(dl0_rxdatahs),
.dl1_rxvalidhs(dl1_rxvalidhs),
.dl1_rxdatahs(dl1_rxdatahs),
.word_out(aligned_word_out),
.word_valid(aligned_word_valid)
);
pckthandler depacket(
.rxbyteclkhs(rxbyteclkhs),
.reset(reset),
.in_stream_valid(aligned_word_valid),
.in_stream(aligned_word_out),
.frame_active(frame_active),
.frame_valid(frame_valid),
.out_stream(frame_out),
.lines_per_frame(CSI_FR_LINES_REG),
.last_packet(last_packet)
);
raw10_decoder unpack(
.rxbyteclkhs(rxbyteclkhs),
.reset(reset),
.frame_active(frame_active),
.frame_valid(frame_valid),
.data_in(frame_out),
.out_valid(unpacked_out_valid),
.data_out(unpacked_out),
.last_packet_in(last_packet),
.last_packet_out(unpacked_last)
);
always @(posedge S_AXI_ACLK)
begin
if ( S_AXI_ARESETN == 1'b0 )
enable_output <= 0;
else if(~frame_active_last & frame_active_new)
enable_output <= CSI_CONFIG_REG[OUTPUT_EN_BIT];
else
enable_output <= enable_output;
end
assign m_axis_tdata = enable_output ? unpacked_out : 0;
assign m_axis_tvalid = enable_output ? unpacked_out_valid : 0;
assign m_axis_tstrb = enable_output ? 8'b11111111 : 0;
assign m_axis_tlast = enable_output ? unpacked_last : 0;
assign cl_enable = 1'b1;
assign dl0_enable = 1'b1;
assign dl1_enable = 1'b1;
assign dl0_forcerxmode = 1'b1;
assign dl1_forcerxmode = 1'b1;
endmodule | module axilite_control #
(
parameter integer N_DATA_LANES = 2,
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 5
)
(
output wire csi_intr,
input wire rxbyteclkhs_resetn,
input wire cl_stopstate,
output wire cl_enable,
input wire rxbyteclkhs,
input wire dl0_rxactivehs,
input wire dl0_rxsynchs,
output wire dl0_enable,
output wire dl0_forcerxmode,
input wire dl0_rxvalidhs,
input wire [7:0] dl0_rxdatahs,
input wire dl1_rxactivehs,
input wire dl1_rxsynchs,
output wire dl1_enable,
output wire dl1_forcerxmode,
input wire dl1_rxvalidhs,
input wire [7:0] dl1_rxdatahs,
output wire m_axis_tvalid,
output wire [63:0] m_axis_tdata,
output wire [7:0] m_axis_tstrb,
output wire m_axis_tlast,
input wire m_axis_tready,
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
input wire [2 : 0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [1 : 0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
input wire [2 : 0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
output wire [1 : 0] S_AXI_RRESP,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
); |
localparam NUM_INTRS = 2;
localparam SOF_REG_BIT = 2;
localparam SOF_INTR_BIT = 0;
localparam EOF_REG_BIT = 3;
localparam OUTPUT_EN_BIT = 4;
localparam EOF_INTR_BIT = 1;
localparam GLOBALINT_BIT= 1;
localparam RS_REG_BIT = 0;
reg [(NUM_INTRS-1):0] irqs_posted, irqs_acked;
reg frame_active_new, frame_active_last;
reg RS_flag;
reg RS_new, RS_last;
reg enable_output;
wire reset;
wire [(N_DATA_LANES*8)-1:0] aligned_word_out;
wire aligned_word_valid;
wire frame_active;
wire frame_valid;
wire [(N_DATA_LANES*8)-1:0] frame_out;
wire [63:0] unpacked_out;
wire unpacked_out_valid;
wire unpacked_last;
wire last_packet;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 2;
reg [C_S_AXI_DATA_WIDTH-1:0] CSI_CONFIG_REG;
reg [C_S_AXI_DATA_WIDTH-1:0] CSI_CTRL_SET_REG;
reg [C_S_AXI_DATA_WIDTH-1:0] CSI_CTRL_CLEAR_REG;
reg [C_S_AXI_DATA_WIDTH-1:0] CSI_STATUS_REG;
reg [C_S_AXI_DATA_WIDTH-1:0] CSI_FR_LINES_REG;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (S_AXI_BREADY && axi_bvalid)
begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
axi_awaddr <= S_AXI_AWADDR;
end
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
begin
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
CSI_CONFIG_REG <= 0;
CSI_CTRL_SET_REG <= 0;
CSI_CTRL_CLEAR_REG <= 0;
CSI_STATUS_REG <= 0;
CSI_FR_LINES_REG <= 0;
slv_reg5 <= 0;
slv_reg6 <= 0;
slv_reg7 <= 0;
irqs_acked <= 0;
RS_new <= 0;
RS_last <= 0;
end
else begin
irqs_acked <= 0;
RS_last <= RS_new;
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
3'h0: begin
CSI_CONFIG_REG <= S_AXI_WDATA;
end
3'h1: begin
irqs_acked <= {2{S_AXI_WDATA[GLOBALINT_BIT]}} | {S_AXI_WDATA[EOF_REG_BIT], S_AXI_WDATA[SOF_REG_BIT]};
if(S_AXI_WDATA[0] & ~RS_flag) begin
RS_new <= 1'b1;
RS_last <= 1'b0;
end
end
3'h2: begin
if(S_AXI_WDATA[0] == 1'b1) begin
RS_new <= 1'b0;
end
end
3'h3: begin
CSI_STATUS_REG <= CSI_STATUS_REG;
end
3'h4: begin
CSI_FR_LINES_REG <= S_AXI_WDATA;
end
3'h5:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h6:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h7:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
CSI_CONFIG_REG <= CSI_CONFIG_REG;
CSI_CTRL_SET_REG <= CSI_CTRL_SET_REG;
CSI_CTRL_CLEAR_REG <= CSI_CTRL_CLEAR_REG;
CSI_STATUS_REG <= CSI_STATUS_REG;
CSI_FR_LINES_REG <= CSI_FR_LINES_REG;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end
endcase
end
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0;
end
else
begin
if (S_AXI_BREADY && axi_bvalid)
begin
axi_bvalid <= 1'b0;
end
end
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
axi_arready <= 1'b1;
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0;
end
else if (axi_rvalid && S_AXI_RREADY)
begin
axi_rvalid <= 1'b0;
end
end
end
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
3'h0 : reg_data_out <= CSI_CONFIG_REG;
3'h1 : reg_data_out <= 0;
3'h2 : reg_data_out <= 0;
3'h3 : begin
reg_data_out[31:4] <= 0;
reg_data_out[3] <= irqs_posted[EOF_INTR_BIT];
reg_data_out[2] <= irqs_posted[SOF_INTR_BIT];
reg_data_out[1] <= (| irqs_posted);
reg_data_out[0] <= RS_flag;
end
3'h4 : reg_data_out <= CSI_FR_LINES_REG;
3'h5 : reg_data_out <= 32'hDEADBEEF;
3'h6 : reg_data_out <= 32'hDEADBEEF;
3'h7 : reg_data_out <= 32'hDEADBEEF;
default : reg_data_out <= 0;
endcase
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out;
end
end
end
assign reset = ~rxbyteclkhs_resetn | ~RS_flag;
assign csi_intr = CSI_CONFIG_REG[GLOBALINT_BIT] & (| (irqs_posted & CSI_CONFIG_REG[EOF_REG_BIT:SOF_REG_BIT]));
always @(posedge S_AXI_ACLK)
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
irqs_posted <= 0;
frame_active_new <= 0;
frame_active_last <= 0;
end
else begin
frame_active_new <= frame_active;
frame_active_last <= frame_active_new;
if(~frame_active_last & frame_active_new) irqs_posted[SOF_INTR_BIT] <= 1'b1;
else if(frame_active_last & ~frame_active_new) irqs_posted[EOF_INTR_BIT] <= 1'b1;
else begin
irqs_posted[SOF_INTR_BIT] <= irqs_posted[SOF_INTR_BIT] & ~irqs_acked[SOF_INTR_BIT];
irqs_posted[EOF_INTR_BIT] <= irqs_posted[EOF_INTR_BIT] & ~irqs_acked[EOF_INTR_BIT];
end
end
end
always @(posedge S_AXI_ACLK)
begin
if ( S_AXI_ARESETN == 1'b0 ) RS_flag <= 0;
else begin
if(RS_last & ~RS_new) RS_flag <= 1'b0;
else if(~RS_last & RS_new) RS_flag <= 1'b1;
else if(~CSI_CONFIG_REG[RS_REG_BIT] & ~frame_active_new & frame_active_last) RS_flag <= 1'b0;
else RS_flag <= RS_flag;
end
end
wordalign align(
.clk(rxbyteclkhs),
.resetn(rxbyteclkhs_resetn),
.dl0_rxvalidhs(dl0_rxvalidhs),
.dl0_rxdatahs(dl0_rxdatahs),
.dl1_rxvalidhs(dl1_rxvalidhs),
.dl1_rxdatahs(dl1_rxdatahs),
.word_out(aligned_word_out),
.word_valid(aligned_word_valid)
);
pckthandler depacket(
.rxbyteclkhs(rxbyteclkhs),
.reset(reset),
.in_stream_valid(aligned_word_valid),
.in_stream(aligned_word_out),
.frame_active(frame_active),
.frame_valid(frame_valid),
.out_stream(frame_out),
.lines_per_frame(CSI_FR_LINES_REG),
.last_packet(last_packet)
);
raw10_decoder unpack(
.rxbyteclkhs(rxbyteclkhs),
.reset(reset),
.frame_active(frame_active),
.frame_valid(frame_valid),
.data_in(frame_out),
.out_valid(unpacked_out_valid),
.data_out(unpacked_out),
.last_packet_in(last_packet),
.last_packet_out(unpacked_last)
);
always @(posedge S_AXI_ACLK)
begin
if ( S_AXI_ARESETN == 1'b0 )
enable_output <= 0;
else if(~frame_active_last & frame_active_new)
enable_output <= CSI_CONFIG_REG[OUTPUT_EN_BIT];
else
enable_output <= enable_output;
end
assign m_axis_tdata = enable_output ? unpacked_out : 0;
assign m_axis_tvalid = enable_output ? unpacked_out_valid : 0;
assign m_axis_tstrb = enable_output ? 8'b11111111 : 0;
assign m_axis_tlast = enable_output ? unpacked_last : 0;
assign cl_enable = 1'b1;
assign dl0_enable = 1'b1;
assign dl1_enable = 1'b1;
assign dl0_forcerxmode = 1'b1;
assign dl1_forcerxmode = 1'b1;
endmodule | 31 |
6,454 | data/full_repos/permissive/116308238/hdl/ecc_block.v | 116,308,238 | ecc_block.v | v | 71 | 142 | [] | [] | [] | [(14, 71)] | null | data/verilator_xmls/0cab4b0a-c067-47d1-8da3-8d07de440a52.xml | null | 7,364 | module | module ecc_block(PH_in, PH_out, no_error, corrected_error, error);
parameter PH_SIZE = 32;
parameter ECC_SIZE = 8;
input [(PH_SIZE-1):0] PH_in;
output reg [(PH_SIZE-ECC_SIZE-1):0] PH_out;
output reg no_error, corrected_error, error;
wire [(PH_SIZE-ECC_SIZE-1):0] data = PH_in[(PH_SIZE-ECC_SIZE-1):0];
reg [(ECC_SIZE-1):0] calc_ecc;
reg [(ECC_SIZE-1):0] syndrome;
always @(*) begin
calc_ecc = {2'b00,
(^ {data[10], data[11], data[12], data[13], data[14], data[15], data[16], data[17], data[18], data[19], data[21], data[22], data[23]}),
(^ {data[4], data[5], data[6], data[7], data[8], data[9], data[16], data[17], data[18], data[19], data[20], data[22], data[23]}),
(^ {data[1], data[2], data[3], data[7], data[8], data[9], data[13], data[14], data[15], data[19], data[20], data[21], data[23]}),
(^ {data[0], data[2], data[3], data[5], data[6], data[9], data[11], data[12], data[15], data[18], data[20], data[21], data[22]}),
(^ {data[0], data[1], data[3], data[4], data[6], data[8], data[10], data[12], data[14], data[17], data[20], data[21], data[22], data[23]}),
(^ {data[0], data[1], data[2], data[4], data[5], data[7], data[10], data[11], data[13], data[16], data[20], data[21], data[22], data[23]})
};
syndrome = PH_in[(PH_SIZE-1):(PH_SIZE-ECC_SIZE)] ^ calc_ecc;
case(syndrome)
8'h07 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<0); end
8'h0B : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<1); end
8'h0D : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<2); end
8'h0E : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<3); end
8'h13 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<4); end
8'h15 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<5); end
8'h16 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<6); end
8'h19 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<7); end
8'h1A : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<8); end
8'h1C : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<9); end
8'h23 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<10); end
8'h25 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<11); end
8'h26 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<12); end
8'h29 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<13); end
8'h2A : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<14); end
8'h2C : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<15); end
8'h31 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<16); end
8'h32 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<17); end
8'h34 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<18); end
8'h38 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<19); end
8'h1F : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<20); end
8'h2F : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<21); end
8'h37 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<22); end
8'h3B : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<23); end
8'h00 : begin {no_error, corrected_error, error} = 3'b100; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0]; end
default: begin {no_error, corrected_error, error} = 3'b001; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0]; end
endcase
end
endmodule | module ecc_block(PH_in, PH_out, no_error, corrected_error, error); |
parameter PH_SIZE = 32;
parameter ECC_SIZE = 8;
input [(PH_SIZE-1):0] PH_in;
output reg [(PH_SIZE-ECC_SIZE-1):0] PH_out;
output reg no_error, corrected_error, error;
wire [(PH_SIZE-ECC_SIZE-1):0] data = PH_in[(PH_SIZE-ECC_SIZE-1):0];
reg [(ECC_SIZE-1):0] calc_ecc;
reg [(ECC_SIZE-1):0] syndrome;
always @(*) begin
calc_ecc = {2'b00,
(^ {data[10], data[11], data[12], data[13], data[14], data[15], data[16], data[17], data[18], data[19], data[21], data[22], data[23]}),
(^ {data[4], data[5], data[6], data[7], data[8], data[9], data[16], data[17], data[18], data[19], data[20], data[22], data[23]}),
(^ {data[1], data[2], data[3], data[7], data[8], data[9], data[13], data[14], data[15], data[19], data[20], data[21], data[23]}),
(^ {data[0], data[2], data[3], data[5], data[6], data[9], data[11], data[12], data[15], data[18], data[20], data[21], data[22]}),
(^ {data[0], data[1], data[3], data[4], data[6], data[8], data[10], data[12], data[14], data[17], data[20], data[21], data[22], data[23]}),
(^ {data[0], data[1], data[2], data[4], data[5], data[7], data[10], data[11], data[13], data[16], data[20], data[21], data[22], data[23]})
};
syndrome = PH_in[(PH_SIZE-1):(PH_SIZE-ECC_SIZE)] ^ calc_ecc;
case(syndrome)
8'h07 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<0); end
8'h0B : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<1); end
8'h0D : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<2); end
8'h0E : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<3); end
8'h13 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<4); end
8'h15 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<5); end
8'h16 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<6); end
8'h19 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<7); end
8'h1A : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<8); end
8'h1C : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<9); end
8'h23 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<10); end
8'h25 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<11); end
8'h26 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<12); end
8'h29 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<13); end
8'h2A : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<14); end
8'h2C : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<15); end
8'h31 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<16); end
8'h32 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<17); end
8'h34 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<18); end
8'h38 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<19); end
8'h1F : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<20); end
8'h2F : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<21); end
8'h37 : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<22); end
8'h3B : begin {no_error, corrected_error, error} = 3'b010; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0] ^ (1<<23); end
8'h00 : begin {no_error, corrected_error, error} = 3'b100; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0]; end
default: begin {no_error, corrected_error, error} = 3'b001; PH_out = PH_in[(PH_SIZE-ECC_SIZE-1):0]; end
endcase
end
endmodule | 31 |
6,456 | data/full_repos/permissive/116308238/hdl/pckthandler_fsm.v | 116,308,238 | pckthandler_fsm.v | v | 128 | 103 | [] | [] | [] | [(20, 128)] | null | data/verilator_xmls/7fdf11cd-88b9-4ead-8943-497c23de2336.xml | null | 7,366 | module | module pckthandler_fsm(rxbyteclkhs, reset, data_stream, ph_stream, ph_select, valid_stream, ecc_error,
out_stream, frame_active, frame_valid, lines_per_frame, last_packet
);
parameter DATA_STREAM_WIDTH = 16;
parameter PH_STREAM_WIDTH = 24;
input rxbyteclkhs, reset, ph_select, valid_stream, ecc_error;
input [(DATA_STREAM_WIDTH-1):0] data_stream;
input [(PH_STREAM_WIDTH-1):0] ph_stream;
input [31:0] lines_per_frame;
output frame_active, frame_valid;
output [(DATA_STREAM_WIDTH-1):0] out_stream;
output last_packet;
reg frame_active, frame_valid;
reg [(DATA_STREAM_WIDTH-1):0] out_stream;
wire sof_id, eof_id, pxdata_id;
assign sof_id = (ph_stream[5:0] == 6'h00) ? 1'b1 : 1'b0;
assign eof_id = (ph_stream[5:0] == 6'h01) ? 1'b1 : 1'b0;
assign pxdata_id = (ph_stream[5:0] == 6'h2B) ? 1'b1 : 1'b0;
reg [1:0] state;
reg [15:0] packet_size, byte_count;
reg [31:0] line_count;
reg last_line, last_out;
parameter PH_DECODE = 2'b00;
parameter WAIT_EOT = 2'b01;
parameter REC_DATA = 2'b10;
assign last_packet = last_out;
always @(posedge rxbyteclkhs) begin
if(reset) begin
frame_active <= 0;
frame_valid <= 0;
packet_size <= 0;
byte_count <= 0;
out_stream <= 0;
line_count <= 0;
last_line <= 0;
last_out <= 0;
state <= PH_DECODE;
end
else begin
case(state)
PH_DECODE: begin
if(valid_stream && ph_select && ~ecc_error) begin
if(sof_id) begin
frame_active <= 1'b1;
line_count <= 0;
last_line <= 0;
last_out <= 0;
state <= PH_DECODE;
end
else if(eof_id) begin
frame_active <= 1'b0;
line_count <= 0;
last_line <= 0;
last_out <= 0;
state <= PH_DECODE;
end
else if(pxdata_id) begin
if(frame_active) begin
byte_count <= 0;
packet_size <= ph_stream[23:8];
line_count <= line_count + 1;
if((line_count + 1) == lines_per_frame) last_line <= 1'b1;
else last_line <= 1'b0;
state <= REC_DATA;
end
else state <= WAIT_EOT;
end
end
else if(valid_stream && ~ph_select) state <= WAIT_EOT;
else state <= PH_DECODE;
end
WAIT_EOT: begin
if(valid_stream) state <= WAIT_EOT;
else state <= PH_DECODE;
end
REC_DATA: begin
if(byte_count < packet_size) begin
frame_valid <= 1'b1;
out_stream <= data_stream;
byte_count <= byte_count + 2;
state <= REC_DATA;
if(((byte_count + 2) >= packet_size) && last_line) last_out <= 1'b1;
else last_out <= 1'b0;
end
else begin
frame_valid <= 1'b0;
out_stream <= 0;
last_out <= 0;
state <= WAIT_EOT;
end
end
endcase
end
end
endmodule | module pckthandler_fsm(rxbyteclkhs, reset, data_stream, ph_stream, ph_select, valid_stream, ecc_error,
out_stream, frame_active, frame_valid, lines_per_frame, last_packet
); |
parameter DATA_STREAM_WIDTH = 16;
parameter PH_STREAM_WIDTH = 24;
input rxbyteclkhs, reset, ph_select, valid_stream, ecc_error;
input [(DATA_STREAM_WIDTH-1):0] data_stream;
input [(PH_STREAM_WIDTH-1):0] ph_stream;
input [31:0] lines_per_frame;
output frame_active, frame_valid;
output [(DATA_STREAM_WIDTH-1):0] out_stream;
output last_packet;
reg frame_active, frame_valid;
reg [(DATA_STREAM_WIDTH-1):0] out_stream;
wire sof_id, eof_id, pxdata_id;
assign sof_id = (ph_stream[5:0] == 6'h00) ? 1'b1 : 1'b0;
assign eof_id = (ph_stream[5:0] == 6'h01) ? 1'b1 : 1'b0;
assign pxdata_id = (ph_stream[5:0] == 6'h2B) ? 1'b1 : 1'b0;
reg [1:0] state;
reg [15:0] packet_size, byte_count;
reg [31:0] line_count;
reg last_line, last_out;
parameter PH_DECODE = 2'b00;
parameter WAIT_EOT = 2'b01;
parameter REC_DATA = 2'b10;
assign last_packet = last_out;
always @(posedge rxbyteclkhs) begin
if(reset) begin
frame_active <= 0;
frame_valid <= 0;
packet_size <= 0;
byte_count <= 0;
out_stream <= 0;
line_count <= 0;
last_line <= 0;
last_out <= 0;
state <= PH_DECODE;
end
else begin
case(state)
PH_DECODE: begin
if(valid_stream && ph_select && ~ecc_error) begin
if(sof_id) begin
frame_active <= 1'b1;
line_count <= 0;
last_line <= 0;
last_out <= 0;
state <= PH_DECODE;
end
else if(eof_id) begin
frame_active <= 1'b0;
line_count <= 0;
last_line <= 0;
last_out <= 0;
state <= PH_DECODE;
end
else if(pxdata_id) begin
if(frame_active) begin
byte_count <= 0;
packet_size <= ph_stream[23:8];
line_count <= line_count + 1;
if((line_count + 1) == lines_per_frame) last_line <= 1'b1;
else last_line <= 1'b0;
state <= REC_DATA;
end
else state <= WAIT_EOT;
end
end
else if(valid_stream && ~ph_select) state <= WAIT_EOT;
else state <= PH_DECODE;
end
WAIT_EOT: begin
if(valid_stream) state <= WAIT_EOT;
else state <= PH_DECODE;
end
REC_DATA: begin
if(byte_count < packet_size) begin
frame_valid <= 1'b1;
out_stream <= data_stream;
byte_count <= byte_count + 2;
state <= REC_DATA;
if(((byte_count + 2) >= packet_size) && last_line) last_out <= 1'b1;
else last_out <= 1'b0;
end
else begin
frame_valid <= 1'b0;
out_stream <= 0;
last_out <= 0;
state <= WAIT_EOT;
end
end
endcase
end
end
endmodule | 31 |
6,457 | data/full_repos/permissive/116308238/hdl/ph_finder.v | 116,308,238 | ph_finder.v | v | 78 | 100 | [] | [] | [] | [(18, 77)] | null | data/verilator_xmls/f79c6885-8ee8-4df1-8918-6f647c52f0a8.xml | null | 7,367 | module | module ph_finder(rxbyteclkhs, reset, din, din_valid, dout, dout_valid, ph_select);
input wire rxbyteclkhs, reset;
input wire [15:0] din;
input wire din_valid;
output reg [31:0] dout;
output reg dout_valid;
output reg ph_select;
parameter STATE_HALF_PH = 2'b00;
parameter STATE_FULL_PH = 2'b01;
parameter STATE_BYPASS = 2'b10;
reg [7:0] prev_byte1, prev_byte2;
reg [1:0] state;
always @(posedge rxbyteclkhs) begin
if(reset | ~din_valid) begin
dout <= 32'd0;
dout_valid <= 1'b0;
ph_select <= 1'b0;
prev_byte1 <= 8'd0;
prev_byte2 <= 8'd0;
state <= STATE_HALF_PH;
end
else begin
case(state)
STATE_HALF_PH: begin
prev_byte1 <= din[15:8];
prev_byte2 <= din[7:0];
state <= STATE_FULL_PH;
end
STATE_FULL_PH: begin
dout <= {din[7:0], din[15:8], prev_byte2, prev_byte1};
dout_valid <= 1'b1;
ph_select <= 1'b1;
state <= STATE_BYPASS;
end
STATE_BYPASS: begin
dout <= {din, 16'd0};
ph_select <= 1'b0;
state <= STATE_BYPASS;
end
default: begin
dout <= 32'd0;
dout_valid <= 1'b0;
ph_select <= 1'b0;
end
endcase
end
end
endmodule | module ph_finder(rxbyteclkhs, reset, din, din_valid, dout, dout_valid, ph_select); |
input wire rxbyteclkhs, reset;
input wire [15:0] din;
input wire din_valid;
output reg [31:0] dout;
output reg dout_valid;
output reg ph_select;
parameter STATE_HALF_PH = 2'b00;
parameter STATE_FULL_PH = 2'b01;
parameter STATE_BYPASS = 2'b10;
reg [7:0] prev_byte1, prev_byte2;
reg [1:0] state;
always @(posedge rxbyteclkhs) begin
if(reset | ~din_valid) begin
dout <= 32'd0;
dout_valid <= 1'b0;
ph_select <= 1'b0;
prev_byte1 <= 8'd0;
prev_byte2 <= 8'd0;
state <= STATE_HALF_PH;
end
else begin
case(state)
STATE_HALF_PH: begin
prev_byte1 <= din[15:8];
prev_byte2 <= din[7:0];
state <= STATE_FULL_PH;
end
STATE_FULL_PH: begin
dout <= {din[7:0], din[15:8], prev_byte2, prev_byte1};
dout_valid <= 1'b1;
ph_select <= 1'b1;
state <= STATE_BYPASS;
end
STATE_BYPASS: begin
dout <= {din, 16'd0};
ph_select <= 1'b0;
state <= STATE_BYPASS;
end
default: begin
dout <= 32'd0;
dout_valid <= 1'b0;
ph_select <= 1'b0;
end
endcase
end
end
endmodule | 31 |
6,459 | data/full_repos/permissive/116308238/hdl/wordalign.v | 116,308,238 | wordalign.v | v | 110 | 86 | [] | [] | [] | [(12, 108)] | null | data/verilator_xmls/a7b25c3d-7f92-45cd-ae46-18d9a73bcf0a.xml | null | 7,369 | module | module wordalign # (
parameter integer MAX_CHANNEL_DELAY = 2
)
(
input wire clk,
input wire resetn,
input wire dl0_rxvalidhs,
input wire dl1_rxvalidhs,
input wire [7:0] dl0_rxdatahs,
input wire [7:0] dl1_rxdatahs,
output wire [15:0] word_out,
output reg word_valid
);
reg[15:0] word_delay[MAX_CHANNEL_DELAY+1:0];
reg[1:0] sync_delay[MAX_CHANNEL_DELAY+1:0];
reg[1:0] valid_delay[MAX_CHANNEL_DELAY+1:0];
wire locked;
reg[7:0] byte_lane0;
reg[7:0] byte_lane1;
integer i;
always @(posedge clk) begin
if(~resetn) begin
byte_lane0 <= 0;
byte_lane1 <= 0;
for(i = 0; i <= MAX_CHANNEL_DELAY; i = i+1) begin
word_delay[i] <= 0;
sync_delay[i] <= 2'b00;
valid_delay[i] <= 2'b00;
end
word_valid <= 1'b0;
end
else begin
word_delay[0] <= {dl0_rxdatahs, dl1_rxdatahs};
word_delay[1] <= word_delay[0];
word_delay[2] <= word_delay[1];
valid_delay[0] <= {dl0_rxvalidhs, dl1_rxvalidhs};
valid_delay[1] <= valid_delay[0];
valid_delay[2] <= valid_delay[1];
if(~locked) begin
sync_delay[0] <= {dl0_rxvalidhs != valid_delay[0][1],
dl1_rxvalidhs != valid_delay[0][0]};
sync_delay[1] <= sync_delay[0];
sync_delay[2] <= sync_delay[1];
end
word_valid <= locked;
if(sync_delay[0][1])
byte_lane0 <= word_delay[0][15:8];
else if(sync_delay[1][1])
byte_lane0 <= word_delay[1][15:8];
else if(sync_delay[2][1])
byte_lane0 <= word_delay[2][15:8];
else
byte_lane0 <= 0;
if(sync_delay[0][0])
byte_lane1 <= word_delay[0][7:0];
else if(sync_delay[1][0])
byte_lane1 <= word_delay[1][7:0];
else if(sync_delay[2][0])
byte_lane1 <= word_delay[2][7:0];
else
byte_lane1 <= 0;
end
end
assign locked = ((sync_delay[0][0] & valid_delay[0][0]) |
(sync_delay[1][0] & valid_delay[1][0]) |
(sync_delay[2][0] & valid_delay[2][0])) &
((sync_delay[0][1] & valid_delay[0][1]) |
(sync_delay[1][1] & valid_delay[1][1]) |
(sync_delay[2][1] & valid_delay[2][1]));
assign word_out = {byte_lane0, byte_lane1};
endmodule | module wordalign # (
parameter integer MAX_CHANNEL_DELAY = 2
)
(
input wire clk,
input wire resetn,
input wire dl0_rxvalidhs,
input wire dl1_rxvalidhs,
input wire [7:0] dl0_rxdatahs,
input wire [7:0] dl1_rxdatahs,
output wire [15:0] word_out,
output reg word_valid
); |
reg[15:0] word_delay[MAX_CHANNEL_DELAY+1:0];
reg[1:0] sync_delay[MAX_CHANNEL_DELAY+1:0];
reg[1:0] valid_delay[MAX_CHANNEL_DELAY+1:0];
wire locked;
reg[7:0] byte_lane0;
reg[7:0] byte_lane1;
integer i;
always @(posedge clk) begin
if(~resetn) begin
byte_lane0 <= 0;
byte_lane1 <= 0;
for(i = 0; i <= MAX_CHANNEL_DELAY; i = i+1) begin
word_delay[i] <= 0;
sync_delay[i] <= 2'b00;
valid_delay[i] <= 2'b00;
end
word_valid <= 1'b0;
end
else begin
word_delay[0] <= {dl0_rxdatahs, dl1_rxdatahs};
word_delay[1] <= word_delay[0];
word_delay[2] <= word_delay[1];
valid_delay[0] <= {dl0_rxvalidhs, dl1_rxvalidhs};
valid_delay[1] <= valid_delay[0];
valid_delay[2] <= valid_delay[1];
if(~locked) begin
sync_delay[0] <= {dl0_rxvalidhs != valid_delay[0][1],
dl1_rxvalidhs != valid_delay[0][0]};
sync_delay[1] <= sync_delay[0];
sync_delay[2] <= sync_delay[1];
end
word_valid <= locked;
if(sync_delay[0][1])
byte_lane0 <= word_delay[0][15:8];
else if(sync_delay[1][1])
byte_lane0 <= word_delay[1][15:8];
else if(sync_delay[2][1])
byte_lane0 <= word_delay[2][15:8];
else
byte_lane0 <= 0;
if(sync_delay[0][0])
byte_lane1 <= word_delay[0][7:0];
else if(sync_delay[1][0])
byte_lane1 <= word_delay[1][7:0];
else if(sync_delay[2][0])
byte_lane1 <= word_delay[2][7:0];
else
byte_lane1 <= 0;
end
end
assign locked = ((sync_delay[0][0] & valid_delay[0][0]) |
(sync_delay[1][0] & valid_delay[1][0]) |
(sync_delay[2][0] & valid_delay[2][0])) &
((sync_delay[0][1] & valid_delay[0][1]) |
(sync_delay[1][1] & valid_delay[1][1]) |
(sync_delay[2][1] & valid_delay[2][1]));
assign word_out = {byte_lane0, byte_lane1};
endmodule | 31 |
6,462 | data/full_repos/permissive/116308238/unit_tests/pckthandler_fsm_tb.v | 116,308,238 | pckthandler_fsm_tb.v | v | 46 | 105 | [] | [] | [] | null | line:21: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116308238/unit_tests/pckthandler_fsm_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n repeat(4) #10 clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116308238/unit_tests/pckthandler_fsm_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk=~clk;\n ^\n%Error: data/full_repos/permissive/116308238/unit_tests/pckthandler_fsm_tb.v:34: syntax error, unexpected \'@\'\n @(negedge reset);\n ^\n%Error: data/full_repos/permissive/116308238/unit_tests/pckthandler_fsm_tb.v:38: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116308238/unit_tests/pckthandler_fsm_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #1 $display("out=%h, out_exp=%h, fr_active=%h, fr_active_exp=%h, fr_valid=%h, fr_valid_exp=%h",\n ^\n%Error: data/full_repos/permissive/116308238/unit_tests/pckthandler_fsm_tb.v:42: syntax error, unexpected \'@\'\n repeat(20) @(posedge clk);\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,372 | module | module pckthandler_fsm_tb;
reg clk, reset;
reg [15:0] data_stream;
reg [23:0] ph_stream;
reg ph_select, valid_stream, ecc_error;
wire [15:0] out_stream;
wire frame_active, frame_valid;
integer fd, status;
reg [15:0] out_exp;
reg fr_active_exp, fr_valid_exp;
pckthandler_fsm DUT(clk, reset, data_stream, ph_stream, ph_select, valid_stream,
ecc_error, out_stream, frame_active, frame_valid);
initial begin
clk = 0; reset =1;
repeat(4) #10 clk=~clk;
reset = 0;
forever #10 clk=~clk;
end
initial begin
fd = $fopen("pckthandler_fsm_testvec.txt", "r");
end
initial begin
data_stream = 0; ph_stream= 0; ph_select = 0; valid_stream=0; ecc_error=0;
@(negedge reset);
while(!$feof(fd)) begin
status = $fscanf(fd, "%h, %h, %h, %h, %h, %h, %h\n", data_stream, ph_stream, valid_stream, ph_select,
out_exp, fr_active_exp, fr_valid_exp);
@(posedge clk);
#1 $display("out=%h, out_exp=%h, fr_active=%h, fr_active_exp=%h, fr_valid=%h, fr_valid_exp=%h",
out_stream, out_exp, frame_active, fr_active_exp, frame_valid, fr_valid_exp);
end
repeat(20) @(posedge clk);
$fclose(fd);
$finish;
end
endmodule | module pckthandler_fsm_tb; |
reg clk, reset;
reg [15:0] data_stream;
reg [23:0] ph_stream;
reg ph_select, valid_stream, ecc_error;
wire [15:0] out_stream;
wire frame_active, frame_valid;
integer fd, status;
reg [15:0] out_exp;
reg fr_active_exp, fr_valid_exp;
pckthandler_fsm DUT(clk, reset, data_stream, ph_stream, ph_select, valid_stream,
ecc_error, out_stream, frame_active, frame_valid);
initial begin
clk = 0; reset =1;
repeat(4) #10 clk=~clk;
reset = 0;
forever #10 clk=~clk;
end
initial begin
fd = $fopen("pckthandler_fsm_testvec.txt", "r");
end
initial begin
data_stream = 0; ph_stream= 0; ph_select = 0; valid_stream=0; ecc_error=0;
@(negedge reset);
while(!$feof(fd)) begin
status = $fscanf(fd, "%h, %h, %h, %h, %h, %h, %h\n", data_stream, ph_stream, valid_stream, ph_select,
out_exp, fr_active_exp, fr_valid_exp);
@(posedge clk);
#1 $display("out=%h, out_exp=%h, fr_active=%h, fr_active_exp=%h, fr_valid=%h, fr_valid_exp=%h",
out_stream, out_exp, frame_active, fr_active_exp, frame_valid, fr_valid_exp);
end
repeat(20) @(posedge clk);
$fclose(fd);
$finish;
end
endmodule | 31 |
6,465 | data/full_repos/permissive/116308238/unit_tests/ph_finder_tb.v | 116,308,238 | ph_finder_tb.v | v | 45 | 95 | [] | [] | [] | null | line:21: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116308238/unit_tests/ph_finder_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n repeat(4) #10 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116308238/unit_tests/ph_finder_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/116308238/unit_tests/ph_finder_tb.v:34: syntax error, unexpected \'@\'\n @(negedge reset);\n ^\n%Error: data/full_repos/permissive/116308238/unit_tests/ph_finder_tb.v:37: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116308238/unit_tests/ph_finder_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #1 $display("input=%h, output=%h, output_exp=%h, v=%b, v_exp=%b, ph_sel=%b, ph_sel_exp=%b",\n ^\n%Error: data/full_repos/permissive/116308238/unit_tests/ph_finder_tb.v:41: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,375 | module | module ph_finder_tb;
reg clk, reset, din_valid;
reg [15:0] din;
wire [31:0] dout;
wire dout_valid, ph_select;
integer fd, status;
reg [31:0] d_exp;
reg v_exp, ph_exp;
ph_finder DUT(clk, reset, din, din_valid, dout, dout_valid, ph_select);
initial begin
clk = 0; reset = 1;
repeat(4) #10 clk = ~clk;
reset = 0;
forever #10 clk = ~clk;
end
initial begin
fd = $fopen("ph_finder_testvec.txt", "r");
end
initial begin
din = 0; din_valid = 1;
@(negedge reset);
while(!$feof(fd)) begin
status = $fscanf(fd, "%h, %h, %h, %h, %h\n", din, din_valid, d_exp, v_exp, ph_exp);
@(posedge clk);
#1 $display("input=%h, output=%h, output_exp=%h, v=%b, v_exp=%b, ph_sel=%b, ph_sel_exp=%b",
din, dout, d_exp, dout_valid, v_exp, ph_select, ph_exp);
end
@(posedge clk);
$fclose(fd);
$finish;
end
endmodule | module ph_finder_tb; |
reg clk, reset, din_valid;
reg [15:0] din;
wire [31:0] dout;
wire dout_valid, ph_select;
integer fd, status;
reg [31:0] d_exp;
reg v_exp, ph_exp;
ph_finder DUT(clk, reset, din, din_valid, dout, dout_valid, ph_select);
initial begin
clk = 0; reset = 1;
repeat(4) #10 clk = ~clk;
reset = 0;
forever #10 clk = ~clk;
end
initial begin
fd = $fopen("ph_finder_testvec.txt", "r");
end
initial begin
din = 0; din_valid = 1;
@(negedge reset);
while(!$feof(fd)) begin
status = $fscanf(fd, "%h, %h, %h, %h, %h\n", din, din_valid, d_exp, v_exp, ph_exp);
@(posedge clk);
#1 $display("input=%h, output=%h, output_exp=%h, v=%b, v_exp=%b, ph_sel=%b, ph_sel_exp=%b",
din, dout, d_exp, dout_valid, v_exp, ph_select, ph_exp);
end
@(posedge clk);
$fclose(fd);
$finish;
end
endmodule | 31 |
6,467 | data/full_repos/permissive/116468596/count14D.v | 116,468,596 | count14D.v | v | 85 | 189 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/116468596/count14D.v:33: Operator ADD expects 14 bits on the LHS, but LHS\'s CONST \'10\'h10\' generates 10 bits.\n : ... In instance count14D\n assign inD = ( 10\'d16 + sw[15:7]*10\'d32 );\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/116468596/count14D.v:64: Cannot find file containing module: \'FDRE\'\n FDRE #(.INIT(1\'b0) ) bit1 (.C(clk), .R(1\'b0), .CE((enable | LD)), .D(temp[0]), .Q(outQ[0]));\n ^~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n FDRE\n FDRE.v\n FDRE.sv\n obj_dir/FDRE\n obj_dir/FDRE.v\n obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/count14D.v:65: Cannot find file containing module: \'FDRE\'\n FDRE #(.INIT(1\'b0) ) bit2 (.C(clk), .R(1\'b0), .CE((enable | LD)), .D(temp[1]), .Q(outQ[1]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count14D.v:66: Cannot find file containing module: \'FDRE\'\n FDRE #(.INIT(1\'b0) ) bit3 (.C(clk), .R(1\'b0), .CE((enable | LD)), .D(temp[2]), .Q(outQ[2]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count14D.v:67: Cannot find file containing module: \'FDRE\'\n FDRE #(.INIT(1\'b0) ) bit4 (.C(clk), .R(1\'b0), .CE((enable | LD)), .D(temp[3]), .Q(outQ[3]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count14D.v:68: Cannot find file containing module: \'FDRE\'\n FDRE #(.INIT(1\'b0) ) bit5 (.C(clk), .R(1\'b0), .CE((enable | LD)), .D(temp[4]), .Q(outQ[4]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count14D.v:69: Cannot find file containing module: \'FDRE\'\n FDRE #(.INIT(1\'b0) ) bit6 (.C(clk), .R(1\'b0), .CE((enable | LD)), .D(temp[6]), .Q(outQ[6]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count14D.v:70: Cannot find file containing module: \'FDRE\'\n FDRE #(.INIT(1\'b0) ) bit8 (.C(clk), .R(1\'b0), .CE((enable | LD)), .D(temp[7]), .Q(outQ[7]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count14D.v:71: Cannot find file containing module: \'FDRE\'\n FDRE #(.INIT(1\'b0) ) bit9 (.C(clk), .R(1\'b0), .CE((enable | LD)), .D(temp[8]), .Q(outQ[8]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count14D.v:72: Cannot find file containing module: \'FDRE\'\n FDRE #(.INIT(1\'b0) ) bit10 (.C(clk), .R(1\'b0), .CE((enable | LD)), .D(temp[9]), .Q(outQ[9]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count14D.v:73: Cannot find file containing module: \'FDRE\'\n FDRE #(.INIT(1\'b0) ) bit11 (.C(clk), .R(1\'b0), .CE((enable | LD)), .D(temp[10]), .Q(outQ[10]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count14D.v:74: Cannot find file containing module: \'FDRE\'\n FDRE #(.INIT(1\'b0) ) bit12 (.C(clk), .R(1\'b0), .CE((enable | LD)), .D(temp[11]), .Q(outQ[11]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count14D.v:75: Cannot find file containing module: \'FDRE\'\n FDRE #(.INIT(1\'b0) ) bit13 (.C(clk), .R(1\'b0), .CE((enable | LD)), .D(temp[12]), .Q(outQ[12]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count14D.v:76: Cannot find file containing module: \'FDRE\'\n FDRE #(.INIT(1\'b0) ) bit14 (.C(clk), .R(1\'b0), .CE((enable | LD)), .D(temp[13]), .Q(outQ[13]));\n ^~~~\n%Error: Exiting due to 13 error(s), 1 warning(s)\n' | 7,377 | module | module count14D(
input clk, enable, LD, reset,
input [15:0] sw,
output [13:0] outQ,
output TC
);
wire internalReset;
wire [13:0] inD;
wire [13:0] invD;
wire [13:0] temp;
assign inD = ( 10'd16 + sw[15:7]*10'd32 );
assign invD[0] = enable ^ outQ[0];
assign invD[1] = (enable & ~outQ[0]) ^ outQ[1];
assign invD[2] = (enable & ~outQ[0] & ~outQ[1]) ^ outQ[2];
assign invD[3] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2]) ^ outQ[3];
assign invD[4] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3]) ^ outQ[4];
assign invD[5] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4]) ^ outQ[5];
assign invD[6] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5]) ^ outQ[6];
assign invD[7] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6]) ^ outQ[7];
assign invD[8] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7]) ^ outQ[8];
assign invD[9] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7] & ~outQ[8]) ^ outQ[9];
assign invD[10] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7] & ~outQ[8] & ~outQ[9]) ^ outQ[10];
assign invD[11] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7] & ~outQ[8] & ~outQ[9] & ~outQ[10]) ^ outQ[11];
assign invD[12] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7] & ~outQ[8] & ~outQ[9] & ~outQ[10] & ~outQ[11]) ^ outQ[12];
assign invD[13] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7] & ~outQ[8] & ~outQ[9] & ~outQ[10] & ~outQ[11] & ~outQ[12]) ^ outQ[13];
assign temp[0] = ( (~LD & invD[0]) | (LD & inD[0]) );
assign temp[1] = ( (~LD & invD[1]) | (LD & inD[1]) );
assign temp[2] = ( (~LD & invD[2]) | (LD & inD[2]) );
assign temp[3] = ( (~LD & invD[3]) | (LD & inD[3]) );
assign temp[4] = ( (~LD & invD[4]) | (LD & inD[4]) );
assign temp[5] = ( (~LD & invD[5]) | (LD & inD[5]) );
assign temp[6] = ( (~LD & invD[6]) | (LD & inD[6]) );
assign temp[7] = ( (~LD & invD[7]) | (LD & inD[7]) );
assign temp[8] = ( (~LD & invD[8]) | (LD & inD[8]) );
assign temp[9] = ( (~LD & invD[9]) | (LD & inD[9]) );
assign temp[10] = ( (~LD & invD[10]) | (LD & inD[10]) );
assign temp[11] = ( (~LD & invD[11]) | (LD & inD[11]) );
assign temp[12] = ( (~LD & invD[12]) | (LD & inD[12]) );
assign temp[13] = ( (~LD & invD[13]) | (LD & inD[13]) );
FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[0]), .Q(outQ[0]));
FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[1]), .Q(outQ[1]));
FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[2]), .Q(outQ[2]));
FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[3]), .Q(outQ[3]));
FDRE #(.INIT(1'b0) ) bit5 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[4]), .Q(outQ[4]));
FDRE #(.INIT(1'b0) ) bit6 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[6]), .Q(outQ[6]));
FDRE #(.INIT(1'b0) ) bit8 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[7]), .Q(outQ[7]));
FDRE #(.INIT(1'b0) ) bit9 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[8]), .Q(outQ[8]));
FDRE #(.INIT(1'b0) ) bit10 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[9]), .Q(outQ[9]));
FDRE #(.INIT(1'b0) ) bit11 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[10]), .Q(outQ[10]));
FDRE #(.INIT(1'b0) ) bit12 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[11]), .Q(outQ[11]));
FDRE #(.INIT(1'b0) ) bit13 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[12]), .Q(outQ[12]));
FDRE #(.INIT(1'b0) ) bit14 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[13]), .Q(outQ[13]));
assign TC = (~outQ[6] & ~outQ[7] & ~outQ[8] & ~outQ[9] & ~outQ[10] & ~outQ[11] & ~outQ[12] & ~outQ[13]);
endmodule | module count14D(
input clk, enable, LD, reset,
input [15:0] sw,
output [13:0] outQ,
output TC
); |
wire internalReset;
wire [13:0] inD;
wire [13:0] invD;
wire [13:0] temp;
assign inD = ( 10'd16 + sw[15:7]*10'd32 );
assign invD[0] = enable ^ outQ[0];
assign invD[1] = (enable & ~outQ[0]) ^ outQ[1];
assign invD[2] = (enable & ~outQ[0] & ~outQ[1]) ^ outQ[2];
assign invD[3] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2]) ^ outQ[3];
assign invD[4] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3]) ^ outQ[4];
assign invD[5] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4]) ^ outQ[5];
assign invD[6] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5]) ^ outQ[6];
assign invD[7] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6]) ^ outQ[7];
assign invD[8] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7]) ^ outQ[8];
assign invD[9] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7] & ~outQ[8]) ^ outQ[9];
assign invD[10] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7] & ~outQ[8] & ~outQ[9]) ^ outQ[10];
assign invD[11] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7] & ~outQ[8] & ~outQ[9] & ~outQ[10]) ^ outQ[11];
assign invD[12] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7] & ~outQ[8] & ~outQ[9] & ~outQ[10] & ~outQ[11]) ^ outQ[12];
assign invD[13] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7] & ~outQ[8] & ~outQ[9] & ~outQ[10] & ~outQ[11] & ~outQ[12]) ^ outQ[13];
assign temp[0] = ( (~LD & invD[0]) | (LD & inD[0]) );
assign temp[1] = ( (~LD & invD[1]) | (LD & inD[1]) );
assign temp[2] = ( (~LD & invD[2]) | (LD & inD[2]) );
assign temp[3] = ( (~LD & invD[3]) | (LD & inD[3]) );
assign temp[4] = ( (~LD & invD[4]) | (LD & inD[4]) );
assign temp[5] = ( (~LD & invD[5]) | (LD & inD[5]) );
assign temp[6] = ( (~LD & invD[6]) | (LD & inD[6]) );
assign temp[7] = ( (~LD & invD[7]) | (LD & inD[7]) );
assign temp[8] = ( (~LD & invD[8]) | (LD & inD[8]) );
assign temp[9] = ( (~LD & invD[9]) | (LD & inD[9]) );
assign temp[10] = ( (~LD & invD[10]) | (LD & inD[10]) );
assign temp[11] = ( (~LD & invD[11]) | (LD & inD[11]) );
assign temp[12] = ( (~LD & invD[12]) | (LD & inD[12]) );
assign temp[13] = ( (~LD & invD[13]) | (LD & inD[13]) );
FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[0]), .Q(outQ[0]));
FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[1]), .Q(outQ[1]));
FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[2]), .Q(outQ[2]));
FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[3]), .Q(outQ[3]));
FDRE #(.INIT(1'b0) ) bit5 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[4]), .Q(outQ[4]));
FDRE #(.INIT(1'b0) ) bit6 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[6]), .Q(outQ[6]));
FDRE #(.INIT(1'b0) ) bit8 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[7]), .Q(outQ[7]));
FDRE #(.INIT(1'b0) ) bit9 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[8]), .Q(outQ[8]));
FDRE #(.INIT(1'b0) ) bit10 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[9]), .Q(outQ[9]));
FDRE #(.INIT(1'b0) ) bit11 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[10]), .Q(outQ[10]));
FDRE #(.INIT(1'b0) ) bit12 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[11]), .Q(outQ[11]));
FDRE #(.INIT(1'b0) ) bit13 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[12]), .Q(outQ[12]));
FDRE #(.INIT(1'b0) ) bit14 (.C(clk), .R(1'b0), .CE((enable | LD)), .D(temp[13]), .Q(outQ[13]));
assign TC = (~outQ[6] & ~outQ[7] & ~outQ[8] & ~outQ[9] & ~outQ[10] & ~outQ[11] & ~outQ[12] & ~outQ[13]);
endmodule | 0 |
6,468 | data/full_repos/permissive/116468596/count4.v | 116,468,596 | count4.v | v | 41 | 91 | [] | [] | [] | [(23, 41)] | null | null | 1: b"%Error: data/full_repos/permissive/116468596/count4.v:33: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(eightSec), .CE(enable), .D(inD0), .Q(outQ[0]));\n ^~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n FDRE\n FDRE.v\n FDRE.sv\n obj_dir/FDRE\n obj_dir/FDRE.v\n obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/count4.v:34: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(eightSec), .CE(enable), .D(inD1), .Q(outQ[1]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count4.v:35: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(eightSec), .CE(enable), .D(inD2), .Q(outQ[2]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count4.v:36: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(eightSec), .CE(enable), .D(inD3), .Q(outQ[3]));\n ^~~~\n%Error: Exiting due to 4 error(s)\n" | 7,378 | module | module count4(
input clk, enable,
output eightSec
);
wire [3:0] outQ;
wire inD0 = enable ^ outQ[0];
wire inD1 = (enable & outQ[0]) ^ outQ[1];
wire inD2 = (enable & outQ[0] & outQ[1]) ^ outQ[2];
wire inD3 = (enable & outQ[0] & outQ[1] & outQ[2]) ^ outQ[3];
FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(eightSec), .CE(enable), .D(inD0), .Q(outQ[0]));
FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(eightSec), .CE(enable), .D(inD1), .Q(outQ[1]));
FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(eightSec), .CE(enable), .D(inD2), .Q(outQ[2]));
FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(eightSec), .CE(enable), .D(inD3), .Q(outQ[3]));
assign eightSec = ( ~outQ[0] & ~outQ[1] & ~outQ[2] & outQ[3] );
endmodule | module count4(
input clk, enable,
output eightSec
); |
wire [3:0] outQ;
wire inD0 = enable ^ outQ[0];
wire inD1 = (enable & outQ[0]) ^ outQ[1];
wire inD2 = (enable & outQ[0] & outQ[1]) ^ outQ[2];
wire inD3 = (enable & outQ[0] & outQ[1] & outQ[2]) ^ outQ[3];
FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(eightSec), .CE(enable), .D(inD0), .Q(outQ[0]));
FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(eightSec), .CE(enable), .D(inD1), .Q(outQ[1]));
FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(eightSec), .CE(enable), .D(inD2), .Q(outQ[2]));
FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(eightSec), .CE(enable), .D(inD3), .Q(outQ[3]));
assign eightSec = ( ~outQ[0] & ~outQ[1] & ~outQ[2] & outQ[3] );
endmodule | 0 |
6,469 | data/full_repos/permissive/116468596/count8.v | 116,468,596 | count8.v | v | 48 | 113 | [] | [] | [] | [(23, 48)] | null | null | 1: b"%Error: data/full_repos/permissive/116468596/count8.v:37: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD0), .Q(outQ[0]));\n ^~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n FDRE\n FDRE.v\n FDRE.sv\n obj_dir/FDRE\n obj_dir/FDRE.v\n obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/count8.v:38: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD1), .Q(outQ[1]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count8.v:39: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD2), .Q(outQ[2]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count8.v:40: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD3), .Q(outQ[3]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count8.v:41: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) bit5 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD4), .Q(outQ[4]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count8.v:42: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) bit6 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD5), .Q(outQ[5]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count8.v:43: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) bit7 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD6), .Q(outQ[6]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/count8.v:44: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) bit8 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD7), .Q(outQ[7]));\n ^~~~\n%Error: Exiting due to 8 error(s)\n" | 7,379 | module | module count8(
input clk, enable, reset,
output twoSec
);
wire [7:0] outQ;
wire inD0 = enable ^ outQ[0];
wire inD1 = (enable & outQ[0]) ^ outQ[1];
wire inD2 = (enable & outQ[0] & outQ[1]) ^ outQ[2];
wire inD3 = (enable & outQ[0] & outQ[1] & outQ[2]) ^ outQ[3];
wire inD4 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3]) ^ outQ[4];
wire inD5 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4]) ^ outQ[5];
wire inD6 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5]) ^ outQ[6];
wire inD7 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5] & outQ[6]) ^ outQ[7];
FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD0), .Q(outQ[0]));
FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD1), .Q(outQ[1]));
FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD2), .Q(outQ[2]));
FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD3), .Q(outQ[3]));
FDRE #(.INIT(1'b0) ) bit5 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD4), .Q(outQ[4]));
FDRE #(.INIT(1'b0) ) bit6 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD5), .Q(outQ[5]));
FDRE #(.INIT(1'b0) ) bit7 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD6), .Q(outQ[6]));
FDRE #(.INIT(1'b0) ) bit8 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD7), .Q(outQ[7]));
assign twoSec = ( ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & outQ[7] );
endmodule | module count8(
input clk, enable, reset,
output twoSec
); |
wire [7:0] outQ;
wire inD0 = enable ^ outQ[0];
wire inD1 = (enable & outQ[0]) ^ outQ[1];
wire inD2 = (enable & outQ[0] & outQ[1]) ^ outQ[2];
wire inD3 = (enable & outQ[0] & outQ[1] & outQ[2]) ^ outQ[3];
wire inD4 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3]) ^ outQ[4];
wire inD5 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4]) ^ outQ[5];
wire inD6 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5]) ^ outQ[6];
wire inD7 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5] & outQ[6]) ^ outQ[7];
FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD0), .Q(outQ[0]));
FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD1), .Q(outQ[1]));
FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD2), .Q(outQ[2]));
FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD3), .Q(outQ[3]));
FDRE #(.INIT(1'b0) ) bit5 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD4), .Q(outQ[4]));
FDRE #(.INIT(1'b0) ) bit6 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD5), .Q(outQ[5]));
FDRE #(.INIT(1'b0) ) bit7 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD6), .Q(outQ[6]));
FDRE #(.INIT(1'b0) ) bit8 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD7), .Q(outQ[7]));
assign twoSec = ( ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & outQ[7] );
endmodule | 0 |
6,470 | data/full_repos/permissive/116468596/count8D.v | 116,468,596 | count8D.v | v | 61 | 118 | [] | [] | [] | [(23, 61)] | null | null | 1: b"%Error: data/full_repos/permissive/116468596/count8D.v:50: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[0]), .Q(outQ[0]));\n^~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n FDRE\n FDRE.v\n FDRE.sv\n obj_dir/FDRE\n obj_dir/FDRE.v\n obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/count8D.v:51: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[1]), .Q(outQ[1]));\n^~~~\n%Error: data/full_repos/permissive/116468596/count8D.v:52: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[2]), .Q(outQ[2]));\n^~~~\n%Error: data/full_repos/permissive/116468596/count8D.v:53: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[3]), .Q(outQ[3]));\n^~~~\n%Error: data/full_repos/permissive/116468596/count8D.v:54: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) bit5 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[4]), .Q(outQ[4]));\n^~~~\n%Error: data/full_repos/permissive/116468596/count8D.v:55: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) bit6 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[5]), .Q(outQ[5]));\n^~~~\n%Error: data/full_repos/permissive/116468596/count8D.v:56: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) bit7 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[6]), .Q(outQ[6]));\n^~~~\n%Error: data/full_repos/permissive/116468596/count8D.v:57: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) bit8 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[7]), .Q(outQ[7]));\n^~~~\n%Error: Exiting due to 8 error(s)\n" | 7,380 | module | module count8D(
input clk, enable, LD, reset,
input [7:0] inD,
output TC
);
wire [7:0] invD;
wire [7:0] outQ;
wire [7:0] temp;
assign invD[0] = enable ^ outQ[0];
assign invD[1] = (enable & ~outQ[0]) ^ outQ[1];
assign invD[2] = (enable & ~outQ[0] & ~outQ[1]) ^ outQ[2];
assign invD[3] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2]) ^ outQ[3];
assign invD[4] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3]) ^ outQ[4];
assign invD[5] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4]) ^ outQ[5];
assign invD[6] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5]) ^ outQ[6];
assign invD[7] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6]) ^ outQ[7];
assign temp[0] = ( (~LD & invD[0]) | (LD & inD[0]) );
assign temp[1] = ( (~LD & invD[1]) | (LD & inD[1]) );
assign temp[2] = ( (~LD & invD[2]) | (LD & inD[2]) );
assign temp[3] = ( (~LD & invD[3]) | (LD & inD[3]) );
assign temp[4] = ( (~LD & invD[4]) | (LD & inD[4]) );
assign temp[5] = ( (~LD & invD[5]) | (LD & inD[5]) );
assign temp[6] = ( (~LD & invD[6]) | (LD & inD[6]) );
assign temp[7] = ( (~LD & invD[7]) | (LD & inD[7]) );
FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[0]), .Q(outQ[0]));
FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[1]), .Q(outQ[1]));
FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[2]), .Q(outQ[2]));
FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[3]), .Q(outQ[3]));
FDRE #(.INIT(1'b0) ) bit5 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[4]), .Q(outQ[4]));
FDRE #(.INIT(1'b0) ) bit6 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[5]), .Q(outQ[5]));
FDRE #(.INIT(1'b0) ) bit7 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[6]), .Q(outQ[6]));
FDRE #(.INIT(1'b0) ) bit8 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[7]), .Q(outQ[7]));
assign TC = ( ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7]);
endmodule | module count8D(
input clk, enable, LD, reset,
input [7:0] inD,
output TC
); |
wire [7:0] invD;
wire [7:0] outQ;
wire [7:0] temp;
assign invD[0] = enable ^ outQ[0];
assign invD[1] = (enable & ~outQ[0]) ^ outQ[1];
assign invD[2] = (enable & ~outQ[0] & ~outQ[1]) ^ outQ[2];
assign invD[3] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2]) ^ outQ[3];
assign invD[4] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3]) ^ outQ[4];
assign invD[5] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4]) ^ outQ[5];
assign invD[6] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5]) ^ outQ[6];
assign invD[7] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6]) ^ outQ[7];
assign temp[0] = ( (~LD & invD[0]) | (LD & inD[0]) );
assign temp[1] = ( (~LD & invD[1]) | (LD & inD[1]) );
assign temp[2] = ( (~LD & invD[2]) | (LD & inD[2]) );
assign temp[3] = ( (~LD & invD[3]) | (LD & inD[3]) );
assign temp[4] = ( (~LD & invD[4]) | (LD & inD[4]) );
assign temp[5] = ( (~LD & invD[5]) | (LD & inD[5]) );
assign temp[6] = ( (~LD & invD[6]) | (LD & inD[6]) );
assign temp[7] = ( (~LD & invD[7]) | (LD & inD[7]) );
FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[0]), .Q(outQ[0]));
FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[1]), .Q(outQ[1]));
FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[2]), .Q(outQ[2]));
FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[3]), .Q(outQ[3]));
FDRE #(.INIT(1'b0) ) bit5 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[4]), .Q(outQ[4]));
FDRE #(.INIT(1'b0) ) bit6 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[5]), .Q(outQ[5]));
FDRE #(.INIT(1'b0) ) bit7 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[6]), .Q(outQ[6]));
FDRE #(.INIT(1'b0) ) bit8 (.C(clk), .R(reset), .CE(enable & (~TC | LD)), .D(temp[7]), .Q(outQ[7]));
assign TC = ( ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7]);
endmodule | 0 |
6,471 | data/full_repos/permissive/116468596/edgeDetector.v | 116,468,596 | edgeDetector.v | v | 33 | 102 | [] | [] | [] | [(23, 32)] | null | null | 1: b"%Error: data/full_repos/permissive/116468596/edgeDetector.v:28: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) ff_instance_1 (.C(clk), .R(reset), .CE(1'b1), .D(btnC), .Q(outQ[0]));\n ^~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n FDRE\n FDRE.v\n FDRE.sv\n obj_dir/FDRE\n obj_dir/FDRE.v\n obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/edgeDetector.v:29: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(reset), .CE(1'b1), .D(outQ[0]), .Q(outQ[1]));\n ^~~~\n%Error: Exiting due to 2 error(s)\n" | 7,381 | module | module edgeDetector(
input clk, btnC,
output edgeOut
);
wire [1:0] outQ;
FDRE #(.INIT(1'b0) ) ff_instance_1 (.C(clk), .R(reset), .CE(1'b1), .D(btnC), .Q(outQ[0]));
FDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(reset), .CE(1'b1), .D(outQ[0]), .Q(outQ[1]));
assign edgeOut = btnC & (~outQ[0] & ~outQ[1]);
endmodule | module edgeDetector(
input clk, btnC,
output edgeOut
); |
wire [1:0] outQ;
FDRE #(.INIT(1'b0) ) ff_instance_1 (.C(clk), .R(reset), .CE(1'b1), .D(btnC), .Q(outQ[0]));
FDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(reset), .CE(1'b1), .D(outQ[0]), .Q(outQ[1]));
assign edgeOut = btnC & (~outQ[0] & ~outQ[1]);
endmodule | 0 |
6,472 | data/full_repos/permissive/116468596/hex7seg.v | 116,468,596 | hex7seg.v | v | 40 | 121 | [] | [] | [] | [(23, 39)] | null | null | 1: b"%Error: data/full_repos/permissive/116468596/hex7seg.v:31: Cannot find file containing module: 'm8_le'\n m8_le ca (.in({ 1'b0, n[0], n[0], 1'b0, 1'b0, notN, 1'b0, n[0]}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[0]));\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/m8_le\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/m8_le.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/m8_le.sv\n m8_le\n m8_le.v\n m8_le.sv\n obj_dir/m8_le\n obj_dir/m8_le.v\n obj_dir/m8_le.sv\n%Error: data/full_repos/permissive/116468596/hex7seg.v:32: Cannot find file containing module: 'm8_le'\n m8_le cb (.in({ 1'b1, notN, n[0], 1'b0, notN, n[0], 1'b0, 1'b0}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[1]));\n ^~~~~\n%Error: data/full_repos/permissive/116468596/hex7seg.v:33: Cannot find file containing module: 'm8_le'\n m8_le cc (.in({ 1'b1, notN, 1'b0, 1'b0, 1'b0, 1'b0, notN, 1'b0}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[2]));\n ^~~~~\n%Error: data/full_repos/permissive/116468596/hex7seg.v:34: Cannot find file containing module: 'm8_le'\n m8_le cd (.in({ n[0], 1'b0, notN, 1'b0, n[0], notN, 1'b0, n[0]}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[3]));\n ^~~~~\n%Error: data/full_repos/permissive/116468596/hex7seg.v:35: Cannot find file containing module: 'm8_le'\n m8_le ce (.in({ 1'b0, 1'b0, 1'b0, n[0], n[0], 1'b1, n[0], n[0]}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[4]));\n ^~~~~\n%Error: data/full_repos/permissive/116468596/hex7seg.v:36: Cannot find file containing module: 'm8_le'\n m8_le cf (.in({ 1'b0, n[0], 1'b0, 1'b0, n[0], 1'b0, 1'b1, n[0]}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[5]));\n ^~~~~\n%Error: data/full_repos/permissive/116468596/hex7seg.v:37: Cannot find file containing module: 'm8_le'\n m8_le cg (.in({ 1'b0, notN, 1'b0, 1'b0, n[0], 1'b0, 1'b0, 1'b1}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[6]));\n ^~~~~\n%Error: Exiting due to 7 error(s)\n" | 7,382 | module | module hex7seg(
input [3:0] n,
input enable,
output [6:0] seg
);
wire notN = ~n[0];
m8_le ca (.in({ 1'b0, n[0], n[0], 1'b0, 1'b0, notN, 1'b0, n[0]}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[0]));
m8_le cb (.in({ 1'b1, notN, n[0], 1'b0, notN, n[0], 1'b0, 1'b0}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[1]));
m8_le cc (.in({ 1'b1, notN, 1'b0, 1'b0, 1'b0, 1'b0, notN, 1'b0}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[2]));
m8_le cd (.in({ n[0], 1'b0, notN, 1'b0, n[0], notN, 1'b0, n[0]}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[3]));
m8_le ce (.in({ 1'b0, 1'b0, 1'b0, n[0], n[0], 1'b1, n[0], n[0]}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[4]));
m8_le cf (.in({ 1'b0, n[0], 1'b0, 1'b0, n[0], 1'b0, 1'b1, n[0]}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[5]));
m8_le cg (.in({ 1'b0, notN, 1'b0, 1'b0, n[0], 1'b0, 1'b0, 1'b1}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[6]));
endmodule | module hex7seg(
input [3:0] n,
input enable,
output [6:0] seg
); |
wire notN = ~n[0];
m8_le ca (.in({ 1'b0, n[0], n[0], 1'b0, 1'b0, notN, 1'b0, n[0]}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[0]));
m8_le cb (.in({ 1'b1, notN, n[0], 1'b0, notN, n[0], 1'b0, 1'b0}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[1]));
m8_le cc (.in({ 1'b1, notN, 1'b0, 1'b0, 1'b0, 1'b0, notN, 1'b0}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[2]));
m8_le cd (.in({ n[0], 1'b0, notN, 1'b0, n[0], notN, 1'b0, n[0]}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[3]));
m8_le ce (.in({ 1'b0, 1'b0, 1'b0, n[0], n[0], 1'b1, n[0], n[0]}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[4]));
m8_le cf (.in({ 1'b0, n[0], 1'b0, 1'b0, n[0], 1'b0, 1'b1, n[0]}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[5]));
m8_le cg (.in({ 1'b0, notN, 1'b0, 1'b0, n[0], 1'b0, 1'b0, 1'b1}), .sel({n[3], n[2], n[1]}), .e(enable), .o(seg[6]));
endmodule | 0 |
6,473 | data/full_repos/permissive/116468596/lfsr.v | 116,468,596 | lfsr.v | v | 41 | 100 | [] | [] | [] | [(23, 40)] | null | null | 1: b"%Error: data/full_repos/permissive/116468596/lfsr.v:29: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) ff_instance_1 (.C(clk), .R(1'b0), .CE(frame), .D(rndIn1), .Q(rnd[0]));\n ^~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n FDRE\n FDRE.v\n FDRE.sv\n obj_dir/FDRE\n obj_dir/FDRE.v\n obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/lfsr.v:30: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[0]), .Q(rnd[1]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/lfsr.v:31: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) ff_instance_3 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[1]), .Q(rnd[2]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/lfsr.v:32: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) ff_instance_4 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[2]), .Q(rnd[3]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/lfsr.v:33: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) ff_instance_5 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[3]), .Q(rnd[4]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/lfsr.v:34: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) ff_instance_6 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[4]), .Q(rnd[5]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/lfsr.v:35: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) ff_instance_7 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[5]), .Q(rnd[6]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/lfsr.v:36: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b1) ) ff_instance_8 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[6]), .Q(rnd[7]));\n ^~~~\n%Error: Exiting due to 8 error(s)\n" | 7,383 | module | module lfsr(
input clk, frame,
output [7:0] rnd
);
wire TC;
wire rndIn1 = rnd[0] ^ rnd[5] ^ rnd[6] ^ rnd[7];
FDRE #(.INIT(1'b0) ) ff_instance_1 (.C(clk), .R(1'b0), .CE(frame), .D(rndIn1), .Q(rnd[0]));
FDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[0]), .Q(rnd[1]));
FDRE #(.INIT(1'b0) ) ff_instance_3 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[1]), .Q(rnd[2]));
FDRE #(.INIT(1'b0) ) ff_instance_4 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[2]), .Q(rnd[3]));
FDRE #(.INIT(1'b0) ) ff_instance_5 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[3]), .Q(rnd[4]));
FDRE #(.INIT(1'b0) ) ff_instance_6 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[4]), .Q(rnd[5]));
FDRE #(.INIT(1'b0) ) ff_instance_7 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[5]), .Q(rnd[6]));
FDRE #(.INIT(1'b1) ) ff_instance_8 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[6]), .Q(rnd[7]));
assign TC = rnd[0] & rnd[1] & rnd[2] & rnd[3] & rnd[4] & rnd[5] & rnd[6] & rnd[7];
endmodule | module lfsr(
input clk, frame,
output [7:0] rnd
); |
wire TC;
wire rndIn1 = rnd[0] ^ rnd[5] ^ rnd[6] ^ rnd[7];
FDRE #(.INIT(1'b0) ) ff_instance_1 (.C(clk), .R(1'b0), .CE(frame), .D(rndIn1), .Q(rnd[0]));
FDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[0]), .Q(rnd[1]));
FDRE #(.INIT(1'b0) ) ff_instance_3 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[1]), .Q(rnd[2]));
FDRE #(.INIT(1'b0) ) ff_instance_4 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[2]), .Q(rnd[3]));
FDRE #(.INIT(1'b0) ) ff_instance_5 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[3]), .Q(rnd[4]));
FDRE #(.INIT(1'b0) ) ff_instance_6 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[4]), .Q(rnd[5]));
FDRE #(.INIT(1'b0) ) ff_instance_7 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[5]), .Q(rnd[6]));
FDRE #(.INIT(1'b1) ) ff_instance_8 (.C(clk), .R(1'b0), .CE(frame), .D(rnd[6]), .Q(rnd[7]));
assign TC = rnd[0] & rnd[1] & rnd[2] & rnd[3] & rnd[4] & rnd[5] & rnd[6] & rnd[7];
endmodule | 0 |
6,474 | data/full_repos/permissive/116468596/m8_le.v | 116,468,596 | m8_le.v | v | 42 | 83 | [] | [] | [] | [(23, 42)] | null | data/verilator_xmls/f8faa2ca-38a0-4595-94d3-f87d88903f90.xml | null | 7,384 | module | module m8_le(
input [7:0] in,
input [2:0] sel,
input e,
output o
);
wire [7:0] c;
assign c[0] = (~sel[2] & ~sel[1] & ~sel[0] * in[0]);
assign c[1] = (~sel[2] & ~sel[1] & sel[0] * in[1]);
assign c[2] = (~sel[2] & sel[1] & ~sel[0] * in[2]);
assign c[3] = (~sel[2] & sel[1] & sel[0] * in[3]);
assign c[4] = (sel[2] & ~sel[1] & ~sel[0] * in[4]);
assign c[5] = (sel[2] & ~sel[1] & sel[0] * in[5]);
assign c[6] = (sel[2] & sel[1] & ~sel[0] * in[6]);
assign c[7] = (sel[2] & sel[1] & sel[0] * in[7]);
assign o = e & (c[0] | c[1] | c[2] | c[3] | c[4] | c[5] | c[6] | c[7]);
endmodule | module m8_le(
input [7:0] in,
input [2:0] sel,
input e,
output o
); |
wire [7:0] c;
assign c[0] = (~sel[2] & ~sel[1] & ~sel[0] * in[0]);
assign c[1] = (~sel[2] & ~sel[1] & sel[0] * in[1]);
assign c[2] = (~sel[2] & sel[1] & ~sel[0] * in[2]);
assign c[3] = (~sel[2] & sel[1] & sel[0] * in[3]);
assign c[4] = (sel[2] & ~sel[1] & ~sel[0] * in[4]);
assign c[5] = (sel[2] & ~sel[1] & sel[0] * in[5]);
assign c[6] = (sel[2] & sel[1] & ~sel[0] * in[6]);
assign c[7] = (sel[2] & sel[1] & sel[0] * in[7]);
assign o = e & (c[0] | c[1] | c[2] | c[3] | c[4] | c[5] | c[6] | c[7]);
endmodule | 0 |
6,475 | data/full_repos/permissive/116468596/rectangleSM.v | 116,468,596 | rectangleSM.v | v | 62 | 91 | [] | [] | [] | [(23, 61)] | null | null | 1: b"%Error: data/full_repos/permissive/116468596/rectangleSM.v:48: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b1)) ff_instance_0 (.C(clk), .CE(1'b1), .D(inD[0]), .Q(outQ[0]));\n ^~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n FDRE\n FDRE.v\n FDRE.sv\n obj_dir/FDRE\n obj_dir/FDRE.v\n obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/rectangleSM.v:49: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0)) ff_instance_1 (.C(clk), .CE(1'b1), .D(inD[1]), .Q(outQ[1]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/rectangleSM.v:50: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0)) ff_instance_2 (.C(clk), .CE(1'b1), .D(inD[2]), .Q(outQ[2]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/rectangleSM.v:51: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0)) ff_instance_3 (.C(clk), .CE(1'b1), .D(inD[3]), .Q(outQ[3]));\n ^~~~\n%Error: Exiting due to 4 error(s)\n" | 7,385 | module | module rectangleSM(
input hit, allHit, timeOut,
input clk, btnC,
output startState,loadTime,
output returnHit, resetState,
output flash, go, activeRed
);
wire [9:0] con;
wire [3:0] inD;
wire [3:0] outQ;
assign con[0] = ~btnC & outQ[0];
assign con[1] = btnC & outQ[0];
assign con[2] = ~hit & outQ[1];
assign con[3] = hit & outQ[1] & ~timeOut;
assign con[4] = ~allHit & outQ[2] & ~timeOut;
assign con[5] = allHit & outQ[2];
assign con[6] = ~btnC & outQ[3];
assign con[7] = (btnC & outQ[3])|timeOut;
assign con[8] = timeOut & outQ[2];
assign con[9] = timeOut & outQ[1];
assign inD[0] = con[0];
assign inD[1] = con[1] | con[2] | con[7] | con[8];
assign inD[2] = con[3] | con[4];
assign inD[3] = con[5] | con[6];
FDRE #(.INIT(1'b1)) ff_instance_0 (.C(clk), .CE(1'b1), .D(inD[0]), .Q(outQ[0]));
FDRE #(.INIT(1'b0)) ff_instance_1 (.C(clk), .CE(1'b1), .D(inD[1]), .Q(outQ[1]));
FDRE #(.INIT(1'b0)) ff_instance_2 (.C(clk), .CE(1'b1), .D(inD[2]), .Q(outQ[2]));
FDRE #(.INIT(1'b0)) ff_instance_3 (.C(clk), .CE(1'b1), .D(inD[3]), .Q(outQ[3]));
assign loadTime = con[8] | con[9];
assign startState = outQ[0];
assign resetState = con[7] | timeOut;
assign returnHit = outQ[2] | outQ[3] ;
assign go = outQ[1];
assign flash = outQ[2] | outQ[3];
assign activeRed = outQ[1];
endmodule | module rectangleSM(
input hit, allHit, timeOut,
input clk, btnC,
output startState,loadTime,
output returnHit, resetState,
output flash, go, activeRed
); |
wire [9:0] con;
wire [3:0] inD;
wire [3:0] outQ;
assign con[0] = ~btnC & outQ[0];
assign con[1] = btnC & outQ[0];
assign con[2] = ~hit & outQ[1];
assign con[3] = hit & outQ[1] & ~timeOut;
assign con[4] = ~allHit & outQ[2] & ~timeOut;
assign con[5] = allHit & outQ[2];
assign con[6] = ~btnC & outQ[3];
assign con[7] = (btnC & outQ[3])|timeOut;
assign con[8] = timeOut & outQ[2];
assign con[9] = timeOut & outQ[1];
assign inD[0] = con[0];
assign inD[1] = con[1] | con[2] | con[7] | con[8];
assign inD[2] = con[3] | con[4];
assign inD[3] = con[5] | con[6];
FDRE #(.INIT(1'b1)) ff_instance_0 (.C(clk), .CE(1'b1), .D(inD[0]), .Q(outQ[0]));
FDRE #(.INIT(1'b0)) ff_instance_1 (.C(clk), .CE(1'b1), .D(inD[1]), .Q(outQ[1]));
FDRE #(.INIT(1'b0)) ff_instance_2 (.C(clk), .CE(1'b1), .D(inD[2]), .Q(outQ[2]));
FDRE #(.INIT(1'b0)) ff_instance_3 (.C(clk), .CE(1'b1), .D(inD[3]), .Q(outQ[3]));
assign loadTime = con[8] | con[9];
assign startState = outQ[0];
assign resetState = con[7] | timeOut;
assign returnHit = outQ[2] | outQ[3] ;
assign go = outQ[1];
assign flash = outQ[2] | outQ[3];
assign activeRed = outQ[1];
endmodule | 0 |
6,476 | data/full_repos/permissive/116468596/redRectangle.v | 116,468,596 | redRectangle.v | v | 58 | 239 | [] | [] | [] | [(23, 57)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/116468596/redRectangle.v:42: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ADD generates 10 bits.\n : ... In instance redRectangle\n wire bottomLength = yPos+recLength; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/116468596/redRectangle.v:43: Cannot find file containing module: \'rectangleSM\'\n rectangleSM rectSM (.clk(clk), .btnC(btnC), .hit(hit), .timeOut(timeOut), .loadTime(loadTime), .allHit(allHit), .startState(startState), .returnHit(returnHit), .activeRed(activeRed), .flash(flash), .go(go), .resetState(resetState) ); \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/rectangleSM\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/rectangleSM.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/rectangleSM.sv\n rectangleSM\n rectangleSM.v\n rectangleSM.sv\n obj_dir/rectangleSM\n obj_dir/rectangleSM.v\n obj_dir/rectangleSM.sv\n%Error: data/full_repos/permissive/116468596/redRectangle.v:45: Cannot find file containing module: \'tenBitCount\'\n tenBitCount vertical (.clk(clk), .reset(resetState | startState), .enable(go & frame & doneCount), .up(1\'b1), .down(1\'b0),\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 7,386 | module | module redRectangle(
input syncFlash, timeOut,
input hit, allHit,
input [15:0] sw,
input [9:0] hOutQ,
input [9:0] vOutQ,
input [9:0] horizontalPosition,
input clk, frame, doneCount,
input btnC,
output redRect, flash, startState, loadTime,
output [9:0] yPos,
output outOfAR, outOfTopAR,
output resetState, activeRed,
output returnHit
);
wire topWall, leftWall, rightWall, bottomWall;
wire go;
wire activeRegion;
wire [9:0] recLength;
wire bottomLength = yPos+recLength;
rectangleSM rectSM (.clk(clk), .btnC(btnC), .hit(hit), .timeOut(timeOut), .loadTime(loadTime), .allHit(allHit), .startState(startState), .returnHit(returnHit), .activeRed(activeRed), .flash(flash), .go(go), .resetState(resetState) );
tenBitCount vertical (.clk(clk), .reset(resetState | startState), .enable(go & frame & doneCount), .up(1'b1), .down(1'b0),
.LD(1'b0), .outQ(yPos) );
assign activeRegion = ( (hOutQ > 10'd8) & (hOutQ < 10'd631) & (vOutQ > 10'd8) & (vOutQ < 10'd471) );
assign outOfAR = ( yPos == 10'd4 );
assign recLength = ( 10'd16 + sw[6:4]*10'd32 );
assign redRect = (activeRed | (syncFlash & flash)) & ~(yPos < 10'd9) & ~startState & doneCount & activeRegion &
((hOutQ >= horizontalPosition-10'd4) & (hOutQ <= horizontalPosition+10'd4)) & ((vOutQ >= yPos) & (vOutQ <= yPos+recLength));
endmodule | module redRectangle(
input syncFlash, timeOut,
input hit, allHit,
input [15:0] sw,
input [9:0] hOutQ,
input [9:0] vOutQ,
input [9:0] horizontalPosition,
input clk, frame, doneCount,
input btnC,
output redRect, flash, startState, loadTime,
output [9:0] yPos,
output outOfAR, outOfTopAR,
output resetState, activeRed,
output returnHit
); |
wire topWall, leftWall, rightWall, bottomWall;
wire go;
wire activeRegion;
wire [9:0] recLength;
wire bottomLength = yPos+recLength;
rectangleSM rectSM (.clk(clk), .btnC(btnC), .hit(hit), .timeOut(timeOut), .loadTime(loadTime), .allHit(allHit), .startState(startState), .returnHit(returnHit), .activeRed(activeRed), .flash(flash), .go(go), .resetState(resetState) );
tenBitCount vertical (.clk(clk), .reset(resetState | startState), .enable(go & frame & doneCount), .up(1'b1), .down(1'b0),
.LD(1'b0), .outQ(yPos) );
assign activeRegion = ( (hOutQ > 10'd8) & (hOutQ < 10'd631) & (vOutQ > 10'd8) & (vOutQ < 10'd471) );
assign outOfAR = ( yPos == 10'd4 );
assign recLength = ( 10'd16 + sw[6:4]*10'd32 );
assign redRect = (activeRed | (syncFlash & flash)) & ~(yPos < 10'd9) & ~startState & doneCount & activeRegion &
((hOutQ >= horizontalPosition-10'd4) & (hOutQ <= horizontalPosition+10'd4)) & ((vOutQ >= yPos) & (vOutQ <= yPos+recLength));
endmodule | 0 |
6,477 | data/full_repos/permissive/116468596/ringCounter.v | 116,468,596 | ringCounter.v | v | 46 | 104 | [] | [] | [] | [(23, 45)] | null | null | 1: b"%Error: data/full_repos/permissive/116468596/ringCounter.v:34: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b1) ) ff_instance_1 (.C(clk), .R(reset), .CE(digsel), .D(outQ[3]), .Q(outQ[0]));\n ^~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n FDRE\n FDRE.v\n FDRE.sv\n obj_dir/FDRE\n obj_dir/FDRE.v\n obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/ringCounter.v:35: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(reset), .CE(digsel), .D(outQ[0]), .Q(outQ[1]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/ringCounter.v:36: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) ff_instance_3 (.C(clk), .R(reset), .CE(digsel), .D(outQ[1]), .Q(outQ[2]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/ringCounter.v:37: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0) ) ff_instance_4 (.C(clk), .R(reset), .CE(digsel), .D(outQ[2]), .Q(outQ[3]));\n ^~~~\n%Error: Exiting due to 4 error(s)\n" | 7,387 | module | module ringCounter(
input clk,digsel,
output [3:0] sel
);
wire [3:0] outQ;
FDRE #(.INIT(1'b1) ) ff_instance_1 (.C(clk), .R(reset), .CE(digsel), .D(outQ[3]), .Q(outQ[0]));
FDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(reset), .CE(digsel), .D(outQ[0]), .Q(outQ[1]));
FDRE #(.INIT(1'b0) ) ff_instance_3 (.C(clk), .R(reset), .CE(digsel), .D(outQ[1]), .Q(outQ[2]));
FDRE #(.INIT(1'b0) ) ff_instance_4 (.C(clk), .R(reset), .CE(digsel), .D(outQ[2]), .Q(outQ[3]));
assign sel = outQ;
endmodule | module ringCounter(
input clk,digsel,
output [3:0] sel
); |
wire [3:0] outQ;
FDRE #(.INIT(1'b1) ) ff_instance_1 (.C(clk), .R(reset), .CE(digsel), .D(outQ[3]), .Q(outQ[0]));
FDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(reset), .CE(digsel), .D(outQ[0]), .Q(outQ[1]));
FDRE #(.INIT(1'b0) ) ff_instance_3 (.C(clk), .R(reset), .CE(digsel), .D(outQ[1]), .Q(outQ[2]));
FDRE #(.INIT(1'b0) ) ff_instance_4 (.C(clk), .R(reset), .CE(digsel), .D(outQ[2]), .Q(outQ[3]));
assign sel = outQ;
endmodule | 0 |
6,478 | data/full_repos/permissive/116468596/selector.v | 116,468,596 | selector.v | v | 37 | 119 | [] | [] | [] | [(23, 36)] | null | data/verilator_xmls/8a7231c5-f889-46d5-85ab-7d2001e46046.xml | null | 7,388 | module | module selector(
input [3:0] sel,
input [15:0] N,
output [3:0] H
);
assign H = ((N[15:12] & {4{sel[3]}}) | (N[11:8] & {4{sel[2]}}) | (N[7:4] & {4{sel[1]}}) | (N[3:0] & {4{sel[0]}}));
endmodule | module selector(
input [3:0] sel,
input [15:0] N,
output [3:0] H
); |
assign H = ((N[15:12] & {4{sel[3]}}) | (N[11:8] & {4{sel[2]}}) | (N[7:4] & {4{sel[1]}}) | (N[3:0] & {4{sel[0]}}));
endmodule | 0 |
6,479 | data/full_repos/permissive/116468596/taggerMod.v | 116,468,596 | taggerMod.v | v | 50 | 154 | [] | [] | [] | [(22, 49)] | null | null | 1: b"%Error: data/full_repos/permissive/116468596/taggerMod.v:36: Cannot find file containing module: 'tenBitCount'\n tenBitCount horizontal (.clk(clk), .enable( frame & (cntLeft | cntRight)), .up(cntRight), .down(cntLeft), .LD(upDownLD), .reset(1'b0),\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/tenBitCount\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/tenBitCount.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/tenBitCount.sv\n tenBitCount\n tenBitCount.v\n tenBitCount.sv\n obj_dir/tenBitCount\n obj_dir/tenBitCount.v\n obj_dir/tenBitCount.sv\n%Error: data/full_repos/permissive/116468596/taggerMod.v:39: Cannot find file containing module: 'tenBitCount'\n tenBitCount vertical (.clk(clk), .enable( frame & (cntDown | cntUp)), .up(cntDown), .down(cntUp), .LD(upDownLD), .reset(1'b0),\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 7,389 | module | module taggerMod(
input [9:0] hOutQ,
input [9:0] vOutQ,
input frame, syncFlash, activeGreen,
input clk, upDownLD, leftRightLD, cntUp, cntDown, cntLeft, cntRight,
output greenSquare,
output [9:0] xPos,
output [9:0] yPos,
output topHit, bottomHit, leftHit, rightHit
);
wire [9:0] loadxD;
wire [9:0] loadyD;
wire xStop, yStop;
tenBitCount horizontal (.clk(clk), .enable( frame & (cntLeft | cntRight)), .up(cntRight), .down(cntLeft), .LD(upDownLD), .reset(1'b0),
.loadD(10'd320), .outQ(xPos));
tenBitCount vertical (.clk(clk), .enable( frame & (cntDown | cntUp)), .up(cntDown), .down(cntUp), .LD(upDownLD), .reset(1'b0),
.loadD(10'd240), .outQ(yPos));
assign topHit = (yPos == 10'd16);
assign bottomHit = (yPos == 10'd463);
assign rightHit = (xPos == 10'd623);
assign leftHit = (xPos == 10'd16);
assign greenSquare = (activeGreen | syncFlash) & ((hOutQ >= xPos-10'd8) & (hOutQ <= xPos+10'd8)) & ((vOutQ >= yPos-10'd8) & (vOutQ <= yPos+10'd8));
endmodule | module taggerMod(
input [9:0] hOutQ,
input [9:0] vOutQ,
input frame, syncFlash, activeGreen,
input clk, upDownLD, leftRightLD, cntUp, cntDown, cntLeft, cntRight,
output greenSquare,
output [9:0] xPos,
output [9:0] yPos,
output topHit, bottomHit, leftHit, rightHit
); |
wire [9:0] loadxD;
wire [9:0] loadyD;
wire xStop, yStop;
tenBitCount horizontal (.clk(clk), .enable( frame & (cntLeft | cntRight)), .up(cntRight), .down(cntLeft), .LD(upDownLD), .reset(1'b0),
.loadD(10'd320), .outQ(xPos));
tenBitCount vertical (.clk(clk), .enable( frame & (cntDown | cntUp)), .up(cntDown), .down(cntUp), .LD(upDownLD), .reset(1'b0),
.loadD(10'd240), .outQ(yPos));
assign topHit = (yPos == 10'd16);
assign bottomHit = (yPos == 10'd463);
assign rightHit = (xPos == 10'd623);
assign leftHit = (xPos == 10'd16);
assign greenSquare = (activeGreen | syncFlash) & ((hOutQ >= xPos-10'd8) & (hOutQ <= xPos+10'd8)) & ((vOutQ >= yPos-10'd8) & (vOutQ <= yPos+10'd8));
endmodule | 0 |
6,480 | data/full_repos/permissive/116468596/tenBitCount.v | 116,468,596 | tenBitCount.v | v | 82 | 136 | [] | [] | [] | [(23, 81)] | null | null | 1: b"%Error: data/full_repos/permissive/116468596/tenBitCount.v:68: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) ff_instance_1 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[0]), .Q(outQ[0]));\n^~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n FDRE\n FDRE.v\n FDRE.sv\n obj_dir/FDRE\n obj_dir/FDRE.v\n obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/tenBitCount.v:69: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[1]), .Q(outQ[1]));\n^~~~\n%Error: data/full_repos/permissive/116468596/tenBitCount.v:70: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) ff_instance_3 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[2]), .Q(outQ[2]));\n^~~~\n%Error: data/full_repos/permissive/116468596/tenBitCount.v:71: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) ff_instance_4 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[3]), .Q(outQ[3]));\n^~~~\n%Error: data/full_repos/permissive/116468596/tenBitCount.v:72: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) ff_instance_5 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[4]), .Q(outQ[4]));\n^~~~\n%Error: data/full_repos/permissive/116468596/tenBitCount.v:73: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) ff_instance_6 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[5]), .Q(outQ[5]));\n^~~~\n%Error: data/full_repos/permissive/116468596/tenBitCount.v:74: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) ff_instance_7 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[6]), .Q(outQ[6]));\n^~~~\n%Error: data/full_repos/permissive/116468596/tenBitCount.v:75: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) ff_instance_8 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[7]), .Q(outQ[7]));\n^~~~\n%Error: data/full_repos/permissive/116468596/tenBitCount.v:76: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) ff_instance_9 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[8]), .Q(outQ[8]));\n^~~~\n%Error: data/full_repos/permissive/116468596/tenBitCount.v:77: Cannot find file containing module: 'FDRE'\nFDRE #(.INIT(1'b0) ) ff_instance_10 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[9]), .Q(outQ[9]));\n^~~~\n%Error: Exiting due to 10 error(s)\n" | 7,390 | module | module tenBitCount(
input clk, enable, up, down, LD, reset,
input [9:0] loadD,
output [9:0] outQ,
output TC
);
wire [9:0] inD;
wire [9:0] invD;
wire [9:0] countSelect;
wire [9:0] loadSelect;
wire [9:0] temp;
assign inD[0] = enable ^ outQ[0];
assign inD[1] = (enable & outQ[0]) ^ outQ[1];
assign inD[2] = (enable & outQ[0] & outQ[1]) ^ outQ[2];
assign inD[3] = (enable & outQ[0] & outQ[1] & outQ[2]) ^ outQ[3];
assign inD[4] = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3]) ^ outQ[4];
assign inD[5] = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4]) ^ outQ[5];
assign inD[6] = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5]) ^ outQ[6];
assign inD[7] = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5] & outQ[6]) ^ outQ[7];
assign inD[8] = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5] & outQ[6] & outQ[7]) ^ outQ[8];
assign inD[9] = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5] & outQ[6] & outQ[7] & outQ[8]) ^ outQ[9];
assign invD[0] = enable ^ outQ[0];
assign invD[1] = (enable & ~outQ[0]) ^ outQ[1];
assign invD[2] = (enable & ~outQ[0] & ~outQ[1]) ^ outQ[2];
assign invD[3] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2]) ^ outQ[3];
assign invD[4] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3]) ^ outQ[4];
assign invD[5] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4]) ^ outQ[5];
assign invD[6] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5]) ^ outQ[6];
assign invD[7] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6]) ^ outQ[7];
assign invD[8] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7]) ^ outQ[8];
assign invD[9] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7] & ~outQ[8]) ^ outQ[9];
assign temp[0] = ( (~LD & up & inD[0]) | (~LD & down & invD[0]) | (LD & loadD[0]) );
assign temp[1] = ( (~LD & up & inD[1]) | (~LD & down & invD[1]) | (LD & loadD[1]) );
assign temp[2] = ( (~LD & up & inD[2]) | (~LD & down & invD[2]) | (LD & loadD[2]) );
assign temp[3] = ( (~LD & up & inD[3]) | (~LD & down & invD[3]) | (LD & loadD[3]) );
assign temp[4] = ( (~LD & up & inD[4]) | (~LD & down & invD[4]) | (LD & loadD[4]) );
assign temp[5] = ( (~LD & up & inD[5]) | (~LD & down & invD[5]) | (LD & loadD[5]) );
assign temp[6] = ( (~LD & up & inD[6]) | (~LD & down & invD[6]) | (LD & loadD[6]) );
assign temp[7] = ( (~LD & up & inD[7]) | (~LD & down & invD[7]) | (LD & loadD[7]) );
assign temp[8] = ( (~LD & up & inD[8]) | (~LD & down & invD[8]) | (LD & loadD[8]) );
assign temp[9] = ( (~LD & up & inD[9]) | (~LD & down & invD[9]) | (LD & loadD[9]) );
FDRE #(.INIT(1'b0) ) ff_instance_1 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[0]), .Q(outQ[0]));
FDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[1]), .Q(outQ[1]));
FDRE #(.INIT(1'b0) ) ff_instance_3 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[2]), .Q(outQ[2]));
FDRE #(.INIT(1'b0) ) ff_instance_4 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[3]), .Q(outQ[3]));
FDRE #(.INIT(1'b0) ) ff_instance_5 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[4]), .Q(outQ[4]));
FDRE #(.INIT(1'b0) ) ff_instance_6 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[5]), .Q(outQ[5]));
FDRE #(.INIT(1'b0) ) ff_instance_7 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[6]), .Q(outQ[6]));
FDRE #(.INIT(1'b0) ) ff_instance_8 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[7]), .Q(outQ[7]));
FDRE #(.INIT(1'b0) ) ff_instance_9 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[8]), .Q(outQ[8]));
FDRE #(.INIT(1'b0) ) ff_instance_10 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[9]), .Q(outQ[9]));
assign TC = outQ[9] & outQ[8] & ~outQ[7] & ~outQ[6] & ~outQ[5] & outQ[4] & outQ[3] & outQ[2] & outQ[1] & outQ[0];
endmodule | module tenBitCount(
input clk, enable, up, down, LD, reset,
input [9:0] loadD,
output [9:0] outQ,
output TC
); |
wire [9:0] inD;
wire [9:0] invD;
wire [9:0] countSelect;
wire [9:0] loadSelect;
wire [9:0] temp;
assign inD[0] = enable ^ outQ[0];
assign inD[1] = (enable & outQ[0]) ^ outQ[1];
assign inD[2] = (enable & outQ[0] & outQ[1]) ^ outQ[2];
assign inD[3] = (enable & outQ[0] & outQ[1] & outQ[2]) ^ outQ[3];
assign inD[4] = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3]) ^ outQ[4];
assign inD[5] = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4]) ^ outQ[5];
assign inD[6] = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5]) ^ outQ[6];
assign inD[7] = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5] & outQ[6]) ^ outQ[7];
assign inD[8] = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5] & outQ[6] & outQ[7]) ^ outQ[8];
assign inD[9] = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5] & outQ[6] & outQ[7] & outQ[8]) ^ outQ[9];
assign invD[0] = enable ^ outQ[0];
assign invD[1] = (enable & ~outQ[0]) ^ outQ[1];
assign invD[2] = (enable & ~outQ[0] & ~outQ[1]) ^ outQ[2];
assign invD[3] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2]) ^ outQ[3];
assign invD[4] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3]) ^ outQ[4];
assign invD[5] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4]) ^ outQ[5];
assign invD[6] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5]) ^ outQ[6];
assign invD[7] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6]) ^ outQ[7];
assign invD[8] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7]) ^ outQ[8];
assign invD[9] = (enable & ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & ~outQ[7] & ~outQ[8]) ^ outQ[9];
assign temp[0] = ( (~LD & up & inD[0]) | (~LD & down & invD[0]) | (LD & loadD[0]) );
assign temp[1] = ( (~LD & up & inD[1]) | (~LD & down & invD[1]) | (LD & loadD[1]) );
assign temp[2] = ( (~LD & up & inD[2]) | (~LD & down & invD[2]) | (LD & loadD[2]) );
assign temp[3] = ( (~LD & up & inD[3]) | (~LD & down & invD[3]) | (LD & loadD[3]) );
assign temp[4] = ( (~LD & up & inD[4]) | (~LD & down & invD[4]) | (LD & loadD[4]) );
assign temp[5] = ( (~LD & up & inD[5]) | (~LD & down & invD[5]) | (LD & loadD[5]) );
assign temp[6] = ( (~LD & up & inD[6]) | (~LD & down & invD[6]) | (LD & loadD[6]) );
assign temp[7] = ( (~LD & up & inD[7]) | (~LD & down & invD[7]) | (LD & loadD[7]) );
assign temp[8] = ( (~LD & up & inD[8]) | (~LD & down & invD[8]) | (LD & loadD[8]) );
assign temp[9] = ( (~LD & up & inD[9]) | (~LD & down & invD[9]) | (LD & loadD[9]) );
FDRE #(.INIT(1'b0) ) ff_instance_1 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[0]), .Q(outQ[0]));
FDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[1]), .Q(outQ[1]));
FDRE #(.INIT(1'b0) ) ff_instance_3 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[2]), .Q(outQ[2]));
FDRE #(.INIT(1'b0) ) ff_instance_4 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[3]), .Q(outQ[3]));
FDRE #(.INIT(1'b0) ) ff_instance_5 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[4]), .Q(outQ[4]));
FDRE #(.INIT(1'b0) ) ff_instance_6 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[5]), .Q(outQ[5]));
FDRE #(.INIT(1'b0) ) ff_instance_7 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[6]), .Q(outQ[6]));
FDRE #(.INIT(1'b0) ) ff_instance_8 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[7]), .Q(outQ[7]));
FDRE #(.INIT(1'b0) ) ff_instance_9 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[8]), .Q(outQ[8]));
FDRE #(.INIT(1'b0) ) ff_instance_10 (.C(clk), .R(reset), .CE(enable | LD), .D(temp[9]), .Q(outQ[9]));
assign TC = outQ[9] & outQ[8] & ~outQ[7] & ~outQ[6] & ~outQ[5] & outQ[4] & outQ[3] & outQ[2] & outQ[1] & outQ[0];
endmodule | 0 |
6,481 | data/full_repos/permissive/116468596/topMod.v | 116,468,596 | topMod.v | v | 144 | 408 | [] | [] | [] | [(23, 143)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/116468596/topMod.v:86: Signal definition not found, creating implicitly: \'rnd8\'\n : ... Suggested alternative: \'rnd\'\n assign rnd8 = {1\'b1, rnd[2], 1\'b0, rnd[4], 1\'b1, rnd[3], 1\'b0, rnd[6]}; \n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/116468596/topMod.v:115: Signal definition not found, creating implicitly: \'allHit\'\n : ... Suggested alternative: \'allhit\'\n assign allHit = {returnHit[0]&returnHit[1]&returnHit[2]&returnHit[3]&returnHit[4]&returnHit[5]&returnHit[6]&returnHit[7]};\n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/116468596/topMod.v:120: Signal definition not found, creating implicitly: \'syncFlash\'\n assign vgaRed = {4{redRectPass | (activeRegion & goodWall& allHit & syncFlash) }};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:54: Cannot find file containing module: \'FDRE\'\n FDRE #(.INIT(1\'b0) ) syncFlsh (.C(clk), .R(1\'b0), .CE(1\'b1), .D(eightSec^syncFlash), .Q(syncFlash));\n ^~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n FDRE\n FDRE.v\n FDRE.sv\n obj_dir/FDRE\n obj_dir/FDRE.v\n obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/topMod.v:56: Cannot find file containing module: \'lab7_clks\'\n lab7_clks not_so_slow (.clkin(clkin), .greset(sw[0]), .clk(clk), .digsel(digsel));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:57: Cannot find file containing module: \'count8\'\n count8 twoSecCount (.clk(clk), .enable(frame), .reset(1\'b0), .twoSec(twoSec)); \n ^~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:58: Cannot find file containing module: \'count4\'\n count4 eighthSecCount (.clk(clk), .enable(frame), .eightSec(eightSec)); \n ^~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:59: Cannot find file containing module: \'edgeDetector\'\n edgeDetector ed_btnC (.clk(clk), .btnC(btnC), .edgeOut(edgeOut)); \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:62: Cannot find file containing module: \'vgaControlMod\'\n vgaControlMod monitor (.clk(clk), .enable(1\'b1), .up(1\'b1), .LD(1\'b0), .Hsync(Hsync),\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:68: Cannot find file containing module: \'taggerMod\'\n taggerMod greenSq ( .hOutQ (hOutQ), .vOutQ(vOutQ), .frame(frame), .syncFlash(syncFlash), .activeGreen(activeGreen),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:72: Cannot find file containing module: \'updownTagger\'\n updownTagger upDownSM (.clk(clk), .twoSec(twoSec), .top(topHit), .bottom(bottomHit), .up(btnU), .down(btnD),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:74: Cannot find file containing module: \'updownTagger\'\n updownTagger leftRightSM (.clk(clk), .twoSec(twoSec), .top(rightHit), .bottom(leftHit), .up(btnR), .down(btnL),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:78: Cannot find file containing module: \'lfsr\'\n lfsr rect1Random (.clk(clk), .frame(frame), .rnd(rnd));\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/116468596/topMod.v:86: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n : ... In instance topMod\n assign rnd8 = {1\'b1, rnd[2], 1\'b0, rnd[4], 1\'b1, rnd[3], 1\'b0, rnd[6]}; \n ^\n%Error: data/full_repos/permissive/116468596/topMod.v:87: Cannot find file containing module: \'count8D\'\n count8D count1 (.clk(clk), .enable(frame), .reset(1\'b0), .LD(outOfAR[0]), .inD(rnd), .TC(doneC[0]) );\n ^~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:88: Cannot find file containing module: \'count8D\'\n count8D count2 (.clk(clk), .enable(frame), .reset(1\'b0), .LD(outOfAR[1]), .inD(rnd1), .TC(doneC[1]) );\n ^~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:89: Cannot find file containing module: \'count8D\'\n count8D count3 (.clk(clk), .enable(frame), .reset(1\'b0), .LD(outOfAR[2]), .inD(rnd2), .TC(doneC[2]) );\n ^~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:90: Cannot find file containing module: \'count8D\'\n count8D count4 (.clk(clk), .enable(frame), .reset(1\'b0), .LD(outOfAR[3]), .inD(rnd3), .TC(doneC[3]) );\n ^~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:91: Cannot find file containing module: \'count8D\'\n count8D count5 (.clk(clk), .enable(frame), .reset(1\'b0), .LD(outOfAR[4]), .inD(rnd4), .TC(doneC[4]) );\n ^~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:92: Cannot find file containing module: \'count8D\'\n count8D count6 (.clk(clk), .enable(frame), .reset(1\'b0), .LD(outOfAR[5]), .inD(rnd5), .TC(doneC[5]) );\n ^~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:93: Cannot find file containing module: \'count8D\'\n count8D count7 (.clk(clk), .enable(frame), .reset(1\'b0), .LD(outOfAR[6]), .inD(rnd6), .TC(doneC[6]) );\n ^~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:94: Cannot find file containing module: \'count8D\'\n count8D count8 (.clk(clk), .enable(frame), .reset(1\'b0), .LD(outOfAR[7]), .inD(rnd7), .TC(doneC[7]) );\n ^~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:95: Cannot find file containing module: \'redRectangle\'\n%Error: data/full_repos/permissive/116468596/topMod.v:96: Cannot find file containing module: \'redRectangle\'\n%Error: data/full_repos/permissive/116468596/topMod.v:97: Cannot find file containing module: \'redRectangle\'\n%Error: data/full_repos/permissive/116468596/topMod.v:98: Cannot find file containing module: \'redRectangle\'\n%Error: data/full_repos/permissive/116468596/topMod.v:99: Cannot find file containing module: \'redRectangle\'\n%Error: data/full_repos/permissive/116468596/topMod.v:100: Cannot find file containing module: \'redRectangle\'\n%Error: data/full_repos/permissive/116468596/topMod.v:101: Cannot find file containing module: \'redRectangle\'\n%Error: data/full_repos/permissive/116468596/topMod.v:102: Cannot find file containing module: \'redRectangle\'\n%Warning-WIDTH: data/full_repos/permissive/116468596/topMod.v:103: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 8 bits.\n : ... In instance topMod\n assign btncFilter = {8{btnC}} & resetState & startState & loadTime;\n ^\n%Error: data/full_repos/permissive/116468596/topMod.v:126: Cannot find file containing module: \'count14D\'\n count14D countDown (.clk(clk), .enable(frame & (anyHit & scoreCounterEnable < 4\'d8)), .LD(startState | resetState), .sw(sw), .outQ(outTime), .TC(timeOut) );\n ^~~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:132: Cannot find file containing module: \'ringCounter\'\n ringCounter ring (.clk(clk), .digsel(digsel), .sel(ringOut));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:133: Cannot find file containing module: \'selector\'\n selector select (.sel(ringOut), .N(selectorIn), .H(selOut));\n ^~~~~~~~\n%Error: data/full_repos/permissive/116468596/topMod.v:134: Cannot find file containing module: \'hex7seg\'\n hex7seg display (.n(selOut), .enable(1\'b1), .seg(seg));\n ^~~~~~~\n%Error: Exiting due to 30 error(s), 5 warning(s)\n' | 7,392 | module | module topMod(
input btnU, btnL, btnC, btnR, btnD,
input clkin,
input [15:0] sw,
output [3:0] an,
output [6:0] seg,
output [15:0] led,
output Hsync, Vsync,
output [3:0]vgaRed,
output [3:0] vgaBlue,
output [3:0] vgaGreen
);
wire clk, digsel, frame, eightSec, twoSec, edgeOut;
wire [7:0] doneCount;
wire topHit, bottomHit, cntUp, cntDown, cntRight, cntLeft, upDownLD, leftRightLD;
wire activeGreen, greenSquareOut, greenTagger;
wire [7:0] redRect,activeRed,resetState, startState,loadTime;
wire redRectPass;
wire activeRegion, goodWall, topWall, bottomWall, leftWall, rightWall;
wire [9:0] hOutQ, vOutQ;
wire [7:0] outOfAR, doneC;
wire [7:0] rnd, rnd1, rnd2, rnd3, rnd4, rnd5, rnd6, rnd7;
wire allhit, anyHit, timeOut;
wire [3:0] scoreCounterEnable;
wire [13:0] tempInTime;
wire [13:0] outTime;
wire [7:0] hit, returnHit;
wire [15:0] selectorIn;
wire [3:0] ringOut;
wire [3:0] selOut;
wire btncFilter;
FDRE #(.INIT(1'b0) ) syncFlsh (.C(clk), .R(1'b0), .CE(1'b1), .D(eightSec^syncFlash), .Q(syncFlash));
lab7_clks not_so_slow (.clkin(clkin), .greset(sw[0]), .clk(clk), .digsel(digsel));
count8 twoSecCount (.clk(clk), .enable(frame), .reset(1'b0), .twoSec(twoSec));
count4 eighthSecCount (.clk(clk), .enable(frame), .eightSec(eightSec));
edgeDetector ed_btnC (.clk(clk), .btnC(btnC), .edgeOut(edgeOut));
vgaControlMod monitor (.clk(clk), .enable(1'b1), .up(1'b1), .LD(1'b0), .Hsync(Hsync),
.activeRegion(activeRegion), .Vsync(Vsync), .hOutQ(hOutQ), .vOutQ(vOutQ), .goodWall(goodWall),
.topWall(topWall), .bottomWall(bottomWall), .leftWall(leftWall), .rightWall(rightWall), .frame(frame) );
taggerMod greenSq ( .hOutQ (hOutQ), .vOutQ(vOutQ), .frame(frame), .syncFlash(syncFlash), .activeGreen(activeGreen),
.clk(clk), .cntUp(cntUp), .cntDown(cntDown), .cntRight(cntRight), .cntLeft(cntLeft), .upDownLD(upDownLD),
.leftRightLD(leftRightLD), .greenSquare(greenSquareOut), .topHit(topHit), .bottomHit(bottomHit), .leftHit(leftHit), .rightHit(rightHit) );
updownTagger upDownSM (.clk(clk), .twoSec(twoSec), .top(topHit), .bottom(bottomHit), .up(btnU), .down(btnD),
.countUp(cntUp), .countDown(cntDown), .upDownLD(upDownLD), .activeGreen(activeGreen) );
updownTagger leftRightSM (.clk(clk), .twoSec(twoSec), .top(rightHit), .bottom(leftHit), .up(btnR), .down(btnL),
.countUp(cntRight), .countDown(cntLeft), .upDownLD(leftRightLD) );
lfsr rect1Random (.clk(clk), .frame(frame), .rnd(rnd));
assign rnd1 = {1'b1, rnd[1], 1'b0, rnd[4], 1'b1, rnd[6], 1'b0, rnd[2]};
assign rnd2 = {1'b0, rnd[1], 1'b0, rnd[3], 1'b0, rnd[5], 1'b0, rnd[7]};
assign rnd3 = {1'b0, rnd[2], 1'b0, rnd[4], 1'b0, rnd[6], 1'b0, rnd[3]};
assign rnd4 = {1'b1, rnd[1], 1'b1, rnd[3], 1'b1, rnd[5], 1'b1, rnd[7]};
assign rnd5 = {1'b1, rnd[2], 1'b1, rnd[4], 1'b1, rnd[6], 1'b1, rnd[6]};
assign rnd6 = {1'b0, rnd[1], 1'b1, rnd[3], 1'b0, rnd[5], 1'b1, rnd[7]};
assign rnd7 = {1'b0, rnd[2], 1'b1, rnd[4], 1'b0, rnd[6], 1'b1, rnd[5]};
assign rnd8 = {1'b1, rnd[2], 1'b0, rnd[4], 1'b1, rnd[3], 1'b0, rnd[6]};
count8D count1 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[0]), .inD(rnd), .TC(doneC[0]) );
count8D count2 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[1]), .inD(rnd1), .TC(doneC[1]) );
count8D count3 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[2]), .inD(rnd2), .TC(doneC[2]) );
count8D count4 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[3]), .inD(rnd3), .TC(doneC[3]) );
count8D count5 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[4]), .inD(rnd4), .TC(doneC[4]) );
count8D count6 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[5]), .inD(rnd5), .TC(doneC[5]) );
count8D count7 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[6]), .inD(rnd6), .TC(doneC[6]) );
count8D count8 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[7]), .inD(rnd7), .TC(doneC[7]) );
redRectangle rect1 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[0]), .allHit(allHit), .returnHit(returnHit[0]), .doneCount(doneC[0]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd78), .redRect(redRect[0]), .outOfAR(outOfAR[0]), .activeRed(activeRed[0]), .resetState(resetState[0]), .startState(startState[0]),.loadTime(loadTime[0]) );
redRectangle rect2 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[1]), .allHit(allHit), .returnHit(returnHit[1]), .doneCount(doneC[1]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd146), .redRect(redRect[1]), .outOfAR(outOfAR[1]), .activeRed(activeRed[1]), .resetState(resetState[1]), .startState(startState[1]),.loadTime(loadTime[1]) );
redRectangle rect3 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[2]), .allHit(allHit), .returnHit(returnHit[2]), .doneCount(doneC[2]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd214), .redRect(redRect[2]), .outOfAR(outOfAR[2]), .activeRed(activeRed[2]), .resetState(resetState[2]), .startState(startState[2]),.loadTime(loadTime[2]) );
redRectangle rect4 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[3]), .allHit(allHit), .returnHit(returnHit[3]), .doneCount(doneC[3]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd282), .redRect(redRect[3]), .outOfAR(outOfAR[3]), .activeRed(activeRed[3]), .resetState(resetState[3]), .startState(startState[3]),.loadTime(loadTime[3]) );
redRectangle rect5 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[4]), .allHit(allHit), .returnHit(returnHit[4]), .doneCount(doneC[4]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd350), .redRect(redRect[4]), .outOfAR(outOfAR[4]), .activeRed(activeRed[4]), .resetState(resetState[4]), .startState(startState[4]),.loadTime(loadTime[4]) );
redRectangle rect6 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[5]), .allHit(allHit), .returnHit(returnHit[5]), .doneCount(doneC[5]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd418), .redRect(redRect[5]), .outOfAR(outOfAR[5]), .activeRed(activeRed[5]), .resetState(resetState[5]), .startState(startState[5]),.loadTime(loadTime[5]) );
redRectangle rect7 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[6]), .allHit(allHit), .returnHit(returnHit[6]), .doneCount(doneC[6]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd486), .redRect(redRect[6]), .outOfAR(outOfAR[6]), .activeRed(activeRed[6]), .resetState(resetState[6]), .startState(startState[6]),.loadTime(loadTime[6]) );
redRectangle rect8 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[7]), .allHit(allHit), .returnHit(returnHit[7]), .doneCount(doneC[7]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd554), .redRect(redRect[7]), .outOfAR(outOfAR[7]), .activeRed(activeRed[7]), .resetState(resetState[7]), .startState(startState[7]),.loadTime(loadTime[7]) );
assign btncFilter = {8{btnC}} & resetState & startState & loadTime;
assign hit[0] = {redRect[0] & greenTagger};
assign hit[1] = {redRect[1] & greenTagger};
assign hit[2] = {redRect[2] & greenTagger};
assign hit[3] = {redRect[3] & greenTagger};
assign hit[4] = {redRect[4] & greenTagger};
assign hit[5] = {redRect[5] & greenTagger};
assign hit[6] = {redRect[6] & greenTagger};
assign hit[7] = {redRect[7] & greenTagger};
assign scoreCounterEnable = { {3'b000, returnHit[0]} + {3'b000, returnHit[1]} + {3'b000, returnHit[2]} + {3'b000, returnHit[3]} + {3'b000, returnHit[4]} +
{3'b000, returnHit[5]} + {3'b000, returnHit[6]} + {3'b000, returnHit[7]} };
assign allHit = {returnHit[0]&returnHit[1]&returnHit[2]&returnHit[3]&returnHit[4]&returnHit[5]&returnHit[6]&returnHit[7]};
assign anyHit = {returnHit[0]|returnHit[1]|returnHit[2]|returnHit[3]|returnHit[4]|returnHit[5]|returnHit[6]|returnHit[7]};
assign redRectPass = (activeRegion & redRect[0])|(activeRegion & redRect[1])|(activeRegion & redRect[2])|(activeRegion & redRect[3])
|(activeRegion & redRect[4])|(activeRegion & redRect[5])|(activeRegion & redRect[6])|(activeRegion & redRect[7]);
assign vgaRed = {4{redRectPass | (activeRegion & goodWall& allHit & syncFlash) }};
assign greenTagger = activeRegion & greenSquareOut;
assign vgaGreen = {4{greenTagger | (activeRegion & goodWall & allHit & syncFlash) }};
assign vgaBlue = {4{(activeRegion & goodWall & ~allHit) |
(activeRegion & goodWall & allHit & syncFlash)}};
count14D countDown (.clk(clk), .enable(frame & (anyHit & scoreCounterEnable < 4'd8)), .LD(startState | resetState), .sw(sw), .outQ(outTime), .TC(timeOut) );
assign selectorIn = {scoreCounterEnable, 1'b0,1'b0,1'b0,1'b0, outTime[13:10],outTime[9:6]};
ringCounter ring (.clk(clk), .digsel(digsel), .sel(ringOut));
selector select (.sel(ringOut), .N(selectorIn), .H(selOut));
hex7seg display (.n(selOut), .enable(1'b1), .seg(seg));
assign led[15:4] = sw[15:4];
assign an[0] = ~ringOut[0];
assign an[1] = ~ringOut[1];
assign an[2] = 1'b1;
assign an[3] = ~ringOut[3];
endmodule | module topMod(
input btnU, btnL, btnC, btnR, btnD,
input clkin,
input [15:0] sw,
output [3:0] an,
output [6:0] seg,
output [15:0] led,
output Hsync, Vsync,
output [3:0]vgaRed,
output [3:0] vgaBlue,
output [3:0] vgaGreen
); |
wire clk, digsel, frame, eightSec, twoSec, edgeOut;
wire [7:0] doneCount;
wire topHit, bottomHit, cntUp, cntDown, cntRight, cntLeft, upDownLD, leftRightLD;
wire activeGreen, greenSquareOut, greenTagger;
wire [7:0] redRect,activeRed,resetState, startState,loadTime;
wire redRectPass;
wire activeRegion, goodWall, topWall, bottomWall, leftWall, rightWall;
wire [9:0] hOutQ, vOutQ;
wire [7:0] outOfAR, doneC;
wire [7:0] rnd, rnd1, rnd2, rnd3, rnd4, rnd5, rnd6, rnd7;
wire allhit, anyHit, timeOut;
wire [3:0] scoreCounterEnable;
wire [13:0] tempInTime;
wire [13:0] outTime;
wire [7:0] hit, returnHit;
wire [15:0] selectorIn;
wire [3:0] ringOut;
wire [3:0] selOut;
wire btncFilter;
FDRE #(.INIT(1'b0) ) syncFlsh (.C(clk), .R(1'b0), .CE(1'b1), .D(eightSec^syncFlash), .Q(syncFlash));
lab7_clks not_so_slow (.clkin(clkin), .greset(sw[0]), .clk(clk), .digsel(digsel));
count8 twoSecCount (.clk(clk), .enable(frame), .reset(1'b0), .twoSec(twoSec));
count4 eighthSecCount (.clk(clk), .enable(frame), .eightSec(eightSec));
edgeDetector ed_btnC (.clk(clk), .btnC(btnC), .edgeOut(edgeOut));
vgaControlMod monitor (.clk(clk), .enable(1'b1), .up(1'b1), .LD(1'b0), .Hsync(Hsync),
.activeRegion(activeRegion), .Vsync(Vsync), .hOutQ(hOutQ), .vOutQ(vOutQ), .goodWall(goodWall),
.topWall(topWall), .bottomWall(bottomWall), .leftWall(leftWall), .rightWall(rightWall), .frame(frame) );
taggerMod greenSq ( .hOutQ (hOutQ), .vOutQ(vOutQ), .frame(frame), .syncFlash(syncFlash), .activeGreen(activeGreen),
.clk(clk), .cntUp(cntUp), .cntDown(cntDown), .cntRight(cntRight), .cntLeft(cntLeft), .upDownLD(upDownLD),
.leftRightLD(leftRightLD), .greenSquare(greenSquareOut), .topHit(topHit), .bottomHit(bottomHit), .leftHit(leftHit), .rightHit(rightHit) );
updownTagger upDownSM (.clk(clk), .twoSec(twoSec), .top(topHit), .bottom(bottomHit), .up(btnU), .down(btnD),
.countUp(cntUp), .countDown(cntDown), .upDownLD(upDownLD), .activeGreen(activeGreen) );
updownTagger leftRightSM (.clk(clk), .twoSec(twoSec), .top(rightHit), .bottom(leftHit), .up(btnR), .down(btnL),
.countUp(cntRight), .countDown(cntLeft), .upDownLD(leftRightLD) );
lfsr rect1Random (.clk(clk), .frame(frame), .rnd(rnd));
assign rnd1 = {1'b1, rnd[1], 1'b0, rnd[4], 1'b1, rnd[6], 1'b0, rnd[2]};
assign rnd2 = {1'b0, rnd[1], 1'b0, rnd[3], 1'b0, rnd[5], 1'b0, rnd[7]};
assign rnd3 = {1'b0, rnd[2], 1'b0, rnd[4], 1'b0, rnd[6], 1'b0, rnd[3]};
assign rnd4 = {1'b1, rnd[1], 1'b1, rnd[3], 1'b1, rnd[5], 1'b1, rnd[7]};
assign rnd5 = {1'b1, rnd[2], 1'b1, rnd[4], 1'b1, rnd[6], 1'b1, rnd[6]};
assign rnd6 = {1'b0, rnd[1], 1'b1, rnd[3], 1'b0, rnd[5], 1'b1, rnd[7]};
assign rnd7 = {1'b0, rnd[2], 1'b1, rnd[4], 1'b0, rnd[6], 1'b1, rnd[5]};
assign rnd8 = {1'b1, rnd[2], 1'b0, rnd[4], 1'b1, rnd[3], 1'b0, rnd[6]};
count8D count1 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[0]), .inD(rnd), .TC(doneC[0]) );
count8D count2 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[1]), .inD(rnd1), .TC(doneC[1]) );
count8D count3 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[2]), .inD(rnd2), .TC(doneC[2]) );
count8D count4 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[3]), .inD(rnd3), .TC(doneC[3]) );
count8D count5 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[4]), .inD(rnd4), .TC(doneC[4]) );
count8D count6 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[5]), .inD(rnd5), .TC(doneC[5]) );
count8D count7 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[6]), .inD(rnd6), .TC(doneC[6]) );
count8D count8 (.clk(clk), .enable(frame), .reset(1'b0), .LD(outOfAR[7]), .inD(rnd7), .TC(doneC[7]) );
redRectangle rect1 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[0]), .allHit(allHit), .returnHit(returnHit[0]), .doneCount(doneC[0]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd78), .redRect(redRect[0]), .outOfAR(outOfAR[0]), .activeRed(activeRed[0]), .resetState(resetState[0]), .startState(startState[0]),.loadTime(loadTime[0]) );
redRectangle rect2 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[1]), .allHit(allHit), .returnHit(returnHit[1]), .doneCount(doneC[1]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd146), .redRect(redRect[1]), .outOfAR(outOfAR[1]), .activeRed(activeRed[1]), .resetState(resetState[1]), .startState(startState[1]),.loadTime(loadTime[1]) );
redRectangle rect3 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[2]), .allHit(allHit), .returnHit(returnHit[2]), .doneCount(doneC[2]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd214), .redRect(redRect[2]), .outOfAR(outOfAR[2]), .activeRed(activeRed[2]), .resetState(resetState[2]), .startState(startState[2]),.loadTime(loadTime[2]) );
redRectangle rect4 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[3]), .allHit(allHit), .returnHit(returnHit[3]), .doneCount(doneC[3]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd282), .redRect(redRect[3]), .outOfAR(outOfAR[3]), .activeRed(activeRed[3]), .resetState(resetState[3]), .startState(startState[3]),.loadTime(loadTime[3]) );
redRectangle rect5 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[4]), .allHit(allHit), .returnHit(returnHit[4]), .doneCount(doneC[4]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd350), .redRect(redRect[4]), .outOfAR(outOfAR[4]), .activeRed(activeRed[4]), .resetState(resetState[4]), .startState(startState[4]),.loadTime(loadTime[4]) );
redRectangle rect6 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[5]), .allHit(allHit), .returnHit(returnHit[5]), .doneCount(doneC[5]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd418), .redRect(redRect[5]), .outOfAR(outOfAR[5]), .activeRed(activeRed[5]), .resetState(resetState[5]), .startState(startState[5]),.loadTime(loadTime[5]) );
redRectangle rect7 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[6]), .allHit(allHit), .returnHit(returnHit[6]), .doneCount(doneC[6]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd486), .redRect(redRect[6]), .outOfAR(outOfAR[6]), .activeRed(activeRed[6]), .resetState(resetState[6]), .startState(startState[6]),.loadTime(loadTime[6]) );
redRectangle rect8 (.clk(clk), .btnC(edgeOut), .frame(frame), .timeOut(timeOut), .syncFlash(syncFlash), .hit(hit[7]), .allHit(allHit), .returnHit(returnHit[7]), .doneCount(doneC[7]), .sw(sw), .hOutQ(hOutQ), .vOutQ(vOutQ), .horizontalPosition(10'd554), .redRect(redRect[7]), .outOfAR(outOfAR[7]), .activeRed(activeRed[7]), .resetState(resetState[7]), .startState(startState[7]),.loadTime(loadTime[7]) );
assign btncFilter = {8{btnC}} & resetState & startState & loadTime;
assign hit[0] = {redRect[0] & greenTagger};
assign hit[1] = {redRect[1] & greenTagger};
assign hit[2] = {redRect[2] & greenTagger};
assign hit[3] = {redRect[3] & greenTagger};
assign hit[4] = {redRect[4] & greenTagger};
assign hit[5] = {redRect[5] & greenTagger};
assign hit[6] = {redRect[6] & greenTagger};
assign hit[7] = {redRect[7] & greenTagger};
assign scoreCounterEnable = { {3'b000, returnHit[0]} + {3'b000, returnHit[1]} + {3'b000, returnHit[2]} + {3'b000, returnHit[3]} + {3'b000, returnHit[4]} +
{3'b000, returnHit[5]} + {3'b000, returnHit[6]} + {3'b000, returnHit[7]} };
assign allHit = {returnHit[0]&returnHit[1]&returnHit[2]&returnHit[3]&returnHit[4]&returnHit[5]&returnHit[6]&returnHit[7]};
assign anyHit = {returnHit[0]|returnHit[1]|returnHit[2]|returnHit[3]|returnHit[4]|returnHit[5]|returnHit[6]|returnHit[7]};
assign redRectPass = (activeRegion & redRect[0])|(activeRegion & redRect[1])|(activeRegion & redRect[2])|(activeRegion & redRect[3])
|(activeRegion & redRect[4])|(activeRegion & redRect[5])|(activeRegion & redRect[6])|(activeRegion & redRect[7]);
assign vgaRed = {4{redRectPass | (activeRegion & goodWall& allHit & syncFlash) }};
assign greenTagger = activeRegion & greenSquareOut;
assign vgaGreen = {4{greenTagger | (activeRegion & goodWall & allHit & syncFlash) }};
assign vgaBlue = {4{(activeRegion & goodWall & ~allHit) |
(activeRegion & goodWall & allHit & syncFlash)}};
count14D countDown (.clk(clk), .enable(frame & (anyHit & scoreCounterEnable < 4'd8)), .LD(startState | resetState), .sw(sw), .outQ(outTime), .TC(timeOut) );
assign selectorIn = {scoreCounterEnable, 1'b0,1'b0,1'b0,1'b0, outTime[13:10],outTime[9:6]};
ringCounter ring (.clk(clk), .digsel(digsel), .sel(ringOut));
selector select (.sel(ringOut), .N(selectorIn), .H(selOut));
hex7seg display (.n(selOut), .enable(1'b1), .seg(seg));
assign led[15:4] = sw[15:4];
assign an[0] = ~ringOut[0];
assign an[1] = ~ringOut[1];
assign an[2] = 1'b1;
assign an[3] = ~ringOut[3];
endmodule | 0 |
6,482 | data/full_repos/permissive/116468596/updownTagger.v | 116,468,596 | updownTagger.v | v | 65 | 92 | [] | [] | [] | [(23, 64)] | null | null | 1: b"%Error: data/full_repos/permissive/116468596/updownTagger.v:55: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b1)) ff_instance_0 (.C(clk), .CE(1'b1), .D(inD[0]), .Q(outQ[0]));\n ^~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n FDRE\n FDRE.v\n FDRE.sv\n obj_dir/FDRE\n obj_dir/FDRE.v\n obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/updownTagger.v:56: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0)) ff_instance_1 (.C(clk), .CE(1'b1), .D(inD[1]), .Q(outQ[1]));\n ^~~~\n%Error: data/full_repos/permissive/116468596/updownTagger.v:57: Cannot find file containing module: 'FDRE'\n FDRE #(.INIT(1'b0)) ff_instance_2 (.C(clk), .CE(1'b1), .D(inD[2]), .Q(outQ[2]));\n ^~~~\n%Error: Exiting due to 3 error(s)\n" | 7,393 | module | module updownTagger(
input clk, twoSec, top, bottom, up, down,
output countUp, countDown, upDownLD, activeGreen
);
wire [14:0] con;
wire [2:0] inD;
wire [2:0] outQ;
assign con[0] = 1'b0;
assign con[1] = ~twoSec & outQ[0];
assign con[2] = twoSec & outQ[0];
assign con[3] = ~bottom & ~up & outQ[1];
assign con[4] = bottom & down & outQ[1];
assign con[5] = bottom & ~down & outQ[1];
assign con[6] = ~bottom & up & outQ[1];
assign con[7] = bottom & up & outQ[1];
assign con[8] = ~top & ~down & outQ[2];
assign con[9] = top & up & outQ[2];
assign con[10] = top & ~up & outQ[2];
assign con[11] = ~top & down & outQ[2];
assign con[12] = top & down & outQ[2];
assign con[13] = up & down & outQ[1];
assign con[14] = up & down & outQ[2];
assign inD[0] = con[1];
assign inD[1] = con[2] | con[3] | con[4] | con[10] | con[11] | con[12];
assign inD[2] = con[5] | con[6] | con[7] | con[8] | con[9];
assign activeGreen = ~outQ[0];
assign upDownLD = outQ[0];
assign countUp = outQ[2] & ~con[9] & ~con[14];
assign countDown = outQ[1] & ~con[4] & ~con[13];
FDRE #(.INIT(1'b1)) ff_instance_0 (.C(clk), .CE(1'b1), .D(inD[0]), .Q(outQ[0]));
FDRE #(.INIT(1'b0)) ff_instance_1 (.C(clk), .CE(1'b1), .D(inD[1]), .Q(outQ[1]));
FDRE #(.INIT(1'b0)) ff_instance_2 (.C(clk), .CE(1'b1), .D(inD[2]), .Q(outQ[2]));
endmodule | module updownTagger(
input clk, twoSec, top, bottom, up, down,
output countUp, countDown, upDownLD, activeGreen
); |
wire [14:0] con;
wire [2:0] inD;
wire [2:0] outQ;
assign con[0] = 1'b0;
assign con[1] = ~twoSec & outQ[0];
assign con[2] = twoSec & outQ[0];
assign con[3] = ~bottom & ~up & outQ[1];
assign con[4] = bottom & down & outQ[1];
assign con[5] = bottom & ~down & outQ[1];
assign con[6] = ~bottom & up & outQ[1];
assign con[7] = bottom & up & outQ[1];
assign con[8] = ~top & ~down & outQ[2];
assign con[9] = top & up & outQ[2];
assign con[10] = top & ~up & outQ[2];
assign con[11] = ~top & down & outQ[2];
assign con[12] = top & down & outQ[2];
assign con[13] = up & down & outQ[1];
assign con[14] = up & down & outQ[2];
assign inD[0] = con[1];
assign inD[1] = con[2] | con[3] | con[4] | con[10] | con[11] | con[12];
assign inD[2] = con[5] | con[6] | con[7] | con[8] | con[9];
assign activeGreen = ~outQ[0];
assign upDownLD = outQ[0];
assign countUp = outQ[2] & ~con[9] & ~con[14];
assign countDown = outQ[1] & ~con[4] & ~con[13];
FDRE #(.INIT(1'b1)) ff_instance_0 (.C(clk), .CE(1'b1), .D(inD[0]), .Q(outQ[0]));
FDRE #(.INIT(1'b0)) ff_instance_1 (.C(clk), .CE(1'b1), .D(inD[1]), .Q(outQ[1]));
FDRE #(.INIT(1'b0)) ff_instance_2 (.C(clk), .CE(1'b1), .D(inD[2]), .Q(outQ[2]));
endmodule | 0 |
6,483 | data/full_repos/permissive/116468596/vgaControlMod.v | 116,468,596 | vgaControlMod.v | v | 54 | 142 | [] | [] | [] | [(22, 53)] | null | null | 1: b"%Error: data/full_repos/permissive/116468596/vgaControlMod.v:36: Cannot find file containing module: 'tenBitCount'\n tenBitCount horizontal (.clk(clk), .enable(enable), .up(up), .down(1'b0), .LD(LD), .reset(hReset), .loadD(loadD), .outQ(hOutQ), .TC(TC));\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/tenBitCount\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/tenBitCount.v\n data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/tenBitCount.sv\n tenBitCount\n tenBitCount.v\n tenBitCount.sv\n obj_dir/tenBitCount\n obj_dir/tenBitCount.v\n obj_dir/tenBitCount.sv\n%Error: data/full_repos/permissive/116468596/vgaControlMod.v:37: Cannot find file containing module: 'tenBitCountY'\n tenBitCountY vertical (.clk(clk), .enable(TC), .up(up), .down(1'b0), .LD(LD), .reset(vReset), .loadD(loadD), .outQ(vOutQ));\n ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 7,394 | module | module vgaControlMod(
input clk, enable, up, LD,
input [9:0] loadD,
output Hsync, Vsync, activeRegion,
output [9:0] hOutQ,
output [9:0] vOutQ,
output goodWall, topWall, bottomWall, leftWall, rightWall,
output greenSquare,
output frame
);
wire topgreenWall;
wire hReset, vReset;
wire TC;
tenBitCount horizontal (.clk(clk), .enable(enable), .up(up), .down(1'b0), .LD(LD), .reset(hReset), .loadD(loadD), .outQ(hOutQ), .TC(TC));
tenBitCountY vertical (.clk(clk), .enable(TC), .up(up), .down(1'b0), .LD(LD), .reset(vReset), .loadD(loadD), .outQ(vOutQ));
assign activeRegion = ( (hOutQ > 10'd0) & (hOutQ < 10'd639) & (vOutQ > 10'd0) & (vOutQ < 10'd479) );
assign hReset = ( hOutQ == 10'd799);
assign vReset = ( vOutQ == 10'd524 & hOutQ == 10'd799);
assign Hsync = (hOutQ < 10'd655) | (hOutQ > 10'd750);
assign Vsync = (vOutQ < 10'd489) | (vOutQ > 10'd490);
assign topWall = ((hOutQ >= 10'd0) & (hOutQ <= 10'd639)) & ((vOutQ >= 10'd0) & (vOutQ <= 10'd8));
assign bottomWall = ((hOutQ >= 10'd0) & (hOutQ <= 10'd639)) & ((vOutQ >= 10'd471) & (vOutQ <= 10'd479));
assign leftWall = ((hOutQ >= 10'd0) & (hOutQ <= 10'd8)) & ((vOutQ >= 10'd0) & (vOutQ <= 10'd479));
assign rightWall = ((hOutQ >= 10'd631) & (hOutQ <= 10'd639)) & ((vOutQ >= 10'd0) & (vOutQ <= 10'd479));
assign goodWall = topWall | bottomWall | leftWall | rightWall;
assign frame = ( (hOutQ == 10'd755) & (vOutQ == 10'd0) );
endmodule | module vgaControlMod(
input clk, enable, up, LD,
input [9:0] loadD,
output Hsync, Vsync, activeRegion,
output [9:0] hOutQ,
output [9:0] vOutQ,
output goodWall, topWall, bottomWall, leftWall, rightWall,
output greenSquare,
output frame
); |
wire topgreenWall;
wire hReset, vReset;
wire TC;
tenBitCount horizontal (.clk(clk), .enable(enable), .up(up), .down(1'b0), .LD(LD), .reset(hReset), .loadD(loadD), .outQ(hOutQ), .TC(TC));
tenBitCountY vertical (.clk(clk), .enable(TC), .up(up), .down(1'b0), .LD(LD), .reset(vReset), .loadD(loadD), .outQ(vOutQ));
assign activeRegion = ( (hOutQ > 10'd0) & (hOutQ < 10'd639) & (vOutQ > 10'd0) & (vOutQ < 10'd479) );
assign hReset = ( hOutQ == 10'd799);
assign vReset = ( vOutQ == 10'd524 & hOutQ == 10'd799);
assign Hsync = (hOutQ < 10'd655) | (hOutQ > 10'd750);
assign Vsync = (vOutQ < 10'd489) | (vOutQ > 10'd490);
assign topWall = ((hOutQ >= 10'd0) & (hOutQ <= 10'd639)) & ((vOutQ >= 10'd0) & (vOutQ <= 10'd8));
assign bottomWall = ((hOutQ >= 10'd0) & (hOutQ <= 10'd639)) & ((vOutQ >= 10'd471) & (vOutQ <= 10'd479));
assign leftWall = ((hOutQ >= 10'd0) & (hOutQ <= 10'd8)) & ((vOutQ >= 10'd0) & (vOutQ <= 10'd479));
assign rightWall = ((hOutQ >= 10'd631) & (hOutQ <= 10'd639)) & ((vOutQ >= 10'd0) & (vOutQ <= 10'd479));
assign goodWall = topWall | bottomWall | leftWall | rightWall;
assign frame = ( (hOutQ == 10'd755) & (vOutQ == 10'd0) );
endmodule | 0 |
6,485 | data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/tb_countdown.v | 116,473,298 | tb_countdown.v | v | 67 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd6 in position 521: invalid continuation byte | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/tb_countdown.v:48: Unsupported: Ignoring delay on this delayed statement.\n #(T/2);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/tb_countdown.v:50: Unsupported: Ignoring delay on this delayed statement.\n #(T/2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/tb_countdown.v:58: Unsupported: Ignoring delay on this delayed statement.\n #(5.1*T);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/tb_countdown.v:60: Unsupported: Ignoring delay on this delayed statement.\n #(T);\n ^\n%Error: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/tb_countdown.v:31: Cannot find file containing module: \'countdown_double\'\ncountdown_double #(.DVSR(5))\n^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new,data/full_repos/permissive/116473298/countdown_double\n data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new,data/full_repos/permissive/116473298/countdown_double.v\n data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new,data/full_repos/permissive/116473298/countdown_double.sv\n countdown_double\n countdown_double.v\n countdown_double.sv\n obj_dir/countdown_double\n obj_dir/countdown_double.v\n obj_dir/countdown_double.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,398 | module | module tb_countdown();
reg clk,clr,en;
reg [3:0] dh;
reg [3:0] dl;
wire tick;
wire [3:0] qh;
wire [3:0] ql;
countdown_double #(.DVSR(5))
tb_countdown_double
(
.clk(clk),
.clr(clr),
.en(en),
.dh(dh),
.dl(dl),
.tick(tick),
.qh(qh),
.ql(ql)
);
parameter T = 4;
always begin
clk = 1'b1;
#(T/2);
clk = 1'b0;
#(T/2);
end
initial begin
clr = 1'b1;
en = 1'b0;
dh = 4'h5;
dl = 4'h0;
#(5.1*T);
en = 1'b1;
#(T);
clr = 1'b0;
end
endmodule | module tb_countdown(); |
reg clk,clr,en;
reg [3:0] dh;
reg [3:0] dl;
wire tick;
wire [3:0] qh;
wire [3:0] ql;
countdown_double #(.DVSR(5))
tb_countdown_double
(
.clk(clk),
.clr(clr),
.en(en),
.dh(dh),
.dl(dl),
.tick(tick),
.qh(qh),
.ql(ql)
);
parameter T = 4;
always begin
clk = 1'b1;
#(T/2);
clk = 1'b0;
#(T/2);
end
initial begin
clr = 1'b1;
en = 1'b0;
dh = 4'h5;
dl = 4'h0;
#(5.1*T);
en = 1'b1;
#(T);
clr = 1'b0;
end
endmodule | 6 |
6,486 | data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v | 116,473,298 | testbench.v | v | 84 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc6 in position 522: invalid continuation byte | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:55: Unsupported: Ignoring delay on this delayed statement.\n #(T/2);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n #(T/2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:64: Unsupported: Ignoring delay on this delayed statement.\n #(1.5*T);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:66: Unsupported: Ignoring delay on this delayed statement.\n #(T);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:68: Unsupported: Ignoring delay on this delayed statement.\n #(19.4*T);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:70: Unsupported: Ignoring delay on this delayed statement.\n #(100*T);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:72: Unsupported: Ignoring delay on this delayed statement.\n #(100*T);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:74: Unsupported: Ignoring delay on this delayed statement.\n #(100*T);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:76: Unsupported: Ignoring delay on this delayed statement.\n #(100*T);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:78: Unsupported: Ignoring delay on this delayed statement.\n #(500*T);\n ^\n%Error: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:34: Cannot find file containing module: \'Traffic_lights_ce\'\nTraffic_lights_ce #(.DVSR(5))\n^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new,data/full_repos/permissive/116473298/Traffic_lights_ce\n data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new,data/full_repos/permissive/116473298/Traffic_lights_ce.v\n data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new,data/full_repos/permissive/116473298/Traffic_lights_ce.sv\n Traffic_lights_ce\n Traffic_lights_ce.v\n Traffic_lights_ce.sv\n obj_dir/Traffic_lights_ce\n obj_dir/Traffic_lights_ce.v\n obj_dir/Traffic_lights_ce.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,399 | module | module testbench();
reg clk;
reg reset;
reg go;
reg emergency;
wire [7:0] sseg;
wire [3:0] an;
wire redout_2,yellowout_2,greenout_2;
wire redout_1,yellowout_1,greenout_1;
wire s_tick;
Traffic_lights_ce #(.DVSR(5))
U_Traffic_lights_ce
(
.clk(clk),
.reset(reset),
.go(go),
.emergency(emergency),
.sseg(sseg),
.an(an),
.redout_2(redout_2),
.yellowout_2(yellowout_2),
.greenout_2(greenout_2),
.redout_1(redout_1),
.yellowout_1(yellowout_1),
.greenout_1(greenout_1)
);
parameter T = 4;
always begin
clk = 1'b1;
#(T/2);
clk = 1'b0;
#(T/2);
end
initial begin
reset = 1'b1;
emergency = 1'b0;
go = 1'b0;
#(1.5*T);
reset = 1'b0;
#(T);
go = 1'b1;
#(19.4*T);
emergency = 1'b0;
#(100*T);
emergency = 1'b0;
#(100*T);
go = 1'b0;
#(100*T);
go = 1'b1;
#(100*T);
emergency = 1'b1;
#(500*T);
emergency = 1'b0;
end
endmodule | module testbench(); |
reg clk;
reg reset;
reg go;
reg emergency;
wire [7:0] sseg;
wire [3:0] an;
wire redout_2,yellowout_2,greenout_2;
wire redout_1,yellowout_1,greenout_1;
wire s_tick;
Traffic_lights_ce #(.DVSR(5))
U_Traffic_lights_ce
(
.clk(clk),
.reset(reset),
.go(go),
.emergency(emergency),
.sseg(sseg),
.an(an),
.redout_2(redout_2),
.yellowout_2(yellowout_2),
.greenout_2(greenout_2),
.redout_1(redout_1),
.yellowout_1(yellowout_1),
.greenout_1(greenout_1)
);
parameter T = 4;
always begin
clk = 1'b1;
#(T/2);
clk = 1'b0;
#(T/2);
end
initial begin
reset = 1'b1;
emergency = 1'b0;
go = 1'b0;
#(1.5*T);
reset = 1'b0;
#(T);
go = 1'b1;
#(19.4*T);
emergency = 1'b0;
#(100*T);
emergency = 1'b0;
#(100*T);
go = 1'b0;
#(100*T);
go = 1'b1;
#(100*T);
emergency = 1'b1;
#(500*T);
emergency = 1'b0;
end
endmodule | 6 |
6,487 | data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sources_1/new/blink.v | 116,473,298 | blink.v | v | 57 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbc in position 683: invalid start byte | data/verilator_xmls/bc39ccd1-2481-49f6-927b-16785f42ef59.xml | null | 7,400 | module | module blink#(parameter DVSR = 10000_0000 - 1)
(
input clk,reset,
input en,
output blink
);
reg [29:0] ms_reg;
wire [29:0] ms_next;
reg blink_reg;
reg blink_next;
always@(posedge clk) begin
ms_reg <= ms_next;
blink_reg <= blink_next;
end
assign ms_next = (reset||(ms_reg == DVSR && en)) ? 0 :
(en) ? ms_reg + 1 :
ms_reg;
always@(*) begin
if(reset||~en) begin
blink_next = 1'b0;
end else if(en && (ms_reg == DVSR)) begin
blink_next = ~blink_reg;
end
end
assign blink = blink_reg;
endmodule | module blink#(parameter DVSR = 10000_0000 - 1)
(
input clk,reset,
input en,
output blink
); |
reg [29:0] ms_reg;
wire [29:0] ms_next;
reg blink_reg;
reg blink_next;
always@(posedge clk) begin
ms_reg <= ms_next;
blink_reg <= blink_next;
end
assign ms_next = (reset||(ms_reg == DVSR && en)) ? 0 :
(en) ? ms_reg + 1 :
ms_reg;
always@(*) begin
if(reset||~en) begin
blink_next = 1'b0;
end else if(en && (ms_reg == DVSR)) begin
blink_next = ~blink_reg;
end
end
assign blink = blink_reg;
endmodule | 6 |
6,489 | data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sources_1/new/countdown_double.v | 116,473,298 | countdown_double.v | v | 97 | 87 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd6 in position 604: invalid continuation byte | data/verilator_xmls/c238e1ea-3bc7-4356-bce4-85d23a38ccad.xml | null | 7,402 | module | module countdown_double
#(parameter DVSR = 10000_0000 - 1,dh_min = 0,dl_min = 1)
(
input wire clk,clr,en,
input wire [3:0] dh,
input wire [3:0] dl,
output wire tick,
output wire [3:0] qh,
output wire [3:0] ql
);
reg [29:0] ms_reg;
wire [29:0] ms_next;
wire ms_tick;
reg [3:0] dh_reg,dl_reg;
reg [3:0] dh_next,dl_next;
wire pe;
always@(posedge clk) begin
dh_reg <= dh_next;
dl_reg <= dl_next;
ms_reg <= ms_next;
end
assign ms_next = (clr||(ms_reg == DVSR && en)) ? 0 :
(en) ? ms_reg + 1 :
ms_reg;
assign ms_tick = (en)&&(ms_reg == DVSR) ? 1'b1 : 1'b0;
always@(*) begin
dh_next = dh_reg;
dl_next = dl_reg;
if(clr) begin
dh_next = dh;
dl_next = dl;
end else if(ms_tick) begin
if(dh_reg == dh_min && dl_reg == dl_min) begin
dh_next = dh;
dl_next = dl;
end else if(dl_reg != 0) begin
dl_next = dl_reg - 1;
end else begin
dl_next = 4'h9;
if(dh_reg != 0) begin
dh_next = dh_reg - 1;
end else begin
dl_next = dl;
dh_next = dh;
end
end
end
end
assign qh = dh_reg;
assign ql = dl_reg;
assign tick = (dl_reg==dl_min && dh_reg==dh_min)?1'b1:1'b0;
reg delay_reg;
always@(posedge clk,posedge clr) begin
if(clr) begin
delay_reg <= 1'b0;
end else begin
delay_reg <= tick;
end
end
assign pe = (~delay_reg & tick)||clr;
endmodule | module countdown_double
#(parameter DVSR = 10000_0000 - 1,dh_min = 0,dl_min = 1)
(
input wire clk,clr,en,
input wire [3:0] dh,
input wire [3:0] dl,
output wire tick,
output wire [3:0] qh,
output wire [3:0] ql
); |
reg [29:0] ms_reg;
wire [29:0] ms_next;
wire ms_tick;
reg [3:0] dh_reg,dl_reg;
reg [3:0] dh_next,dl_next;
wire pe;
always@(posedge clk) begin
dh_reg <= dh_next;
dl_reg <= dl_next;
ms_reg <= ms_next;
end
assign ms_next = (clr||(ms_reg == DVSR && en)) ? 0 :
(en) ? ms_reg + 1 :
ms_reg;
assign ms_tick = (en)&&(ms_reg == DVSR) ? 1'b1 : 1'b0;
always@(*) begin
dh_next = dh_reg;
dl_next = dl_reg;
if(clr) begin
dh_next = dh;
dl_next = dl;
end else if(ms_tick) begin
if(dh_reg == dh_min && dl_reg == dl_min) begin
dh_next = dh;
dl_next = dl;
end else if(dl_reg != 0) begin
dl_next = dl_reg - 1;
end else begin
dl_next = 4'h9;
if(dh_reg != 0) begin
dh_next = dh_reg - 1;
end else begin
dl_next = dl;
dh_next = dh;
end
end
end
end
assign qh = dh_reg;
assign ql = dl_reg;
assign tick = (dl_reg==dl_min && dh_reg==dh_min)?1'b1:1'b0;
reg delay_reg;
always@(posedge clk,posedge clr) begin
if(clr) begin
delay_reg <= 1'b0;
end else begin
delay_reg <= tick;
end
end
assign pe = (~delay_reg & tick)||clr;
endmodule | 6 |
6,491 | data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sources_1/new/edge_trigger.v | 116,473,298 | edge_trigger.v | v | 42 | 83 | [] | [] | [] | [(23, 41)] | null | data/verilator_xmls/de8d163a-0727-4c97-ad2b-049921aaebc0.xml | null | 7,404 | module | module edge_trigger
(
input wire clk,reset,
input wire level,
output wire tick
);
reg delay_reg;
always@(posedge clk,posedge reset) begin
if(reset) begin
delay_reg <= 1'b0;
end else begin
delay_reg <= level;
end
end
assign tick = ~delay_reg & level;
endmodule | module edge_trigger
(
input wire clk,reset,
input wire level,
output wire tick
); |
reg delay_reg;
always@(posedge clk,posedge reset) begin
if(reset) begin
delay_reg <= 1'b0;
end else begin
delay_reg <= level;
end
end
assign tick = ~delay_reg & level;
endmodule | 6 |
6,492 | data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sources_1/new/emergency.v | 116,473,298 | emergency.v | v | 38 | 88 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xba in position 734: invalid start byte | data/verilator_xmls/b228400c-f46e-4641-9cf5-d36e5ba23cd5.xml | null | 7,405 | module | module emergency
(
input emergency,
input [3:0] counterh,counterl,
input [2:0] lights_in,
output [3:0] qh,ql,
output [2:0] lights_out
);
parameter [3:0] time_emergency = 4'h8;
parameter [2:0] lights_emergency = 3'b100;
assign {qh,ql} = emergency ? {time_emergency,time_emergency} : {counterh,counterl};
assign {lights_out} = emergency ? {lights_emergency} : {lights_in};
endmodule | module emergency
(
input emergency,
input [3:0] counterh,counterl,
input [2:0] lights_in,
output [3:0] qh,ql,
output [2:0] lights_out
); |
parameter [3:0] time_emergency = 4'h8;
parameter [2:0] lights_emergency = 3'b100;
assign {qh,ql} = emergency ? {time_emergency,time_emergency} : {counterh,counterl};
assign {lights_out} = emergency ? {lights_emergency} : {lights_in};
endmodule | 6 |
6,496 | data/full_repos/permissive/116476954/alu.v | 116,476,954 | alu.v | v | 66 | 82 | [] | [] | [] | [(1, 65)] | null | data/verilator_xmls/3590ba3b-39fc-451a-9e32-13307cd88a55.xml | null | 7,410 | module | module alu (aclk,mdat,acc_out, opcd, alu_out, zr);
input aclk;
input [7:0] mdat;
input [7:0] acc_out;
input [2:0] opcd;
output [7:0] alu_out;
output zr;
reg [7:0] a;
wire [7:0] alu_out;
wire zr;
always @ ( posedge aclk ) begin
case (opcd)
3'b000 : begin
a <= acc_out;
end
3'b001 : begin
a <=acc_out;
end
3'b010 : begin
a <= {mdat + acc_out};
end
3'b011 : begin
a <= {mdat & acc_out};
end
3'b100 : begin
a <= {mdat ^ acc_out};
end
3'b101 : begin
a <= mdat;
end
3'b110 : begin
a <= acc_out;
end
3'b111 : begin
a <= acc_out;
end
default : begin
a <= 0;
end
endcase
end
assign alu_out = a;
assign zr = &(a);
endmodule | module alu (aclk,mdat,acc_out, opcd, alu_out, zr); |
input aclk;
input [7:0] mdat;
input [7:0] acc_out;
input [2:0] opcd;
output [7:0] alu_out;
output zr;
reg [7:0] a;
wire [7:0] alu_out;
wire zr;
always @ ( posedge aclk ) begin
case (opcd)
3'b000 : begin
a <= acc_out;
end
3'b001 : begin
a <=acc_out;
end
3'b010 : begin
a <= {mdat + acc_out};
end
3'b011 : begin
a <= {mdat & acc_out};
end
3'b100 : begin
a <= {mdat ^ acc_out};
end
3'b101 : begin
a <= mdat;
end
3'b110 : begin
a <= acc_out;
end
3'b111 : begin
a <= acc_out;
end
default : begin
a <= 0;
end
endcase
end
assign alu_out = a;
assign zr = &(a);
endmodule | 1 |
6,500 | data/full_repos/permissive/116476954/iobuffer.v | 116,476,954 | iobuffer.v | v | 17 | 44 | [] | [] | [] | [(1, 16)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/116476954/iobuffer.v:13: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'alu_out\' generates 8 bits.\n : ... In instance iobuffer\nassign mdat = (en1) ? alu_out : \'hzz ;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/116476954/iobuffer.v:13: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance iobuffer\nassign mdat = (en1) ? alu_out : \'hzz ;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 7,414 | module | module iobuffer(clk2,mrd,fch,alu_out,mdat);
input clk2,mrd,fch;
input [7:0] alu_out;
output [7:0] mdat;
wire en, en1;
assign en = mrd || fch || clk2;
assign en1 = ~en;
assign mdat = (en1) ? alu_out : 'hzz ;
endmodule | module iobuffer(clk2,mrd,fch,alu_out,mdat); |
input clk2,mrd,fch;
input [7:0] alu_out;
output [7:0] mdat;
wire en, en1;
assign en = mrd || fch || clk2;
assign en1 = ~en;
assign mdat = (en1) ? alu_out : 'hzz ;
endmodule | 1 |
6,502 | data/full_repos/permissive/116476954/mux.v | 116,476,954 | mux.v | v | 20 | 39 | [] | [] | [] | [(1, 19)] | null | data/verilator_xmls/b0c0dba9-b749-4fe1-b37a-f54a859e01f2.xml | null | 7,416 | module | module mux2_1(adir, adpc, fch, admem);
input [4:0] adir;
input [4:0] adpc;
input fch;
output [4:0] admem;
reg [4:0] admem;
always @ (fch,adpc,adir) begin
case (fch)
1'b1 : admem = adpc;
1'b0 : admem = adir;
endcase
end
endmodule | module mux2_1(adir, adpc, fch, admem); |
input [4:0] adir;
input [4:0] adpc;
input fch;
output [4:0] admem;
reg [4:0] admem;
always @ (fch,adpc,adir) begin
case (fch)
1'b1 : admem = adpc;
1'b0 : admem = adir;
endcase
end
endmodule | 1 |
6,505 | data/full_repos/permissive/116476954/topmodule.v | 116,476,954 | topmodule.v | v | 53 | 159 | [] | [] | [] | [(1, 51)] | null | null | 1: b"%Error: data/full_repos/permissive/116476954/topmodule.v:32: Cannot find file containing module: 'iobuffer'\niobuffer io1( .clk2(clk2), .mrd(mrd) , .fch(fch), .alu_out(alu_out), .mdat(mdat));\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116476954,data/full_repos/permissive/116476954/iobuffer\n data/full_repos/permissive/116476954,data/full_repos/permissive/116476954/iobuffer.v\n data/full_repos/permissive/116476954,data/full_repos/permissive/116476954/iobuffer.sv\n iobuffer\n iobuffer.v\n iobuffer.sv\n obj_dir/iobuffer\n obj_dir/iobuffer.v\n obj_dir/iobuffer.sv\n%Error: data/full_repos/permissive/116476954/topmodule.v:34: Cannot find file containing module: 'accum'\naccum accum1( .clk(clk1), .rst(rst), .alu_out(alu_out), .ldac(ldac) , .acc_out(acc_out));\n^~~~~\n%Error: data/full_repos/permissive/116476954/topmodule.v:36: Cannot find file containing module: 'clkgen'\nclkgen clkgen1( .clk(clk), .rstreq(rstreq), .clk1(clk1), .clk2(clk2), .fch(fch), .rst(rst));\n^~~~~~\n%Error: data/full_repos/permissive/116476954/topmodule.v:38: Cannot find file containing module: 'decode'\ndecode decoder1( .clk1(clk1),.clk2(clk2),.fch(fch), .rst(rst), .opcd(opcd),.ldir(ldir),.ldac(ldac),.mrd(mrd),.mwr(mwr),.ldpc(ldpc),.pclk(pclk),.aclk(aclk));\n^~~~~~\n%Error: data/full_repos/permissive/116476954/topmodule.v:40: Cannot find file containing module: 'instreg'\ninstreg instreg1( .clk(clk1) , .rst(rst), .ldir(ldir), .mdat(mdat), .adir(adir), .opcd(opcd));\n^~~~~~~\n%Error: data/full_repos/permissive/116476954/topmodule.v:42: Cannot find file containing module: 'alu'\nalu alu1( .aclk(aclk) , .mdat(mdat) , .acc_out(acc_out) , .opcd(opcd) , .alu_out(alu_out) , .zr(zr) );\n^~~\n%Error: data/full_repos/permissive/116476954/topmodule.v:44: Cannot find file containing module: 'memory'\nmemory mem1(.rst(rst) , .mrd(mrd) , .mwr(mwr) , .ewr(ewr), .mad(admem), .ead(ead), .edat(edat), .mdat(mdat));\n^~~~~~\n%Error: data/full_repos/permissive/116476954/topmodule.v:46: Cannot find file containing module: 'pc'\npc pc1( .pclk(pclk), .rst(rst), .adir(adir), .ldpc(ldpc), .adpc(adpc));\n^~\n%Error: data/full_repos/permissive/116476954/topmodule.v:48: Cannot find file containing module: 'mux2_1'\nmux2_1 mux2( .adir(adir), .adpc(adpc), .fch(fch) , .admem(admem));\n^~~~~~\n%Error: Exiting due to 9 error(s)\n" | 7,419 | module | module topmodule(clk,rstreq,ewr,ead,edat,zr);
input clk;
input rstreq;
input ewr;
input [4:0] ead;
input [7:0] edat;
output zr;
wire zr;
wire clk1;
wire clk2;
wire fch;
wire rst;
wire [7:0] alu_out;
wire [7:0] acc_out;
wire ldac;
wire ldir;
wire [7:0] mdat;
wire [4:0] adir;
wire [2:0] opcd;
wire [4:0] adpc;
wire [4:0] admem;
wire ldpc;
wire pclk;
wire aclk;
wire mrd;
wire mwr;
iobuffer io1( .clk2(clk2), .mrd(mrd) , .fch(fch), .alu_out(alu_out), .mdat(mdat));
accum accum1( .clk(clk1), .rst(rst), .alu_out(alu_out), .ldac(ldac) , .acc_out(acc_out));
clkgen clkgen1( .clk(clk), .rstreq(rstreq), .clk1(clk1), .clk2(clk2), .fch(fch), .rst(rst));
decode decoder1( .clk1(clk1),.clk2(clk2),.fch(fch), .rst(rst), .opcd(opcd),.ldir(ldir),.ldac(ldac),.mrd(mrd),.mwr(mwr),.ldpc(ldpc),.pclk(pclk),.aclk(aclk));
instreg instreg1( .clk(clk1) , .rst(rst), .ldir(ldir), .mdat(mdat), .adir(adir), .opcd(opcd));
alu alu1( .aclk(aclk) , .mdat(mdat) , .acc_out(acc_out) , .opcd(opcd) , .alu_out(alu_out) , .zr(zr) );
memory mem1(.rst(rst) , .mrd(mrd) , .mwr(mwr) , .ewr(ewr), .mad(admem), .ead(ead), .edat(edat), .mdat(mdat));
pc pc1( .pclk(pclk), .rst(rst), .adir(adir), .ldpc(ldpc), .adpc(adpc));
mux2_1 mux2( .adir(adir), .adpc(adpc), .fch(fch) , .admem(admem));
endmodule | module topmodule(clk,rstreq,ewr,ead,edat,zr); |
input clk;
input rstreq;
input ewr;
input [4:0] ead;
input [7:0] edat;
output zr;
wire zr;
wire clk1;
wire clk2;
wire fch;
wire rst;
wire [7:0] alu_out;
wire [7:0] acc_out;
wire ldac;
wire ldir;
wire [7:0] mdat;
wire [4:0] adir;
wire [2:0] opcd;
wire [4:0] adpc;
wire [4:0] admem;
wire ldpc;
wire pclk;
wire aclk;
wire mrd;
wire mwr;
iobuffer io1( .clk2(clk2), .mrd(mrd) , .fch(fch), .alu_out(alu_out), .mdat(mdat));
accum accum1( .clk(clk1), .rst(rst), .alu_out(alu_out), .ldac(ldac) , .acc_out(acc_out));
clkgen clkgen1( .clk(clk), .rstreq(rstreq), .clk1(clk1), .clk2(clk2), .fch(fch), .rst(rst));
decode decoder1( .clk1(clk1),.clk2(clk2),.fch(fch), .rst(rst), .opcd(opcd),.ldir(ldir),.ldac(ldac),.mrd(mrd),.mwr(mwr),.ldpc(ldpc),.pclk(pclk),.aclk(aclk));
instreg instreg1( .clk(clk1) , .rst(rst), .ldir(ldir), .mdat(mdat), .adir(adir), .opcd(opcd));
alu alu1( .aclk(aclk) , .mdat(mdat) , .acc_out(acc_out) , .opcd(opcd) , .alu_out(alu_out) , .zr(zr) );
memory mem1(.rst(rst) , .mrd(mrd) , .mwr(mwr) , .ewr(ewr), .mad(admem), .ead(ead), .edat(edat), .mdat(mdat));
pc pc1( .pclk(pclk), .rst(rst), .adir(adir), .ldpc(ldpc), .adpc(adpc));
mux2_1 mux2( .adir(adir), .adpc(adpc), .fch(fch) , .admem(admem));
endmodule | 1 |
6,507 | data/full_repos/permissive/116478018/RFIFO_TB.v | 116,478,018 | RFIFO_TB.v | v | 98 | 232 | [] | [] | [] | null | line:68: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116478018/RFIFO_TB.v:15: Unsupported: Ignoring delay on this delayed statement.\n #(DELAY/2);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116478018/RFIFO_TB.v:17: Unsupported: Ignoring delay on this delayed statement.\n #(DELAY/2);\n ^\n%Error: data/full_repos/permissive/116478018/RFIFO_TB.v:33: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/116478018/RFIFO_TB.v:41: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/116478018/RFIFO_TB.v:50: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/116478018/RFIFO_TB.v:57: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/116478018/RFIFO_TB.v:62: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/116478018/RFIFO_TB.v:70: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/116478018/RFIFO_TB.v:77: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116478018/RFIFO_TB.v:93: Unsupported: Ignoring delay on this delayed statement.\n #1000 $finish;\n ^\n%Error: data/full_repos/permissive/116478018/RFIFO_TB.v:96: Unsupported or unknown PLI call: $monitor\n$monitor("Values of clock=%b, resetn=%b, write_enb=%b, read_enb=%b, lfd_state=%b, soft_reset=%b, data_in=%b, full=%b, empty=%b, data_out=%b", clock, resetn, write_enb, read_enb, lfd_state, soft_reset, data_in,full, empty, data_out);\n^~~~~~~~\n%Error: Exiting due to 8 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,422 | module | module router_fifo_tb();
parameter DELAY=10;
parameter DEPTH=16, WIDTH=9, ADD_SIZE=5;
reg clock, resetn, write_enb, read_enb, lfd_state, soft_reset;
reg [7:0]data_in;
wire full, empty;
wire [7:0]data_out;
integer i;
router_fifo DUT(clock, resetn, write_enb, read_enb, lfd_state, soft_reset, data_in, full, empty, data_out);
always
begin
clock=1'b0;
#(DELAY/2);
clock=1'b1;
#(DELAY/2);
end
task initialize;
begin
write_enb =1'b0;
soft_reset=1'b0;
read_enb =1'b0;
data_in=0;
lfd_state = 1'b0;
end
endtask
task rst;
begin
resetn=1'b0;
@(negedge clock);
resetn=1'b1;
end
endtask
task soft_rst;
begin
soft_reset=1'b1;
@(negedge clock);
soft_reset=1'b0;
end
endtask
task pkt_gen;
reg [7:0]header, payload_data, parity;
reg [5:0]payloadlen;
begin
@(negedge clock);
payloadlen=8;
header={payloadlen,2'b10};
data_in=header;
lfd_state= 1'b1;
for(i=0;i<payloadlen;i=i+1)
begin
@(negedge clock);
payload_data={$random}%256;
data_in=payload_data;
lfd_state=1'b0;
end
@(negedge clock);
parity={$random}%256;
data_in=parity;
end
endtask
task read();
begin
@(negedge clock);
read_enb =1'b1;
end
endtask
task write(input a);
begin
@(negedge clock);
write_enb=a;
end
endtask
initial
begin
initialize;
rst;
repeat(9)
write(1);
pkt_gen;
write(0);
read;
soft_rst;
#1000 $finish;
end
initial
$monitor("Values of clock=%b, resetn=%b, write_enb=%b, read_enb=%b, lfd_state=%b, soft_reset=%b, data_in=%b, full=%b, empty=%b, data_out=%b", clock, resetn, write_enb, read_enb, lfd_state, soft_reset, data_in,full, empty, data_out);
endmodule | module router_fifo_tb(); |
parameter DELAY=10;
parameter DEPTH=16, WIDTH=9, ADD_SIZE=5;
reg clock, resetn, write_enb, read_enb, lfd_state, soft_reset;
reg [7:0]data_in;
wire full, empty;
wire [7:0]data_out;
integer i;
router_fifo DUT(clock, resetn, write_enb, read_enb, lfd_state, soft_reset, data_in, full, empty, data_out);
always
begin
clock=1'b0;
#(DELAY/2);
clock=1'b1;
#(DELAY/2);
end
task initialize;
begin
write_enb =1'b0;
soft_reset=1'b0;
read_enb =1'b0;
data_in=0;
lfd_state = 1'b0;
end
endtask
task rst;
begin
resetn=1'b0;
@(negedge clock);
resetn=1'b1;
end
endtask
task soft_rst;
begin
soft_reset=1'b1;
@(negedge clock);
soft_reset=1'b0;
end
endtask
task pkt_gen;
reg [7:0]header, payload_data, parity;
reg [5:0]payloadlen;
begin
@(negedge clock);
payloadlen=8;
header={payloadlen,2'b10};
data_in=header;
lfd_state= 1'b1;
for(i=0;i<payloadlen;i=i+1)
begin
@(negedge clock);
payload_data={$random}%256;
data_in=payload_data;
lfd_state=1'b0;
end
@(negedge clock);
parity={$random}%256;
data_in=parity;
end
endtask
task read();
begin
@(negedge clock);
read_enb =1'b1;
end
endtask
task write(input a);
begin
@(negedge clock);
write_enb=a;
end
endtask
initial
begin
initialize;
rst;
repeat(9)
write(1);
pkt_gen;
write(0);
read;
soft_rst;
#1000 $finish;
end
initial
$monitor("Values of clock=%b, resetn=%b, write_enb=%b, read_enb=%b, lfd_state=%b, soft_reset=%b, data_in=%b, full=%b, empty=%b, data_out=%b", clock, resetn, write_enb, read_enb, lfd_state, soft_reset, data_in,full, empty, data_out);
endmodule | 1 |
6,508 | data/full_repos/permissive/116478018/RFSM.v | 116,478,018 | RFSM.v | v | 132 | 183 | [] | [] | [] | [(1, 131)] | null | data/verilator_xmls/61ba8047-4b3d-43c9-b8f9-ef34d990d984.xml | null | 7,423 | module | module router_fsm
(input clock, resetn, pkt_valid,
input [1:0]data_in,
input fifo_full, fifo_empty_0, fifo_empty_1, fifo_empty_2, soft_reset_0, soft_reset_1, soft_reset_2, parity_done, low_packet_valid,
output write_enb_reg, detect_add, ld_state, laf_state, lfd_state, full_state, rst_int_reg, busy);
parameter
DECODE_ADDRESS= 3'b000,
LOAD_FIRST_DATA=3'b001,
LOAD_DATA=3'b010,
LOAD_PARITY=3'b011,
FIFO_FULL_STATE=3'b100,
LOAD_AFTER_FULL=3'b101,
WAIT_TILL_EMPTY=3'b110,
CHECK_PARITY_ERROR=3'b111;
reg [2:0]state, next_state;
always@(posedge clock)
begin
if(~resetn)
state<= DECODE_ADDRESS;
else
state<= next_state;
end
always@*
begin
next_state= DECODE_ADDRESS;
case(state)
DECODE_ADDRESS : if((pkt_valid && (data_in[1:0]==2'b00)) && fifo_empty_0 || (pkt_valid && (data_in[1:0]==2'b01) && fifo_empty_1)||(pkt_valid && (data_in[1:0]==2'b10) && fifo_empty_2))
next_state= LOAD_FIRST_DATA;
else if((pkt_valid &&(data_in[1:0]==2'b00)) && ~fifo_empty_0 ||
(pkt_valid &&(data_in[1:0]==2'b01)&& ~fifo_empty_1) ||
(pkt_valid&&(data_in[1:0]==2'b10)&& ~fifo_empty_2))
next_state= WAIT_TILL_EMPTY;
else
next_state=DECODE_ADDRESS;
LOAD_FIRST_DATA: next_state= LOAD_DATA;
LOAD_DATA: if(fifo_full==1)
next_state=FIFO_FULL_STATE;
else if(fifo_full==0 && pkt_valid==0)
next_state=LOAD_PARITY;
else
next_state= LOAD_DATA;
LOAD_PARITY: next_state= CHECK_PARITY_ERROR;
FIFO_FULL_STATE: if(fifo_full==0)
next_state= LOAD_AFTER_FULL;
else
next_state=FIFO_FULL_STATE;
LOAD_AFTER_FULL :if(parity_done==0 && low_packet_valid==0)
next_state= LOAD_DATA;
else if(parity_done==0 && low_packet_valid==1)
next_state= LOAD_PARITY;
else if(parity_done==1)
next_state= DECODE_ADDRESS;
WAIT_TILL_EMPTY :
begin
next_state = DECODE_ADDRESS;
case(data_in)
2'b00 :begin
if(soft_reset_0)
next_state = DECODE_ADDRESS;
else if(~fifo_empty_0)
next_state = WAIT_TILL_EMPTY;
else if(fifo_empty_0)
next_state = LOAD_FIRST_DATA;
end
2'b01 :begin
if(soft_reset_1)
next_state = DECODE_ADDRESS;
else if(~fifo_empty_1)
next_state = WAIT_TILL_EMPTY;
else if(fifo_empty_1)
next_state = LOAD_FIRST_DATA;
end
2'b10 :begin
if(soft_reset_2)
next_state = DECODE_ADDRESS;
else if(~fifo_empty_2)
next_state = WAIT_TILL_EMPTY;
else if(fifo_empty_2)
next_state = LOAD_FIRST_DATA;
end
endcase
end
CHECK_PARITY_ERROR:if (fifo_full)
next_state= FIFO_FULL_STATE;
else
next_state=DECODE_ADDRESS;
endcase
end
assign detect_add =(state==DECODE_ADDRESS)?1:0;
assign rst_int_reg=(state==CHECK_PARITY_ERROR)?1:0;
assign lfd_state=(state==LOAD_FIRST_DATA)?1:0;
assign busy=(state==LOAD_PARITY || state== LOAD_AFTER_FULL || state==CHECK_PARITY_ERROR || state==LOAD_FIRST_DATA || state==FIFO_FULL_STATE || state== WAIT_TILL_EMPTY)?1:0;
assign write_enb_reg=(state==LOAD_PARITY || state==LOAD_AFTER_FULL || state==LOAD_DATA)?1:0;
assign laf_state=(state==LOAD_AFTER_FULL)?1:0;
assign full_state=(state==FIFO_FULL_STATE)?1:0;
assign ld_state=(state==LOAD_DATA);
endmodule | module router_fsm
(input clock, resetn, pkt_valid,
input [1:0]data_in,
input fifo_full, fifo_empty_0, fifo_empty_1, fifo_empty_2, soft_reset_0, soft_reset_1, soft_reset_2, parity_done, low_packet_valid,
output write_enb_reg, detect_add, ld_state, laf_state, lfd_state, full_state, rst_int_reg, busy); |
parameter
DECODE_ADDRESS= 3'b000,
LOAD_FIRST_DATA=3'b001,
LOAD_DATA=3'b010,
LOAD_PARITY=3'b011,
FIFO_FULL_STATE=3'b100,
LOAD_AFTER_FULL=3'b101,
WAIT_TILL_EMPTY=3'b110,
CHECK_PARITY_ERROR=3'b111;
reg [2:0]state, next_state;
always@(posedge clock)
begin
if(~resetn)
state<= DECODE_ADDRESS;
else
state<= next_state;
end
always@*
begin
next_state= DECODE_ADDRESS;
case(state)
DECODE_ADDRESS : if((pkt_valid && (data_in[1:0]==2'b00)) && fifo_empty_0 || (pkt_valid && (data_in[1:0]==2'b01) && fifo_empty_1)||(pkt_valid && (data_in[1:0]==2'b10) && fifo_empty_2))
next_state= LOAD_FIRST_DATA;
else if((pkt_valid &&(data_in[1:0]==2'b00)) && ~fifo_empty_0 ||
(pkt_valid &&(data_in[1:0]==2'b01)&& ~fifo_empty_1) ||
(pkt_valid&&(data_in[1:0]==2'b10)&& ~fifo_empty_2))
next_state= WAIT_TILL_EMPTY;
else
next_state=DECODE_ADDRESS;
LOAD_FIRST_DATA: next_state= LOAD_DATA;
LOAD_DATA: if(fifo_full==1)
next_state=FIFO_FULL_STATE;
else if(fifo_full==0 && pkt_valid==0)
next_state=LOAD_PARITY;
else
next_state= LOAD_DATA;
LOAD_PARITY: next_state= CHECK_PARITY_ERROR;
FIFO_FULL_STATE: if(fifo_full==0)
next_state= LOAD_AFTER_FULL;
else
next_state=FIFO_FULL_STATE;
LOAD_AFTER_FULL :if(parity_done==0 && low_packet_valid==0)
next_state= LOAD_DATA;
else if(parity_done==0 && low_packet_valid==1)
next_state= LOAD_PARITY;
else if(parity_done==1)
next_state= DECODE_ADDRESS;
WAIT_TILL_EMPTY :
begin
next_state = DECODE_ADDRESS;
case(data_in)
2'b00 :begin
if(soft_reset_0)
next_state = DECODE_ADDRESS;
else if(~fifo_empty_0)
next_state = WAIT_TILL_EMPTY;
else if(fifo_empty_0)
next_state = LOAD_FIRST_DATA;
end
2'b01 :begin
if(soft_reset_1)
next_state = DECODE_ADDRESS;
else if(~fifo_empty_1)
next_state = WAIT_TILL_EMPTY;
else if(fifo_empty_1)
next_state = LOAD_FIRST_DATA;
end
2'b10 :begin
if(soft_reset_2)
next_state = DECODE_ADDRESS;
else if(~fifo_empty_2)
next_state = WAIT_TILL_EMPTY;
else if(fifo_empty_2)
next_state = LOAD_FIRST_DATA;
end
endcase
end
CHECK_PARITY_ERROR:if (fifo_full)
next_state= FIFO_FULL_STATE;
else
next_state=DECODE_ADDRESS;
endcase
end
assign detect_add =(state==DECODE_ADDRESS)?1:0;
assign rst_int_reg=(state==CHECK_PARITY_ERROR)?1:0;
assign lfd_state=(state==LOAD_FIRST_DATA)?1:0;
assign busy=(state==LOAD_PARITY || state== LOAD_AFTER_FULL || state==CHECK_PARITY_ERROR || state==LOAD_FIRST_DATA || state==FIFO_FULL_STATE || state== WAIT_TILL_EMPTY)?1:0;
assign write_enb_reg=(state==LOAD_PARITY || state==LOAD_AFTER_FULL || state==LOAD_DATA)?1:0;
assign laf_state=(state==LOAD_AFTER_FULL)?1:0;
assign full_state=(state==FIFO_FULL_STATE)?1:0;
assign ld_state=(state==LOAD_DATA);
endmodule | 1 |
6,510 | data/full_repos/permissive/116478018/RREG.v | 116,478,018 | RREG.v | v | 81 | 156 | [] | [] | [] | [(1, 80)] | null | data/verilator_xmls/f7b88abb-1e5d-422d-bf68-57dfc2bceb72.xml | null | 7,425 | module | module router_reg(input clock, resetn, pkt_valid, input [7:0] data_in, input fifo_full, detect_add, ld_state, laf_state, full_state, lfd_state, rst_int_reg,
output reg err, parity_done, low_packet_valid, output reg [7:0]dout);
reg [7:0]header_byte, internal_parity, temp_parity;
reg [7:0] data_reg;
always @(posedge clock)
begin
if(~resetn)
begin
dout<=0;
header_byte<=0;
data_reg<=0;
end
else if(detect_add && pkt_valid)
header_byte<= data_in;
else if(lfd_state)
dout<= header_byte;
else if(ld_state && ~fifo_full)
dout<= data_in;
else if(ld_state && fifo_full)
data_reg<=data_in;
else if(laf_state)
dout<=data_reg;
end
always@(posedge clock)
begin
if(~resetn)
begin
parity_done<=0;
end
else if(ld_state && (~fifo_full && ~pkt_valid) || (laf_state && low_packet_valid && (parity_done==0)))
parity_done<=1'b1;
else if(detect_add)
parity_done<=0;
end
always@(posedge clock)
begin
if(~resetn)
low_packet_valid<=0;
else if(ld_state && ~pkt_valid)
low_packet_valid<=1'b1;
else if(rst_int_reg)
low_packet_valid<=1'b0;
end
always@(posedge clock)
begin
if(~resetn)
err<=0;
else if(parity_done)
begin
if(internal_parity==temp_parity)
err<=1'b0;
else
err<=1'b1;
end
end
always@(posedge clock)
begin
if(~resetn)
internal_parity<=0;
else if(lfd_state && pkt_valid)
internal_parity<= internal_parity^header_byte;
else if (ld_state && ~full_state && pkt_valid)
internal_parity<= internal_parity^data_in;
end
always@(posedge clock)
begin
if(~resetn)
temp_parity<=0;
else if(ld_state && ~pkt_valid)
temp_parity<= data_in;
end
endmodule | module router_reg(input clock, resetn, pkt_valid, input [7:0] data_in, input fifo_full, detect_add, ld_state, laf_state, full_state, lfd_state, rst_int_reg,
output reg err, parity_done, low_packet_valid, output reg [7:0]dout); |
reg [7:0]header_byte, internal_parity, temp_parity;
reg [7:0] data_reg;
always @(posedge clock)
begin
if(~resetn)
begin
dout<=0;
header_byte<=0;
data_reg<=0;
end
else if(detect_add && pkt_valid)
header_byte<= data_in;
else if(lfd_state)
dout<= header_byte;
else if(ld_state && ~fifo_full)
dout<= data_in;
else if(ld_state && fifo_full)
data_reg<=data_in;
else if(laf_state)
dout<=data_reg;
end
always@(posedge clock)
begin
if(~resetn)
begin
parity_done<=0;
end
else if(ld_state && (~fifo_full && ~pkt_valid) || (laf_state && low_packet_valid && (parity_done==0)))
parity_done<=1'b1;
else if(detect_add)
parity_done<=0;
end
always@(posedge clock)
begin
if(~resetn)
low_packet_valid<=0;
else if(ld_state && ~pkt_valid)
low_packet_valid<=1'b1;
else if(rst_int_reg)
low_packet_valid<=1'b0;
end
always@(posedge clock)
begin
if(~resetn)
err<=0;
else if(parity_done)
begin
if(internal_parity==temp_parity)
err<=1'b0;
else
err<=1'b1;
end
end
always@(posedge clock)
begin
if(~resetn)
internal_parity<=0;
else if(lfd_state && pkt_valid)
internal_parity<= internal_parity^header_byte;
else if (ld_state && ~full_state && pkt_valid)
internal_parity<= internal_parity^data_in;
end
always@(posedge clock)
begin
if(~resetn)
temp_parity<=0;
else if(ld_state && ~pkt_valid)
temp_parity<= data_in;
end
endmodule | 1 |
6,511 | data/full_repos/permissive/116478018/RREG_TB.v | 116,478,018 | RREG_TB.v | v | 127 | 370 | [] | [] | [] | null | line:24: before: "resetn" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116478018/RREG_TB.v:15: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116478018/RREG_TB.v:17: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Error: data/full_repos/permissive/116478018/RREG_TB.v:23: syntax error, unexpected \'@\'\n @(negedge clock)\n ^\n%Error: data/full_repos/permissive/116478018/RREG_TB.v:39: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/116478018/RREG_TB.v:48: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/116478018/RREG_TB.v:54: syntax error, unexpected \'@\'\n @(negedge clock); \n ^\n%Error: data/full_repos/permissive/116478018/RREG_TB.v:63: syntax error, unexpected \'@\'\n @(negedge clock); \n ^\n%Error: data/full_repos/permissive/116478018/RREG_TB.v:67: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/116478018/RREG_TB.v:76: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/116478018/RREG_TB.v:85: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/116478018/RREG_TB.v:95: syntax error, unexpected \'@\'\n @(negedge clock); \n ^\n%Error: data/full_repos/permissive/116478018/RREG_TB.v:103: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/116478018/RREG_TB.v:107: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116478018/RREG_TB.v:117: Unsupported: Ignoring delay on this delayed statement.\n #105;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116478018/RREG_TB.v:119: Unsupported: Ignoring delay on this delayed statement.\n #1000 $finish;\n ^\n%Error: data/full_repos/permissive/116478018/RREG_TB.v:124: Unsupported or unknown PLI call: $monitor\n$monitor("clock=%b, resetn=%b, pkt_valid=%b, data_in=%b, fifo_full=%b, detect_add=%b, ld_state=%b, laf_state=%b, full_state=%b, lfd_state=%b, rst_int_reg=%b, err=%b, parity_done=%b, low_packet_valid=%b, dout=%b", clock, resetn, pkt_valid, data_in, fifo_full, detect_add, ld_state, laf_state, full_state, lfd_state, rst_int_reg, err, parity_done, low_packet_valid, dout);\n^~~~~~~~\n%Error: Exiting due to 12 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,426 | module | module router_reg_tb();
reg clock, resetn, pkt_valid;
reg [7:0] data_in;
reg fifo_full, detect_add, ld_state, laf_state, full_state, lfd_state, rst_int_reg;
wire err, parity_done, low_packet_valid;
wire [7:0]dout;
integer i;
parameter DELAY=10;
router_reg DUT (clock, resetn, pkt_valid, data_in, fifo_full, detect_add, ld_state, laf_state, full_state, lfd_state, rst_int_reg, err, parity_done, low_packet_valid, dout);
always
begin
clock=0;
#DELAY;
clock=1'b1;
#DELAY;
end
task rst;
begin
resetn=0;
@(negedge clock)
resetn=1'b1;
end
endtask
task initialize;
begin
{pkt_valid, data_in, fifo_full, detect_add, ld_state, laf_state, full_state, lfd_state, rst_int_reg}=0;
end
endtask
task goodpkt_gen;
reg [7:0]header, payload_data, parity;
reg [5:0]payloadlen;
begin
@(negedge clock);
payloadlen=8;
parity=0;
detect_add=1'b1;
pkt_valid=1'b1;
header={payloadlen,2'b10};
data_in=header;
parity=parity^data_in;
@(negedge clock);
detect_add=1'b0;
lfd_state=1'b1;
for(i=0;i<payloadlen;i=i+1)
begin
@(negedge clock);
lfd_state=0;
ld_state=1;
payload_data={$random}%256;
data_in=payload_data;
parity=parity^data_in;
end
@(negedge clock);
pkt_valid=0;
data_in=parity;
@(negedge clock);
ld_state=0;
end
endtask
task badpkt_gen;
reg [7:0]header, payload_data, parity;
reg [5:0]payloadlen;
begin
@(negedge clock);
payloadlen=8;
parity=0;
detect_add=1'b1;
pkt_valid=1'b1;
header={payloadlen,2'b10};
data_in=header;
parity=parity^data_in;
@(negedge clock);
detect_add=1'b0;
lfd_state=1'b1;
for(i=0;i<payloadlen;i=i+1)
begin
@(negedge clock);
lfd_state=0;
ld_state=1;
payload_data={$random}%256;
data_in=payload_data;
parity=parity^data_in;
end
@(negedge clock);
pkt_valid=0;
data_in=~parity;
@(negedge clock);
ld_state=0;
end
endtask
initial
begin
initialize;
rst;
goodpkt_gen;
#105;
badpkt_gen;
#1000 $finish;
end
initial
$monitor("clock=%b, resetn=%b, pkt_valid=%b, data_in=%b, fifo_full=%b, detect_add=%b, ld_state=%b, laf_state=%b, full_state=%b, lfd_state=%b, rst_int_reg=%b, err=%b, parity_done=%b, low_packet_valid=%b, dout=%b", clock, resetn, pkt_valid, data_in, fifo_full, detect_add, ld_state, laf_state, full_state, lfd_state, rst_int_reg, err, parity_done, low_packet_valid, dout);
endmodule | module router_reg_tb(); |
reg clock, resetn, pkt_valid;
reg [7:0] data_in;
reg fifo_full, detect_add, ld_state, laf_state, full_state, lfd_state, rst_int_reg;
wire err, parity_done, low_packet_valid;
wire [7:0]dout;
integer i;
parameter DELAY=10;
router_reg DUT (clock, resetn, pkt_valid, data_in, fifo_full, detect_add, ld_state, laf_state, full_state, lfd_state, rst_int_reg, err, parity_done, low_packet_valid, dout);
always
begin
clock=0;
#DELAY;
clock=1'b1;
#DELAY;
end
task rst;
begin
resetn=0;
@(negedge clock)
resetn=1'b1;
end
endtask
task initialize;
begin
{pkt_valid, data_in, fifo_full, detect_add, ld_state, laf_state, full_state, lfd_state, rst_int_reg}=0;
end
endtask
task goodpkt_gen;
reg [7:0]header, payload_data, parity;
reg [5:0]payloadlen;
begin
@(negedge clock);
payloadlen=8;
parity=0;
detect_add=1'b1;
pkt_valid=1'b1;
header={payloadlen,2'b10};
data_in=header;
parity=parity^data_in;
@(negedge clock);
detect_add=1'b0;
lfd_state=1'b1;
for(i=0;i<payloadlen;i=i+1)
begin
@(negedge clock);
lfd_state=0;
ld_state=1;
payload_data={$random}%256;
data_in=payload_data;
parity=parity^data_in;
end
@(negedge clock);
pkt_valid=0;
data_in=parity;
@(negedge clock);
ld_state=0;
end
endtask
task badpkt_gen;
reg [7:0]header, payload_data, parity;
reg [5:0]payloadlen;
begin
@(negedge clock);
payloadlen=8;
parity=0;
detect_add=1'b1;
pkt_valid=1'b1;
header={payloadlen,2'b10};
data_in=header;
parity=parity^data_in;
@(negedge clock);
detect_add=1'b0;
lfd_state=1'b1;
for(i=0;i<payloadlen;i=i+1)
begin
@(negedge clock);
lfd_state=0;
ld_state=1;
payload_data={$random}%256;
data_in=payload_data;
parity=parity^data_in;
end
@(negedge clock);
pkt_valid=0;
data_in=~parity;
@(negedge clock);
ld_state=0;
end
endtask
initial
begin
initialize;
rst;
goodpkt_gen;
#105;
badpkt_gen;
#1000 $finish;
end
initial
$monitor("clock=%b, resetn=%b, pkt_valid=%b, data_in=%b, fifo_full=%b, detect_add=%b, ld_state=%b, laf_state=%b, full_state=%b, lfd_state=%b, rst_int_reg=%b, err=%b, parity_done=%b, low_packet_valid=%b, dout=%b", clock, resetn, pkt_valid, data_in, fifo_full, detect_add, ld_state, laf_state, full_state, lfd_state, rst_int_reg, err, parity_done, low_packet_valid, dout);
endmodule | 1 |
6,513 | data/full_repos/permissive/116478018/RSYNC_TB.v | 116,478,018 | RSYNC_TB.v | v | 86 | 330 | [] | [] | [] | null | line:38: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116478018/RSYNC_TB.v:16: Unsupported: Ignoring delay on this delayed statement.\n #(DELAY/2);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116478018/RSYNC_TB.v:18: Unsupported: Ignoring delay on this delayed statement.\n #(DELAY/2);\n ^\n%Error: data/full_repos/permissive/116478018/RSYNC_TB.v:41: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/116478018/RSYNC_TB.v:49: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116478018/RSYNC_TB.v:57: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116478018/RSYNC_TB.v:77: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116478018/RSYNC_TB.v:78: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116478018/RSYNC_TB.v:80: Unsupported: Ignoring delay on this delayed statement.\n #1000 $finish;\n ^\n%Error: data/full_repos/permissive/116478018/RSYNC_TB.v:84: Unsupported or unknown PLI call: $monitor\n $monitor("clock=%b, resetn=%b, detect_add=%b, full_0=%b, full_1=%b, full_2=%b, empty_0=%b, empty_1=%b, empty_2=%b, write_enb_reg=%b, read_enb_0=%b, read_enb_1=%b, read_enb_2=%b, data_in=%b", clock, resetn, detect_add, full_0, full_1, full_2, empty_0, empty_1, empty_2, write_enb_reg, read_enb_0, read_enb_1, read_enb_2, data_in);\n ^~~~~~~~\n%Error: Exiting due to 3 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,428 | module | module router_sync_tb();
reg clock, resetn, detect_add, full_0, full_1, full_2, empty_0, empty_1, empty_2, write_enb_reg, read_enb_0, read_enb_1, read_enb_2;
reg [1:0]data_in;
wire [2:0]write_enb;
wire fifo_full, soft_reset_0, soft_reset_1, soft_reset_2;
wire vld_out_1, vld_out_2, vld_out_0;
parameter DELAY=10;
router_sync DUT(clock, resetn, detect_add, full_0, full_1, full_2, empty_0, empty_1, empty_2, write_enb_reg, read_enb_0, read_enb_1, read_enb_2, data_in, write_enb, fifo_full, soft_reset_0, soft_reset_1, soft_reset_2, vld_out_1, vld_out_2, vld_out_0);
always
begin
clock=1'b0;
#(DELAY/2);
clock=1'b1;
#(DELAY/2);
end
task initialize;
begin
data_in=0;
detect_add=0;
full_0=0;
full_1=0;
full_2=0;
empty_0=0;
empty_1=0;
empty_2=0;
write_enb_reg=0;
read_enb_0=0;
read_enb_1=0;
read_enb_2=0;
end
endtask
task rst();
begin
resetn= 0;
@(negedge clock);
resetn=1'b1;
end
endtask
task write_enb_s;
begin
write_enb_reg=1'b1;
@(negedge clock);
end
endtask
task drive(input[1:0]m);
begin
data_in=m;
#DELAY;
end
endtask
initial
begin
initialize;
rst;
drive(1);
detect_add=1'b1;
read_enb_0=1'b0;
read_enb_1=1'b0;
read_enb_2=1'b1;
write_enb_s;
full_0=1'b0;
full_1=1'b1;
full_2=1'b0;
empty_0=1'b1;
empty_1=1'b0;
empty_2=1'b1;
#DELAY;
#DELAY;
#1000 $finish;
end
initial
$monitor("clock=%b, resetn=%b, detect_add=%b, full_0=%b, full_1=%b, full_2=%b, empty_0=%b, empty_1=%b, empty_2=%b, write_enb_reg=%b, read_enb_0=%b, read_enb_1=%b, read_enb_2=%b, data_in=%b", clock, resetn, detect_add, full_0, full_1, full_2, empty_0, empty_1, empty_2, write_enb_reg, read_enb_0, read_enb_1, read_enb_2, data_in);
endmodule | module router_sync_tb(); |
reg clock, resetn, detect_add, full_0, full_1, full_2, empty_0, empty_1, empty_2, write_enb_reg, read_enb_0, read_enb_1, read_enb_2;
reg [1:0]data_in;
wire [2:0]write_enb;
wire fifo_full, soft_reset_0, soft_reset_1, soft_reset_2;
wire vld_out_1, vld_out_2, vld_out_0;
parameter DELAY=10;
router_sync DUT(clock, resetn, detect_add, full_0, full_1, full_2, empty_0, empty_1, empty_2, write_enb_reg, read_enb_0, read_enb_1, read_enb_2, data_in, write_enb, fifo_full, soft_reset_0, soft_reset_1, soft_reset_2, vld_out_1, vld_out_2, vld_out_0);
always
begin
clock=1'b0;
#(DELAY/2);
clock=1'b1;
#(DELAY/2);
end
task initialize;
begin
data_in=0;
detect_add=0;
full_0=0;
full_1=0;
full_2=0;
empty_0=0;
empty_1=0;
empty_2=0;
write_enb_reg=0;
read_enb_0=0;
read_enb_1=0;
read_enb_2=0;
end
endtask
task rst();
begin
resetn= 0;
@(negedge clock);
resetn=1'b1;
end
endtask
task write_enb_s;
begin
write_enb_reg=1'b1;
@(negedge clock);
end
endtask
task drive(input[1:0]m);
begin
data_in=m;
#DELAY;
end
endtask
initial
begin
initialize;
rst;
drive(1);
detect_add=1'b1;
read_enb_0=1'b0;
read_enb_1=1'b0;
read_enb_2=1'b1;
write_enb_s;
full_0=1'b0;
full_1=1'b1;
full_2=1'b0;
empty_0=1'b1;
empty_1=1'b0;
empty_2=1'b1;
#DELAY;
#DELAY;
#1000 $finish;
end
initial
$monitor("clock=%b, resetn=%b, detect_add=%b, full_0=%b, full_1=%b, full_2=%b, empty_0=%b, empty_1=%b, empty_2=%b, write_enb_reg=%b, read_enb_0=%b, read_enb_1=%b, read_enb_2=%b, data_in=%b", clock, resetn, detect_add, full_0, full_1, full_2, empty_0, empty_1, empty_2, write_enb_reg, read_enb_0, read_enb_1, read_enb_2, data_in);
endmodule | 1 |
6,516 | data/full_repos/permissive/11649754/p1/p1.v | 11,649,754 | p1.v | v | 34 | 91 | [] | [] | [] | [(1, 33)] | null | null | 1: b"%Error: data/full_repos/permissive/11649754/p1/p1.v:7: Duplicate declaration of signal: 'IsEnd'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire IsEnd = stage_ == 3;\n ^~~~~\n data/full_repos/permissive/11649754/p1/p1.v:1: ... Location of original declaration\nmodule p1( input Init, input CLK, output IsEnd, output reg [31:0] sum_ );\n ^~~~~\n%Error: Exiting due to 1 error(s)\n" | 7,431 | module | module p1( input Init, input CLK, output IsEnd, output reg [31:0] sum_ );
parameter Upto = 1000;
reg [10:0] cnt_;
reg [1000:0] flags_;
reg [3:0] stage_;
wire IsLoopEnd = cnt_ >= (Upto-1);
wire IsEnd = stage_ == 3;
wire [13:0] c5 = cnt_ * 5;
wire [13:0] c3 = cnt_ * 3;
initial begin
stage_ <= 0;
sum_ <= 0;
cnt_ <= 0;
end
always @(posedge CLK) begin
flags_[c5] <= (Init | stage_ == 0) ? 0 : ( c5 <= Upto & stage_ == 1 ) ? 1 : flags_[c5];
flags_[c3] <= (Init | stage_ == 0) ? 0 : ( c3 <= Upto & stage_ == 1 ) ? 1 : flags_[c3];
flags_[cnt_] <= (Init | stage_ == 0) ? 0 : flags_[cnt_];
stage_ <= Init ? 0:
(stage_ == 0 & IsLoopEnd) ? 1:
(stage_ == 1 & IsLoopEnd) ? 2:
(stage_ == 2 & IsLoopEnd) ? 3 : stage_;
cnt_ <= (IsEnd) ? cnt_:
(Init | IsLoopEnd) ? 0:
cnt_ + 1;
sum_ <= (IsEnd) ? sum_ : (Init | stage_ != 2) ? 0:
(flags_[cnt_]) ? (sum_+cnt_) : sum_;
end
endmodule | module p1( input Init, input CLK, output IsEnd, output reg [31:0] sum_ ); |
parameter Upto = 1000;
reg [10:0] cnt_;
reg [1000:0] flags_;
reg [3:0] stage_;
wire IsLoopEnd = cnt_ >= (Upto-1);
wire IsEnd = stage_ == 3;
wire [13:0] c5 = cnt_ * 5;
wire [13:0] c3 = cnt_ * 3;
initial begin
stage_ <= 0;
sum_ <= 0;
cnt_ <= 0;
end
always @(posedge CLK) begin
flags_[c5] <= (Init | stage_ == 0) ? 0 : ( c5 <= Upto & stage_ == 1 ) ? 1 : flags_[c5];
flags_[c3] <= (Init | stage_ == 0) ? 0 : ( c3 <= Upto & stage_ == 1 ) ? 1 : flags_[c3];
flags_[cnt_] <= (Init | stage_ == 0) ? 0 : flags_[cnt_];
stage_ <= Init ? 0:
(stage_ == 0 & IsLoopEnd) ? 1:
(stage_ == 1 & IsLoopEnd) ? 2:
(stage_ == 2 & IsLoopEnd) ? 3 : stage_;
cnt_ <= (IsEnd) ? cnt_:
(Init | IsLoopEnd) ? 0:
cnt_ + 1;
sum_ <= (IsEnd) ? sum_ : (Init | stage_ != 2) ? 0:
(flags_[cnt_]) ? (sum_+cnt_) : sum_;
end
endmodule | 0 |
6,517 | data/full_repos/permissive/11649754/p2/core.v | 11,649,754 | core.v | v | 20 | 76 | [] | [] | [] | [(30, 121)] | null | null | 1: b"%Error: data/full_repos/permissive/11649754/p2/core.v:5: Duplicate declaration of signal: 'IsEnd'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire IsEnd = now_ >= Upto;\n ^~~~~\n data/full_repos/permissive/11649754/p2/core.v:1: ... Location of original declaration\nmodule core (input Init, input CLK, output IsEnd, output reg [31:0] sum_ );\n ^~~~~\n%Error: Exiting due to 1 error(s)\n" | 7,433 | module | module core (input Init, input CLK, output IsEnd, output reg [31:0] sum_ );
parameter Upto = 4000000;
reg [31:0] last_;
reg [31:0] now_;
wire IsEnd = now_ >= Upto;
initial begin
sum_ <= 0;
last_<= 1;
now_ <= 2;
end
always @(posedge CLK) begin
sum_ <= (IsEnd | ((now_ & 1) == 1)) ? sum_ : sum_ + now_;
now_ <= (IsEnd) ? now_ : last_ + now_;
last_ <= (IsEnd) ? last_ : now_;
end
endmodule | module core (input Init, input CLK, output IsEnd, output reg [31:0] sum_ ); |
parameter Upto = 4000000;
reg [31:0] last_;
reg [31:0] now_;
wire IsEnd = now_ >= Upto;
initial begin
sum_ <= 0;
last_<= 1;
now_ <= 2;
end
always @(posedge CLK) begin
sum_ <= (IsEnd | ((now_ & 1) == 1)) ? sum_ : sum_ + now_;
now_ <= (IsEnd) ? now_ : last_ + now_;
last_ <= (IsEnd) ? last_ : now_;
end
endmodule | 0 |
6,518 | data/full_repos/permissive/11649754/p2/test.v | 11,649,754 | test.v | v | 55 | 48 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/11649754/p2/test.v:21: Unsupported: Ignoring delay on this delayed statement.\n #CLKH clk = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11649754/p2/test.v:22: Unsupported: Ignoring delay on this delayed statement.\n #CLKL clk = 1;\n ^\n%Error: data/full_repos/permissive/11649754/p2/test.v:28: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/11649754/p2/test.v:29: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,test.c);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/11649754/p2/test.v:38: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/11649754/p2/test.v:41: Unsupported or unknown PLI call: $dumpall\n $dumpall;\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/11649754/p2/test.v:47: Unsupported: Ignoring delay on this delayed statement.\n #1 reset = 1;\n ^\n%Error: data/full_repos/permissive/11649754/p2/test.v:48: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,434 | module | module test;
reg clk;
reg reset;
wire isEnd;
wire [31:0] sum;
core c(reset, clk, isEnd, sum);
parameter CLKP = 5000;
parameter CLKH = CLKP/2;
parameter CLKL = CLKP-CLKH;
always begin
#CLKH clk = 0;
#CLKL clk = 1;
end
`ifdef GTK
initial begin
$dumpfile("test.vcd");
$dumpvars(0,test.c);
end
`endif
initial begin : test
$display("*** Simulation Started. ***");
sys_reset;
$display("*** Simulation Initialized. ***");
while (~isEnd)
@(posedge clk);
$display("*** Simulation Complete! ***");
$display("RESULT: %d", sum);
$dumpall;
$finish;
end
task sys_reset;
begin
#1 reset = 1;
@(posedge clk);
reset = 0;
end
endtask
endmodule | module test; |
reg clk;
reg reset;
wire isEnd;
wire [31:0] sum;
core c(reset, clk, isEnd, sum);
parameter CLKP = 5000;
parameter CLKH = CLKP/2;
parameter CLKL = CLKP-CLKH;
always begin
#CLKH clk = 0;
#CLKL clk = 1;
end
`ifdef GTK
initial begin
$dumpfile("test.vcd");
$dumpvars(0,test.c);
end
`endif
initial begin : test
$display("*** Simulation Started. ***");
sys_reset;
$display("*** Simulation Initialized. ***");
while (~isEnd)
@(posedge clk);
$display("*** Simulation Complete! ***");
$display("RESULT: %d", sum);
$dumpall;
$finish;
end
task sys_reset;
begin
#1 reset = 1;
@(posedge clk);
reset = 0;
end
endtask
endmodule | 0 |
6,519 | data/full_repos/permissive/116563702/combitional in always/full adder/advanced_testBench.v | 116,563,702 | advanced_testBench.v | v | 54 | 155 | [] | [] | [] | [(3, 53)] | null | null | 1: b'%Error: Cannot find file containing module: in\n ... Looked in:\n data/full_repos/permissive/116563702/combitional/in\n data/full_repos/permissive/116563702/combitional/in.v\n data/full_repos/permissive/116563702/combitional/in.sv\n in\n in.v\n in.sv\n obj_dir/in\n obj_dir/in.v\n obj_dir/in.sv\n%Error: Cannot find file containing module: always/full\n%Error: Cannot find file containing module: adder,data/full_repos/permissive/116563702\n%Error: Cannot find file containing module: data/full_repos/permissive/116563702/combitional\n%Error: Cannot find file containing module: adder/advanced_testBench.v\n%Error: Exiting due to 5 error(s)\n' | 7,435 | module | module testbench;
reg a, b, cin, cout_exp, sum_exp, clk, reset;
wire cout, sum;
reg [4:0] i, error;
reg [4:0] testvector[8:1];
fulladder uut(a, b, cin, cout, sum);
always
begin
#5 clk = ~clk;
end
initial
begin
clk = 0;
i = 1;
error = 0;
$readmemb("/media/nipun/789CB1599CB1131C/Nipun Pruthi/Study/IITR/vivado/files/understanding/combitional in always/full adder/test_data.txt", testvector);
reset = 1;
#10 reset = 0;
end
always @(posedge clk)
begin
#1 {a,b,cin,cout_exp,sum_exp} = testvector[i];
end
always @(negedge clk)
begin
if(~reset)
begin
if ({cout_exp,sum_exp} !== {cout,sum})
begin
$display("Error: inputs = %b",{a,b,cin});
$display("Output: %b cout,sum(%b expected)",{cout,sum},{cout_exp,sum_exp});
error = error + 1;
end
else
begin
$display("Passed: inputs = %b",{a,b,cin});
end
i = i + 1;
if(testvector[i] === 5'bx)
begin
$display("%d tests complete with %d errors", i, error);
$finish;
end
end
end
endmodule | module testbench; |
reg a, b, cin, cout_exp, sum_exp, clk, reset;
wire cout, sum;
reg [4:0] i, error;
reg [4:0] testvector[8:1];
fulladder uut(a, b, cin, cout, sum);
always
begin
#5 clk = ~clk;
end
initial
begin
clk = 0;
i = 1;
error = 0;
$readmemb("/media/nipun/789CB1599CB1131C/Nipun Pruthi/Study/IITR/vivado/files/understanding/combitional in always/full adder/test_data.txt", testvector);
reset = 1;
#10 reset = 0;
end
always @(posedge clk)
begin
#1 {a,b,cin,cout_exp,sum_exp} = testvector[i];
end
always @(negedge clk)
begin
if(~reset)
begin
if ({cout_exp,sum_exp} !== {cout,sum})
begin
$display("Error: inputs = %b",{a,b,cin});
$display("Output: %b cout,sum(%b expected)",{cout,sum},{cout_exp,sum_exp});
error = error + 1;
end
else
begin
$display("Passed: inputs = %b",{a,b,cin});
end
i = i + 1;
if(testvector[i] === 5'bx)
begin
$display("%d tests complete with %d errors", i, error);
$finish;
end
end
end
endmodule | 0 |
6,520 | data/full_repos/permissive/116563702/combitional in always/full adder/fulladderStyle2.v | 116,563,702 | fulladderStyle2.v | v | 17 | 34 | [] | [] | [] | null | line:17: before: "ut" | null | 1: b'%Error: Cannot find file containing module: in\n ... Looked in:\n data/full_repos/permissive/116563702/combitional/in\n data/full_repos/permissive/116563702/combitional/in.v\n data/full_repos/permissive/116563702/combitional/in.sv\n in\n in.v\n in.sv\n obj_dir/in\n obj_dir/in.v\n obj_dir/in.sv\n%Error: Cannot find file containing module: always/full\n%Error: Cannot find file containing module: adder,data/full_repos/permissive/116563702\n%Error: Cannot find file containing module: data/full_repos/permissive/116563702/combitional\n%Error: Cannot find file containing module: adder/fulladderStyle2.v\n%Error: Exiting due to 5 error(s)\n' | 7,437 | module | module fulladder(input a, b, cin,
output reg cout, sum);
reg p, g;
always @(a,b,cin)
begin
p = a ^ b;
g = a & b;
cout = g | p & cin;
sum = p ^ cin;
end
endmodule | module fulladder(input a, b, cin,
output reg cout, sum); |
reg p, g;
always @(a,b,cin)
begin
p = a ^ b;
g = a & b;
cout = g | p & cin;
sum = p ^ cin;
end
endmodule | 0 |
6,521 | data/full_repos/permissive/116563702/combitional in always/full adder/testbench.v | 116,563,702 | testbench.v | v | 23 | 40 | [] | [] | [] | [(3, 22)] | null | null | 1: b'%Error: Cannot find file containing module: in\n ... Looked in:\n data/full_repos/permissive/116563702/combitional/in\n data/full_repos/permissive/116563702/combitional/in.v\n data/full_repos/permissive/116563702/combitional/in.sv\n in\n in.v\n in.sv\n obj_dir/in\n obj_dir/in.v\n obj_dir/in.sv\n%Error: Cannot find file containing module: always/full\n%Error: Cannot find file containing module: adder,data/full_repos/permissive/116563702\n%Error: Cannot find file containing module: data/full_repos/permissive/116563702/combitional\n%Error: Cannot find file containing module: adder/testbench.v\n%Error: Exiting due to 5 error(s)\n' | 7,438 | module | module testbench;
reg a, b, cin;
wire sum, cout;
initial
begin
a = 0;
b = 0;
cin=0;
#5 a = 1;
#5 b = 1;
#5 a = 0;
#5 b = 0;
#5 cin = 1;
#5 a = 1;
#5 b = 1;
#5 a = 0;
end
fulladder uut(a, b, cin, cout, sum);
endmodule | module testbench; |
reg a, b, cin;
wire sum, cout;
initial
begin
a = 0;
b = 0;
cin=0;
#5 a = 1;
#5 b = 1;
#5 a = 0;
#5 b = 0;
#5 cin = 1;
#5 a = 1;
#5 b = 1;
#5 a = 0;
end
fulladder uut(a, b, cin, cout, sum);
endmodule | 0 |
6,522 | data/full_repos/permissive/116563702/combitional in always/inverter in always/inverter.v | 116,563,702 | inverter.v | v | 11 | 70 | [] | [] | [] | [(3, 10)] | null | null | 1: b'%Error: Cannot find file containing module: in\n ... Looked in:\n data/full_repos/permissive/116563702/combitional/in\n data/full_repos/permissive/116563702/combitional/in.v\n data/full_repos/permissive/116563702/combitional/in.sv\n in\n in.v\n in.sv\n obj_dir/in\n obj_dir/in.v\n obj_dir/in.sv\n%Error: Cannot find file containing module: always/inverter\n%Error: Cannot find file containing module: always,data/full_repos/permissive/116563702\n%Error: Cannot find file containing module: data/full_repos/permissive/116563702/combitional\n%Error: Cannot find file containing module: always/inverter.v\n%Error: Exiting due to 5 error(s)\n' | 7,439 | module | module inverter(input [3:0] d,
output reg [3:0] q);
always @(*)
begin
q <= ~d;
end
endmodule | module inverter(input [3:0] d,
output reg [3:0] q); |
always @(*)
begin
q <= ~d;
end
endmodule | 0 |
6,523 | data/full_repos/permissive/116563702/decoder3_8/decoder3_8style.v | 116,563,702 | decoder3_8style.v | v | 15 | 40 | [] | [] | [] | [(3, 14)] | null | data/verilator_xmls/bdc38a7d-50a8-458b-b5c8-21873639dd89.xml | null | 7,441 | module | module decoder3_8( input [2:0] a,
output [7:0] y);
assign y[0] = ~(|a);
assign y[1] = ~a[2] & ~a[1] & a[0];
assign y[2] = ~a[2] & a[1] & ~a[0];
assign y[3] = ~a[2] & a[1] & a[0];
assign y[4] = a[2] & ~a[1] & ~a[0];
assign y[5] = a[2] & ~a[1] & a[0];
assign y[6] = a[2] & a[1] & ~a[0];
assign y[7] = &a;
endmodule | module decoder3_8( input [2:0] a,
output [7:0] y); |
assign y[0] = ~(|a);
assign y[1] = ~a[2] & ~a[1] & a[0];
assign y[2] = ~a[2] & a[1] & ~a[0];
assign y[3] = ~a[2] & a[1] & a[0];
assign y[4] = a[2] & ~a[1] & ~a[0];
assign y[5] = a[2] & ~a[1] & a[0];
assign y[6] = a[2] & a[1] & ~a[0];
assign y[7] = &a;
endmodule | 0 |
6,524 | data/full_repos/permissive/116563702/decoder_parameterized/decoder.v | 116,563,702 | decoder.v | v | 14 | 39 | [] | [] | [] | [(3, 13)] | null | data/verilator_xmls/f1137f33-226e-47b7-b60a-9ee0e2fd3bb4.xml | null | 7,442 | module | module decoder #(parameter N=3)
(input [N:0] a,
output reg [2**(N+1)-1:0] y);
always @(*)
begin
y = 0;
y[a] = 1;
end
endmodule | module decoder #(parameter N=3)
(input [N:0] a,
output reg [2**(N+1)-1:0] y); |
always @(*)
begin
y = 0;
y[a] = 1;
end
endmodule | 0 |
6,525 | data/full_repos/permissive/116563702/fsm/counter/mod3counter.v | 116,563,702 | mod3counter.v | v | 36 | 67 | [] | [] | [] | null | line:14: before: "reset" | data/verilator_xmls/57091ecf-cb0c-4099-8cf9-6aa8bc74a82f.xml | null | 7,445 | module | module mod3counter( input clk,
input reset,
output y);
reg [1:0] state, nextstate;
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b01;
always @(posedge clk, reset)
begin
if (reset)
state <= 2'b00;
else
state <= nextstate;
end
always @(*)
begin
case (state)
S0 : nextstate = S1;
S1 : nextstate = S2;
S2 : nextstate = S0;
default : nextstate = S0;
endcase
end
assign y = (state == S0);
endmodule | module mod3counter( input clk,
input reset,
output y); |
reg [1:0] state, nextstate;
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b01;
always @(posedge clk, reset)
begin
if (reset)
state <= 2'b00;
else
state <= nextstate;
end
always @(*)
begin
case (state)
S0 : nextstate = S1;
S1 : nextstate = S2;
S2 : nextstate = S0;
default : nextstate = S0;
endcase
end
assign y = (state == S0);
endmodule | 0 |
6,526 | data/full_repos/permissive/116563702/fsm/counter/mod3counter_testbench.v | 116,563,702 | mod3counter_testbench.v | v | 25 | 35 | [] | [] | [] | [(3, 24)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116563702/fsm/counter/mod3counter_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n #50 reset = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116563702/fsm/counter/mod3counter_testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116563702/fsm/counter/mod3counter_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/116563702/fsm/counter/mod3counter_testbench.v:22: Cannot find file containing module: \'mod3counter\'\n mod3counter uut(clk, reset, y);\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116563702/fsm/counter,data/full_repos/permissive/116563702/mod3counter\n data/full_repos/permissive/116563702/fsm/counter,data/full_repos/permissive/116563702/mod3counter.v\n data/full_repos/permissive/116563702/fsm/counter,data/full_repos/permissive/116563702/mod3counter.sv\n mod3counter\n mod3counter.v\n mod3counter.sv\n obj_dir/mod3counter\n obj_dir/mod3counter.v\n obj_dir/mod3counter.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,446 | module | module testbench;
reg clk, reset;
wire y;
reg [1:0] state, nextstate;
initial
begin
reset = 0;
clk = 0;
#50 reset = 1;
#20 reset = 0;
end
always
begin
#5 clk = ~clk;
end
mod3counter uut(clk, reset, y);
endmodule | module testbench; |
reg clk, reset;
wire y;
reg [1:0] state, nextstate;
initial
begin
reset = 0;
clk = 0;
#50 reset = 1;
#20 reset = 0;
end
always
begin
#5 clk = ~clk;
end
mod3counter uut(clk, reset, y);
endmodule | 0 |
6,527 | data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps/lamps.v | 116,563,702 | lamps.v | v | 51 | 146 | [] | [] | [] | [(3, 50)] | null | data/verilator_xmls/1407140f-acd8-41c9-b4ac-e9c6dd9aa757.xml | null | 7,448 | module | module ford_thunderbird( input reset,
input left,
input right,
input clk,
output [5:0] y);
parameter S0 = 3'd0;
parameter S1 = 3'd1;
parameter S2 = 3'd2;
parameter S3 = 3'd3;
parameter S4 = 3'd4;
parameter S5 = 3'd5;
parameter S6 = 3'd6;
reg [2:0] state, nextstate;
always @(posedge clk)
if (reset) state <= S0;
else state <= nextstate;
always @(*)
begin
case(state)
S0 : if (left) nextstate = S1;
else if (right) nextstate = S4;
else nextstate = S0;
S1 : nextstate = S2;
S2 : nextstate = S3;
S3 : nextstate = S0;
S4 : nextstate = S5;
S5 : nextstate = S6;
S6 : nextstate = S0;
default : nextstate = S0;
endcase
end
assign y[5] = (state === 3'd3);
assign y[4] = (state === 3'd3 || state === 3'd2);
assign y[3] = (state === 3'd3 || state === 3'd2 || state === 3'd1);
assign y[2] = (state === 3'd4 || state === 3'd5 || state === 3'd6);
assign y[1] = (state === 3'd5 || state === 3'd6);
assign y[0] = (state === 3'd6);
endmodule | module ford_thunderbird( input reset,
input left,
input right,
input clk,
output [5:0] y); |
parameter S0 = 3'd0;
parameter S1 = 3'd1;
parameter S2 = 3'd2;
parameter S3 = 3'd3;
parameter S4 = 3'd4;
parameter S5 = 3'd5;
parameter S6 = 3'd6;
reg [2:0] state, nextstate;
always @(posedge clk)
if (reset) state <= S0;
else state <= nextstate;
always @(*)
begin
case(state)
S0 : if (left) nextstate = S1;
else if (right) nextstate = S4;
else nextstate = S0;
S1 : nextstate = S2;
S2 : nextstate = S3;
S3 : nextstate = S0;
S4 : nextstate = S5;
S5 : nextstate = S6;
S6 : nextstate = S0;
default : nextstate = S0;
endcase
end
assign y[5] = (state === 3'd3);
assign y[4] = (state === 3'd3 || state === 3'd2);
assign y[3] = (state === 3'd3 || state === 3'd2 || state === 3'd1);
assign y[2] = (state === 3'd4 || state === 3'd5 || state === 3'd6);
assign y[1] = (state === 3'd5 || state === 3'd6);
assign y[0] = (state === 3'd6);
endmodule | 0 |
6,528 | data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps/testbench.v | 116,563,702 | testbench.v | v | 56 | 148 | [] | [] | [] | [(3, 55)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps/testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps/testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n #20 resetest = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2 {left, right, reset, y_exp} = vector[i];\n ^\n%Error: data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps/testbench.v:11: Cannot find file containing module: \'ford_thunderbird\'\n ford_thunderbird uut(reset, left, right, clk, y);\n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps,data/full_repos/permissive/116563702/ford_thunderbird\n data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps,data/full_repos/permissive/116563702/ford_thunderbird.v\n data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps,data/full_repos/permissive/116563702/ford_thunderbird.sv\n ford_thunderbird\n ford_thunderbird.v\n ford_thunderbird.sv\n obj_dir/ford_thunderbird\n obj_dir/ford_thunderbird.v\n obj_dir/ford_thunderbird.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 7,449 | module | module testbench;
reg left, right, resetest, reset, clk;
reg [5:0] y_exp;
wire [5:0] y;
reg [10:0] i, error;
reg [8:0] vector[100:1];
ford_thunderbird uut(reset, left, right, clk, y);
always begin
#5 clk = ~clk;
end
initial
begin
clk = 0;
i = 1;
error = 0;
$readmemb("/media/nipun/789CB1599CB1131C/Nipun Pruthi/Study/IITR/vivado/files/understanding/fsm/ford_thunderbird_tail_lamps/test_data.tv",vector);
resetest = 1;
#20 resetest = 0;
end
always @(negedge clk)
begin
#2 {left, right, reset, y_exp} = vector[i];
end
always @(negedge clk)
begin
if(~resetest)
begin
if (y_exp !== y)
begin
$display ("Error : input = %b",{left, right, reset});
$display ("Output : %b ( %b expected)",y, y_exp);
error = error + 1;
end
else
begin
$display("Passed : Input = %b", {left,right,reset});
$display("Output : %b (%b expected)",y, y_exp);
end
i = i + 1;
if (vector[i] === 9'bx)
begin
$display("%d test complete with %d errors", i-1, error);
$finish;
end
end
end
endmodule | module testbench; |
reg left, right, resetest, reset, clk;
reg [5:0] y_exp;
wire [5:0] y;
reg [10:0] i, error;
reg [8:0] vector[100:1];
ford_thunderbird uut(reset, left, right, clk, y);
always begin
#5 clk = ~clk;
end
initial
begin
clk = 0;
i = 1;
error = 0;
$readmemb("/media/nipun/789CB1599CB1131C/Nipun Pruthi/Study/IITR/vivado/files/understanding/fsm/ford_thunderbird_tail_lamps/test_data.tv",vector);
resetest = 1;
#20 resetest = 0;
end
always @(negedge clk)
begin
#2 {left, right, reset, y_exp} = vector[i];
end
always @(negedge clk)
begin
if(~resetest)
begin
if (y_exp !== y)
begin
$display ("Error : input = %b",{left, right, reset});
$display ("Output : %b ( %b expected)",y, y_exp);
error = error + 1;
end
else
begin
$display("Passed : Input = %b", {left,right,reset});
$display("Output : %b (%b expected)",y, y_exp);
end
i = i + 1;
if (vector[i] === 9'bx)
begin
$display("%d test complete with %d errors", i-1, error);
$finish;
end
end
end
endmodule | 0 |
6,529 | data/full_repos/permissive/116563702/fsm/snail_pattern_1101/mealy.v | 116,563,702 | mealy.v | v | 50 | 42 | [] | [] | [] | [(3, 49)] | null | data/verilator_xmls/ce4600e6-a7af-418d-b9dc-5147f4c34c69.xml | null | 7,450 | module | module snail_mealy_1101( input d,
input clk,
input reset,
output y);
parameter S0 = 3'd0;
parameter S1 = 3'd1;
parameter S2 = 3'd2;
parameter S3 = 3'd3;
reg [2:0] state, nextstate;
always @(posedge clk or posedge reset)
begin
if (reset) state <= S0;
else state <= nextstate;
end
always @(*)
begin
case (state)
S0 :
if (d) nextstate = S1;
else nextstate = S0;
S1 :
if (d) nextstate = S2;
else nextstate = S0;
S2 :
if (~d) nextstate = S3;
else nextstate = S2;
S3 :
if (d) nextstate = S1;
else nextstate = S0;
default :
nextstate = S0;
endcase
end
assign y = (d & state == S3);
endmodule | module snail_mealy_1101( input d,
input clk,
input reset,
output y); |
parameter S0 = 3'd0;
parameter S1 = 3'd1;
parameter S2 = 3'd2;
parameter S3 = 3'd3;
reg [2:0] state, nextstate;
always @(posedge clk or posedge reset)
begin
if (reset) state <= S0;
else state <= nextstate;
end
always @(*)
begin
case (state)
S0 :
if (d) nextstate = S1;
else nextstate = S0;
S1 :
if (d) nextstate = S2;
else nextstate = S0;
S2 :
if (~d) nextstate = S3;
else nextstate = S2;
S3 :
if (d) nextstate = S1;
else nextstate = S0;
default :
nextstate = S0;
endcase
end
assign y = (d & state == S3);
endmodule | 0 |
6,530 | data/full_repos/permissive/116563702/generate_hardware/genrate_parameter_NinputAnd.v | 116,563,702 | genrate_parameter_NinputAnd.v | v | 23 | 35 | [] | [] | [] | [(3, 22)] | null | data/verilator_xmls/671f9012-e136-46b4-8486-84a8c9d9ce00.xml | null | 7,452 | module | module andN #(parameter N=8)
(input [N-1:0] a,
output y);
wire [N-1:1] x;
genvar i;
generate
for (i=1; i<N; i=i+1)
begin:ForLoop
if (i==1)
assign x[1] = a[0] & a[1];
else
assign x[i] = x[i-1] & a[i];
end
endgenerate
assign y = x[N-1];
endmodule | module andN #(parameter N=8)
(input [N-1:0] a,
output y); |
wire [N-1:1] x;
genvar i;
generate
for (i=1; i<N; i=i+1)
begin:ForLoop
if (i==1)
assign x[1] = a[0] & a[1];
else
assign x[i] = x[i-1] & a[i];
end
endgenerate
assign y = x[N-1];
endmodule | 0 |
6,531 | data/full_repos/permissive/116563702/muxs with paramatirization/mux2.v | 116,563,702 | mux2.v | v | 9 | 52 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: with\n ... Looked in:\n data/full_repos/permissive/116563702/muxs/with\n data/full_repos/permissive/116563702/muxs/with.v\n data/full_repos/permissive/116563702/muxs/with.sv\n with\n with.v\n with.sv\n obj_dir/with\n obj_dir/with.v\n obj_dir/with.sv\n%Error: Cannot find file containing module: paramatirization,data/full_repos/permissive/116563702\n%Error: Cannot find file containing module: data/full_repos/permissive/116563702/muxs\n%Error: Cannot find file containing module: paramatirization/mux2.v\n%Error: Exiting due to 4 error(s)\n' | 7,454 | module | module mux2 #(parameter N=3) (input [N-1:0] d1, d0,
input s,
output [N-1:0] data);
assign data = s ? d1 : d0;
endmodule | module mux2 #(parameter N=3) (input [N-1:0] d1, d0,
input s,
output [N-1:0] data); |
assign data = s ? d1 : d0;
endmodule | 0 |
6,532 | data/full_repos/permissive/116563702/muxs with paramatirization/mux2Tristate.v | 116,563,702 | mux2Tristate.v | v | 10 | 52 | [] | [] | [] | [(3, 9)] | null | null | 1: b'%Error: Cannot find file containing module: with\n ... Looked in:\n data/full_repos/permissive/116563702/muxs/with\n data/full_repos/permissive/116563702/muxs/with.v\n data/full_repos/permissive/116563702/muxs/with.sv\n with\n with.v\n with.sv\n obj_dir/with\n obj_dir/with.v\n obj_dir/with.sv\n%Error: Cannot find file containing module: paramatirization,data/full_repos/permissive/116563702\n%Error: Cannot find file containing module: data/full_repos/permissive/116563702/muxs\n%Error: Cannot find file containing module: paramatirization/mux2Tristate.v\n%Error: Exiting due to 4 error(s)\n' | 7,455 | module | module mux2 #(parameter N=4) (input [N-1:0] d1, d0,
input s,
output [N-1:0] data);
tristate #(N) l1(d0, ~s, data);
tristate #(N) l2(d1, s, data);
endmodule | module mux2 #(parameter N=4) (input [N-1:0] d1, d0,
input s,
output [N-1:0] data); |
tristate #(N) l1(d0, ~s, data);
tristate #(N) l2(d1, s, data);
endmodule | 0 |
6,533 | data/full_repos/permissive/116563702/muxs with paramatirization/mux4.v | 116,563,702 | mux4.v | v | 13 | 61 | [] | [] | [] | [(3, 12)] | null | null | 1: b'%Error: Cannot find file containing module: with\n ... Looked in:\n data/full_repos/permissive/116563702/muxs/with\n data/full_repos/permissive/116563702/muxs/with.v\n data/full_repos/permissive/116563702/muxs/with.sv\n with\n with.v\n with.sv\n obj_dir/with\n obj_dir/with.v\n obj_dir/with.sv\n%Error: Cannot find file containing module: paramatirization,data/full_repos/permissive/116563702\n%Error: Cannot find file containing module: data/full_repos/permissive/116563702/muxs\n%Error: Cannot find file containing module: paramatirization/mux4.v\n%Error: Exiting due to 4 error(s)\n' | 7,456 | module | module mux4 #(parameter N=4) ( input [N-1:0] d0, d1, d2, d3,
input [1:0] s,
output [N-1:0] data);
wire [N-1:0] bhigh, blow;
mux2 #(N) muxhigh(d3, d2, s[0], bhigh);
mux2 #(N) muxlow( d1, d0, s[0], blow);
mux2 #(N) muxfinal(bhigh, blow, s[1], data);
endmodule | module mux4 #(parameter N=4) ( input [N-1:0] d0, d1, d2, d3,
input [1:0] s,
output [N-1:0] data); |
wire [N-1:0] bhigh, blow;
mux2 #(N) muxhigh(d3, d2, s[0], bhigh);
mux2 #(N) muxlow( d1, d0, s[0], blow);
mux2 #(N) muxfinal(bhigh, blow, s[1], data);
endmodule | 0 |
6,534 | data/full_repos/permissive/116563702/muxs with paramatirization/testbench.v | 116,563,702 | testbench.v | v | 28 | 78 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Error: Cannot find file containing module: with\n ... Looked in:\n data/full_repos/permissive/116563702/muxs/with\n data/full_repos/permissive/116563702/muxs/with.v\n data/full_repos/permissive/116563702/muxs/with.sv\n with\n with.v\n with.sv\n obj_dir/with\n obj_dir/with.v\n obj_dir/with.sv\n%Error: Cannot find file containing module: paramatirization,data/full_repos/permissive/116563702\n%Error: Cannot find file containing module: data/full_repos/permissive/116563702/muxs\n%Error: Cannot find file containing module: paramatirization/testbench.v\n%Error: Exiting due to 4 error(s)\n' | 7,458 | module | module testbench;
reg [1:0] s;
reg [3:0] a, b, c, d;
wire [3:0] y;
initial
begin
$monitor (" A = %b B = %b C = %b D = %b s = %b y = %b",a,b,c,d, s, y);
a = 1;
b = 2;
c = 3;
d = 4;
s=0;
#10 s=1;
#10 s=2;
#10 s=3;
#10 $finish;
end
mux4 uut(a, b, c, d, s, y);
endmodule | module testbench; |
reg [1:0] s;
reg [3:0] a, b, c, d;
wire [3:0] y;
initial
begin
$monitor (" A = %b B = %b C = %b D = %b s = %b y = %b",a,b,c,d, s, y);
a = 1;
b = 2;
c = 3;
d = 4;
s=0;
#10 s=1;
#10 s=2;
#10 s=3;
#10 $finish;
end
mux4 uut(a, b, c, d, s, y);
endmodule | 0 |
6,535 | data/full_repos/permissive/116563702/muxs with paramatirization/testbench_mux2_tristate.v | 116,563,702 | testbench_mux2_tristate.v | v | 22 | 26 | [] | [] | [] | null | line:17: before: "$" | null | 1: b'%Error: Cannot find file containing module: with\n ... Looked in:\n data/full_repos/permissive/116563702/muxs/with\n data/full_repos/permissive/116563702/muxs/with.v\n data/full_repos/permissive/116563702/muxs/with.sv\n with\n with.v\n with.sv\n obj_dir/with\n obj_dir/with.v\n obj_dir/with.sv\n%Error: Cannot find file containing module: paramatirization,data/full_repos/permissive/116563702\n%Error: Cannot find file containing module: data/full_repos/permissive/116563702/muxs\n%Error: Cannot find file containing module: paramatirization/testbench_mux2_tristate.v\n%Error: Exiting due to 4 error(s)\n' | 7,459 | module | module testbench;
reg [3:0] a, b;
reg s;
wire [3:0] y;
initial
begin
s = 0;
a = 1;
b = 2;
#5 a = 4;
#5 s = 1;
#5 a = 3;
#5 s = 0;
#5 $finish;
end
mux2 uut(a, b, s, y);
endmodule | module testbench; |
reg [3:0] a, b;
reg s;
wire [3:0] y;
initial
begin
s = 0;
a = 1;
b = 2;
#5 a = 4;
#5 s = 1;
#5 a = 3;
#5 s = 0;
#5 $finish;
end
mux2 uut(a, b, s, y);
endmodule | 0 |
6,536 | data/full_repos/permissive/116563702/muxs with paramatirization/testbench_tristate.v | 116,563,702 | testbench_tristate.v | v | 21 | 29 | [] | [] | [] | null | line:15: before: "$" | null | 1: b'%Error: Cannot find file containing module: with\n ... Looked in:\n data/full_repos/permissive/116563702/muxs/with\n data/full_repos/permissive/116563702/muxs/with.v\n data/full_repos/permissive/116563702/muxs/with.sv\n with\n with.v\n with.sv\n obj_dir/with\n obj_dir/with.v\n obj_dir/with.sv\n%Error: Cannot find file containing module: paramatirization,data/full_repos/permissive/116563702\n%Error: Cannot find file containing module: data/full_repos/permissive/116563702/muxs\n%Error: Cannot find file containing module: paramatirization/testbench_tristate.v\n%Error: Exiting due to 4 error(s)\n' | 7,460 | module | module testbench;
reg s;
reg [3:0] data;
wire [3:0] y;
initial
begin
s=0;
data=4;
#5 data=3;
#5 s=1;
#5 data=6;
#5 $finish;
end
tristate uut(data, s, y);
endmodule | module testbench; |
reg s;
reg [3:0] data;
wire [3:0] y;
initial
begin
s=0;
data=4;
#5 data=3;
#5 s=1;
#5 data=6;
#5 $finish;
end
tristate uut(data, s, y);
endmodule | 0 |
6,537 | data/full_repos/permissive/116563702/muxs with paramatirization/tristateBuffer.v | 116,563,702 | tristateBuffer.v | v | 9 | 54 | [] | [] | [] | [(3, 8)] | null | null | 1: b'%Error: Cannot find file containing module: with\n ... Looked in:\n data/full_repos/permissive/116563702/muxs/with\n data/full_repos/permissive/116563702/muxs/with.v\n data/full_repos/permissive/116563702/muxs/with.sv\n with\n with.v\n with.sv\n obj_dir/with\n obj_dir/with.v\n obj_dir/with.sv\n%Error: Cannot find file containing module: paramatirization,data/full_repos/permissive/116563702\n%Error: Cannot find file containing module: data/full_repos/permissive/116563702/muxs\n%Error: Cannot find file containing module: paramatirization/tristateBuffer.v\n%Error: Exiting due to 4 error(s)\n' | 7,461 | module | module tristate #(parameter N=4) (input [N-1:0] data,
input s,
output [N-1:0] bus);
assign bus = s ? data : 'bz;
endmodule | module tristate #(parameter N=4) (input [N-1:0] data,
input s,
output [N-1:0] bus); |
assign bus = s ? data : 'bz;
endmodule | 0 |
6,538 | data/full_repos/permissive/116563702/priority_encoder/pri_encoder.v | 116,563,702 | pri_encoder.v | v | 20 | 39 | [] | [] | [] | [(3, 19)] | null | data/verilator_xmls/83298b3a-2668-458e-a747-ee0f2a8cf22a.xml | null | 7,462 | module | module priority_encoder(input [3:0] a,
output reg [3:0] y);
always @(a)
begin
if (a[3])
y = 4'b1000;
else if (a[2])
y = 4'b0100;
else if (a[1])
y = 4'b0010;
else if(a[0])
y = 4'b0001;
else
y = 4'b0000;
end
endmodule | module priority_encoder(input [3:0] a,
output reg [3:0] y); |
always @(a)
begin
if (a[3])
y = 4'b1000;
else if (a[2])
y = 4'b0100;
else if (a[1])
y = 4'b0010;
else if(a[0])
y = 4'b0001;
else
y = 4'b0000;
end
endmodule | 0 |
6,539 | data/full_repos/permissive/116563702/priority_encoder/pri_encoder_casez.v | 116,563,702 | pri_encoder_casez.v | v | 17 | 38 | [] | [] | [] | [(3, 16)] | null | data/verilator_xmls/fab37fb0-cd75-4504-897c-fe1d1a4ccfeb.xml | null | 7,463 | module | module pri_using_casez(input [3:0] a,
output reg [3:0] y);
always @(a)
begin
casez (a)
4'b1??? : y = 4'b1000;
4'b01?? : y = 4'b0100;
4'b001? : y = 4'b0010;
4'b0001 : y = 4'b0001;
default : y = 4'b0000;
endcase
end
endmodule | module pri_using_casez(input [3:0] a,
output reg [3:0] y); |
always @(a)
begin
casez (a)
4'b1??? : y = 4'b1000;
4'b01?? : y = 4'b0100;
4'b001? : y = 4'b0010;
4'b0001 : y = 4'b0001;
default : y = 4'b0000;
endcase
end
endmodule | 0 |
6,540 | data/full_repos/permissive/116563702/register/regSyncReset.v | 116,563,702 | regSyncReset.v | v | 17 | 27 | [] | [] | [] | [(3, 16)] | null | data/verilator_xmls/2410d103-728a-4454-982a-366b04d3c271.xml | null | 7,465 | module | module register(input clk,
input reset,
input en,
input [3:0] data,
output reg [3:0] q);
always @(posedge clk)
begin
if (reset)
q <= 4'b0;
else if (en)
q <= data;
end
endmodule | module register(input clk,
input reset,
input en,
input [3:0] data,
output reg [3:0] q); |
always @(posedge clk)
begin
if (reset)
q <= 4'b0;
else if (en)
q <= data;
end
endmodule | 0 |
6,541 | data/full_repos/permissive/116563702/sevensegmentdisplay/ssd.v | 116,563,702 | ssd.v | v | 26 | 33 | [] | [] | [] | [(3, 24)] | null | data/verilator_xmls/a7f41366-c305-4de8-be54-28619e454b75.xml | null | 7,467 | module | module ssd( input [3:0] data,
output reg [6:0] segments);
always @(data)
begin
case(data)
0: segments = 7'b1111_110;
1: segments = 7'b0110_000;
2: segments = 7'b1101_101;
3: segments = 7'b1111_001;
4: segments = 7'b0110_011;
5: segments = 7'b1011_011;
6: segments = 7'b1011_111;
7: segments = 7'b1110_000;
8: segments = 7'b1111_111;
9: segments = 7'b1111_011;
default:
segments = 7'b0000_000;
endcase
end
endmodule | module ssd( input [3:0] data,
output reg [6:0] segments); |
always @(data)
begin
case(data)
0: segments = 7'b1111_110;
1: segments = 7'b0110_000;
2: segments = 7'b1101_101;
3: segments = 7'b1111_001;
4: segments = 7'b0110_011;
5: segments = 7'b1011_011;
6: segments = 7'b1011_111;
7: segments = 7'b1110_000;
8: segments = 7'b1111_111;
9: segments = 7'b1111_011;
default:
segments = 7'b0000_000;
endcase
end
endmodule | 0 |
6,542 | data/full_repos/permissive/116563702/tristateBuffer/tristateBuffer.v | 116,563,702 | tristateBuffer.v | v | 9 | 34 | [] | [] | [] | [(3, 8)] | null | data/verilator_xmls/3df8747e-b58e-4420-b35a-9d0c1052af02.xml | null | 7,468 | module | module tristate(input [3:0] data,
input s,
output [3:0] bus);
assign bus = s ? data : 4'bz;
endmodule | module tristate(input [3:0] data,
input s,
output [3:0] bus); |
assign bus = s ? data : 4'bz;
endmodule | 0 |
6,543 | data/full_repos/permissive/116588652/fpga/10M16SAE144C8G/memory.v | 116,588,652 | memory.v | v | 168 | 80 | [] | [] | [] | null | line:135: before: "." | null | 1: b"%Error: data/full_repos/permissive/116588652/fpga/10M16SAE144C8G/memory.v:105: Cannot find file containing module: 'altsyncram'\naltsyncram altsyncram_i (\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116588652/fpga/10M16SAE144C8G,data/full_repos/permissive/116588652/altsyncram\n data/full_repos/permissive/116588652/fpga/10M16SAE144C8G,data/full_repos/permissive/116588652/altsyncram.v\n data/full_repos/permissive/116588652/fpga/10M16SAE144C8G,data/full_repos/permissive/116588652/altsyncram.sv\n altsyncram\n altsyncram.v\n altsyncram.sv\n obj_dir/altsyncram\n obj_dir/altsyncram.v\n obj_dir/altsyncram.sv\n%Error: Exiting due to 1 error(s)\n" | 7,469 | module | module memory #(
parameter SIZE = 8192,
parameter FIRMWARE = ""
)(
input clk_i,
input reset_i,
input [31:0] iaddr_i,
output [31:0] irdata_o,
input ird_i,
input [31:0] daddr_i,
input [31:0] dwdata_i,
output [31:0] drdata_o,
input [1:0] dsize_i,
input drd_i,
input dwr_i
);
localparam
SIZE_BYTE = 2'd0,
SIZE_HALF = 2'd1,
SIZE_WORD = 2'd2;
localparam
DEPTH = $clog2(SIZE);
wire [31:0] dwdata_w =
(SIZE_BYTE == dsize_i) ? {4{dwdata_i[7:0]}} :
(SIZE_HALF == dsize_i) ? {2{dwdata_i[15:0]}} : dwdata_i;
wire [3:0] dbe_byte_w =
(2'b00 == daddr_i[1:0]) ? 4'b0001 :
(2'b01 == daddr_i[1:0]) ? 4'b0010 :
(2'b10 == daddr_i[1:0]) ? 4'b0100 : 4'b1000;
wire [3:0] dbe_half_w =
daddr_i[1] ? 4'b1100 : 4'b0011;
wire [3:0] dbe_w =
(SIZE_BYTE == dsize_i) ? dbe_byte_w :
(SIZE_HALF == dsize_i) ? dbe_half_w : 4'b1111;
wire [7:0] rdata_byte_w =
(2'b00 == daddr_r) ? drdata_w[7:0] :
(2'b01 == daddr_r) ? drdata_w[15:8] :
(2'b10 == daddr_r) ? drdata_w[23:16] : drdata_w[31:24];
wire [15:0] rdata_half_w =
daddr_r[1] ? drdata_w[31:16] : drdata_w[15:0];
assign drdata_o =
(SIZE_BYTE == dsize_r) ? { 24'h0, rdata_byte_w } :
(SIZE_HALF == dsize_r) ? { 16'h0, rdata_half_w } : drdata_w;
reg [1:0] daddr_r;
reg [1:0] dsize_r;
always @(posedge clk_i) begin
if (reset_i) begin
daddr_r <= 2'b00;
dsize_r <= SIZE_BYTE;
end else begin
daddr_r <= daddr_i[1:0];
dsize_r <= dsize_i;
end
end
wire [31:0] drdata_w;
altsyncram altsyncram_i (
.clock0(clk_i),
.aclr0 (reset_i),
.address_a(iaddr_i[31:2]),
.data_a(32'h0),
.rden_a(ird_i),
.wren_a(1'b0),
.q_a(irdata_o),
.address_b(daddr_i[31:2]),
.byteena_b(dbe_w),
.data_b(dwdata_w),
.rden_b(drd_i),
.wren_b(dwr_i),
.q_b(drdata_w),
.aclr1(1'b0),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.eccstatus()
);
defparam
altsyncram_i.address_reg_b = "CLOCK0",
altsyncram_i.byteena_reg_b = "CLOCK0",
altsyncram_i.byte_size = 8,
altsyncram_i.clock_enable_input_a = "BYPASS",
altsyncram_i.clock_enable_input_b = "BYPASS",
altsyncram_i.clock_enable_output_a = "BYPASS",
altsyncram_i.clock_enable_output_b = "BYPASS",
altsyncram_i.indata_reg_b = "CLOCK0",
altsyncram_i.init_file = FIRMWARE,
altsyncram_i.intended_device_family = "MAX 10",
altsyncram_i.lpm_type = "altsyncram",
altsyncram_i.numwords_a = SIZE / 4,
altsyncram_i.numwords_b = SIZE / 4,
altsyncram_i.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_i.outdata_aclr_a = "CLEAR0",
altsyncram_i.outdata_aclr_b = "CLEAR0",
altsyncram_i.outdata_reg_a = "UNREGISTERED",
altsyncram_i.outdata_reg_b = "UNREGISTERED",
altsyncram_i.power_up_uninitialized = "FALSE",
altsyncram_i.ram_block_type = "M9K",
altsyncram_i.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_i.read_during_write_mode_port_a = "NEW_DATA_WITH_NBE_READ",
altsyncram_i.read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ",
altsyncram_i.widthad_a = DEPTH,
altsyncram_i.widthad_b = DEPTH,
altsyncram_i.width_a = 32,
altsyncram_i.width_b = 32,
altsyncram_i.width_byteena_a = 1,
altsyncram_i.width_byteena_b = 4,
altsyncram_i.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule | module memory #(
parameter SIZE = 8192,
parameter FIRMWARE = ""
)(
input clk_i,
input reset_i,
input [31:0] iaddr_i,
output [31:0] irdata_o,
input ird_i,
input [31:0] daddr_i,
input [31:0] dwdata_i,
output [31:0] drdata_o,
input [1:0] dsize_i,
input drd_i,
input dwr_i
); |
localparam
SIZE_BYTE = 2'd0,
SIZE_HALF = 2'd1,
SIZE_WORD = 2'd2;
localparam
DEPTH = $clog2(SIZE);
wire [31:0] dwdata_w =
(SIZE_BYTE == dsize_i) ? {4{dwdata_i[7:0]}} :
(SIZE_HALF == dsize_i) ? {2{dwdata_i[15:0]}} : dwdata_i;
wire [3:0] dbe_byte_w =
(2'b00 == daddr_i[1:0]) ? 4'b0001 :
(2'b01 == daddr_i[1:0]) ? 4'b0010 :
(2'b10 == daddr_i[1:0]) ? 4'b0100 : 4'b1000;
wire [3:0] dbe_half_w =
daddr_i[1] ? 4'b1100 : 4'b0011;
wire [3:0] dbe_w =
(SIZE_BYTE == dsize_i) ? dbe_byte_w :
(SIZE_HALF == dsize_i) ? dbe_half_w : 4'b1111;
wire [7:0] rdata_byte_w =
(2'b00 == daddr_r) ? drdata_w[7:0] :
(2'b01 == daddr_r) ? drdata_w[15:8] :
(2'b10 == daddr_r) ? drdata_w[23:16] : drdata_w[31:24];
wire [15:0] rdata_half_w =
daddr_r[1] ? drdata_w[31:16] : drdata_w[15:0];
assign drdata_o =
(SIZE_BYTE == dsize_r) ? { 24'h0, rdata_byte_w } :
(SIZE_HALF == dsize_r) ? { 16'h0, rdata_half_w } : drdata_w;
reg [1:0] daddr_r;
reg [1:0] dsize_r;
always @(posedge clk_i) begin
if (reset_i) begin
daddr_r <= 2'b00;
dsize_r <= SIZE_BYTE;
end else begin
daddr_r <= daddr_i[1:0];
dsize_r <= dsize_i;
end
end
wire [31:0] drdata_w;
altsyncram altsyncram_i (
.clock0(clk_i),
.aclr0 (reset_i),
.address_a(iaddr_i[31:2]),
.data_a(32'h0),
.rden_a(ird_i),
.wren_a(1'b0),
.q_a(irdata_o),
.address_b(daddr_i[31:2]),
.byteena_b(dbe_w),
.data_b(dwdata_w),
.rden_b(drd_i),
.wren_b(dwr_i),
.q_b(drdata_w),
.aclr1(1'b0),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.eccstatus()
);
defparam
altsyncram_i.address_reg_b = "CLOCK0",
altsyncram_i.byteena_reg_b = "CLOCK0",
altsyncram_i.byte_size = 8,
altsyncram_i.clock_enable_input_a = "BYPASS",
altsyncram_i.clock_enable_input_b = "BYPASS",
altsyncram_i.clock_enable_output_a = "BYPASS",
altsyncram_i.clock_enable_output_b = "BYPASS",
altsyncram_i.indata_reg_b = "CLOCK0",
altsyncram_i.init_file = FIRMWARE,
altsyncram_i.intended_device_family = "MAX 10",
altsyncram_i.lpm_type = "altsyncram",
altsyncram_i.numwords_a = SIZE / 4,
altsyncram_i.numwords_b = SIZE / 4,
altsyncram_i.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_i.outdata_aclr_a = "CLEAR0",
altsyncram_i.outdata_aclr_b = "CLEAR0",
altsyncram_i.outdata_reg_a = "UNREGISTERED",
altsyncram_i.outdata_reg_b = "UNREGISTERED",
altsyncram_i.power_up_uninitialized = "FALSE",
altsyncram_i.ram_block_type = "M9K",
altsyncram_i.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_i.read_during_write_mode_port_a = "NEW_DATA_WITH_NBE_READ",
altsyncram_i.read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ",
altsyncram_i.widthad_a = DEPTH,
altsyncram_i.widthad_b = DEPTH,
altsyncram_i.width_a = 32,
altsyncram_i.width_b = 32,
altsyncram_i.width_byteena_a = 1,
altsyncram_i.width_byteena_b = 4,
altsyncram_i.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule | 71 |
6,548 | data/full_repos/permissive/116588652/rtl/per_uart.v | 116,588,652 | per_uart.v | v | 195 | 80 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/116588652/rtl/per_uart.v:96: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'tx_bit_cnt_r\' generates 4 bits.\n : ... In instance per_uart\n end else if (tx_bit_cnt_r) begin\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/116588652/rtl/per_uart.v:127: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n : ... In instance per_uart\n rx_shifter_r <= 10\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116588652/rtl/per_uart.v:142: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n : ... In instance per_uart\n rx_shifter_r <= 10\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116588652/rtl/per_uart.v:144: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'rx_br_cnt_r\' generates 16 bits.\n : ... In instance per_uart\n if (rx_br_cnt_r)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116588652/rtl/per_uart.v:129: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'rx_bit_cnt_r\' generates 4 bits.\n : ... In instance per_uart\n end else if (rx_bit_cnt_r) begin\n ^~\n%Error: Exiting due to 5 warning(s)\n' | 7,474 | module | module per_uart (
input clk_i,
input reset_i,
input [31:0] addr_i,
input [31:0] wdata_i,
output [31:0] rdata_o,
input [1:0] size_i,
input rd_i,
input wr_i,
input uart_rx_i,
output uart_tx_o
);
localparam
REG_CSR = 8'h00,
REG_BR = 8'h04,
REG_DATA = 8'h08;
localparam
BIT_CSR_TX_READY = 0,
BIT_CSR_RX_READY = 1;
wire reg_csr_w = (REG_CSR == addr_i[7:0]);
wire reg_br_w = (REG_BR == addr_i[7:0]);
wire reg_data_w = (REG_DATA == addr_i[7:0]);
reg [15:0] br_r;
always @(posedge clk_i) begin
if (reset_i)
br_r <= 16'h0;
else if (wr_i && reg_br_w)
br_r <= wdata_i[15:0];
end
`ifdef SIMULATOR
always @(posedge clk_i) begin
if (wr_i && reg_data_w)
$write("%c", wdata_i[7:0]);
end
assign uart_tx_o = 1'b1;
`else
reg [15:0] tx_br_cnt_r;
reg [3:0] tx_bit_cnt_r;
reg [9:0] tx_shifter_r;
reg tx_ready_r;
always @(posedge clk_i) begin
if (reset_i) begin
tx_br_cnt_r <= 16'd0;
tx_bit_cnt_r <= 4'd0;
tx_shifter_r <= 10'h1;
tx_ready_r <= 1'b1;
end else if (tx_bit_cnt_r) begin
if (tx_br_cnt_r == br_r) begin
tx_shifter_r <= { 1'b1, tx_shifter_r[9:1] };
tx_bit_cnt_r <= tx_bit_cnt_r - 4'd1;
tx_br_cnt_r <= 16'd0;
end else begin
tx_br_cnt_r <= tx_br_cnt_r + 16'd1;
end
end else if (!tx_ready_r) begin
tx_ready_r <= 1'b1;
end else if (wr_i && reg_data_w) begin
tx_shifter_r <= { 1'b1, wdata_i[7:0], 1'b0 };
tx_bit_cnt_r <= 4'd10;
tx_ready_r <= 1'b0;
end
end
assign uart_tx_o = tx_shifter_r[0];
`endif
reg [15:0] rx_br_cnt_r;
reg [3:0] rx_bit_cnt_r;
reg [8:0] rx_shifter_r;
reg [7:0] rx_data_r;
reg rx_done_r;
always @(posedge clk_i) begin
if (reset_i) begin
rx_br_cnt_r <= 16'd1;
rx_bit_cnt_r <= 4'd0;
rx_shifter_r <= 10'h0;
rx_done_r <= 1'b0;
end else if (rx_bit_cnt_r) begin
if (rx_br_cnt_r == br_r) begin
rx_shifter_r <= { uart_rx_i, rx_shifter_r[8:1] };
rx_bit_cnt_r <= rx_bit_cnt_r - 4'd1;
rx_br_cnt_r <= 16'd0;
end else begin
rx_br_cnt_r <= rx_br_cnt_r + 16'd1;
end
end else if (rx_done_r) begin
rx_done_r <= 1'b0;
end else if (rx_shifter_r[8]) begin
rx_data_r <= rx_shifter_r[7:0];
rx_done_r <= 1'b1;
rx_shifter_r <= 10'h0;
end else if (!uart_rx_i) begin
if (rx_br_cnt_r)
rx_br_cnt_r <= rx_br_cnt_r - 16'd1;
else
rx_bit_cnt_r <= 4'd9;
end else begin
rx_br_cnt_r <= { 1'b0, br_r[15:1] };
end
end
reg rx_ready_r;
always @(posedge clk_i) begin
if (reset_i)
rx_ready_r <= 1'b0;
else if (rx_done_r)
rx_ready_r <= 1'b1;
else if (rd_i && reg_data_w)
rx_ready_r <= 1'b0;
end
reg [31:0] reg_data_r;
always @(posedge clk_i) begin
if (reset_i)
reg_data_r <= csr_w;
else if (reg_data_w)
reg_data_r <= { 24'h0, rx_data_r };
else
reg_data_r <= csr_w;
end
wire [31:0] csr_w;
`ifdef SIMULATOR
assign csr_w[BIT_CSR_TX_READY] = 1'b1;
assign csr_w[BIT_CSR_RX_READY] = 1'b0;
`else
assign csr_w[BIT_CSR_TX_READY] = tx_ready_r;
assign csr_w[BIT_CSR_RX_READY] = rx_ready_r;
`endif
assign csr_w[31:2] = 30'h0;
assign rdata_o = reg_data_r;
endmodule | module per_uart (
input clk_i,
input reset_i,
input [31:0] addr_i,
input [31:0] wdata_i,
output [31:0] rdata_o,
input [1:0] size_i,
input rd_i,
input wr_i,
input uart_rx_i,
output uart_tx_o
); |
localparam
REG_CSR = 8'h00,
REG_BR = 8'h04,
REG_DATA = 8'h08;
localparam
BIT_CSR_TX_READY = 0,
BIT_CSR_RX_READY = 1;
wire reg_csr_w = (REG_CSR == addr_i[7:0]);
wire reg_br_w = (REG_BR == addr_i[7:0]);
wire reg_data_w = (REG_DATA == addr_i[7:0]);
reg [15:0] br_r;
always @(posedge clk_i) begin
if (reset_i)
br_r <= 16'h0;
else if (wr_i && reg_br_w)
br_r <= wdata_i[15:0];
end
`ifdef SIMULATOR
always @(posedge clk_i) begin
if (wr_i && reg_data_w)
$write("%c", wdata_i[7:0]);
end
assign uart_tx_o = 1'b1;
`else
reg [15:0] tx_br_cnt_r;
reg [3:0] tx_bit_cnt_r;
reg [9:0] tx_shifter_r;
reg tx_ready_r;
always @(posedge clk_i) begin
if (reset_i) begin
tx_br_cnt_r <= 16'd0;
tx_bit_cnt_r <= 4'd0;
tx_shifter_r <= 10'h1;
tx_ready_r <= 1'b1;
end else if (tx_bit_cnt_r) begin
if (tx_br_cnt_r == br_r) begin
tx_shifter_r <= { 1'b1, tx_shifter_r[9:1] };
tx_bit_cnt_r <= tx_bit_cnt_r - 4'd1;
tx_br_cnt_r <= 16'd0;
end else begin
tx_br_cnt_r <= tx_br_cnt_r + 16'd1;
end
end else if (!tx_ready_r) begin
tx_ready_r <= 1'b1;
end else if (wr_i && reg_data_w) begin
tx_shifter_r <= { 1'b1, wdata_i[7:0], 1'b0 };
tx_bit_cnt_r <= 4'd10;
tx_ready_r <= 1'b0;
end
end
assign uart_tx_o = tx_shifter_r[0];
`endif
reg [15:0] rx_br_cnt_r;
reg [3:0] rx_bit_cnt_r;
reg [8:0] rx_shifter_r;
reg [7:0] rx_data_r;
reg rx_done_r;
always @(posedge clk_i) begin
if (reset_i) begin
rx_br_cnt_r <= 16'd1;
rx_bit_cnt_r <= 4'd0;
rx_shifter_r <= 10'h0;
rx_done_r <= 1'b0;
end else if (rx_bit_cnt_r) begin
if (rx_br_cnt_r == br_r) begin
rx_shifter_r <= { uart_rx_i, rx_shifter_r[8:1] };
rx_bit_cnt_r <= rx_bit_cnt_r - 4'd1;
rx_br_cnt_r <= 16'd0;
end else begin
rx_br_cnt_r <= rx_br_cnt_r + 16'd1;
end
end else if (rx_done_r) begin
rx_done_r <= 1'b0;
end else if (rx_shifter_r[8]) begin
rx_data_r <= rx_shifter_r[7:0];
rx_done_r <= 1'b1;
rx_shifter_r <= 10'h0;
end else if (!uart_rx_i) begin
if (rx_br_cnt_r)
rx_br_cnt_r <= rx_br_cnt_r - 16'd1;
else
rx_bit_cnt_r <= 4'd9;
end else begin
rx_br_cnt_r <= { 1'b0, br_r[15:1] };
end
end
reg rx_ready_r;
always @(posedge clk_i) begin
if (reset_i)
rx_ready_r <= 1'b0;
else if (rx_done_r)
rx_ready_r <= 1'b1;
else if (rd_i && reg_data_w)
rx_ready_r <= 1'b0;
end
reg [31:0] reg_data_r;
always @(posedge clk_i) begin
if (reset_i)
reg_data_r <= csr_w;
else if (reg_data_w)
reg_data_r <= { 24'h0, rx_data_r };
else
reg_data_r <= csr_w;
end
wire [31:0] csr_w;
`ifdef SIMULATOR
assign csr_w[BIT_CSR_TX_READY] = 1'b1;
assign csr_w[BIT_CSR_RX_READY] = 1'b0;
`else
assign csr_w[BIT_CSR_TX_READY] = tx_ready_r;
assign csr_w[BIT_CSR_RX_READY] = rx_ready_r;
`endif
assign csr_w[31:2] = 30'h0;
assign rdata_o = reg_data_r;
endmodule | 71 |
6,549 | data/full_repos/permissive/116588652/rtl/soc.v | 116,588,652 | soc.v | v | 185 | 80 | [] | [] | [] | [(31, 183)] | null | null | 1: b"%Error: data/full_repos/permissive/116588652/rtl/soc.v:59: Cannot find file containing module: 'riscv_core'\nriscv_core #(\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116588652/rtl,data/full_repos/permissive/116588652/riscv_core\n data/full_repos/permissive/116588652/rtl,data/full_repos/permissive/116588652/riscv_core.v\n data/full_repos/permissive/116588652/rtl,data/full_repos/permissive/116588652/riscv_core.sv\n riscv_core\n riscv_core.v\n riscv_core.sv\n obj_dir/riscv_core\n obj_dir/riscv_core.v\n obj_dir/riscv_core.sv\n%Error: data/full_repos/permissive/116588652/rtl/soc.v:95: Cannot find file containing module: 'bus_mux'\nbus_mux #(\n^~~~~~~\n%Error: data/full_repos/permissive/116588652/rtl/soc.v:119: Cannot find file containing module: 'memory'\nmemory #(\n^~~~~~\n%Error: data/full_repos/permissive/116588652/rtl/soc.v:139: Cannot find file containing module: 'per_uart'\nper_uart per_uart_i (\n^~~~~~~~\n%Error: data/full_repos/permissive/116588652/rtl/soc.v:155: Cannot find file containing module: 'per_gpio'\nper_gpio per_gpio_i (\n^~~~~~~~\n%Error: data/full_repos/permissive/116588652/rtl/soc.v:171: Cannot find file containing module: 'per_timer'\nper_timer per_timer_i (\n^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n" | 7,476 | module | module soc #(
parameter MEM_SIZE = 8192,
parameter FIRMWARE = ""
)(
input clk_i,
input reset_i,
output lock_o,
input uart_rx_i,
output uart_tx_o,
input [31:0] gpio_in_i,
output [31:0] gpio_out_o
);
wire [31:0] iaddr_w;
wire [31:0] irdata_w;
wire ird_w;
wire [31:0] daddr_w;
wire [31:0] dwdata_w;
wire [31:0] drdata_w;
wire [1:0] dsize_w;
wire drd_w;
wire dwr_w;
riscv_core #(
.PC_SIZE(16),
.RESET_SP(MEM_SIZE)
) core_i (
.clk_i(clk_i),
.reset_i(reset_i),
.lock_o(lock_o),
.iaddr_o(iaddr_w),
.irdata_i(irdata_w),
.ird_o(ird_w),
.daddr_o(daddr_w),
.dwdata_o(dwdata_w),
.drdata_i(drdata_w),
.dsize_o(dsize_w),
.drd_o(drd_w),
.dwr_o(dwr_w)
);
localparam N_SLAVES = 4;
wire [31:0] mem_addr_w, uart_addr_w, gpio_addr_w, timer_addr_w;
wire [31:0] mem_wdata_w, uart_wdata_w, gpio_wdata_w, timer_wdata_w;
wire [31:0] mem_rdata_w, uart_rdata_w, gpio_rdata_w, timer_rdata_w;
wire [1:0] mem_size_w, uart_size_w, gpio_size_w, timer_size_w;
wire mem_rd_w, uart_rd_w, gpio_rd_w, timer_rd_w;
wire mem_wr_w, uart_wr_w, gpio_wr_w, timer_wr_w;
wire mem_sel_w = (4'h0 == daddr_w[31:28]);
wire uart_sel_w = (4'h1 == daddr_w[31:28]);
wire gpio_sel_w = (4'h2 == daddr_w[31:28]);
wire timer_sel_w = (4'h3 == daddr_w[31:28]);
bus_mux #(
.N(N_SLAVES)
) bus_mux_i (
.clk_i(clk_i),
.reset_i(reset_i),
.ss_i({ mem_sel_w, uart_sel_w, gpio_sel_w, timer_sel_w }),
.m_addr_i(daddr_w),
.m_wdata_i(dwdata_w),
.m_rdata_o(drdata_w),
.m_size_i(dsize_w),
.m_rd_i(drd_w),
.m_wr_i(dwr_w),
.s_addr_o({ mem_addr_w, uart_addr_w, gpio_addr_w, timer_addr_w }),
.s_wdata_o({ mem_wdata_w, uart_wdata_w, gpio_wdata_w, timer_wdata_w }),
.s_rdata_i({ mem_rdata_w, uart_rdata_w, gpio_rdata_w, timer_rdata_w }),
.s_size_o({ mem_size_w, uart_size_w, gpio_size_w, timer_size_w }),
.s_rd_o({ mem_rd_w, uart_rd_w, gpio_rd_w, timer_rd_w }),
.s_wr_o({ mem_wr_w, uart_wr_w, gpio_wr_w, timer_wr_w })
);
memory #(
.SIZE(MEM_SIZE),
.FIRMWARE(FIRMWARE)
) memory_i (
.clk_i(clk_i),
.reset_i(reset_i),
.iaddr_i(iaddr_w),
.irdata_o(irdata_w),
.ird_i(ird_w),
.daddr_i(mem_addr_w),
.dwdata_i(mem_wdata_w),
.drdata_o(mem_rdata_w),
.dsize_i(mem_size_w),
.drd_i(mem_rd_w),
.dwr_i(mem_wr_w)
);
per_uart per_uart_i (
.clk_i(clk_i),
.reset_i(reset_i),
.addr_i(uart_addr_w),
.wdata_i(uart_wdata_w),
.rdata_o(uart_rdata_w),
.size_i(uart_size_w),
.rd_i(uart_rd_w),
.wr_i(uart_wr_w),
.uart_rx_i(uart_rx_i),
.uart_tx_o(uart_tx_o)
);
per_gpio per_gpio_i (
.clk_i(clk_i),
.reset_i(reset_i),
.addr_i(gpio_addr_w),
.wdata_i(gpio_wdata_w),
.rdata_o(gpio_rdata_w),
.size_i(gpio_size_w),
.rd_i(gpio_rd_w),
.wr_i(gpio_wr_w),
.gpio_in_i(gpio_in_i),
.gpio_out_o(gpio_out_o)
);
per_timer per_timer_i (
.clk_i(clk_i),
.reset_i(reset_i),
.addr_i(timer_addr_w),
.wdata_i(timer_wdata_w),
.rdata_o(timer_rdata_w),
.size_i(timer_size_w),
.rd_i(timer_rd_w),
.wr_i(timer_wr_w)
);
endmodule | module soc #(
parameter MEM_SIZE = 8192,
parameter FIRMWARE = ""
)(
input clk_i,
input reset_i,
output lock_o,
input uart_rx_i,
output uart_tx_o,
input [31:0] gpio_in_i,
output [31:0] gpio_out_o
); |
wire [31:0] iaddr_w;
wire [31:0] irdata_w;
wire ird_w;
wire [31:0] daddr_w;
wire [31:0] dwdata_w;
wire [31:0] drdata_w;
wire [1:0] dsize_w;
wire drd_w;
wire dwr_w;
riscv_core #(
.PC_SIZE(16),
.RESET_SP(MEM_SIZE)
) core_i (
.clk_i(clk_i),
.reset_i(reset_i),
.lock_o(lock_o),
.iaddr_o(iaddr_w),
.irdata_i(irdata_w),
.ird_o(ird_w),
.daddr_o(daddr_w),
.dwdata_o(dwdata_w),
.drdata_i(drdata_w),
.dsize_o(dsize_w),
.drd_o(drd_w),
.dwr_o(dwr_w)
);
localparam N_SLAVES = 4;
wire [31:0] mem_addr_w, uart_addr_w, gpio_addr_w, timer_addr_w;
wire [31:0] mem_wdata_w, uart_wdata_w, gpio_wdata_w, timer_wdata_w;
wire [31:0] mem_rdata_w, uart_rdata_w, gpio_rdata_w, timer_rdata_w;
wire [1:0] mem_size_w, uart_size_w, gpio_size_w, timer_size_w;
wire mem_rd_w, uart_rd_w, gpio_rd_w, timer_rd_w;
wire mem_wr_w, uart_wr_w, gpio_wr_w, timer_wr_w;
wire mem_sel_w = (4'h0 == daddr_w[31:28]);
wire uart_sel_w = (4'h1 == daddr_w[31:28]);
wire gpio_sel_w = (4'h2 == daddr_w[31:28]);
wire timer_sel_w = (4'h3 == daddr_w[31:28]);
bus_mux #(
.N(N_SLAVES)
) bus_mux_i (
.clk_i(clk_i),
.reset_i(reset_i),
.ss_i({ mem_sel_w, uart_sel_w, gpio_sel_w, timer_sel_w }),
.m_addr_i(daddr_w),
.m_wdata_i(dwdata_w),
.m_rdata_o(drdata_w),
.m_size_i(dsize_w),
.m_rd_i(drd_w),
.m_wr_i(dwr_w),
.s_addr_o({ mem_addr_w, uart_addr_w, gpio_addr_w, timer_addr_w }),
.s_wdata_o({ mem_wdata_w, uart_wdata_w, gpio_wdata_w, timer_wdata_w }),
.s_rdata_i({ mem_rdata_w, uart_rdata_w, gpio_rdata_w, timer_rdata_w }),
.s_size_o({ mem_size_w, uart_size_w, gpio_size_w, timer_size_w }),
.s_rd_o({ mem_rd_w, uart_rd_w, gpio_rd_w, timer_rd_w }),
.s_wr_o({ mem_wr_w, uart_wr_w, gpio_wr_w, timer_wr_w })
);
memory #(
.SIZE(MEM_SIZE),
.FIRMWARE(FIRMWARE)
) memory_i (
.clk_i(clk_i),
.reset_i(reset_i),
.iaddr_i(iaddr_w),
.irdata_o(irdata_w),
.ird_i(ird_w),
.daddr_i(mem_addr_w),
.dwdata_i(mem_wdata_w),
.drdata_o(mem_rdata_w),
.dsize_i(mem_size_w),
.drd_i(mem_rd_w),
.dwr_i(mem_wr_w)
);
per_uart per_uart_i (
.clk_i(clk_i),
.reset_i(reset_i),
.addr_i(uart_addr_w),
.wdata_i(uart_wdata_w),
.rdata_o(uart_rdata_w),
.size_i(uart_size_w),
.rd_i(uart_rd_w),
.wr_i(uart_wr_w),
.uart_rx_i(uart_rx_i),
.uart_tx_o(uart_tx_o)
);
per_gpio per_gpio_i (
.clk_i(clk_i),
.reset_i(reset_i),
.addr_i(gpio_addr_w),
.wdata_i(gpio_wdata_w),
.rdata_o(gpio_rdata_w),
.size_i(gpio_size_w),
.rd_i(gpio_rd_w),
.wr_i(gpio_wr_w),
.gpio_in_i(gpio_in_i),
.gpio_out_o(gpio_out_o)
);
per_timer per_timer_i (
.clk_i(clk_i),
.reset_i(reset_i),
.addr_i(timer_addr_w),
.wdata_i(timer_wdata_w),
.rdata_o(timer_rdata_w),
.size_i(timer_size_w),
.rd_i(timer_rd_w),
.wr_i(timer_wr_w)
);
endmodule | 71 |
6,550 | data/full_repos/permissive/116588652/test/memory.v | 116,588,652 | memory.v | v | 148 | 80 | [] | [] | [] | [(31, 146)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/116588652/test/memory.v:116: Bit extraction of array[2047:0] requires 11 bit index, not 12 bits.\n : ... In instance memory\n irdata_r <= mem_r[iaddr_i[DEPTH:2]];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/116588652/test/memory.v:126: Bit extraction of array[2047:0] requires 11 bit index, not 12 bits.\n : ... In instance memory\n drdata_r <= mem_r[daddr_i[DEPTH:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/116588652/test/memory.v:131: Bit extraction of array[2047:0] requires 11 bit index, not 12 bits.\n : ... In instance memory\n mem_r[daddr_i[DEPTH:2]][7:0] <= dwdata_w[7:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/116588652/test/memory.v:134: Bit extraction of array[2047:0] requires 11 bit index, not 12 bits.\n : ... In instance memory\n mem_r[daddr_i[DEPTH:2]][15:8] <= dwdata_w[15:8];\n ^\n%Warning-WIDTH: data/full_repos/permissive/116588652/test/memory.v:137: Bit extraction of array[2047:0] requires 11 bit index, not 12 bits.\n : ... In instance memory\n mem_r[daddr_i[DEPTH:2]][23:16] <= dwdata_w[23:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/116588652/test/memory.v:140: Bit extraction of array[2047:0] requires 11 bit index, not 12 bits.\n : ... In instance memory\n mem_r[daddr_i[DEPTH:2]][31:24] <= dwdata_w[31:24];\n ^\n%Error: Exiting due to 6 warning(s)\n' | 7,477 | module | module memory #(
parameter SIZE = 8192,
parameter FIRMWARE = ""
)(
input clk_i,
input reset_i,
input [31:0] iaddr_i,
output [31:0] irdata_o,
input ird_i,
input [31:0] daddr_i,
input [31:0] dwdata_i,
output [31:0] drdata_o,
input [1:0] dsize_i,
input drd_i,
input dwr_i
);
localparam
SIZE_BYTE = 2'd0,
SIZE_HALF = 2'd1,
SIZE_WORD = 2'd2;
localparam
DEPTH = $clog2(SIZE);
wire [31:0] dwdata_w =
(SIZE_BYTE == dsize_i) ? {4{dwdata_i[7:0]}} :
(SIZE_HALF == dsize_i) ? {2{dwdata_i[15:0]}} : dwdata_i;
wire [3:0] dbe_byte_w =
(2'b00 == daddr_i[1:0]) ? 4'b0001 :
(2'b01 == daddr_i[1:0]) ? 4'b0010 :
(2'b10 == daddr_i[1:0]) ? 4'b0100 : 4'b1000;
wire [3:0] dbe_half_w =
daddr_i[1] ? 4'b1100 : 4'b0011;
wire [3:0] dbe_w =
(SIZE_BYTE == dsize_i) ? dbe_byte_w :
(SIZE_HALF == dsize_i) ? dbe_half_w : 4'b1111;
wire [7:0] rdata_byte_w =
(2'b00 == daddr_r) ? drdata_r[7:0] :
(2'b01 == daddr_r) ? drdata_r[15:8] :
(2'b10 == daddr_r) ? drdata_r[23:16] : drdata_r[31:24];
wire [15:0] rdata_half_w =
daddr_r[1] ? drdata_r[31:16] : drdata_r[15:0];
assign drdata_o =
(SIZE_BYTE == dsize_r) ? { 24'b0, rdata_byte_w } :
(SIZE_HALF == dsize_r) ? { 16'b0, rdata_half_w } : drdata_r;
reg [1:0] daddr_r;
reg [1:0] dsize_r;
always @(posedge clk_i) begin
if (reset_i) begin
daddr_r <= 2'b00;
dsize_r <= SIZE_BYTE;
end else begin
daddr_r <= daddr_i[1:0];
dsize_r <= dsize_i;
end
end
reg [31:0] mem_r [0:SIZE/4-1];
initial begin
$readmemh(FIRMWARE, mem_r);
end
reg [31:0] irdata_r;
always @(posedge clk_i) begin
if (reset_i)
irdata_r <= 32'h0;
else if (ird_i)
irdata_r <= mem_r[iaddr_i[DEPTH:2]];
end
reg [31:0] drdata_r;
always @(posedge clk_i) begin
if (reset_i)
drdata_r <= 32'h0;
else if (drd_i)
drdata_r <= mem_r[daddr_i[DEPTH:2]];
end
always @(posedge clk_i) begin
if (dbe_w[0] && dwr_i)
mem_r[daddr_i[DEPTH:2]][7:0] <= dwdata_w[7:0];
if (dbe_w[1] && dwr_i)
mem_r[daddr_i[DEPTH:2]][15:8] <= dwdata_w[15:8];
if (dbe_w[2] && dwr_i)
mem_r[daddr_i[DEPTH:2]][23:16] <= dwdata_w[23:16];
if (dbe_w[3] && dwr_i)
mem_r[daddr_i[DEPTH:2]][31:24] <= dwdata_w[31:24];
end
assign irdata_o = irdata_r;
endmodule | module memory #(
parameter SIZE = 8192,
parameter FIRMWARE = ""
)(
input clk_i,
input reset_i,
input [31:0] iaddr_i,
output [31:0] irdata_o,
input ird_i,
input [31:0] daddr_i,
input [31:0] dwdata_i,
output [31:0] drdata_o,
input [1:0] dsize_i,
input drd_i,
input dwr_i
); |
localparam
SIZE_BYTE = 2'd0,
SIZE_HALF = 2'd1,
SIZE_WORD = 2'd2;
localparam
DEPTH = $clog2(SIZE);
wire [31:0] dwdata_w =
(SIZE_BYTE == dsize_i) ? {4{dwdata_i[7:0]}} :
(SIZE_HALF == dsize_i) ? {2{dwdata_i[15:0]}} : dwdata_i;
wire [3:0] dbe_byte_w =
(2'b00 == daddr_i[1:0]) ? 4'b0001 :
(2'b01 == daddr_i[1:0]) ? 4'b0010 :
(2'b10 == daddr_i[1:0]) ? 4'b0100 : 4'b1000;
wire [3:0] dbe_half_w =
daddr_i[1] ? 4'b1100 : 4'b0011;
wire [3:0] dbe_w =
(SIZE_BYTE == dsize_i) ? dbe_byte_w :
(SIZE_HALF == dsize_i) ? dbe_half_w : 4'b1111;
wire [7:0] rdata_byte_w =
(2'b00 == daddr_r) ? drdata_r[7:0] :
(2'b01 == daddr_r) ? drdata_r[15:8] :
(2'b10 == daddr_r) ? drdata_r[23:16] : drdata_r[31:24];
wire [15:0] rdata_half_w =
daddr_r[1] ? drdata_r[31:16] : drdata_r[15:0];
assign drdata_o =
(SIZE_BYTE == dsize_r) ? { 24'b0, rdata_byte_w } :
(SIZE_HALF == dsize_r) ? { 16'b0, rdata_half_w } : drdata_r;
reg [1:0] daddr_r;
reg [1:0] dsize_r;
always @(posedge clk_i) begin
if (reset_i) begin
daddr_r <= 2'b00;
dsize_r <= SIZE_BYTE;
end else begin
daddr_r <= daddr_i[1:0];
dsize_r <= dsize_i;
end
end
reg [31:0] mem_r [0:SIZE/4-1];
initial begin
$readmemh(FIRMWARE, mem_r);
end
reg [31:0] irdata_r;
always @(posedge clk_i) begin
if (reset_i)
irdata_r <= 32'h0;
else if (ird_i)
irdata_r <= mem_r[iaddr_i[DEPTH:2]];
end
reg [31:0] drdata_r;
always @(posedge clk_i) begin
if (reset_i)
drdata_r <= 32'h0;
else if (drd_i)
drdata_r <= mem_r[daddr_i[DEPTH:2]];
end
always @(posedge clk_i) begin
if (dbe_w[0] && dwr_i)
mem_r[daddr_i[DEPTH:2]][7:0] <= dwdata_w[7:0];
if (dbe_w[1] && dwr_i)
mem_r[daddr_i[DEPTH:2]][15:8] <= dwdata_w[15:8];
if (dbe_w[2] && dwr_i)
mem_r[daddr_i[DEPTH:2]][23:16] <= dwdata_w[23:16];
if (dbe_w[3] && dwr_i)
mem_r[daddr_i[DEPTH:2]][31:24] <= dwdata_w[31:24];
end
assign irdata_o = irdata_r;
endmodule | 71 |
6,555 | data/full_repos/permissive/116704972/regs.v | 116,704,972 | regs.v | v | 61 | 76 | [] | [] | [] | [(17, 59)] | null | data/verilator_xmls/7a45ea2f-4883-4a0f-a56f-5c3b902cb4cf.xml | null | 7,482 | module | module registers(
input rst,
input clk,
input write_enable,
input [REG_WIDTH-1 : 0] rs1_offset,
input [REG_WIDTH-1 : 0] rs2_offset,
input [REG_WIDTH-1 : 0] rd_offset,
input [WIDTH-1 : 0] rd_data_in,
output [WIDTH-1 : 0] rs1_data_out,
output [WIDTH-1 : 0] rs2_data_out);
parameter REG_WIDTH = 5;
parameter WIDTH = 32;
parameter STACK_REG = 2;
parameter STACK_START = 1024;
localparam REG_COUNT = 1 << REG_WIDTH;
reg [WIDTH-1 : 0] regs [0 : REG_COUNT-1];
`ifdef IVERILOG
integer i;
initial begin
for (i = 0; i < REG_COUNT; i = i + 1) begin
regs[i] = 0;
end
end
`endif
assign rs1_data_out = regs[rs1_offset];
assign rs2_data_out = regs[rs2_offset];
always @(posedge clk) begin
if (rst) begin
regs[2] <= STACK_START;
end else begin
if (write_enable && (rd_offset != 0)) begin
regs[rd_offset] <= rd_data_in;
end
end
end
endmodule | module registers(
input rst,
input clk,
input write_enable,
input [REG_WIDTH-1 : 0] rs1_offset,
input [REG_WIDTH-1 : 0] rs2_offset,
input [REG_WIDTH-1 : 0] rd_offset,
input [WIDTH-1 : 0] rd_data_in,
output [WIDTH-1 : 0] rs1_data_out,
output [WIDTH-1 : 0] rs2_data_out); |
parameter REG_WIDTH = 5;
parameter WIDTH = 32;
parameter STACK_REG = 2;
parameter STACK_START = 1024;
localparam REG_COUNT = 1 << REG_WIDTH;
reg [WIDTH-1 : 0] regs [0 : REG_COUNT-1];
`ifdef IVERILOG
integer i;
initial begin
for (i = 0; i < REG_COUNT; i = i + 1) begin
regs[i] = 0;
end
end
`endif
assign rs1_data_out = regs[rs1_offset];
assign rs2_data_out = regs[rs2_offset];
always @(posedge clk) begin
if (rst) begin
regs[2] <= STACK_START;
end else begin
if (write_enable && (rd_offset != 0)) begin
regs[rd_offset] <= rd_data_in;
end
end
end
endmodule | 10 |
6,556 | data/full_repos/permissive/116704972/riscv_test.v | 116,704,972 | riscv_test.v | v | 81 | 77 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/116704972/riscv_test.v:18: Cannot find include file: test_defines.v\n`include "test_defines.v" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116704972,data/full_repos/permissive/116704972/test_defines.v\n data/full_repos/permissive/116704972,data/full_repos/permissive/116704972/test_defines.v.v\n data/full_repos/permissive/116704972,data/full_repos/permissive/116704972/test_defines.v.sv\n test_defines.v\n test_defines.v.v\n test_defines.v.sv\n obj_dir/test_defines.v\n obj_dir/test_defines.v.v\n obj_dir/test_defines.v.sv\n%Error: data/full_repos/permissive/116704972/riscv_test.v:19: Cannot find include file: top.v\n`include "top.v" \n ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/116704972/riscv_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n always #2 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116704972/riscv_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n always #8 uart_clk = !uart_clk; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/116704972/riscv_test.v:44: Unsupported: Ignoring delay on this delayed statement.\n #9999 $display("Test timeout!\\n");\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116704972/riscv_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n #10000 $finish;\n ^\n%Error: data/full_repos/permissive/116704972/riscv_test.v:62: Define or directive not defined: \'`TEST_NAME\'\n $display("%s\\ttest pass\\n", `TEST_NAME);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/116704972/riscv_test.v:62: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n $display("%s\\ttest pass\\n", `TEST_NAME);\n ^\n%Error: data/full_repos/permissive/116704972/riscv_test.v:65: Define or directive not defined: \'`TEST_NAME\'\n $display("%s\\ttest failed!\\n", `TEST_NAME);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/116704972/riscv_test.v:65: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n $display("%s\\ttest failed!\\n", `TEST_NAME);\n ^\n%Error: Exiting due to 6 error(s), 4 warning(s)\n' | 7,483 | module | module top_test;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 12;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
reg [WIDTH-1 : 0] expected_output = 80;
wire uart_tx;
always #2 clk = !clk;
always #8 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
initial begin
#9999 $display("Test timeout!\n");
#10000 $finish;
end
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1 ) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (serial_data == expected_output) begin
$display("%s\ttest pass\n", `TEST_NAME);
$finish;
end else begin
$display("%s\ttest failed!\n", `TEST_NAME);
$finish;
end
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule | module top_test; |
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 12;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
reg [WIDTH-1 : 0] expected_output = 80;
wire uart_tx;
always #2 clk = !clk;
always #8 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
initial begin
#9999 $display("Test timeout!\n");
#10000 $finish;
end
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1 ) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (serial_data == expected_output) begin
$display("%s\ttest pass\n", `TEST_NAME);
$finish;
end else begin
$display("%s\ttest failed!\n", `TEST_NAME);
$finish;
end
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule | 10 |
6,557 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/c5soc/system/system_bb.v | 116,866,011 | system_bb.v | v | 137 | 46 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/fc5e8c56-5251-4a33-a6b2-3f86a6b22fcb.xml | null | 7,488 | module | module system (
clk_50_clk,
reset_50_reset_n,
kernel_clk_clk,
fpga_memory_mem_a,
fpga_memory_mem_ba,
fpga_memory_mem_ck,
fpga_memory_mem_ck_n,
fpga_memory_mem_cke,
fpga_memory_mem_cs_n,
fpga_memory_mem_dm,
fpga_memory_mem_ras_n,
fpga_memory_mem_cas_n,
fpga_memory_mem_we_n,
fpga_memory_mem_reset_n,
fpga_memory_mem_dq,
fpga_memory_mem_dqs,
fpga_memory_mem_dqs_n,
fpga_memory_mem_odt,
fpga_memory_oct_rzqin,
fpga_sdram_status_local_init_done,
fpga_sdram_status_local_cal_success,
fpga_sdram_status_local_cal_fail,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
peripheral_hps_io_emac0_inst_TX_CLK,
peripheral_hps_io_emac0_inst_TXD0,
peripheral_hps_io_emac0_inst_TXD1,
peripheral_hps_io_emac0_inst_TXD2,
peripheral_hps_io_emac0_inst_TXD3,
peripheral_hps_io_emac0_inst_RXD0,
peripheral_hps_io_emac0_inst_MDIO,
peripheral_hps_io_emac0_inst_MDC,
peripheral_hps_io_emac0_inst_RX_CTL,
peripheral_hps_io_emac0_inst_TX_CTL,
peripheral_hps_io_emac0_inst_RX_CLK,
peripheral_hps_io_emac0_inst_RXD1,
peripheral_hps_io_emac0_inst_RXD2,
peripheral_hps_io_emac0_inst_RXD3,
peripheral_hps_io_sdio_inst_CMD,
peripheral_hps_io_sdio_inst_D0,
peripheral_hps_io_sdio_inst_D1,
peripheral_hps_io_sdio_inst_CLK,
peripheral_hps_io_sdio_inst_D2,
peripheral_hps_io_sdio_inst_D3,
peripheral_hps_io_uart0_inst_RX,
peripheral_hps_io_uart0_inst_TX,
peripheral_hps_io_i2c0_inst_SDA,
peripheral_hps_io_i2c0_inst_SCL,
peripheral_hps_io_gpio_inst_GPIO41,
peripheral_hps_io_gpio_inst_GPIO42,
peripheral_hps_io_gpio_inst_GPIO43,
peripheral_hps_io_gpio_inst_GPIO44);
input clk_50_clk;
input reset_50_reset_n;
output kernel_clk_clk;
output [14:0] fpga_memory_mem_a;
output [2:0] fpga_memory_mem_ba;
output [0:0] fpga_memory_mem_ck;
output [0:0] fpga_memory_mem_ck_n;
output [0:0] fpga_memory_mem_cke;
output [0:0] fpga_memory_mem_cs_n;
output [3:0] fpga_memory_mem_dm;
output [0:0] fpga_memory_mem_ras_n;
output [0:0] fpga_memory_mem_cas_n;
output [0:0] fpga_memory_mem_we_n;
output fpga_memory_mem_reset_n;
inout [31:0] fpga_memory_mem_dq;
inout [3:0] fpga_memory_mem_dqs;
inout [3:0] fpga_memory_mem_dqs_n;
output [0:0] fpga_memory_mem_odt;
input fpga_memory_oct_rzqin;
output fpga_sdram_status_local_init_done;
output fpga_sdram_status_local_cal_success;
output fpga_sdram_status_local_cal_fail;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [39:0] memory_mem_dq;
inout [4:0] memory_mem_dqs;
inout [4:0] memory_mem_dqs_n;
output memory_mem_odt;
output [4:0] memory_mem_dm;
input memory_oct_rzqin;
output peripheral_hps_io_emac0_inst_TX_CLK;
output peripheral_hps_io_emac0_inst_TXD0;
output peripheral_hps_io_emac0_inst_TXD1;
output peripheral_hps_io_emac0_inst_TXD2;
output peripheral_hps_io_emac0_inst_TXD3;
input peripheral_hps_io_emac0_inst_RXD0;
inout peripheral_hps_io_emac0_inst_MDIO;
output peripheral_hps_io_emac0_inst_MDC;
input peripheral_hps_io_emac0_inst_RX_CTL;
output peripheral_hps_io_emac0_inst_TX_CTL;
input peripheral_hps_io_emac0_inst_RX_CLK;
input peripheral_hps_io_emac0_inst_RXD1;
input peripheral_hps_io_emac0_inst_RXD2;
input peripheral_hps_io_emac0_inst_RXD3;
inout peripheral_hps_io_sdio_inst_CMD;
inout peripheral_hps_io_sdio_inst_D0;
inout peripheral_hps_io_sdio_inst_D1;
output peripheral_hps_io_sdio_inst_CLK;
inout peripheral_hps_io_sdio_inst_D2;
inout peripheral_hps_io_sdio_inst_D3;
input peripheral_hps_io_uart0_inst_RX;
output peripheral_hps_io_uart0_inst_TX;
inout peripheral_hps_io_i2c0_inst_SDA;
inout peripheral_hps_io_i2c0_inst_SCL;
inout peripheral_hps_io_gpio_inst_GPIO41;
inout peripheral_hps_io_gpio_inst_GPIO42;
inout peripheral_hps_io_gpio_inst_GPIO43;
inout peripheral_hps_io_gpio_inst_GPIO44;
endmodule | module system (
clk_50_clk,
reset_50_reset_n,
kernel_clk_clk,
fpga_memory_mem_a,
fpga_memory_mem_ba,
fpga_memory_mem_ck,
fpga_memory_mem_ck_n,
fpga_memory_mem_cke,
fpga_memory_mem_cs_n,
fpga_memory_mem_dm,
fpga_memory_mem_ras_n,
fpga_memory_mem_cas_n,
fpga_memory_mem_we_n,
fpga_memory_mem_reset_n,
fpga_memory_mem_dq,
fpga_memory_mem_dqs,
fpga_memory_mem_dqs_n,
fpga_memory_mem_odt,
fpga_memory_oct_rzqin,
fpga_sdram_status_local_init_done,
fpga_sdram_status_local_cal_success,
fpga_sdram_status_local_cal_fail,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
peripheral_hps_io_emac0_inst_TX_CLK,
peripheral_hps_io_emac0_inst_TXD0,
peripheral_hps_io_emac0_inst_TXD1,
peripheral_hps_io_emac0_inst_TXD2,
peripheral_hps_io_emac0_inst_TXD3,
peripheral_hps_io_emac0_inst_RXD0,
peripheral_hps_io_emac0_inst_MDIO,
peripheral_hps_io_emac0_inst_MDC,
peripheral_hps_io_emac0_inst_RX_CTL,
peripheral_hps_io_emac0_inst_TX_CTL,
peripheral_hps_io_emac0_inst_RX_CLK,
peripheral_hps_io_emac0_inst_RXD1,
peripheral_hps_io_emac0_inst_RXD2,
peripheral_hps_io_emac0_inst_RXD3,
peripheral_hps_io_sdio_inst_CMD,
peripheral_hps_io_sdio_inst_D0,
peripheral_hps_io_sdio_inst_D1,
peripheral_hps_io_sdio_inst_CLK,
peripheral_hps_io_sdio_inst_D2,
peripheral_hps_io_sdio_inst_D3,
peripheral_hps_io_uart0_inst_RX,
peripheral_hps_io_uart0_inst_TX,
peripheral_hps_io_i2c0_inst_SDA,
peripheral_hps_io_i2c0_inst_SCL,
peripheral_hps_io_gpio_inst_GPIO41,
peripheral_hps_io_gpio_inst_GPIO42,
peripheral_hps_io_gpio_inst_GPIO43,
peripheral_hps_io_gpio_inst_GPIO44); |
input clk_50_clk;
input reset_50_reset_n;
output kernel_clk_clk;
output [14:0] fpga_memory_mem_a;
output [2:0] fpga_memory_mem_ba;
output [0:0] fpga_memory_mem_ck;
output [0:0] fpga_memory_mem_ck_n;
output [0:0] fpga_memory_mem_cke;
output [0:0] fpga_memory_mem_cs_n;
output [3:0] fpga_memory_mem_dm;
output [0:0] fpga_memory_mem_ras_n;
output [0:0] fpga_memory_mem_cas_n;
output [0:0] fpga_memory_mem_we_n;
output fpga_memory_mem_reset_n;
inout [31:0] fpga_memory_mem_dq;
inout [3:0] fpga_memory_mem_dqs;
inout [3:0] fpga_memory_mem_dqs_n;
output [0:0] fpga_memory_mem_odt;
input fpga_memory_oct_rzqin;
output fpga_sdram_status_local_init_done;
output fpga_sdram_status_local_cal_success;
output fpga_sdram_status_local_cal_fail;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [39:0] memory_mem_dq;
inout [4:0] memory_mem_dqs;
inout [4:0] memory_mem_dqs_n;
output memory_mem_odt;
output [4:0] memory_mem_dm;
input memory_oct_rzqin;
output peripheral_hps_io_emac0_inst_TX_CLK;
output peripheral_hps_io_emac0_inst_TXD0;
output peripheral_hps_io_emac0_inst_TXD1;
output peripheral_hps_io_emac0_inst_TXD2;
output peripheral_hps_io_emac0_inst_TXD3;
input peripheral_hps_io_emac0_inst_RXD0;
inout peripheral_hps_io_emac0_inst_MDIO;
output peripheral_hps_io_emac0_inst_MDC;
input peripheral_hps_io_emac0_inst_RX_CTL;
output peripheral_hps_io_emac0_inst_TX_CTL;
input peripheral_hps_io_emac0_inst_RX_CLK;
input peripheral_hps_io_emac0_inst_RXD1;
input peripheral_hps_io_emac0_inst_RXD2;
input peripheral_hps_io_emac0_inst_RXD3;
inout peripheral_hps_io_sdio_inst_CMD;
inout peripheral_hps_io_sdio_inst_D0;
inout peripheral_hps_io_sdio_inst_D1;
output peripheral_hps_io_sdio_inst_CLK;
inout peripheral_hps_io_sdio_inst_D2;
inout peripheral_hps_io_sdio_inst_D3;
input peripheral_hps_io_uart0_inst_RX;
output peripheral_hps_io_uart0_inst_TX;
inout peripheral_hps_io_i2c0_inst_SDA;
inout peripheral_hps_io_i2c0_inst_SCL;
inout peripheral_hps_io_gpio_inst_GPIO41;
inout peripheral_hps_io_gpio_inst_GPIO42;
inout peripheral_hps_io_gpio_inst_GPIO43;
inout peripheral_hps_io_gpio_inst_GPIO44;
endmodule | 5 |
6,559 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/c5soc/system/synthesis/submodules/pll_lock_avs.v | 116,866,011 | pll_lock_avs.v | v | 26 | 32 | [] | [] | [] | null | line:26: before: "v" | data/verilator_xmls/c81a7a24-ceb8-498e-be2d-585a1e7f8230.xml | null | 7,501 | module | module pll_lock_avs
#(
parameter WIDTH=32
)
(
input clk,
input resetn,
input slave_read,
output slave_readdata,
input lock,
output lock_export
);
reg locked;
always@(posedge clk)
locked <= lock;
assign slave_readdata = locked;
assign lock_export = lock;
endmodule | module pll_lock_avs
#(
parameter WIDTH=32
)
(
input clk,
input resetn,
input slave_read,
output slave_readdata,
input lock,
output lock_export
); |
reg locked;
always@(posedge clk)
locked <= lock;
assign slave_readdata = locked;
assign lock_export = lock;
endmodule | 5 |
6,560 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/c5soc/system/synthesis/submodules/snoop_adapter.v | 116,866,011 | snoop_adapter.v | v | 145 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/c5soc/system/synthesis/submodules/snoop_adapter.v:95: Cannot find file containing module: \'dcfifo\'\n dcfifo dcfifo_component (\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/c5soc/system/synthesis/submodules,data/full_repos/permissive/116866011/dcfifo\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/c5soc/system/synthesis/submodules,data/full_repos/permissive/116866011/dcfifo.v\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/c5soc/system/synthesis/submodules,data/full_repos/permissive/116866011/dcfifo.sv\n dcfifo\n dcfifo.v\n dcfifo.sv\n obj_dir/dcfifo\n obj_dir/dcfifo.v\n obj_dir/dcfifo.sv\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/c5soc/system/synthesis/submodules/snoop_adapter.v:125: Operator GTE expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'rdusedw\' generates 8 bits.\n : ... In instance snoop_adapter\n snoop_overflow = ( rdusedw >= ( FIFO_SIZE - 12 ) );\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 7,502 | module | module snoop_adapter (
clk,
reset,
kernel_clk,
kernel_reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
snoop_data,
snoop_valid,
snoop_ready,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
localparam DEVICE_BLOCKRAM_MIN_DEPTH = 256;
localparam FIFO_SIZE = DEVICE_BLOCKRAM_MIN_DEPTH;
localparam LOG2_FIFO_SIZE =$clog2(FIFO_SIZE);
input clk;
input reset;
input kernel_clk;
input kernel_reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output [1+WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data;
output snoop_valid;
input snoop_ready;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
reg snoop_overflow;
reg [WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data_r;
reg snoop_valid_r;
wire snoop_fifo_empty;
wire overflow;
wire [ LOG2_FIFO_SIZE-1 : 0 ] rdusedw;
always@(posedge clk)
begin
snoop_data_r<={address,export_burstcount};
snoop_valid_r<=export_write && !export_waitrequest;
end
dcfifo dcfifo_component (
.wrclk (clk),
.data (snoop_data_r),
.wrreq (snoop_valid_r),
.rdclk (kernel_clk),
.rdreq (snoop_valid & snoop_ready),
.q (snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0]),
.rdempty (snoop_fifo_empty),
.rdfull (overflow),
.aclr (1'b0),
.rdusedw (rdusedw),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Stratix IV",
dcfifo_component.lpm_numwords = FIFO_SIZE,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH,
dcfifo_component.lpm_widthu = LOG2_FIFO_SIZE,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
assign snoop_valid=~snoop_fifo_empty;
always@(posedge kernel_clk)
snoop_overflow = ( rdusedw >= ( FIFO_SIZE - 12 ) );
assign snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH] = snoop_overflow;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign waitrequest = export_waitrequest;
endmodule | module snoop_adapter (
clk,
reset,
kernel_clk,
kernel_reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
snoop_data,
snoop_valid,
snoop_ready,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest
); |
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
localparam DEVICE_BLOCKRAM_MIN_DEPTH = 256;
localparam FIFO_SIZE = DEVICE_BLOCKRAM_MIN_DEPTH;
localparam LOG2_FIFO_SIZE =$clog2(FIFO_SIZE);
input clk;
input reset;
input kernel_clk;
input kernel_reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output [1+WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data;
output snoop_valid;
input snoop_ready;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
reg snoop_overflow;
reg [WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data_r;
reg snoop_valid_r;
wire snoop_fifo_empty;
wire overflow;
wire [ LOG2_FIFO_SIZE-1 : 0 ] rdusedw;
always@(posedge clk)
begin
snoop_data_r<={address,export_burstcount};
snoop_valid_r<=export_write && !export_waitrequest;
end
dcfifo dcfifo_component (
.wrclk (clk),
.data (snoop_data_r),
.wrreq (snoop_valid_r),
.rdclk (kernel_clk),
.rdreq (snoop_valid & snoop_ready),
.q (snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0]),
.rdempty (snoop_fifo_empty),
.rdfull (overflow),
.aclr (1'b0),
.rdusedw (rdusedw),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Stratix IV",
dcfifo_component.lpm_numwords = FIFO_SIZE,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH,
dcfifo_component.lpm_widthu = LOG2_FIFO_SIZE,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
assign snoop_valid=~snoop_fifo_empty;
always@(posedge kernel_clk)
snoop_overflow = ( rdusedw >= ( FIFO_SIZE - 12 ) );
assign snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH] = snoop_overflow;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign waitrequest = export_waitrequest;
endmodule | 5 |
6,562 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/c5soc/system/synthesis/submodules/version_id.v | 116,866,011 | version_id.v | v | 19 | 37 | [] | [] | [] | [(1, 17)] | null | data/verilator_xmls/415ba90b-d42a-4fe6-b53e-fa69a79c57a1.xml | null | 7,539 | module | module version_id
#(
parameter WIDTH=32,
parameter VERSION_ID=0
)
(
input clk,
input resetn,
input slave_read,
output [WIDTH-1:0] slave_readdata
);
assign slave_readdata = VERSION_ID;
endmodule | module version_id
#(
parameter WIDTH=32,
parameter VERSION_ID=0
)
(
input clk,
input resetn,
input slave_read,
output [WIDTH-1:0] slave_readdata
); |
assign slave_readdata = VERSION_ID;
endmodule | 5 |
6,569 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/ip/i2c/I2C_WRITE_WDATA.v | 116,866,011 | I2C_WRITE_WDATA.v | v | 107 | 90 | [] | [] | [] | [(1, 106)] | null | data/verilator_xmls/38500eef-9560-45ba-9f36-9bd3dd035ce7.xml | null | 7,548 | module | module I2C_WRITE_WDATA (
input RESET_N ,
input PT_CK,
input GO,
input [15:0] REG_DATA,
input [7:0] SLAVE_ADDRESS,
input SDAI,
output reg SDAO,
output reg SCLO,
output reg END_OK,
output reg [7:0] ST ,
output reg [7:0] CNT,
output reg [7:0] BYTE,
output reg ACK_OK,
input [7:0] BYTE_NUM
);
reg [8:0]A ;
reg [7:0]DELY ;
always @( negedge RESET_N or posedge PT_CK )begin
if (!RESET_N ) ST <=0;
else
case (ST)
0: begin
SDAO <=1;
SCLO <=1;
ACK_OK <=0;
CNT <=0;
END_OK <=1;
BYTE <=0;
if (GO) ST <=30 ;
end
1: begin
ST <=2 ;
{ SDAO, SCLO } <= 2'b01;
A <= {SLAVE_ADDRESS ,1'b1 };
end
2: begin
ST <=3 ;
{ SDAO, SCLO } <= 2'b00;
end
3: begin
ST <=4 ;
{ SDAO, A } <= { A ,1'b0 };
end
4: begin
ST <=5 ;
SCLO <= 1'b1 ;
CNT <= CNT +1 ;
end
5: begin
SCLO <= 1'b0 ;
if (CNT==9) begin
if ( BYTE == BYTE_NUM ) ST <= 6 ;
else begin
CNT <=0 ;
ST <= 2 ;
if ( BYTE ==0 ) begin BYTE <=1 ; A <= {REG_DATA[15:8] ,1'b1 }; end
else if ( BYTE ==1 ) begin BYTE <=2 ; A <= {REG_DATA[7:0] ,1'b1 }; end
end
if (SDAI ) ACK_OK <=1 ;
end
else ST <= 2;
end
6: begin
ST <=7 ;
{ SDAO, SCLO } <= 2'b00;
end
7: begin
ST <=8 ;
{ SDAO, SCLO } <= 2'b01;
end
8: begin
ST <=9 ;
{ SDAO, SCLO } <= 2'b11;
end
9: begin
ST <= 30;
SDAO <=1;
SCLO <=1;
CNT <=0;
END_OK <=1;
BYTE <=0;
end
30: begin
if (!GO) ST <=31;
end
31: begin
END_OK<=0;
ACK_OK<=0;
ST <=1;
end
endcase
end
endmodule | module I2C_WRITE_WDATA (
input RESET_N ,
input PT_CK,
input GO,
input [15:0] REG_DATA,
input [7:0] SLAVE_ADDRESS,
input SDAI,
output reg SDAO,
output reg SCLO,
output reg END_OK,
output reg [7:0] ST ,
output reg [7:0] CNT,
output reg [7:0] BYTE,
output reg ACK_OK,
input [7:0] BYTE_NUM
); |
reg [8:0]A ;
reg [7:0]DELY ;
always @( negedge RESET_N or posedge PT_CK )begin
if (!RESET_N ) ST <=0;
else
case (ST)
0: begin
SDAO <=1;
SCLO <=1;
ACK_OK <=0;
CNT <=0;
END_OK <=1;
BYTE <=0;
if (GO) ST <=30 ;
end
1: begin
ST <=2 ;
{ SDAO, SCLO } <= 2'b01;
A <= {SLAVE_ADDRESS ,1'b1 };
end
2: begin
ST <=3 ;
{ SDAO, SCLO } <= 2'b00;
end
3: begin
ST <=4 ;
{ SDAO, A } <= { A ,1'b0 };
end
4: begin
ST <=5 ;
SCLO <= 1'b1 ;
CNT <= CNT +1 ;
end
5: begin
SCLO <= 1'b0 ;
if (CNT==9) begin
if ( BYTE == BYTE_NUM ) ST <= 6 ;
else begin
CNT <=0 ;
ST <= 2 ;
if ( BYTE ==0 ) begin BYTE <=1 ; A <= {REG_DATA[15:8] ,1'b1 }; end
else if ( BYTE ==1 ) begin BYTE <=2 ; A <= {REG_DATA[7:0] ,1'b1 }; end
end
if (SDAI ) ACK_OK <=1 ;
end
else ST <= 2;
end
6: begin
ST <=7 ;
{ SDAO, SCLO } <= 2'b00;
end
7: begin
ST <=8 ;
{ SDAO, SCLO } <= 2'b01;
end
8: begin
ST <=9 ;
{ SDAO, SCLO } <= 2'b11;
end
9: begin
ST <= 30;
SDAO <=1;
SCLO <=1;
CNT <=0;
END_OK <=1;
BYTE <=0;
end
30: begin
if (!GO) ST <=31;
end
31: begin
END_OK<=0;
ACK_OK<=0;
ST <=1;
end
endcase
end
endmodule | 5 |
6,573 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_common_frame_counter.v | 116,866,011 | alt_vipitc131_common_frame_counter.v | v | 85 | 87 | [] | [] | [] | null | line:44: before: "." | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_common_frame_counter.v:28: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_common_frame_counter.v:34: Cannot find file containing module: \'alt_vipitc131_common_sample_counter\'\nalt_vipitc131_common_sample_counter sample_counter(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_sample_counter\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_sample_counter.v\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_sample_counter.sv\n alt_vipitc131_common_sample_counter\n alt_vipitc131_common_sample_counter.v\n alt_vipitc131_common_sample_counter.sv\n obj_dir/alt_vipitc131_common_sample_counter\n obj_dir/alt_vipitc131_common_sample_counter.v\n obj_dir/alt_vipitc131_common_sample_counter.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 7,594 | module | module alt_vipitc131_common_frame_counter
#(parameter
NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0,
CONVERT_SEQ_TO_PAR = 0,
TOTALS_MINUS_ONE = 0)
(
input wire rst,
input wire clk,
input wire sclr,
input wire enable,
input wire hd_sdn,
input wire [13:0] h_total,
input wire [12:0] v_total,
input wire [13:0] h_reset,
input wire [12:0] v_reset,
output wire new_line,
output wire start_of_sample,
output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks,
output reg [13:0] h_count,
output reg [12:0] v_count);
wire count_sample;
alt_vipitc131_common_sample_counter sample_counter(
.rst(rst),
.clk(clk),
.sclr(sclr),
.hd_sdn(hd_sdn),
.count_cycle(enable),
.count_sample(count_sample),
.start_of_sample(start_of_sample),
.sample_ticks(sample_ticks));
defparam sample_counter.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
sample_counter.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
sample_counter.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_NUMBER_OF_COLOUR_PLANES;
wire [13:0] h_total_int;
wire [12:0] v_total_int;
generate
if(TOTALS_MINUS_ONE) begin : totals_minus_one_generate
assign h_total_int = h_total;
assign v_total_int = v_total;
end else begin
assign h_total_int = h_total - 14'd1;
assign v_total_int = v_total - 13'd1;
end
endgenerate
always @ (posedge rst or posedge clk) begin
if(rst) begin
h_count <= 14'd0;
v_count <= 13'd0;
end else begin
if(sclr) begin
h_count <= h_reset + {{13{1'b0}}, count_sample & hd_sdn};
v_count <= v_reset;
end else if(enable) begin
if(new_line) begin
h_count <= 14'd0;
if(v_count >= v_total_int)
v_count <= 13'd0;
else
v_count <= v_count + 13'd1;
end else if(count_sample)
h_count <= h_count + 14'd1;
end
end
end
assign new_line = (h_count >= h_total_int) && count_sample;
endmodule | module alt_vipitc131_common_frame_counter
#(parameter
NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0,
CONVERT_SEQ_TO_PAR = 0,
TOTALS_MINUS_ONE = 0)
(
input wire rst,
input wire clk,
input wire sclr,
input wire enable,
input wire hd_sdn,
input wire [13:0] h_total,
input wire [12:0] v_total,
input wire [13:0] h_reset,
input wire [12:0] v_reset,
output wire new_line,
output wire start_of_sample,
output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks,
output reg [13:0] h_count,
output reg [12:0] v_count); |
wire count_sample;
alt_vipitc131_common_sample_counter sample_counter(
.rst(rst),
.clk(clk),
.sclr(sclr),
.hd_sdn(hd_sdn),
.count_cycle(enable),
.count_sample(count_sample),
.start_of_sample(start_of_sample),
.sample_ticks(sample_ticks));
defparam sample_counter.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
sample_counter.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
sample_counter.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_NUMBER_OF_COLOUR_PLANES;
wire [13:0] h_total_int;
wire [12:0] v_total_int;
generate
if(TOTALS_MINUS_ONE) begin : totals_minus_one_generate
assign h_total_int = h_total;
assign v_total_int = v_total;
end else begin
assign h_total_int = h_total - 14'd1;
assign v_total_int = v_total - 13'd1;
end
endgenerate
always @ (posedge rst or posedge clk) begin
if(rst) begin
h_count <= 14'd0;
v_count <= 13'd0;
end else begin
if(sclr) begin
h_count <= h_reset + {{13{1'b0}}, count_sample & hd_sdn};
v_count <= v_reset;
end else if(enable) begin
if(new_line) begin
h_count <= 14'd0;
if(v_count >= v_total_int)
v_count <= 13'd0;
else
v_count <= v_count + 13'd1;
end else if(count_sample)
h_count <= h_count + 14'd1;
end
end
end
assign new_line = (h_count >= h_total_int) && count_sample;
endmodule | 5 |
6,574 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_common_generic_count.v | 116,866,011 | alt_vipitc131_common_generic_count.v | v | 53 | 123 | [] | [] | [] | [(1, 52)] | null | data/verilator_xmls/ccc2d818-0e74-4946-bfec-8f47980579c9.xml | null | 7,595 | module | module alt_vipitc131_common_generic_count
#( parameter WORD_LENGTH = 12,
parameter MAX_COUNT = 1280,
parameter RESET_VALUE = 0,
parameter TICKS_WORD_LENGTH = 1,
parameter TICKS_PER_COUNT = 1
)
(
input wire clk,
input wire reset_n,
input wire enable,
input wire enable_ticks,
input wire [WORD_LENGTH-1:0] max_count,
output reg [WORD_LENGTH-1:0] count,
input wire restart_count,
input wire [WORD_LENGTH-1:0] reset_value,
output wire enable_count,
output wire start_count,
output wire [TICKS_WORD_LENGTH-1:0] cp_ticks
);
generate
if(TICKS_PER_COUNT == 1) begin
assign start_count = 1'b1;
assign enable_count = enable;
assign cp_ticks = 1'b0;
end else begin
reg [TICKS_WORD_LENGTH-1:0] ticks;
always @(posedge clk or negedge reset_n)
if (!reset_n)
ticks <= {TICKS_WORD_LENGTH{1'b0}};
else
ticks <= (restart_count) ? {TICKS_WORD_LENGTH{1'b0}} :
(enable) ? (ticks >= TICKS_PER_COUNT - 1) ? {TICKS_WORD_LENGTH{1'b0}} : ticks + 1'b1 : ticks;
assign start_count = ticks == {TICKS_WORD_LENGTH{1'b0}} || !enable_ticks;
assign enable_count = enable && ((ticks >= TICKS_PER_COUNT - 1) || !enable_ticks);
assign cp_ticks = ticks & {TICKS_WORD_LENGTH{enable_ticks}};
end
endgenerate
always @(posedge clk or negedge reset_n)
if (!reset_n)
count <= RESET_VALUE[WORD_LENGTH-1:0];
else
count <= (restart_count) ? reset_value :
(enable_count) ? (count < max_count) ? count + 1'b1 : {(WORD_LENGTH){1'b0}} : count;
endmodule | module alt_vipitc131_common_generic_count
#( parameter WORD_LENGTH = 12,
parameter MAX_COUNT = 1280,
parameter RESET_VALUE = 0,
parameter TICKS_WORD_LENGTH = 1,
parameter TICKS_PER_COUNT = 1
)
(
input wire clk,
input wire reset_n,
input wire enable,
input wire enable_ticks,
input wire [WORD_LENGTH-1:0] max_count,
output reg [WORD_LENGTH-1:0] count,
input wire restart_count,
input wire [WORD_LENGTH-1:0] reset_value,
output wire enable_count,
output wire start_count,
output wire [TICKS_WORD_LENGTH-1:0] cp_ticks
); |
generate
if(TICKS_PER_COUNT == 1) begin
assign start_count = 1'b1;
assign enable_count = enable;
assign cp_ticks = 1'b0;
end else begin
reg [TICKS_WORD_LENGTH-1:0] ticks;
always @(posedge clk or negedge reset_n)
if (!reset_n)
ticks <= {TICKS_WORD_LENGTH{1'b0}};
else
ticks <= (restart_count) ? {TICKS_WORD_LENGTH{1'b0}} :
(enable) ? (ticks >= TICKS_PER_COUNT - 1) ? {TICKS_WORD_LENGTH{1'b0}} : ticks + 1'b1 : ticks;
assign start_count = ticks == {TICKS_WORD_LENGTH{1'b0}} || !enable_ticks;
assign enable_count = enable && ((ticks >= TICKS_PER_COUNT - 1) || !enable_ticks);
assign cp_ticks = ticks & {TICKS_WORD_LENGTH{enable_ticks}};
end
endgenerate
always @(posedge clk or negedge reset_n)
if (!reset_n)
count <= RESET_VALUE[WORD_LENGTH-1:0];
else
count <= (restart_count) ? reset_value :
(enable_count) ? (count < max_count) ? count + 1'b1 : {(WORD_LENGTH){1'b0}} : count;
endmodule | 5 |
6,575 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_common_sync.v | 116,866,011 | alt_vipitc131_common_sync.v | v | 35 | 191 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/24dc8cf1-93ac-41ed-8468-1af6e73353ef.xml | null | 7,597 | module | module alt_vipitc131_common_sync
#(parameter
CLOCKS_ARE_SAME = 0,
WIDTH = 1)
(
input wire rst,
input wire sync_clock,
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out);
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name SDC_STATEMENT \"set_false_path -to [get_keepers *data_out_sync0*]\"" *) reg [WIDTH-1:0] data_out_sync0;
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS" *) reg [WIDTH-1:0] data_out_sync1;
generate
if(CLOCKS_ARE_SAME)
assign data_out = data_in;
else begin
always @ (posedge rst or posedge sync_clock) begin
if(rst) begin
data_out_sync0 <= {WIDTH{1'b0}};
data_out_sync1 <= {WIDTH{1'b0}};
end else begin
data_out_sync0 <= data_in;
data_out_sync1 <= data_out_sync0;
end
end
assign data_out = data_out_sync1;
end
endgenerate
endmodule | module alt_vipitc131_common_sync
#(parameter
CLOCKS_ARE_SAME = 0,
WIDTH = 1)
(
input wire rst,
input wire sync_clock,
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out); |
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name SDC_STATEMENT \"set_false_path -to [get_keepers *data_out_sync0*]\"" *) reg [WIDTH-1:0] data_out_sync0;
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS" *) reg [WIDTH-1:0] data_out_sync1;
generate
if(CLOCKS_ARE_SAME)
assign data_out = data_in;
else begin
always @ (posedge rst or posedge sync_clock) begin
if(rst) begin
data_out_sync0 <= {WIDTH{1'b0}};
data_out_sync1 <= {WIDTH{1'b0}};
end else begin
data_out_sync0 <= data_in;
data_out_sync1 <= data_out_sync0;
end
end
assign data_out = data_out_sync1;
end
endgenerate
endmodule | 5 |
6,576 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv | 116,866,011 | alt_vipitc131_IS2Vid.sv | sv | 1,203 | 182 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:388: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) enable_resync_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_sync\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_sync.v\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_sync.sv\n alt_vipitc131_common_sync\n alt_vipitc131_common_sync.v\n alt_vipitc131_common_sync.sv\n obj_dir/alt_vipitc131_common_sync\n obj_dir/alt_vipitc131_common_sync.v\n obj_dir/alt_vipitc131_common_sync.sv\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:394: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) underflow_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:400: Cannot find file containing module: \'alt_vipitc131_common_trigger_sync\'\nalt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) mode_change_trigger_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:410: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) genlocked_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:416: Cannot find file containing module: \'alt_vipitc131_IS2Vid_control\'\nalt_vipitc131_IS2Vid_control control(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:452: Cannot find file containing module: \'alt_vipitc131_common_trigger_sync\'\nalt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) av_write_trigger_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:462: Cannot find file containing module: \'alt_vipitc131_IS2Vid_mode_banks\'\nalt_vipitc131_IS2Vid_mode_banks mode_banks(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:545: Cannot find file containing module: \'alt_vipitc131_common_trigger_sync\'\nalt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) av_waitrequest_trigger_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:573: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign repeat_reset_point = !remove_repeatn && h_count == sync_compare_h_reset && v_count == sync_compare_v_reset;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:573: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign repeat_reset_point = !remove_repeatn && h_count == sync_compare_h_reset && v_count == sync_compare_v_reset;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:574: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign remove_reset_point = remove_repeatn && h_count == 16\'d0 && v_count == 16\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:574: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign remove_reset_point = remove_repeatn && h_count == 16\'d0 && v_count == 16\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:581: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'cp_ticks\' generates 1 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign lines_reset = (repeat_lines_reset || remove_lines_reset) && ((cp_ticks == NUMBER_OF_COLOUR_PLANES - 1) || ~serial_output);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:582: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'cp_ticks\' generates 1 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign samples_reset = (repeat_samples_reset || remove_samples_reset) && ((cp_ticks == NUMBER_OF_COLOUR_PLANES - 1) || ~serial_output);\n ^~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:591: Cannot find file containing module: \'alt_vipitc131_common_generic_count\'\nalt_vipitc131_common_generic_count\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:609: Cannot find file containing module: \'alt_vipitc131_common_generic_count\'\nalt_vipitc131_common_generic_count\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:621: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign start_of_frame = (start_of_cp && h_count == H_OFFSET) && ((interlaced && v_count == f1_v_end) || v_count == V_OFFSET);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:623: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign v_enable = enable_synced_nxt && enable_vcount && h_count == h_total_minus_one;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:624: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign ap = h_count >= h_blank && ~vid_v_nxt;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:627: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_h_nxt = enable_synced_nxt && h_count < h_blank;\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:628: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_h_sync_nxt = enable_synced_nxt && (h_count >= h_sync_start && h_count < h_sync_end);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:628: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_h_sync_nxt = enable_synced_nxt && (h_count >= h_sync_start && h_count < h_sync_end);\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:629: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_v_nxt = enable_synced_nxt && (v_count >= f2_v_start ||\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:630: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && (v_count >= f1_v_start && v_count < f1_v_end)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:630: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && (v_count >= f1_v_start && v_count < f1_v_end)));\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:631: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_v_sync_nxt = enable_synced_nxt && ((v_count >= f2_v_sync_start && v_count < f2_v_sync_end) ||\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:631: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_v_sync_nxt = enable_synced_nxt && ((v_count >= f2_v_sync_start && v_count < f2_v_sync_end) ||\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:632: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && (v_count >= f1_v_sync_start && v_count < f1_v_sync_end)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:632: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && (v_count >= f1_v_sync_start && v_count < f1_v_sync_end)));\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:634: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign anc_datavalid_nxt = enable_synced_nxt && h_count >= h_blank && (v_count >= f2_anc_v_start || \n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:634: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign anc_datavalid_nxt = enable_synced_nxt && h_count >= h_blank && (v_count >= f2_anc_v_start || \n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:635: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && v_count >= f1_anc_v_start && v_count < f1_v_end));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:635: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && v_count >= f1_anc_v_start && v_count < f1_v_end));\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:636: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_f_nxt = interlaced && (v_count >= f_rising_edge && v_count < f_falling_edge);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:636: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_f_nxt = interlaced && (v_count >= f_rising_edge && v_count < f_falling_edge);\n ^\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:652: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) clear_underflow_sticky_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:712: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) enable_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:718: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME, 2) genlock_enable_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:731: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'cp_ticks\' generates 1 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (cp_ticks == 2) ? BLANKING_SER1 :\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:784: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'cp_ticks\' generates 1 bits.\n : ... In instance alt_vipitc131_IS2Vid\n assign sav_enable = (serial_output) ? cp_ticks == TRS_CP_OFFSET : 1\'b1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:787: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (sav_enable && h_count == sav));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:800: Operator LTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n vid_ln_reg <= (v_count <= ap_line_end) ? v_count_plus_ap[10:0] : v_count_minus_ap[10:0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:838: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n assign v_count_plus_ap = v_count + ap_line;\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:839: Operator SUB expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n assign v_count_minus_ap = v_count - ap_line_end;\n ^\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:934: Cannot find file containing module: \'alt_vipitc131_common_fifo\'\nalt_vipitc131_common_fifo input_fifo(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1059: Cannot find file containing module: \'alt_vipitc131_IS2Vid_statemachine\'\nalt_vipitc131_IS2Vid_statemachine #(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1100: Cannot find file containing module: \'alt_vipitc131_common_sync_generation\'\n alt_vipitc131_common_sync_generation sync_generation(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1138: Cannot find file containing module: \'alt_vipitc131_common_sync\'\n alt_vipitc131_common_sync #(0) sof_cvi_sync(\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1144: Cannot find file containing module: \'alt_vipitc131_common_sync\'\n alt_vipitc131_common_sync #(0) sof_cvi_locked_sync(\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1151: Cannot find file containing module: \'alt_vipitc131_common_sync\'\n alt_vipitc131_common_sync #(0) sof_cvo_sync(\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1157: Cannot find file containing module: \'alt_vipitc131_IS2Vid_sync_compare\'\n alt_vipitc131_IS2Vid_sync_compare sync_compare(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 20 error(s), 31 warning(s)\n' | 7,601 | module | module alt_vipitc131_IS2Vid(
rst,
vid_clk,
vid_data,
vid_datavalid,
vid_v,
vid_h,
vid_f,
vid_v_sync,
vid_h_sync,
vid_ln,
vid_trs,
vid_std,
vid_mode_change,
vid_sof,
vid_sof_locked,
vid_vcoclk_div,
is_clk,
is_ready,
is_valid,
is_data,
is_sop,
is_eop,
av_address,
av_read,
av_readdata,
av_write,
av_writedata,
av_waitrequest,
sof,
sof_locked,
status_update_int,
underflow);
parameter BPS = 10;
parameter NUMBER_OF_COLOUR_PLANES = 2;
parameter COLOUR_PLANES_ARE_IN_PARALLEL = 1;
parameter FIFO_DEPTH = 1920;
parameter USE_EMBEDDED_SYNCS = 1;
parameter CLOCKS_ARE_SAME = 0;
parameter USE_CONTROL = 1;
parameter Y_C_SWAP = 1;
parameter NO_OF_MODES = 3;
parameter ACCEPT_COLOURS_IN_SEQ = 0;
parameter THRESHOLD = 0;
parameter STD_WIDTH = 3;
parameter GENERATE_SYNC = 1;
parameter INTERLACED = 0;
parameter AP_LINE = 42;
parameter H_ACTIVE_PIXELS = 1920;
parameter H_SYNC_LENGTH = 112;
parameter H_FRONT_PORCH = 48;
parameter H_BACK_PORCH = 120;
parameter H_OFFSET = 0;
parameter H_BLANK = 280;
parameter V_ACTIVE_LINES = 538;
parameter V_SYNC_LENGTH = 3;
parameter V_FRONT_PORCH = 4;
parameter V_BACK_PORCH = 38;
parameter V_OFFSET = 0;
parameter V_BLANK = 45;
parameter F_RISING_EDGE = 564;
parameter F_FALLING_EDGE = 18;
parameter FIELD0_V_RISING_EDGE = 561;
parameter FIELD0_V_SYNC_LENGTH = 3;
parameter FIELD0_V_FRONT_PORCH = 4;
parameter FIELD0_V_BACK_PORCH = 38;
parameter FIELD0_V_BLANK = 45;
parameter ANC_LINE = 10;
parameter FIELD0_ANC_LINE = 562;
localparam CONVERT_SEQ_TO_PAR = COLOUR_PLANES_ARE_IN_PARALLEL == 1 && ACCEPT_COLOURS_IN_SEQ != 0 && NUMBER_OF_COLOUR_PLANES > 1;
localparam COLOUR_PLANES_IN_SEQUENCE = (COLOUR_PLANES_ARE_IN_PARALLEL && !CONVERT_SEQ_TO_PAR) ? 1 : NUMBER_OF_COLOUR_PLANES;
localparam DATA_WIDTH = (COLOUR_PLANES_ARE_IN_PARALLEL) ? BPS * NUMBER_OF_COLOUR_PLANES : BPS;
localparam NUMBER_OF_COLOUR_PLANES_IN_PARALLEL = (COLOUR_PLANES_ARE_IN_PARALLEL) ? NUMBER_OF_COLOUR_PLANES : 1;
localparam READ_LATENCY = 2;
localparam TRS_PARALLEL = 4;
localparam TRS_SEQUENCE = 4 / NUMBER_OF_COLOUR_PLANES;
localparam TRS = (COLOUR_PLANES_ARE_IN_PARALLEL) ? TRS_PARALLEL : TRS_SEQUENCE;
localparam TRS_CP_OFFSET = 4 % NUMBER_OF_COLOUR_PLANES;
localparam H_BLANK_INT = (USE_EMBEDDED_SYNCS) ? H_BLANK : H_FRONT_PORCH + H_SYNC_LENGTH + H_BACK_PORCH;
localparam V_BLANK_INT = (USE_EMBEDDED_SYNCS) ? V_BLANK : V_FRONT_PORCH + V_SYNC_LENGTH + V_BACK_PORCH;
localparam FIELD0_V_BLANK_INT = (USE_EMBEDDED_SYNCS) ? FIELD0_V_BLANK : FIELD0_V_FRONT_PORCH + FIELD0_V_SYNC_LENGTH + FIELD0_V_BACK_PORCH;
localparam FIELD0_V_RISING_EDGE_INT = FIELD0_V_RISING_EDGE - AP_LINE;
localparam H_TOTAL = H_ACTIVE_PIXELS + H_BLANK_INT;
localparam V_TOTAL = V_ACTIVE_LINES + ((INTERLACED) ? FIELD0_V_BLANK_INT : 0) + V_BLANK_INT;
localparam LOG2_H_TOTAL = alt_clogb2(H_TOTAL);
localparam LOG2_V_TOTAL = alt_clogb2(V_TOTAL);
localparam LOG2_COLOUR_PLANES_IN_SEQUENCE = alt_clogb2(COLOUR_PLANES_IN_SEQUENCE);
localparam NO_OF_MODES_INT = (USE_CONTROL) ? NO_OF_MODES : 1;
localparam LOG2_NO_OF_MODES = alt_clogb2(NO_OF_MODES_INT);
localparam COLOUR_PLANES_IN_SEQUENCE_FIFO = (COLOUR_PLANES_ARE_IN_PARALLEL) ? 1 : NUMBER_OF_COLOUR_PLANES;
localparam FIFO_DEPTH_INT = (FIFO_DEPTH * COLOUR_PLANES_IN_SEQUENCE_FIFO) + 4;
localparam THRESHOLD_INT = (THRESHOLD * COLOUR_PLANES_IN_SEQUENCE_FIFO);
localparam USED_WORDS_WIDTH = alt_clogb2(FIFO_DEPTH_INT);
localparam F_RISING_EDGE_INT = F_RISING_EDGE - AP_LINE;
localparam F_FALLING_EDGE_INT = V_TOTAL - (AP_LINE - F_RISING_EDGE);
localparam F0_LINE_COUNT = (INTERLACED) ? FIELD0_V_RISING_EDGE_INT : V_ACTIVE_LINES;
localparam F1_LINE_COUNT = V_ACTIVE_LINES - F0_LINE_COUNT;
localparam BLANKING_SER1 = (BPS < 10) ? 128 : 512;
localparam BLANKING_SER2 = (BPS < 10) ? 16 : 64;
localparam BLANKING_PAR = 66048;
function integer alt_clogb2;
input [31:0] value;
integer i;
begin
alt_clogb2 = 32;
for (i=31; i>0; i=i-1) begin
if (2**i>=value)
alt_clogb2 = i;
end
end
endfunction
function [9:0] calc_xyz;
input [2:0] FVH;
case (FVH)
3'b000 : calc_xyz = 10'h200;
3'b001 : calc_xyz = 10'h274;
3'b010 : calc_xyz = 10'h2ac;
3'b011 : calc_xyz = 10'h2d8;
3'b100 : calc_xyz = 10'h31c;
3'b101 : calc_xyz = 10'h368;
3'b110 : calc_xyz = 10'h3b0;
3'b111 : calc_xyz = 10'h3c4;
endcase
endfunction
input rst;
input vid_clk;
output [DATA_WIDTH-1:0] vid_data;
output vid_datavalid;
output vid_v;
output vid_h;
output vid_f;
output vid_v_sync;
output vid_h_sync;
output [10:0] vid_ln;
output vid_trs;
output [STD_WIDTH-1:0] vid_std;
output vid_mode_change;
output vid_sof;
output vid_sof_locked;
output vid_vcoclk_div;
input is_clk;
output is_ready;
input is_valid;
input [DATA_WIDTH-1:0] is_data;
input is_sop;
input is_eop;
input [7:0] av_address;
input av_read;
output [15:0] av_readdata;
input av_write;
input [15:0] av_writedata;
output av_waitrequest;
input sof;
input sof_locked;
output status_update_int;
output underflow;
reg [DATA_WIDTH-1:0] vid_data;
wire vid_v;
wire vid_h;
wire vid_f;
wire vid_v_sync;
wire vid_h_sync;
wire vid_trs;
wire vid_datavalid;
wire vid_sof;
wire vid_sof_locked;
reg vid_v_reg;
reg vid_h_reg;
reg vid_f_reg;
reg vid_v_sync_reg;
reg vid_h_sync_reg;
reg vid_datavalid_reg;
wire status_update_int;
wire vid_f_nxt;
wire vid_h_nxt;
wire vid_v_nxt;
wire vid_h_sync_nxt;
wire vid_v_sync_nxt;
reg [READ_LATENCY-1:0] vid_datavalid_pipeline;
reg [READ_LATENCY-1:0] vid_f_pipeline;
reg [READ_LATENCY-1:0] vid_h_pipeline;
reg [READ_LATENCY-1:0] vid_v_pipeline;
reg [READ_LATENCY-1:0] vid_h_sync_pipeline;
reg [READ_LATENCY-1:0] vid_v_sync_pipeline;
reg [READ_LATENCY-1:0] anc_valid_word_pipeline;
wire rdreq;
wire rdreq_pre_swap;
wire wrreq;
wire [DATA_WIDTH-1:0] q_data;
wire [DATA_WIDTH-1:0] q_post_swap;
wire empty;
wire [USED_WORDS_WIDTH-1:0] usedw;
wire [USED_WORDS_WIDTH-1:0] rdusedw;
wire enable;
wire [11:0] h_count;
wire [11:0] v_count;
wire v_enable;
wire request_data_nxt;
reg request_data;
reg request_data_valid;
wire trs;
wire [DATA_WIDTH-1:0] trs_data;
wire ap;
wire [DATA_WIDTH-1:0] vid_data_pre_ln;
wire [DATA_WIDTH:0] q;
wire [DATA_WIDTH:0] writedata;
wire sop;
reg sop_reg;
wire enable_sync1;
reg enable_synced;
reg enable_threshold;
wire threshold_reached;
reg [15:0] frames_in_sync;
reg reset_counters;
wire enable_synced_nxt;
wire ap_synched;
wire underflow_nxt;
wire anc_underflow_nxt;
reg underflow_reg;
localparam [3:0] IDLE = 4'd0;
localparam [3:0] FIND_SOP = 4'd1;
localparam [3:0] WIDTH_3 = 4'd2;
localparam [3:0] WIDTH_2 = 4'd3;
localparam [3:0] WIDTH_1 = 4'd4;
localparam [3:0] WIDTH_0 = 4'd5;
localparam [3:0] HEIGHT_3 = 4'd6;
localparam [3:0] HEIGHT_2 = 4'd7;
localparam [3:0] HEIGHT_1 = 4'd8;
localparam [3:0] HEIGHT_0 = 4'd9;
localparam [3:0] INTERLACING = 4'd10;
localparam [3:0] FIND_MODE = 4'd11;
localparam [3:0] SYNCHED = 4'd12;
localparam [3:0] WAIT_FOR_SYNCH = 4'd13;
localparam [3:0] WAIT_FOR_ANC = 4'd14;
localparam [3:0] INSERT_ANC = 4'd15;
wire [3:0] state_next, state;
reg [15:0] samples, lines;
reg [3:0] interlaced_field;
reg field_prediction;
wire field_prediction_nxt;
reg start_of_ap;
wire start_of_ap_nxt;
reg start_of_vsync;
wire clear_underflow_sticky;
wire clear_underflow_sticky_sync1;
wire vid_clk_int;
wire rst_vid_clk;
wire [DATA_WIDTH-1:0] blanking_value;
wire start_of_cp;
wire start_of_frame, vid_datavalid_nxt;
wire anc_datavalid_nxt;
wire anc_valid_word_nxt;
wire find_mode_nxt;
wire wait_for_anc_nxt;
wire mode_change;
wire dirty_modes;
wire [NO_OF_MODES_INT-1:0] mode_match_safe;
wire write_trigger;
wire write_trigger_ack;
wire [1:0] genlock_enable;
wire [1:0] genlock_enable_sync1;
wire genlocked;
wire genlocked_sync1;
wire mode_write;
wire sync_lines;
wire sync_samples;
wire remove_repeatn;
wire [15:0] sync_compare_h_reset;
wire [15:0] sync_compare_v_reset;
wire interlaced;
wire serial_output;
wire [15:0] h_total_minus_one;
wire [15:0] v_total_minus_one;
wire [15:0] ap_line;
wire [15:0] ap_line_end;
wire [15:0] h_blank;
wire [15:0] sav;
wire [15:0] h_sync_start;
wire [15:0] h_sync_end;
wire [15:0] f2_v_start;
wire [15:0] f1_v_start;
wire [15:0] f1_v_end;
wire [15:0] f2_v_sync_start;
wire [15:0] f2_v_sync_end;
wire [15:0] f1_v_sync_start;
wire [15:0] f1_v_sync_end;
wire [15:0] f_rising_edge;
wire [15:0] f_falling_edge;
wire [15:0] f1_v_end_nxt;
wire [12:0] total_line_count_f0;
wire [12:0] total_line_count_f1;
wire [13:0] sof_sample;
wire [12:0] sof_line;
wire [1:0] sof_subsample;
wire [13:0] vcoclk_divider_value;
wire [15:0] f2_anc_v_start;
wire [15:0] f1_anc_v_start;
generate
if(CLOCKS_ARE_SAME) begin
assign rst_vid_clk = rst;
assign vid_clk_int = is_clk;
end else begin
reg rst_vid_clk_reg;
reg rst_vid_clk_reg2;
always @ (posedge rst or posedge vid_clk_int) begin
if(rst) begin
rst_vid_clk_reg <= 1'b1;
rst_vid_clk_reg2 <= 1'b1;
end else begin
rst_vid_clk_reg <= 1'b0;
rst_vid_clk_reg2 <= rst_vid_clk_reg;
end
end
assign rst_vid_clk = rst_vid_clk_reg2;
assign vid_clk_int = vid_clk;
end
endgenerate
wire enable_resync1;
wire underflow_sticky_sync1;
wire mode_change_sync1;
wire av_write_ack;
alt_vipitc131_common_sync #(CLOCKS_ARE_SAME) enable_resync_sync(
.rst(rst),
.sync_clock(is_clk),
.data_in(enable_synced),
.data_out(enable_resync1));
alt_vipitc131_common_sync #(CLOCKS_ARE_SAME) underflow_sync(
.rst(rst),
.sync_clock(is_clk),
.data_in(underflow),
.data_out(underflow_sticky_sync1));
alt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) mode_change_trigger_sync(
.input_rst(rst_vid_clk),
.input_clock(vid_clk_int),
.rst(rst),
.sync_clock(is_clk),
.trigger_in(mode_change),
.ack_in(1'b0),
.trigger_out(mode_change_sync1));
alt_vipitc131_common_sync #(CLOCKS_ARE_SAME) genlocked_sync(
.rst(rst),
.sync_clock(is_clk),
.data_in(genlocked),
.data_out(genlocked_sync1));
alt_vipitc131_IS2Vid_control control(
.rst(rst),
.clk(is_clk),
.av_write_ack(av_write_ack),
.mode_change(mode_change_sync1),
.mode_match(mode_match_safe),
.usedw(usedw),
.underflow_sticky(underflow_sticky_sync1),
.enable_resync(enable_resync1),
.genlocked(genlocked_sync1),
.enable(enable),
.clear_underflow_sticky(clear_underflow_sticky),
.write_trigger(write_trigger),
.write_trigger_ack(write_trigger_ack),
.genlock_enable(genlock_enable),
.av_address(av_address),
.av_read(av_read),
.av_readdata(av_readdata),
.av_write(av_write),
.av_writedata(av_writedata),
.av_waitrequest(av_waitrequest),
.status_update_int(status_update_int));
defparam control.USE_CONTROL = USE_CONTROL,
control.NO_OF_MODES_INT = NO_OF_MODES_INT,
control.USED_WORDS_WIDTH = USED_WORDS_WIDTH;
alt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) av_write_trigger_sync(
.input_rst(rst),
.input_clock(is_clk),
.rst(rst_vid_clk),
.sync_clock(vid_clk_int),
.trigger_in(write_trigger),
.ack_in(write_trigger_ack),
.trigger_out(mode_write));
alt_vipitc131_IS2Vid_mode_banks mode_banks(
.rst(rst_vid_clk),
.clk(vid_clk_int),
.mode_write(mode_write),
.find_mode_nxt(find_mode_nxt),
.av_address(av_address),
.av_writedata(av_writedata),
.mode_match_safe(mode_match_safe),
.dirty_modes(dirty_modes),
.mode_change(mode_change),
.vid_std(vid_std),
.vid_mode_change(vid_mode_change),
.interlaced_field(interlaced_field),
.field_prediction(field_prediction_nxt),
.samples(samples),
.lines(lines),
.interlaced(interlaced),
.serial_output(serial_output),
.h_total_minus_one(h_total_minus_one),
.v_total_minus_one(v_total_minus_one),
.ap_line(ap_line),
.ap_line_end(ap_line_end),
.h_blank(h_blank),
.sav(sav),
.h_sync_start(h_sync_start),
.h_sync_end(h_sync_end),
.f2_v_start(f2_v_start),
.f1_v_start(f1_v_start),
.f1_v_end(f1_v_end),
.f2_v_sync_start(f2_v_sync_start),
.f2_v_sync_end(f2_v_sync_end),
.f1_v_sync_start(f1_v_sync_start),
.f1_v_sync_end(f1_v_sync_end),
.f_rising_edge(f_rising_edge),
.f_falling_edge(f_falling_edge),
.f1_v_end_nxt(f1_v_end_nxt),
.sof_sample(sof_sample),
.sof_line(sof_line),
.sof_subsample(sof_subsample),
.vcoclk_divider_value(vcoclk_divider_value),
.f2_anc_v_start(f2_anc_v_start),
.f1_anc_v_start(f1_anc_v_start)
);
defparam mode_banks.USE_CONTROL = USE_CONTROL,
mode_banks.NO_OF_MODES_INT = NO_OF_MODES_INT,
mode_banks.LOG2_NO_OF_MODES = LOG2_NO_OF_MODES,
mode_banks.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
mode_banks.TRS = TRS,
mode_banks.INTERLACED = INTERLACED,
mode_banks.H_ACTIVE_PIXELS = H_ACTIVE_PIXELS,
mode_banks.F0_LINE_COUNT = F0_LINE_COUNT,
mode_banks.F1_LINE_COUNT = F1_LINE_COUNT,
mode_banks.H_FRONT_PORCH = H_FRONT_PORCH,
mode_banks.H_SYNC_LENGTH = H_SYNC_LENGTH,
mode_banks.H_BLANK_INT = H_BLANK_INT,
mode_banks.V_FRONT_PORCH = V_FRONT_PORCH,
mode_banks.V_SYNC_LENGTH = V_SYNC_LENGTH,
mode_banks.V_BLANK_INT = V_BLANK_INT,
mode_banks.FIELD0_V_FRONT_PORCH = FIELD0_V_FRONT_PORCH,
mode_banks.FIELD0_V_SYNC_LENGTH = FIELD0_V_SYNC_LENGTH,
mode_banks.FIELD0_V_BLANK_INT = FIELD0_V_BLANK_INT,
mode_banks.AP_LINE = AP_LINE,
mode_banks.FIELD0_V_RISING_EDGE = FIELD0_V_RISING_EDGE,
mode_banks.F_RISING_EDGE = F_RISING_EDGE,
mode_banks.F_FALLING_EDGE = F_FALLING_EDGE,
mode_banks.CONVERT_SEQ_TO_PAR = CONVERT_SEQ_TO_PAR,
mode_banks.TRS_SEQUENCE = TRS_SEQUENCE,
mode_banks.TRS_PARALLEL = TRS_PARALLEL,
mode_banks.STD_WIDTH = STD_WIDTH,
mode_banks.ANC_LINE = ANC_LINE,
mode_banks.FIELD0_ANC_LINE = FIELD0_ANC_LINE;
alt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) av_waitrequest_trigger_sync(
.input_rst(rst_vid_clk),
.input_clock(vid_clk_int),
.rst(rst),
.sync_clock(is_clk),
.trigger_in(mode_write),
.ack_in(1'b0),
.trigger_out(av_write_ack));
wire enable_vcount;
wire [LOG2_COLOUR_PLANES_IN_SEQUENCE-1:0] cp_ticks;
wire repeat_reset_point;
wire remove_reset_point;
wire repeat_lines_reset;
wire remove_lines_reset;
wire repeat_samples_reset;
wire remove_samples_reset;
wire lines_reset;
wire samples_reset;
wire clear_enable;
wire restart_sample_count;
wire restart_lines_count;
wire [15:0] v_reset_value;
wire restart_line_count;
localparam integer v_offset_const = V_OFFSET;
localparam integer h_offset_const = H_OFFSET;
assign repeat_reset_point = !remove_repeatn && h_count == sync_compare_h_reset && v_count == sync_compare_v_reset;
assign remove_reset_point = remove_repeatn && h_count == 16'd0 && v_count == 16'd0;
assign repeat_lines_reset = sync_lines & repeat_reset_point;
assign remove_lines_reset = sync_lines & remove_reset_point;
assign repeat_samples_reset = sync_samples & repeat_reset_point;
assign remove_samples_reset = sync_samples & remove_reset_point;
assign lines_reset = (repeat_lines_reset || remove_lines_reset) && ((cp_ticks == NUMBER_OF_COLOUR_PLANES - 1) || ~serial_output);
assign samples_reset = (repeat_samples_reset || remove_samples_reset) && ((cp_ticks == NUMBER_OF_COLOUR_PLANES - 1) || ~serial_output);
assign clear_enable = mode_change | reset_counters;
assign restart_line_count = clear_enable | lines_reset;
assign restart_sample_count = clear_enable | samples_reset;
assign v_reset_value = (genlock_enable_sync1[0]) ? (remove_repeatn) ? sync_compare_v_reset : v_offset_const[15:0] :
(interlaced_field[3] & field_prediction) ? f1_v_end_nxt : v_offset_const[15:0];
alt_vipitc131_common_generic_count
#(.WORD_LENGTH(12),
.RESET_VALUE(H_OFFSET),
.TICKS_WORD_LENGTH(LOG2_COLOUR_PLANES_IN_SEQUENCE),
.TICKS_PER_COUNT(COLOUR_PLANES_IN_SEQUENCE))
h_counter
(.clk(vid_clk_int),
.reset_n(~rst_vid_clk),
.enable(enable_synced_nxt),
.enable_ticks(serial_output),
.max_count(h_total_minus_one),
.count(h_count),
.restart_count(restart_sample_count),
.reset_value((remove_repeatn) ? sync_compare_h_reset : H_OFFSET),
.enable_count(enable_vcount),
.start_count(start_of_cp),
.cp_ticks(cp_ticks));
alt_vipitc131_common_generic_count
#(.WORD_LENGTH(12),
.RESET_VALUE(V_OFFSET))
v_counter
(.clk(vid_clk_int),
.reset_n(~rst_vid_clk),
.enable(v_enable),
.max_count(v_total_minus_one),
.count(v_count),
.restart_count(restart_line_count),
.reset_value(v_reset_value));
assign start_of_frame = (start_of_cp && h_count == H_OFFSET) && ((interlaced && v_count == f1_v_end) || v_count == V_OFFSET);
assign v_enable = enable_synced_nxt && enable_vcount && h_count == h_total_minus_one;
assign ap = h_count >= h_blank && ~vid_v_nxt;
assign vid_h_nxt = enable_synced_nxt && h_count < h_blank;
assign vid_h_sync_nxt = enable_synced_nxt && (h_count >= h_sync_start && h_count < h_sync_end);
assign vid_v_nxt = enable_synced_nxt && (v_count >= f2_v_start ||
(interlaced && (v_count >= f1_v_start && v_count < f1_v_end)));
assign vid_v_sync_nxt = enable_synced_nxt && ((v_count >= f2_v_sync_start && v_count < f2_v_sync_end) ||
(interlaced && (v_count >= f1_v_sync_start && v_count < f1_v_sync_end)));
assign vid_datavalid_nxt = enable_synced_nxt & ap;
assign anc_datavalid_nxt = enable_synced_nxt && h_count >= h_blank && (v_count >= f2_anc_v_start ||
(interlaced && v_count >= f1_anc_v_start && v_count < f1_v_end));
assign vid_f_nxt = interlaced && (v_count >= f_rising_edge && v_count < f_falling_edge);
assign underflow = underflow_reg;
assign underflow_nxt = vid_datavalid_nxt & empty;
assign anc_underflow_nxt = anc_datavalid_nxt & empty;
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if (rst_vid_clk) begin
underflow_reg <= 1'b0;
end else begin
underflow_reg <= (underflow_nxt | underflow_reg) & ~clear_underflow_sticky_sync1;
end
end
alt_vipitc131_common_sync #(CLOCKS_ARE_SAME) clear_underflow_sticky_sync(
.rst(rst_vid_clk),
.sync_clock(vid_clk_int),
.data_in(clear_underflow_sticky),
.data_out(clear_underflow_sticky_sync1));
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if (rst_vid_clk) begin
enable_threshold <= 1'b0;
frames_in_sync <= 16'd0;
enable_synced <= 1'b0;
vid_f_pipeline <= {READ_LATENCY{1'b0}};
vid_h_pipeline <= {READ_LATENCY{1'b0}};
vid_h_sync_pipeline <= {READ_LATENCY{1'b0}};
vid_v_pipeline <= {READ_LATENCY{1'b0}};
vid_v_sync_pipeline <= {READ_LATENCY{1'b0}};
vid_datavalid_pipeline <= {READ_LATENCY{1'b0}};
anc_valid_word_pipeline <= {READ_LATENCY{1'b0}};
vid_f_reg <= 1'b0;
vid_h_reg <= 1'b0;
vid_h_sync_reg <= 1'b0;
vid_v_reg <= 1'b0;
vid_v_sync_reg <= 1'b0;
vid_datavalid_reg <= 1'b0;
end else begin
if(clear_enable) begin
enable_threshold <= 1'b0;
frames_in_sync <= 16'd0;
end else begin
enable_threshold <= (threshold_reached | enable_threshold) & enable_sync1;
if(enable_synced_nxt & start_of_frame)
frames_in_sync <= frames_in_sync + 1'b1;
end
enable_synced <= enable_synced_nxt;
vid_f_pipeline <= {vid_f_pipeline[READ_LATENCY-2:0], vid_f_nxt};
vid_h_pipeline <= {vid_h_pipeline[READ_LATENCY-2:0], vid_h_nxt};
vid_h_sync_pipeline <= {vid_h_sync_pipeline[READ_LATENCY-2:0], vid_h_sync_nxt};
vid_v_pipeline <= {vid_v_pipeline[READ_LATENCY-2:0], vid_v_nxt};
vid_v_sync_pipeline <= {vid_v_sync_pipeline[READ_LATENCY-2:0], vid_v_sync_nxt};
vid_datavalid_pipeline <= {vid_datavalid_pipeline[READ_LATENCY-2:0], vid_datavalid_nxt};
anc_valid_word_pipeline <= {anc_valid_word_pipeline[READ_LATENCY-2:0], anc_valid_word_nxt};
vid_f_reg <= vid_f_pipeline[READ_LATENCY-1];
vid_h_reg <= vid_h_pipeline[READ_LATENCY-1];
vid_h_sync_reg <= vid_h_sync_pipeline[READ_LATENCY-1];
vid_v_reg <= vid_v_pipeline[READ_LATENCY-1];
vid_v_sync_reg <= vid_v_sync_pipeline[READ_LATENCY-1];
vid_datavalid_reg <= vid_datavalid_pipeline[READ_LATENCY-1];
end
end
assign threshold_reached = rdusedw >= THRESHOLD_INT;
assign enable_synced_nxt = (start_of_frame) ? enable_threshold : enable_synced;
alt_vipitc131_common_sync #(CLOCKS_ARE_SAME) enable_sync(
.rst(rst_vid_clk),
.sync_clock(vid_clk_int),
.data_in(enable),
.data_out(enable_sync1));
alt_vipitc131_common_sync #(CLOCKS_ARE_SAME, 2) genlock_enable_sync(
.rst(rst_vid_clk),
.sync_clock(vid_clk_int),
.data_in(genlock_enable),
.data_out(genlock_enable_sync1));
generate
if(USE_EMBEDDED_SYNCS) begin
wire [BPS-1:0] blanking_serial;
wire [DATA_WIDTH-1:0] blanking_parallel;
assign blanking_serial = (cp_ticks == 0) ? BLANKING_SER1 :
(cp_ticks == 1) ? BLANKING_SER2 :
(cp_ticks == 2) ? BLANKING_SER1 :
BLANKING_SER2;
if(NUMBER_OF_COLOUR_PLANES_IN_PARALLEL > 1) begin
genvar i;
for(i = 0; i < NUMBER_OF_COLOUR_PLANES; i=i+1) begin : xyz_creation
if(i % 2 == 0)
assign blanking_parallel[(i*BPS)+BPS-1:i*BPS] = BLANKING_SER1;
else
assign blanking_parallel[(i*BPS)+BPS-1:i*BPS] = BLANKING_SER2;
assign blanking_value[(i*BPS)+BPS-1:i*BPS] = (serial_output) ? blanking_serial : blanking_parallel[(i*BPS)+BPS-1:i*BPS];
end
end else
assign blanking_value[DATA_WIDTH-1:0] = blanking_serial;
end else
assign blanking_value = {DATA_WIDTH{1'b0}};
endgenerate
assign vid_data_pre_ln = (trs) ? trs_data : (~vid_datavalid_pipeline[READ_LATENCY-1] & ~(anc_valid_word_pipeline[READ_LATENCY-1] & ~(sop | sop_reg))) ? blanking_value : q_post_swap;
parameter [2:0] S_IDLE = 3'b000;
parameter [2:0] S_TRS_WORD2 = 3'b001;
parameter [2:0] S_TRS_WORD3 = 3'b010;
parameter [2:0] S_TRS_XYZ = 3'b011;
parameter [2:0] S_TRS_LN0 = 3'b100;
parameter [2:0] S_TRS_LN1 = 3'b101;
parameter [2:0] S_TRS_CR0 = 3'b110;
parameter [2:0] S_TRS_CR1 = 3'b111;
generate
if(USE_EMBEDDED_SYNCS) begin
wire vid_trs_nxt;
reg vid_trs_reg;
reg [10:0] vid_ln_reg;
reg [READ_LATENCY-1:0] vid_trs_pipeline;
wire [9:0] xyz;
wire [DATA_WIDTH-1:0] flags;
wire vid_trs_int;
wire trs_word2;
wire trs_word3;
wire trs_xyz;
reg [2:0] emb_state;
wire [BPS-1:0] xyz_fixed;
wire sav_enable;
wire [15:0] v_count_plus_ap;
wire [15:0] v_count_minus_ap;
assign sav_enable = (serial_output) ? cp_ticks == TRS_CP_OFFSET : 1'b1;
assign vid_trs_nxt = enable_synced_nxt && ((start_of_cp && h_count == 0) ||
(sav_enable && h_count == sav));
assign xyz = calc_xyz({vid_f_nxt, vid_v_nxt, vid_h_nxt});
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if (rst_vid_clk) begin
vid_trs_pipeline <= {READ_LATENCY{1'b0}};
vid_trs_reg <= 1'b0;
vid_ln_reg <= 11'd0;
emb_state <= S_IDLE;
end else begin
vid_trs_pipeline <= {vid_trs_pipeline[READ_LATENCY-2:0], vid_trs_nxt};
vid_trs_reg <= vid_trs_int;
vid_ln_reg <= (v_count <= ap_line_end) ? v_count_plus_ap[10:0] : v_count_minus_ap[10:0];
if(enable_synced_nxt)
case (emb_state)
S_IDLE: begin
if(vid_trs_int)
emb_state <= S_TRS_WORD2;
end
S_TRS_WORD2 : emb_state <= S_TRS_WORD3;
S_TRS_WORD3 : emb_state <= S_TRS_XYZ;
S_TRS_XYZ : emb_state <= S_IDLE;
endcase
end
end
assign vid_trs_int = vid_trs_pipeline[READ_LATENCY-1];
if(BPS > 10)
assign xyz_fixed = {{BPS-10{1'b0}}, xyz};
else
assign xyz_fixed = xyz[9:10-BPS];
genvar i;
if(COLOUR_PLANES_ARE_IN_PARALLEL)
for(i = 0; i < NUMBER_OF_COLOUR_PLANES; i=i+1) begin : xyz_creation
assign flags[(i*BPS)+BPS-1:i*BPS] = xyz_fixed;
end
else
assign flags[BPS-1:0] = xyz_fixed;
assign trs_word2 = (emb_state == S_TRS_WORD2);
assign trs_word3 = (emb_state == S_TRS_WORD3);
assign trs_xyz = (emb_state == S_TRS_XYZ);
assign trs = vid_trs_int | trs_word2 | trs_word3 | trs_xyz;
assign trs_data = (vid_trs_int) ? {DATA_WIDTH{1'b1}} :
(trs_word2) ? {DATA_WIDTH{1'b0}} :
(trs_word3) ? {DATA_WIDTH{1'b0}} :
flags;
assign v_count_plus_ap = v_count + ap_line;
assign v_count_minus_ap = v_count - ap_line_end;
assign vid_ln = vid_ln_reg;
assign vid_trs = vid_trs_reg;
assign vid_v = 1'b0;
assign vid_h = 1'b0;
assign vid_f = 1'b0;
assign vid_v_sync = 1'b0;
assign vid_h_sync = 1'b0;
assign vid_datavalid = 1'b0;
end else begin
assign trs = 1'b0;
assign trs_data = {DATA_WIDTH{1'bx}};
assign vid_ln = 11'd0;
assign vid_trs = 1'b0;
assign vid_v = vid_v_reg;
assign vid_h = vid_h_reg;
assign vid_f = vid_f_reg;
assign vid_v_sync = vid_v_sync_reg;
assign vid_h_sync = vid_h_sync_reg;
assign vid_datavalid = vid_datavalid_reg;
end
endgenerate
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if (rst_vid_clk)
vid_data <= {DATA_WIDTH{1'b0}};
else
vid_data <= vid_data_pre_ln;
end
generate
if(CONVERT_SEQ_TO_PAR) begin
reg stall_req;
reg [LOG2_COLOUR_PLANES_IN_SEQUENCE-1:0] cp_ticks_pipeline[READ_LATENCY-1:0];
wire [LOG2_COLOUR_PLANES_IN_SEQUENCE-1:0] cp_ticks_delayed;
wire [BPS-1:0] q_mux[NUMBER_OF_COLOUR_PLANES-1:0];
genvar i;
for(i = 0; i < NUMBER_OF_COLOUR_PLANES; i=i+1) begin : q_mux_generation
assign q_mux[i] = q_data[(i*BPS)+(BPS-1):(i*BPS)];
end
for(i = 0; i < (READ_LATENCY-1); i=i+1) begin : cp_ticks_pipeline_generation
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if (rst_vid_clk) begin
cp_ticks_pipeline[i+1] <= {LOG2_COLOUR_PLANES_IN_SEQUENCE{1'b0}};
end else begin
if(serial_output && state_next == INSERT_ANC) begin
cp_ticks_pipeline[i+1] <= 1;
end else begin
cp_ticks_pipeline[i+1] <= cp_ticks_pipeline[i];
end
end
end
end
assign cp_ticks_delayed = cp_ticks_pipeline[READ_LATENCY-1];
assign q_post_swap = {q_data[DATA_WIDTH-1:BPS], q_mux[cp_ticks_delayed]};
assign rdreq_pre_swap = rdreq & ~stall_req;
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if (rst_vid_clk) begin
cp_ticks_pipeline[0] <= {LOG2_COLOUR_PLANES_IN_SEQUENCE{1'b0}};
stall_req <= 1'b0;
end else begin
cp_ticks_pipeline[0] <= cp_ticks;
if(serial_output && state == SYNCHED) begin
if(cp_ticks_delayed == NUMBER_OF_COLOUR_PLANES - 2) begin
stall_req <= 1'b0;
end else begin
stall_req <= 1'b1;
end
end else begin
stall_req <= 1'b0;
end
end
end
end else begin
assign q_post_swap = q_data;
assign rdreq_pre_swap = rdreq;
end
endgenerate
assign is_ready = ~(usedw >= (FIFO_DEPTH_INT - 4));
assign {q_data, sop} = q;
assign writedata = {is_data, is_sop};
alt_vipitc131_common_fifo input_fifo(
.wrclk(is_clk),
.rdreq(rdreq_pre_swap),
.aclr(rst),
.rdclk(vid_clk_int),
.wrreq(is_valid),
.data(writedata),
.rdempty(empty),
.rdusedw(rdusedw),
.q(q),
.wrusedw(usedw));
defparam
input_fifo.DATA_WIDTH = DATA_WIDTH + 1,
input_fifo.CLOCKS_ARE_SAME = CLOCKS_ARE_SAME,
input_fifo.FIFO_DEPTH = FIFO_DEPTH_INT;
reg request_data_stalled;
reg sync_lost;
reg interlaced_field_valid;
wire interlaced_field_valid_nxt;
wire start_of_vsync_nxt;
wire lost_field_sync;
assign lost_field_sync = genlock_enable_sync1[0] & (vid_f_nxt ^ field_prediction);
assign ap_synched = start_of_ap_nxt & ~lost_field_sync;
assign rdreq = request_data & ~empty;
assign start_of_ap_nxt = ap & ~start_of_ap;
assign interlaced_field_valid_nxt = (state == WIDTH_3 || interlaced_field_valid) &&
!(state == SYNCHED && state_next != SYNCHED);
assign field_prediction_nxt = (interlaced_field_valid_nxt) ? interlaced_field[2] :
(state == SYNCHED && state_next != SYNCHED) ? ~field_prediction & interlaced_field[3] :
field_prediction & interlaced_field[3];
assign anc_valid_word_nxt = (state_next == INSERT_ANC) && anc_datavalid_nxt;
generate
if(USE_EMBEDDED_SYNCS)
assign start_of_vsync_nxt = vid_v_pipeline[READ_LATENCY-2] & ~vid_v_pipeline[READ_LATENCY-1];
else
assign start_of_vsync_nxt = vid_v_sync_pipeline[READ_LATENCY-2] & ~vid_v_sync_pipeline[READ_LATENCY-1];
endgenerate
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if(rst_vid_clk) begin
start_of_ap <= 1'b0;
start_of_vsync <= 1'b0;
request_data <= 1'b0;
request_data_stalled <= 1'b0;
request_data_valid <= 1'b0;
sync_lost <= 1'b0;
reset_counters <= 1'b0;
interlaced_field_valid <= 1'b0;
field_prediction <= 1'b0;
sop_reg <= 1'b0;
end else begin
start_of_ap <= (start_of_frame | vid_v_nxt | reset_counters) ? 1'b0 : ap | start_of_ap;
start_of_vsync <= start_of_vsync_nxt;
request_data <= ~(find_mode_nxt ||
wait_for_anc_nxt ||
state == FIND_MODE ||
state == WAIT_FOR_SYNCH ||
state == WAIT_FOR_ANC ||
(state == SYNCHED && ~vid_datavalid_nxt) ||
(state == INSERT_ANC && ~anc_datavalid_nxt)) ||
(request_data_stalled && ~rdreq);
request_data_stalled <= ((state != state_next && (state_next == FIND_MODE || state_next == WAIT_FOR_ANC)) || request_data_stalled) && ~rdreq;
request_data_valid <= rdreq;
sync_lost <= (( (state != FIND_MODE && state != WAIT_FOR_SYNCH && start_of_ap_nxt)
|| (state == SYNCHED && request_data_valid && sop && !vid_v_pipeline[READ_LATENCY-2])
|| (underflow_nxt)
|| (state == SYNCHED && interlaced_field_valid && interlaced_field[3] && (field_prediction != vid_f_nxt))
|| sync_lost) && !reset_counters && !mode_change) && !genlock_enable_sync1[0];
reset_counters <= sync_lost && (state_next == WAIT_FOR_SYNCH);
interlaced_field_valid <= interlaced_field_valid_nxt;
field_prediction <= field_prediction_nxt;
sop_reg <= sop;
end
end
generate
begin : generate_control_header
genvar i;
genvar symbol;
for(symbol = 0; symbol < 9; symbol = symbol + NUMBER_OF_COLOUR_PLANES_IN_PARALLEL) begin : header_extraction
for(i = 0; i < NUMBER_OF_COLOUR_PLANES_IN_PARALLEL; i = i + 1) begin : unpack_control_header
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if(rst_vid_clk) begin
case(symbol + i)
0 : samples[15:12] <= 4'd0;
1 : samples[11:8] <= 4'd0;
2 : samples[7:4] <= 4'd0;
3 : samples[3:0] <= 4'd0;
4 : lines[15:12] <= 4'd0;
5 : lines[11:8] <= 4'd0;
6 : lines[7:4] <= 4'd0;
7 : lines[3:0] <= 4'd0;
8 : interlaced_field <= 4'd0;
endcase
end else begin
if(state == (WIDTH_3 + symbol/NUMBER_OF_COLOUR_PLANES_IN_PARALLEL)) begin
case(symbol + i)
0 : samples[15:12] <= q_data[BPS*i+3:BPS*i];
1 : samples[11:8] <= q_data[BPS*i+3:BPS*i];
2 : samples[7:4] <= q_data[BPS*i+3:BPS*i];
3 : samples[3:0] <= q_data[BPS*i+3:BPS*i];
4 : lines[15:12] <= q_data[BPS*i+3:BPS*i];
5 : lines[11:8] <= q_data[BPS*i+3:BPS*i];
6 : lines[7:4] <= q_data[BPS*i+3:BPS*i];
7 : lines[3:0] <= q_data[BPS*i+3:BPS*i];
8 : interlaced_field <= q_data[BPS*i+3:BPS*i];
endcase
end
end
end
end
end
end
endgenerate
assign find_mode_nxt = state_next == FIND_MODE;
assign wait_for_anc_nxt = state_next == WAIT_FOR_ANC;
alt_vipitc131_IS2Vid_statemachine #(
.USE_EMBEDDED_SYNCS(USE_EMBEDDED_SYNCS),
.NUMBER_OF_COLOUR_PLANES_IN_PARALLEL(NUMBER_OF_COLOUR_PLANES_IN_PARALLEL),
.IDLE(IDLE),
.FIND_SOP(FIND_SOP),
.WIDTH_3(WIDTH_3),
.WIDTH_2(WIDTH_2),
.WIDTH_1(WIDTH_1),
.WIDTH_0(WIDTH_0),
.HEIGHT_3(HEIGHT_3),
.HEIGHT_2(HEIGHT_2),
.HEIGHT_1(HEIGHT_1),
.HEIGHT_0(HEIGHT_0),
.INTERLACING(INTERLACING),
.FIND_MODE(FIND_MODE),
.SYNCHED(SYNCHED),
.WAIT_FOR_SYNCH(WAIT_FOR_SYNCH),
.WAIT_FOR_ANC(WAIT_FOR_ANC),
.INSERT_ANC(INSERT_ANC)
)
statemachine(
.rst(rst_vid_clk),
.clk(vid_clk_int),
.request_data_valid(request_data_valid),
.sop(sop),
.vid_v_nxt(vid_v_nxt),
.anc_datavalid_nxt(anc_datavalid_nxt),
.q_data(q_data[3:0]),
.sync_lost(sync_lost),
.anc_underflow_nxt(anc_underflow_nxt),
.ap_synched(ap_synched),
.enable_synced_nxt(enable_synced_nxt),
.state_next(state_next),
.state(state));
generate begin : sync_generation_generate
if(GENERATE_SYNC) begin
wire restart_count;
assign restart_count = restart_sample_count | restart_line_count;
alt_vipitc131_common_sync_generation sync_generation(
.rst(rst_vid_clk),
.clk(vid_clk_int),
.clear_enable(restart_count),
.enable_count(1'b1),
.hd_sdn(~serial_output),
.start_of_vsync(start_of_vsync),
.field_prediction(field_prediction),
.interlaced(interlaced),
.total_sample_count(h_total_minus_one[13:0]),
.total_sample_count_valid(1'b1),
.total_line_count(v_total_minus_one[13:0]),
.total_line_count_valid(1'b1),
.stable(enable_synced_nxt),
.divider_value(vcoclk_divider_value),
.sof_sample(sof_sample),
.sof_line(sof_line),
.sof_subsample(sof_subsample),
.output_enable(genlock_enable_sync1[0]),
.sof(vid_sof),
.sof_locked(vid_sof_locked),
.div(vid_vcoclk_div));
defparam sync_generation.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
sync_generation.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
sync_generation.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_COLOUR_PLANES_IN_SEQUENCE,
sync_generation.TOTALS_MINUS_ONE = 1;
assign sync_compare_h_reset[15:13] = 3'b000;
assign sync_compare_v_reset[15:13] = 3'b000;
wire sof_cvi_sync1;
wire sof_cvi_locked_sync1;
wire vid_sof_sync1;
alt_vipitc131_common_sync #(0) sof_cvi_sync(
.rst(rst_vid_clk),
.sync_clock(vid_clk_int),
.data_in(sof),
.data_out(sof_cvi_sync1));
alt_vipitc131_common_sync #(0) sof_cvi_locked_sync(
.rst(rst_vid_clk),
.sync_clock(vid_clk_int),
.data_in(sof_locked),
.data_out(sof_cvi_locked_sync1));
alt_vipitc131_common_sync #(0) sof_cvo_sync(
.rst(rst_vid_clk),
.sync_clock(vid_clk_int),
.data_in(vid_sof),
.data_out(vid_sof_sync1));
alt_vipitc131_IS2Vid_sync_compare sync_compare(
.rst(rst_vid_clk),
.clk(vid_clk_int),
.genlock_enable(genlock_enable_sync1),
.serial_output(serial_output),
.h_total_minus_one(h_total_minus_one[13:0]),
.restart_count(restart_count),
.divider_value(vcoclk_divider_value),
.sync_lines(sync_lines),
.sync_samples(sync_samples),
.remove_repeatn(remove_repeatn),
.sync_compare_h_reset(sync_compare_h_reset[12:0]),
.sync_compare_v_reset(sync_compare_v_reset[12:0]),
.genlocked(genlocked),
.sof_cvi(sof_cvi_sync1),
.sof_cvi_locked(sof_cvi_locked_sync1),
.sof_cvo(vid_sof_sync1),
.sof_cvo_locked(vid_sof_locked));
defparam
sync_compare.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
sync_compare.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
sync_compare.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_COLOUR_PLANES_IN_SEQUENCE;
end else begin
assign vid_sof = 1'b0;
assign vid_sof_locked = 1'b0;
assign vid_vcoclk_div = 1'b0;
assign remove_repeatn = 1'b0;
assign sync_compare_h_reset = v_offset_const[15:0];
assign sync_compare_v_reset = v_offset_const[15:0];
assign sync_samples = 1'b0;
assign sync_lines = 1'b0;
assign genlocked = 1'b0;
end
end endgenerate
endmodule | module alt_vipitc131_IS2Vid(
rst,
vid_clk,
vid_data,
vid_datavalid,
vid_v,
vid_h,
vid_f,
vid_v_sync,
vid_h_sync,
vid_ln,
vid_trs,
vid_std,
vid_mode_change,
vid_sof,
vid_sof_locked,
vid_vcoclk_div,
is_clk,
is_ready,
is_valid,
is_data,
is_sop,
is_eop,
av_address,
av_read,
av_readdata,
av_write,
av_writedata,
av_waitrequest,
sof,
sof_locked,
status_update_int,
underflow); |
parameter BPS = 10;
parameter NUMBER_OF_COLOUR_PLANES = 2;
parameter COLOUR_PLANES_ARE_IN_PARALLEL = 1;
parameter FIFO_DEPTH = 1920;
parameter USE_EMBEDDED_SYNCS = 1;
parameter CLOCKS_ARE_SAME = 0;
parameter USE_CONTROL = 1;
parameter Y_C_SWAP = 1;
parameter NO_OF_MODES = 3;
parameter ACCEPT_COLOURS_IN_SEQ = 0;
parameter THRESHOLD = 0;
parameter STD_WIDTH = 3;
parameter GENERATE_SYNC = 1;
parameter INTERLACED = 0;
parameter AP_LINE = 42;
parameter H_ACTIVE_PIXELS = 1920;
parameter H_SYNC_LENGTH = 112;
parameter H_FRONT_PORCH = 48;
parameter H_BACK_PORCH = 120;
parameter H_OFFSET = 0;
parameter H_BLANK = 280;
parameter V_ACTIVE_LINES = 538;
parameter V_SYNC_LENGTH = 3;
parameter V_FRONT_PORCH = 4;
parameter V_BACK_PORCH = 38;
parameter V_OFFSET = 0;
parameter V_BLANK = 45;
parameter F_RISING_EDGE = 564;
parameter F_FALLING_EDGE = 18;
parameter FIELD0_V_RISING_EDGE = 561;
parameter FIELD0_V_SYNC_LENGTH = 3;
parameter FIELD0_V_FRONT_PORCH = 4;
parameter FIELD0_V_BACK_PORCH = 38;
parameter FIELD0_V_BLANK = 45;
parameter ANC_LINE = 10;
parameter FIELD0_ANC_LINE = 562;
localparam CONVERT_SEQ_TO_PAR = COLOUR_PLANES_ARE_IN_PARALLEL == 1 && ACCEPT_COLOURS_IN_SEQ != 0 && NUMBER_OF_COLOUR_PLANES > 1;
localparam COLOUR_PLANES_IN_SEQUENCE = (COLOUR_PLANES_ARE_IN_PARALLEL && !CONVERT_SEQ_TO_PAR) ? 1 : NUMBER_OF_COLOUR_PLANES;
localparam DATA_WIDTH = (COLOUR_PLANES_ARE_IN_PARALLEL) ? BPS * NUMBER_OF_COLOUR_PLANES : BPS;
localparam NUMBER_OF_COLOUR_PLANES_IN_PARALLEL = (COLOUR_PLANES_ARE_IN_PARALLEL) ? NUMBER_OF_COLOUR_PLANES : 1;
localparam READ_LATENCY = 2;
localparam TRS_PARALLEL = 4;
localparam TRS_SEQUENCE = 4 / NUMBER_OF_COLOUR_PLANES;
localparam TRS = (COLOUR_PLANES_ARE_IN_PARALLEL) ? TRS_PARALLEL : TRS_SEQUENCE;
localparam TRS_CP_OFFSET = 4 % NUMBER_OF_COLOUR_PLANES;
localparam H_BLANK_INT = (USE_EMBEDDED_SYNCS) ? H_BLANK : H_FRONT_PORCH + H_SYNC_LENGTH + H_BACK_PORCH;
localparam V_BLANK_INT = (USE_EMBEDDED_SYNCS) ? V_BLANK : V_FRONT_PORCH + V_SYNC_LENGTH + V_BACK_PORCH;
localparam FIELD0_V_BLANK_INT = (USE_EMBEDDED_SYNCS) ? FIELD0_V_BLANK : FIELD0_V_FRONT_PORCH + FIELD0_V_SYNC_LENGTH + FIELD0_V_BACK_PORCH;
localparam FIELD0_V_RISING_EDGE_INT = FIELD0_V_RISING_EDGE - AP_LINE;
localparam H_TOTAL = H_ACTIVE_PIXELS + H_BLANK_INT;
localparam V_TOTAL = V_ACTIVE_LINES + ((INTERLACED) ? FIELD0_V_BLANK_INT : 0) + V_BLANK_INT;
localparam LOG2_H_TOTAL = alt_clogb2(H_TOTAL);
localparam LOG2_V_TOTAL = alt_clogb2(V_TOTAL);
localparam LOG2_COLOUR_PLANES_IN_SEQUENCE = alt_clogb2(COLOUR_PLANES_IN_SEQUENCE);
localparam NO_OF_MODES_INT = (USE_CONTROL) ? NO_OF_MODES : 1;
localparam LOG2_NO_OF_MODES = alt_clogb2(NO_OF_MODES_INT);
localparam COLOUR_PLANES_IN_SEQUENCE_FIFO = (COLOUR_PLANES_ARE_IN_PARALLEL) ? 1 : NUMBER_OF_COLOUR_PLANES;
localparam FIFO_DEPTH_INT = (FIFO_DEPTH * COLOUR_PLANES_IN_SEQUENCE_FIFO) + 4;
localparam THRESHOLD_INT = (THRESHOLD * COLOUR_PLANES_IN_SEQUENCE_FIFO);
localparam USED_WORDS_WIDTH = alt_clogb2(FIFO_DEPTH_INT);
localparam F_RISING_EDGE_INT = F_RISING_EDGE - AP_LINE;
localparam F_FALLING_EDGE_INT = V_TOTAL - (AP_LINE - F_RISING_EDGE);
localparam F0_LINE_COUNT = (INTERLACED) ? FIELD0_V_RISING_EDGE_INT : V_ACTIVE_LINES;
localparam F1_LINE_COUNT = V_ACTIVE_LINES - F0_LINE_COUNT;
localparam BLANKING_SER1 = (BPS < 10) ? 128 : 512;
localparam BLANKING_SER2 = (BPS < 10) ? 16 : 64;
localparam BLANKING_PAR = 66048;
function integer alt_clogb2;
input [31:0] value;
integer i;
begin
alt_clogb2 = 32;
for (i=31; i>0; i=i-1) begin
if (2**i>=value)
alt_clogb2 = i;
end
end
endfunction
function [9:0] calc_xyz;
input [2:0] FVH;
case (FVH)
3'b000 : calc_xyz = 10'h200;
3'b001 : calc_xyz = 10'h274;
3'b010 : calc_xyz = 10'h2ac;
3'b011 : calc_xyz = 10'h2d8;
3'b100 : calc_xyz = 10'h31c;
3'b101 : calc_xyz = 10'h368;
3'b110 : calc_xyz = 10'h3b0;
3'b111 : calc_xyz = 10'h3c4;
endcase
endfunction
input rst;
input vid_clk;
output [DATA_WIDTH-1:0] vid_data;
output vid_datavalid;
output vid_v;
output vid_h;
output vid_f;
output vid_v_sync;
output vid_h_sync;
output [10:0] vid_ln;
output vid_trs;
output [STD_WIDTH-1:0] vid_std;
output vid_mode_change;
output vid_sof;
output vid_sof_locked;
output vid_vcoclk_div;
input is_clk;
output is_ready;
input is_valid;
input [DATA_WIDTH-1:0] is_data;
input is_sop;
input is_eop;
input [7:0] av_address;
input av_read;
output [15:0] av_readdata;
input av_write;
input [15:0] av_writedata;
output av_waitrequest;
input sof;
input sof_locked;
output status_update_int;
output underflow;
reg [DATA_WIDTH-1:0] vid_data;
wire vid_v;
wire vid_h;
wire vid_f;
wire vid_v_sync;
wire vid_h_sync;
wire vid_trs;
wire vid_datavalid;
wire vid_sof;
wire vid_sof_locked;
reg vid_v_reg;
reg vid_h_reg;
reg vid_f_reg;
reg vid_v_sync_reg;
reg vid_h_sync_reg;
reg vid_datavalid_reg;
wire status_update_int;
wire vid_f_nxt;
wire vid_h_nxt;
wire vid_v_nxt;
wire vid_h_sync_nxt;
wire vid_v_sync_nxt;
reg [READ_LATENCY-1:0] vid_datavalid_pipeline;
reg [READ_LATENCY-1:0] vid_f_pipeline;
reg [READ_LATENCY-1:0] vid_h_pipeline;
reg [READ_LATENCY-1:0] vid_v_pipeline;
reg [READ_LATENCY-1:0] vid_h_sync_pipeline;
reg [READ_LATENCY-1:0] vid_v_sync_pipeline;
reg [READ_LATENCY-1:0] anc_valid_word_pipeline;
wire rdreq;
wire rdreq_pre_swap;
wire wrreq;
wire [DATA_WIDTH-1:0] q_data;
wire [DATA_WIDTH-1:0] q_post_swap;
wire empty;
wire [USED_WORDS_WIDTH-1:0] usedw;
wire [USED_WORDS_WIDTH-1:0] rdusedw;
wire enable;
wire [11:0] h_count;
wire [11:0] v_count;
wire v_enable;
wire request_data_nxt;
reg request_data;
reg request_data_valid;
wire trs;
wire [DATA_WIDTH-1:0] trs_data;
wire ap;
wire [DATA_WIDTH-1:0] vid_data_pre_ln;
wire [DATA_WIDTH:0] q;
wire [DATA_WIDTH:0] writedata;
wire sop;
reg sop_reg;
wire enable_sync1;
reg enable_synced;
reg enable_threshold;
wire threshold_reached;
reg [15:0] frames_in_sync;
reg reset_counters;
wire enable_synced_nxt;
wire ap_synched;
wire underflow_nxt;
wire anc_underflow_nxt;
reg underflow_reg;
localparam [3:0] IDLE = 4'd0;
localparam [3:0] FIND_SOP = 4'd1;
localparam [3:0] WIDTH_3 = 4'd2;
localparam [3:0] WIDTH_2 = 4'd3;
localparam [3:0] WIDTH_1 = 4'd4;
localparam [3:0] WIDTH_0 = 4'd5;
localparam [3:0] HEIGHT_3 = 4'd6;
localparam [3:0] HEIGHT_2 = 4'd7;
localparam [3:0] HEIGHT_1 = 4'd8;
localparam [3:0] HEIGHT_0 = 4'd9;
localparam [3:0] INTERLACING = 4'd10;
localparam [3:0] FIND_MODE = 4'd11;
localparam [3:0] SYNCHED = 4'd12;
localparam [3:0] WAIT_FOR_SYNCH = 4'd13;
localparam [3:0] WAIT_FOR_ANC = 4'd14;
localparam [3:0] INSERT_ANC = 4'd15;
wire [3:0] state_next, state;
reg [15:0] samples, lines;
reg [3:0] interlaced_field;
reg field_prediction;
wire field_prediction_nxt;
reg start_of_ap;
wire start_of_ap_nxt;
reg start_of_vsync;
wire clear_underflow_sticky;
wire clear_underflow_sticky_sync1;
wire vid_clk_int;
wire rst_vid_clk;
wire [DATA_WIDTH-1:0] blanking_value;
wire start_of_cp;
wire start_of_frame, vid_datavalid_nxt;
wire anc_datavalid_nxt;
wire anc_valid_word_nxt;
wire find_mode_nxt;
wire wait_for_anc_nxt;
wire mode_change;
wire dirty_modes;
wire [NO_OF_MODES_INT-1:0] mode_match_safe;
wire write_trigger;
wire write_trigger_ack;
wire [1:0] genlock_enable;
wire [1:0] genlock_enable_sync1;
wire genlocked;
wire genlocked_sync1;
wire mode_write;
wire sync_lines;
wire sync_samples;
wire remove_repeatn;
wire [15:0] sync_compare_h_reset;
wire [15:0] sync_compare_v_reset;
wire interlaced;
wire serial_output;
wire [15:0] h_total_minus_one;
wire [15:0] v_total_minus_one;
wire [15:0] ap_line;
wire [15:0] ap_line_end;
wire [15:0] h_blank;
wire [15:0] sav;
wire [15:0] h_sync_start;
wire [15:0] h_sync_end;
wire [15:0] f2_v_start;
wire [15:0] f1_v_start;
wire [15:0] f1_v_end;
wire [15:0] f2_v_sync_start;
wire [15:0] f2_v_sync_end;
wire [15:0] f1_v_sync_start;
wire [15:0] f1_v_sync_end;
wire [15:0] f_rising_edge;
wire [15:0] f_falling_edge;
wire [15:0] f1_v_end_nxt;
wire [12:0] total_line_count_f0;
wire [12:0] total_line_count_f1;
wire [13:0] sof_sample;
wire [12:0] sof_line;
wire [1:0] sof_subsample;
wire [13:0] vcoclk_divider_value;
wire [15:0] f2_anc_v_start;
wire [15:0] f1_anc_v_start;
generate
if(CLOCKS_ARE_SAME) begin
assign rst_vid_clk = rst;
assign vid_clk_int = is_clk;
end else begin
reg rst_vid_clk_reg;
reg rst_vid_clk_reg2;
always @ (posedge rst or posedge vid_clk_int) begin
if(rst) begin
rst_vid_clk_reg <= 1'b1;
rst_vid_clk_reg2 <= 1'b1;
end else begin
rst_vid_clk_reg <= 1'b0;
rst_vid_clk_reg2 <= rst_vid_clk_reg;
end
end
assign rst_vid_clk = rst_vid_clk_reg2;
assign vid_clk_int = vid_clk;
end
endgenerate
wire enable_resync1;
wire underflow_sticky_sync1;
wire mode_change_sync1;
wire av_write_ack;
alt_vipitc131_common_sync #(CLOCKS_ARE_SAME) enable_resync_sync(
.rst(rst),
.sync_clock(is_clk),
.data_in(enable_synced),
.data_out(enable_resync1));
alt_vipitc131_common_sync #(CLOCKS_ARE_SAME) underflow_sync(
.rst(rst),
.sync_clock(is_clk),
.data_in(underflow),
.data_out(underflow_sticky_sync1));
alt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) mode_change_trigger_sync(
.input_rst(rst_vid_clk),
.input_clock(vid_clk_int),
.rst(rst),
.sync_clock(is_clk),
.trigger_in(mode_change),
.ack_in(1'b0),
.trigger_out(mode_change_sync1));
alt_vipitc131_common_sync #(CLOCKS_ARE_SAME) genlocked_sync(
.rst(rst),
.sync_clock(is_clk),
.data_in(genlocked),
.data_out(genlocked_sync1));
alt_vipitc131_IS2Vid_control control(
.rst(rst),
.clk(is_clk),
.av_write_ack(av_write_ack),
.mode_change(mode_change_sync1),
.mode_match(mode_match_safe),
.usedw(usedw),
.underflow_sticky(underflow_sticky_sync1),
.enable_resync(enable_resync1),
.genlocked(genlocked_sync1),
.enable(enable),
.clear_underflow_sticky(clear_underflow_sticky),
.write_trigger(write_trigger),
.write_trigger_ack(write_trigger_ack),
.genlock_enable(genlock_enable),
.av_address(av_address),
.av_read(av_read),
.av_readdata(av_readdata),
.av_write(av_write),
.av_writedata(av_writedata),
.av_waitrequest(av_waitrequest),
.status_update_int(status_update_int));
defparam control.USE_CONTROL = USE_CONTROL,
control.NO_OF_MODES_INT = NO_OF_MODES_INT,
control.USED_WORDS_WIDTH = USED_WORDS_WIDTH;
alt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) av_write_trigger_sync(
.input_rst(rst),
.input_clock(is_clk),
.rst(rst_vid_clk),
.sync_clock(vid_clk_int),
.trigger_in(write_trigger),
.ack_in(write_trigger_ack),
.trigger_out(mode_write));
alt_vipitc131_IS2Vid_mode_banks mode_banks(
.rst(rst_vid_clk),
.clk(vid_clk_int),
.mode_write(mode_write),
.find_mode_nxt(find_mode_nxt),
.av_address(av_address),
.av_writedata(av_writedata),
.mode_match_safe(mode_match_safe),
.dirty_modes(dirty_modes),
.mode_change(mode_change),
.vid_std(vid_std),
.vid_mode_change(vid_mode_change),
.interlaced_field(interlaced_field),
.field_prediction(field_prediction_nxt),
.samples(samples),
.lines(lines),
.interlaced(interlaced),
.serial_output(serial_output),
.h_total_minus_one(h_total_minus_one),
.v_total_minus_one(v_total_minus_one),
.ap_line(ap_line),
.ap_line_end(ap_line_end),
.h_blank(h_blank),
.sav(sav),
.h_sync_start(h_sync_start),
.h_sync_end(h_sync_end),
.f2_v_start(f2_v_start),
.f1_v_start(f1_v_start),
.f1_v_end(f1_v_end),
.f2_v_sync_start(f2_v_sync_start),
.f2_v_sync_end(f2_v_sync_end),
.f1_v_sync_start(f1_v_sync_start),
.f1_v_sync_end(f1_v_sync_end),
.f_rising_edge(f_rising_edge),
.f_falling_edge(f_falling_edge),
.f1_v_end_nxt(f1_v_end_nxt),
.sof_sample(sof_sample),
.sof_line(sof_line),
.sof_subsample(sof_subsample),
.vcoclk_divider_value(vcoclk_divider_value),
.f2_anc_v_start(f2_anc_v_start),
.f1_anc_v_start(f1_anc_v_start)
);
defparam mode_banks.USE_CONTROL = USE_CONTROL,
mode_banks.NO_OF_MODES_INT = NO_OF_MODES_INT,
mode_banks.LOG2_NO_OF_MODES = LOG2_NO_OF_MODES,
mode_banks.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
mode_banks.TRS = TRS,
mode_banks.INTERLACED = INTERLACED,
mode_banks.H_ACTIVE_PIXELS = H_ACTIVE_PIXELS,
mode_banks.F0_LINE_COUNT = F0_LINE_COUNT,
mode_banks.F1_LINE_COUNT = F1_LINE_COUNT,
mode_banks.H_FRONT_PORCH = H_FRONT_PORCH,
mode_banks.H_SYNC_LENGTH = H_SYNC_LENGTH,
mode_banks.H_BLANK_INT = H_BLANK_INT,
mode_banks.V_FRONT_PORCH = V_FRONT_PORCH,
mode_banks.V_SYNC_LENGTH = V_SYNC_LENGTH,
mode_banks.V_BLANK_INT = V_BLANK_INT,
mode_banks.FIELD0_V_FRONT_PORCH = FIELD0_V_FRONT_PORCH,
mode_banks.FIELD0_V_SYNC_LENGTH = FIELD0_V_SYNC_LENGTH,
mode_banks.FIELD0_V_BLANK_INT = FIELD0_V_BLANK_INT,
mode_banks.AP_LINE = AP_LINE,
mode_banks.FIELD0_V_RISING_EDGE = FIELD0_V_RISING_EDGE,
mode_banks.F_RISING_EDGE = F_RISING_EDGE,
mode_banks.F_FALLING_EDGE = F_FALLING_EDGE,
mode_banks.CONVERT_SEQ_TO_PAR = CONVERT_SEQ_TO_PAR,
mode_banks.TRS_SEQUENCE = TRS_SEQUENCE,
mode_banks.TRS_PARALLEL = TRS_PARALLEL,
mode_banks.STD_WIDTH = STD_WIDTH,
mode_banks.ANC_LINE = ANC_LINE,
mode_banks.FIELD0_ANC_LINE = FIELD0_ANC_LINE;
alt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) av_waitrequest_trigger_sync(
.input_rst(rst_vid_clk),
.input_clock(vid_clk_int),
.rst(rst),
.sync_clock(is_clk),
.trigger_in(mode_write),
.ack_in(1'b0),
.trigger_out(av_write_ack));
wire enable_vcount;
wire [LOG2_COLOUR_PLANES_IN_SEQUENCE-1:0] cp_ticks;
wire repeat_reset_point;
wire remove_reset_point;
wire repeat_lines_reset;
wire remove_lines_reset;
wire repeat_samples_reset;
wire remove_samples_reset;
wire lines_reset;
wire samples_reset;
wire clear_enable;
wire restart_sample_count;
wire restart_lines_count;
wire [15:0] v_reset_value;
wire restart_line_count;
localparam integer v_offset_const = V_OFFSET;
localparam integer h_offset_const = H_OFFSET;
assign repeat_reset_point = !remove_repeatn && h_count == sync_compare_h_reset && v_count == sync_compare_v_reset;
assign remove_reset_point = remove_repeatn && h_count == 16'd0 && v_count == 16'd0;
assign repeat_lines_reset = sync_lines & repeat_reset_point;
assign remove_lines_reset = sync_lines & remove_reset_point;
assign repeat_samples_reset = sync_samples & repeat_reset_point;
assign remove_samples_reset = sync_samples & remove_reset_point;
assign lines_reset = (repeat_lines_reset || remove_lines_reset) && ((cp_ticks == NUMBER_OF_COLOUR_PLANES - 1) || ~serial_output);
assign samples_reset = (repeat_samples_reset || remove_samples_reset) && ((cp_ticks == NUMBER_OF_COLOUR_PLANES - 1) || ~serial_output);
assign clear_enable = mode_change | reset_counters;
assign restart_line_count = clear_enable | lines_reset;
assign restart_sample_count = clear_enable | samples_reset;
assign v_reset_value = (genlock_enable_sync1[0]) ? (remove_repeatn) ? sync_compare_v_reset : v_offset_const[15:0] :
(interlaced_field[3] & field_prediction) ? f1_v_end_nxt : v_offset_const[15:0];
alt_vipitc131_common_generic_count
#(.WORD_LENGTH(12),
.RESET_VALUE(H_OFFSET),
.TICKS_WORD_LENGTH(LOG2_COLOUR_PLANES_IN_SEQUENCE),
.TICKS_PER_COUNT(COLOUR_PLANES_IN_SEQUENCE))
h_counter
(.clk(vid_clk_int),
.reset_n(~rst_vid_clk),
.enable(enable_synced_nxt),
.enable_ticks(serial_output),
.max_count(h_total_minus_one),
.count(h_count),
.restart_count(restart_sample_count),
.reset_value((remove_repeatn) ? sync_compare_h_reset : H_OFFSET),
.enable_count(enable_vcount),
.start_count(start_of_cp),
.cp_ticks(cp_ticks));
alt_vipitc131_common_generic_count
#(.WORD_LENGTH(12),
.RESET_VALUE(V_OFFSET))
v_counter
(.clk(vid_clk_int),
.reset_n(~rst_vid_clk),
.enable(v_enable),
.max_count(v_total_minus_one),
.count(v_count),
.restart_count(restart_line_count),
.reset_value(v_reset_value));
assign start_of_frame = (start_of_cp && h_count == H_OFFSET) && ((interlaced && v_count == f1_v_end) || v_count == V_OFFSET);
assign v_enable = enable_synced_nxt && enable_vcount && h_count == h_total_minus_one;
assign ap = h_count >= h_blank && ~vid_v_nxt;
assign vid_h_nxt = enable_synced_nxt && h_count < h_blank;
assign vid_h_sync_nxt = enable_synced_nxt && (h_count >= h_sync_start && h_count < h_sync_end);
assign vid_v_nxt = enable_synced_nxt && (v_count >= f2_v_start ||
(interlaced && (v_count >= f1_v_start && v_count < f1_v_end)));
assign vid_v_sync_nxt = enable_synced_nxt && ((v_count >= f2_v_sync_start && v_count < f2_v_sync_end) ||
(interlaced && (v_count >= f1_v_sync_start && v_count < f1_v_sync_end)));
assign vid_datavalid_nxt = enable_synced_nxt & ap;
assign anc_datavalid_nxt = enable_synced_nxt && h_count >= h_blank && (v_count >= f2_anc_v_start ||
(interlaced && v_count >= f1_anc_v_start && v_count < f1_v_end));
assign vid_f_nxt = interlaced && (v_count >= f_rising_edge && v_count < f_falling_edge);
assign underflow = underflow_reg;
assign underflow_nxt = vid_datavalid_nxt & empty;
assign anc_underflow_nxt = anc_datavalid_nxt & empty;
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if (rst_vid_clk) begin
underflow_reg <= 1'b0;
end else begin
underflow_reg <= (underflow_nxt | underflow_reg) & ~clear_underflow_sticky_sync1;
end
end
alt_vipitc131_common_sync #(CLOCKS_ARE_SAME) clear_underflow_sticky_sync(
.rst(rst_vid_clk),
.sync_clock(vid_clk_int),
.data_in(clear_underflow_sticky),
.data_out(clear_underflow_sticky_sync1));
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if (rst_vid_clk) begin
enable_threshold <= 1'b0;
frames_in_sync <= 16'd0;
enable_synced <= 1'b0;
vid_f_pipeline <= {READ_LATENCY{1'b0}};
vid_h_pipeline <= {READ_LATENCY{1'b0}};
vid_h_sync_pipeline <= {READ_LATENCY{1'b0}};
vid_v_pipeline <= {READ_LATENCY{1'b0}};
vid_v_sync_pipeline <= {READ_LATENCY{1'b0}};
vid_datavalid_pipeline <= {READ_LATENCY{1'b0}};
anc_valid_word_pipeline <= {READ_LATENCY{1'b0}};
vid_f_reg <= 1'b0;
vid_h_reg <= 1'b0;
vid_h_sync_reg <= 1'b0;
vid_v_reg <= 1'b0;
vid_v_sync_reg <= 1'b0;
vid_datavalid_reg <= 1'b0;
end else begin
if(clear_enable) begin
enable_threshold <= 1'b0;
frames_in_sync <= 16'd0;
end else begin
enable_threshold <= (threshold_reached | enable_threshold) & enable_sync1;
if(enable_synced_nxt & start_of_frame)
frames_in_sync <= frames_in_sync + 1'b1;
end
enable_synced <= enable_synced_nxt;
vid_f_pipeline <= {vid_f_pipeline[READ_LATENCY-2:0], vid_f_nxt};
vid_h_pipeline <= {vid_h_pipeline[READ_LATENCY-2:0], vid_h_nxt};
vid_h_sync_pipeline <= {vid_h_sync_pipeline[READ_LATENCY-2:0], vid_h_sync_nxt};
vid_v_pipeline <= {vid_v_pipeline[READ_LATENCY-2:0], vid_v_nxt};
vid_v_sync_pipeline <= {vid_v_sync_pipeline[READ_LATENCY-2:0], vid_v_sync_nxt};
vid_datavalid_pipeline <= {vid_datavalid_pipeline[READ_LATENCY-2:0], vid_datavalid_nxt};
anc_valid_word_pipeline <= {anc_valid_word_pipeline[READ_LATENCY-2:0], anc_valid_word_nxt};
vid_f_reg <= vid_f_pipeline[READ_LATENCY-1];
vid_h_reg <= vid_h_pipeline[READ_LATENCY-1];
vid_h_sync_reg <= vid_h_sync_pipeline[READ_LATENCY-1];
vid_v_reg <= vid_v_pipeline[READ_LATENCY-1];
vid_v_sync_reg <= vid_v_sync_pipeline[READ_LATENCY-1];
vid_datavalid_reg <= vid_datavalid_pipeline[READ_LATENCY-1];
end
end
assign threshold_reached = rdusedw >= THRESHOLD_INT;
assign enable_synced_nxt = (start_of_frame) ? enable_threshold : enable_synced;
alt_vipitc131_common_sync #(CLOCKS_ARE_SAME) enable_sync(
.rst(rst_vid_clk),
.sync_clock(vid_clk_int),
.data_in(enable),
.data_out(enable_sync1));
alt_vipitc131_common_sync #(CLOCKS_ARE_SAME, 2) genlock_enable_sync(
.rst(rst_vid_clk),
.sync_clock(vid_clk_int),
.data_in(genlock_enable),
.data_out(genlock_enable_sync1));
generate
if(USE_EMBEDDED_SYNCS) begin
wire [BPS-1:0] blanking_serial;
wire [DATA_WIDTH-1:0] blanking_parallel;
assign blanking_serial = (cp_ticks == 0) ? BLANKING_SER1 :
(cp_ticks == 1) ? BLANKING_SER2 :
(cp_ticks == 2) ? BLANKING_SER1 :
BLANKING_SER2;
if(NUMBER_OF_COLOUR_PLANES_IN_PARALLEL > 1) begin
genvar i;
for(i = 0; i < NUMBER_OF_COLOUR_PLANES; i=i+1) begin : xyz_creation
if(i % 2 == 0)
assign blanking_parallel[(i*BPS)+BPS-1:i*BPS] = BLANKING_SER1;
else
assign blanking_parallel[(i*BPS)+BPS-1:i*BPS] = BLANKING_SER2;
assign blanking_value[(i*BPS)+BPS-1:i*BPS] = (serial_output) ? blanking_serial : blanking_parallel[(i*BPS)+BPS-1:i*BPS];
end
end else
assign blanking_value[DATA_WIDTH-1:0] = blanking_serial;
end else
assign blanking_value = {DATA_WIDTH{1'b0}};
endgenerate
assign vid_data_pre_ln = (trs) ? trs_data : (~vid_datavalid_pipeline[READ_LATENCY-1] & ~(anc_valid_word_pipeline[READ_LATENCY-1] & ~(sop | sop_reg))) ? blanking_value : q_post_swap;
parameter [2:0] S_IDLE = 3'b000;
parameter [2:0] S_TRS_WORD2 = 3'b001;
parameter [2:0] S_TRS_WORD3 = 3'b010;
parameter [2:0] S_TRS_XYZ = 3'b011;
parameter [2:0] S_TRS_LN0 = 3'b100;
parameter [2:0] S_TRS_LN1 = 3'b101;
parameter [2:0] S_TRS_CR0 = 3'b110;
parameter [2:0] S_TRS_CR1 = 3'b111;
generate
if(USE_EMBEDDED_SYNCS) begin
wire vid_trs_nxt;
reg vid_trs_reg;
reg [10:0] vid_ln_reg;
reg [READ_LATENCY-1:0] vid_trs_pipeline;
wire [9:0] xyz;
wire [DATA_WIDTH-1:0] flags;
wire vid_trs_int;
wire trs_word2;
wire trs_word3;
wire trs_xyz;
reg [2:0] emb_state;
wire [BPS-1:0] xyz_fixed;
wire sav_enable;
wire [15:0] v_count_plus_ap;
wire [15:0] v_count_minus_ap;
assign sav_enable = (serial_output) ? cp_ticks == TRS_CP_OFFSET : 1'b1;
assign vid_trs_nxt = enable_synced_nxt && ((start_of_cp && h_count == 0) ||
(sav_enable && h_count == sav));
assign xyz = calc_xyz({vid_f_nxt, vid_v_nxt, vid_h_nxt});
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if (rst_vid_clk) begin
vid_trs_pipeline <= {READ_LATENCY{1'b0}};
vid_trs_reg <= 1'b0;
vid_ln_reg <= 11'd0;
emb_state <= S_IDLE;
end else begin
vid_trs_pipeline <= {vid_trs_pipeline[READ_LATENCY-2:0], vid_trs_nxt};
vid_trs_reg <= vid_trs_int;
vid_ln_reg <= (v_count <= ap_line_end) ? v_count_plus_ap[10:0] : v_count_minus_ap[10:0];
if(enable_synced_nxt)
case (emb_state)
S_IDLE: begin
if(vid_trs_int)
emb_state <= S_TRS_WORD2;
end
S_TRS_WORD2 : emb_state <= S_TRS_WORD3;
S_TRS_WORD3 : emb_state <= S_TRS_XYZ;
S_TRS_XYZ : emb_state <= S_IDLE;
endcase
end
end
assign vid_trs_int = vid_trs_pipeline[READ_LATENCY-1];
if(BPS > 10)
assign xyz_fixed = {{BPS-10{1'b0}}, xyz};
else
assign xyz_fixed = xyz[9:10-BPS];
genvar i;
if(COLOUR_PLANES_ARE_IN_PARALLEL)
for(i = 0; i < NUMBER_OF_COLOUR_PLANES; i=i+1) begin : xyz_creation
assign flags[(i*BPS)+BPS-1:i*BPS] = xyz_fixed;
end
else
assign flags[BPS-1:0] = xyz_fixed;
assign trs_word2 = (emb_state == S_TRS_WORD2);
assign trs_word3 = (emb_state == S_TRS_WORD3);
assign trs_xyz = (emb_state == S_TRS_XYZ);
assign trs = vid_trs_int | trs_word2 | trs_word3 | trs_xyz;
assign trs_data = (vid_trs_int) ? {DATA_WIDTH{1'b1}} :
(trs_word2) ? {DATA_WIDTH{1'b0}} :
(trs_word3) ? {DATA_WIDTH{1'b0}} :
flags;
assign v_count_plus_ap = v_count + ap_line;
assign v_count_minus_ap = v_count - ap_line_end;
assign vid_ln = vid_ln_reg;
assign vid_trs = vid_trs_reg;
assign vid_v = 1'b0;
assign vid_h = 1'b0;
assign vid_f = 1'b0;
assign vid_v_sync = 1'b0;
assign vid_h_sync = 1'b0;
assign vid_datavalid = 1'b0;
end else begin
assign trs = 1'b0;
assign trs_data = {DATA_WIDTH{1'bx}};
assign vid_ln = 11'd0;
assign vid_trs = 1'b0;
assign vid_v = vid_v_reg;
assign vid_h = vid_h_reg;
assign vid_f = vid_f_reg;
assign vid_v_sync = vid_v_sync_reg;
assign vid_h_sync = vid_h_sync_reg;
assign vid_datavalid = vid_datavalid_reg;
end
endgenerate
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if (rst_vid_clk)
vid_data <= {DATA_WIDTH{1'b0}};
else
vid_data <= vid_data_pre_ln;
end
generate
if(CONVERT_SEQ_TO_PAR) begin
reg stall_req;
reg [LOG2_COLOUR_PLANES_IN_SEQUENCE-1:0] cp_ticks_pipeline[READ_LATENCY-1:0];
wire [LOG2_COLOUR_PLANES_IN_SEQUENCE-1:0] cp_ticks_delayed;
wire [BPS-1:0] q_mux[NUMBER_OF_COLOUR_PLANES-1:0];
genvar i;
for(i = 0; i < NUMBER_OF_COLOUR_PLANES; i=i+1) begin : q_mux_generation
assign q_mux[i] = q_data[(i*BPS)+(BPS-1):(i*BPS)];
end
for(i = 0; i < (READ_LATENCY-1); i=i+1) begin : cp_ticks_pipeline_generation
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if (rst_vid_clk) begin
cp_ticks_pipeline[i+1] <= {LOG2_COLOUR_PLANES_IN_SEQUENCE{1'b0}};
end else begin
if(serial_output && state_next == INSERT_ANC) begin
cp_ticks_pipeline[i+1] <= 1;
end else begin
cp_ticks_pipeline[i+1] <= cp_ticks_pipeline[i];
end
end
end
end
assign cp_ticks_delayed = cp_ticks_pipeline[READ_LATENCY-1];
assign q_post_swap = {q_data[DATA_WIDTH-1:BPS], q_mux[cp_ticks_delayed]};
assign rdreq_pre_swap = rdreq & ~stall_req;
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if (rst_vid_clk) begin
cp_ticks_pipeline[0] <= {LOG2_COLOUR_PLANES_IN_SEQUENCE{1'b0}};
stall_req <= 1'b0;
end else begin
cp_ticks_pipeline[0] <= cp_ticks;
if(serial_output && state == SYNCHED) begin
if(cp_ticks_delayed == NUMBER_OF_COLOUR_PLANES - 2) begin
stall_req <= 1'b0;
end else begin
stall_req <= 1'b1;
end
end else begin
stall_req <= 1'b0;
end
end
end
end else begin
assign q_post_swap = q_data;
assign rdreq_pre_swap = rdreq;
end
endgenerate
assign is_ready = ~(usedw >= (FIFO_DEPTH_INT - 4));
assign {q_data, sop} = q;
assign writedata = {is_data, is_sop};
alt_vipitc131_common_fifo input_fifo(
.wrclk(is_clk),
.rdreq(rdreq_pre_swap),
.aclr(rst),
.rdclk(vid_clk_int),
.wrreq(is_valid),
.data(writedata),
.rdempty(empty),
.rdusedw(rdusedw),
.q(q),
.wrusedw(usedw));
defparam
input_fifo.DATA_WIDTH = DATA_WIDTH + 1,
input_fifo.CLOCKS_ARE_SAME = CLOCKS_ARE_SAME,
input_fifo.FIFO_DEPTH = FIFO_DEPTH_INT;
reg request_data_stalled;
reg sync_lost;
reg interlaced_field_valid;
wire interlaced_field_valid_nxt;
wire start_of_vsync_nxt;
wire lost_field_sync;
assign lost_field_sync = genlock_enable_sync1[0] & (vid_f_nxt ^ field_prediction);
assign ap_synched = start_of_ap_nxt & ~lost_field_sync;
assign rdreq = request_data & ~empty;
assign start_of_ap_nxt = ap & ~start_of_ap;
assign interlaced_field_valid_nxt = (state == WIDTH_3 || interlaced_field_valid) &&
!(state == SYNCHED && state_next != SYNCHED);
assign field_prediction_nxt = (interlaced_field_valid_nxt) ? interlaced_field[2] :
(state == SYNCHED && state_next != SYNCHED) ? ~field_prediction & interlaced_field[3] :
field_prediction & interlaced_field[3];
assign anc_valid_word_nxt = (state_next == INSERT_ANC) && anc_datavalid_nxt;
generate
if(USE_EMBEDDED_SYNCS)
assign start_of_vsync_nxt = vid_v_pipeline[READ_LATENCY-2] & ~vid_v_pipeline[READ_LATENCY-1];
else
assign start_of_vsync_nxt = vid_v_sync_pipeline[READ_LATENCY-2] & ~vid_v_sync_pipeline[READ_LATENCY-1];
endgenerate
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if(rst_vid_clk) begin
start_of_ap <= 1'b0;
start_of_vsync <= 1'b0;
request_data <= 1'b0;
request_data_stalled <= 1'b0;
request_data_valid <= 1'b0;
sync_lost <= 1'b0;
reset_counters <= 1'b0;
interlaced_field_valid <= 1'b0;
field_prediction <= 1'b0;
sop_reg <= 1'b0;
end else begin
start_of_ap <= (start_of_frame | vid_v_nxt | reset_counters) ? 1'b0 : ap | start_of_ap;
start_of_vsync <= start_of_vsync_nxt;
request_data <= ~(find_mode_nxt ||
wait_for_anc_nxt ||
state == FIND_MODE ||
state == WAIT_FOR_SYNCH ||
state == WAIT_FOR_ANC ||
(state == SYNCHED && ~vid_datavalid_nxt) ||
(state == INSERT_ANC && ~anc_datavalid_nxt)) ||
(request_data_stalled && ~rdreq);
request_data_stalled <= ((state != state_next && (state_next == FIND_MODE || state_next == WAIT_FOR_ANC)) || request_data_stalled) && ~rdreq;
request_data_valid <= rdreq;
sync_lost <= (( (state != FIND_MODE && state != WAIT_FOR_SYNCH && start_of_ap_nxt)
|| (state == SYNCHED && request_data_valid && sop && !vid_v_pipeline[READ_LATENCY-2])
|| (underflow_nxt)
|| (state == SYNCHED && interlaced_field_valid && interlaced_field[3] && (field_prediction != vid_f_nxt))
|| sync_lost) && !reset_counters && !mode_change) && !genlock_enable_sync1[0];
reset_counters <= sync_lost && (state_next == WAIT_FOR_SYNCH);
interlaced_field_valid <= interlaced_field_valid_nxt;
field_prediction <= field_prediction_nxt;
sop_reg <= sop;
end
end
generate
begin : generate_control_header
genvar i;
genvar symbol;
for(symbol = 0; symbol < 9; symbol = symbol + NUMBER_OF_COLOUR_PLANES_IN_PARALLEL) begin : header_extraction
for(i = 0; i < NUMBER_OF_COLOUR_PLANES_IN_PARALLEL; i = i + 1) begin : unpack_control_header
always @ (posedge rst_vid_clk or posedge vid_clk_int) begin
if(rst_vid_clk) begin
case(symbol + i)
0 : samples[15:12] <= 4'd0;
1 : samples[11:8] <= 4'd0;
2 : samples[7:4] <= 4'd0;
3 : samples[3:0] <= 4'd0;
4 : lines[15:12] <= 4'd0;
5 : lines[11:8] <= 4'd0;
6 : lines[7:4] <= 4'd0;
7 : lines[3:0] <= 4'd0;
8 : interlaced_field <= 4'd0;
endcase
end else begin
if(state == (WIDTH_3 + symbol/NUMBER_OF_COLOUR_PLANES_IN_PARALLEL)) begin
case(symbol + i)
0 : samples[15:12] <= q_data[BPS*i+3:BPS*i];
1 : samples[11:8] <= q_data[BPS*i+3:BPS*i];
2 : samples[7:4] <= q_data[BPS*i+3:BPS*i];
3 : samples[3:0] <= q_data[BPS*i+3:BPS*i];
4 : lines[15:12] <= q_data[BPS*i+3:BPS*i];
5 : lines[11:8] <= q_data[BPS*i+3:BPS*i];
6 : lines[7:4] <= q_data[BPS*i+3:BPS*i];
7 : lines[3:0] <= q_data[BPS*i+3:BPS*i];
8 : interlaced_field <= q_data[BPS*i+3:BPS*i];
endcase
end
end
end
end
end
end
endgenerate
assign find_mode_nxt = state_next == FIND_MODE;
assign wait_for_anc_nxt = state_next == WAIT_FOR_ANC;
alt_vipitc131_IS2Vid_statemachine #(
.USE_EMBEDDED_SYNCS(USE_EMBEDDED_SYNCS),
.NUMBER_OF_COLOUR_PLANES_IN_PARALLEL(NUMBER_OF_COLOUR_PLANES_IN_PARALLEL),
.IDLE(IDLE),
.FIND_SOP(FIND_SOP),
.WIDTH_3(WIDTH_3),
.WIDTH_2(WIDTH_2),
.WIDTH_1(WIDTH_1),
.WIDTH_0(WIDTH_0),
.HEIGHT_3(HEIGHT_3),
.HEIGHT_2(HEIGHT_2),
.HEIGHT_1(HEIGHT_1),
.HEIGHT_0(HEIGHT_0),
.INTERLACING(INTERLACING),
.FIND_MODE(FIND_MODE),
.SYNCHED(SYNCHED),
.WAIT_FOR_SYNCH(WAIT_FOR_SYNCH),
.WAIT_FOR_ANC(WAIT_FOR_ANC),
.INSERT_ANC(INSERT_ANC)
)
statemachine(
.rst(rst_vid_clk),
.clk(vid_clk_int),
.request_data_valid(request_data_valid),
.sop(sop),
.vid_v_nxt(vid_v_nxt),
.anc_datavalid_nxt(anc_datavalid_nxt),
.q_data(q_data[3:0]),
.sync_lost(sync_lost),
.anc_underflow_nxt(anc_underflow_nxt),
.ap_synched(ap_synched),
.enable_synced_nxt(enable_synced_nxt),
.state_next(state_next),
.state(state));
generate begin : sync_generation_generate
if(GENERATE_SYNC) begin
wire restart_count;
assign restart_count = restart_sample_count | restart_line_count;
alt_vipitc131_common_sync_generation sync_generation(
.rst(rst_vid_clk),
.clk(vid_clk_int),
.clear_enable(restart_count),
.enable_count(1'b1),
.hd_sdn(~serial_output),
.start_of_vsync(start_of_vsync),
.field_prediction(field_prediction),
.interlaced(interlaced),
.total_sample_count(h_total_minus_one[13:0]),
.total_sample_count_valid(1'b1),
.total_line_count(v_total_minus_one[13:0]),
.total_line_count_valid(1'b1),
.stable(enable_synced_nxt),
.divider_value(vcoclk_divider_value),
.sof_sample(sof_sample),
.sof_line(sof_line),
.sof_subsample(sof_subsample),
.output_enable(genlock_enable_sync1[0]),
.sof(vid_sof),
.sof_locked(vid_sof_locked),
.div(vid_vcoclk_div));
defparam sync_generation.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
sync_generation.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
sync_generation.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_COLOUR_PLANES_IN_SEQUENCE,
sync_generation.TOTALS_MINUS_ONE = 1;
assign sync_compare_h_reset[15:13] = 3'b000;
assign sync_compare_v_reset[15:13] = 3'b000;
wire sof_cvi_sync1;
wire sof_cvi_locked_sync1;
wire vid_sof_sync1;
alt_vipitc131_common_sync #(0) sof_cvi_sync(
.rst(rst_vid_clk),
.sync_clock(vid_clk_int),
.data_in(sof),
.data_out(sof_cvi_sync1));
alt_vipitc131_common_sync #(0) sof_cvi_locked_sync(
.rst(rst_vid_clk),
.sync_clock(vid_clk_int),
.data_in(sof_locked),
.data_out(sof_cvi_locked_sync1));
alt_vipitc131_common_sync #(0) sof_cvo_sync(
.rst(rst_vid_clk),
.sync_clock(vid_clk_int),
.data_in(vid_sof),
.data_out(vid_sof_sync1));
alt_vipitc131_IS2Vid_sync_compare sync_compare(
.rst(rst_vid_clk),
.clk(vid_clk_int),
.genlock_enable(genlock_enable_sync1),
.serial_output(serial_output),
.h_total_minus_one(h_total_minus_one[13:0]),
.restart_count(restart_count),
.divider_value(vcoclk_divider_value),
.sync_lines(sync_lines),
.sync_samples(sync_samples),
.remove_repeatn(remove_repeatn),
.sync_compare_h_reset(sync_compare_h_reset[12:0]),
.sync_compare_v_reset(sync_compare_v_reset[12:0]),
.genlocked(genlocked),
.sof_cvi(sof_cvi_sync1),
.sof_cvi_locked(sof_cvi_locked_sync1),
.sof_cvo(vid_sof_sync1),
.sof_cvo_locked(vid_sof_locked));
defparam
sync_compare.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
sync_compare.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
sync_compare.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_COLOUR_PLANES_IN_SEQUENCE;
end else begin
assign vid_sof = 1'b0;
assign vid_sof_locked = 1'b0;
assign vid_vcoclk_div = 1'b0;
assign remove_repeatn = 1'b0;
assign sync_compare_h_reset = v_offset_const[15:0];
assign sync_compare_v_reset = v_offset_const[15:0];
assign sync_samples = 1'b0;
assign sync_lines = 1'b0;
assign genlocked = 1'b0;
end
end endgenerate
endmodule | 5 |
6,577 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv | 116,866,011 | alt_vipitc131_IS2Vid.sv | sv | 1,203 | 182 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:388: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) enable_resync_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_sync\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_sync.v\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_sync.sv\n alt_vipitc131_common_sync\n alt_vipitc131_common_sync.v\n alt_vipitc131_common_sync.sv\n obj_dir/alt_vipitc131_common_sync\n obj_dir/alt_vipitc131_common_sync.v\n obj_dir/alt_vipitc131_common_sync.sv\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:394: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) underflow_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:400: Cannot find file containing module: \'alt_vipitc131_common_trigger_sync\'\nalt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) mode_change_trigger_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:410: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) genlocked_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:416: Cannot find file containing module: \'alt_vipitc131_IS2Vid_control\'\nalt_vipitc131_IS2Vid_control control(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:452: Cannot find file containing module: \'alt_vipitc131_common_trigger_sync\'\nalt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) av_write_trigger_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:462: Cannot find file containing module: \'alt_vipitc131_IS2Vid_mode_banks\'\nalt_vipitc131_IS2Vid_mode_banks mode_banks(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:545: Cannot find file containing module: \'alt_vipitc131_common_trigger_sync\'\nalt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) av_waitrequest_trigger_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:573: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign repeat_reset_point = !remove_repeatn && h_count == sync_compare_h_reset && v_count == sync_compare_v_reset;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:573: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign repeat_reset_point = !remove_repeatn && h_count == sync_compare_h_reset && v_count == sync_compare_v_reset;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:574: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign remove_reset_point = remove_repeatn && h_count == 16\'d0 && v_count == 16\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:574: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign remove_reset_point = remove_repeatn && h_count == 16\'d0 && v_count == 16\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:581: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'cp_ticks\' generates 1 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign lines_reset = (repeat_lines_reset || remove_lines_reset) && ((cp_ticks == NUMBER_OF_COLOUR_PLANES - 1) || ~serial_output);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:582: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'cp_ticks\' generates 1 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign samples_reset = (repeat_samples_reset || remove_samples_reset) && ((cp_ticks == NUMBER_OF_COLOUR_PLANES - 1) || ~serial_output);\n ^~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:591: Cannot find file containing module: \'alt_vipitc131_common_generic_count\'\nalt_vipitc131_common_generic_count\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:609: Cannot find file containing module: \'alt_vipitc131_common_generic_count\'\nalt_vipitc131_common_generic_count\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:621: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign start_of_frame = (start_of_cp && h_count == H_OFFSET) && ((interlaced && v_count == f1_v_end) || v_count == V_OFFSET);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:623: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign v_enable = enable_synced_nxt && enable_vcount && h_count == h_total_minus_one;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:624: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign ap = h_count >= h_blank && ~vid_v_nxt;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:627: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_h_nxt = enable_synced_nxt && h_count < h_blank;\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:628: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_h_sync_nxt = enable_synced_nxt && (h_count >= h_sync_start && h_count < h_sync_end);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:628: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_h_sync_nxt = enable_synced_nxt && (h_count >= h_sync_start && h_count < h_sync_end);\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:629: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_v_nxt = enable_synced_nxt && (v_count >= f2_v_start ||\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:630: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && (v_count >= f1_v_start && v_count < f1_v_end)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:630: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && (v_count >= f1_v_start && v_count < f1_v_end)));\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:631: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_v_sync_nxt = enable_synced_nxt && ((v_count >= f2_v_sync_start && v_count < f2_v_sync_end) ||\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:631: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_v_sync_nxt = enable_synced_nxt && ((v_count >= f2_v_sync_start && v_count < f2_v_sync_end) ||\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:632: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && (v_count >= f1_v_sync_start && v_count < f1_v_sync_end)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:632: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && (v_count >= f1_v_sync_start && v_count < f1_v_sync_end)));\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:634: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign anc_datavalid_nxt = enable_synced_nxt && h_count >= h_blank && (v_count >= f2_anc_v_start || \n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:634: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign anc_datavalid_nxt = enable_synced_nxt && h_count >= h_blank && (v_count >= f2_anc_v_start || \n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:635: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && v_count >= f1_anc_v_start && v_count < f1_v_end));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:635: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && v_count >= f1_anc_v_start && v_count < f1_v_end));\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:636: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_f_nxt = interlaced && (v_count >= f_rising_edge && v_count < f_falling_edge);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:636: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_f_nxt = interlaced && (v_count >= f_rising_edge && v_count < f_falling_edge);\n ^\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:652: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) clear_underflow_sticky_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:712: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) enable_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:718: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME, 2) genlock_enable_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:731: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'cp_ticks\' generates 1 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (cp_ticks == 2) ? BLANKING_SER1 :\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:784: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'cp_ticks\' generates 1 bits.\n : ... In instance alt_vipitc131_IS2Vid\n assign sav_enable = (serial_output) ? cp_ticks == TRS_CP_OFFSET : 1\'b1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:787: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (sav_enable && h_count == sav));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:800: Operator LTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n vid_ln_reg <= (v_count <= ap_line_end) ? v_count_plus_ap[10:0] : v_count_minus_ap[10:0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:838: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n assign v_count_plus_ap = v_count + ap_line;\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:839: Operator SUB expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n assign v_count_minus_ap = v_count - ap_line_end;\n ^\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:934: Cannot find file containing module: \'alt_vipitc131_common_fifo\'\nalt_vipitc131_common_fifo input_fifo(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1059: Cannot find file containing module: \'alt_vipitc131_IS2Vid_statemachine\'\nalt_vipitc131_IS2Vid_statemachine #(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1100: Cannot find file containing module: \'alt_vipitc131_common_sync_generation\'\n alt_vipitc131_common_sync_generation sync_generation(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1138: Cannot find file containing module: \'alt_vipitc131_common_sync\'\n alt_vipitc131_common_sync #(0) sof_cvi_sync(\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1144: Cannot find file containing module: \'alt_vipitc131_common_sync\'\n alt_vipitc131_common_sync #(0) sof_cvi_locked_sync(\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1151: Cannot find file containing module: \'alt_vipitc131_common_sync\'\n alt_vipitc131_common_sync #(0) sof_cvo_sync(\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1157: Cannot find file containing module: \'alt_vipitc131_IS2Vid_sync_compare\'\n alt_vipitc131_IS2Vid_sync_compare sync_compare(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 20 error(s), 31 warning(s)\n' | 7,601 | function | function integer alt_clogb2;
input [31:0] value;
integer i;
begin
alt_clogb2 = 32;
for (i=31; i>0; i=i-1) begin
if (2**i>=value)
alt_clogb2 = i;
end
end
endfunction | function integer alt_clogb2; |
input [31:0] value;
integer i;
begin
alt_clogb2 = 32;
for (i=31; i>0; i=i-1) begin
if (2**i>=value)
alt_clogb2 = i;
end
end
endfunction | 5 |
6,578 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv | 116,866,011 | alt_vipitc131_IS2Vid.sv | sv | 1,203 | 182 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:388: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) enable_resync_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_sync\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_sync.v\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_sync.sv\n alt_vipitc131_common_sync\n alt_vipitc131_common_sync.v\n alt_vipitc131_common_sync.sv\n obj_dir/alt_vipitc131_common_sync\n obj_dir/alt_vipitc131_common_sync.v\n obj_dir/alt_vipitc131_common_sync.sv\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:394: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) underflow_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:400: Cannot find file containing module: \'alt_vipitc131_common_trigger_sync\'\nalt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) mode_change_trigger_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:410: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) genlocked_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:416: Cannot find file containing module: \'alt_vipitc131_IS2Vid_control\'\nalt_vipitc131_IS2Vid_control control(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:452: Cannot find file containing module: \'alt_vipitc131_common_trigger_sync\'\nalt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) av_write_trigger_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:462: Cannot find file containing module: \'alt_vipitc131_IS2Vid_mode_banks\'\nalt_vipitc131_IS2Vid_mode_banks mode_banks(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:545: Cannot find file containing module: \'alt_vipitc131_common_trigger_sync\'\nalt_vipitc131_common_trigger_sync #(CLOCKS_ARE_SAME) av_waitrequest_trigger_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:573: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign repeat_reset_point = !remove_repeatn && h_count == sync_compare_h_reset && v_count == sync_compare_v_reset;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:573: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign repeat_reset_point = !remove_repeatn && h_count == sync_compare_h_reset && v_count == sync_compare_v_reset;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:574: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign remove_reset_point = remove_repeatn && h_count == 16\'d0 && v_count == 16\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:574: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign remove_reset_point = remove_repeatn && h_count == 16\'d0 && v_count == 16\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:581: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'cp_ticks\' generates 1 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign lines_reset = (repeat_lines_reset || remove_lines_reset) && ((cp_ticks == NUMBER_OF_COLOUR_PLANES - 1) || ~serial_output);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:582: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'cp_ticks\' generates 1 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign samples_reset = (repeat_samples_reset || remove_samples_reset) && ((cp_ticks == NUMBER_OF_COLOUR_PLANES - 1) || ~serial_output);\n ^~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:591: Cannot find file containing module: \'alt_vipitc131_common_generic_count\'\nalt_vipitc131_common_generic_count\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:609: Cannot find file containing module: \'alt_vipitc131_common_generic_count\'\nalt_vipitc131_common_generic_count\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:621: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign start_of_frame = (start_of_cp && h_count == H_OFFSET) && ((interlaced && v_count == f1_v_end) || v_count == V_OFFSET);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:623: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign v_enable = enable_synced_nxt && enable_vcount && h_count == h_total_minus_one;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:624: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign ap = h_count >= h_blank && ~vid_v_nxt;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:627: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_h_nxt = enable_synced_nxt && h_count < h_blank;\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:628: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_h_sync_nxt = enable_synced_nxt && (h_count >= h_sync_start && h_count < h_sync_end);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:628: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_h_sync_nxt = enable_synced_nxt && (h_count >= h_sync_start && h_count < h_sync_end);\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:629: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_v_nxt = enable_synced_nxt && (v_count >= f2_v_start ||\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:630: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && (v_count >= f1_v_start && v_count < f1_v_end)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:630: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && (v_count >= f1_v_start && v_count < f1_v_end)));\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:631: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_v_sync_nxt = enable_synced_nxt && ((v_count >= f2_v_sync_start && v_count < f2_v_sync_end) ||\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:631: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_v_sync_nxt = enable_synced_nxt && ((v_count >= f2_v_sync_start && v_count < f2_v_sync_end) ||\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:632: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && (v_count >= f1_v_sync_start && v_count < f1_v_sync_end)));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:632: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && (v_count >= f1_v_sync_start && v_count < f1_v_sync_end)));\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:634: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign anc_datavalid_nxt = enable_synced_nxt && h_count >= h_blank && (v_count >= f2_anc_v_start || \n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:634: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign anc_datavalid_nxt = enable_synced_nxt && h_count >= h_blank && (v_count >= f2_anc_v_start || \n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:635: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && v_count >= f1_anc_v_start && v_count < f1_v_end));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:635: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (interlaced && v_count >= f1_anc_v_start && v_count < f1_v_end));\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:636: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_f_nxt = interlaced && (v_count >= f_rising_edge && v_count < f_falling_edge);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:636: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\nassign vid_f_nxt = interlaced && (v_count >= f_rising_edge && v_count < f_falling_edge);\n ^\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:652: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) clear_underflow_sticky_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:712: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME) enable_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:718: Cannot find file containing module: \'alt_vipitc131_common_sync\'\nalt_vipitc131_common_sync #(CLOCKS_ARE_SAME, 2) genlock_enable_sync(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:731: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'cp_ticks\' generates 1 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (cp_ticks == 2) ? BLANKING_SER1 :\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:784: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'cp_ticks\' generates 1 bits.\n : ... In instance alt_vipitc131_IS2Vid\n assign sav_enable = (serial_output) ? cp_ticks == TRS_CP_OFFSET : 1\'b1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:787: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'h_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n (sav_enable && h_count == sav));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:800: Operator LTE expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n vid_ln_reg <= (v_count <= ap_line_end) ? v_count_plus_ap[10:0] : v_count_minus_ap[10:0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:838: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n assign v_count_plus_ap = v_count + ap_line;\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:839: Operator SUB expects 16 bits on the LHS, but LHS\'s VARREF \'v_count\' generates 12 bits.\n : ... In instance alt_vipitc131_IS2Vid\n assign v_count_minus_ap = v_count - ap_line_end;\n ^\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:934: Cannot find file containing module: \'alt_vipitc131_common_fifo\'\nalt_vipitc131_common_fifo input_fifo(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1059: Cannot find file containing module: \'alt_vipitc131_IS2Vid_statemachine\'\nalt_vipitc131_IS2Vid_statemachine #(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1100: Cannot find file containing module: \'alt_vipitc131_common_sync_generation\'\n alt_vipitc131_common_sync_generation sync_generation(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1138: Cannot find file containing module: \'alt_vipitc131_common_sync\'\n alt_vipitc131_common_sync #(0) sof_cvi_sync(\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1144: Cannot find file containing module: \'alt_vipitc131_common_sync\'\n alt_vipitc131_common_sync #(0) sof_cvi_locked_sync(\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1151: Cannot find file containing module: \'alt_vipitc131_common_sync\'\n alt_vipitc131_common_sync #(0) sof_cvo_sync(\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid.sv:1157: Cannot find file containing module: \'alt_vipitc131_IS2Vid_sync_compare\'\n alt_vipitc131_IS2Vid_sync_compare sync_compare(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 20 error(s), 31 warning(s)\n' | 7,601 | function | function [9:0] calc_xyz;
input [2:0] FVH;
case (FVH)
3'b000 : calc_xyz = 10'h200;
3'b001 : calc_xyz = 10'h274;
3'b010 : calc_xyz = 10'h2ac;
3'b011 : calc_xyz = 10'h2d8;
3'b100 : calc_xyz = 10'h31c;
3'b101 : calc_xyz = 10'h368;
3'b110 : calc_xyz = 10'h3b0;
3'b111 : calc_xyz = 10'h3c4;
endcase
endfunction | function [9:0] calc_xyz; |
input [2:0] FVH;
case (FVH)
3'b000 : calc_xyz = 10'h200;
3'b001 : calc_xyz = 10'h274;
3'b010 : calc_xyz = 10'h2ac;
3'b011 : calc_xyz = 10'h2d8;
3'b100 : calc_xyz = 10'h31c;
3'b101 : calc_xyz = 10'h368;
3'b110 : calc_xyz = 10'h3b0;
3'b111 : calc_xyz = 10'h3c4;
endcase
endfunction | 5 |
6,579 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_mode_banks.sv | 116,866,011 | alt_vipitc131_IS2Vid_mode_banks.sv | sv | 609 | 197 | [] | [] | [] | null | line:87: before: "integer" | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_mode_banks.sv:42: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [NO_OF_MODES_INT-1:0] mode_match_safe,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_mode_banks.sv:117: Cannot find file containing module: \'alt_vipitc131_IS2Vid_calculate_mode\'\nalt_vipitc131_IS2Vid_calculate_mode u_calculate_mode(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_IS2Vid_calculate_mode\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_IS2Vid_calculate_mode.v\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_IS2Vid_calculate_mode.sv\n alt_vipitc131_IS2Vid_calculate_mode\n alt_vipitc131_IS2Vid_calculate_mode.v\n alt_vipitc131_IS2Vid_calculate_mode.sv\n obj_dir/alt_vipitc131_IS2Vid_calculate_mode\n obj_dir/alt_vipitc131_IS2Vid_calculate_mode.v\n obj_dir/alt_vipitc131_IS2Vid_calculate_mode.sv\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_mode_banks.sv:603: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n : ... In instance alt_vipitc131_IS2Vid_mode_banks\n assign mode_match_safe = {NO_OF_MODES_INT{1\'b0}};\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_mode_banks.sv:603: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1 bits.\n : ... In instance alt_vipitc131_IS2Vid_mode_banks\n assign mode_match_safe = {NO_OF_MODES_INT{1\'b0}};\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 7,604 | module | module alt_vipitc131_IS2Vid_mode_banks
#(parameter
USE_CONTROL = 0,
NO_OF_MODES_INT = 0,
LOG2_NO_OF_MODES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
TRS = 0,
INTERLACED = 0,
H_ACTIVE_PIXELS = 0,
F0_LINE_COUNT = 0,
F1_LINE_COUNT = 0,
H_FRONT_PORCH = 0,
H_SYNC_LENGTH = 0,
H_BLANK_INT = 0,
V_FRONT_PORCH = 0,
V_SYNC_LENGTH = 0,
V_BLANK_INT = 0,
FIELD0_V_FRONT_PORCH = 0,
FIELD0_V_SYNC_LENGTH = 0,
FIELD0_V_BLANK_INT = 0,
AP_LINE = 0,
FIELD0_V_RISING_EDGE = 0,
F_RISING_EDGE = 0,
F_FALLING_EDGE = 0,
CONVERT_SEQ_TO_PAR = 0,
TRS_SEQUENCE = 0,
TRS_PARALLEL = 0,
STD_WIDTH = 1,
ANC_LINE = 0,
FIELD0_ANC_LINE = 0)
(
input wire rst,
input wire clk,
input wire mode_write,
input wire find_mode_nxt,
input wire [7:0] av_address,
input wire [15:0] av_writedata,
output wire [NO_OF_MODES_INT-1:0] mode_match_safe,
output wire dirty_modes,
output wire mode_change,
output wire [STD_WIDTH-1:0] vid_std,
output wire vid_mode_change,
input wire [3:0] interlaced_field,
input wire field_prediction,
input wire [15:0] samples,
input wire [15:0] lines,
output wire interlaced,
output wire serial_output,
output wire [15:0] h_total_minus_one,
output wire [15:0] v_total_minus_one,
output wire [15:0] ap_line,
output wire [15:0] ap_line_end,
output wire [15:0] h_blank,
output wire [15:0] sav,
output wire [15:0] h_sync_start,
output wire [15:0] h_sync_end,
output wire [15:0] f2_v_start,
output wire [15:0] f1_v_start,
output wire [15:0] f1_v_end,
output wire [15:0] f2_v_sync_start,
output wire [15:0] f2_v_sync_end,
output wire [15:0] f1_v_sync_start,
output wire [15:0] f1_v_sync_end,
output wire [15:0] f_rising_edge,
output wire [15:0] f_falling_edge,
output wire [15:0] f1_v_end_nxt,
output wire [13:0] sof_sample,
output wire [12:0] sof_line,
output wire [1:0] sof_subsample,
output wire [13:0] vcoclk_divider_value,
output wire [15:0] f2_anc_v_start,
output wire [15:0] f1_anc_v_start);
localparam REGISTERS_PER_MODE = 23;
function integer get_register_address;
input integer mode;
input integer register_no;
begin
get_register_address = (mode*(REGISTERS_PER_MODE+1))+5+register_no;
end
endfunction
wire interlaced_rst;
wire serial_output_rst;
wire [15:0] h_total_minus_one_rst;
wire [15:0] v_total_minus_one_rst;
wire [15:0] ap_line_rst;
wire [15:0] ap_line_end_rst;
wire [15:0] h_blank_rst;
wire [15:0] sav_rst;
wire [15:0] h_sync_start_rst;
wire [15:0] h_sync_end_rst;
wire [15:0] f2_v_start_rst;
wire [15:0] f1_v_start_rst;
wire [15:0] f1_v_end_rst;
wire [15:0] f2_v_sync_start_rst;
wire [15:0] f2_v_sync_end_rst;
wire [15:0] f1_v_sync_start_rst;
wire [15:0] f1_v_sync_end_rst;
wire [15:0] f_rising_edge_rst;
wire [15:0] f_falling_edge_rst;
wire [15:0] f2_anc_v_start_rst;
wire [15:0] f1_anc_v_start_rst;
alt_vipitc131_IS2Vid_calculate_mode u_calculate_mode(
.trs(TRS),
.is_interlaced(INTERLACED),
.is_serial_output(!COLOUR_PLANES_ARE_IN_PARALLEL),
.is_sample_count_f0(H_ACTIVE_PIXELS),
.is_line_count_f0(F0_LINE_COUNT),
.is_sample_count_f1(H_ACTIVE_PIXELS),
.is_line_count_f1(F1_LINE_COUNT),
.is_h_front_porch(H_FRONT_PORCH),
.is_h_sync_length(H_SYNC_LENGTH),
.is_h_blank(H_BLANK_INT),
.is_v_front_porch(V_FRONT_PORCH),
.is_v_sync_length(V_SYNC_LENGTH),
.is_v_blank(V_BLANK_INT),
.is_v1_front_porch(FIELD0_V_FRONT_PORCH),
.is_v1_sync_length(FIELD0_V_SYNC_LENGTH),
.is_v1_blank(FIELD0_V_BLANK_INT),
.is_ap_line(AP_LINE),
.is_v1_rising_edge(FIELD0_V_RISING_EDGE),
.is_f_rising_edge(F_RISING_EDGE),
.is_f_falling_edge(F_FALLING_EDGE),
.is_anc_line(ANC_LINE),
.is_v1_anc_line(FIELD0_ANC_LINE),
.interlaced_nxt(interlaced_rst),
.serial_output_nxt(serial_output_rst),
.h_total_minus_one_nxt(h_total_minus_one_rst),
.v_total_minus_one_nxt(v_total_minus_one_rst),
.ap_line_nxt(ap_line_rst),
.ap_line_end_nxt(ap_line_end_rst),
.h_blank_nxt(h_blank_rst),
.sav_nxt(sav_rst),
.h_sync_start_nxt(h_sync_start_rst),
.h_sync_end_nxt(h_sync_end_rst),
.f2_v_start_nxt(f2_v_start_rst),
.f1_v_start_nxt(f1_v_start_rst),
.f1_v_end_nxt(f1_v_end_rst),
.f2_v_sync_start_nxt(f2_v_sync_start_rst),
.f2_v_sync_end_nxt(f2_v_sync_end_rst),
.f1_v_sync_start_nxt(f1_v_sync_start_rst),
.f1_v_sync_end_nxt(f1_v_sync_end_rst),
.f_rising_edge_nxt(f_rising_edge_rst),
.f_falling_edge_nxt(f_falling_edge_rst),
.f2_anc_v_start_nxt(f2_anc_v_start_rst),
.f1_anc_v_start_nxt(f1_anc_v_start_rst));
generate
if(USE_CONTROL) begin
reg is_valid_mode[NO_OF_MODES_INT-1:0];
reg is_interlaced[NO_OF_MODES_INT-1:0];
reg is_serial_output[NO_OF_MODES_INT-1:0];
reg [15:0] is_sample_count[NO_OF_MODES_INT-1:0];
reg [15:0] is_line_count_f0[NO_OF_MODES_INT-1:0];
reg [15:0] is_line_count_f1[NO_OF_MODES_INT-1:0];
reg [15:0] is_h_front_porch[NO_OF_MODES_INT-1:0];
reg [15:0] is_h_sync_length[NO_OF_MODES_INT-1:0];
reg [15:0] is_h_blank[NO_OF_MODES_INT-1:0];
reg [15:0] is_v_front_porch[NO_OF_MODES_INT-1:0];
reg [15:0] is_v_sync_length[NO_OF_MODES_INT-1:0];
reg [15:0] is_v_blank[NO_OF_MODES_INT-1:0];
reg [15:0] is_v1_front_porch[NO_OF_MODES_INT-1:0];
reg [15:0] is_v1_sync_length[NO_OF_MODES_INT-1:0];
reg [15:0] is_v1_blank[NO_OF_MODES_INT-1:0];
reg [15:0] is_ap_line[NO_OF_MODES_INT-1:0];
reg [15:0] is_v1_rising_edge[NO_OF_MODES_INT-1:0];
reg [15:0] is_f_rising_edge[NO_OF_MODES_INT-1:0];
reg [15:0] is_f_falling_edge[NO_OF_MODES_INT-1:0];
reg [STD_WIDTH-1:0] is_standard[NO_OF_MODES_INT-1:0];
reg [13:0] is_sof_sample[NO_OF_MODES_INT-1:0];
reg [1:0] is_sof_subsample[NO_OF_MODES_INT-1:0];
reg [12:0] is_sof_line[NO_OF_MODES_INT-1:0];
reg [13:0] is_vcoclk_divider_value[NO_OF_MODES_INT-1:0];
reg [15:0] is_anc_line[NO_OF_MODES_INT-1:0];
reg [15:0] is_v1_anc_line[NO_OF_MODES_INT-1:0];
reg [NO_OF_MODES_INT-1:0] dirty_mode;
reg [NO_OF_MODES_INT-1:0] mode_match;
reg [NO_OF_MODES_INT-1:0] mode_match_reg;
reg find_mode;
reg dirty_modes_reg;
always @ (posedge rst or posedge clk) begin
if(rst) begin
find_mode <= 1'b0;
dirty_modes_reg <= 1'b0;
end else begin
find_mode <= find_mode_nxt;
dirty_modes_reg <= |dirty_mode;
end
end
genvar i;
for(i = 0; i < NO_OF_MODES_INT; i = i + 1) begin : is_registers
always @ (posedge rst or posedge clk) begin
if(rst) begin
is_valid_mode[i] <= 1'b0;
is_interlaced[i] <= 1'b0;
is_serial_output[i] <= 1'b0;
is_sample_count[i] <= 16'd0;
is_line_count_f0[i] <= 16'd0;
is_line_count_f1[i] <= 16'd0;
is_h_front_porch[i] <= 16'd0;
is_h_sync_length[i] <= 16'd0;
is_h_blank[i] <= 16'd0;
is_v_front_porch[i] <= 16'd0;
is_v_sync_length[i] <= 16'd0;
is_v_blank[i] <= 16'd0;
is_v1_front_porch[i] <= 16'd0;
is_v1_sync_length[i] <= 16'd0;
is_v1_blank[i] <= 16'd0;
is_ap_line[i] <= 16'd0;
is_v1_rising_edge[i] <= 16'd0;
is_f_rising_edge[i] <= 16'd0;
is_f_falling_edge[i] <= 16'd0;
is_standard[i] <= {STD_WIDTH{1'b0}};
is_sof_sample[i] <= 14'd0;
is_sof_subsample[i] <= 2'd0;
is_sof_line[i] <= 13'd0;
is_vcoclk_divider_value[i] <= 14'd0;
is_anc_line[i] <= 16'd0;
is_v1_anc_line[i] <= 16'd0;
dirty_mode[i] <= 1'b0;
mode_match[i] <= 1'b0;
end else begin
if(mode_write) begin
if(~is_valid_mode[i]) begin
if(av_address == get_register_address(i, 0)) begin
is_interlaced[i] <= av_writedata[0];
if(CONVERT_SEQ_TO_PAR)
is_serial_output[i] <= av_writedata[1];
else
is_serial_output[i] <= serial_output_rst;
end
is_sample_count[i] <= (av_address == get_register_address(i, 1)) ? av_writedata : is_sample_count[i];
is_line_count_f0[i] <= (av_address == get_register_address(i, 2)) ? av_writedata : is_line_count_f0[i];
is_line_count_f1[i] <= (av_address == get_register_address(i, 3)) ? av_writedata : is_line_count_f1[i];
is_h_front_porch[i] <= (av_address == get_register_address(i, 4)) ? av_writedata : is_h_front_porch[i];
is_h_sync_length[i] <= (av_address == get_register_address(i, 5)) ? av_writedata : is_h_sync_length[i];
is_h_blank[i] <= (av_address == get_register_address(i, 6)) ? av_writedata : is_h_blank[i];
is_v_front_porch[i] <= (av_address == get_register_address(i, 7)) ? av_writedata : is_v_front_porch[i];
is_v_sync_length[i] <= (av_address == get_register_address(i, 8)) ? av_writedata : is_v_sync_length[i];
is_v_blank[i] <= (av_address == get_register_address(i, 9)) ? av_writedata : is_v_blank[i];
is_v1_front_porch[i] <= (av_address == get_register_address(i, 10)) ? av_writedata : is_v1_front_porch[i];
is_v1_sync_length[i] <= (av_address == get_register_address(i, 11)) ? av_writedata : is_v1_sync_length[i];
is_v1_blank[i] <= (av_address == get_register_address(i, 12)) ? av_writedata : is_v1_blank[i];
is_ap_line[i] <= (av_address == get_register_address(i, 13)) ? av_writedata : is_ap_line[i];
is_v1_rising_edge[i] <= (av_address == get_register_address(i, 14)) ? av_writedata : is_v1_rising_edge[i];
is_f_rising_edge[i] <= (av_address == get_register_address(i, 15)) ? av_writedata : is_f_rising_edge[i];
is_f_falling_edge[i] <= (av_address == get_register_address(i, 16)) ? av_writedata : is_f_falling_edge[i];
is_standard[i] <= (av_address == get_register_address(i, 17)) ? av_writedata[STD_WIDTH-1:0] : is_standard[i];
if(av_address == get_register_address(i, 18)) begin
is_sof_sample[i] <= av_writedata[15:2];
is_sof_subsample[i] <= av_writedata[1:0];
end
is_sof_line[i] <= (av_address == get_register_address(i, 19)) ? av_writedata[12:0] : is_sof_line[i];
is_vcoclk_divider_value[i] <= (av_address == get_register_address(i, 20)) ? av_writedata[13:0] : is_vcoclk_divider_value[i];
is_anc_line[i] <= (av_address == get_register_address(i, 21)) ? av_writedata[15:0] : is_anc_line[i];
is_v1_anc_line[i] <= (av_address == get_register_address(i, 22)) ? av_writedata[15:0] : is_v1_anc_line[i];
end
is_valid_mode[i] <= (av_address == get_register_address(i, 23)) ? av_writedata[0] : is_valid_mode[i];
end
dirty_mode[i] <= (mode_write && av_address == get_register_address(i, 23) && av_writedata[0]) || (dirty_mode[i] && ~mode_change);
mode_match[i] <= ({interlaced_field[3], field_prediction} == 2'b11) ? is_valid_mode[i] & is_interlaced[i] & samples == is_sample_count[i] & lines == is_line_count_f1[i] :
({interlaced_field[3], field_prediction} == 2'b10) ? is_valid_mode[i] & is_interlaced[i] & samples == is_sample_count[i] & lines == is_line_count_f0[i] :
is_valid_mode[i] & samples == is_sample_count[i] & lines == is_line_count_f0[i];
end
end
end
assign dirty_modes = dirty_modes_reg;
wire interlaced_nxt;
wire serial_output_nxt;
wire [15:0] h_total_minus_one_nxt;
wire [15:0] v_total_minus_one_nxt;
wire [15:0] ap_line_nxt;
wire [15:0] ap_line_end_nxt;
wire [15:0] h_blank_nxt;
wire [15:0] sav_nxt;
wire [15:0] h_sync_start_nxt;
wire [15:0] h_sync_end_nxt;
wire [15:0] f2_v_start_nxt;
wire [15:0] f1_v_start_nxt;
wire [15:0] f2_v_sync_start_nxt;
wire [15:0] f2_v_sync_end_nxt;
wire [15:0] f1_v_sync_start_nxt;
wire [15:0] f1_v_sync_end_nxt;
wire [15:0] f_rising_edge_nxt;
wire [15:0] f_falling_edge_nxt;
wire [15:0] f2_anc_v_start_nxt;
wire [15:0] f1_anc_v_start_nxt;
reg interlaced_reg;
reg serial_output_reg;
reg [15:0] h_total_minus_one_reg;
reg [15:0] v_total_minus_one_reg;
reg [15:0] ap_line_reg;
reg [15:0] ap_line_end_reg;
reg [15:0] h_blank_reg;
reg [15:0] sav_reg;
reg [15:0] h_sync_start_reg;
reg [15:0] h_sync_end_reg;
reg [15:0] f2_v_start_reg;
reg [15:0] f1_v_start_reg;
reg [15:0] f1_v_end_reg;
reg [15:0] f2_v_sync_start_reg;
reg [15:0] f2_v_sync_end_reg;
reg [15:0] f1_v_sync_start_reg;
reg [15:0] f1_v_sync_end_reg;
reg [15:0] f_rising_edge_reg;
reg [15:0] f_falling_edge_reg;
reg [STD_WIDTH-1:0] standard_reg;
reg [13:0] sof_sample_reg;
reg [1:0] sof_subsample_reg;
reg [12:0] sof_line_reg;
reg [13:0] vcoclk_divider_value_reg;
reg [15:0] f2_anc_v_start_reg;
reg [15:0] f1_anc_v_start_reg;
wire [LOG2_NO_OF_MODES-1:0] mode;
reg mode_change_reg;
if(NO_OF_MODES_INT > 1) begin
assign mode_match_safe[0] = mode_match[0];
for(i = 1; i < NO_OF_MODES_INT; i = i + 1) begin : is_registers
assign mode_match_safe[i] = mode_match[i] & ~|mode_match[i-1:0];
end
alt_vipitc131_common_to_binary u_to_binary(
.one_hot(mode_match_safe[NO_OF_MODES_INT-1:1]),
.binary(mode)
);
defparam u_to_binary.NO_OF_MODES = NO_OF_MODES_INT - 1,
u_to_binary.LOG2_NO_OF_MODES = LOG2_NO_OF_MODES;
end else begin
assign mode = 1'b0;
assign mode_match_safe = mode_match;
end
assign mode_change = find_mode & |mode_match_safe & (|(mode_match_safe ^ mode_match_reg) | dirty_mode[mode]);
assign vid_std = standard_reg;
assign vid_mode_change = mode_change_reg;
wire [3:0] trs_mux;
assign trs_mux = (is_serial_output[mode]) ? TRS_SEQUENCE : TRS_PARALLEL;
alt_vipitc131_IS2Vid_calculate_mode u_calculate_mode_dynamic(
.trs(trs_mux),
.is_interlaced(is_interlaced[mode]),
.is_serial_output(is_serial_output[mode]),
.is_sample_count_f0(is_sample_count[mode]),
.is_line_count_f0(is_line_count_f0[mode]),
.is_sample_count_f1(is_sample_count[mode]),
.is_line_count_f1(is_line_count_f1[mode]),
.is_h_front_porch(is_h_front_porch[mode]),
.is_h_sync_length(is_h_sync_length[mode]),
.is_h_blank(is_h_blank[mode]),
.is_v_front_porch(is_v_front_porch[mode]),
.is_v_sync_length(is_v_sync_length[mode]),
.is_v_blank(is_v_blank[mode]),
.is_v1_front_porch(is_v1_front_porch[mode]),
.is_v1_sync_length(is_v1_sync_length[mode]),
.is_v1_blank(is_v1_blank[mode]),
.is_ap_line(is_ap_line[mode]),
.is_v1_rising_edge(is_v1_rising_edge[mode]),
.is_f_rising_edge(is_f_rising_edge[mode]),
.is_f_falling_edge(is_f_falling_edge[mode]),
.is_anc_line(is_anc_line[mode]),
.is_v1_anc_line(is_v1_anc_line[mode]),
.interlaced_nxt(interlaced_nxt),
.serial_output_nxt(serial_output_nxt),
.h_total_minus_one_nxt(h_total_minus_one_nxt),
.v_total_minus_one_nxt(v_total_minus_one_nxt),
.ap_line_nxt(ap_line_nxt),
.ap_line_end_nxt(ap_line_end_nxt),
.h_blank_nxt(h_blank_nxt),
.sav_nxt(sav_nxt),
.h_sync_start_nxt(h_sync_start_nxt),
.h_sync_end_nxt(h_sync_end_nxt),
.f2_v_start_nxt(f2_v_start_nxt),
.f1_v_start_nxt(f1_v_start_nxt),
.f1_v_end_nxt(f1_v_end_nxt),
.f2_v_sync_start_nxt(f2_v_sync_start_nxt),
.f2_v_sync_end_nxt(f2_v_sync_end_nxt),
.f1_v_sync_start_nxt(f1_v_sync_start_nxt),
.f1_v_sync_end_nxt(f1_v_sync_end_nxt),
.f_rising_edge_nxt(f_rising_edge_nxt),
.f_falling_edge_nxt(f_falling_edge_nxt),
.f2_anc_v_start_nxt(f2_anc_v_start_nxt),
.f1_anc_v_start_nxt(f1_anc_v_start_nxt));
always @ (posedge rst or posedge clk) begin
if(rst) begin
mode_change_reg <= 1'b0;
mode_match_reg <= {NO_OF_MODES_INT{1'b0}};
interlaced_reg <= interlaced_rst;
serial_output_reg <= serial_output_rst;
h_total_minus_one_reg <= h_total_minus_one_rst;
v_total_minus_one_reg <= v_total_minus_one_rst;
ap_line_reg <= ap_line_rst;
ap_line_end_reg <= ap_line_end_rst;
h_blank_reg <= h_blank_rst;
sav_reg <= sav_rst;
h_sync_start_reg <= h_sync_start_rst;
h_sync_end_reg <= h_sync_end_rst;
f2_v_start_reg <= f2_v_start_rst;
f1_v_start_reg <= f1_v_start_rst;
f1_v_end_reg <= f1_v_end_rst;
f2_v_sync_start_reg <= f2_v_sync_start_rst;
f2_v_sync_end_reg <= f2_v_sync_end_rst;
f1_v_sync_start_reg <= f1_v_sync_start_rst;
f1_v_sync_end_reg <= f1_v_sync_end_rst;
f_rising_edge_reg <= f_rising_edge_rst;
f_falling_edge_reg <= f_falling_edge_rst;
standard_reg <= {STD_WIDTH{1'b0}};
sof_sample_reg <= 14'd0;
sof_subsample_reg <= 2'd0;
sof_line_reg <= 13'd0;
vcoclk_divider_value_reg <= 14'd0;
f2_anc_v_start_reg <= f2_anc_v_start_rst;
f1_anc_v_start_reg <= f1_anc_v_start_rst;
end else begin
mode_change_reg <= mode_change;
mode_match_reg <= (mode_change) ? mode_match_safe : mode_match_reg;
if(mode_change) begin
interlaced_reg <= interlaced_nxt;
serial_output_reg = serial_output_nxt;
h_total_minus_one_reg <= h_total_minus_one_nxt;
v_total_minus_one_reg <= v_total_minus_one_nxt;
ap_line_reg <= ap_line_nxt;
ap_line_end_reg <= ap_line_end_nxt;
h_blank_reg <= h_blank_nxt;
sav_reg <= sav_nxt;
h_sync_start_reg <= h_sync_start_nxt;
h_sync_end_reg <= h_sync_end_nxt;
f2_v_start_reg <= f2_v_start_nxt;
f1_v_start_reg <= f1_v_start_nxt;
f1_v_end_reg <= f1_v_end_nxt;
f2_v_sync_start_reg <= f2_v_sync_start_nxt;
f2_v_sync_end_reg <= f2_v_sync_end_nxt;
f1_v_sync_start_reg <= f1_v_sync_start_nxt;
f1_v_sync_end_reg <= f1_v_sync_end_nxt;
f_rising_edge_reg <= f_rising_edge_nxt;
f_falling_edge_reg <= f_falling_edge_nxt;
standard_reg <= is_standard[mode];
sof_sample_reg <= is_sof_sample[mode];
sof_subsample_reg <= is_sof_subsample[mode];
sof_line_reg <= is_sof_line[mode];
vcoclk_divider_value_reg <= is_vcoclk_divider_value[mode];
f2_anc_v_start_reg <= f2_anc_v_start_nxt;
f1_anc_v_start_reg <= f1_anc_v_start_nxt;
end
end
end
assign interlaced = interlaced_reg;
assign serial_output = serial_output_reg;
assign h_total_minus_one = h_total_minus_one_reg;
assign v_total_minus_one = v_total_minus_one_reg;
assign ap_line = ap_line_reg;
assign ap_line_end = ap_line_end_reg;
assign h_blank = h_blank_reg;
assign sav = sav_reg;
assign h_sync_start = h_sync_start_reg;
assign h_sync_end = h_sync_end_reg;
assign f2_v_start = f2_v_start_reg;
assign f1_v_start = f1_v_start_reg;
assign f1_v_end = f1_v_end_reg;
assign f2_v_sync_start = f2_v_sync_start_reg;
assign f2_v_sync_end = f2_v_sync_end_reg;
assign f1_v_sync_start = f1_v_sync_start_reg;
assign f1_v_sync_end = f1_v_sync_end_reg;
assign f_rising_edge = f_rising_edge_reg;
assign f_falling_edge = f_falling_edge_reg;
assign sof_sample = sof_sample_reg;
assign sof_subsample = sof_subsample_reg;
assign sof_line = sof_line_reg;
assign vcoclk_divider_value = vcoclk_divider_value_reg;
assign f2_anc_v_start = f2_anc_v_start_reg;
assign f1_anc_v_start = f1_anc_v_start_reg;
end else begin
assign mode_change = 1'b0;
assign vid_std = {STD_WIDTH{1'b0}};
assign vid_mode_change = 1'b0;
assign dirty_modes = 1'b0;
assign interlaced = interlaced_rst;
assign serial_output = serial_output_rst;
assign h_total_minus_one = h_total_minus_one_rst;
assign v_total_minus_one = v_total_minus_one_rst;
assign ap_line = ap_line_rst;
assign ap_line_end = ap_line_end_rst;
assign h_blank = h_blank_rst;
assign sav = sav_rst;
assign h_sync_start = h_sync_start_rst;
assign h_sync_end = h_sync_end_rst;
assign f2_v_start = f2_v_start_rst;
assign f1_v_start = f1_v_start_rst;
assign f1_v_end = f1_v_end_rst;
assign f1_v_end_nxt = f1_v_end_rst;
assign f2_v_sync_start = f2_v_sync_start_rst;
assign f2_v_sync_end = f2_v_sync_end_rst;
assign f1_v_sync_start = f1_v_sync_start_rst;
assign f1_v_sync_end = f1_v_sync_end_rst;
assign f_rising_edge = f_rising_edge_rst;
assign f_falling_edge = f_falling_edge_rst;
assign sof_sample = 14'd0;
assign sof_subsample = 2'd0;
assign sof_line = 13'd0;
assign vcoclk_divider_value = 14'd0;
assign f2_anc_v_start = f2_anc_v_start_rst;
assign f1_anc_v_start = f1_anc_v_start_rst;
assign mode_match_safe = {NO_OF_MODES_INT{1'b0}};
end
endgenerate
endmodule | module alt_vipitc131_IS2Vid_mode_banks
#(parameter
USE_CONTROL = 0,
NO_OF_MODES_INT = 0,
LOG2_NO_OF_MODES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
TRS = 0,
INTERLACED = 0,
H_ACTIVE_PIXELS = 0,
F0_LINE_COUNT = 0,
F1_LINE_COUNT = 0,
H_FRONT_PORCH = 0,
H_SYNC_LENGTH = 0,
H_BLANK_INT = 0,
V_FRONT_PORCH = 0,
V_SYNC_LENGTH = 0,
V_BLANK_INT = 0,
FIELD0_V_FRONT_PORCH = 0,
FIELD0_V_SYNC_LENGTH = 0,
FIELD0_V_BLANK_INT = 0,
AP_LINE = 0,
FIELD0_V_RISING_EDGE = 0,
F_RISING_EDGE = 0,
F_FALLING_EDGE = 0,
CONVERT_SEQ_TO_PAR = 0,
TRS_SEQUENCE = 0,
TRS_PARALLEL = 0,
STD_WIDTH = 1,
ANC_LINE = 0,
FIELD0_ANC_LINE = 0)
(
input wire rst,
input wire clk,
input wire mode_write,
input wire find_mode_nxt,
input wire [7:0] av_address,
input wire [15:0] av_writedata,
output wire [NO_OF_MODES_INT-1:0] mode_match_safe,
output wire dirty_modes,
output wire mode_change,
output wire [STD_WIDTH-1:0] vid_std,
output wire vid_mode_change,
input wire [3:0] interlaced_field,
input wire field_prediction,
input wire [15:0] samples,
input wire [15:0] lines,
output wire interlaced,
output wire serial_output,
output wire [15:0] h_total_minus_one,
output wire [15:0] v_total_minus_one,
output wire [15:0] ap_line,
output wire [15:0] ap_line_end,
output wire [15:0] h_blank,
output wire [15:0] sav,
output wire [15:0] h_sync_start,
output wire [15:0] h_sync_end,
output wire [15:0] f2_v_start,
output wire [15:0] f1_v_start,
output wire [15:0] f1_v_end,
output wire [15:0] f2_v_sync_start,
output wire [15:0] f2_v_sync_end,
output wire [15:0] f1_v_sync_start,
output wire [15:0] f1_v_sync_end,
output wire [15:0] f_rising_edge,
output wire [15:0] f_falling_edge,
output wire [15:0] f1_v_end_nxt,
output wire [13:0] sof_sample,
output wire [12:0] sof_line,
output wire [1:0] sof_subsample,
output wire [13:0] vcoclk_divider_value,
output wire [15:0] f2_anc_v_start,
output wire [15:0] f1_anc_v_start); |
localparam REGISTERS_PER_MODE = 23;
function integer get_register_address;
input integer mode;
input integer register_no;
begin
get_register_address = (mode*(REGISTERS_PER_MODE+1))+5+register_no;
end
endfunction
wire interlaced_rst;
wire serial_output_rst;
wire [15:0] h_total_minus_one_rst;
wire [15:0] v_total_minus_one_rst;
wire [15:0] ap_line_rst;
wire [15:0] ap_line_end_rst;
wire [15:0] h_blank_rst;
wire [15:0] sav_rst;
wire [15:0] h_sync_start_rst;
wire [15:0] h_sync_end_rst;
wire [15:0] f2_v_start_rst;
wire [15:0] f1_v_start_rst;
wire [15:0] f1_v_end_rst;
wire [15:0] f2_v_sync_start_rst;
wire [15:0] f2_v_sync_end_rst;
wire [15:0] f1_v_sync_start_rst;
wire [15:0] f1_v_sync_end_rst;
wire [15:0] f_rising_edge_rst;
wire [15:0] f_falling_edge_rst;
wire [15:0] f2_anc_v_start_rst;
wire [15:0] f1_anc_v_start_rst;
alt_vipitc131_IS2Vid_calculate_mode u_calculate_mode(
.trs(TRS),
.is_interlaced(INTERLACED),
.is_serial_output(!COLOUR_PLANES_ARE_IN_PARALLEL),
.is_sample_count_f0(H_ACTIVE_PIXELS),
.is_line_count_f0(F0_LINE_COUNT),
.is_sample_count_f1(H_ACTIVE_PIXELS),
.is_line_count_f1(F1_LINE_COUNT),
.is_h_front_porch(H_FRONT_PORCH),
.is_h_sync_length(H_SYNC_LENGTH),
.is_h_blank(H_BLANK_INT),
.is_v_front_porch(V_FRONT_PORCH),
.is_v_sync_length(V_SYNC_LENGTH),
.is_v_blank(V_BLANK_INT),
.is_v1_front_porch(FIELD0_V_FRONT_PORCH),
.is_v1_sync_length(FIELD0_V_SYNC_LENGTH),
.is_v1_blank(FIELD0_V_BLANK_INT),
.is_ap_line(AP_LINE),
.is_v1_rising_edge(FIELD0_V_RISING_EDGE),
.is_f_rising_edge(F_RISING_EDGE),
.is_f_falling_edge(F_FALLING_EDGE),
.is_anc_line(ANC_LINE),
.is_v1_anc_line(FIELD0_ANC_LINE),
.interlaced_nxt(interlaced_rst),
.serial_output_nxt(serial_output_rst),
.h_total_minus_one_nxt(h_total_minus_one_rst),
.v_total_minus_one_nxt(v_total_minus_one_rst),
.ap_line_nxt(ap_line_rst),
.ap_line_end_nxt(ap_line_end_rst),
.h_blank_nxt(h_blank_rst),
.sav_nxt(sav_rst),
.h_sync_start_nxt(h_sync_start_rst),
.h_sync_end_nxt(h_sync_end_rst),
.f2_v_start_nxt(f2_v_start_rst),
.f1_v_start_nxt(f1_v_start_rst),
.f1_v_end_nxt(f1_v_end_rst),
.f2_v_sync_start_nxt(f2_v_sync_start_rst),
.f2_v_sync_end_nxt(f2_v_sync_end_rst),
.f1_v_sync_start_nxt(f1_v_sync_start_rst),
.f1_v_sync_end_nxt(f1_v_sync_end_rst),
.f_rising_edge_nxt(f_rising_edge_rst),
.f_falling_edge_nxt(f_falling_edge_rst),
.f2_anc_v_start_nxt(f2_anc_v_start_rst),
.f1_anc_v_start_nxt(f1_anc_v_start_rst));
generate
if(USE_CONTROL) begin
reg is_valid_mode[NO_OF_MODES_INT-1:0];
reg is_interlaced[NO_OF_MODES_INT-1:0];
reg is_serial_output[NO_OF_MODES_INT-1:0];
reg [15:0] is_sample_count[NO_OF_MODES_INT-1:0];
reg [15:0] is_line_count_f0[NO_OF_MODES_INT-1:0];
reg [15:0] is_line_count_f1[NO_OF_MODES_INT-1:0];
reg [15:0] is_h_front_porch[NO_OF_MODES_INT-1:0];
reg [15:0] is_h_sync_length[NO_OF_MODES_INT-1:0];
reg [15:0] is_h_blank[NO_OF_MODES_INT-1:0];
reg [15:0] is_v_front_porch[NO_OF_MODES_INT-1:0];
reg [15:0] is_v_sync_length[NO_OF_MODES_INT-1:0];
reg [15:0] is_v_blank[NO_OF_MODES_INT-1:0];
reg [15:0] is_v1_front_porch[NO_OF_MODES_INT-1:0];
reg [15:0] is_v1_sync_length[NO_OF_MODES_INT-1:0];
reg [15:0] is_v1_blank[NO_OF_MODES_INT-1:0];
reg [15:0] is_ap_line[NO_OF_MODES_INT-1:0];
reg [15:0] is_v1_rising_edge[NO_OF_MODES_INT-1:0];
reg [15:0] is_f_rising_edge[NO_OF_MODES_INT-1:0];
reg [15:0] is_f_falling_edge[NO_OF_MODES_INT-1:0];
reg [STD_WIDTH-1:0] is_standard[NO_OF_MODES_INT-1:0];
reg [13:0] is_sof_sample[NO_OF_MODES_INT-1:0];
reg [1:0] is_sof_subsample[NO_OF_MODES_INT-1:0];
reg [12:0] is_sof_line[NO_OF_MODES_INT-1:0];
reg [13:0] is_vcoclk_divider_value[NO_OF_MODES_INT-1:0];
reg [15:0] is_anc_line[NO_OF_MODES_INT-1:0];
reg [15:0] is_v1_anc_line[NO_OF_MODES_INT-1:0];
reg [NO_OF_MODES_INT-1:0] dirty_mode;
reg [NO_OF_MODES_INT-1:0] mode_match;
reg [NO_OF_MODES_INT-1:0] mode_match_reg;
reg find_mode;
reg dirty_modes_reg;
always @ (posedge rst or posedge clk) begin
if(rst) begin
find_mode <= 1'b0;
dirty_modes_reg <= 1'b0;
end else begin
find_mode <= find_mode_nxt;
dirty_modes_reg <= |dirty_mode;
end
end
genvar i;
for(i = 0; i < NO_OF_MODES_INT; i = i + 1) begin : is_registers
always @ (posedge rst or posedge clk) begin
if(rst) begin
is_valid_mode[i] <= 1'b0;
is_interlaced[i] <= 1'b0;
is_serial_output[i] <= 1'b0;
is_sample_count[i] <= 16'd0;
is_line_count_f0[i] <= 16'd0;
is_line_count_f1[i] <= 16'd0;
is_h_front_porch[i] <= 16'd0;
is_h_sync_length[i] <= 16'd0;
is_h_blank[i] <= 16'd0;
is_v_front_porch[i] <= 16'd0;
is_v_sync_length[i] <= 16'd0;
is_v_blank[i] <= 16'd0;
is_v1_front_porch[i] <= 16'd0;
is_v1_sync_length[i] <= 16'd0;
is_v1_blank[i] <= 16'd0;
is_ap_line[i] <= 16'd0;
is_v1_rising_edge[i] <= 16'd0;
is_f_rising_edge[i] <= 16'd0;
is_f_falling_edge[i] <= 16'd0;
is_standard[i] <= {STD_WIDTH{1'b0}};
is_sof_sample[i] <= 14'd0;
is_sof_subsample[i] <= 2'd0;
is_sof_line[i] <= 13'd0;
is_vcoclk_divider_value[i] <= 14'd0;
is_anc_line[i] <= 16'd0;
is_v1_anc_line[i] <= 16'd0;
dirty_mode[i] <= 1'b0;
mode_match[i] <= 1'b0;
end else begin
if(mode_write) begin
if(~is_valid_mode[i]) begin
if(av_address == get_register_address(i, 0)) begin
is_interlaced[i] <= av_writedata[0];
if(CONVERT_SEQ_TO_PAR)
is_serial_output[i] <= av_writedata[1];
else
is_serial_output[i] <= serial_output_rst;
end
is_sample_count[i] <= (av_address == get_register_address(i, 1)) ? av_writedata : is_sample_count[i];
is_line_count_f0[i] <= (av_address == get_register_address(i, 2)) ? av_writedata : is_line_count_f0[i];
is_line_count_f1[i] <= (av_address == get_register_address(i, 3)) ? av_writedata : is_line_count_f1[i];
is_h_front_porch[i] <= (av_address == get_register_address(i, 4)) ? av_writedata : is_h_front_porch[i];
is_h_sync_length[i] <= (av_address == get_register_address(i, 5)) ? av_writedata : is_h_sync_length[i];
is_h_blank[i] <= (av_address == get_register_address(i, 6)) ? av_writedata : is_h_blank[i];
is_v_front_porch[i] <= (av_address == get_register_address(i, 7)) ? av_writedata : is_v_front_porch[i];
is_v_sync_length[i] <= (av_address == get_register_address(i, 8)) ? av_writedata : is_v_sync_length[i];
is_v_blank[i] <= (av_address == get_register_address(i, 9)) ? av_writedata : is_v_blank[i];
is_v1_front_porch[i] <= (av_address == get_register_address(i, 10)) ? av_writedata : is_v1_front_porch[i];
is_v1_sync_length[i] <= (av_address == get_register_address(i, 11)) ? av_writedata : is_v1_sync_length[i];
is_v1_blank[i] <= (av_address == get_register_address(i, 12)) ? av_writedata : is_v1_blank[i];
is_ap_line[i] <= (av_address == get_register_address(i, 13)) ? av_writedata : is_ap_line[i];
is_v1_rising_edge[i] <= (av_address == get_register_address(i, 14)) ? av_writedata : is_v1_rising_edge[i];
is_f_rising_edge[i] <= (av_address == get_register_address(i, 15)) ? av_writedata : is_f_rising_edge[i];
is_f_falling_edge[i] <= (av_address == get_register_address(i, 16)) ? av_writedata : is_f_falling_edge[i];
is_standard[i] <= (av_address == get_register_address(i, 17)) ? av_writedata[STD_WIDTH-1:0] : is_standard[i];
if(av_address == get_register_address(i, 18)) begin
is_sof_sample[i] <= av_writedata[15:2];
is_sof_subsample[i] <= av_writedata[1:0];
end
is_sof_line[i] <= (av_address == get_register_address(i, 19)) ? av_writedata[12:0] : is_sof_line[i];
is_vcoclk_divider_value[i] <= (av_address == get_register_address(i, 20)) ? av_writedata[13:0] : is_vcoclk_divider_value[i];
is_anc_line[i] <= (av_address == get_register_address(i, 21)) ? av_writedata[15:0] : is_anc_line[i];
is_v1_anc_line[i] <= (av_address == get_register_address(i, 22)) ? av_writedata[15:0] : is_v1_anc_line[i];
end
is_valid_mode[i] <= (av_address == get_register_address(i, 23)) ? av_writedata[0] : is_valid_mode[i];
end
dirty_mode[i] <= (mode_write && av_address == get_register_address(i, 23) && av_writedata[0]) || (dirty_mode[i] && ~mode_change);
mode_match[i] <= ({interlaced_field[3], field_prediction} == 2'b11) ? is_valid_mode[i] & is_interlaced[i] & samples == is_sample_count[i] & lines == is_line_count_f1[i] :
({interlaced_field[3], field_prediction} == 2'b10) ? is_valid_mode[i] & is_interlaced[i] & samples == is_sample_count[i] & lines == is_line_count_f0[i] :
is_valid_mode[i] & samples == is_sample_count[i] & lines == is_line_count_f0[i];
end
end
end
assign dirty_modes = dirty_modes_reg;
wire interlaced_nxt;
wire serial_output_nxt;
wire [15:0] h_total_minus_one_nxt;
wire [15:0] v_total_minus_one_nxt;
wire [15:0] ap_line_nxt;
wire [15:0] ap_line_end_nxt;
wire [15:0] h_blank_nxt;
wire [15:0] sav_nxt;
wire [15:0] h_sync_start_nxt;
wire [15:0] h_sync_end_nxt;
wire [15:0] f2_v_start_nxt;
wire [15:0] f1_v_start_nxt;
wire [15:0] f2_v_sync_start_nxt;
wire [15:0] f2_v_sync_end_nxt;
wire [15:0] f1_v_sync_start_nxt;
wire [15:0] f1_v_sync_end_nxt;
wire [15:0] f_rising_edge_nxt;
wire [15:0] f_falling_edge_nxt;
wire [15:0] f2_anc_v_start_nxt;
wire [15:0] f1_anc_v_start_nxt;
reg interlaced_reg;
reg serial_output_reg;
reg [15:0] h_total_minus_one_reg;
reg [15:0] v_total_minus_one_reg;
reg [15:0] ap_line_reg;
reg [15:0] ap_line_end_reg;
reg [15:0] h_blank_reg;
reg [15:0] sav_reg;
reg [15:0] h_sync_start_reg;
reg [15:0] h_sync_end_reg;
reg [15:0] f2_v_start_reg;
reg [15:0] f1_v_start_reg;
reg [15:0] f1_v_end_reg;
reg [15:0] f2_v_sync_start_reg;
reg [15:0] f2_v_sync_end_reg;
reg [15:0] f1_v_sync_start_reg;
reg [15:0] f1_v_sync_end_reg;
reg [15:0] f_rising_edge_reg;
reg [15:0] f_falling_edge_reg;
reg [STD_WIDTH-1:0] standard_reg;
reg [13:0] sof_sample_reg;
reg [1:0] sof_subsample_reg;
reg [12:0] sof_line_reg;
reg [13:0] vcoclk_divider_value_reg;
reg [15:0] f2_anc_v_start_reg;
reg [15:0] f1_anc_v_start_reg;
wire [LOG2_NO_OF_MODES-1:0] mode;
reg mode_change_reg;
if(NO_OF_MODES_INT > 1) begin
assign mode_match_safe[0] = mode_match[0];
for(i = 1; i < NO_OF_MODES_INT; i = i + 1) begin : is_registers
assign mode_match_safe[i] = mode_match[i] & ~|mode_match[i-1:0];
end
alt_vipitc131_common_to_binary u_to_binary(
.one_hot(mode_match_safe[NO_OF_MODES_INT-1:1]),
.binary(mode)
);
defparam u_to_binary.NO_OF_MODES = NO_OF_MODES_INT - 1,
u_to_binary.LOG2_NO_OF_MODES = LOG2_NO_OF_MODES;
end else begin
assign mode = 1'b0;
assign mode_match_safe = mode_match;
end
assign mode_change = find_mode & |mode_match_safe & (|(mode_match_safe ^ mode_match_reg) | dirty_mode[mode]);
assign vid_std = standard_reg;
assign vid_mode_change = mode_change_reg;
wire [3:0] trs_mux;
assign trs_mux = (is_serial_output[mode]) ? TRS_SEQUENCE : TRS_PARALLEL;
alt_vipitc131_IS2Vid_calculate_mode u_calculate_mode_dynamic(
.trs(trs_mux),
.is_interlaced(is_interlaced[mode]),
.is_serial_output(is_serial_output[mode]),
.is_sample_count_f0(is_sample_count[mode]),
.is_line_count_f0(is_line_count_f0[mode]),
.is_sample_count_f1(is_sample_count[mode]),
.is_line_count_f1(is_line_count_f1[mode]),
.is_h_front_porch(is_h_front_porch[mode]),
.is_h_sync_length(is_h_sync_length[mode]),
.is_h_blank(is_h_blank[mode]),
.is_v_front_porch(is_v_front_porch[mode]),
.is_v_sync_length(is_v_sync_length[mode]),
.is_v_blank(is_v_blank[mode]),
.is_v1_front_porch(is_v1_front_porch[mode]),
.is_v1_sync_length(is_v1_sync_length[mode]),
.is_v1_blank(is_v1_blank[mode]),
.is_ap_line(is_ap_line[mode]),
.is_v1_rising_edge(is_v1_rising_edge[mode]),
.is_f_rising_edge(is_f_rising_edge[mode]),
.is_f_falling_edge(is_f_falling_edge[mode]),
.is_anc_line(is_anc_line[mode]),
.is_v1_anc_line(is_v1_anc_line[mode]),
.interlaced_nxt(interlaced_nxt),
.serial_output_nxt(serial_output_nxt),
.h_total_minus_one_nxt(h_total_minus_one_nxt),
.v_total_minus_one_nxt(v_total_minus_one_nxt),
.ap_line_nxt(ap_line_nxt),
.ap_line_end_nxt(ap_line_end_nxt),
.h_blank_nxt(h_blank_nxt),
.sav_nxt(sav_nxt),
.h_sync_start_nxt(h_sync_start_nxt),
.h_sync_end_nxt(h_sync_end_nxt),
.f2_v_start_nxt(f2_v_start_nxt),
.f1_v_start_nxt(f1_v_start_nxt),
.f1_v_end_nxt(f1_v_end_nxt),
.f2_v_sync_start_nxt(f2_v_sync_start_nxt),
.f2_v_sync_end_nxt(f2_v_sync_end_nxt),
.f1_v_sync_start_nxt(f1_v_sync_start_nxt),
.f1_v_sync_end_nxt(f1_v_sync_end_nxt),
.f_rising_edge_nxt(f_rising_edge_nxt),
.f_falling_edge_nxt(f_falling_edge_nxt),
.f2_anc_v_start_nxt(f2_anc_v_start_nxt),
.f1_anc_v_start_nxt(f1_anc_v_start_nxt));
always @ (posedge rst or posedge clk) begin
if(rst) begin
mode_change_reg <= 1'b0;
mode_match_reg <= {NO_OF_MODES_INT{1'b0}};
interlaced_reg <= interlaced_rst;
serial_output_reg <= serial_output_rst;
h_total_minus_one_reg <= h_total_minus_one_rst;
v_total_minus_one_reg <= v_total_minus_one_rst;
ap_line_reg <= ap_line_rst;
ap_line_end_reg <= ap_line_end_rst;
h_blank_reg <= h_blank_rst;
sav_reg <= sav_rst;
h_sync_start_reg <= h_sync_start_rst;
h_sync_end_reg <= h_sync_end_rst;
f2_v_start_reg <= f2_v_start_rst;
f1_v_start_reg <= f1_v_start_rst;
f1_v_end_reg <= f1_v_end_rst;
f2_v_sync_start_reg <= f2_v_sync_start_rst;
f2_v_sync_end_reg <= f2_v_sync_end_rst;
f1_v_sync_start_reg <= f1_v_sync_start_rst;
f1_v_sync_end_reg <= f1_v_sync_end_rst;
f_rising_edge_reg <= f_rising_edge_rst;
f_falling_edge_reg <= f_falling_edge_rst;
standard_reg <= {STD_WIDTH{1'b0}};
sof_sample_reg <= 14'd0;
sof_subsample_reg <= 2'd0;
sof_line_reg <= 13'd0;
vcoclk_divider_value_reg <= 14'd0;
f2_anc_v_start_reg <= f2_anc_v_start_rst;
f1_anc_v_start_reg <= f1_anc_v_start_rst;
end else begin
mode_change_reg <= mode_change;
mode_match_reg <= (mode_change) ? mode_match_safe : mode_match_reg;
if(mode_change) begin
interlaced_reg <= interlaced_nxt;
serial_output_reg = serial_output_nxt;
h_total_minus_one_reg <= h_total_minus_one_nxt;
v_total_minus_one_reg <= v_total_minus_one_nxt;
ap_line_reg <= ap_line_nxt;
ap_line_end_reg <= ap_line_end_nxt;
h_blank_reg <= h_blank_nxt;
sav_reg <= sav_nxt;
h_sync_start_reg <= h_sync_start_nxt;
h_sync_end_reg <= h_sync_end_nxt;
f2_v_start_reg <= f2_v_start_nxt;
f1_v_start_reg <= f1_v_start_nxt;
f1_v_end_reg <= f1_v_end_nxt;
f2_v_sync_start_reg <= f2_v_sync_start_nxt;
f2_v_sync_end_reg <= f2_v_sync_end_nxt;
f1_v_sync_start_reg <= f1_v_sync_start_nxt;
f1_v_sync_end_reg <= f1_v_sync_end_nxt;
f_rising_edge_reg <= f_rising_edge_nxt;
f_falling_edge_reg <= f_falling_edge_nxt;
standard_reg <= is_standard[mode];
sof_sample_reg <= is_sof_sample[mode];
sof_subsample_reg <= is_sof_subsample[mode];
sof_line_reg <= is_sof_line[mode];
vcoclk_divider_value_reg <= is_vcoclk_divider_value[mode];
f2_anc_v_start_reg <= f2_anc_v_start_nxt;
f1_anc_v_start_reg <= f1_anc_v_start_nxt;
end
end
end
assign interlaced = interlaced_reg;
assign serial_output = serial_output_reg;
assign h_total_minus_one = h_total_minus_one_reg;
assign v_total_minus_one = v_total_minus_one_reg;
assign ap_line = ap_line_reg;
assign ap_line_end = ap_line_end_reg;
assign h_blank = h_blank_reg;
assign sav = sav_reg;
assign h_sync_start = h_sync_start_reg;
assign h_sync_end = h_sync_end_reg;
assign f2_v_start = f2_v_start_reg;
assign f1_v_start = f1_v_start_reg;
assign f1_v_end = f1_v_end_reg;
assign f2_v_sync_start = f2_v_sync_start_reg;
assign f2_v_sync_end = f2_v_sync_end_reg;
assign f1_v_sync_start = f1_v_sync_start_reg;
assign f1_v_sync_end = f1_v_sync_end_reg;
assign f_rising_edge = f_rising_edge_reg;
assign f_falling_edge = f_falling_edge_reg;
assign sof_sample = sof_sample_reg;
assign sof_subsample = sof_subsample_reg;
assign sof_line = sof_line_reg;
assign vcoclk_divider_value = vcoclk_divider_value_reg;
assign f2_anc_v_start = f2_anc_v_start_reg;
assign f1_anc_v_start = f1_anc_v_start_reg;
end else begin
assign mode_change = 1'b0;
assign vid_std = {STD_WIDTH{1'b0}};
assign vid_mode_change = 1'b0;
assign dirty_modes = 1'b0;
assign interlaced = interlaced_rst;
assign serial_output = serial_output_rst;
assign h_total_minus_one = h_total_minus_one_rst;
assign v_total_minus_one = v_total_minus_one_rst;
assign ap_line = ap_line_rst;
assign ap_line_end = ap_line_end_rst;
assign h_blank = h_blank_rst;
assign sav = sav_rst;
assign h_sync_start = h_sync_start_rst;
assign h_sync_end = h_sync_end_rst;
assign f2_v_start = f2_v_start_rst;
assign f1_v_start = f1_v_start_rst;
assign f1_v_end = f1_v_end_rst;
assign f1_v_end_nxt = f1_v_end_rst;
assign f2_v_sync_start = f2_v_sync_start_rst;
assign f2_v_sync_end = f2_v_sync_end_rst;
assign f1_v_sync_start = f1_v_sync_start_rst;
assign f1_v_sync_end = f1_v_sync_end_rst;
assign f_rising_edge = f_rising_edge_rst;
assign f_falling_edge = f_falling_edge_rst;
assign sof_sample = 14'd0;
assign sof_subsample = 2'd0;
assign sof_line = 13'd0;
assign vcoclk_divider_value = 14'd0;
assign f2_anc_v_start = f2_anc_v_start_rst;
assign f1_anc_v_start = f1_anc_v_start_rst;
assign mode_match_safe = {NO_OF_MODES_INT{1'b0}};
end
endgenerate
endmodule | 5 |
6,580 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_mode_banks.sv | 116,866,011 | alt_vipitc131_IS2Vid_mode_banks.sv | sv | 609 | 197 | [] | [] | [] | null | line:87: before: "integer" | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_mode_banks.sv:42: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [NO_OF_MODES_INT-1:0] mode_match_safe,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_mode_banks.sv:117: Cannot find file containing module: \'alt_vipitc131_IS2Vid_calculate_mode\'\nalt_vipitc131_IS2Vid_calculate_mode u_calculate_mode(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_IS2Vid_calculate_mode\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_IS2Vid_calculate_mode.v\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_IS2Vid_calculate_mode.sv\n alt_vipitc131_IS2Vid_calculate_mode\n alt_vipitc131_IS2Vid_calculate_mode.v\n alt_vipitc131_IS2Vid_calculate_mode.sv\n obj_dir/alt_vipitc131_IS2Vid_calculate_mode\n obj_dir/alt_vipitc131_IS2Vid_calculate_mode.v\n obj_dir/alt_vipitc131_IS2Vid_calculate_mode.sv\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_mode_banks.sv:603: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n : ... In instance alt_vipitc131_IS2Vid_mode_banks\n assign mode_match_safe = {NO_OF_MODES_INT{1\'b0}};\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_mode_banks.sv:603: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1 bits.\n : ... In instance alt_vipitc131_IS2Vid_mode_banks\n assign mode_match_safe = {NO_OF_MODES_INT{1\'b0}};\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 7,604 | function | function integer get_register_address;
input integer mode;
input integer register_no;
begin
get_register_address = (mode*(REGISTERS_PER_MODE+1))+5+register_no;
end
endfunction | function integer get_register_address; |
input integer mode;
input integer register_no;
begin
get_register_address = (mode*(REGISTERS_PER_MODE+1))+5+register_no;
end
endfunction | 5 |
6,582 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v | 116,866,011 | alt_vipitc131_IS2Vid_sync_compare.v | v | 263 | 104 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v:120: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s CONST \'14\'h0\' generates 14 bits.\n : ... In instance alt_vipitc131_IS2Vid_sync_compare\n sync_compare_h_reset <= 14\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v:167: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s VARREF \'sync_compare_h_reset_next\' generates 13 bits.\n : ... In instance alt_vipitc131_IS2Vid_sync_compare\n sync_compare_h_reset0 <= sync_compare_h_reset_next;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v:176: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s VARREF \'sync_compare_h_reset_next\' generates 13 bits.\n : ... In instance alt_vipitc131_IS2Vid_sync_compare\n sync_compare_h_reset0 <= sync_compare_h_reset_next;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v:175: Operator GT expects 14 bits on the LHS, but LHS\'s VARREF \'sync_compare_h_reset_next\' generates 13 bits.\n : ... In instance alt_vipitc131_IS2Vid_sync_compare\n if(sync_compare_h_reset_next > divider_value) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v:202: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'sync_compare_h_reset1\' generates 14 bits.\n : ... In instance alt_vipitc131_IS2Vid_sync_compare\n sync_compare_h_reset <= sync_compare_h_reset1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v:214: Operator ASSIGNW expects 13 bits on the Assign RHS, but Assign RHS\'s COND generates 14 bits.\n : ... In instance alt_vipitc131_IS2Vid_sync_compare\nassign sync_compare_h_reset_next = (remove_lines_next) ? h_count_remove : h_count_repeat;\n ^\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v:240: Cannot find file containing module: \'alt_vipitc131_common_frame_counter\'\nalt_vipitc131_common_frame_counter frame_counter(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_frame_counter\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_frame_counter.v\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipitc131_common_frame_counter.sv\n alt_vipitc131_common_frame_counter\n alt_vipitc131_common_frame_counter.v\n alt_vipitc131_common_frame_counter.sv\n obj_dir/alt_vipitc131_common_frame_counter\n obj_dir/alt_vipitc131_common_frame_counter.v\n obj_dir/alt_vipitc131_common_frame_counter.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n' | 7,606 | module | module alt_vipitc131_IS2Vid_sync_compare(
input wire rst,
input wire clk,
input wire [1:0] genlock_enable,
input wire serial_output,
input wire [13:0] h_total_minus_one,
input wire restart_count,
input wire [13:0] divider_value,
output reg sync_lines,
output reg sync_samples,
output reg remove_repeatn,
output reg [12:0] sync_compare_h_reset,
output reg [12:0] sync_compare_v_reset,
output reg genlocked,
input wire sof_cvi,
input wire sof_cvi_locked,
input wire sof_cvo,
input wire sof_cvo_locked);
parameter NUMBER_OF_COLOUR_PLANES = 0;
parameter COLOUR_PLANES_ARE_IN_PARALLEL = 0;
parameter LOG2_NUMBER_OF_COLOUR_PLANES = 0;
wire sof_cvi_int;
wire sof_cvo_int;
reg sof_cvi_reg;
reg sof_cvo_reg;
always @ (posedge rst or posedge clk) begin
if(rst) begin
sof_cvi_reg <= 1'b0;
sof_cvo_reg <= 1'b0;
end else begin
sof_cvi_reg <= sof_cvi;
sof_cvo_reg <= sof_cvo;
end
end
assign sof_cvi_int = sof_cvi & ~sof_cvi_reg;
assign sof_cvo_int = sof_cvo & ~sof_cvo_reg;
wire enable;
wire sclr;
wire sclr_frame_counter;
wire sclr_state;
assign enable = sof_cvi_locked & sof_cvo_locked & genlock_enable[1] & genlock_enable[0];
assign sclr = ~enable | restart_count;
assign sclr_frame_counter = sclr | sof_cvi_int | sof_cvo_int;
assign sclr_state = (sof_cvi_int & sof_cvo_int);
reg [13:0] h_count_repeat;
reg [13:0] h_count_remove;
reg [12:0] v_count_repeat;
reg [12:0] v_count_remove;
reg [1:0] next_state;
reg [1:0] state;
wire [13:0] h_count;
wire [12:0] v_count;
wire remove_lines_next;
wire [12:0] sync_compare_v_reset_next;
wire [12:0] sync_compare_h_reset_next;
wire valid;
reg v_count_remove_valid;
reg v_count_repeat_valid;
wire syncing_lines;
wire remove_samples_next;
reg sync_lines0;
reg sync_samples0;
reg remove_repeatn0;
reg [13:0] sync_compare_h_reset0;
reg [12:0] sync_compare_v_reset0;
reg genlocked0;
reg sync_lines1;
reg sync_samples1;
reg remove_repeatn1;
reg [13:0] sync_compare_h_reset1;
reg [12:0] sync_compare_v_reset1;
reg genlocked1;
always @ (posedge rst or posedge clk) begin
if(rst) begin
h_count_repeat <= 14'd0;
h_count_remove <= 14'd0;
v_count_repeat <= 13'd0;
v_count_repeat_valid <= 1'b0;
v_count_remove <= 13'd0;
v_count_remove_valid <= 1'b0;
state <= `SC_IDLE;
sync_lines0 <= 1'b0;
sync_samples0 <= 1'b0;
sync_compare_v_reset0 <= 13'd0;
sync_compare_h_reset0 <= 14'd0;
remove_repeatn0 <= 1'b0;
genlocked0 <= 1'b0;
sync_lines1 <= 1'b0;
sync_samples1 <= 1'b0;
sync_compare_v_reset1 <= 13'd0;
sync_compare_h_reset1 <= 14'd0;
remove_repeatn1 <= 1'b0;
genlocked1 <= 1'b0;
sync_lines <= 1'b0;
sync_samples <= 1'b0;
sync_compare_v_reset <= 13'd0;
sync_compare_h_reset <= 14'd0;
remove_repeatn <= 1'b0;
genlocked <= 1'b0;
end else begin
if(sclr) begin
h_count_repeat <= 14'd0;
h_count_remove <= 14'd0;
v_count_repeat <= 13'd0;
v_count_repeat_valid <= 1'b0;
v_count_remove <= 13'd0;
v_count_remove_valid <= 1'b0;
state <= `SC_IDLE;
end else begin
if(sclr_state) begin
h_count_repeat <= 14'd0;
h_count_remove <= 14'd0;
v_count_repeat <= 13'd0;
v_count_repeat_valid <= (14'd0 == h_count_repeat) && (13'd0 == v_count_repeat);
v_count_remove <= 13'd0;
v_count_remove_valid <= (14'd0 == h_count_remove) && (13'd0 == v_count_remove);
end else begin
if(state == `SC_CVI && next_state == `SC_CVO) begin
h_count_remove <= h_count;
v_count_remove <= v_count;
v_count_remove_valid <= (h_count == h_count_remove) && (v_count == v_count_remove);
end
if(state == `SC_CVO && next_state == `SC_CVI) begin
h_count_repeat <= h_count;
v_count_repeat <= v_count;
v_count_repeat_valid <= (h_count == h_count_repeat) && (v_count == v_count_repeat);
end
end
state <= next_state;
end
if(sclr | ~valid) begin
sync_lines0 <= 1'b0;
sync_samples0 <= 1'b0;
sync_compare_v_reset0 <= 13'd0;
sync_compare_h_reset0 <= 14'd0;
genlocked0 <= 1'b0;
end else begin
if(syncing_lines) begin
sync_compare_v_reset0 <= sync_compare_v_reset_next;
sync_lines0 <= 1'b1;
sync_compare_h_reset0 <= sync_compare_h_reset_next;
sync_samples0 <= 1'b1;
genlocked0 <= 1'b0;
end else begin
sync_compare_v_reset0 <= 13'd0;
sync_lines0 <= 1'b0;
if(sync_compare_h_reset_next > divider_value) begin
sync_compare_h_reset0 <= sync_compare_h_reset_next;
sync_samples0 <= 1'b1;
genlocked0 <= 1'b0;
end else begin
sync_compare_h_reset0 <= 14'd0;
sync_samples0 <= 1'b0;
genlocked0 <= 1'b1;
end
end
end
remove_repeatn0 <= remove_samples_next;
sync_lines1 <= sync_lines0;
sync_samples1 <= sync_samples0;
remove_repeatn1 <= remove_repeatn0;
sync_compare_h_reset1 <= sync_compare_h_reset0;
sync_compare_v_reset1 <= sync_compare_v_reset0;
genlocked1 <= genlocked0;
sync_lines <= sync_lines1;
sync_samples <= sync_samples1;
remove_repeatn <= remove_repeatn1;
sync_compare_h_reset <= sync_compare_h_reset1;
sync_compare_v_reset <= sync_compare_v_reset1;
genlocked <= genlocked1;
end
end
assign valid = v_count_remove_valid & v_count_repeat_valid;
assign remove_lines_next = v_count_remove < v_count_repeat;
assign sync_compare_v_reset_next = (remove_lines_next) ? v_count_remove : v_count_repeat;
assign syncing_lines = sync_compare_v_reset_next > 13'd0;
assign remove_samples_next = (syncing_lines) ? remove_lines_next : h_count_remove < h_count_repeat;
assign sync_compare_h_reset_next = (remove_lines_next) ? h_count_remove : h_count_repeat;
always @ (state or sof_cvi_int or sof_cvo_int) begin
next_state = state;
case(state)
`SC_CVI: begin
if(sof_cvo_int & sof_cvi_int)
next_state = `SC_IDLE;
else if(sof_cvo_int)
next_state = `SC_CVO;
end
`SC_CVO: begin
if(sof_cvi_int & sof_cvo_int)
next_state = `SC_IDLE;
else if(sof_cvi_int)
next_state = `SC_CVI;
end
default: begin
if(sof_cvi_int & ~sof_cvo_int)
next_state = `SC_CVI;
else if(~sof_cvi_int & sof_cvo_int)
next_state = `SC_CVO;
end
endcase
end
alt_vipitc131_common_frame_counter frame_counter(
.rst(rst),
.clk(clk),
.sclr(sclr_frame_counter),
.enable(enable),
.hd_sdn(~serial_output),
.h_total(h_total_minus_one),
.v_total({13{1'b1}}),
.h_reset(14'd0),
.v_reset(13'd0),
.h_count(h_count),
.v_count(v_count));
defparam frame_counter.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
frame_counter.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
frame_counter.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_NUMBER_OF_COLOUR_PLANES,
frame_counter.TOTALS_MINUS_ONE = 1;
endmodule | module alt_vipitc131_IS2Vid_sync_compare(
input wire rst,
input wire clk,
input wire [1:0] genlock_enable,
input wire serial_output,
input wire [13:0] h_total_minus_one,
input wire restart_count,
input wire [13:0] divider_value,
output reg sync_lines,
output reg sync_samples,
output reg remove_repeatn,
output reg [12:0] sync_compare_h_reset,
output reg [12:0] sync_compare_v_reset,
output reg genlocked,
input wire sof_cvi,
input wire sof_cvi_locked,
input wire sof_cvo,
input wire sof_cvo_locked); |
parameter NUMBER_OF_COLOUR_PLANES = 0;
parameter COLOUR_PLANES_ARE_IN_PARALLEL = 0;
parameter LOG2_NUMBER_OF_COLOUR_PLANES = 0;
wire sof_cvi_int;
wire sof_cvo_int;
reg sof_cvi_reg;
reg sof_cvo_reg;
always @ (posedge rst or posedge clk) begin
if(rst) begin
sof_cvi_reg <= 1'b0;
sof_cvo_reg <= 1'b0;
end else begin
sof_cvi_reg <= sof_cvi;
sof_cvo_reg <= sof_cvo;
end
end
assign sof_cvi_int = sof_cvi & ~sof_cvi_reg;
assign sof_cvo_int = sof_cvo & ~sof_cvo_reg;
wire enable;
wire sclr;
wire sclr_frame_counter;
wire sclr_state;
assign enable = sof_cvi_locked & sof_cvo_locked & genlock_enable[1] & genlock_enable[0];
assign sclr = ~enable | restart_count;
assign sclr_frame_counter = sclr | sof_cvi_int | sof_cvo_int;
assign sclr_state = (sof_cvi_int & sof_cvo_int);
reg [13:0] h_count_repeat;
reg [13:0] h_count_remove;
reg [12:0] v_count_repeat;
reg [12:0] v_count_remove;
reg [1:0] next_state;
reg [1:0] state;
wire [13:0] h_count;
wire [12:0] v_count;
wire remove_lines_next;
wire [12:0] sync_compare_v_reset_next;
wire [12:0] sync_compare_h_reset_next;
wire valid;
reg v_count_remove_valid;
reg v_count_repeat_valid;
wire syncing_lines;
wire remove_samples_next;
reg sync_lines0;
reg sync_samples0;
reg remove_repeatn0;
reg [13:0] sync_compare_h_reset0;
reg [12:0] sync_compare_v_reset0;
reg genlocked0;
reg sync_lines1;
reg sync_samples1;
reg remove_repeatn1;
reg [13:0] sync_compare_h_reset1;
reg [12:0] sync_compare_v_reset1;
reg genlocked1;
always @ (posedge rst or posedge clk) begin
if(rst) begin
h_count_repeat <= 14'd0;
h_count_remove <= 14'd0;
v_count_repeat <= 13'd0;
v_count_repeat_valid <= 1'b0;
v_count_remove <= 13'd0;
v_count_remove_valid <= 1'b0;
state <= `SC_IDLE;
sync_lines0 <= 1'b0;
sync_samples0 <= 1'b0;
sync_compare_v_reset0 <= 13'd0;
sync_compare_h_reset0 <= 14'd0;
remove_repeatn0 <= 1'b0;
genlocked0 <= 1'b0;
sync_lines1 <= 1'b0;
sync_samples1 <= 1'b0;
sync_compare_v_reset1 <= 13'd0;
sync_compare_h_reset1 <= 14'd0;
remove_repeatn1 <= 1'b0;
genlocked1 <= 1'b0;
sync_lines <= 1'b0;
sync_samples <= 1'b0;
sync_compare_v_reset <= 13'd0;
sync_compare_h_reset <= 14'd0;
remove_repeatn <= 1'b0;
genlocked <= 1'b0;
end else begin
if(sclr) begin
h_count_repeat <= 14'd0;
h_count_remove <= 14'd0;
v_count_repeat <= 13'd0;
v_count_repeat_valid <= 1'b0;
v_count_remove <= 13'd0;
v_count_remove_valid <= 1'b0;
state <= `SC_IDLE;
end else begin
if(sclr_state) begin
h_count_repeat <= 14'd0;
h_count_remove <= 14'd0;
v_count_repeat <= 13'd0;
v_count_repeat_valid <= (14'd0 == h_count_repeat) && (13'd0 == v_count_repeat);
v_count_remove <= 13'd0;
v_count_remove_valid <= (14'd0 == h_count_remove) && (13'd0 == v_count_remove);
end else begin
if(state == `SC_CVI && next_state == `SC_CVO) begin
h_count_remove <= h_count;
v_count_remove <= v_count;
v_count_remove_valid <= (h_count == h_count_remove) && (v_count == v_count_remove);
end
if(state == `SC_CVO && next_state == `SC_CVI) begin
h_count_repeat <= h_count;
v_count_repeat <= v_count;
v_count_repeat_valid <= (h_count == h_count_repeat) && (v_count == v_count_repeat);
end
end
state <= next_state;
end
if(sclr | ~valid) begin
sync_lines0 <= 1'b0;
sync_samples0 <= 1'b0;
sync_compare_v_reset0 <= 13'd0;
sync_compare_h_reset0 <= 14'd0;
genlocked0 <= 1'b0;
end else begin
if(syncing_lines) begin
sync_compare_v_reset0 <= sync_compare_v_reset_next;
sync_lines0 <= 1'b1;
sync_compare_h_reset0 <= sync_compare_h_reset_next;
sync_samples0 <= 1'b1;
genlocked0 <= 1'b0;
end else begin
sync_compare_v_reset0 <= 13'd0;
sync_lines0 <= 1'b0;
if(sync_compare_h_reset_next > divider_value) begin
sync_compare_h_reset0 <= sync_compare_h_reset_next;
sync_samples0 <= 1'b1;
genlocked0 <= 1'b0;
end else begin
sync_compare_h_reset0 <= 14'd0;
sync_samples0 <= 1'b0;
genlocked0 <= 1'b1;
end
end
end
remove_repeatn0 <= remove_samples_next;
sync_lines1 <= sync_lines0;
sync_samples1 <= sync_samples0;
remove_repeatn1 <= remove_repeatn0;
sync_compare_h_reset1 <= sync_compare_h_reset0;
sync_compare_v_reset1 <= sync_compare_v_reset0;
genlocked1 <= genlocked0;
sync_lines <= sync_lines1;
sync_samples <= sync_samples1;
remove_repeatn <= remove_repeatn1;
sync_compare_h_reset <= sync_compare_h_reset1;
sync_compare_v_reset <= sync_compare_v_reset1;
genlocked <= genlocked1;
end
end
assign valid = v_count_remove_valid & v_count_repeat_valid;
assign remove_lines_next = v_count_remove < v_count_repeat;
assign sync_compare_v_reset_next = (remove_lines_next) ? v_count_remove : v_count_repeat;
assign syncing_lines = sync_compare_v_reset_next > 13'd0;
assign remove_samples_next = (syncing_lines) ? remove_lines_next : h_count_remove < h_count_repeat;
assign sync_compare_h_reset_next = (remove_lines_next) ? h_count_remove : h_count_repeat;
always @ (state or sof_cvi_int or sof_cvo_int) begin
next_state = state;
case(state)
`SC_CVI: begin
if(sof_cvo_int & sof_cvi_int)
next_state = `SC_IDLE;
else if(sof_cvo_int)
next_state = `SC_CVO;
end
`SC_CVO: begin
if(sof_cvi_int & sof_cvo_int)
next_state = `SC_IDLE;
else if(sof_cvi_int)
next_state = `SC_CVI;
end
default: begin
if(sof_cvi_int & ~sof_cvo_int)
next_state = `SC_CVI;
else if(~sof_cvi_int & sof_cvo_int)
next_state = `SC_CVO;
end
endcase
end
alt_vipitc131_common_frame_counter frame_counter(
.rst(rst),
.clk(clk),
.sclr(sclr_frame_counter),
.enable(enable),
.hd_sdn(~serial_output),
.h_total(h_total_minus_one),
.v_total({13{1'b1}}),
.h_reset(14'd0),
.v_reset(13'd0),
.h_count(h_count),
.v_count(v_count));
defparam frame_counter.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
frame_counter.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
frame_counter.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_NUMBER_OF_COLOUR_PLANES,
frame_counter.TOTALS_MINUS_ONE = 1;
endmodule | 5 |
6,583 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_common_avalon_mm_master.v | 116,866,011 | alt_vipvfr131_common_avalon_mm_master.v | v | 129 | 88 | [] | [] | [] | null | line:1 column:1: Illegal character '\x00' | null | 1: b"%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_common_avalon_mm_master.v:72: Cannot find file containing module: 'alt_vipvfr131_common_avalon_mm_bursting_master_fifo'\nalt_vipvfr131_common_avalon_mm_bursting_master_fifo\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_common_avalon_mm_bursting_master_fifo\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.v\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.sv\n alt_vipvfr131_common_avalon_mm_bursting_master_fifo\n alt_vipvfr131_common_avalon_mm_bursting_master_fifo.v\n alt_vipvfr131_common_avalon_mm_bursting_master_fifo.sv\n obj_dir/alt_vipvfr131_common_avalon_mm_bursting_master_fifo\n obj_dir/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.v\n obj_dir/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.sv\n%Error: Exiting due to 1 error(s)\n" | 7,607 | module | module alt_vipvfr131_common_avalon_mm_master
( clock,
reset,
av_clock,
av_reset,
av_address,
av_burstcount,
av_writedata,
av_readdata,
av_write,
av_read,
av_readdatavalid,
av_waitrequest,
addr,
command,
is_burst,
is_write_not_read,
burst_length,
writedata,
write,
readdata,
read,
stall);
parameter ADDR_WIDTH = 16;
parameter DATA_WIDTH = 16;
parameter MAX_BURST_LENGTH_REQUIREDWIDTH = 11;
parameter READ_USED = 1;
parameter WRITE_USED = 1;
parameter READ_FIFO_DEPTH = 8;
parameter WRITE_FIFO_DEPTH = 8;
parameter COMMAND_FIFO_DEPTH = 8;
parameter WRITE_TARGET_BURST_SIZE = 5;
parameter READ_TARGET_BURST_SIZE = 5;
parameter CLOCKS_ARE_SAME = 1;
parameter BURST_WIDTH = 6;
input clock;
input reset;
input av_clock;
input av_reset;
output [ADDR_WIDTH-1 : 0] av_address;
output [BURST_WIDTH-1 : 0] av_burstcount;
output [DATA_WIDTH-1 : 0] av_writedata;
input [DATA_WIDTH-1 : 0] av_readdata;
output av_write;
output av_read;
input av_readdatavalid;
input av_waitrequest;
input [ADDR_WIDTH-1 : 0] addr;
input command;
input is_burst;
input is_write_not_read;
input [MAX_BURST_LENGTH_REQUIREDWIDTH-1 : 0] burst_length;
input [DATA_WIDTH-1 : 0] writedata;
input write;
output [DATA_WIDTH-1 : 0] readdata;
input read;
output stall;
alt_vipvfr131_common_avalon_mm_bursting_master_fifo
#(.ADDR_WIDTH (ADDR_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.READ_USED (READ_USED),
.WRITE_USED (WRITE_USED),
.CMD_FIFO_DEPTH (COMMAND_FIFO_DEPTH),
.RDATA_FIFO_DEPTH (READ_FIFO_DEPTH),
.WDATA_FIFO_DEPTH (WRITE_FIFO_DEPTH),
.WDATA_TARGET_BURST_SIZE (WRITE_TARGET_BURST_SIZE),
.RDATA_TARGET_BURST_SIZE (READ_TARGET_BURST_SIZE),
.CLOCKS_ARE_SYNC (CLOCKS_ARE_SAME),
.BYTEENABLE_USED (0),
.LEN_BE_WIDTH (MAX_BURST_LENGTH_REQUIREDWIDTH),
.BURST_WIDTH (BURST_WIDTH),
.INTERRUPT_USED (0),
.INTERRUPT_WIDTH (8))
fu_inst
( .clock (clock),
.reset (reset),
.ena (!stall),
.ready (),
.stall (stall),
.addr (addr),
.write (is_write_not_read),
.burst (is_burst),
.len_be (burst_length),
.cenable (1'b1),
.cenable_en (command),
.wdata (writedata),
.wenable (1'b1),
.wenable_en (write),
.rdata (readdata),
.renable (1'b1),
.renable_en (read),
.activeirqs (),
.av_address (av_address),
.av_burstcount (av_burstcount),
.av_writedata (av_writedata),
.av_byteenable (),
.av_write (av_write),
.av_read (av_read),
.av_clock (av_clock),
.av_reset (av_reset),
.av_readdata (av_readdata),
.av_readdatavalid (av_readdatavalid),
.av_waitrequest (av_waitrequest),
.av_interrupt (8'd0));
endmodule | module alt_vipvfr131_common_avalon_mm_master
( clock,
reset,
av_clock,
av_reset,
av_address,
av_burstcount,
av_writedata,
av_readdata,
av_write,
av_read,
av_readdatavalid,
av_waitrequest,
addr,
command,
is_burst,
is_write_not_read,
burst_length,
writedata,
write,
readdata,
read,
stall); |
parameter ADDR_WIDTH = 16;
parameter DATA_WIDTH = 16;
parameter MAX_BURST_LENGTH_REQUIREDWIDTH = 11;
parameter READ_USED = 1;
parameter WRITE_USED = 1;
parameter READ_FIFO_DEPTH = 8;
parameter WRITE_FIFO_DEPTH = 8;
parameter COMMAND_FIFO_DEPTH = 8;
parameter WRITE_TARGET_BURST_SIZE = 5;
parameter READ_TARGET_BURST_SIZE = 5;
parameter CLOCKS_ARE_SAME = 1;
parameter BURST_WIDTH = 6;
input clock;
input reset;
input av_clock;
input av_reset;
output [ADDR_WIDTH-1 : 0] av_address;
output [BURST_WIDTH-1 : 0] av_burstcount;
output [DATA_WIDTH-1 : 0] av_writedata;
input [DATA_WIDTH-1 : 0] av_readdata;
output av_write;
output av_read;
input av_readdatavalid;
input av_waitrequest;
input [ADDR_WIDTH-1 : 0] addr;
input command;
input is_burst;
input is_write_not_read;
input [MAX_BURST_LENGTH_REQUIREDWIDTH-1 : 0] burst_length;
input [DATA_WIDTH-1 : 0] writedata;
input write;
output [DATA_WIDTH-1 : 0] readdata;
input read;
output stall;
alt_vipvfr131_common_avalon_mm_bursting_master_fifo
#(.ADDR_WIDTH (ADDR_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.READ_USED (READ_USED),
.WRITE_USED (WRITE_USED),
.CMD_FIFO_DEPTH (COMMAND_FIFO_DEPTH),
.RDATA_FIFO_DEPTH (READ_FIFO_DEPTH),
.WDATA_FIFO_DEPTH (WRITE_FIFO_DEPTH),
.WDATA_TARGET_BURST_SIZE (WRITE_TARGET_BURST_SIZE),
.RDATA_TARGET_BURST_SIZE (READ_TARGET_BURST_SIZE),
.CLOCKS_ARE_SYNC (CLOCKS_ARE_SAME),
.BYTEENABLE_USED (0),
.LEN_BE_WIDTH (MAX_BURST_LENGTH_REQUIREDWIDTH),
.BURST_WIDTH (BURST_WIDTH),
.INTERRUPT_USED (0),
.INTERRUPT_WIDTH (8))
fu_inst
( .clock (clock),
.reset (reset),
.ena (!stall),
.ready (),
.stall (stall),
.addr (addr),
.write (is_write_not_read),
.burst (is_burst),
.len_be (burst_length),
.cenable (1'b1),
.cenable_en (command),
.wdata (writedata),
.wenable (1'b1),
.wenable_en (write),
.rdata (readdata),
.renable (1'b1),
.renable_en (read),
.activeirqs (),
.av_address (av_address),
.av_burstcount (av_burstcount),
.av_writedata (av_writedata),
.av_byteenable (),
.av_write (av_write),
.av_read (av_read),
.av_clock (av_clock),
.av_reset (av_reset),
.av_readdata (av_readdata),
.av_readdatavalid (av_readdatavalid),
.av_waitrequest (av_waitrequest),
.av_interrupt (8'd0));
endmodule | 5 |
6,586 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_common_unpack_data.v | 116,866,011 | alt_vipvfr131_common_unpack_data.v | v | 83 | 68 | [] | [] | [] | [(2, 79)] | null | null | 1: b"%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_common_unpack_data.v:54: Cannot find file containing module: 'alt_vipvfr131_common_pulling_width_adapter'\nalt_vipvfr131_common_pulling_width_adapter\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_common_pulling_width_adapter\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_common_pulling_width_adapter.v\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_common_pulling_width_adapter.sv\n alt_vipvfr131_common_pulling_width_adapter\n alt_vipvfr131_common_pulling_width_adapter.v\n alt_vipvfr131_common_pulling_width_adapter.sv\n obj_dir/alt_vipvfr131_common_pulling_width_adapter\n obj_dir/alt_vipvfr131_common_pulling_width_adapter.v\n obj_dir/alt_vipvfr131_common_pulling_width_adapter.sv\n%Error: Exiting due to 1 error(s)\n" | 7,610 | module | module alt_vipvfr131_common_unpack_data
( clock,
reset,
data_in,
read,
stall_in,
data_out,
write,
stall_out,
clear);
parameter DATA_WIDTH_IN = 128;
parameter DATA_WIDTH_OUT = 24;
input clock;
input reset;
input [DATA_WIDTH_IN - 1 : 0] data_in;
output read;
input stall_in;
input stall_out;
output reg write;
output [DATA_WIDTH_OUT - 1:0] data_out;
input clear;
wire need_input;
wire ena;
assign ena = ~stall_in;
assign read = need_input;
alt_vipvfr131_common_pulling_width_adapter
#(.IN_WIDTH (DATA_WIDTH_IN),
.OUT_WIDTH (DATA_WIDTH_OUT)
)
fu_inst
( .clock (clock),
.reset (reset),
.input_data (data_in),
.need_input (need_input),
.output_data (data_out),
.pull (1'b1),
.pull_en (~stall_out),
.discard (1'b1),
.discard_en (clear),
.ena (ena)
);
always @(posedge clock or posedge reset)
if (reset) begin
write <= 1'b0;
end
else if (~stall_out) begin
write <= ena;
end
endmodule | module alt_vipvfr131_common_unpack_data
( clock,
reset,
data_in,
read,
stall_in,
data_out,
write,
stall_out,
clear); |
parameter DATA_WIDTH_IN = 128;
parameter DATA_WIDTH_OUT = 24;
input clock;
input reset;
input [DATA_WIDTH_IN - 1 : 0] data_in;
output read;
input stall_in;
input stall_out;
output reg write;
output [DATA_WIDTH_OUT - 1:0] data_out;
input clear;
wire need_input;
wire ena;
assign ena = ~stall_in;
assign read = need_input;
alt_vipvfr131_common_pulling_width_adapter
#(.IN_WIDTH (DATA_WIDTH_IN),
.OUT_WIDTH (DATA_WIDTH_OUT)
)
fu_inst
( .clock (clock),
.reset (reset),
.input_data (data_in),
.need_input (need_input),
.output_data (data_out),
.pull (1'b1),
.pull_en (~stall_out),
.discard (1'b1),
.discard_en (clear),
.ena (ena)
);
always @(posedge clock or posedge reset)
if (reset) begin
write <= 1'b0;
end
else if (~stall_out) begin
write <= ena;
end
endmodule | 5 |
6,587 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_prc_core.v | 116,866,011 | alt_vipvfr131_prc_core.v | v | 342 | 165 | [] | [] | [] | [(3, 338)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_prc_core.v:186: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'packet_type\' generates 4 bits.\n : ... In instance alt_vipvfr131_prc_core\n pre_data_out <= packet_type;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 7,612 | module | module alt_vipvfr131_prc_core
(
clock,
reset,
stall,
ena,
read,
data,
discard_remaining_data_of_read_word,
cmd_length_of_burst,
cmd,
cmd_addr,
ready_out,
valid_out,
data_out,
sop_out,
eop_out,
enable,
clear_enable,
stopped,
complete,
packet_addr,
packet_type,
packet_samples,
packet_words
);
parameter BITS_PER_SYMBOL = 8;
parameter SYMBOLS_PER_BEAT = 3;
parameter BURST_LENGTH_REQUIREDWIDTH = 7;
parameter PACKET_SAMPLES_REQUIREDWIDTH = 32;
localparam ADDR_WIDTH = 32;
localparam READ_LATENCY = 3;
input clock;
input reset;
output stall;
input ena;
output reg read;
input [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] data;
output reg discard_remaining_data_of_read_word;
output reg cmd;
output reg [BURST_LENGTH_REQUIREDWIDTH-1:0] cmd_length_of_burst;
output reg [ADDR_WIDTH-1:0] cmd_addr;
input ready_out;
output valid_out;
output [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] data_out;
output sop_out;
output eop_out;
input enable;
output reg clear_enable;
output stopped;
output reg complete;
input [ADDR_WIDTH-1:0] packet_addr;
input [3:0] packet_type;
input [PACKET_SAMPLES_REQUIREDWIDTH-1:0] packet_samples;
input [BURST_LENGTH_REQUIREDWIDTH-1:0] packet_words;
reg [READ_LATENCY-1:0] input_valid_shift_reg;
reg [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1 : 0] data_out_d1;
reg sop_out_d1;
reg eop_out_d1;
reg [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] pre_data_out;
reg internal_output_is_valid;
reg pre_sop_out;
reg pre_eop_out;
reg [PACKET_SAMPLES_REQUIREDWIDTH-1:0] packet_samples_reg;
reg [PACKET_SAMPLES_REQUIREDWIDTH-1:0] reads_issued;
wire reads_complete;
assign reads_complete = (reads_issued == packet_samples_reg-1);
localparam IDLE = 0;
localparam WAITING = 1;
localparam RUNNING = 2;
localparam ENDING = 3;
reg [1:0] state;
reg status;
integer i;
always @(posedge clock or posedge reset)
if (reset) begin
state <= IDLE;
status <= 1'b0;
clear_enable <= 1'b1;
cmd <= 1'b0;
internal_output_is_valid <= 1'b0;
pre_sop_out <= 1'b0;
pre_eop_out <= 1'b0;
complete <= 1'b0;
input_valid_shift_reg <= {READ_LATENCY{1'b0}};
discard_remaining_data_of_read_word <= 1'b0;
read <= 1'b0;
reads_issued <= {PACKET_SAMPLES_REQUIREDWIDTH{1'b0}};
end
else begin
reads_issued <= read & ena & ~reads_complete ? reads_issued + 1'b1 : reads_issued;
if(ena) begin
input_valid_shift_reg[READ_LATENCY-1] <= (read);
for(i=0;i<READ_LATENCY-1;i=i+1) begin
input_valid_shift_reg[i] <= input_valid_shift_reg[i+1];
end
end
case (state)
IDLE : begin
reads_issued <= {PACKET_SAMPLES_REQUIREDWIDTH{1'b0}};
if( ena & discard_remaining_data_of_read_word) begin
discard_remaining_data_of_read_word <= 0;
end
clear_enable <= 1'b0;
if (pre_eop_out & ena) begin
pre_eop_out <= 1'b0;
end
complete <= 1'b0;
if (enable & !discard_remaining_data_of_read_word) begin
clear_enable <= 1'b1;
status <= 1'b1;
cmd <= 1'b1;
cmd_addr <= packet_addr;
cmd_length_of_burst <= packet_words;
packet_samples_reg <= packet_samples;
internal_output_is_valid <= 1'b1;
pre_sop_out <= 1'b1;
pre_data_out <= packet_type;
state <= WAITING;
end else begin
status <= 1'b0;
state <= IDLE;
cmd <= 1'b0;
internal_output_is_valid <= 1'b0;
pre_sop_out <= 1'b0;
end
end
WAITING : begin
clear_enable <= 1'b0;
if (cmd & ena) begin
cmd <= 1'b0;
end
if(ena) begin
internal_output_is_valid <= 1'b0;
pre_sop_out <= 1'b0;
state <= RUNNING;
end
end
RUNNING : begin
if(ena) begin
internal_output_is_valid <= input_valid_shift_reg[0];
end
if ((cmd & ena) | !cmd & !reads_complete) begin
cmd <= 1'b0;
read <= 1'b1;
end
if (reads_complete & ena) begin
read <= 1'b0;
end
pre_data_out <= ena ? data : pre_data_out;
if(input_valid_shift_reg==1 & reads_complete & ena) begin
discard_remaining_data_of_read_word <= 1;
pre_eop_out <= 1'b1;
state <= ENDING;
end else begin
state <= RUNNING;
pre_eop_out <= 1'b0;
end
end
ENDING : begin
internal_output_is_valid <= 1'b1;
if( ena & discard_remaining_data_of_read_word) begin
discard_remaining_data_of_read_word <= 0;
end
if(ena) begin
status <= 1'b0;
complete <= 1'b1;
pre_eop_out <= 1'b0;
state <= IDLE;
internal_output_is_valid <= 1'b0;
end
end
endcase
end
assign stopped = ~status;
assign stall = !ready_out;
assign valid_out = internal_output_is_valid & ena;
assign data_out = valid_out ? pre_data_out : data_out_d1;
assign eop_out = valid_out ? pre_eop_out : eop_out_d1;
assign sop_out = valid_out ? pre_sop_out : sop_out_d1;
always @(posedge clock or posedge reset)
if (reset) begin
data_out_d1 <= {(BITS_PER_SYMBOL * SYMBOLS_PER_BEAT){1'b0}};
sop_out_d1 <= 1'b0;
eop_out_d1 <= 1'b0;
end
else begin
data_out_d1 <= data_out;
sop_out_d1 <= sop_out;
eop_out_d1 <= eop_out;
end
endmodule | module alt_vipvfr131_prc_core
(
clock,
reset,
stall,
ena,
read,
data,
discard_remaining_data_of_read_word,
cmd_length_of_burst,
cmd,
cmd_addr,
ready_out,
valid_out,
data_out,
sop_out,
eop_out,
enable,
clear_enable,
stopped,
complete,
packet_addr,
packet_type,
packet_samples,
packet_words
); |
parameter BITS_PER_SYMBOL = 8;
parameter SYMBOLS_PER_BEAT = 3;
parameter BURST_LENGTH_REQUIREDWIDTH = 7;
parameter PACKET_SAMPLES_REQUIREDWIDTH = 32;
localparam ADDR_WIDTH = 32;
localparam READ_LATENCY = 3;
input clock;
input reset;
output stall;
input ena;
output reg read;
input [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] data;
output reg discard_remaining_data_of_read_word;
output reg cmd;
output reg [BURST_LENGTH_REQUIREDWIDTH-1:0] cmd_length_of_burst;
output reg [ADDR_WIDTH-1:0] cmd_addr;
input ready_out;
output valid_out;
output [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] data_out;
output sop_out;
output eop_out;
input enable;
output reg clear_enable;
output stopped;
output reg complete;
input [ADDR_WIDTH-1:0] packet_addr;
input [3:0] packet_type;
input [PACKET_SAMPLES_REQUIREDWIDTH-1:0] packet_samples;
input [BURST_LENGTH_REQUIREDWIDTH-1:0] packet_words;
reg [READ_LATENCY-1:0] input_valid_shift_reg;
reg [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1 : 0] data_out_d1;
reg sop_out_d1;
reg eop_out_d1;
reg [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] pre_data_out;
reg internal_output_is_valid;
reg pre_sop_out;
reg pre_eop_out;
reg [PACKET_SAMPLES_REQUIREDWIDTH-1:0] packet_samples_reg;
reg [PACKET_SAMPLES_REQUIREDWIDTH-1:0] reads_issued;
wire reads_complete;
assign reads_complete = (reads_issued == packet_samples_reg-1);
localparam IDLE = 0;
localparam WAITING = 1;
localparam RUNNING = 2;
localparam ENDING = 3;
reg [1:0] state;
reg status;
integer i;
always @(posedge clock or posedge reset)
if (reset) begin
state <= IDLE;
status <= 1'b0;
clear_enable <= 1'b1;
cmd <= 1'b0;
internal_output_is_valid <= 1'b0;
pre_sop_out <= 1'b0;
pre_eop_out <= 1'b0;
complete <= 1'b0;
input_valid_shift_reg <= {READ_LATENCY{1'b0}};
discard_remaining_data_of_read_word <= 1'b0;
read <= 1'b0;
reads_issued <= {PACKET_SAMPLES_REQUIREDWIDTH{1'b0}};
end
else begin
reads_issued <= read & ena & ~reads_complete ? reads_issued + 1'b1 : reads_issued;
if(ena) begin
input_valid_shift_reg[READ_LATENCY-1] <= (read);
for(i=0;i<READ_LATENCY-1;i=i+1) begin
input_valid_shift_reg[i] <= input_valid_shift_reg[i+1];
end
end
case (state)
IDLE : begin
reads_issued <= {PACKET_SAMPLES_REQUIREDWIDTH{1'b0}};
if( ena & discard_remaining_data_of_read_word) begin
discard_remaining_data_of_read_word <= 0;
end
clear_enable <= 1'b0;
if (pre_eop_out & ena) begin
pre_eop_out <= 1'b0;
end
complete <= 1'b0;
if (enable & !discard_remaining_data_of_read_word) begin
clear_enable <= 1'b1;
status <= 1'b1;
cmd <= 1'b1;
cmd_addr <= packet_addr;
cmd_length_of_burst <= packet_words;
packet_samples_reg <= packet_samples;
internal_output_is_valid <= 1'b1;
pre_sop_out <= 1'b1;
pre_data_out <= packet_type;
state <= WAITING;
end else begin
status <= 1'b0;
state <= IDLE;
cmd <= 1'b0;
internal_output_is_valid <= 1'b0;
pre_sop_out <= 1'b0;
end
end
WAITING : begin
clear_enable <= 1'b0;
if (cmd & ena) begin
cmd <= 1'b0;
end
if(ena) begin
internal_output_is_valid <= 1'b0;
pre_sop_out <= 1'b0;
state <= RUNNING;
end
end
RUNNING : begin
if(ena) begin
internal_output_is_valid <= input_valid_shift_reg[0];
end
if ((cmd & ena) | !cmd & !reads_complete) begin
cmd <= 1'b0;
read <= 1'b1;
end
if (reads_complete & ena) begin
read <= 1'b0;
end
pre_data_out <= ena ? data : pre_data_out;
if(input_valid_shift_reg==1 & reads_complete & ena) begin
discard_remaining_data_of_read_word <= 1;
pre_eop_out <= 1'b1;
state <= ENDING;
end else begin
state <= RUNNING;
pre_eop_out <= 1'b0;
end
end
ENDING : begin
internal_output_is_valid <= 1'b1;
if( ena & discard_remaining_data_of_read_word) begin
discard_remaining_data_of_read_word <= 0;
end
if(ena) begin
status <= 1'b0;
complete <= 1'b1;
pre_eop_out <= 1'b0;
state <= IDLE;
internal_output_is_valid <= 1'b0;
end
end
endcase
end
assign stopped = ~status;
assign stall = !ready_out;
assign valid_out = internal_output_is_valid & ena;
assign data_out = valid_out ? pre_data_out : data_out_d1;
assign eop_out = valid_out ? pre_eop_out : eop_out_d1;
assign sop_out = valid_out ? pre_sop_out : sop_out_d1;
always @(posedge clock or posedge reset)
if (reset) begin
data_out_d1 <= {(BITS_PER_SYMBOL * SYMBOLS_PER_BEAT){1'b0}};
sop_out_d1 <= 1'b0;
eop_out_d1 <= 1'b0;
end
else begin
data_out_d1 <= data_out;
sop_out_d1 <= sop_out;
eop_out_d1 <= eop_out;
end
endmodule | 5 |
6,588 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_prc_read_master.v | 116,866,011 | alt_vipvfr131_prc_read_master.v | v | 184 | 80 | [] | [] | [] | null | line:47: before: ")" | null | 1: b"%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_prc_read_master.v:47: syntax error, unexpected ')', expecting '['\n );\n ^\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_prc_read_master.v:60: syntax error, unexpected input\ninput clock;\n^~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_prc_read_master.v:100: syntax error, unexpected IDENTIFIER\nalt_vipvfr131_common_avalon_mm_bursting_master_fifo\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 7,613 | module | module alt_vipvfr131_prc_read_master
( clock,
reset,
ena,
stall,
cmd_addr,
cmd_write_instead_of_read,
cmd_burst_instead_of_single_op,
cmd_length_of_burst,
cmd,
read_data,
read,
discard_remaining_data_of_read_word,
av_address,
av_burstcount,
av_writedata,
av_write,
av_read,
av_clock,
av_reset,
av_readdata,
av_readdatavalid,
av_waitrequest,
);
parameter ADDR_WIDTH = 16;
parameter DATA_WIDTH = 16;
parameter MAX_BURST_LENGTH_REQUIREDWIDTH = 11;
parameter READ_USED = 1;
parameter READ_FIFO_DEPTH = 8;
parameter COMMAND_FIFO_DEPTH = 8;
parameter READ_TARGET_BURST_SIZE = 5;
parameter CLOCKS_ARE_SAME = 1;
parameter BURST_WIDTH = 6;
parameter UNPACKED_WIDTH = 16;
input clock;
input reset;
input ena;
output stall;
input [ADDR_WIDTH-1 : 0] cmd_addr;
input cmd_write_instead_of_read;
input cmd_burst_instead_of_single_op;
input [MAX_BURST_LENGTH_REQUIREDWIDTH-1 : 0] cmd_length_of_burst;
input cmd;
output [UNPACKED_WIDTH-1 : 0] read_data;
input read;
input discard_remaining_data_of_read_word;
input av_clock;
input av_reset;
output [ADDR_WIDTH-1 : 0] av_address;
output [BURST_WIDTH-1 : 0] av_burstcount;
output [DATA_WIDTH-1 : 0] av_writedata;
input [DATA_WIDTH-1 : 0] av_readdata;
output av_write;
output av_read;
input av_readdatavalid;
input av_waitrequest;
wire read_FROM_width_adaptor_TO_master_fifo;
wire [DATA_WIDTH-1:0] readdata_FROM_master_fifo_TO_width_adaptor;
alt_vipvfr131_common_avalon_mm_bursting_master_fifo
#(.ADDR_WIDTH (ADDR_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.READ_USED (READ_USED),
.WRITE_USED (0),
.CMD_FIFO_DEPTH (COMMAND_FIFO_DEPTH),
.RDATA_FIFO_DEPTH (READ_FIFO_DEPTH),
.WDATA_FIFO_DEPTH (0),
.WDATA_TARGET_BURST_SIZE (0),
.RDATA_TARGET_BURST_SIZE (READ_TARGET_BURST_SIZE),
.CLOCKS_ARE_SYNC (CLOCKS_ARE_SAME),
.BYTEENABLE_USED (0),
.LEN_BE_WIDTH (MAX_BURST_LENGTH_REQUIREDWIDTH),
.BURST_WIDTH (BURST_WIDTH),
.INTERRUPT_USED (0),
.INTERRUPT_WIDTH (8))
master_fifo
( .clock (clock),
.reset (reset),
.ena (ena),
.ready (),
.stall (stall),
.addr (cmd_addr),
.write (cmd_write_instead_of_read),
.burst (cmd_burst_instead_of_single_op),
.len_be (cmd_length_of_burst),
.cenable (1'b1),
.cenable_en (cmd),
.wdata (),
.wenable (),
.wenable_en(),
.rdata (readdata_FROM_master_fifo_TO_width_adaptor),
.renable (1'b1),
.renable_en (read_FROM_width_adaptor_TO_master_fifo),
.activeirqs (),
.av_address (av_address),
.av_burstcount (av_burstcount),
.av_writedata (av_writedata),
.av_byteenable (),
.av_write (av_write),
.av_read (av_read),
.av_clock (av_clock),
.av_reset (av_reset),
.av_readdata (av_readdata),
.av_readdatavalid (av_readdatavalid),
.av_waitrequest (av_waitrequest),
.av_interrupt (8'd0)
);
alt_vipvfr131_common_pulling_width_adapter
#(.IN_WIDTH (DATA_WIDTH),
.OUT_WIDTH (UNPACKED_WIDTH)
)
width_adaptor
( .clock (clock),
.reset (reset),
.input_data (readdata_FROM_master_fifo_TO_width_adaptor),
.need_input (read_FROM_width_adaptor_TO_master_fifo),
.output_data (read_data),
.pull (1'b1),
.pull_en (read),
.discard (1'b1),
.discard_en (discard_remaining_data_of_read_word),
.ena (ena)
);
endmodule | module alt_vipvfr131_prc_read_master
( clock,
reset,
ena,
stall,
cmd_addr,
cmd_write_instead_of_read,
cmd_burst_instead_of_single_op,
cmd_length_of_burst,
cmd,
read_data,
read,
discard_remaining_data_of_read_word,
av_address,
av_burstcount,
av_writedata,
av_write,
av_read,
av_clock,
av_reset,
av_readdata,
av_readdatavalid,
av_waitrequest,
); |
parameter ADDR_WIDTH = 16;
parameter DATA_WIDTH = 16;
parameter MAX_BURST_LENGTH_REQUIREDWIDTH = 11;
parameter READ_USED = 1;
parameter READ_FIFO_DEPTH = 8;
parameter COMMAND_FIFO_DEPTH = 8;
parameter READ_TARGET_BURST_SIZE = 5;
parameter CLOCKS_ARE_SAME = 1;
parameter BURST_WIDTH = 6;
parameter UNPACKED_WIDTH = 16;
input clock;
input reset;
input ena;
output stall;
input [ADDR_WIDTH-1 : 0] cmd_addr;
input cmd_write_instead_of_read;
input cmd_burst_instead_of_single_op;
input [MAX_BURST_LENGTH_REQUIREDWIDTH-1 : 0] cmd_length_of_burst;
input cmd;
output [UNPACKED_WIDTH-1 : 0] read_data;
input read;
input discard_remaining_data_of_read_word;
input av_clock;
input av_reset;
output [ADDR_WIDTH-1 : 0] av_address;
output [BURST_WIDTH-1 : 0] av_burstcount;
output [DATA_WIDTH-1 : 0] av_writedata;
input [DATA_WIDTH-1 : 0] av_readdata;
output av_write;
output av_read;
input av_readdatavalid;
input av_waitrequest;
wire read_FROM_width_adaptor_TO_master_fifo;
wire [DATA_WIDTH-1:0] readdata_FROM_master_fifo_TO_width_adaptor;
alt_vipvfr131_common_avalon_mm_bursting_master_fifo
#(.ADDR_WIDTH (ADDR_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.READ_USED (READ_USED),
.WRITE_USED (0),
.CMD_FIFO_DEPTH (COMMAND_FIFO_DEPTH),
.RDATA_FIFO_DEPTH (READ_FIFO_DEPTH),
.WDATA_FIFO_DEPTH (0),
.WDATA_TARGET_BURST_SIZE (0),
.RDATA_TARGET_BURST_SIZE (READ_TARGET_BURST_SIZE),
.CLOCKS_ARE_SYNC (CLOCKS_ARE_SAME),
.BYTEENABLE_USED (0),
.LEN_BE_WIDTH (MAX_BURST_LENGTH_REQUIREDWIDTH),
.BURST_WIDTH (BURST_WIDTH),
.INTERRUPT_USED (0),
.INTERRUPT_WIDTH (8))
master_fifo
( .clock (clock),
.reset (reset),
.ena (ena),
.ready (),
.stall (stall),
.addr (cmd_addr),
.write (cmd_write_instead_of_read),
.burst (cmd_burst_instead_of_single_op),
.len_be (cmd_length_of_burst),
.cenable (1'b1),
.cenable_en (cmd),
.wdata (),
.wenable (),
.wenable_en(),
.rdata (readdata_FROM_master_fifo_TO_width_adaptor),
.renable (1'b1),
.renable_en (read_FROM_width_adaptor_TO_master_fifo),
.activeirqs (),
.av_address (av_address),
.av_burstcount (av_burstcount),
.av_writedata (av_writedata),
.av_byteenable (),
.av_write (av_write),
.av_read (av_read),
.av_clock (av_clock),
.av_reset (av_reset),
.av_readdata (av_readdata),
.av_readdatavalid (av_readdatavalid),
.av_waitrequest (av_waitrequest),
.av_interrupt (8'd0)
);
alt_vipvfr131_common_pulling_width_adapter
#(.IN_WIDTH (DATA_WIDTH),
.OUT_WIDTH (UNPACKED_WIDTH)
)
width_adaptor
( .clock (clock),
.reset (reset),
.input_data (readdata_FROM_master_fifo_TO_width_adaptor),
.need_input (read_FROM_width_adaptor_TO_master_fifo),
.output_data (read_data),
.pull (1'b1),
.pull_en (read),
.discard (1'b1),
.discard_en (discard_remaining_data_of_read_word),
.ena (ena)
);
endmodule | 5 |
6,589 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_vfr.v | 116,866,011 | alt_vipvfr131_vfr.v | v | 368 | 181 | [] | [] | [] | [(1, 359)] | null | null | 1: b"%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_vfr.v:110: Cannot find file containing module: 'alt_vipvfr131_prc'\n alt_vipvfr131_prc #(\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_prc\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_prc.v\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_prc.sv\n alt_vipvfr131_prc\n alt_vipvfr131_prc.v\n alt_vipvfr131_prc.sv\n obj_dir/alt_vipvfr131_prc\n obj_dir/alt_vipvfr131_prc.v\n obj_dir/alt_vipvfr131_prc.sv\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_vfr.v:185: Cannot find file containing module: 'alt_vipvfr131_vfr_controller'\nalt_vipvfr131_vfr_controller #(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_vfr.v:240: Cannot find file containing module: 'alt_vipvfr131_common_avalon_mm_slave'\nalt_vipvfr131_common_avalon_mm_slave\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_vfr.v:308: Cannot find file containing module: 'alt_vipvfr131_vfr_control_packet_encoder'\nalt_vipvfr131_vfr_control_packet_encoder\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_vfr.v:339: Cannot find file containing module: 'alt_vipvfr131_common_stream_output'\n alt_vipvfr131_common_stream_output\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 7,614 | module | module alt_vipvfr131_vfr
( clock,
reset,
master_clock,
master_reset,
master_address,
master_burstcount,
master_readdata,
master_read,
master_readdatavalid,
master_waitrequest,
slave_address,
slave_write,
slave_writedata,
slave_read,
slave_readdata,
slave_irq,
dout_ready,
dout_valid,
dout_data,
dout_startofpacket,
dout_endofpacket);
parameter BITS_PER_PIXEL_PER_COLOR_PLANE = 8;
parameter NUMBER_OF_CHANNELS_IN_PARALLEL = 3;
parameter NUMBER_OF_CHANNELS_IN_SEQUENCE = 1;
parameter MAX_IMAGE_WIDTH = 1920;
parameter MAX_IMAGE_HEIGHT = 1080;
parameter MEM_PORT_WIDTH = 256;
parameter RMASTER_FIFO_DEPTH = 128;
parameter RMASTER_BURST_TARGET = 64;
parameter CLOCKS_ARE_SEPARATE = 1;
function integer alt_vipfunc_required_width;
input [511:0] value;
integer i;
begin
alt_vipfunc_required_width = 512;
for (i=512; i>0; i=i-1) begin
if (2**i>value)
alt_vipfunc_required_width = i;
end
end
endfunction
localparam DATA_WIDTH = BITS_PER_PIXEL_PER_COLOR_PLANE * NUMBER_OF_CHANNELS_IN_PARALLEL;
localparam MM_ADDR_REQUIREDWIDTH = 32;
localparam MM_MASTER_BURST_REQUIREDWIDTH = alt_vipfunc_required_width(RMASTER_BURST_TARGET);
localparam SLAVE_ADDRESS_REQUIREDWIDTH = 5;
localparam SLAVE_DATA_REQUIREDWIDTH = 32;
input clock;
input reset;
input master_clock;
input master_reset;
output [MM_ADDR_REQUIREDWIDTH-1 : 0] master_address;
output [MM_MASTER_BURST_REQUIREDWIDTH-1 : 0] master_burstcount;
input [MEM_PORT_WIDTH-1 : 0] master_readdata;
output master_read;
input master_readdatavalid;
input master_waitrequest;
input [SLAVE_ADDRESS_REQUIREDWIDTH-1:0] slave_address;
input slave_read;
output [SLAVE_DATA_REQUIREDWIDTH-1:0] slave_readdata;
input slave_write;
input [SLAVE_DATA_REQUIREDWIDTH-1:0] slave_writedata;
output slave_irq;
input dout_ready;
output dout_valid;
output dout_startofpacket;
output dout_endofpacket;
output [DATA_WIDTH-1:0] dout_data;
wire ready_FROM_encoder_TO_prc;
wire valid_FROM_prc_TO_encoder;
wire [DATA_WIDTH-1:0] data_FROM_prc_TO_encoder;
wire sop_FROM_prc_TO_encoder;
wire eop_FROM_prc_TO_encoder;
localparam INTERNAL_MASTER_DATA_REQUIREDWIDTH = 32;
localparam INTERNAL_MASTER_ADDRESS_REQUIREDWIDTH = 32;
wire [INTERNAL_MASTER_ADDRESS_REQUIREDWIDTH-1:0] master_address_FROM_controller_TO_prc;
wire master_write_FROM_controller_TO_prc;
wire [INTERNAL_MASTER_DATA_REQUIREDWIDTH-1:0] master_writedata_FROM_controller_TO_prc;
wire slave_irq_FROM_prc_TO_controller;
alt_vipvfr131_prc #(
.BPS(BITS_PER_PIXEL_PER_COLOR_PLANE),
.CHANNELS_IN_PAR(NUMBER_OF_CHANNELS_IN_PARALLEL),
.CHANNELS_IN_SEQ(NUMBER_OF_CHANNELS_IN_SEQUENCE),
.MAX_WIDTH(MAX_IMAGE_WIDTH),
.MAX_HEIGHT(MAX_IMAGE_HEIGHT),
.MEM_PORT_WIDTH(MEM_PORT_WIDTH),
.RMASTER_FIFO_DEPTH(RMASTER_FIFO_DEPTH),
.RMASTER_BURST_TARGET(RMASTER_BURST_TARGET),
.CLOCKS_ARE_SEPARATE(CLOCKS_ARE_SEPARATE),
.READY_LATENCY(0))
prc(
.clock(clock),
.reset(reset),
.master_av_clock(master_clock),
.master_av_reset(master_reset),
.master_av_address(master_address),
.master_av_burstcount(master_burstcount),
.master_av_readdata(master_readdata),
.master_av_read(master_read),
.master_av_readdatavalid(master_readdatavalid),
.master_av_waitrequest(master_waitrequest),
.dout_valid(valid_FROM_prc_TO_encoder),
.dout_ready(ready_FROM_encoder_TO_prc),
.dout_data(data_FROM_prc_TO_encoder),
.dout_startofpacket(sop_FROM_prc_TO_encoder),
.dout_endofpacket(eop_FROM_prc_TO_encoder),
.control_av_address(master_address_FROM_controller_TO_prc),
.control_av_write(master_write_FROM_controller_TO_prc),
.control_av_writedata(master_writedata_FROM_controller_TO_prc),
.control_av_read(),
.control_av_readdata(),
.control_av_irq(slave_irq_FROM_prc_TO_controller)
);
localparam CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH = 16;
localparam CONTROL_PACKET_INTERLACED_REQUIREDWIDTH = 4;
wire [CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1 : 0 ] width_FROM_controller_TO_encoder;
wire [CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1 : 0 ] height_FROM_controller_TO_encoder;
wire [CONTROL_PACKET_INTERLACED_REQUIREDWIDTH-1 : 0 ] interlaced_FROM_controller_TO_encoder;
wire do_control_packet_FROM_controller_TO_encoder;
wire go_bit_FROM_slave_TO_controller;
wire status_bit_zero_FROM_controller_TO_slave;
wire irq_FROM_controller_TO_slave;
wire next_bank_FROM_slave_TO_controller;
wire [CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1 : 0 ] ctrl_packet_width_bank0_bits_FROM_slave_TO_controller;
wire [CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1 : 0 ] ctrl_packet_height_bank0_bits_FROM_slave_TO_controller;
wire [CONTROL_PACKET_INTERLACED_REQUIREDWIDTH-1 : 0 ] ctrl_packet_interlaced_bank0_bits_FROM_slave_TO_controller;
wire [SLAVE_DATA_REQUIREDWIDTH-1 : 0] vid_packet_base_address_bank0_bits_FROM_slave_TO_controller;
wire [SLAVE_DATA_REQUIREDWIDTH-1 : 0] vid_packet_samples_bank0_bits_FROM_slave_TO_controller;
wire [SLAVE_DATA_REQUIREDWIDTH-1 : 0] vid_packet_words_bank0_bits_FROM_slave_TO_controller;
wire [CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1 : 0 ] ctrl_packet_width_bank1_bits_FROM_slave_TO_controller;
wire [CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1 : 0 ] ctrl_packet_height_bank1_bits_FROM_slave_TO_controller;
wire [CONTROL_PACKET_INTERLACED_REQUIREDWIDTH-1 : 0 ] ctrl_packet_interlaced_bank1_bits_FROM_slave_TO_controller;
wire [SLAVE_DATA_REQUIREDWIDTH-1 : 0] vid_packet_base_address_bank1_bits_FROM_slave_TO_controller;
wire [SLAVE_DATA_REQUIREDWIDTH-1 : 0] vid_packet_samples_bank1_bits_FROM_slave_TO_controller;
wire [SLAVE_DATA_REQUIREDWIDTH-1 : 0] vid_packet_words_bank1_bits_FROM_slave_TO_controller;
alt_vipvfr131_vfr_controller #(
.CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH(CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH),
.CONTROL_PACKET_INTERLACED_REQUIREDWIDTH(CONTROL_PACKET_INTERLACED_REQUIREDWIDTH),
.PACKET_ADDRESS_WIDTH(32),
.PACKET_SAMPLES_WIDTH(32),
.PACKET_WORDS_WIDTH(32))
controller(
.clock(clock),
.reset(reset),
.master_address(master_address_FROM_controller_TO_prc),
.master_write(master_write_FROM_controller_TO_prc),
.master_writedata(master_writedata_FROM_controller_TO_prc),
.master_interrupt_recieve(slave_irq_FROM_prc_TO_controller),
.go_bit(go_bit_FROM_slave_TO_controller),
.running(status_bit_zero_FROM_controller_TO_slave),
.frame_complete(irq_FROM_controller_TO_slave),
.next_bank(next_bank_FROM_slave_TO_controller),
.ctrl_packet_width_bank0(ctrl_packet_width_bank0_bits_FROM_slave_TO_controller),
.ctrl_packet_height_bank0(ctrl_packet_height_bank0_bits_FROM_slave_TO_controller),
.ctrl_packet_interlaced_bank0(ctrl_packet_interlaced_bank0_bits_FROM_slave_TO_controller),
.vid_packet_base_address_bank0(vid_packet_base_address_bank0_bits_FROM_slave_TO_controller),
.vid_packet_samples_bank0(vid_packet_samples_bank0_bits_FROM_slave_TO_controller),
.vid_packet_words_bank0(vid_packet_words_bank0_bits_FROM_slave_TO_controller),
.ctrl_packet_width_bank1(ctrl_packet_width_bank1_bits_FROM_slave_TO_controller),
.ctrl_packet_height_bank1(ctrl_packet_height_bank1_bits_FROM_slave_TO_controller),
.ctrl_packet_interlaced_bank1(ctrl_packet_interlaced_bank1_bits_FROM_slave_TO_controller),
.vid_packet_base_address_bank1(vid_packet_base_address_bank1_bits_FROM_slave_TO_controller),
.vid_packet_samples_bank1(vid_packet_samples_bank1_bits_FROM_slave_TO_controller),
.vid_packet_words_bank1(vid_packet_words_bank1_bits_FROM_slave_TO_controller),
.width_of_next_vid_packet(width_FROM_controller_TO_encoder),
.height_of_next_vid_packet(height_FROM_controller_TO_encoder),
.interlaced_of_next_vid_packet(interlaced_FROM_controller_TO_encoder),
.do_control_packet(do_control_packet_FROM_controller_TO_encoder)
);
localparam NO_REGISTERS = 18;
wire stopped;
wire enable;
wire clear_enable;
wire [NO_REGISTERS-1:0] triggers;
wire [(SLAVE_DATA_REQUIREDWIDTH * NO_REGISTERS)-1:0] registers;
wire [(SLAVE_DATA_REQUIREDWIDTH * NO_REGISTERS)-1:0] registers_in;
assign registers_in = {(SLAVE_DATA_REQUIREDWIDTH * NO_REGISTERS){1'b0}};
wire [NO_REGISTERS-1:0] registers_write;
assign registers_write = {NO_REGISTERS{1'b0}};
alt_vipvfr131_common_avalon_mm_slave
#(
.AV_ADDRESS_WIDTH (SLAVE_ADDRESS_REQUIREDWIDTH),
.AV_DATA_WIDTH (SLAVE_DATA_REQUIREDWIDTH),
.NO_OUTPUTS (1),
.NO_INTERRUPTS (1),
.NO_REGISTERS (NO_REGISTERS),
.ALLOW_INTERNAL_WRITE (0))
slave
(
.rst (reset),
.clk (clock),
.av_address (slave_address),
.av_read (slave_read),
.av_readdata (slave_readdata),
.av_write (slave_write),
.av_writedata (slave_writedata),
.av_irq (slave_irq),
.enable (go_bit_FROM_slave_TO_controller),
.clear_enable (1'b0),
.triggers (triggers),
.registers (registers),
.registers_in (registers_in),
.registers_write (registers_write),
.interrupts (irq_FROM_controller_TO_slave),
.stopped (status_bit_zero_FROM_controller_TO_slave)
);
assign next_bank_FROM_slave_TO_controller = registers[0];
assign vid_packet_base_address_bank0_bits_FROM_slave_TO_controller= registers[(SLAVE_DATA_REQUIREDWIDTH*1)+SLAVE_DATA_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*1];
assign vid_packet_words_bank0_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*2)+SLAVE_DATA_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*2];
assign vid_packet_samples_bank0_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*3)+SLAVE_DATA_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*3];
assign ctrl_packet_width_bank0_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*5)+CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*5];
assign ctrl_packet_height_bank0_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*6)+CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*6];
assign ctrl_packet_interlaced_bank0_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*7)+CONTROL_PACKET_INTERLACED_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*7];
assign vid_packet_base_address_bank1_bits_FROM_slave_TO_controller= registers[(SLAVE_DATA_REQUIREDWIDTH*8)+SLAVE_DATA_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*8];
assign vid_packet_words_bank1_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*9)+SLAVE_DATA_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*9];
assign vid_packet_samples_bank1_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*10)+SLAVE_DATA_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*10];
assign ctrl_packet_width_bank1_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*12)+CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*12];
assign ctrl_packet_height_bank1_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*13)+CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*13];
assign ctrl_packet_interlaced_bank1_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*14)+CONTROL_PACKET_INTERLACED_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*14];
wire ready_FROM_outputter_TO_encoder;
wire valid_FROM_encoder_TO_outputter;
wire sop_FROM_encoder_TO_outputter;
wire eop_FROM_encoder_TO_outputter;
wire [DATA_WIDTH-1:0] data_FROM_encoder_TO_outputter;
alt_vipvfr131_vfr_control_packet_encoder
#(
.BITS_PER_SYMBOL(BITS_PER_PIXEL_PER_COLOR_PLANE),
.SYMBOLS_PER_BEAT(NUMBER_OF_CHANNELS_IN_PARALLEL))
encoder
(
.clk(clock),
.rst(reset),
.din_ready(ready_FROM_encoder_TO_prc),
.din_valid(valid_FROM_prc_TO_encoder),
.din_data(data_FROM_prc_TO_encoder),
.din_sop(sop_FROM_prc_TO_encoder),
.din_eop(eop_FROM_prc_TO_encoder),
.dout_ready(ready_FROM_outputter_TO_encoder),
.dout_valid(valid_FROM_encoder_TO_outputter),
.dout_sop(sop_FROM_encoder_TO_outputter),
.dout_eop(eop_FROM_encoder_TO_outputter),
.dout_data(data_FROM_encoder_TO_outputter),
.do_control_packet(do_control_packet_FROM_controller_TO_encoder),
.width(width_FROM_controller_TO_encoder),
.height(height_FROM_controller_TO_encoder),
.interlaced(interlaced_FROM_controller_TO_encoder)
);
alt_vipvfr131_common_stream_output
#(.DATA_WIDTH (DATA_WIDTH))
outputter
( .clk (clock),
.rst (reset),
.dout_ready (dout_ready),
.dout_valid (dout_valid),
.dout_data (dout_data),
.dout_sop (dout_startofpacket),
.dout_eop (dout_endofpacket),
.int_ready (ready_FROM_outputter_TO_encoder),
.int_valid (valid_FROM_encoder_TO_outputter),
.int_data (data_FROM_encoder_TO_outputter),
.int_sop (sop_FROM_encoder_TO_outputter),
.int_eop (eop_FROM_encoder_TO_outputter),
.enable (1'b1),
.synced ()
);
endmodule | module alt_vipvfr131_vfr
( clock,
reset,
master_clock,
master_reset,
master_address,
master_burstcount,
master_readdata,
master_read,
master_readdatavalid,
master_waitrequest,
slave_address,
slave_write,
slave_writedata,
slave_read,
slave_readdata,
slave_irq,
dout_ready,
dout_valid,
dout_data,
dout_startofpacket,
dout_endofpacket); |
parameter BITS_PER_PIXEL_PER_COLOR_PLANE = 8;
parameter NUMBER_OF_CHANNELS_IN_PARALLEL = 3;
parameter NUMBER_OF_CHANNELS_IN_SEQUENCE = 1;
parameter MAX_IMAGE_WIDTH = 1920;
parameter MAX_IMAGE_HEIGHT = 1080;
parameter MEM_PORT_WIDTH = 256;
parameter RMASTER_FIFO_DEPTH = 128;
parameter RMASTER_BURST_TARGET = 64;
parameter CLOCKS_ARE_SEPARATE = 1;
function integer alt_vipfunc_required_width;
input [511:0] value;
integer i;
begin
alt_vipfunc_required_width = 512;
for (i=512; i>0; i=i-1) begin
if (2**i>value)
alt_vipfunc_required_width = i;
end
end
endfunction
localparam DATA_WIDTH = BITS_PER_PIXEL_PER_COLOR_PLANE * NUMBER_OF_CHANNELS_IN_PARALLEL;
localparam MM_ADDR_REQUIREDWIDTH = 32;
localparam MM_MASTER_BURST_REQUIREDWIDTH = alt_vipfunc_required_width(RMASTER_BURST_TARGET);
localparam SLAVE_ADDRESS_REQUIREDWIDTH = 5;
localparam SLAVE_DATA_REQUIREDWIDTH = 32;
input clock;
input reset;
input master_clock;
input master_reset;
output [MM_ADDR_REQUIREDWIDTH-1 : 0] master_address;
output [MM_MASTER_BURST_REQUIREDWIDTH-1 : 0] master_burstcount;
input [MEM_PORT_WIDTH-1 : 0] master_readdata;
output master_read;
input master_readdatavalid;
input master_waitrequest;
input [SLAVE_ADDRESS_REQUIREDWIDTH-1:0] slave_address;
input slave_read;
output [SLAVE_DATA_REQUIREDWIDTH-1:0] slave_readdata;
input slave_write;
input [SLAVE_DATA_REQUIREDWIDTH-1:0] slave_writedata;
output slave_irq;
input dout_ready;
output dout_valid;
output dout_startofpacket;
output dout_endofpacket;
output [DATA_WIDTH-1:0] dout_data;
wire ready_FROM_encoder_TO_prc;
wire valid_FROM_prc_TO_encoder;
wire [DATA_WIDTH-1:0] data_FROM_prc_TO_encoder;
wire sop_FROM_prc_TO_encoder;
wire eop_FROM_prc_TO_encoder;
localparam INTERNAL_MASTER_DATA_REQUIREDWIDTH = 32;
localparam INTERNAL_MASTER_ADDRESS_REQUIREDWIDTH = 32;
wire [INTERNAL_MASTER_ADDRESS_REQUIREDWIDTH-1:0] master_address_FROM_controller_TO_prc;
wire master_write_FROM_controller_TO_prc;
wire [INTERNAL_MASTER_DATA_REQUIREDWIDTH-1:0] master_writedata_FROM_controller_TO_prc;
wire slave_irq_FROM_prc_TO_controller;
alt_vipvfr131_prc #(
.BPS(BITS_PER_PIXEL_PER_COLOR_PLANE),
.CHANNELS_IN_PAR(NUMBER_OF_CHANNELS_IN_PARALLEL),
.CHANNELS_IN_SEQ(NUMBER_OF_CHANNELS_IN_SEQUENCE),
.MAX_WIDTH(MAX_IMAGE_WIDTH),
.MAX_HEIGHT(MAX_IMAGE_HEIGHT),
.MEM_PORT_WIDTH(MEM_PORT_WIDTH),
.RMASTER_FIFO_DEPTH(RMASTER_FIFO_DEPTH),
.RMASTER_BURST_TARGET(RMASTER_BURST_TARGET),
.CLOCKS_ARE_SEPARATE(CLOCKS_ARE_SEPARATE),
.READY_LATENCY(0))
prc(
.clock(clock),
.reset(reset),
.master_av_clock(master_clock),
.master_av_reset(master_reset),
.master_av_address(master_address),
.master_av_burstcount(master_burstcount),
.master_av_readdata(master_readdata),
.master_av_read(master_read),
.master_av_readdatavalid(master_readdatavalid),
.master_av_waitrequest(master_waitrequest),
.dout_valid(valid_FROM_prc_TO_encoder),
.dout_ready(ready_FROM_encoder_TO_prc),
.dout_data(data_FROM_prc_TO_encoder),
.dout_startofpacket(sop_FROM_prc_TO_encoder),
.dout_endofpacket(eop_FROM_prc_TO_encoder),
.control_av_address(master_address_FROM_controller_TO_prc),
.control_av_write(master_write_FROM_controller_TO_prc),
.control_av_writedata(master_writedata_FROM_controller_TO_prc),
.control_av_read(),
.control_av_readdata(),
.control_av_irq(slave_irq_FROM_prc_TO_controller)
);
localparam CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH = 16;
localparam CONTROL_PACKET_INTERLACED_REQUIREDWIDTH = 4;
wire [CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1 : 0 ] width_FROM_controller_TO_encoder;
wire [CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1 : 0 ] height_FROM_controller_TO_encoder;
wire [CONTROL_PACKET_INTERLACED_REQUIREDWIDTH-1 : 0 ] interlaced_FROM_controller_TO_encoder;
wire do_control_packet_FROM_controller_TO_encoder;
wire go_bit_FROM_slave_TO_controller;
wire status_bit_zero_FROM_controller_TO_slave;
wire irq_FROM_controller_TO_slave;
wire next_bank_FROM_slave_TO_controller;
wire [CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1 : 0 ] ctrl_packet_width_bank0_bits_FROM_slave_TO_controller;
wire [CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1 : 0 ] ctrl_packet_height_bank0_bits_FROM_slave_TO_controller;
wire [CONTROL_PACKET_INTERLACED_REQUIREDWIDTH-1 : 0 ] ctrl_packet_interlaced_bank0_bits_FROM_slave_TO_controller;
wire [SLAVE_DATA_REQUIREDWIDTH-1 : 0] vid_packet_base_address_bank0_bits_FROM_slave_TO_controller;
wire [SLAVE_DATA_REQUIREDWIDTH-1 : 0] vid_packet_samples_bank0_bits_FROM_slave_TO_controller;
wire [SLAVE_DATA_REQUIREDWIDTH-1 : 0] vid_packet_words_bank0_bits_FROM_slave_TO_controller;
wire [CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1 : 0 ] ctrl_packet_width_bank1_bits_FROM_slave_TO_controller;
wire [CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1 : 0 ] ctrl_packet_height_bank1_bits_FROM_slave_TO_controller;
wire [CONTROL_PACKET_INTERLACED_REQUIREDWIDTH-1 : 0 ] ctrl_packet_interlaced_bank1_bits_FROM_slave_TO_controller;
wire [SLAVE_DATA_REQUIREDWIDTH-1 : 0] vid_packet_base_address_bank1_bits_FROM_slave_TO_controller;
wire [SLAVE_DATA_REQUIREDWIDTH-1 : 0] vid_packet_samples_bank1_bits_FROM_slave_TO_controller;
wire [SLAVE_DATA_REQUIREDWIDTH-1 : 0] vid_packet_words_bank1_bits_FROM_slave_TO_controller;
alt_vipvfr131_vfr_controller #(
.CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH(CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH),
.CONTROL_PACKET_INTERLACED_REQUIREDWIDTH(CONTROL_PACKET_INTERLACED_REQUIREDWIDTH),
.PACKET_ADDRESS_WIDTH(32),
.PACKET_SAMPLES_WIDTH(32),
.PACKET_WORDS_WIDTH(32))
controller(
.clock(clock),
.reset(reset),
.master_address(master_address_FROM_controller_TO_prc),
.master_write(master_write_FROM_controller_TO_prc),
.master_writedata(master_writedata_FROM_controller_TO_prc),
.master_interrupt_recieve(slave_irq_FROM_prc_TO_controller),
.go_bit(go_bit_FROM_slave_TO_controller),
.running(status_bit_zero_FROM_controller_TO_slave),
.frame_complete(irq_FROM_controller_TO_slave),
.next_bank(next_bank_FROM_slave_TO_controller),
.ctrl_packet_width_bank0(ctrl_packet_width_bank0_bits_FROM_slave_TO_controller),
.ctrl_packet_height_bank0(ctrl_packet_height_bank0_bits_FROM_slave_TO_controller),
.ctrl_packet_interlaced_bank0(ctrl_packet_interlaced_bank0_bits_FROM_slave_TO_controller),
.vid_packet_base_address_bank0(vid_packet_base_address_bank0_bits_FROM_slave_TO_controller),
.vid_packet_samples_bank0(vid_packet_samples_bank0_bits_FROM_slave_TO_controller),
.vid_packet_words_bank0(vid_packet_words_bank0_bits_FROM_slave_TO_controller),
.ctrl_packet_width_bank1(ctrl_packet_width_bank1_bits_FROM_slave_TO_controller),
.ctrl_packet_height_bank1(ctrl_packet_height_bank1_bits_FROM_slave_TO_controller),
.ctrl_packet_interlaced_bank1(ctrl_packet_interlaced_bank1_bits_FROM_slave_TO_controller),
.vid_packet_base_address_bank1(vid_packet_base_address_bank1_bits_FROM_slave_TO_controller),
.vid_packet_samples_bank1(vid_packet_samples_bank1_bits_FROM_slave_TO_controller),
.vid_packet_words_bank1(vid_packet_words_bank1_bits_FROM_slave_TO_controller),
.width_of_next_vid_packet(width_FROM_controller_TO_encoder),
.height_of_next_vid_packet(height_FROM_controller_TO_encoder),
.interlaced_of_next_vid_packet(interlaced_FROM_controller_TO_encoder),
.do_control_packet(do_control_packet_FROM_controller_TO_encoder)
);
localparam NO_REGISTERS = 18;
wire stopped;
wire enable;
wire clear_enable;
wire [NO_REGISTERS-1:0] triggers;
wire [(SLAVE_DATA_REQUIREDWIDTH * NO_REGISTERS)-1:0] registers;
wire [(SLAVE_DATA_REQUIREDWIDTH * NO_REGISTERS)-1:0] registers_in;
assign registers_in = {(SLAVE_DATA_REQUIREDWIDTH * NO_REGISTERS){1'b0}};
wire [NO_REGISTERS-1:0] registers_write;
assign registers_write = {NO_REGISTERS{1'b0}};
alt_vipvfr131_common_avalon_mm_slave
#(
.AV_ADDRESS_WIDTH (SLAVE_ADDRESS_REQUIREDWIDTH),
.AV_DATA_WIDTH (SLAVE_DATA_REQUIREDWIDTH),
.NO_OUTPUTS (1),
.NO_INTERRUPTS (1),
.NO_REGISTERS (NO_REGISTERS),
.ALLOW_INTERNAL_WRITE (0))
slave
(
.rst (reset),
.clk (clock),
.av_address (slave_address),
.av_read (slave_read),
.av_readdata (slave_readdata),
.av_write (slave_write),
.av_writedata (slave_writedata),
.av_irq (slave_irq),
.enable (go_bit_FROM_slave_TO_controller),
.clear_enable (1'b0),
.triggers (triggers),
.registers (registers),
.registers_in (registers_in),
.registers_write (registers_write),
.interrupts (irq_FROM_controller_TO_slave),
.stopped (status_bit_zero_FROM_controller_TO_slave)
);
assign next_bank_FROM_slave_TO_controller = registers[0];
assign vid_packet_base_address_bank0_bits_FROM_slave_TO_controller= registers[(SLAVE_DATA_REQUIREDWIDTH*1)+SLAVE_DATA_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*1];
assign vid_packet_words_bank0_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*2)+SLAVE_DATA_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*2];
assign vid_packet_samples_bank0_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*3)+SLAVE_DATA_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*3];
assign ctrl_packet_width_bank0_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*5)+CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*5];
assign ctrl_packet_height_bank0_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*6)+CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*6];
assign ctrl_packet_interlaced_bank0_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*7)+CONTROL_PACKET_INTERLACED_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*7];
assign vid_packet_base_address_bank1_bits_FROM_slave_TO_controller= registers[(SLAVE_DATA_REQUIREDWIDTH*8)+SLAVE_DATA_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*8];
assign vid_packet_words_bank1_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*9)+SLAVE_DATA_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*9];
assign vid_packet_samples_bank1_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*10)+SLAVE_DATA_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*10];
assign ctrl_packet_width_bank1_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*12)+CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*12];
assign ctrl_packet_height_bank1_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*13)+CONTROL_PACKET_RESOLUTION_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*13];
assign ctrl_packet_interlaced_bank1_bits_FROM_slave_TO_controller = registers[(SLAVE_DATA_REQUIREDWIDTH*14)+CONTROL_PACKET_INTERLACED_REQUIREDWIDTH-1:SLAVE_DATA_REQUIREDWIDTH*14];
wire ready_FROM_outputter_TO_encoder;
wire valid_FROM_encoder_TO_outputter;
wire sop_FROM_encoder_TO_outputter;
wire eop_FROM_encoder_TO_outputter;
wire [DATA_WIDTH-1:0] data_FROM_encoder_TO_outputter;
alt_vipvfr131_vfr_control_packet_encoder
#(
.BITS_PER_SYMBOL(BITS_PER_PIXEL_PER_COLOR_PLANE),
.SYMBOLS_PER_BEAT(NUMBER_OF_CHANNELS_IN_PARALLEL))
encoder
(
.clk(clock),
.rst(reset),
.din_ready(ready_FROM_encoder_TO_prc),
.din_valid(valid_FROM_prc_TO_encoder),
.din_data(data_FROM_prc_TO_encoder),
.din_sop(sop_FROM_prc_TO_encoder),
.din_eop(eop_FROM_prc_TO_encoder),
.dout_ready(ready_FROM_outputter_TO_encoder),
.dout_valid(valid_FROM_encoder_TO_outputter),
.dout_sop(sop_FROM_encoder_TO_outputter),
.dout_eop(eop_FROM_encoder_TO_outputter),
.dout_data(data_FROM_encoder_TO_outputter),
.do_control_packet(do_control_packet_FROM_controller_TO_encoder),
.width(width_FROM_controller_TO_encoder),
.height(height_FROM_controller_TO_encoder),
.interlaced(interlaced_FROM_controller_TO_encoder)
);
alt_vipvfr131_common_stream_output
#(.DATA_WIDTH (DATA_WIDTH))
outputter
( .clk (clock),
.rst (reset),
.dout_ready (dout_ready),
.dout_valid (dout_valid),
.dout_data (dout_data),
.dout_sop (dout_startofpacket),
.dout_eop (dout_endofpacket),
.int_ready (ready_FROM_outputter_TO_encoder),
.int_valid (valid_FROM_encoder_TO_outputter),
.int_data (data_FROM_encoder_TO_outputter),
.int_sop (sop_FROM_encoder_TO_outputter),
.int_eop (eop_FROM_encoder_TO_outputter),
.enable (1'b1),
.synced ()
);
endmodule | 5 |
6,590 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_vfr.v | 116,866,011 | alt_vipvfr131_vfr.v | v | 368 | 181 | [] | [] | [] | [(1, 359)] | null | null | 1: b"%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_vfr.v:110: Cannot find file containing module: 'alt_vipvfr131_prc'\n alt_vipvfr131_prc #(\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_prc\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_prc.v\n data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_prc.sv\n alt_vipvfr131_prc\n alt_vipvfr131_prc.v\n alt_vipvfr131_prc.sv\n obj_dir/alt_vipvfr131_prc\n obj_dir/alt_vipvfr131_prc.v\n obj_dir/alt_vipvfr131_prc.sv\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_vfr.v:185: Cannot find file containing module: 'alt_vipvfr131_vfr_controller'\nalt_vipvfr131_vfr_controller #(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_vfr.v:240: Cannot find file containing module: 'alt_vipvfr131_common_avalon_mm_slave'\nalt_vipvfr131_common_avalon_mm_slave\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_vfr.v:308: Cannot find file containing module: 'alt_vipvfr131_vfr_control_packet_encoder'\nalt_vipvfr131_vfr_control_packet_encoder\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_vfr.v:339: Cannot find file containing module: 'alt_vipvfr131_common_stream_output'\n alt_vipvfr131_common_stream_output\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 7,614 | function | function integer alt_vipfunc_required_width;
input [511:0] value;
integer i;
begin
alt_vipfunc_required_width = 512;
for (i=512; i>0; i=i-1) begin
if (2**i>value)
alt_vipfunc_required_width = i;
end
end
endfunction | function integer alt_vipfunc_required_width; |
input [511:0] value;
integer i;
begin
alt_vipfunc_required_width = 512;
for (i=512; i>0; i=i-1) begin
if (2**i>value)
alt_vipfunc_required_width = i;
end
end
endfunction | 5 |
6,592 | data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_vfr_control_packet_encoder.v | 116,866,011 | alt_vipvfr131_vfr_control_packet_encoder.v | v | 214 | 138 | [] | [] | [] | null | line:79: before: "begin" | data/verilator_xmls/d5b50972-2e31-4f03-b31e-e20854312880.xml | null | 7,616 | module | module alt_vipvfr131_vfr_control_packet_encoder
#(parameter BITS_PER_SYMBOL = 8,
parameter SYMBOLS_PER_BEAT = 3)
( input clk,
input rst,
output din_ready,
input din_valid,
input [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] din_data,
input din_sop,
input din_eop,
input dout_ready,
output dout_valid,
output dout_sop,
output dout_eop,
output [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] dout_data,
input do_control_packet,
input [15:0] width,
input [15:0] height,
input [3:0] interlaced);
localparam [3:0] IDLE = 4'd15;
localparam [3:0] WAITING = 4'd14;
localparam [3:0] WIDTH_3 = 4'd0;
localparam [3:0] WIDTH_2 = 4'd1;
localparam [3:0] WIDTH_1 = 4'd2;
localparam [3:0] WIDTH_0 = 4'd3;
localparam [3:0] HEIGHT_3 = 4'd4;
localparam [3:0] HEIGHT_2 = 4'd5;
localparam [3:0] HEIGHT_1 = 4'd6;
localparam [3:0] HEIGHT_0 = 4'd7;
localparam [3:0] INTERLACING = 4'd8;
localparam [3:0] DUMMY_STATE = 4'd9;
localparam [3:0] DUMMY_STATE2 = 4'd10;
localparam [3:0] DUMMY_STATE3 = 4'd12;
localparam [3:0] WAIT_FOR_END = 4'd11;
localparam PACKET_LENGTH = 10;
reg [3:0] state;
wire sop;
wire eop;
wire [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] data;
wire control_valid;
reg writing_control;
reg [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT * (PACKET_LENGTH - 1) - 1 : 0] control_data;
wire [3:0] control_header_state [PACKET_LENGTH - 2: 0];
wire [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] control_header_data [(PACKET_LENGTH-2) : 0];
always @(posedge clk or posedge rst)
if (rst) begin
control_data <= {(BITS_PER_SYMBOL * SYMBOLS_PER_BEAT * (PACKET_LENGTH - 1)){1'b0}};
end
else if (do_control_packet) begin
control_data [3: 0] <= width [15:12];
control_data [BITS_PER_SYMBOL + 3: BITS_PER_SYMBOL] <= width [11:8];
control_data [2 * BITS_PER_SYMBOL + 3: 2 * BITS_PER_SYMBOL] <= width [7:4];
control_data [3 * BITS_PER_SYMBOL + 3: 3 * BITS_PER_SYMBOL] <= width [3:0];
control_data [4 * BITS_PER_SYMBOL + 3: 4 * BITS_PER_SYMBOL] <= height[15:12];
control_data [5 * BITS_PER_SYMBOL + 3: 5 * BITS_PER_SYMBOL] <= height [11:8];
control_data [6 * BITS_PER_SYMBOL + 3: 6 * BITS_PER_SYMBOL] <= height [7:4];
control_data [7 * BITS_PER_SYMBOL + 3: 7 * BITS_PER_SYMBOL] <= height [3:0];
control_data [8 * BITS_PER_SYMBOL + 3: 8 * BITS_PER_SYMBOL] <= interlaced;
end
generate
begin : generate_control_header
genvar symbol;
for(symbol = 0; symbol < PACKET_LENGTH - 1; symbol = symbol + SYMBOLS_PER_BEAT) begin : control_header_states
assign control_header_state [symbol] = symbol + SYMBOLS_PER_BEAT;
assign control_header_data [symbol] = control_data [((symbol + SYMBOLS_PER_BEAT) * BITS_PER_SYMBOL - 1) : (symbol * BITS_PER_SYMBOL)];
end
end
endgenerate
always @(posedge clk or posedge rst)
if (rst) begin
state <= IDLE;
writing_control <= 1'b1;
end
else begin
case (state)
IDLE : begin
state <= do_control_packet ? (~dout_ready) ? WAITING : WIDTH_3 : IDLE;
writing_control <= do_control_packet | writing_control;
end
WAITING : begin
state <= (dout_ready) ? WIDTH_3 : WAITING;
writing_control <= 1'b1;
end
WIDTH_3 : begin
state <= dout_ready ? control_header_state [0] : WIDTH_3;
writing_control <= 1'b1;
end
WIDTH_2 : begin
state <= dout_ready ? control_header_state [1] : WIDTH_2;
writing_control <= 1'b1;
end
WIDTH_1 : begin
state <= dout_ready ? control_header_state [2] : WIDTH_1;
writing_control <= 1'b1;
end
WIDTH_0 : begin
state <= dout_ready ? control_header_state [3] : WIDTH_0;
writing_control <= 1'b1;
end
HEIGHT_3 : begin
state <= dout_ready ? control_header_state [4] : HEIGHT_3;
writing_control <= 1'b1;
end
HEIGHT_2 : begin
state <= dout_ready ? control_header_state [5] : HEIGHT_2;
writing_control <= 1'b1;
end
HEIGHT_1 : begin
state <= dout_ready ? control_header_state [6] : HEIGHT_1;
writing_control <= 1'b1;
end
HEIGHT_0 : begin
state <= dout_ready ? control_header_state [7] : HEIGHT_0;
writing_control <= 1'b1;
end
INTERLACING : begin
state <= dout_ready ? control_header_state [8] : INTERLACING;
writing_control <= 1'b1;
end
DUMMY_STATE : begin
state <= dout_ready ? WAIT_FOR_END : DUMMY_STATE;
writing_control <= 1'b1;
end
DUMMY_STATE2 : begin
state <= dout_ready ? WAIT_FOR_END : DUMMY_STATE2;
writing_control <= 1'b1;
end
DUMMY_STATE3 : begin
state <= dout_ready ? WAIT_FOR_END : DUMMY_STATE3;
writing_control <= 1'b1;
end
WAIT_FOR_END : begin
state <= (din_valid & din_ready & din_eop) ? IDLE : WAIT_FOR_END;
writing_control <= 1'b0;
end
endcase
end
assign control_valid = (state == IDLE) ? (do_control_packet & dout_ready) :
(state == WAIT_FOR_END | state == DUMMY_STATE | state == DUMMY_STATE2 | state == DUMMY_STATE3) ? 1'b0 : dout_ready;
assign data = (state == IDLE) ? {{(BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 4) {1'b0}}, 4'hf} :
(state == WAITING) ? {{(BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 4) {1'b0}}, 4'hf} :
(state == WIDTH_3) ? control_header_data [0] :
(state == WIDTH_2) ? control_header_data [1] :
(state == WIDTH_1) ? control_header_data [2] :
(state == WIDTH_0) ? control_header_data [3] :
(state == HEIGHT_3) ? control_header_data [4] :
(state == HEIGHT_2) ? control_header_data [5] :
(state == HEIGHT_1) ? control_header_data [6] :
(state == HEIGHT_0) ? control_header_data [7] :
(state == INTERLACING) ? control_header_data [8] :
(state == DUMMY_STATE) ? {{(BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 4) {1'b0}}, 4'h0} :
(state == DUMMY_STATE2) ? {{(BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 4) {1'b0}}, 4'h0} :
(state == DUMMY_STATE3) ? {{(BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 4) {1'b0}}, 4'h0} : din_data;
assign sop = ((state == IDLE) || (state == WAITING)) ? 1'b1 : 1'b0;
assign eop = (state <= INTERLACING) ? (state == ((PACKET_LENGTH-2)/SYMBOLS_PER_BEAT * SYMBOLS_PER_BEAT)) : 1'b0;
assign din_ready = ~(do_control_packet | writing_control) & dout_ready;
assign dout_valid = control_valid ? 1'b1 : din_valid & din_ready;
assign dout_data = control_valid ? data : din_data;
assign dout_sop = control_valid ? sop : din_sop;
assign dout_eop = control_valid ? eop : din_eop;
endmodule | module alt_vipvfr131_vfr_control_packet_encoder
#(parameter BITS_PER_SYMBOL = 8,
parameter SYMBOLS_PER_BEAT = 3)
( input clk,
input rst,
output din_ready,
input din_valid,
input [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] din_data,
input din_sop,
input din_eop,
input dout_ready,
output dout_valid,
output dout_sop,
output dout_eop,
output [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] dout_data,
input do_control_packet,
input [15:0] width,
input [15:0] height,
input [3:0] interlaced); |
localparam [3:0] IDLE = 4'd15;
localparam [3:0] WAITING = 4'd14;
localparam [3:0] WIDTH_3 = 4'd0;
localparam [3:0] WIDTH_2 = 4'd1;
localparam [3:0] WIDTH_1 = 4'd2;
localparam [3:0] WIDTH_0 = 4'd3;
localparam [3:0] HEIGHT_3 = 4'd4;
localparam [3:0] HEIGHT_2 = 4'd5;
localparam [3:0] HEIGHT_1 = 4'd6;
localparam [3:0] HEIGHT_0 = 4'd7;
localparam [3:0] INTERLACING = 4'd8;
localparam [3:0] DUMMY_STATE = 4'd9;
localparam [3:0] DUMMY_STATE2 = 4'd10;
localparam [3:0] DUMMY_STATE3 = 4'd12;
localparam [3:0] WAIT_FOR_END = 4'd11;
localparam PACKET_LENGTH = 10;
reg [3:0] state;
wire sop;
wire eop;
wire [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] data;
wire control_valid;
reg writing_control;
reg [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT * (PACKET_LENGTH - 1) - 1 : 0] control_data;
wire [3:0] control_header_state [PACKET_LENGTH - 2: 0];
wire [BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 1:0] control_header_data [(PACKET_LENGTH-2) : 0];
always @(posedge clk or posedge rst)
if (rst) begin
control_data <= {(BITS_PER_SYMBOL * SYMBOLS_PER_BEAT * (PACKET_LENGTH - 1)){1'b0}};
end
else if (do_control_packet) begin
control_data [3: 0] <= width [15:12];
control_data [BITS_PER_SYMBOL + 3: BITS_PER_SYMBOL] <= width [11:8];
control_data [2 * BITS_PER_SYMBOL + 3: 2 * BITS_PER_SYMBOL] <= width [7:4];
control_data [3 * BITS_PER_SYMBOL + 3: 3 * BITS_PER_SYMBOL] <= width [3:0];
control_data [4 * BITS_PER_SYMBOL + 3: 4 * BITS_PER_SYMBOL] <= height[15:12];
control_data [5 * BITS_PER_SYMBOL + 3: 5 * BITS_PER_SYMBOL] <= height [11:8];
control_data [6 * BITS_PER_SYMBOL + 3: 6 * BITS_PER_SYMBOL] <= height [7:4];
control_data [7 * BITS_PER_SYMBOL + 3: 7 * BITS_PER_SYMBOL] <= height [3:0];
control_data [8 * BITS_PER_SYMBOL + 3: 8 * BITS_PER_SYMBOL] <= interlaced;
end
generate
begin : generate_control_header
genvar symbol;
for(symbol = 0; symbol < PACKET_LENGTH - 1; symbol = symbol + SYMBOLS_PER_BEAT) begin : control_header_states
assign control_header_state [symbol] = symbol + SYMBOLS_PER_BEAT;
assign control_header_data [symbol] = control_data [((symbol + SYMBOLS_PER_BEAT) * BITS_PER_SYMBOL - 1) : (symbol * BITS_PER_SYMBOL)];
end
end
endgenerate
always @(posedge clk or posedge rst)
if (rst) begin
state <= IDLE;
writing_control <= 1'b1;
end
else begin
case (state)
IDLE : begin
state <= do_control_packet ? (~dout_ready) ? WAITING : WIDTH_3 : IDLE;
writing_control <= do_control_packet | writing_control;
end
WAITING : begin
state <= (dout_ready) ? WIDTH_3 : WAITING;
writing_control <= 1'b1;
end
WIDTH_3 : begin
state <= dout_ready ? control_header_state [0] : WIDTH_3;
writing_control <= 1'b1;
end
WIDTH_2 : begin
state <= dout_ready ? control_header_state [1] : WIDTH_2;
writing_control <= 1'b1;
end
WIDTH_1 : begin
state <= dout_ready ? control_header_state [2] : WIDTH_1;
writing_control <= 1'b1;
end
WIDTH_0 : begin
state <= dout_ready ? control_header_state [3] : WIDTH_0;
writing_control <= 1'b1;
end
HEIGHT_3 : begin
state <= dout_ready ? control_header_state [4] : HEIGHT_3;
writing_control <= 1'b1;
end
HEIGHT_2 : begin
state <= dout_ready ? control_header_state [5] : HEIGHT_2;
writing_control <= 1'b1;
end
HEIGHT_1 : begin
state <= dout_ready ? control_header_state [6] : HEIGHT_1;
writing_control <= 1'b1;
end
HEIGHT_0 : begin
state <= dout_ready ? control_header_state [7] : HEIGHT_0;
writing_control <= 1'b1;
end
INTERLACING : begin
state <= dout_ready ? control_header_state [8] : INTERLACING;
writing_control <= 1'b1;
end
DUMMY_STATE : begin
state <= dout_ready ? WAIT_FOR_END : DUMMY_STATE;
writing_control <= 1'b1;
end
DUMMY_STATE2 : begin
state <= dout_ready ? WAIT_FOR_END : DUMMY_STATE2;
writing_control <= 1'b1;
end
DUMMY_STATE3 : begin
state <= dout_ready ? WAIT_FOR_END : DUMMY_STATE3;
writing_control <= 1'b1;
end
WAIT_FOR_END : begin
state <= (din_valid & din_ready & din_eop) ? IDLE : WAIT_FOR_END;
writing_control <= 1'b0;
end
endcase
end
assign control_valid = (state == IDLE) ? (do_control_packet & dout_ready) :
(state == WAIT_FOR_END | state == DUMMY_STATE | state == DUMMY_STATE2 | state == DUMMY_STATE3) ? 1'b0 : dout_ready;
assign data = (state == IDLE) ? {{(BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 4) {1'b0}}, 4'hf} :
(state == WAITING) ? {{(BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 4) {1'b0}}, 4'hf} :
(state == WIDTH_3) ? control_header_data [0] :
(state == WIDTH_2) ? control_header_data [1] :
(state == WIDTH_1) ? control_header_data [2] :
(state == WIDTH_0) ? control_header_data [3] :
(state == HEIGHT_3) ? control_header_data [4] :
(state == HEIGHT_2) ? control_header_data [5] :
(state == HEIGHT_1) ? control_header_data [6] :
(state == HEIGHT_0) ? control_header_data [7] :
(state == INTERLACING) ? control_header_data [8] :
(state == DUMMY_STATE) ? {{(BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 4) {1'b0}}, 4'h0} :
(state == DUMMY_STATE2) ? {{(BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 4) {1'b0}}, 4'h0} :
(state == DUMMY_STATE3) ? {{(BITS_PER_SYMBOL * SYMBOLS_PER_BEAT - 4) {1'b0}}, 4'h0} : din_data;
assign sop = ((state == IDLE) || (state == WAITING)) ? 1'b1 : 1'b0;
assign eop = (state <= INTERLACING) ? (state == ((PACKET_LENGTH-2)/SYMBOLS_PER_BEAT * SYMBOLS_PER_BEAT)) : 1'b0;
assign din_ready = ~(do_control_packet | writing_control) & dout_ready;
assign dout_valid = control_valid ? 1'b1 : din_valid & din_ready;
assign dout_data = control_valid ? data : din_data;
assign dout_sop = control_valid ? sop : din_sop;
assign dout_eop = control_valid ? eop : din_eop;
endmodule | 5 |
6,595 | data/full_repos/permissive/116866011/PipeCNN/project/efi_testbench.sv | 116,866,011 | efi_testbench.sv | sv | 209 | 102 | [] | [] | [] | null | line:6: before: "import" | null | 1: b'%Error: data/full_repos/permissive/116866011/PipeCNN/project/efi_testbench.sv:6: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport avalon_mm_pkg::*; \n ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/116866011/PipeCNN/project/efi_testbench.sv:60: Unsupported: Ignoring delay on this delayed statement.\n #200 reset_n = 1\'b1; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116866011/PipeCNN/project/efi_testbench.sv:61: Unsupported: Ignoring delay on this delayed statement.\n #50; \n ^\n%Error: data/full_repos/permissive/116866011/PipeCNN/project/efi_testbench.sv:65: syntax error, unexpected \'@\'\n @(posedge clk); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/116866011/PipeCNN/project/efi_testbench.sv:78: Unsupported: Ignoring delay on this delayed statement.\n #2.5 clk <= ~clk; \n ^\n%Error: data/full_repos/permissive/116866011/PipeCNN/project/efi_testbench.sv:174: Unsupported: fork statements\n fork : get_response_block \n ^~~~\n%Error: data/full_repos/permissive/116866011/PipeCNN/project/efi_testbench.sv:177: syntax error, unexpected \'@\'\n @(posedge clk); \n ^\n%Error: data/full_repos/permissive/116866011/PipeCNN/project/efi_testbench.sv:180: syntax error, unexpected \'@\'\n repeat (100) @(posedge clk); \n ^\n%Error: data/full_repos/permissive/116866011/PipeCNN/project/efi_testbench.sv:185: Unsupported: disable fork statements\n disable fork; \n ^~~~~~~\n%Error: Exiting due to 6 error(s), 3 warning(s)\n' | 7,714 | module | module efi_testbench;
localparam MAX_WIDTH=`MAX_WIDTH;
localparam NUM_SNKS=`NUM_SNKS;
localparam NUM_SRCS=`NUM_SRCS;
import "DPI-C" context task dpi_init( input int num_efis, input int max_width, input int debug);
import "DPI-C" context task dpi_update();
import "DPI-C" context task dpi_close();
import "DPI-C" context task dpi_efi_return(input bit [31:0] id, input bit [MAX_WIDTH-1:0] data);
export "DPI-C" task dpi_efi_call;
reg clk;
reg reset_n;
integer i;
logic [NUM_SNKS-1:0] snk_valid;
logic [MAX_WIDTH-1:0] snk_data[NUM_SNKS];
logic [NUM_SNKS-1:0] snk_ready;
logic [NUM_SRCS-1:0] src_valid;
logic [MAX_WIDTH-1:0] src_data[NUM_SRCS];
logic [NUM_SRCS-1:0] src_ready;
initial
begin
`ifdef DEBUG_VERBOSITY
set_verbosity( VERBOSITY_INFO );
`else
set_verbosity( VERBOSITY_WARNING );
`endif
end
initial
begin
reset_n = 1'b0;
#200 reset_n = 1'b1;
#50;
dpi_init(NUM_SRCS, MAX_WIDTH, (get_verbosity() >= VERBOSITY_INFO));
forever begin
dpi_update();
@(posedge clk);
end
end
final
begin
end
initial
clk = 1'b1;
always
#2.5 clk <= ~clk;
genvar s;
generate
for ( s=0; s<NUM_SNKS; s=s+1)
begin : src_bfm
altera_avalon_st_source_bfm #(
.ST_SYMBOL_W(1),
.ST_NUMSYMBOLS(MAX_WIDTH)
) st_source (
.clk(clk),
.reset(!resetn),
.src_data(snk_data[s]),
.src_channel(),
.src_valid(snk_valid[s]),
.src_startofpacket(),
.src_endofpacket(),
.src_error(),
.src_empty(),
.src_ready(snk_ready[s])
);
end
endgenerate
generate
for ( s=0; s<NUM_SRCS; s=s+1)
begin : snk_bfm
altera_avalon_st_sink_bfm #(
.ST_SYMBOL_W(1),
.ST_NUMSYMBOLS(MAX_WIDTH)
) st_sink (
.clk(clk),
.reset(!resetn),
.sink_data(src_data[s]),
.sink_channel(),
.sink_valid(src_valid[s]),
.sink_startofpacket(),
.sink_endofpacket(),
.sink_error(),
.sink_empty(),
.sink_ready(src_ready[s]));
always@(posedge clk)
begin
if (snk_bfm[s].st_sink.get_transaction_queue_size() > 0)
begin
logic [MAX_WIDTH-1:0] return_val;
snk_bfm[s].st_sink.pop_transaction();
return_val = snk_bfm[s].st_sink.get_transaction_data();
if(get_verbosity() >= VERBOSITY_INFO)
$display( "%0d: Received from channel %2d value = 0x%h", $time, s, return_val);
dpi_efi_return( s, return_val );
end
end
initial
begin
snk_bfm[s].st_sink.init();
snk_bfm[s].st_sink.set_ready(1'b1);
end
end
endgenerate
task dpi_efi_call;
input bit [31:0] id;
input bit [MAX_WIDTH-1:0] data;
if(get_verbosity() >= VERBOSITY_INFO)
$display( "%0d: Writing to channel %2d with value = 0x%h", $time, id, data );
case (id)
'hdeadbeef : begin
dpi_close();
$finish;
end
0 : channel_write_src0(data);
default : begin
$display ("%0d: Invalid call id called: %d",$time,id);
dpi_close();
$finish;
end
endcase
endtask
task channel_write_src0;
input [MAX_WIDTH-1:0] data;
src_bfm[0].st_source.set_transaction_data(data);
src_bfm[0].st_source.push_transaction();
fork : get_response_block
begin
while(src_bfm[0].st_source.get_response_queue_size() == 0)
@(posedge clk);
end
begin
repeat (100) @(posedge clk);
print(VERBOSITY_ERROR, "No response received");
$stop;
end
join_any : get_response_block
disable fork;
src_bfm[0].st_source.pop_response();
endtask
mult_add_fix8bx4 mult_add_fix8bx40 (
.clock ( clk ),
.resetn ( reset_n ),
.iready ( src_ready[0] ),
.dataa_0 ( snk_data[0][7:0] ),
.datab_0 ( snk_data[0][15:8] ),
.dataa_1 ( snk_data[0][23:16] ),
.datab_1 ( snk_data[0][31:24] ),
.dataa_2 ( snk_data[0][39:32] ),
.datab_2 ( snk_data[0][47:40] ),
.dataa_3 ( snk_data[0][55:48] ),
.datab_3 ( snk_data[0][63:56] ),
.ivalid ( snk_valid[0] ),
.ovalid ( src_valid[0] ),
.result ( src_data[0] ),
.oready ( snk_ready[0] )
);
endmodule | module efi_testbench; |
localparam MAX_WIDTH=`MAX_WIDTH;
localparam NUM_SNKS=`NUM_SNKS;
localparam NUM_SRCS=`NUM_SRCS;
import "DPI-C" context task dpi_init( input int num_efis, input int max_width, input int debug);
import "DPI-C" context task dpi_update();
import "DPI-C" context task dpi_close();
import "DPI-C" context task dpi_efi_return(input bit [31:0] id, input bit [MAX_WIDTH-1:0] data);
export "DPI-C" task dpi_efi_call;
reg clk;
reg reset_n;
integer i;
logic [NUM_SNKS-1:0] snk_valid;
logic [MAX_WIDTH-1:0] snk_data[NUM_SNKS];
logic [NUM_SNKS-1:0] snk_ready;
logic [NUM_SRCS-1:0] src_valid;
logic [MAX_WIDTH-1:0] src_data[NUM_SRCS];
logic [NUM_SRCS-1:0] src_ready;
initial
begin
`ifdef DEBUG_VERBOSITY
set_verbosity( VERBOSITY_INFO );
`else
set_verbosity( VERBOSITY_WARNING );
`endif
end
initial
begin
reset_n = 1'b0;
#200 reset_n = 1'b1;
#50;
dpi_init(NUM_SRCS, MAX_WIDTH, (get_verbosity() >= VERBOSITY_INFO));
forever begin
dpi_update();
@(posedge clk);
end
end
final
begin
end
initial
clk = 1'b1;
always
#2.5 clk <= ~clk;
genvar s;
generate
for ( s=0; s<NUM_SNKS; s=s+1)
begin : src_bfm
altera_avalon_st_source_bfm #(
.ST_SYMBOL_W(1),
.ST_NUMSYMBOLS(MAX_WIDTH)
) st_source (
.clk(clk),
.reset(!resetn),
.src_data(snk_data[s]),
.src_channel(),
.src_valid(snk_valid[s]),
.src_startofpacket(),
.src_endofpacket(),
.src_error(),
.src_empty(),
.src_ready(snk_ready[s])
);
end
endgenerate
generate
for ( s=0; s<NUM_SRCS; s=s+1)
begin : snk_bfm
altera_avalon_st_sink_bfm #(
.ST_SYMBOL_W(1),
.ST_NUMSYMBOLS(MAX_WIDTH)
) st_sink (
.clk(clk),
.reset(!resetn),
.sink_data(src_data[s]),
.sink_channel(),
.sink_valid(src_valid[s]),
.sink_startofpacket(),
.sink_endofpacket(),
.sink_error(),
.sink_empty(),
.sink_ready(src_ready[s]));
always@(posedge clk)
begin
if (snk_bfm[s].st_sink.get_transaction_queue_size() > 0)
begin
logic [MAX_WIDTH-1:0] return_val;
snk_bfm[s].st_sink.pop_transaction();
return_val = snk_bfm[s].st_sink.get_transaction_data();
if(get_verbosity() >= VERBOSITY_INFO)
$display( "%0d: Received from channel %2d value = 0x%h", $time, s, return_val);
dpi_efi_return( s, return_val );
end
end
initial
begin
snk_bfm[s].st_sink.init();
snk_bfm[s].st_sink.set_ready(1'b1);
end
end
endgenerate
task dpi_efi_call;
input bit [31:0] id;
input bit [MAX_WIDTH-1:0] data;
if(get_verbosity() >= VERBOSITY_INFO)
$display( "%0d: Writing to channel %2d with value = 0x%h", $time, id, data );
case (id)
'hdeadbeef : begin
dpi_close();
$finish;
end
0 : channel_write_src0(data);
default : begin
$display ("%0d: Invalid call id called: %d",$time,id);
dpi_close();
$finish;
end
endcase
endtask
task channel_write_src0;
input [MAX_WIDTH-1:0] data;
src_bfm[0].st_source.set_transaction_data(data);
src_bfm[0].st_source.push_transaction();
fork : get_response_block
begin
while(src_bfm[0].st_source.get_response_queue_size() == 0)
@(posedge clk);
end
begin
repeat (100) @(posedge clk);
print(VERBOSITY_ERROR, "No response received");
$stop;
end
join_any : get_response_block
disable fork;
src_bfm[0].st_source.pop_response();
endtask
mult_add_fix8bx4 mult_add_fix8bx40 (
.clock ( clk ),
.resetn ( reset_n ),
.iready ( src_ready[0] ),
.dataa_0 ( snk_data[0][7:0] ),
.datab_0 ( snk_data[0][15:8] ),
.dataa_1 ( snk_data[0][23:16] ),
.datab_1 ( snk_data[0][31:24] ),
.dataa_2 ( snk_data[0][39:32] ),
.datab_2 ( snk_data[0][47:40] ),
.dataa_3 ( snk_data[0][55:48] ),
.datab_3 ( snk_data[0][63:56] ),
.ivalid ( snk_valid[0] ),
.ovalid ( src_valid[0] ),
.result ( src_data[0] ),
.oready ( snk_ready[0] )
);
endmodule | 5 |
6,596 | data/full_repos/permissive/116866011/PipeCNN/project/device/RTL/mult_add_fix8bx4/mult_add_fix8bx4.v | 116,866,011 | mult_add_fix8bx4.v | v | 48 | 53 | [] | [] | [] | [(2, 47)] | null | null | 1: b"%Error: data/full_repos/permissive/116866011/PipeCNN/project/device/RTL/mult_add_fix8bx4/mult_add_fix8bx4.v:34: Cannot find file containing module: 'mult_add_fix8bx4_0002'\n mult_add_fix8bx4_0002 mult_add_fix8bx4_inst (\n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/116866011/PipeCNN/project/device/RTL/mult_add_fix8bx4,data/full_repos/permissive/116866011/mult_add_fix8bx4_0002\n data/full_repos/permissive/116866011/PipeCNN/project/device/RTL/mult_add_fix8bx4,data/full_repos/permissive/116866011/mult_add_fix8bx4_0002.v\n data/full_repos/permissive/116866011/PipeCNN/project/device/RTL/mult_add_fix8bx4,data/full_repos/permissive/116866011/mult_add_fix8bx4_0002.sv\n mult_add_fix8bx4_0002\n mult_add_fix8bx4_0002.v\n mult_add_fix8bx4_0002.sv\n obj_dir/mult_add_fix8bx4_0002\n obj_dir/mult_add_fix8bx4_0002.v\n obj_dir/mult_add_fix8bx4_0002.sv\n%Error: Exiting due to 1 error(s)\n" | 7,715 | module | module mult_add_fix8bx4 (
input clock,
input resetn,
input ivalid,
input iready,
output ovalid,
output oready,
input wire [7:0] dataa_0,
input wire [7:0] datab_0,
input wire [7:0] dataa_1,
input wire [7:0] datab_1,
input wire [7:0] dataa_2,
input wire [7:0] datab_2,
input wire [7:0] dataa_3,
input wire [7:0] datab_3,
output wire [31:0] result
);
wire [17:0] result_18b;
assign ovalid = 1'b1;
assign oready = 1'b1;
assign result = {{14{result_18b[17]}}, result_18b};
mult_add_fix8bx4_0002 mult_add_fix8bx4_inst (
.result (result_18b),
.dataa_0 (dataa_0),
.dataa_1 (dataa_1),
.dataa_2 (dataa_2),
.dataa_3 (dataa_3),
.datab_0 (datab_0),
.datab_1 (datab_1),
.datab_2 (datab_2),
.datab_3 (datab_3),
.clock0 (clock)
);
endmodule | module mult_add_fix8bx4 (
input clock,
input resetn,
input ivalid,
input iready,
output ovalid,
output oready,
input wire [7:0] dataa_0,
input wire [7:0] datab_0,
input wire [7:0] dataa_1,
input wire [7:0] datab_1,
input wire [7:0] dataa_2,
input wire [7:0] datab_2,
input wire [7:0] dataa_3,
input wire [7:0] datab_3,
output wire [31:0] result
); |
wire [17:0] result_18b;
assign ovalid = 1'b1;
assign oready = 1'b1;
assign result = {{14{result_18b[17]}}, result_18b};
mult_add_fix8bx4_0002 mult_add_fix8bx4_inst (
.result (result_18b),
.dataa_0 (dataa_0),
.dataa_1 (dataa_1),
.dataa_2 (dataa_2),
.dataa_3 (dataa_3),
.datab_0 (datab_0),
.datab_1 (datab_1),
.datab_2 (datab_2),
.datab_3 (datab_3),
.clock0 (clock)
);
endmodule | 5 |
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