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5,826 | data/full_repos/permissive/114814262/IC 2015-2016/HARDWARE/[DEPRECATED] sistema_controle_alarme v1.0.0/[FPGA] sistema_para_controle_de_alarme/v1.0.0/controle.v | 114,814,262 | controle.v | v | 46 | 122 | [] | [] | [] | [(22, 46)] | null | null | 1: b'%Error: Cannot find file containing module: 2015-2016/HARDWARE/[DEPRECATED]\n ... Looked in:\n data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED]\n data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED].v\n data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED].sv\n 2015-2016/HARDWARE/[DEPRECATED]\n 2015-2016/HARDWARE/[DEPRECATED].v\n 2015-2016/HARDWARE/[DEPRECATED].sv\n obj_dir/2015-2016/HARDWARE/[DEPRECATED]\n obj_dir/2015-2016/HARDWARE/[DEPRECATED].v\n obj_dir/2015-2016/HARDWARE/[DEPRECATED].sv\n%Error: Cannot find file containing module: sistema_controle_alarme\n%Error: Cannot find file containing module: v1.0.0/[FPGA]\n%Error: Cannot find file containing module: sistema_para_controle_de_alarme/v1.0.0,data/full_repos/permissive/114814262\n%Error: Cannot find file containing module: data/full_repos/permissive/114814262/IC\n%Error: Cannot find file containing module: sistema_para_controle_de_alarme/v1.0.0/controle.v\n%Error: Exiting due to 6 error(s)\n' | 6,616 | module | module controle(
input clk,
input button,
input RxD,
input communication,
output wire[2:0] saida,
output wire led
);
wire[7:0] GPout,GPin;
wire TxD;
wire crianca;
wire clk_out;
clock_atraso clock_atraso(clk,clk_out);
controle2 control(saida, RxD, communication, button, clk_out);
assign led = communication;
endmodule | module controle(
input clk,
input button,
input RxD,
input communication,
output wire[2:0] saida,
output wire led
); |
wire[7:0] GPout,GPin;
wire TxD;
wire crianca;
wire clk_out;
clock_atraso clock_atraso(clk,clk_out);
controle2 control(saida, RxD, communication, button, clk_out);
assign led = communication;
endmodule | 0 |
5,827 | data/full_repos/permissive/114814262/IC 2015-2016/HARDWARE/[DEPRECATED] sistema_controle_alarme v1.0.0/[FPGA] sistema_para_controle_de_alarme/v1.0.0/controle2.v | 114,814,262 | controle2.v | v | 178 | 93 | [] | [] | [] | [(24, 177)] | null | null | 1: b'%Error: Cannot find file containing module: 2015-2016/HARDWARE/[DEPRECATED]\n ... Looked in:\n data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED]\n data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED].v\n data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED].sv\n 2015-2016/HARDWARE/[DEPRECATED]\n 2015-2016/HARDWARE/[DEPRECATED].v\n 2015-2016/HARDWARE/[DEPRECATED].sv\n obj_dir/2015-2016/HARDWARE/[DEPRECATED]\n obj_dir/2015-2016/HARDWARE/[DEPRECATED].v\n obj_dir/2015-2016/HARDWARE/[DEPRECATED].sv\n%Error: Cannot find file containing module: sistema_controle_alarme\n%Error: Cannot find file containing module: v1.0.0/[FPGA]\n%Error: Cannot find file containing module: sistema_para_controle_de_alarme/v1.0.0,data/full_repos/permissive/114814262\n%Error: Cannot find file containing module: data/full_repos/permissive/114814262/IC\n%Error: Cannot find file containing module: sistema_para_controle_de_alarme/v1.0.0/controle2.v\n%Error: Exiting due to 6 error(s)\n' | 6,617 | module | module controle2(saida, crianca, communication, button, clk);
input clk, button, communication, crianca;
output[2:0] saida;
reg[2:0] saida=3'b000;
reg [2:0] state=3'b000;
reg[32:0] count;
parameter WAIT=3'b000,
STAND_BY= 3'b001,
LED=3'b010,
LED_VIBRA1=3'b011,
LED_VIBRA2=3'b100,
LED_VIBRA_APITA=3'b101;
parameter nula=3'b000,
led0=3'b001,
led_vibra0=3'b011,
led_vibra_apita0=3'b111;
always @(posedge clk)
begin
case(state)
WAIT : begin
if(communication==1'b0 && crianca==1'b0)
begin
state<=STAND_BY;
saida<=nula;
end else
if(communication==1'b0 && crianca==1'b1)
begin
state<=LED;
saida<=led0;
end else
begin
state<=WAIT;
saida<=nula;
end
end
STAND_BY : begin
if(communication==1'b1)
begin
state<=WAIT;
saida<=nula;
end
end
LED : begin
if(crianca==1'b0 && communication==1'b1)
begin
state<=WAIT;
saida<=nula;
end else
if(button==1'b1)
begin
state<=#5 LED_VIBRA2;
saida<=#5 led_vibra0;
end else
begin
state<=#5 LED_VIBRA1;
saida<=#5 led_vibra0;
end
end
LED_VIBRA1 : begin
if(crianca==1'b0 && communication==1'b1)
begin
state<=WAIT;
saida<=nula;
end else
if(button==1'b1)
begin
state<=LED_VIBRA2;
saida<=led_vibra0;
end else
begin
state<=#5 LED_VIBRA_APITA;
saida<=#5 led_vibra_apita0;
end
end
LED_VIBRA_APITA: begin
if(crianca==1'b0 && communication==1'b1)
begin
state<=WAIT;
saida<=nula;
end else
if(button==1'b1)
begin
state<=LED_VIBRA2;
saida<=led_vibra0;
end else
begin
state<=LED_VIBRA_APITA;
saida<=led_vibra_apita0;
end
end
LED_VIBRA2 : begin
if(crianca==1'b0 && communication==1'b1)
begin
state<=WAIT;
saida<=nula;
end else
begin
state<=#5 LED_VIBRA_APITA;
saida<=#5 led_vibra_apita0;
end
end
default : begin
state<=WAIT;
saida<=nula;
end
endcase
end
endmodule | module controle2(saida, crianca, communication, button, clk); |
input clk, button, communication, crianca;
output[2:0] saida;
reg[2:0] saida=3'b000;
reg [2:0] state=3'b000;
reg[32:0] count;
parameter WAIT=3'b000,
STAND_BY= 3'b001,
LED=3'b010,
LED_VIBRA1=3'b011,
LED_VIBRA2=3'b100,
LED_VIBRA_APITA=3'b101;
parameter nula=3'b000,
led0=3'b001,
led_vibra0=3'b011,
led_vibra_apita0=3'b111;
always @(posedge clk)
begin
case(state)
WAIT : begin
if(communication==1'b0 && crianca==1'b0)
begin
state<=STAND_BY;
saida<=nula;
end else
if(communication==1'b0 && crianca==1'b1)
begin
state<=LED;
saida<=led0;
end else
begin
state<=WAIT;
saida<=nula;
end
end
STAND_BY : begin
if(communication==1'b1)
begin
state<=WAIT;
saida<=nula;
end
end
LED : begin
if(crianca==1'b0 && communication==1'b1)
begin
state<=WAIT;
saida<=nula;
end else
if(button==1'b1)
begin
state<=#5 LED_VIBRA2;
saida<=#5 led_vibra0;
end else
begin
state<=#5 LED_VIBRA1;
saida<=#5 led_vibra0;
end
end
LED_VIBRA1 : begin
if(crianca==1'b0 && communication==1'b1)
begin
state<=WAIT;
saida<=nula;
end else
if(button==1'b1)
begin
state<=LED_VIBRA2;
saida<=led_vibra0;
end else
begin
state<=#5 LED_VIBRA_APITA;
saida<=#5 led_vibra_apita0;
end
end
LED_VIBRA_APITA: begin
if(crianca==1'b0 && communication==1'b1)
begin
state<=WAIT;
saida<=nula;
end else
if(button==1'b1)
begin
state<=LED_VIBRA2;
saida<=led_vibra0;
end else
begin
state<=LED_VIBRA_APITA;
saida<=led_vibra_apita0;
end
end
LED_VIBRA2 : begin
if(crianca==1'b0 && communication==1'b1)
begin
state<=WAIT;
saida<=nula;
end else
begin
state<=#5 LED_VIBRA_APITA;
saida<=#5 led_vibra_apita0;
end
end
default : begin
state<=WAIT;
saida<=nula;
end
endcase
end
endmodule | 0 |
5,828 | data/full_repos/permissive/114814262/IC 2015-2016/HARDWARE/[DEPRECATED] sistema_controle_alarme v1.0.0/[FPGA] sistema_para_controle_de_alarme/v1.0.0/interface comunicacao.v | 114,814,262 | interface comunicacao.v | v | 23 | 95 | [] | [] | [] | [(7, 23)] | null | null | 1: b'%Error: Cannot find file containing module: 2015-2016/HARDWARE/[DEPRECATED]\n ... Looked in:\n data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED]\n data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED].v\n data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED].sv\n 2015-2016/HARDWARE/[DEPRECATED]\n 2015-2016/HARDWARE/[DEPRECATED].v\n 2015-2016/HARDWARE/[DEPRECATED].sv\n obj_dir/2015-2016/HARDWARE/[DEPRECATED]\n obj_dir/2015-2016/HARDWARE/[DEPRECATED].v\n obj_dir/2015-2016/HARDWARE/[DEPRECATED].sv\n%Error: Cannot find file containing module: sistema_controle_alarme\n%Error: Cannot find file containing module: v1.0.0/[FPGA]\n%Error: Cannot find file containing module: sistema_para_controle_de_alarme/v1.0.0,data/full_repos/permissive/114814262\n%Error: Cannot find file containing module: data/full_repos/permissive/114814262/IC\n%Error: Cannot find file containing module: sistema_para_controle_de_alarme/v1.0.0/interface\n%Error: Cannot find file containing module: comunicacao.v\n%Error: Exiting due to 7 error(s)\n' | 6,618 | module | module Comunicacao(
input clk,
input RxD,
output TxD,
output reg [7:0] GPout,
input [7:0] GPin
);
wire RxD_data_ready;
wire [7:0] RxD_data;
async_receiver RX(.clk(clk), .RxD(RxD), .RxD_data_ready(RxD_data_ready), .RxD_data(RxD_data));
always @(posedge clk) if(RxD_data_ready) GPout <= RxD_data;
async_transmitter TX(.clk(clk), .TxD(TxD), .TxD_start(RxD_data_ready), .TxD_data(GPin));
endmodule | module Comunicacao(
input clk,
input RxD,
output TxD,
output reg [7:0] GPout,
input [7:0] GPin
); |
wire RxD_data_ready;
wire [7:0] RxD_data;
async_receiver RX(.clk(clk), .RxD(RxD), .RxD_data_ready(RxD_data_ready), .RxD_data(RxD_data));
always @(posedge clk) if(RxD_data_ready) GPout <= RxD_data;
async_transmitter TX(.clk(clk), .TxD(TxD), .TxD_start(RxD_data_ready), .TxD_data(GPin));
endmodule | 0 |
5,829 | data/full_repos/permissive/114814262/IC 2015-2016/HARDWARE/[DEPRECATED] sistema_controle_alarme v1.0.0/[FPGA] sistema_para_controle_de_alarme/v1.0.0/sensorDePresenca.v | 114,814,262 | sensorDePresenca.v | v | 10 | 36 | [] | [] | [] | [(1, 9)] | null | null | 1: b'%Error: Cannot find file containing module: 2015-2016/HARDWARE/[DEPRECATED]\n ... Looked in:\n data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED]\n data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED].v\n data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED].sv\n 2015-2016/HARDWARE/[DEPRECATED]\n 2015-2016/HARDWARE/[DEPRECATED].v\n 2015-2016/HARDWARE/[DEPRECATED].sv\n obj_dir/2015-2016/HARDWARE/[DEPRECATED]\n obj_dir/2015-2016/HARDWARE/[DEPRECATED].v\n obj_dir/2015-2016/HARDWARE/[DEPRECATED].sv\n%Error: Cannot find file containing module: sistema_controle_alarme\n%Error: Cannot find file containing module: v1.0.0/[FPGA]\n%Error: Cannot find file containing module: sistema_para_controle_de_alarme/v1.0.0,data/full_repos/permissive/114814262\n%Error: Cannot find file containing module: data/full_repos/permissive/114814262/IC\n%Error: Cannot find file containing module: sistema_para_controle_de_alarme/v1.0.0/sensorDePresenca.v\n%Error: Exiting due to 6 error(s)\n' | 6,620 | module | module sensorDePresenca(sinal,led);
input sinal;
output led;
wire led;
assign led=sinal;
endmodule | module sensorDePresenca(sinal,led); |
input sinal;
output led;
wire led;
assign led=sinal;
endmodule | 0 |
5,831 | data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/addPC.v | 114,882,688 | addPC.v | v | 52 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/addPC.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n const_defination.v\n const_defination.v.v\n const_defination.v.sv\n obj_dir/const_defination.v\n obj_dir/const_defination.v.v\n obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/addPC.v:25: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] f_pc,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/addPC.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`digitsBus] f_pc,\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/addPC.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire need_valc,\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/addPC.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg[`digitsBus] valPC\n ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/addPC.v:28: Define or directive not defined: \'`digitsBus\'\n output reg[`digitsBus] valPC\n ^~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n' | 6,677 | module | module addPC(
input wire[`digitsBus] f_pc,
input wire need_regids,
input wire need_valc,
output reg[`digitsBus] valPC
);
always@(*)
begin
if(need_regids==1&&need_valc==1)
begin
valPC=f_pc+10;
end
else if(need_valc==1)
begin
valPC=f_pc+9;
end
else if(need_regids==1)
begin
valPC=f_pc+2;
end
else
begin
valPC=f_pc+1;
end
end
endmodule | module addPC(
input wire[`digitsBus] f_pc,
input wire need_regids,
input wire need_valc,
output reg[`digitsBus] valPC
); |
always@(*)
begin
if(need_regids==1&&need_valc==1)
begin
valPC=f_pc+10;
end
else if(need_valc==1)
begin
valPC=f_pc+9;
end
else if(need_regids==1)
begin
valPC=f_pc+2;
end
else
begin
valPC=f_pc+1;
end
end
endmodule | 1 |
5,832 | data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v | 114,882,688 | ALU.v | v | 120 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n const_defination.v\n const_defination.v.v\n const_defination.v.sv\n obj_dir/const_defination.v\n obj_dir/const_defination.v.v\n obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:25: Define or directive not defined: \'`digitsBus\'\n input wire [`digitsBus] ALUB,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`digitsBus] ALUB,\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:26: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] ALUA,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg[`digitsBus] valE,\n ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:28: Define or directive not defined: \'`digitsBus\'\n output reg[`digitsBus] valE,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:30: syntax error, unexpected \')\', expecting \',\' or \';\'\n );\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:34: syntax error, unexpected always\n always@(*)\n ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:38: Define or directive not defined: \'`ADD\'\n `ADD:\n ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:59: Define or directive not defined: \'`SUB\'\n `SUB:\n ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:88: Define or directive not defined: \'`AND\'\n `AND:\n ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:100: Define or directive not defined: \'`XOR\'\n `XOR:\n ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:112: Define or directive not defined: \'`NO\'\n `NO:\n ^~~\n%Error: Exiting due to 13 error(s)\n' | 6,678 | module | module ALU(
input wire [`digitsBus] ALUB,
input wire[`digitsBus] ALUA,
input wire[2:0] fun,
output reg[`digitsBus] valE,
output reg[2:0] cc
);
reg[64:0] temp;
reg[64:0] tempin;
always@(*)
begin
tempin=ALUB;
case(fun)
`ADD:
begin
temp=ALUA+tempin;
valE=temp;
if(temp[64]==1)
begin
cc[1]=1'b1;
end
else
begin
cc[1]=1'b0;
end
if(valE==0)
begin
cc[0]=1;
end
else
begin
cc[0]=0;
end
end
`SUB:
begin
temp=tempin-ALUA;
valE=temp[63:0];
if(temp[64]==1)
begin
cc[1]=1'b1;
end
else
begin
cc[1]=1'b0;
end
if(temp[63]==1)
begin
cc[2]=1;
end
else
begin
cc[2]=0;
end
if(valE==0)
begin
cc[0]=1;
end
else
begin
cc[0]=0;
end
end
`AND:
begin
valE=ALUA&ALUB;
if(valE==0)
begin
cc[0]=1;
end
else
begin
cc[0]=0;
end
end
`XOR:
begin
valE=ALUA^ALUB;
if(valE==0)
begin
cc[0]=1;
end
else
begin
cc[0]=0;
end
end
`NO:
begin
end
endcase
end
endmodule | module ALU(
input wire [`digitsBus] ALUB,
input wire[`digitsBus] ALUA,
input wire[2:0] fun,
output reg[`digitsBus] valE,
output reg[2:0] cc
); |
reg[64:0] temp;
reg[64:0] tempin;
always@(*)
begin
tempin=ALUB;
case(fun)
`ADD:
begin
temp=ALUA+tempin;
valE=temp;
if(temp[64]==1)
begin
cc[1]=1'b1;
end
else
begin
cc[1]=1'b0;
end
if(valE==0)
begin
cc[0]=1;
end
else
begin
cc[0]=0;
end
end
`SUB:
begin
temp=tempin-ALUA;
valE=temp[63:0];
if(temp[64]==1)
begin
cc[1]=1'b1;
end
else
begin
cc[1]=1'b0;
end
if(temp[63]==1)
begin
cc[2]=1;
end
else
begin
cc[2]=0;
end
if(valE==0)
begin
cc[0]=1;
end
else
begin
cc[0]=0;
end
end
`AND:
begin
valE=ALUA&ALUB;
if(valE==0)
begin
cc[0]=1;
end
else
begin
cc[0]=0;
end
end
`XOR:
begin
valE=ALUA^ALUB;
if(valE==0)
begin
cc[0]=1;
end
else
begin
cc[0]=0;
end
end
`NO:
begin
end
endcase
end
endmodule | 1 |
5,838 | data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v | 114,882,688 | control.v | v | 100 | 146 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n const_defination.v\n const_defination.v.v\n const_defination.v.sv\n obj_dir/const_defination.v\n obj_dir/const_defination.v.v\n obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:25: Define or directive not defined: \'`icodeBus\'\n input wire[`icodeBus] D_icode,E_icode,M_icode,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`icodeBus] D_icode,E_icode,M_icode,\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:26: Define or directive not defined: \'`regBus\'\n input wire[`regBus] d_srcA,d_srcB,\n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:27: Define or directive not defined: \'`regBus\'\n input wire[`regBus] E_dstM,\n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:29: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`statBus] m_stat,\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:29: Define or directive not defined: \'`statBus\'\n input wire[`statBus] m_stat,\n ^~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:31: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg D_bubble,E_bubble,M_bubble\n ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:32: syntax error, unexpected \')\', expecting \',\' or \';\'\n );\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:37: Define or directive not defined: \'`Ret\'\n if(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret||((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))||m_stat==`dmem_error)\n ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:37: Define or directive not defined: \'`Ret\'\n if(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret||((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))||m_stat==`dmem_error)\n ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:37: Define or directive not defined: \'`Ret\'\n if(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret||((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))||m_stat==`dmem_error)\n ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:37: Define or directive not defined: \'`Mrmovq\'\n if(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret||((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))||m_stat==`dmem_error)\n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:37: Define or directive not defined: \'`Popq\'\n if(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret||((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))||m_stat==`dmem_error)\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:37: Define or directive not defined: \'`dmem_error\'\n if(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret||((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))||m_stat==`dmem_error)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:50: Define or directive not defined: \'`Mrmovq\'\n if(((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))||m_stat==`dmem_error)\n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:50: Define or directive not defined: \'`Popq\'\n if(((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))||m_stat==`dmem_error)\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:50: Define or directive not defined: \'`dmem_error\'\n if(((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))||m_stat==`dmem_error)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:63: Define or directive not defined: \'`Mrmovq\'\n if(e_cnd==1||!((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))&&(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret))\n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:63: Define or directive not defined: \'`Popq\'\n if(e_cnd==1||!((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))&&(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret))\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:63: Define or directive not defined: \'`Ret\'\n if(e_cnd==1||!((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))&&(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret))\n ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:63: Define or directive not defined: \'`Ret\'\n if(e_cnd==1||!((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))&&(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret))\n ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:63: Define or directive not defined: \'`Ret\'\n if(e_cnd==1||!((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))&&(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret))\n ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:76: Define or directive not defined: \'`Mrmovq\'\n if(e_cnd==1||((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB)))\n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:76: Define or directive not defined: \'`Popq\'\n if(e_cnd==1||((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB)))\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:89: Define or directive not defined: \'`dmem_error\'\n if(m_stat==`dmem_error||m_stat==`stop||m_stat==`inst_invalid)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:89: Define or directive not defined: \'`stop\'\n if(m_stat==`dmem_error||m_stat==`stop||m_stat==`inst_invalid)\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/control.v:89: Define or directive not defined: \'`inst_invalid\'\n if(m_stat==`dmem_error||m_stat==`stop||m_stat==`inst_invalid)\n ^~~~~~~~~~~~~\n%Error: Exiting due to 28 error(s)\n' | 6,685 | module | module control(
input wire[`icodeBus] D_icode,E_icode,M_icode,
input wire[`regBus] d_srcA,d_srcB,
input wire[`regBus] E_dstM,
input wire e_cnd,
input wire[`statBus] m_stat,
output reg F_stall,D_stall,
output reg D_bubble,E_bubble,M_bubble
);
always@(*)
begin
if(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret||((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))||m_stat==`dmem_error)
begin
F_stall=1;
end
else
begin
F_stall=0;
end
end
always@(*)
begin
if(((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))||m_stat==`dmem_error)
begin
D_stall=1;
end
else
begin
D_stall=0;
end
end
always@(*)
begin
if(e_cnd==1||!((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))&&(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret))
begin
D_bubble=1;
end
else
begin
D_bubble=0;
end
end
always@(*)
begin
if(e_cnd==1||((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB)))
begin
E_bubble=1;
end
else
begin
E_bubble=0;
end
end
always@(*)
begin
if(m_stat==`dmem_error||m_stat==`stop||m_stat==`inst_invalid)
begin
M_bubble=1;
end
else
begin
M_bubble=0;
end
end
endmodule | module control(
input wire[`icodeBus] D_icode,E_icode,M_icode,
input wire[`regBus] d_srcA,d_srcB,
input wire[`regBus] E_dstM,
input wire e_cnd,
input wire[`statBus] m_stat,
output reg F_stall,D_stall,
output reg D_bubble,E_bubble,M_bubble
); |
always@(*)
begin
if(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret||((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))||m_stat==`dmem_error)
begin
F_stall=1;
end
else
begin
F_stall=0;
end
end
always@(*)
begin
if(((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))||m_stat==`dmem_error)
begin
D_stall=1;
end
else
begin
D_stall=0;
end
end
always@(*)
begin
if(e_cnd==1||!((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB))&&(D_icode==`Ret||E_icode==`Ret||M_icode==`Ret))
begin
D_bubble=1;
end
else
begin
D_bubble=0;
end
end
always@(*)
begin
if(e_cnd==1||((E_icode==`Mrmovq||E_icode==`Popq)&&(E_dstM==d_srcA||E_dstM==d_srcB)))
begin
E_bubble=1;
end
else
begin
E_bubble=0;
end
end
always@(*)
begin
if(m_stat==`dmem_error||m_stat==`stop||m_stat==`inst_invalid)
begin
M_bubble=1;
end
else
begin
M_bubble=0;
end
end
endmodule | 1 |
5,840 | data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v | 114,882,688 | decode.v | v | 107 | 91 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n const_defination.v\n const_defination.v.v\n const_defination.v.sv\n obj_dir/const_defination.v\n obj_dir/const_defination.v.v\n obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:25: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] d_rvalA,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`digitsBus] d_rvalA,\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:26: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] d_rvalB,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:27: Define or directive not defined: \'`icodeBus\'\n input wire[`icodeBus] icode,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:28: Define or directive not defined: \'`regBus\'\n input wire[`regBus] e_dstE,M_dstE,M_dstM,W_dstM,W_dstE, \n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:29: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] e_valE,m_valM,M_valE,W_valM,W_valE, \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:30: Define or directive not defined: \'`regBus\'\n input wire[`regBus] srcA,srcB,\n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:31: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] valP, \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:32: Define or directive not defined: \'`digitsBus\'\n output reg[`digitsBus] valA,valB\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:39: Define or directive not defined: \'`call\'\n `call:\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:43: Define or directive not defined: \'`jmp\'\n `jmp:\n ^~~~\n%Error: Exiting due to 12 error(s)\n' | 6,687 | module | module decode(
input wire[`digitsBus] d_rvalA,
input wire[`digitsBus] d_rvalB,
input wire[`icodeBus] icode,
input wire[`regBus] e_dstE,M_dstE,M_dstM,W_dstM,W_dstE,
input wire[`digitsBus] e_valE,m_valM,M_valE,W_valM,W_valE,
input wire[`regBus] srcA,srcB,
input wire[`digitsBus] valP,
output reg[`digitsBus] valA,valB
);
always@(*)
begin
case({icode,4'h0})
`call:
begin
valA=valP;
end
`jmp:
begin
valA=valP;
end
default:
begin
if(srcA==e_dstE)
begin
valA=e_valE;
end
else if(srcA==M_dstM)
begin
valA=m_valM;
end
else if(srcA==M_dstE)
begin
valA=M_valE;
end
else if(srcA==W_dstM)
begin
valA=W_valM;
end
else if(srcA==W_dstE)
begin
valA=W_valE;
end
else
begin
valA=d_rvalA;
end
end
endcase
end
always@(*)
begin
if(srcB==e_dstE)
begin
valB=e_valE;
end
else if(srcB==M_dstM)
begin
valB=m_valM;
end
else if(srcB==M_dstE)
begin
valB=M_valE;
end
else if(srcB==W_dstM)
begin
valB=W_valM;
end
else if(srcB==W_dstE)
begin
valB=W_valE;
end
else
begin
valB=d_rvalB;
end
end
endmodule | module decode(
input wire[`digitsBus] d_rvalA,
input wire[`digitsBus] d_rvalB,
input wire[`icodeBus] icode,
input wire[`regBus] e_dstE,M_dstE,M_dstM,W_dstM,W_dstE,
input wire[`digitsBus] e_valE,m_valM,M_valE,W_valM,W_valE,
input wire[`regBus] srcA,srcB,
input wire[`digitsBus] valP,
output reg[`digitsBus] valA,valB
); |
always@(*)
begin
case({icode,4'h0})
`call:
begin
valA=valP;
end
`jmp:
begin
valA=valP;
end
default:
begin
if(srcA==e_dstE)
begin
valA=e_valE;
end
else if(srcA==M_dstM)
begin
valA=m_valM;
end
else if(srcA==M_dstE)
begin
valA=M_valE;
end
else if(srcA==W_dstM)
begin
valA=W_valM;
end
else if(srcA==W_dstE)
begin
valA=W_valE;
end
else
begin
valA=d_rvalA;
end
end
endcase
end
always@(*)
begin
if(srcB==e_dstE)
begin
valB=e_valE;
end
else if(srcB==M_dstM)
begin
valB=m_valM;
end
else if(srcB==M_dstE)
begin
valB=M_valE;
end
else if(srcB==W_dstM)
begin
valB=W_valM;
end
else if(srcB==W_dstE)
begin
valB=W_valE;
end
else
begin
valB=d_rvalB;
end
end
endmodule | 1 |
5,841 | data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v | 114,882,688 | decodeReg.v | v | 70 | 89 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n const_defination.v\n const_defination.v.v\n const_defination.v.sv\n obj_dir/const_defination.v\n obj_dir/const_defination.v.v\n obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:26: Define or directive not defined: \'`icodeBus\'\n input wire[`icodeBus] icode,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:26: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`icodeBus] icode,\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:27: Define or directive not defined: \'`ifunBus\'\n input wire[`ifunBus] ifun,\n ^~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:28: Define or directive not defined: \'`icodeBus\'\n input wire[`icodeBus] reg1_read_src,reg2_read_src,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:29: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] valC,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:30: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] valP,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire bubble,stall, \n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:35: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg[`icodeBus] D_icode,\n ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:35: Define or directive not defined: \'`icodeBus\'\n output reg[`icodeBus] D_icode,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:36: Define or directive not defined: \'`ifunBus\'\n output reg[`ifunBus] D_ifun,\n ^~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:37: Define or directive not defined: \'`regBus\'\n output reg[`regBus] D_reg1_read_src,D_reg2_read_src,\n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:38: Define or directive not defined: \'`digitsBus\'\n output reg[`digitsBus] D_valC,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:39: Define or directive not defined: \'`digitsBus\'\n output reg[`digitsBus] D_valP,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:41: syntax error, unexpected \')\', expecting \',\' or \';\'\n );\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:46: Define or directive not defined: \'`stop\'\n else if(stat==`stop||stat==`inst_invalid||bubble==1)\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:46: Define or directive not defined: \'`inst_invalid\'\n else if(stat==`stop||stat==`inst_invalid||bubble==1)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:48: Define or directive not defined: \'`Nop\'\n D_icode<=`Nop;\n ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:50: Define or directive not defined: \'`readZero\'\n D_valP<=`readZero;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:51: Define or directive not defined: \'`NONE\'\n D_reg1_read_src<=`NONE;\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:52: Define or directive not defined: \'`NONE\'\n D_reg2_read_src<=`NONE;\n ^~~~~\n%Error: Exiting due to 21 error(s)\n' | 6,688 | module | module decodeReg(
input clk,
input wire[`icodeBus] icode,
input wire[`ifunBus] ifun,
input wire[`icodeBus] reg1_read_src,reg2_read_src,
input wire[`digitsBus] valC,
input wire[`digitsBus] valP,
input wire[2:0] stat,
input wire bubble,stall,
output reg[`icodeBus] D_icode,
output reg[`ifunBus] D_ifun,
output reg[`regBus] D_reg1_read_src,D_reg2_read_src,
output reg[`digitsBus] D_valC,
output reg[`digitsBus] D_valP,
output reg[2:0] D_stat
);
always@(posedge clk)
begin
if(stall==1)
begin end
else if(stat==`stop||stat==`inst_invalid||bubble==1)
begin
D_icode<=`Nop;
D_ifun<=0;
D_valP<=`readZero;
D_reg1_read_src<=`NONE;
D_reg2_read_src<=`NONE;
D_valP<=0;
D_valC<=0;
D_stat<=stat;
end
else
begin
D_icode<=icode;
D_ifun<=ifun;
D_valP<=valP;
D_reg1_read_src<=reg1_read_src;
D_reg2_read_src<=reg2_read_src;
D_valP<=valP;
D_valC<=valC;
D_stat<=stat;
end
end
endmodule | module decodeReg(
input clk,
input wire[`icodeBus] icode,
input wire[`ifunBus] ifun,
input wire[`icodeBus] reg1_read_src,reg2_read_src,
input wire[`digitsBus] valC,
input wire[`digitsBus] valP,
input wire[2:0] stat,
input wire bubble,stall,
output reg[`icodeBus] D_icode,
output reg[`ifunBus] D_ifun,
output reg[`regBus] D_reg1_read_src,D_reg2_read_src,
output reg[`digitsBus] D_valC,
output reg[`digitsBus] D_valP,
output reg[2:0] D_stat
); |
always@(posedge clk)
begin
if(stall==1)
begin end
else if(stat==`stop||stat==`inst_invalid||bubble==1)
begin
D_icode<=`Nop;
D_ifun<=0;
D_valP<=`readZero;
D_reg1_read_src<=`NONE;
D_reg2_read_src<=`NONE;
D_valP<=0;
D_valC<=0;
D_stat<=stat;
end
else
begin
D_icode<=icode;
D_ifun<=ifun;
D_valP<=valP;
D_reg1_read_src<=reg1_read_src;
D_reg2_read_src<=reg2_read_src;
D_valP<=valP;
D_valC<=valC;
D_stat<=stat;
end
end
endmodule | 1 |
5,844 | data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v | 114,882,688 | introduction_memory.v | v | 52 | 188 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n const_defination.v\n const_defination.v.v\n const_defination.v.sv\n obj_dir/const_defination.v\n obj_dir/const_defination.v.v\n obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:25: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] pc,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`digitsBus] pc,\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:26: Define or directive not defined: \'`MaxIntroduction\'\n output reg[`MaxIntroduction] intd,\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:30: Define or directive not defined: \'`introduction_memory_size\'\n reg[7:0] intds[`introduction_memory_size]; \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:31: syntax error, unexpected initial\n initial $readmemh ( "E:/vivado project/myY-86/test.txt",intds ); \n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:35: Define or directive not defined: \'`introduction_memory_length\'\n if(pc<`introduction_memory_length)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:40: Define or directive not defined: \'`introduction_memory_length\'\n else if(pc>`introduction_memory_length)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n' | 6,691 | module | module introduction_memory(
input wire[`digitsBus] pc,
output reg[`MaxIntroduction] intd,
output reg imem_error
);
reg[7:0] intds[`introduction_memory_size];
initial $readmemh ( "E:/vivado project/myY-86/test.txt",intds );
always@(*)
begin
if(pc<`introduction_memory_length)
begin
intd={intds[pc][7:0],intds[pc+1][7:0],intds[pc+2][7:0],intds[pc+3][7:0],intds[pc+4][7:0],intds[pc+5][7:0],intds[pc+6][7:0],intds[pc+7][7:0],intds[pc+8][7:0],intds[pc+9][7:0]};
imem_error=0;
end
else if(pc>`introduction_memory_length)
begin
imem_error=1;
end
else
begin
intd=80'h10000000000000000000;
imem_error=0;
end
end
endmodule | module introduction_memory(
input wire[`digitsBus] pc,
output reg[`MaxIntroduction] intd,
output reg imem_error
); |
reg[7:0] intds[`introduction_memory_size];
initial $readmemh ( "E:/vivado project/myY-86/test.txt",intds );
always@(*)
begin
if(pc<`introduction_memory_length)
begin
intd={intds[pc][7:0],intds[pc+1][7:0],intds[pc+2][7:0],intds[pc+3][7:0],intds[pc+4][7:0],intds[pc+5][7:0],intds[pc+6][7:0],intds[pc+7][7:0],intds[pc+8][7:0],intds[pc+9][7:0]};
imem_error=0;
end
else if(pc>`introduction_memory_length)
begin
imem_error=1;
end
else
begin
intd=80'h10000000000000000000;
imem_error=0;
end
end
endmodule | 1 |
5,845 | data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v | 114,882,688 | memOperation.v | v | 110 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n const_defination.v\n const_defination.v.v\n const_defination.v.sv\n obj_dir/const_defination.v\n obj_dir/const_defination.v.v\n obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:25: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] valE,valA,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`digitsBus] valE,valA,\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:26: Define or directive not defined: \'`icodeBus\'\n input wire[`icodeBus] icode,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:27: Define or directive not defined: \'`digitsBus\'\n output reg[`digitsBus] dstM,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:29: syntax error, unexpected \')\', expecting \',\' or \';\'\n );\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:34: Define or directive not defined: \'`rmmovq\'\n `rmmovq:\n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:36: Define or directive not defined: \'`mrmovq\'\n if({icode,4\'h0}==`mrmovq)\n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:48: Define or directive not defined: \'`pushq\'\n `pushq:\n ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:50: Define or directive not defined: \'`mrmovq\'\n if({icode,4\'h0}==`mrmovq)\n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:62: Define or directive not defined: \'`call\'\n `call:\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:64: Define or directive not defined: \'`mrmovq\'\n if({icode,4\'h0}==`mrmovq)\n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:76: Define or directive not defined: \'`mrmovq\'\n `mrmovq:\n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:78: Define or directive not defined: \'`mrmovq\'\n if({icode,4\'h0}==`mrmovq)\n ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:90: Define or directive not defined: \'`popq\'\n `popq:\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:96: Define or directive not defined: \'`ret\'\n `ret:\n ^~~~\n%Error: Exiting due to 16 error(s)\n' | 6,692 | module | module memOperation(
input wire[`digitsBus] valE,valA,
input wire[`icodeBus] icode,
output reg[`digitsBus] dstM,
output reg enabler,enablew
);
always@(*)
begin
case({icode,4'h0})
`rmmovq:
begin
if({icode,4'h0}==`mrmovq)
begin
enablew<=0;
enabler<=1;
end
else
begin
enablew<=1;
enabler<=0;
end
dstM<=valE;
end
`pushq:
begin
if({icode,4'h0}==`mrmovq)
begin
enablew<=0;
enabler<=1;
end
else
begin
enablew<=1;
enabler<=0;
end
dstM<=valE;
end
`call:
begin
if({icode,4'h0}==`mrmovq)
begin
enablew<=0;
enabler<=1;
end
else
begin
enablew<=1;
enabler<=0;
end
dstM<=valE;
end
`mrmovq:
begin
if({icode,4'h0}==`mrmovq)
begin
enablew<=0;
enabler<=1;
end
else
begin
enablew<=1;
enabler<=0;
end
dstM<=valE;
end
`popq:
begin
dstM<=valA;
enablew<=0;
enabler<=1;
end
`ret:
begin
dstM<=valA;
enablew<=0;
enabler<=1;
end
default:
begin
enablew<=0;
enabler<=0;
end
endcase
end
endmodule | module memOperation(
input wire[`digitsBus] valE,valA,
input wire[`icodeBus] icode,
output reg[`digitsBus] dstM,
output reg enabler,enablew
); |
always@(*)
begin
case({icode,4'h0})
`rmmovq:
begin
if({icode,4'h0}==`mrmovq)
begin
enablew<=0;
enabler<=1;
end
else
begin
enablew<=1;
enabler<=0;
end
dstM<=valE;
end
`pushq:
begin
if({icode,4'h0}==`mrmovq)
begin
enablew<=0;
enabler<=1;
end
else
begin
enablew<=1;
enabler<=0;
end
dstM<=valE;
end
`call:
begin
if({icode,4'h0}==`mrmovq)
begin
enablew<=0;
enabler<=1;
end
else
begin
enablew<=1;
enabler<=0;
end
dstM<=valE;
end
`mrmovq:
begin
if({icode,4'h0}==`mrmovq)
begin
enablew<=0;
enabler<=1;
end
else
begin
enablew<=1;
enabler<=0;
end
dstM<=valE;
end
`popq:
begin
dstM<=valA;
enablew<=0;
enabler<=1;
end
`ret:
begin
dstM<=valA;
enablew<=0;
enabler<=1;
end
default:
begin
enablew<=0;
enabler<=0;
end
endcase
end
endmodule | 1 |
5,847 | data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/m_stat.v | 114,882,688 | m_stat.v | v | 42 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/m_stat.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n const_defination.v\n const_defination.v.v\n const_defination.v.sv\n obj_dir/const_defination.v\n obj_dir/const_defination.v.v\n obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/m_stat.v:26: Define or directive not defined: \'`statBus\'\n input wire[`statBus] stat,\n ^~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/m_stat.v:26: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`statBus] stat,\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/m_stat.v:27: Define or directive not defined: \'`statBus\'\n output reg[`statBus] m_stat\n ^~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/m_stat.v:34: Define or directive not defined: \'`dmem_error\'\n m_stat=`dmem_error;\n ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n' | 6,694 | module | module m_stat(
input wire dmem_error,
input wire[`statBus] stat,
output reg[`statBus] m_stat
);
always@(*)
begin
if(dmem_error==1)
begin
m_stat=`dmem_error;
end
else
begin
m_stat=stat;
end
end
endmodule | module m_stat(
input wire dmem_error,
input wire[`statBus] stat,
output reg[`statBus] m_stat
); |
always@(*)
begin
if(dmem_error==1)
begin
m_stat=`dmem_error;
end
else
begin
m_stat=stat;
end
end
endmodule | 1 |
5,848 | data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/predictPC.v | 114,882,688 | predictPC.v | v | 58 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/predictPC.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n const_defination.v\n const_defination.v.v\n const_defination.v.sv\n obj_dir/const_defination.v\n obj_dir/const_defination.v.v\n obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/predictPC.v:25: Define or directive not defined: \'`icodeBus\'\n input wire[`icodeBus] icode,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/predictPC.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`icodeBus] icode,\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/predictPC.v:26: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] valC,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/predictPC.v:27: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] valP,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/predictPC.v:28: Define or directive not defined: \'`digitsBus\'\n output reg[`digitsBus] pc\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/predictPC.v:34: Define or directive not defined: \'`jmp\'\n `jmp:\n ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/predictPC.v:38: Define or directive not defined: \'`call\'\n `call:\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/predictPC.v:42: Define or directive not defined: \'`halt\'\n `halt:\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/predictPC.v:46: Define or directive not defined: \'`ret\'\n `ret:\n ^~~~\n%Error: Exiting due to 10 error(s)\n' | 6,695 | module | module predictPC(
input wire[`icodeBus] icode,
input wire[`digitsBus] valC,
input wire[`digitsBus] valP,
output reg[`digitsBus] pc
);
always@(*)
begin
case({icode,4'h0})
`jmp:
begin
pc=valC;
end
`call:
begin
pc=valC;
end
`halt:
begin
pc=valP-1;
end
`ret:
begin
pc=valP-1;
end
default:
begin
pc=valP;
end
endcase
end
endmodule | module predictPC(
input wire[`icodeBus] icode,
input wire[`digitsBus] valC,
input wire[`digitsBus] valP,
output reg[`digitsBus] pc
); |
always@(*)
begin
case({icode,4'h0})
`jmp:
begin
pc=valC;
end
`call:
begin
pc=valC;
end
`halt:
begin
pc=valP-1;
end
`ret:
begin
pc=valP-1;
end
default:
begin
pc=valP;
end
endcase
end
endmodule | 1 |
5,850 | data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v | 114,882,688 | regFile.v | v | 70 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n const_defination.v\n const_defination.v.v\n const_defination.v.sv\n obj_dir/const_defination.v\n obj_dir/const_defination.v.v\n obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:27: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] M,E, \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`digitsBus] M,E, \n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:29: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg[63:0] d_rvalA,d_rvalB \n ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:30: syntax error, unexpected \')\', expecting \',\' or \';\'\n );\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:35: syntax error, unexpected always\n always@(posedge clk)\n ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:37: Define or directive not defined: \'`NONE\'\n if(dstM!=`NONE)\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:46: Define or directive not defined: \'`NONE\'\n if(dstE!=`NONE)\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:55: Define or directive not defined: \'`NONE\'\n if(srcA!=`NONE)\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:64: Define or directive not defined: \'`NONE\'\n if(srcB!=`NONE)\n ^~~~~\n%Error: Exiting due to 10 error(s)\n' | 6,697 | module | module regFile(
input wire clk,
input wire[3:0] dstE,dstM,
input wire[`digitsBus] M,E,
input wire[3:0] srcA,srcB,
output reg[63:0] d_rvalA,d_rvalB
);
reg[63:0] regs[0:15];
always@(posedge clk)
begin
if(dstM!=`NONE)
begin
regs[dstM]=M;
end
end
always@(posedge clk)
begin
if(dstE!=`NONE)
begin
regs[dstE]=E;
end
end
always@(*)
begin
if(srcA!=`NONE)
begin
d_rvalA<=regs[srcA];
end
end
always@(*)
begin
if(srcB!=`NONE)
begin
d_rvalB<=regs[srcB];
end
end
endmodule | module regFile(
input wire clk,
input wire[3:0] dstE,dstM,
input wire[`digitsBus] M,E,
input wire[3:0] srcA,srcB,
output reg[63:0] d_rvalA,d_rvalB
); |
reg[63:0] regs[0:15];
always@(posedge clk)
begin
if(dstM!=`NONE)
begin
regs[dstM]=M;
end
end
always@(posedge clk)
begin
if(dstE!=`NONE)
begin
regs[dstE]=E;
end
end
always@(*)
begin
if(srcA!=`NONE)
begin
d_rvalA<=regs[srcA];
end
end
always@(*)
begin
if(srcB!=`NONE)
begin
d_rvalB<=regs[srcB];
end
end
endmodule | 1 |
5,851 | data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v | 114,882,688 | selectPC.v | v | 58 | 99 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n const_defination.v\n const_defination.v.v\n const_defination.v.sv\n obj_dir/const_defination.v\n obj_dir/const_defination.v.v\n obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:25: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] predPC,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`digitsBus] predPC,\n ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:26: Define or directive not defined: \'`icodeBus\'\n input wire[`icodeBus] M_icode,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:28: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`digitsBus] M_valA,\n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:28: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] M_valA,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:29: Define or directive not defined: \'`icodeBus\'\n input wire[`icodeBus] W_icode,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:30: Define or directive not defined: \'`digitsBus\'\n input wire[`digitsBus] W_valM,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:31: Define or directive not defined: \'`digitsBus\'\n output reg[`digitsBus] pc\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:35: Define or directive not defined: \'`jmp\'\n if({M_icode,4\'h0}==`jmp)\n ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:46: Define or directive not defined: \'`ret\'\n else if({W_icode,4\'h0}==`ret)\n ^~~~\n%Error: Exiting due to 11 error(s)\n' | 6,698 | module | module selectPC(
input wire[`digitsBus] predPC,
input wire[`icodeBus] M_icode,
input wire M_Cnd,
input wire[`digitsBus] M_valA,
input wire[`icodeBus] W_icode,
input wire[`digitsBus] W_valM,
output reg[`digitsBus] pc
);
always@(*)
begin
if({M_icode,4'h0}==`jmp)
begin
if(M_Cnd==0)
begin
pc<=predPC;
end
else
begin
pc<=M_valA;
end
end
else if({W_icode,4'h0}==`ret)
begin
pc<=W_valM;
end
else
begin
pc<=predPC;
end
end
endmodule | module selectPC(
input wire[`digitsBus] predPC,
input wire[`icodeBus] M_icode,
input wire M_Cnd,
input wire[`digitsBus] M_valA,
input wire[`icodeBus] W_icode,
input wire[`digitsBus] W_valM,
output reg[`digitsBus] pc
); |
always@(*)
begin
if({M_icode,4'h0}==`jmp)
begin
if(M_Cnd==0)
begin
pc<=predPC;
end
else
begin
pc<=M_valA;
end
end
else if({W_icode,4'h0}==`ret)
begin
pc<=W_valM;
end
else
begin
pc<=predPC;
end
end
endmodule | 1 |
5,855 | data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new/sopc_tb.v | 114,896,735 | sopc_tb.v | v | 25 | 36 | [] | [] | [] | null | line:17: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new/sopc_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n forever #5 clk <= ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new/sopc_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #5 rst <= 1\'B0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new/sopc_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #1000 $stop;\n ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new/sopc_tb.v:20: Cannot find file containing module: \'sopc\'\n sopc y86_sopc\n ^~~~\n ... Looked in:\n data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new,data/full_repos/permissive/114896735/sopc\n data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new,data/full_repos/permissive/114896735/sopc.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new,data/full_repos/permissive/114896735/sopc.sv\n sopc\n sopc.v\n sopc.sv\n obj_dir/sopc\n obj_dir/sopc.v\n obj_dir/sopc.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,702 | module | module sopc_tb;
reg clk;
reg rst;
initial
begin
clk <= 1'B0;
forever #5 clk <= ~clk;
end
initial
begin
rst <= 1'B1;
#5 rst <= 1'B0;
#1000 $stop;
end
sopc y86_sopc
(
.clk(clk),
.rst(rst)
);
endmodule | module sopc_tb; |
reg clk;
reg rst;
initial
begin
clk <= 1'B0;
forever #5 clk <= ~clk;
end
initial
begin
rst <= 1'B1;
#5 rst <= 1'B0;
#1000 $stop;
end
sopc y86_sopc
(
.clk(clk),
.rst(rst)
);
endmodule | 11 |
5,856 | data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v | 114,896,735 | alu.v | v | 58 | 79 | [] | [] | [] | [(115, 169)] | null | null | 1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:4: Define or directive not defined: \'`DATA_BUS\'\n input wire [`DATA_BUS] aluA_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:4: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`DATA_BUS] aluA_i,\n ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:5: Define or directive not defined: \'`DATA_BUS\'\n input wire [`DATA_BUS] aluB_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:6: Define or directive not defined: \'`IFUN_BUS\'\n input wire [`IFUN_BUS] fun_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:8: Define or directive not defined: \'`DATA_BUS\'\n output reg [`DATA_BUS] e_valE_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:10: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg SF_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:11: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg OF_o\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:17: Define or directive not defined: \'`ADDQ\'\n `ADDQ:\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:21: Define or directive not defined: \'`DATA_WIDTH\'\n SF_o = e_valE_o[`DATA_WIDTH-1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:22: Define or directive not defined: \'`DATA_WIDTH\'\n OF_o = (aluA_i[`DATA_WIDTH-1] == aluB_i[`DATA_WIDTH-1]) &&\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:22: Define or directive not defined: \'`DATA_WIDTH\'\n OF_o = (aluA_i[`DATA_WIDTH-1] == aluB_i[`DATA_WIDTH-1]) &&\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:23: Define or directive not defined: \'`DATA_WIDTH\'\n (aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:23: Define or directive not defined: \'`DATA_WIDTH\'\n (aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:25: Define or directive not defined: \'`SUBQ\'\n `SUBQ:\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:29: Define or directive not defined: \'`DATA_WIDTH\'\n SF_o = e_valE_o[`DATA_WIDTH-1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:30: Define or directive not defined: \'`DATA_WIDTH\'\n OF_o = (aluA_i[`DATA_WIDTH-1] != aluB_i[`DATA_WIDTH-1]) &&\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:30: Define or directive not defined: \'`DATA_WIDTH\'\n OF_o = (aluA_i[`DATA_WIDTH-1] != aluB_i[`DATA_WIDTH-1]) &&\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:31: Define or directive not defined: \'`DATA_WIDTH\'\n (aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:31: Define or directive not defined: \'`DATA_WIDTH\'\n (aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:33: Define or directive not defined: \'`ANDQ\'\n `ANDQ:\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:37: Define or directive not defined: \'`DATA_WIDTH\'\n SF_o = e_valE_o[`DATA_WIDTH-1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:38: Define or directive not defined: \'`FALSE\'\n OF_o = `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:40: Define or directive not defined: \'`XORQ\'\n `XORQ:\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:44: Define or directive not defined: \'`DATA_WIDTH\'\n SF_o = e_valE_o[`DATA_WIDTH-1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:45: Define or directive not defined: \'`FALSE\'\n OF_o = `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:49: Define or directive not defined: \'`DATA_ZERO\'\n e_valE_o = `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:50: Define or directive not defined: \'`FALSE\'\n ZF_o = `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:51: Define or directive not defined: \'`FALSE\'\n SF_o = `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:52: Define or directive not defined: \'`FALSE\'\n OF_o = `FALSE;\n ^~~~~~\n%Error: Exiting due to 30 error(s)\n' | 6,703 | module | module alu(
input wire [`DATA_BUS] aluA_i,
input wire [`DATA_BUS] aluB_i,
input wire [`IFUN_BUS] fun_i,
output reg [`DATA_BUS] e_valE_o,
output reg ZF_o,
output reg SF_o,
output reg OF_o
);
always @(*)
begin
case(fun_i)
`ADDQ:
begin
e_valE_o = aluA_i + aluB_i;
ZF_o = e_valE_o == 0;
SF_o = e_valE_o[`DATA_WIDTH-1];
OF_o = (aluA_i[`DATA_WIDTH-1] == aluB_i[`DATA_WIDTH-1]) &&
(aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);
end
`SUBQ:
begin
e_valE_o = aluA_i - aluB_i;
ZF_o = e_valE_o == 0;
SF_o = e_valE_o[`DATA_WIDTH-1];
OF_o = (aluA_i[`DATA_WIDTH-1] != aluB_i[`DATA_WIDTH-1]) &&
(aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);
end
`ANDQ:
begin
e_valE_o = aluA_i & aluB_i;
ZF_o = e_valE_o == 0;
SF_o = e_valE_o[`DATA_WIDTH-1];
OF_o = `FALSE;
end
`XORQ:
begin
e_valE_o = aluA_i ^ aluB_i;
ZF_o = e_valE_o == 0;
SF_o = e_valE_o[`DATA_WIDTH-1];
OF_o = `FALSE;
end
default:
begin
e_valE_o = `DATA_ZERO;
ZF_o = `FALSE;
SF_o = `FALSE;
OF_o = `FALSE;
end
endcase
end
endmodule | module alu(
input wire [`DATA_BUS] aluA_i,
input wire [`DATA_BUS] aluB_i,
input wire [`IFUN_BUS] fun_i,
output reg [`DATA_BUS] e_valE_o,
output reg ZF_o,
output reg SF_o,
output reg OF_o
); |
always @(*)
begin
case(fun_i)
`ADDQ:
begin
e_valE_o = aluA_i + aluB_i;
ZF_o = e_valE_o == 0;
SF_o = e_valE_o[`DATA_WIDTH-1];
OF_o = (aluA_i[`DATA_WIDTH-1] == aluB_i[`DATA_WIDTH-1]) &&
(aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);
end
`SUBQ:
begin
e_valE_o = aluA_i - aluB_i;
ZF_o = e_valE_o == 0;
SF_o = e_valE_o[`DATA_WIDTH-1];
OF_o = (aluA_i[`DATA_WIDTH-1] != aluB_i[`DATA_WIDTH-1]) &&
(aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);
end
`ANDQ:
begin
e_valE_o = aluA_i & aluB_i;
ZF_o = e_valE_o == 0;
SF_o = e_valE_o[`DATA_WIDTH-1];
OF_o = `FALSE;
end
`XORQ:
begin
e_valE_o = aluA_i ^ aluB_i;
ZF_o = e_valE_o == 0;
SF_o = e_valE_o[`DATA_WIDTH-1];
OF_o = `FALSE;
end
default:
begin
e_valE_o = `DATA_ZERO;
ZF_o = `FALSE;
SF_o = `FALSE;
OF_o = `FALSE;
end
endcase
end
endmodule | 11 |
5,857 | data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v | 114,896,735 | alu_args.v | v | 95 | 50 | [] | [] | [] | [(115, 207)] | null | null | 1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:4: Define or directive not defined: \'`ICODE_BUS\'\n input wire [`ICODE_BUS] E_icode_i,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:4: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`ICODE_BUS] E_icode_i,\n ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:5: Define or directive not defined: \'`IFUN_BUS\'\n input wire [`IFUN_BUS] E_ifun_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:6: Define or directive not defined: \'`DATA_BUS\'\n input wire [`DATA_BUS] E_valC_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:7: Define or directive not defined: \'`DATA_BUS\'\n input wire [`DATA_BUS] E_valA_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:8: Define or directive not defined: \'`DATA_BUS\'\n input wire [`DATA_BUS] E_valB_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:10: Define or directive not defined: \'`DATA_BUS\'\n output reg [`DATA_BUS] aluA_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:11: Define or directive not defined: \'`DATA_BUS\'\n output reg [`DATA_BUS] aluB_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:12: Define or directive not defined: \'`IFUN_BUS\'\n output reg [`IFUN_BUS] fun_o\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:18: Define or directive not defined: \'`CXX\'\n `CXX:\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:21: Define or directive not defined: \'`DATA_ZERO\'\n aluB_o = `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:22: Define or directive not defined: \'`ADDQ\'\n fun_o = `ADDQ;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:24: Define or directive not defined: \'`IXX\'\n `IXX:\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:27: Define or directive not defined: \'`IRMOVQ\'\n if(E_ifun_i == `IRMOVQ)\n ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:29: Define or directive not defined: \'`DATA_ZERO\'\n aluA_o = `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:30: Define or directive not defined: \'`ADDQ\'\n fun_o = `ADDQ;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:38: Define or directive not defined: \'`OPQ\'\n `OPQ:\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:44: Define or directive not defined: \'`RMMOVQ\'\n `RMMOVQ:\n ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:48: Define or directive not defined: \'`ADDQ\'\n fun_o = `ADDQ;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:50: Define or directive not defined: \'`MRMOVQ\'\n `MRMOVQ:\n ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:54: Define or directive not defined: \'`ADDQ\'\n fun_o = `ADDQ;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:56: Define or directive not defined: \'`JXX\'\n `JXX:\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:58: Define or directive not defined: \'`DATA_ZERO\'\n aluA_o = `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:59: Define or directive not defined: \'`DATA_ZERO\'\n aluB_o = `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:60: Define or directive not defined: \'`NOPQ\'\n fun_o = `NOPQ;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:62: Define or directive not defined: \'`CALL\'\n `CALL:\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:65: Define or directive not defined: \'`DATA_WIDTH\'\n aluB_o = `DATA_WIDTH\'H8;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:66: Define or directive not defined: \'`SUBQ\'\n fun_o = `SUBQ;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:68: Define or directive not defined: \'`RET\'\n `RET:\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:71: Define or directive not defined: \'`DATA_WIDTH\'\n aluB_o = `DATA_WIDTH\'H8;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:72: Define or directive not defined: \'`ADDQ\'\n fun_o = `ADDQ;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:74: Define or directive not defined: \'`PUSHQ\'\n `PUSHQ:\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:77: Define or directive not defined: \'`DATA_WIDTH\'\n aluB_o = `DATA_WIDTH\'H8;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:78: Define or directive not defined: \'`SUBQ\'\n fun_o = `SUBQ;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:80: Define or directive not defined: \'`POPQ\'\n `POPQ:\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:83: Define or directive not defined: \'`DATA_WIDTH\'\n aluB_o = `DATA_WIDTH\'H8;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:84: Define or directive not defined: \'`ADDQ\'\n fun_o = `ADDQ;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:88: Define or directive not defined: \'`DATA_ZERO\'\n aluA_o = `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:89: Define or directive not defined: \'`DATA_ZERO\'\n aluB_o = `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu_args.v:90: Define or directive not defined: \'`NOPQ\'\n fun_o = `NOPQ;\n ^~~~~\n%Error: Exiting due to 41 error(s)\n' | 6,704 | module | module alu_args(
input wire [`ICODE_BUS] E_icode_i,
input wire [`IFUN_BUS] E_ifun_i,
input wire [`DATA_BUS] E_valC_i,
input wire [`DATA_BUS] E_valA_i,
input wire [`DATA_BUS] E_valB_i,
output reg [`DATA_BUS] aluA_o,
output reg [`DATA_BUS] aluB_o,
output reg [`IFUN_BUS] fun_o
);
always @(*)
begin
case(E_icode_i)
`CXX:
begin
aluA_o = E_valA_i;
aluB_o = `DATA_ZERO;
fun_o = `ADDQ;
end
`IXX:
begin
aluB_o = E_valC_i;
if(E_ifun_i == `IRMOVQ)
begin
aluA_o = `DATA_ZERO;
fun_o = `ADDQ;
end
else
begin
aluA_o = E_valB_i;
fun_o = E_ifun_i - 1;
end
end
`OPQ:
begin
aluA_o = E_valB_i;
aluB_o = E_valA_i;
fun_o = E_ifun_i;
end
`RMMOVQ:
begin
aluA_o = E_valB_i;
aluB_o = E_valC_i;
fun_o = `ADDQ;
end
`MRMOVQ:
begin
aluA_o = E_valA_i;
aluB_o = E_valC_i;
fun_o = `ADDQ;
end
`JXX:
begin
aluA_o = `DATA_ZERO;
aluB_o = `DATA_ZERO;
fun_o = `NOPQ;
end
`CALL:
begin
aluA_o = E_valB_i;
aluB_o = `DATA_WIDTH'H8;
fun_o = `SUBQ;
end
`RET:
begin
aluA_o = E_valB_i;
aluB_o = `DATA_WIDTH'H8;
fun_o = `ADDQ;
end
`PUSHQ:
begin
aluA_o = E_valB_i;
aluB_o = `DATA_WIDTH'H8;
fun_o = `SUBQ;
end
`POPQ:
begin
aluA_o = E_valB_i;
aluB_o = `DATA_WIDTH'H8;
fun_o = `ADDQ;
end
default:
begin
aluA_o = `DATA_ZERO;
aluB_o = `DATA_ZERO;
fun_o = `NOPQ;
end
endcase
end
endmodule | module alu_args(
input wire [`ICODE_BUS] E_icode_i,
input wire [`IFUN_BUS] E_ifun_i,
input wire [`DATA_BUS] E_valC_i,
input wire [`DATA_BUS] E_valA_i,
input wire [`DATA_BUS] E_valB_i,
output reg [`DATA_BUS] aluA_o,
output reg [`DATA_BUS] aluB_o,
output reg [`IFUN_BUS] fun_o
); |
always @(*)
begin
case(E_icode_i)
`CXX:
begin
aluA_o = E_valA_i;
aluB_o = `DATA_ZERO;
fun_o = `ADDQ;
end
`IXX:
begin
aluB_o = E_valC_i;
if(E_ifun_i == `IRMOVQ)
begin
aluA_o = `DATA_ZERO;
fun_o = `ADDQ;
end
else
begin
aluA_o = E_valB_i;
fun_o = E_ifun_i - 1;
end
end
`OPQ:
begin
aluA_o = E_valB_i;
aluB_o = E_valA_i;
fun_o = E_ifun_i;
end
`RMMOVQ:
begin
aluA_o = E_valB_i;
aluB_o = E_valC_i;
fun_o = `ADDQ;
end
`MRMOVQ:
begin
aluA_o = E_valA_i;
aluB_o = E_valC_i;
fun_o = `ADDQ;
end
`JXX:
begin
aluA_o = `DATA_ZERO;
aluB_o = `DATA_ZERO;
fun_o = `NOPQ;
end
`CALL:
begin
aluA_o = E_valB_i;
aluB_o = `DATA_WIDTH'H8;
fun_o = `SUBQ;
end
`RET:
begin
aluA_o = E_valB_i;
aluB_o = `DATA_WIDTH'H8;
fun_o = `ADDQ;
end
`PUSHQ:
begin
aluA_o = E_valB_i;
aluB_o = `DATA_WIDTH'H8;
fun_o = `SUBQ;
end
`POPQ:
begin
aluA_o = E_valB_i;
aluB_o = `DATA_WIDTH'H8;
fun_o = `ADDQ;
end
default:
begin
aluA_o = `DATA_ZERO;
aluB_o = `DATA_ZERO;
fun_o = `NOPQ;
end
endcase
end
endmodule | 11 |
5,864 | data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v | 114,896,735 | fetch_reg.v | v | 32 | 42 | [] | [] | [] | [(115, 143)] | null | null | 1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:7: Define or directive not defined: \'`ADDR_BUS\'\n input wire [`ADDR_BUS] f_predPC_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`ADDR_BUS] f_predPC_i,\n ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:8: Define or directive not defined: \'`ADDR_BUS\'\n output reg [`ADDR_BUS] F_predPC_o\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:13: Define or directive not defined: \'`ADDR_ZERO\'\n F_predPC_o <= `ADDR_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:18: Define or directive not defined: \'`RST_EN\'\n if(rst == `RST_EN)\n ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:20: Define or directive not defined: \'`ADDR_ZERO\'\n F_predPC_o <= `ADDR_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:22: Define or directive not defined: \'`FALSE\'\n else if(F_stall_i == `FALSE)\n ^~~~~~\n%Error: Exiting due to 8 error(s)\n' | 6,712 | module | module fetch_reg(
input wire clk,
input wire rst,
input wire F_stall_i,
input wire [`ADDR_BUS] f_predPC_i,
output reg [`ADDR_BUS] F_predPC_o
);
initial
begin
F_predPC_o <= `ADDR_ZERO;
end
always @(posedge clk)
begin
if(rst == `RST_EN)
begin
F_predPC_o <= `ADDR_ZERO;
end
else if(F_stall_i == `FALSE)
begin
F_predPC_o <= f_predPC_i;
end
else
begin
F_predPC_o <= F_predPC_o;
end
end
endmodule | module fetch_reg(
input wire clk,
input wire rst,
input wire F_stall_i,
input wire [`ADDR_BUS] f_predPC_i,
output reg [`ADDR_BUS] F_predPC_o
); |
initial
begin
F_predPC_o <= `ADDR_ZERO;
end
always @(posedge clk)
begin
if(rst == `RST_EN)
begin
F_predPC_o <= `ADDR_ZERO;
end
else if(F_stall_i == `FALSE)
begin
F_predPC_o <= f_predPC_i;
end
else
begin
F_predPC_o <= F_predPC_o;
end
end
endmodule | 11 |
5,865 | data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v | 114,896,735 | i_mem.v | v | 83 | 109 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:4: Define or directive not defined: \'`ADDR_BUS\'\n input wire [`ADDR_BUS] addr,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:4: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`ADDR_BUS] addr,\n ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:5: Define or directive not defined: \'`INST_BUS\'\n output reg [`INST_BUS] inst,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:9: Define or directive not defined: \'`BYTE0\'\n reg [`BYTE0]mem[0:`MEM_SIZE];\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`BYTE0]mem[0:`MEM_SIZE];\n ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:9: Define or directive not defined: \'`MEM_SIZE\'\n reg [`BYTE0]mem[0:`MEM_SIZE];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:13: Define or directive not defined: \'`FALSE\'\n error = `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:14: Define or directive not defined: \'`NONE_INST\'\n inst = `NONE_INST;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:20: Define or directive not defined: \'`MEM_SIZE\'\n if(addr <= `MEM_SIZE - 9)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:24: Define or directive not defined: \'`FALSE\'\n error = `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:26: Define or directive not defined: \'`MEM_SIZE\'\n else if(addr <= `MEM_SIZE)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:29: Define or directive not defined: \'`MEM_SIZE\'\n `MEM_SIZE - 8:\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:32: Define or directive not defined: \'`BYTE_ZERO\'\n mem[addr + 5], mem[addr + 6], mem[addr + 7], mem[addr + 8], `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:34: Define or directive not defined: \'`MEM_SIZE\'\n `MEM_SIZE - 7:\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:37: Define or directive not defined: \'`BYTE_ZERO\'\n mem[addr + 5], mem[addr + 6], mem[addr + 7], `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:37: Define or directive not defined: \'`BYTE_ZERO\'\n mem[addr + 5], mem[addr + 6], mem[addr + 7], `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:39: Define or directive not defined: \'`MEM_SIZE\'\n `MEM_SIZE - 6:\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:42: Define or directive not defined: \'`BYTE_ZERO\'\n mem[addr + 5], mem[addr + 6], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:42: Define or directive not defined: \'`BYTE_ZERO\'\n mem[addr + 5], mem[addr + 6], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:42: Define or directive not defined: \'`BYTE_ZERO\'\n mem[addr + 5], mem[addr + 6], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:44: Define or directive not defined: \'`MEM_SIZE\'\n `MEM_SIZE - 5:\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:47: Define or directive not defined: \'`BYTE_ZERO\'\n mem[addr + 5], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:47: Define or directive not defined: \'`BYTE_ZERO\'\n mem[addr + 5], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:47: Define or directive not defined: \'`BYTE_ZERO\'\n mem[addr + 5], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:47: Define or directive not defined: \'`BYTE_ZERO\'\n mem[addr + 5], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:49: Define or directive not defined: \'`MEM_SIZE\'\n `MEM_SIZE - 4:\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:52: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:52: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:52: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:52: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:52: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:54: Define or directive not defined: \'`MEM_SIZE\'\n `MEM_SIZE - 3:\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:56: Define or directive not defined: \'`BYTE_ZERO\'\n inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], `BYTE_ZERO,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:57: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:57: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:57: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:57: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:57: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:59: Define or directive not defined: \'`MEM_SIZE\'\n `MEM_SIZE - 2:\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:61: Define or directive not defined: \'`BYTE_ZERO\'\n inst = {mem[addr], mem[addr + 1], mem[addr + 2], `BYTE_ZERO, `BYTE_ZERO,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:61: Define or directive not defined: \'`BYTE_ZERO\'\n inst = {mem[addr], mem[addr + 1], mem[addr + 2], `BYTE_ZERO, `BYTE_ZERO,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:62: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:62: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:62: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:62: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:62: Define or directive not defined: \'`BYTE_ZERO\'\n `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:64: Define or directive not defined: \'`MEM_SIZE\'\n `MEM_SIZE - 1:\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:66: Define or directive not defined: \'`BYTE_ZERO\'\n inst = {mem[addr], mem[addr + 1], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:66: Define or directive not defined: \'`BYTE_ZERO\'\n inst = {mem[addr], mem[addr + 1], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO,\n ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,713 | module | module i_mem(
input wire [`ADDR_BUS] addr,
output reg [`INST_BUS] inst,
output reg error
);
reg [`BYTE0]mem[0:`MEM_SIZE];
initial
begin
error = `FALSE;
inst = `NONE_INST;
$readmemh("F:/Projects/Verilog/y86cpu/y86cpu.srcs/sim_1/new/insts.data", mem);
end
always @(*)
begin
if(addr <= `MEM_SIZE - 9)
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
mem[addr + 5], mem[addr + 6], mem[addr + 7], mem[addr + 8], mem[addr + 9]};
error = `FALSE;
end
else if(addr <= `MEM_SIZE)
begin
case(addr)
`MEM_SIZE - 8:
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
mem[addr + 5], mem[addr + 6], mem[addr + 7], mem[addr + 8], `BYTE_ZERO};
end
`MEM_SIZE - 7:
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
mem[addr + 5], mem[addr + 6], mem[addr + 7], `BYTE_ZERO, `BYTE_ZERO};
end
`MEM_SIZE - 6:
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
mem[addr + 5], mem[addr + 6], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
end
`MEM_SIZE - 5:
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
mem[addr + 5], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
end
`MEM_SIZE - 4:
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
`BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
end
`MEM_SIZE - 3:
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], `BYTE_ZERO,
`BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
end
`MEM_SIZE - 2:
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], `BYTE_ZERO, `BYTE_ZERO,
`BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
end
`MEM_SIZE - 1:
begin
inst = {mem[addr], mem[addr + 1], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO,
`BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
end
default:
begin
inst = {mem[addr], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO,
`BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
end
endcase
error = `FALSE;
end
else
begin
error = `TRUE;
end
end
endmodule | module i_mem(
input wire [`ADDR_BUS] addr,
output reg [`INST_BUS] inst,
output reg error
); |
reg [`BYTE0]mem[0:`MEM_SIZE];
initial
begin
error = `FALSE;
inst = `NONE_INST;
$readmemh("F:/Projects/Verilog/y86cpu/y86cpu.srcs/sim_1/new/insts.data", mem);
end
always @(*)
begin
if(addr <= `MEM_SIZE - 9)
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
mem[addr + 5], mem[addr + 6], mem[addr + 7], mem[addr + 8], mem[addr + 9]};
error = `FALSE;
end
else if(addr <= `MEM_SIZE)
begin
case(addr)
`MEM_SIZE - 8:
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
mem[addr + 5], mem[addr + 6], mem[addr + 7], mem[addr + 8], `BYTE_ZERO};
end
`MEM_SIZE - 7:
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
mem[addr + 5], mem[addr + 6], mem[addr + 7], `BYTE_ZERO, `BYTE_ZERO};
end
`MEM_SIZE - 6:
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
mem[addr + 5], mem[addr + 6], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
end
`MEM_SIZE - 5:
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
mem[addr + 5], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
end
`MEM_SIZE - 4:
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
`BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
end
`MEM_SIZE - 3:
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], `BYTE_ZERO,
`BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
end
`MEM_SIZE - 2:
begin
inst = {mem[addr], mem[addr + 1], mem[addr + 2], `BYTE_ZERO, `BYTE_ZERO,
`BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
end
`MEM_SIZE - 1:
begin
inst = {mem[addr], mem[addr + 1], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO,
`BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
end
default:
begin
inst = {mem[addr], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO,
`BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
end
endcase
error = `FALSE;
end
else
begin
error = `TRUE;
end
end
endmodule | 11 |
5,866 | data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v | 114,896,735 | mem.v | v | 42 | 63 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:4: Define or directive not defined: \'`DATA_BUS\'\n input wire [`DATA_BUS] M_valE_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:4: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`DATA_BUS] M_valE_i,\n ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:5: Define or directive not defined: \'`DATA_BUS\'\n input wire [`DATA_BUS] M_valA_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:6: Define or directive not defined: \'`ICODE_BUS\'\n input wire [`ICODE_BUS] M_icode_i,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:8: Define or directive not defined: \'`ADDR_BUS\'\n output reg [`ADDR_BUS] addr,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:14: Define or directive not defined: \'`RMMOVQ\'\n if(M_icode_i == `RMMOVQ)\n ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:17: Define or directive not defined: \'`TRUE\'\n write = `TRUE;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:19: Define or directive not defined: \'`MRMOVQ\'\n else if(M_icode_i == `MRMOVQ)\n ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:22: Define or directive not defined: \'`FALSE\'\n write = `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:24: Define or directive not defined: \'`CALL\'\n else if(M_icode_i == `CALL || M_icode_i == `PUSHQ)\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:24: Define or directive not defined: \'`PUSHQ\'\n else if(M_icode_i == `CALL || M_icode_i == `PUSHQ)\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:27: Define or directive not defined: \'`TRUE\'\n write = `TRUE;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:29: Define or directive not defined: \'`RET\'\n else if(M_icode_i == `RET || M_icode_i == `POPQ)\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:29: Define or directive not defined: \'`POPQ\'\n else if(M_icode_i == `RET || M_icode_i == `POPQ)\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:32: Define or directive not defined: \'`FALSE\'\n write = `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:36: Define or directive not defined: \'`ADDR_ZERO\'\n addr = `ADDR_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:37: Define or directive not defined: \'`FALSE\'\n write = `FALSE;\n ^~~~~~\n%Error: Exiting due to 18 error(s)\n' | 6,714 | module | module mem(
input wire [`DATA_BUS] M_valE_i,
input wire [`DATA_BUS] M_valA_i,
input wire [`ICODE_BUS] M_icode_i,
output reg [`ADDR_BUS] addr,
output reg write
);
always @(*)
begin
if(M_icode_i == `RMMOVQ)
begin
addr = M_valE_i;
write = `TRUE;
end
else if(M_icode_i == `MRMOVQ)
begin
addr = M_valE_i;
write = `FALSE;
end
else if(M_icode_i == `CALL || M_icode_i == `PUSHQ)
begin
addr = M_valE_i;
write = `TRUE;
end
else if(M_icode_i == `RET || M_icode_i == `POPQ)
begin
addr = M_valA_i;
write = `FALSE;
end
else
begin
addr = `ADDR_ZERO;
write = `FALSE;
end
end
endmodule | module mem(
input wire [`DATA_BUS] M_valE_i,
input wire [`DATA_BUS] M_valA_i,
input wire [`ICODE_BUS] M_icode_i,
output reg [`ADDR_BUS] addr,
output reg write
); |
always @(*)
begin
if(M_icode_i == `RMMOVQ)
begin
addr = M_valE_i;
write = `TRUE;
end
else if(M_icode_i == `MRMOVQ)
begin
addr = M_valE_i;
write = `FALSE;
end
else if(M_icode_i == `CALL || M_icode_i == `PUSHQ)
begin
addr = M_valE_i;
write = `TRUE;
end
else if(M_icode_i == `RET || M_icode_i == `POPQ)
begin
addr = M_valA_i;
write = `FALSE;
end
else
begin
addr = `ADDR_ZERO;
write = `FALSE;
end
end
endmodule | 11 |
5,867 | data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v | 114,896,735 | mem_reg.v | v | 69 | 42 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:8: Define or directive not defined: \'`STAT_BUS\'\n input wire [`STAT_BUS] E_stat_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`STAT_BUS] E_stat_i,\n ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:9: Define or directive not defined: \'`ICODE_BUS\'\n input wire [`ICODE_BUS] E_icode_i,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:10: Define or directive not defined: \'`DATA_BUS\'\n input wire [`DATA_BUS] e_valE_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:11: Define or directive not defined: \'`DATA_BUS\'\n input wire [`DATA_BUS] E_valA_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:12: Define or directive not defined: \'`REG_ADDR_BUS\'\n input wire [`REG_ADDR_BUS] e_dstE_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:13: Define or directive not defined: \'`REG_ADDR_BUS\'\n input wire [`REG_ADDR_BUS] E_dstM_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:16: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [`STAT_BUS] M_stat_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:16: Define or directive not defined: \'`STAT_BUS\'\n output reg [`STAT_BUS] M_stat_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:17: Define or directive not defined: \'`ICODE_BUS\'\n output reg [`ICODE_BUS] M_icode_o,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:18: Define or directive not defined: \'`DATA_BUS\'\n output reg [`DATA_BUS] M_valE_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:19: Define or directive not defined: \'`DATA_BUS\'\n output reg [`DATA_BUS] M_valA_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:20: Define or directive not defined: \'`REG_ADDR_BUS\'\n output reg [`REG_ADDR_BUS] M_dstE_o,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:21: Define or directive not defined: \'`REG_ADDR_BUS\'\n output reg [`REG_ADDR_BUS] M_dstM_o\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:26: Define or directive not defined: \'`TRUE\'\n M_Cnd_o <= `TRUE;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:27: Define or directive not defined: \'`SAOK\'\n M_stat_o <= `SAOK;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:28: Define or directive not defined: \'`ICODE_ZERO\'\n M_icode_o <= `ICODE_ZERO;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:29: Define or directive not defined: \'`DATA_ZERO\'\n M_valE_o <= `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:30: Define or directive not defined: \'`DATA_ZERO\'\n M_valA_o <= `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:31: Define or directive not defined: \'`NREG\'\n M_dstE_o <= `NREG;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:32: Define or directive not defined: \'`NREG\'\n M_dstM_o <= `NREG;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:37: Define or directive not defined: \'`RST_EN\'\n if(rst == `RST_EN)\n ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:39: Define or directive not defined: \'`TRUE\'\n M_Cnd_o <= `TRUE;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:40: Define or directive not defined: \'`SAOK\'\n M_stat_o <= `SAOK;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:41: Define or directive not defined: \'`ICODE_ZERO\'\n M_icode_o <= `ICODE_ZERO;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:42: Define or directive not defined: \'`DATA_ZERO\'\n M_valE_o <= `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:43: Define or directive not defined: \'`DATA_ZERO\'\n M_valA_o <= `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:44: Define or directive not defined: \'`NREG\'\n M_dstE_o <= `NREG;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:45: Define or directive not defined: \'`NREG\'\n M_dstM_o <= `NREG;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:47: Define or directive not defined: \'`TRUE\'\n else if(M_bubble_i == `TRUE)\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:50: Define or directive not defined: \'`SAOK\'\n M_stat_o <= `SAOK;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:51: Define or directive not defined: \'`NOP\'\n M_icode_o <= `NOP;\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:52: Define or directive not defined: \'`DATA_ZERO\'\n M_valE_o <= `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:53: Define or directive not defined: \'`DATA_ZERO\'\n M_valA_o <= `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:54: Define or directive not defined: \'`NREG\'\n M_dstE_o <= `NREG;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:55: Define or directive not defined: \'`NREG\'\n M_dstM_o <= `NREG;\n ^~~~~\n%Error: Exiting due to 37 error(s)\n' | 6,715 | module | module mem_reg(
input wire clk,
input wire rst,
input wire e_Cnd_i,
input wire M_bubble_i,
input wire [`STAT_BUS] E_stat_i,
input wire [`ICODE_BUS] E_icode_i,
input wire [`DATA_BUS] e_valE_i,
input wire [`DATA_BUS] E_valA_i,
input wire [`REG_ADDR_BUS] e_dstE_i,
input wire [`REG_ADDR_BUS] E_dstM_i,
output reg M_Cnd_o,
output reg [`STAT_BUS] M_stat_o,
output reg [`ICODE_BUS] M_icode_o,
output reg [`DATA_BUS] M_valE_o,
output reg [`DATA_BUS] M_valA_o,
output reg [`REG_ADDR_BUS] M_dstE_o,
output reg [`REG_ADDR_BUS] M_dstM_o
);
initial
begin
M_Cnd_o <= `TRUE;
M_stat_o <= `SAOK;
M_icode_o <= `ICODE_ZERO;
M_valE_o <= `DATA_ZERO;
M_valA_o <= `DATA_ZERO;
M_dstE_o <= `NREG;
M_dstM_o <= `NREG;
end
always @(posedge clk)
begin
if(rst == `RST_EN)
begin
M_Cnd_o <= `TRUE;
M_stat_o <= `SAOK;
M_icode_o <= `ICODE_ZERO;
M_valE_o <= `DATA_ZERO;
M_valA_o <= `DATA_ZERO;
M_dstE_o <= `NREG;
M_dstM_o <= `NREG;
end
else if(M_bubble_i == `TRUE)
begin
M_Cnd_o <= e_Cnd_i;
M_stat_o <= `SAOK;
M_icode_o <= `NOP;
M_valE_o <= `DATA_ZERO;
M_valA_o <= `DATA_ZERO;
M_dstE_o <= `NREG;
M_dstM_o <= `NREG;
end
else
begin
M_Cnd_o <= e_Cnd_i;
M_stat_o <= E_stat_i;
M_icode_o <= E_icode_i;
M_valE_o <= e_valE_i;
M_valA_o <= E_valA_i;
M_dstE_o <= e_dstE_i;
M_dstM_o <= E_dstM_i;
end
end
endmodule | module mem_reg(
input wire clk,
input wire rst,
input wire e_Cnd_i,
input wire M_bubble_i,
input wire [`STAT_BUS] E_stat_i,
input wire [`ICODE_BUS] E_icode_i,
input wire [`DATA_BUS] e_valE_i,
input wire [`DATA_BUS] E_valA_i,
input wire [`REG_ADDR_BUS] e_dstE_i,
input wire [`REG_ADDR_BUS] E_dstM_i,
output reg M_Cnd_o,
output reg [`STAT_BUS] M_stat_o,
output reg [`ICODE_BUS] M_icode_o,
output reg [`DATA_BUS] M_valE_o,
output reg [`DATA_BUS] M_valA_o,
output reg [`REG_ADDR_BUS] M_dstE_o,
output reg [`REG_ADDR_BUS] M_dstM_o
); |
initial
begin
M_Cnd_o <= `TRUE;
M_stat_o <= `SAOK;
M_icode_o <= `ICODE_ZERO;
M_valE_o <= `DATA_ZERO;
M_valA_o <= `DATA_ZERO;
M_dstE_o <= `NREG;
M_dstM_o <= `NREG;
end
always @(posedge clk)
begin
if(rst == `RST_EN)
begin
M_Cnd_o <= `TRUE;
M_stat_o <= `SAOK;
M_icode_o <= `ICODE_ZERO;
M_valE_o <= `DATA_ZERO;
M_valA_o <= `DATA_ZERO;
M_dstE_o <= `NREG;
M_dstM_o <= `NREG;
end
else if(M_bubble_i == `TRUE)
begin
M_Cnd_o <= e_Cnd_i;
M_stat_o <= `SAOK;
M_icode_o <= `NOP;
M_valE_o <= `DATA_ZERO;
M_valA_o <= `DATA_ZERO;
M_dstE_o <= `NREG;
M_dstM_o <= `NREG;
end
else
begin
M_Cnd_o <= e_Cnd_i;
M_stat_o <= E_stat_i;
M_icode_o <= E_icode_i;
M_valE_o <= e_valE_i;
M_valA_o <= E_valA_i;
M_dstE_o <= e_dstE_i;
M_dstM_o <= E_dstM_i;
end
end
endmodule | 11 |
5,868 | data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v | 114,896,735 | registers.v | v | 75 | 52 | [] | [] | [] | [(115, 186)] | null | null | 1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:6: Define or directive not defined: \'`REG_ADDR_BUS\'\n input wire [`REG_ADDR_BUS]W_dstM_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`REG_ADDR_BUS]W_dstM_i,\n ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:7: Define or directive not defined: \'`REG_ADDR_BUS\'\n input wire [`REG_ADDR_BUS]W_dstE_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:8: Define or directive not defined: \'`DATA_BUS\'\n input wire [`DATA_BUS]W_valM_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:9: Define or directive not defined: \'`DATA_BUS\'\n input wire [`DATA_BUS]W_valE_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:10: Define or directive not defined: \'`REG_ADDR_BUS\'\n input wire [`REG_ADDR_BUS]D_rA_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:11: Define or directive not defined: \'`REG_ADDR_BUS\'\n input wire [`REG_ADDR_BUS]D_rB_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:13: Define or directive not defined: \'`DATA_BUS\'\n output reg [`DATA_BUS]r_valA_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:14: Define or directive not defined: \'`DATA_BUS\'\n output reg [`DATA_BUS]r_valB_o\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:17: Define or directive not defined: \'`DATA_BUS\'\n reg [`DATA_BUS]registers[0:`NREG];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:17: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`DATA_BUS]registers[0:`NREG];\n ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:17: Define or directive not defined: \'`NREG\'\n reg [`DATA_BUS]registers[0:`NREG];\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:21: Define or directive not defined: \'`RST_EN\'\n if(rst == ~`RST_EN && W_dstM_i < `NREG)\n ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:21: Define or directive not defined: \'`NREG\'\n if(rst == ~`RST_EN && W_dstM_i < `NREG)\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:29: Define or directive not defined: \'`RST_EN\'\n if(rst == ~`RST_EN && W_dstE_i < `NREG)\n ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:29: Define or directive not defined: \'`NREG\'\n if(rst == ~`RST_EN && W_dstE_i < `NREG)\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:37: Define or directive not defined: \'`RST_EN\'\n if(rst == `RST_EN || D_rA_i >= `NREG)\n ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:37: Define or directive not defined: \'`NREG\'\n if(rst == `RST_EN || D_rA_i >= `NREG)\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:39: Define or directive not defined: \'`DATA_ZERO\'\n r_valA_o = `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:57: Define or directive not defined: \'`RST_EN\'\n if(rst == `RST_EN || D_rB_i >= `NREG)\n ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:57: Define or directive not defined: \'`NREG\'\n if(rst == `RST_EN || D_rB_i >= `NREG)\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:59: Define or directive not defined: \'`DATA_ZERO\'\n r_valB_o = `DATA_ZERO;\n ^~~~~~~~~~\n%Error: Exiting due to 23 error(s)\n' | 6,716 | module | module registers(
input wire clk,
input wire rst,
input wire [`REG_ADDR_BUS]W_dstM_i,
input wire [`REG_ADDR_BUS]W_dstE_i,
input wire [`DATA_BUS]W_valM_i,
input wire [`DATA_BUS]W_valE_i,
input wire [`REG_ADDR_BUS]D_rA_i,
input wire [`REG_ADDR_BUS]D_rB_i,
output reg [`DATA_BUS]r_valA_o,
output reg [`DATA_BUS]r_valB_o
);
reg [`DATA_BUS]registers[0:`NREG];
always @(posedge clk)
begin
if(rst == ~`RST_EN && W_dstM_i < `NREG)
begin
registers[W_dstM_i] <= W_valM_i;
end
end
always @(posedge clk)
begin
if(rst == ~`RST_EN && W_dstE_i < `NREG)
begin
registers[W_dstE_i] <= W_valE_i;
end
end
always @(*)
begin
if(rst == `RST_EN || D_rA_i >= `NREG)
begin
r_valA_o = `DATA_ZERO;
end
else if(D_rA_i == W_dstM_i)
begin
r_valA_o = W_valM_i;
end
else if(D_rA_i == W_dstE_i)
begin
r_valA_o = W_valE_i;
end
else
begin
r_valA_o = registers[D_rA_i];
end
end
always @(*)
begin
if(rst == `RST_EN || D_rB_i >= `NREG)
begin
r_valB_o = `DATA_ZERO;
end
else if(D_rB_i == W_dstM_i)
begin
r_valB_o = W_valM_i;
end
else if(D_rB_i == W_dstE_i)
begin
r_valB_o = W_valE_i;
end
else
begin
r_valB_o = registers[D_rB_i];
end
end
endmodule | module registers(
input wire clk,
input wire rst,
input wire [`REG_ADDR_BUS]W_dstM_i,
input wire [`REG_ADDR_BUS]W_dstE_i,
input wire [`DATA_BUS]W_valM_i,
input wire [`DATA_BUS]W_valE_i,
input wire [`REG_ADDR_BUS]D_rA_i,
input wire [`REG_ADDR_BUS]D_rB_i,
output reg [`DATA_BUS]r_valA_o,
output reg [`DATA_BUS]r_valB_o
); |
reg [`DATA_BUS]registers[0:`NREG];
always @(posedge clk)
begin
if(rst == ~`RST_EN && W_dstM_i < `NREG)
begin
registers[W_dstM_i] <= W_valM_i;
end
end
always @(posedge clk)
begin
if(rst == ~`RST_EN && W_dstE_i < `NREG)
begin
registers[W_dstE_i] <= W_valE_i;
end
end
always @(*)
begin
if(rst == `RST_EN || D_rA_i >= `NREG)
begin
r_valA_o = `DATA_ZERO;
end
else if(D_rA_i == W_dstM_i)
begin
r_valA_o = W_valM_i;
end
else if(D_rA_i == W_dstE_i)
begin
r_valA_o = W_valE_i;
end
else
begin
r_valA_o = registers[D_rA_i];
end
end
always @(*)
begin
if(rst == `RST_EN || D_rB_i >= `NREG)
begin
r_valB_o = `DATA_ZERO;
end
else if(D_rB_i == W_dstM_i)
begin
r_valB_o = W_valM_i;
end
else if(D_rB_i == W_dstE_i)
begin
r_valB_o = W_valE_i;
end
else
begin
r_valB_o = registers[D_rB_i];
end
end
endmodule | 11 |
5,869 | data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v | 114,896,735 | select_pc.v | v | 30 | 46 | [] | [] | [] | [(115, 141)] | null | null | 1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:5: Define or directive not defined: \'`ICODE_BUS\'\n input wire [`ICODE_BUS] M_icode_i,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:5: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`ICODE_BUS] M_icode_i,\n ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:6: Define or directive not defined: \'`ICODE_BUS\'\n input wire [`ICODE_BUS] W_icode_i,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:7: Define or directive not defined: \'`ADDR_BUS\'\n input wire [`ADDR_BUS] M_valA_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:8: Define or directive not defined: \'`ADDR_BUS\'\n input wire [`ADDR_BUS] W_valM_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:9: Define or directive not defined: \'`ADDR_BUS\'\n input wire [`ADDR_BUS] F_predPC_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:11: Define or directive not defined: \'`ADDR_BUS\'\n output reg [`ADDR_BUS] f_pc_o\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:16: Define or directive not defined: \'`JXX\'\n if(M_icode_i == `JXX && !M_Cnd_i)\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:20: Define or directive not defined: \'`RET\'\n else if(W_icode_i == `RET)\n ^~~~\n%Error: Exiting due to 10 error(s)\n' | 6,717 | module | module select_pc(
input wire M_Cnd_i,
input wire [`ICODE_BUS] M_icode_i,
input wire [`ICODE_BUS] W_icode_i,
input wire [`ADDR_BUS] M_valA_i,
input wire [`ADDR_BUS] W_valM_i,
input wire [`ADDR_BUS] F_predPC_i,
output reg [`ADDR_BUS] f_pc_o
);
always @(*)
begin
if(M_icode_i == `JXX && !M_Cnd_i)
begin
f_pc_o = M_valA_i;
end
else if(W_icode_i == `RET)
begin
f_pc_o = W_valM_i;
end
else
begin
f_pc_o = F_predPC_i;
end
end
endmodule | module select_pc(
input wire M_Cnd_i,
input wire [`ICODE_BUS] M_icode_i,
input wire [`ICODE_BUS] W_icode_i,
input wire [`ADDR_BUS] M_valA_i,
input wire [`ADDR_BUS] W_valM_i,
input wire [`ADDR_BUS] F_predPC_i,
output reg [`ADDR_BUS] f_pc_o
); |
always @(*)
begin
if(M_icode_i == `JXX && !M_Cnd_i)
begin
f_pc_o = M_valA_i;
end
else if(W_icode_i == `RET)
begin
f_pc_o = W_valM_i;
end
else
begin
f_pc_o = F_predPC_i;
end
end
endmodule | 11 |
5,870 | data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v | 114,896,735 | set_cond.v | v | 63 | 99 | [] | [] | [] | [(115, 174)] | null | null | 1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:5: Define or directive not defined: \'`ICODE_BUS\'\n input wire [`ICODE_BUS] E_icode_i,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:5: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`ICODE_BUS] E_icode_i,\n ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:6: Define or directive not defined: \'`IFUN_BUS\'\n input wire [`IFUN_BUS] E_ifun_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:7: Define or directive not defined: \'`REG_ADDR_BUS\'\n input wire [`REG_ADDR_BUS] E_dstE_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire SF_i,\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire OF_i,\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:12: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg e_Cnd_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:13: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [`REG_ADDR_BUS] e_dstE_o\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:13: Define or directive not defined: \'`REG_ADDR_BUS\'\n output reg [`REG_ADDR_BUS] e_dstE_o\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:18: syntax error, unexpected initial\n initial\n ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:20: Define or directive not defined: \'`FALSE\'\n ZF = `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:21: Define or directive not defined: \'`FALSE\'\n SF = `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:22: Define or directive not defined: \'`FALSE\'\n OF = `FALSE;\n ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:27: Define or directive not defined: \'`TRUE\'\n if(set_cc_i == `TRUE && (E_icode_i == `OPQ || (E_icode_i == `IXX && E_ifun_i != `IRMOVQ)))\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:27: Define or directive not defined: \'`OPQ\'\n if(set_cc_i == `TRUE && (E_icode_i == `OPQ || (E_icode_i == `IXX && E_ifun_i != `IRMOVQ)))\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:27: Define or directive not defined: \'`IXX\'\n if(set_cc_i == `TRUE && (E_icode_i == `OPQ || (E_icode_i == `IXX && E_ifun_i != `IRMOVQ)))\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:27: Define or directive not defined: \'`IRMOVQ\'\n if(set_cc_i == `TRUE && (E_icode_i == `OPQ || (E_icode_i == `IXX && E_ifun_i != `IRMOVQ)))\n ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:39: Define or directive not defined: \'`JXX\'\n if(E_icode_i == `JXX || E_icode_i == `CXX)\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:39: Define or directive not defined: \'`CXX\'\n if(E_icode_i == `JXX || E_icode_i == `CXX)\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:42: Define or directive not defined: \'`JLE\'\n `JLE: e_Cnd_o = ZF || (!SF && OF) || SF;\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:43: Define or directive not defined: \'`JL\'\n `JL: e_Cnd_o = (!SF && OF) || SF;\n ^~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:44: Define or directive not defined: \'`JE\'\n `JE: e_Cnd_o = ZF;\n ^~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:45: Define or directive not defined: \'`JNE\'\n `JNE: e_Cnd_o = !ZF;\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:46: Define or directive not defined: \'`JGE\'\n `JGE: e_Cnd_o = ZF || (SF && OF) || !SF;\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:47: Define or directive not defined: \'`JG\'\n `JG: e_Cnd_o = (SF && OF) || !SF;\n ^~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:48: Define or directive not defined: \'`TRUE\'\n default: e_Cnd_o = `TRUE;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:51: Define or directive not defined: \'`TRUE\'\n if(e_Cnd_o == `TRUE)\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:54: Define or directive not defined: \'`NREG\'\n e_dstE_o = `NREG;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:59: Define or directive not defined: \'`TRUE\'\n e_Cnd_o = `TRUE;\n ^~~~~\n%Error: Exiting due to 30 error(s)\n' | 6,718 | module | module set_cond(
input wire set_cc_i,
input wire [`ICODE_BUS] E_icode_i,
input wire [`IFUN_BUS] E_ifun_i,
input wire [`REG_ADDR_BUS] E_dstE_i,
input wire ZF_i,
input wire SF_i,
input wire OF_i,
output reg e_Cnd_o,
output reg [`REG_ADDR_BUS] e_dstE_o
);
reg ZF, SF, OF;
initial
begin
ZF = `FALSE;
SF = `FALSE;
OF = `FALSE;
end
always @(*)
begin
if(set_cc_i == `TRUE && (E_icode_i == `OPQ || (E_icode_i == `IXX && E_ifun_i != `IRMOVQ)))
begin
ZF = ZF_i;
SF = SF_i;
OF = OF_i;
end
else
begin
ZF = ZF;
SF = SF;
OF = OF;
end
if(E_icode_i == `JXX || E_icode_i == `CXX)
begin
case(E_ifun_i)
`JLE: e_Cnd_o = ZF || (!SF && OF) || SF;
`JL: e_Cnd_o = (!SF && OF) || SF;
`JE: e_Cnd_o = ZF;
`JNE: e_Cnd_o = !ZF;
`JGE: e_Cnd_o = ZF || (SF && OF) || !SF;
`JG: e_Cnd_o = (SF && OF) || !SF;
default: e_Cnd_o = `TRUE;
endcase
if(e_Cnd_o == `TRUE)
e_dstE_o = E_dstE_i;
else
e_dstE_o = `NREG;
end
else
begin
e_dstE_o = E_dstE_i;
e_Cnd_o = `TRUE;
end
end
endmodule | module set_cond(
input wire set_cc_i,
input wire [`ICODE_BUS] E_icode_i,
input wire [`IFUN_BUS] E_ifun_i,
input wire [`REG_ADDR_BUS] E_dstE_i,
input wire ZF_i,
input wire SF_i,
input wire OF_i,
output reg e_Cnd_o,
output reg [`REG_ADDR_BUS] e_dstE_o
); |
reg ZF, SF, OF;
initial
begin
ZF = `FALSE;
SF = `FALSE;
OF = `FALSE;
end
always @(*)
begin
if(set_cc_i == `TRUE && (E_icode_i == `OPQ || (E_icode_i == `IXX && E_ifun_i != `IRMOVQ)))
begin
ZF = ZF_i;
SF = SF_i;
OF = OF_i;
end
else
begin
ZF = ZF;
SF = SF;
OF = OF;
end
if(E_icode_i == `JXX || E_icode_i == `CXX)
begin
case(E_ifun_i)
`JLE: e_Cnd_o = ZF || (!SF && OF) || SF;
`JL: e_Cnd_o = (!SF && OF) || SF;
`JE: e_Cnd_o = ZF;
`JNE: e_Cnd_o = !ZF;
`JGE: e_Cnd_o = ZF || (SF && OF) || !SF;
`JG: e_Cnd_o = (SF && OF) || !SF;
default: e_Cnd_o = `TRUE;
endcase
if(e_Cnd_o == `TRUE)
e_dstE_o = E_dstE_i;
else
e_dstE_o = `NREG;
end
else
begin
e_dstE_o = E_dstE_i;
e_Cnd_o = `TRUE;
end
end
endmodule | 11 |
5,873 | data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v | 114,896,735 | write_reg.v | v | 64 | 41 | [] | [] | [] | [(115, 175)] | null | null | 1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:7: Define or directive not defined: \'`STAT_BUS\'\n input wire [`STAT_BUS] m_stat_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`STAT_BUS] m_stat_i,\n ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:8: Define or directive not defined: \'`ICODE_BUS\'\n input wire [`ICODE_BUS] M_icode_i,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:9: Define or directive not defined: \'`DATA_BUS\'\n input wire [`DATA_BUS] M_valE_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:10: Define or directive not defined: \'`DATA_BUS\'\n input wire [`DATA_BUS] m_valM_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:11: Define or directive not defined: \'`REG_ADDR_BUS\'\n input wire [`REG_ADDR_BUS] M_dstE_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:12: Define or directive not defined: \'`REG_ADDR_BUS\'\n input wire [`REG_ADDR_BUS] M_dstM_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:14: Define or directive not defined: \'`STAT_BUS\'\n output reg [`STAT_BUS] W_stat_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:15: Define or directive not defined: \'`ICODE_BUS\'\n output reg [`ICODE_BUS] W_icode_o,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:16: Define or directive not defined: \'`DATA_BUS\'\n output reg [`DATA_BUS] W_valE_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:17: Define or directive not defined: \'`DATA_BUS\'\n output reg [`DATA_BUS] W_valM_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:18: Define or directive not defined: \'`REG_ADDR_BUS\'\n output reg [`REG_ADDR_BUS] W_dstE_o,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:19: Define or directive not defined: \'`REG_ADDR_BUS\'\n output reg [`REG_ADDR_BUS] W_dstM_o\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:24: Define or directive not defined: \'`SAOK\'\n W_stat_o <= `SAOK;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:25: Define or directive not defined: \'`NOP\'\n W_icode_o <= `NOP;\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:26: Define or directive not defined: \'`DATA_ZERO\'\n W_valE_o <= `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:27: Define or directive not defined: \'`DATA_ZERO\'\n W_valM_o <= `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:28: Define or directive not defined: \'`NREG\'\n W_dstE_o <= `NREG;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:29: Define or directive not defined: \'`NREG\'\n W_dstM_o <= `NREG;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:34: Define or directive not defined: \'`RST_EN\'\n if(rst == `RST_EN)\n ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:36: Define or directive not defined: \'`SAOK\'\n W_stat_o <= `SAOK;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:37: Define or directive not defined: \'`NOP\'\n W_icode_o <= `NOP;\n ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:38: Define or directive not defined: \'`DATA_ZERO\'\n W_valE_o <= `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:39: Define or directive not defined: \'`DATA_ZERO\'\n W_valM_o <= `DATA_ZERO;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:40: Define or directive not defined: \'`NREG\'\n W_dstE_o <= `NREG;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:41: Define or directive not defined: \'`NREG\'\n W_dstM_o <= `NREG;\n ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:43: Define or directive not defined: \'`TRUE\'\n else if(W_stall_i == `TRUE)\n ^~~~~\n%Error: Exiting due to 28 error(s)\n' | 6,721 | module | module write_reg(
input wire clk,
input wire rst,
input wire W_stall_i,
input wire [`STAT_BUS] m_stat_i,
input wire [`ICODE_BUS] M_icode_i,
input wire [`DATA_BUS] M_valE_i,
input wire [`DATA_BUS] m_valM_i,
input wire [`REG_ADDR_BUS] M_dstE_i,
input wire [`REG_ADDR_BUS] M_dstM_i,
output reg [`STAT_BUS] W_stat_o,
output reg [`ICODE_BUS] W_icode_o,
output reg [`DATA_BUS] W_valE_o,
output reg [`DATA_BUS] W_valM_o,
output reg [`REG_ADDR_BUS] W_dstE_o,
output reg [`REG_ADDR_BUS] W_dstM_o
);
initial
begin
W_stat_o <= `SAOK;
W_icode_o <= `NOP;
W_valE_o <= `DATA_ZERO;
W_valM_o <= `DATA_ZERO;
W_dstE_o <= `NREG;
W_dstM_o <= `NREG;
end
always @(posedge clk)
begin
if(rst == `RST_EN)
begin
W_stat_o <= `SAOK;
W_icode_o <= `NOP;
W_valE_o <= `DATA_ZERO;
W_valM_o <= `DATA_ZERO;
W_dstE_o <= `NREG;
W_dstM_o <= `NREG;
end
else if(W_stall_i == `TRUE)
begin
W_stat_o <= W_stat_o;
W_icode_o <= W_icode_o;
W_valE_o <= W_valE_o;
W_valM_o <= W_valM_o;
W_dstE_o <= W_dstE_o;
W_dstM_o <= W_dstM_o;
end
else
begin
W_stat_o <= m_stat_i;
W_icode_o <= M_icode_i;
W_valE_o <= M_valE_i;
W_valM_o <= m_valM_i;
W_dstE_o <= M_dstE_i;
W_dstM_o <= M_dstM_i;
end
end
endmodule | module write_reg(
input wire clk,
input wire rst,
input wire W_stall_i,
input wire [`STAT_BUS] m_stat_i,
input wire [`ICODE_BUS] M_icode_i,
input wire [`DATA_BUS] M_valE_i,
input wire [`DATA_BUS] m_valM_i,
input wire [`REG_ADDR_BUS] M_dstE_i,
input wire [`REG_ADDR_BUS] M_dstM_i,
output reg [`STAT_BUS] W_stat_o,
output reg [`ICODE_BUS] W_icode_o,
output reg [`DATA_BUS] W_valE_o,
output reg [`DATA_BUS] W_valM_o,
output reg [`REG_ADDR_BUS] W_dstE_o,
output reg [`REG_ADDR_BUS] W_dstM_o
); |
initial
begin
W_stat_o <= `SAOK;
W_icode_o <= `NOP;
W_valE_o <= `DATA_ZERO;
W_valM_o <= `DATA_ZERO;
W_dstE_o <= `NREG;
W_dstM_o <= `NREG;
end
always @(posedge clk)
begin
if(rst == `RST_EN)
begin
W_stat_o <= `SAOK;
W_icode_o <= `NOP;
W_valE_o <= `DATA_ZERO;
W_valM_o <= `DATA_ZERO;
W_dstE_o <= `NREG;
W_dstM_o <= `NREG;
end
else if(W_stall_i == `TRUE)
begin
W_stat_o <= W_stat_o;
W_icode_o <= W_icode_o;
W_valE_o <= W_valE_o;
W_valM_o <= W_valM_o;
W_dstE_o <= W_dstE_o;
W_dstM_o <= W_dstM_o;
end
else
begin
W_stat_o <= m_stat_i;
W_icode_o <= M_icode_i;
W_valE_o <= M_valE_i;
W_valM_o <= m_valM_i;
W_dstE_o <= M_dstE_i;
W_dstM_o <= M_dstM_i;
end
end
endmodule | 11 |
5,876 | data/full_repos/permissive/114943225/adc_control.v | 114,943,225 | adc_control.v | v | 274 | 121 | [] | [] | [] | [(12, 273)] | null | null | 1: b'%Error: data/full_repos/permissive/114943225/adc_control.v:149: syntax error, unexpected type\n .type(trig_type), \n ^~~~\n%Error: Exiting due to 1 error(s)\n' | 6,724 | module | module adc_control (
clkin,
divider_acq_clk,
run_in,
stop_in,
state_runmode,
state_trig,
debug_led,
trig_mode,
trig_lvl,
trig_type,
trig_noiserej,
adc_clkout_a,
adc_clkout_b,
adc_unlatched_data_a,
adc_unlatched_data_b,
adcoen_a,
adcoen_b,
clk_ramout,
addr_ramout_a,
addr_ramout_b,
wr_en_ramout,
data_wr_ramout_a,
data_wr_ramout_b
);
parameter TRIG_NORM = 0;
parameter TRIG_AUTO = 1;
parameter TRIG_SINGLE = 2;
parameter TRIG_STATE_WAIT = 0;
parameter TRIG_STATE_TRIGD = 1;
parameter TRIG_STATE_AUTO = 2;
parameter TRIG_STATE_DONE = 3;
parameter CLK_DIV_WIDTH = 24;
parameter ADC_WIDTH = 14;
parameter ACQ_MAX_SAMPLES = 1024;
parameter ACQ_COUNTER_WIDTH = 12;
parameter AUTO_MODE_DELAY = 60000000;
parameter AUTO_MODE_FAST = 2500000;
parameter NO_TRIG_DELAY = 50000;
parameter HOLD_OFF_DELAY = 4;
parameter STATE_STOPPED = 0;
parameter STATE_WAIT_FOR_TRIG = 1;
parameter STATE_ACQUIRE = 2;
parameter STATE_HOLD_OFF = 3;
parameter STATE_POST_TRIG = 4;
parameter HYST_NOISEREJ_ON = 200;
parameter HYST_NOISEREJ_OFF = 12;
input [CLK_DIV_WIDTH - 1:0] divider_acq_clk;
input [ADC_WIDTH - 1:0] adc_unlatched_data_a;
input [ADC_WIDTH - 1:0] adc_unlatched_data_b;
input clkin;
wire clktrig;
wire clkacq;
output adc_clkout_a;
output adc_clkout_b;
output adcoen_a;
output adcoen_b;
input run_in, stop_in;
output reg state_runmode;
output reg [2:0] state_trig;
input [1:0] trig_mode;
input [15:0] trig_lvl;
input [2:0] trig_type;
input trig_noiserej;
output reg [7:0] debug_led;
output wire clk_ramout;
output reg [ACQ_COUNTER_WIDTH - 1:0] addr_ramout_a;
output reg [ACQ_COUNTER_WIDTH - 1:0] addr_ramout_b;
output reg wr_en_ramout;
output reg [ADC_WIDTH - 1:0] data_wr_ramout_a;
output reg [ADC_WIDTH - 1:0] data_wr_ramout_b;
assign clk_ramout = clkin;
reg trig_en;
wire trig_out;
reg [15:0] hold_off;
reg [31:0] trig_timeout;
reg trig_auto_rapid;
reg auto_trig_gen;
reg [ACQ_COUNTER_WIDTH - 1:0] acq_index;
reg [2:0] acq_state;
adc_clock_gen cg1 (
.clkin(clkin),
.clkout(clkacq),
.reset(0),
.enable(1),
.divider(divider_acq_clk)
);
edge_Trig tr0(
.clkIn(clkin),
.trigLvl(trig_lvl),
.trigHyst((trig_noiserej) ? HYST_NOISEREJ_ON : HYST_NOISEREJ_OFF),
.adc_data(adc_unlatched_data_a),
.type(trig_type),
.enable(trig_en),
.q(trig_out)
);
assign adcoen_a = 1'b0;
assign adcoen_b = 1'b0;
assign adc_clkout_a = clkacq;
assign adc_clkout_b = clkacq;
always @(negedge clkacq) begin
if (acq_state == STATE_STOPPED) begin
debug_led = 5'b00001;
state_runmode <= 0;
if (run_in) begin
state_runmode <= 1;
acq_state = STATE_WAIT_FOR_TRIG;
end
end
if (acq_state == STATE_WAIT_FOR_TRIG) begin
trig_en <= 1;
debug_led = 5'b00010;
if (stop_in) begin
acq_state = STATE_STOPPED;
end else if (trig_out || auto_trig_gen) begin
trig_en <= 0;
acq_index <= 0;
addr_ramout_a = 0;
addr_ramout_b = 0;
acq_state = STATE_ACQUIRE;
if (!auto_trig_gen) begin
state_trig <= TRIG_STATE_TRIGD;
end;
auto_trig_gen <= 0;
end
trig_timeout <= trig_timeout + divider_acq_clk + 1;
if ((trig_mode == TRIG_AUTO) && (trig_timeout > AUTO_MODE_FAST) && (trig_auto_rapid == 1)) begin
trig_timeout <= 0;
state_trig <= TRIG_STATE_AUTO;
auto_trig_gen <= 1;
trig_auto_rapid <= 1;
end else if ((trig_mode == TRIG_AUTO) && (trig_timeout > AUTO_MODE_DELAY) && (trig_auto_rapid == 0)) begin
trig_timeout <= 0;
state_trig <= TRIG_STATE_AUTO;
trig_auto_rapid <= 1;
auto_trig_gen <= 1;
end else if ((trig_timeout > NO_TRIG_DELAY) && (trig_mode != TRIG_AUTO)) begin
state_trig <= TRIG_STATE_WAIT;
end
end
if (acq_state == STATE_ACQUIRE) begin
trig_timeout <= 0;
debug_led = 5'b00100;
if (acq_index == ACQ_MAX_SAMPLES) begin
acq_state = STATE_HOLD_OFF;
hold_off <= HOLD_OFF_DELAY;
wr_en_ramout = 0;
end else begin
addr_ramout_a = addr_ramout_a + 1;
addr_ramout_b = addr_ramout_b + 1;
acq_index <= acq_index + 1;
wr_en_ramout = 1;
data_wr_ramout_a = adc_unlatched_data_a;
data_wr_ramout_b = adc_unlatched_data_b;
end
end
if (acq_state == STATE_HOLD_OFF) begin
hold_off <= hold_off - 1;
debug_led = 5'b01000;
if (hold_off == 0) begin
acq_state = STATE_POST_TRIG;
end;
end;
if (acq_state == STATE_POST_TRIG) begin
if (trig_mode == TRIG_SINGLE) begin
state_trig <= TRIG_STATE_DONE;
acq_state = STATE_STOPPED;
end else begin
debug_led = 5'b10000;
if (stop_in) begin
acq_state = STATE_STOPPED;
end else begin
acq_state = STATE_WAIT_FOR_TRIG;
end
end
end
end
endmodule | module adc_control (
clkin,
divider_acq_clk,
run_in,
stop_in,
state_runmode,
state_trig,
debug_led,
trig_mode,
trig_lvl,
trig_type,
trig_noiserej,
adc_clkout_a,
adc_clkout_b,
adc_unlatched_data_a,
adc_unlatched_data_b,
adcoen_a,
adcoen_b,
clk_ramout,
addr_ramout_a,
addr_ramout_b,
wr_en_ramout,
data_wr_ramout_a,
data_wr_ramout_b
); |
parameter TRIG_NORM = 0;
parameter TRIG_AUTO = 1;
parameter TRIG_SINGLE = 2;
parameter TRIG_STATE_WAIT = 0;
parameter TRIG_STATE_TRIGD = 1;
parameter TRIG_STATE_AUTO = 2;
parameter TRIG_STATE_DONE = 3;
parameter CLK_DIV_WIDTH = 24;
parameter ADC_WIDTH = 14;
parameter ACQ_MAX_SAMPLES = 1024;
parameter ACQ_COUNTER_WIDTH = 12;
parameter AUTO_MODE_DELAY = 60000000;
parameter AUTO_MODE_FAST = 2500000;
parameter NO_TRIG_DELAY = 50000;
parameter HOLD_OFF_DELAY = 4;
parameter STATE_STOPPED = 0;
parameter STATE_WAIT_FOR_TRIG = 1;
parameter STATE_ACQUIRE = 2;
parameter STATE_HOLD_OFF = 3;
parameter STATE_POST_TRIG = 4;
parameter HYST_NOISEREJ_ON = 200;
parameter HYST_NOISEREJ_OFF = 12;
input [CLK_DIV_WIDTH - 1:0] divider_acq_clk;
input [ADC_WIDTH - 1:0] adc_unlatched_data_a;
input [ADC_WIDTH - 1:0] adc_unlatched_data_b;
input clkin;
wire clktrig;
wire clkacq;
output adc_clkout_a;
output adc_clkout_b;
output adcoen_a;
output adcoen_b;
input run_in, stop_in;
output reg state_runmode;
output reg [2:0] state_trig;
input [1:0] trig_mode;
input [15:0] trig_lvl;
input [2:0] trig_type;
input trig_noiserej;
output reg [7:0] debug_led;
output wire clk_ramout;
output reg [ACQ_COUNTER_WIDTH - 1:0] addr_ramout_a;
output reg [ACQ_COUNTER_WIDTH - 1:0] addr_ramout_b;
output reg wr_en_ramout;
output reg [ADC_WIDTH - 1:0] data_wr_ramout_a;
output reg [ADC_WIDTH - 1:0] data_wr_ramout_b;
assign clk_ramout = clkin;
reg trig_en;
wire trig_out;
reg [15:0] hold_off;
reg [31:0] trig_timeout;
reg trig_auto_rapid;
reg auto_trig_gen;
reg [ACQ_COUNTER_WIDTH - 1:0] acq_index;
reg [2:0] acq_state;
adc_clock_gen cg1 (
.clkin(clkin),
.clkout(clkacq),
.reset(0),
.enable(1),
.divider(divider_acq_clk)
);
edge_Trig tr0(
.clkIn(clkin),
.trigLvl(trig_lvl),
.trigHyst((trig_noiserej) ? HYST_NOISEREJ_ON : HYST_NOISEREJ_OFF),
.adc_data(adc_unlatched_data_a),
.type(trig_type),
.enable(trig_en),
.q(trig_out)
);
assign adcoen_a = 1'b0;
assign adcoen_b = 1'b0;
assign adc_clkout_a = clkacq;
assign adc_clkout_b = clkacq;
always @(negedge clkacq) begin
if (acq_state == STATE_STOPPED) begin
debug_led = 5'b00001;
state_runmode <= 0;
if (run_in) begin
state_runmode <= 1;
acq_state = STATE_WAIT_FOR_TRIG;
end
end
if (acq_state == STATE_WAIT_FOR_TRIG) begin
trig_en <= 1;
debug_led = 5'b00010;
if (stop_in) begin
acq_state = STATE_STOPPED;
end else if (trig_out || auto_trig_gen) begin
trig_en <= 0;
acq_index <= 0;
addr_ramout_a = 0;
addr_ramout_b = 0;
acq_state = STATE_ACQUIRE;
if (!auto_trig_gen) begin
state_trig <= TRIG_STATE_TRIGD;
end;
auto_trig_gen <= 0;
end
trig_timeout <= trig_timeout + divider_acq_clk + 1;
if ((trig_mode == TRIG_AUTO) && (trig_timeout > AUTO_MODE_FAST) && (trig_auto_rapid == 1)) begin
trig_timeout <= 0;
state_trig <= TRIG_STATE_AUTO;
auto_trig_gen <= 1;
trig_auto_rapid <= 1;
end else if ((trig_mode == TRIG_AUTO) && (trig_timeout > AUTO_MODE_DELAY) && (trig_auto_rapid == 0)) begin
trig_timeout <= 0;
state_trig <= TRIG_STATE_AUTO;
trig_auto_rapid <= 1;
auto_trig_gen <= 1;
end else if ((trig_timeout > NO_TRIG_DELAY) && (trig_mode != TRIG_AUTO)) begin
state_trig <= TRIG_STATE_WAIT;
end
end
if (acq_state == STATE_ACQUIRE) begin
trig_timeout <= 0;
debug_led = 5'b00100;
if (acq_index == ACQ_MAX_SAMPLES) begin
acq_state = STATE_HOLD_OFF;
hold_off <= HOLD_OFF_DELAY;
wr_en_ramout = 0;
end else begin
addr_ramout_a = addr_ramout_a + 1;
addr_ramout_b = addr_ramout_b + 1;
acq_index <= acq_index + 1;
wr_en_ramout = 1;
data_wr_ramout_a = adc_unlatched_data_a;
data_wr_ramout_b = adc_unlatched_data_b;
end
end
if (acq_state == STATE_HOLD_OFF) begin
hold_off <= hold_off - 1;
debug_led = 5'b01000;
if (hold_off == 0) begin
acq_state = STATE_POST_TRIG;
end;
end;
if (acq_state == STATE_POST_TRIG) begin
if (trig_mode == TRIG_SINGLE) begin
state_trig <= TRIG_STATE_DONE;
acq_state = STATE_STOPPED;
end else begin
debug_led = 5'b10000;
if (stop_in) begin
acq_state = STATE_STOPPED;
end else begin
acq_state = STATE_WAIT_FOR_TRIG;
end
end
end
end
endmodule | 3 |
5,877 | data/full_repos/permissive/114943225/comparator.v | 114,943,225 | comparator.v | v | 49 | 76 | [] | [] | [] | [(11, 48)] | null | data/verilator_xmls/6782b811-5f99-4567-bcd1-08b328c543bf.xml | null | 6,725 | module | module comparator (
input clkIn,
input[13:0] threshold,
input[13:0] hysteresis,
input[13:0] adc_data,
output reg q,
output reg z
);
always @(posedge clkIn) begin
if (adc_data > (threshold + hysteresis)) begin
q <= 1;
z <= 0;
end
else if (adc_data < (threshold - hysteresis)) begin
q <= 0;
z <= 0;
end
else begin
z <= 1;
end;
end
endmodule | module comparator (
input clkIn,
input[13:0] threshold,
input[13:0] hysteresis,
input[13:0] adc_data,
output reg q,
output reg z
); |
always @(posedge clkIn) begin
if (adc_data > (threshold + hysteresis)) begin
q <= 1;
z <= 0;
end
else if (adc_data < (threshold - hysteresis)) begin
q <= 0;
z <= 0;
end
else begin
z <= 1;
end;
end
endmodule | 3 |
5,881 | data/full_repos/permissive/114943225/ps2.v | 114,943,225 | ps2.v | v | 62 | 80 | [] | [] | [] | [(6, 61)] | null | data/verilator_xmls/d04a83ab-5624-446b-9147-a76fedf09d90.xml | null | 6,729 | module | module ps2key(
clk50,
kin,
kclk,
code
);
input kin, kclk, clk50;
output [7:0] code;
reg [7:0] code;
reg [3:0] i;
reg [10:0] ksr;
reg [15:0] cnt;
reg reset;
initial begin
ksr = 0;
i = 0;
code = 0;
cnt = 0;
end
always @ (posedge clk50) begin
if (cnt > 3000) begin
reset <= 0;
cnt <= 0;
end
else if (kclk == 1) begin
reset <= 1;
cnt <= cnt + 1;
end
else begin
reset <= 1;
cnt <= 0;
end
end
always @ (negedge kclk or negedge reset) begin
if (reset == 0) begin
ksr <= ksr;
i <= 0;
code <= code;
end
else if (i < 10) begin
ksr[i] <= kin;
i <= i + 1;
code <= code;
end
else begin
i <= 0;
ksr[i] <= kin;
code <= ksr[8:1];
end
end
endmodule | module ps2key(
clk50,
kin,
kclk,
code
); |
input kin, kclk, clk50;
output [7:0] code;
reg [7:0] code;
reg [3:0] i;
reg [10:0] ksr;
reg [15:0] cnt;
reg reset;
initial begin
ksr = 0;
i = 0;
code = 0;
cnt = 0;
end
always @ (posedge clk50) begin
if (cnt > 3000) begin
reset <= 0;
cnt <= 0;
end
else if (kclk == 1) begin
reset <= 1;
cnt <= cnt + 1;
end
else begin
reset <= 1;
cnt <= 0;
end
end
always @ (negedge kclk or negedge reset) begin
if (reset == 0) begin
ksr <= ksr;
i <= 0;
code <= code;
end
else if (i < 10) begin
ksr[i] <= kin;
i <= i + 1;
code <= code;
end
else begin
i <= 0;
ksr[i] <= kin;
code <= ksr[8:1];
end
end
endmodule | 3 |
5,883 | data/full_repos/permissive/114943225/trigger.v | 114,943,225 | trigger.v | v | 96 | 83 | [] | [] | [] | null | line:37: before: ")" | null | 1: b"%Error: data/full_repos/permissive/114943225/trigger.v:15: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\n input[2:0] type,\n ^~~~\n%Error: data/full_repos/permissive/114943225/trigger.v:28: syntax error, unexpected IDENTIFIER\n comparator triggerComp (\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 6,731 | module | module edge_Trig(
input clkIn,
input[13:0] trigLvl,
input[13:0] adc_data,
input[13:0] trigHyst,
input[2:0] type,
input enable,
output reg q
);
wire compEvent;
wire qStore;
reg qStorePos;
reg qStoreNeg;
wire deadZone;
comparator triggerComp (
.clkIn(clkIn),
.threshold(trigLvl),
.hysteresis(trigHyst),
.adc_data(adc_data),
.q(compEvent),
.z(deadZone),
);
initial begin
qStorePos <= 0;
qStoreNeg <= 0;
end
assign qStore = qStorePos | qStoreNeg;
always @(posedge compEvent) begin
if ((type == 3'd1 || type == 3'd3)) begin
qStorePos <= 1 & enable;
end
end
always @(negedge compEvent) begin
if ((type == 3'd2 || type == 3'd3)) begin
qStoreNeg <= 1 & enable;
end
end
always @(posedge clkIn) begin
if (type == 3'd0) begin
q = 0;
end
else if (type == 3'd4) begin
q = 1;
end
else begin
if (deadZone == 0) begin
q = qStore;
end
end
end
endmodule | module edge_Trig(
input clkIn,
input[13:0] trigLvl,
input[13:0] adc_data,
input[13:0] trigHyst,
input[2:0] type,
input enable,
output reg q
); |
wire compEvent;
wire qStore;
reg qStorePos;
reg qStoreNeg;
wire deadZone;
comparator triggerComp (
.clkIn(clkIn),
.threshold(trigLvl),
.hysteresis(trigHyst),
.adc_data(adc_data),
.q(compEvent),
.z(deadZone),
);
initial begin
qStorePos <= 0;
qStoreNeg <= 0;
end
assign qStore = qStorePos | qStoreNeg;
always @(posedge compEvent) begin
if ((type == 3'd1 || type == 3'd3)) begin
qStorePos <= 1 & enable;
end
end
always @(negedge compEvent) begin
if ((type == 3'd2 || type == 3'd3)) begin
qStoreNeg <= 1 & enable;
end
end
always @(posedge clkIn) begin
if (type == 3'd0) begin
q = 0;
end
else if (type == 3'd4) begin
q = 1;
end
else begin
if (deadZone == 0) begin
q = qStore;
end
end
end
endmodule | 3 |
5,888 | data/full_repos/permissive/114943225/vga_fillarea.v | 114,943,225 | vga_fillarea.v | v | 66 | 90 | [] | [] | [] | null | line:66: before: "mainder" | null | 1: b"%Error: data/full_repos/permissive/114943225/vga_fillarea.v:37: Cannot find file containing module: 'vga_colour'\nvga_colour vgacol0(\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114943225,data/full_repos/permissive/114943225/vga_colour\n data/full_repos/permissive/114943225,data/full_repos/permissive/114943225/vga_colour.v\n data/full_repos/permissive/114943225,data/full_repos/permissive/114943225/vga_colour.sv\n vga_colour\n vga_colour.v\n vga_colour.sv\n obj_dir/vga_colour\n obj_dir/vga_colour.v\n obj_dir/vga_colour.sv\n%Error: Exiting due to 1 error(s)\n" | 6,738 | module | module vga_fillarea(
xin, yin,
x0, y0, x1, y1,
colour,
writeout_r, writeout_g, writeout_b
);
input [9:0] xin;
input [9:0] yin;
input [9:0] x0;
input [9:0] y0;
input [9:0] x1;
input [9:0] y1;
input [4:0] colour;
output reg [7:0] writeout_r;
output reg [7:0] writeout_g;
output reg [7:0] writeout_b;
wire [7:0] col_r_gen;
wire [7:0] col_g_gen;
wire [7:0] col_b_gen;
wire cm;
vga_colour vgacol0(
.cin(colour),
.cout_r(col_r_gen),
.cout_g(col_g_gen),
.cout_b(col_b_gen),
.c_mask(cm)
);
always @(*) begin
writeout_r = 8'bZZZZZZZZ;
writeout_g = 8'bZZZZZZZZ;
writeout_b = 8'bZZZZZZZZ;
if ((xin >= x0) && (yin >= y0) && (xin <= x1) && (yin <= y1)) begin
if (cm) begin
writeout_r = col_r_gen;
writeout_g = col_g_gen;
writeout_b = col_b_gen;
end
end
end
endmodule | module vga_fillarea(
xin, yin,
x0, y0, x1, y1,
colour,
writeout_r, writeout_g, writeout_b
); |
input [9:0] xin;
input [9:0] yin;
input [9:0] x0;
input [9:0] y0;
input [9:0] x1;
input [9:0] y1;
input [4:0] colour;
output reg [7:0] writeout_r;
output reg [7:0] writeout_g;
output reg [7:0] writeout_b;
wire [7:0] col_r_gen;
wire [7:0] col_g_gen;
wire [7:0] col_b_gen;
wire cm;
vga_colour vgacol0(
.cin(colour),
.cout_r(col_r_gen),
.cout_g(col_g_gen),
.cout_b(col_b_gen),
.c_mask(cm)
);
always @(*) begin
writeout_r = 8'bZZZZZZZZ;
writeout_g = 8'bZZZZZZZZ;
writeout_b = 8'bZZZZZZZZ;
if ((xin >= x0) && (yin >= y0) && (xin <= x1) && (yin <= y1)) begin
if (cm) begin
writeout_r = col_r_gen;
writeout_g = col_g_gen;
writeout_b = col_b_gen;
end
end
end
endmodule | 3 |
5,889 | data/full_repos/permissive/114943225/vga_vline.v | 114,943,225 | vga_vline.v | v | 98 | 107 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/114943225/vga_vline.v:36: Cannot find file containing module: \'vga_colour\'\nvga_colour vgacol0(\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114943225,data/full_repos/permissive/114943225/vga_colour\n data/full_repos/permissive/114943225,data/full_repos/permissive/114943225/vga_colour.v\n data/full_repos/permissive/114943225,data/full_repos/permissive/114943225/vga_colour.sv\n vga_colour\n vga_colour.v\n vga_colour.sv\n obj_dir/vga_colour\n obj_dir/vga_colour.v\n obj_dir/vga_colour.sv\n%Warning-WIDTH: data/full_repos/permissive/114943225/vga_vline.v:73: Operator AND expects 32 or 10 bits on the RHS, but RHS\'s CONST \'8\'h8\' generates 8 bits.\n : ... In instance vga_vline\n if ((yin & 8\'h08) == 0) begin\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 6,741 | module | module vga_vline(
xin, yin,
x, y0, y1,
colour,
dot_mode,
writeout_r, writeout_g, writeout_b
);
input [9:0] xin;
input [9:0] yin;
input [9:0] x;
input [9:0] y0;
input [9:0] y1;
input [1:0] dot_mode;
input [4:0] colour;
output reg [7:0] writeout_r;
output reg [7:0] writeout_g;
output reg [7:0] writeout_b;
wire [7:0] col_r_gen;
wire [7:0] col_g_gen;
wire [7:0] col_b_gen;
wire cm;
vga_colour vgacol0(
.cin(colour),
.cout_r(col_r_gen),
.cout_g(col_g_gen),
.cout_b(col_b_gen),
.c_mask(cm)
);
always @(*) begin
if ((yin >= y0) && (yin <= y1) && (x == xin)) begin
if (cm) begin
case (dot_mode)
2'b00: begin
writeout_r = col_r_gen;
writeout_g = col_g_gen;
writeout_b = col_b_gen;
end
2'b01: begin
if ((yin & 3) == 0) begin
writeout_r = col_r_gen;
writeout_g = col_g_gen;
writeout_b = col_b_gen;
end else begin
writeout_r = 8'bZZZZZZZZ;
writeout_g = 8'bZZZZZZZZ;
writeout_b = 8'bZZZZZZZZ;
end
end
2'b10: begin
if ((yin & 8'h08) == 0) begin
writeout_r = col_r_gen;
writeout_g = col_g_gen;
writeout_b = col_b_gen;
end else begin
writeout_r = 8'bZZZZZZZZ;
writeout_g = 8'bZZZZZZZZ;
writeout_b = 8'bZZZZZZZZ;
end
end
endcase
end else begin
writeout_r = 8'bZZZZZZZZ;
writeout_g = 8'bZZZZZZZZ;
writeout_b = 8'bZZZZZZZZ;
end
end else begin
writeout_r = 8'bZZZZZZZZ;
writeout_g = 8'bZZZZZZZZ;
writeout_b = 8'bZZZZZZZZ;
end
end
endmodule | module vga_vline(
xin, yin,
x, y0, y1,
colour,
dot_mode,
writeout_r, writeout_g, writeout_b
); |
input [9:0] xin;
input [9:0] yin;
input [9:0] x;
input [9:0] y0;
input [9:0] y1;
input [1:0] dot_mode;
input [4:0] colour;
output reg [7:0] writeout_r;
output reg [7:0] writeout_g;
output reg [7:0] writeout_b;
wire [7:0] col_r_gen;
wire [7:0] col_g_gen;
wire [7:0] col_b_gen;
wire cm;
vga_colour vgacol0(
.cin(colour),
.cout_r(col_r_gen),
.cout_g(col_g_gen),
.cout_b(col_b_gen),
.c_mask(cm)
);
always @(*) begin
if ((yin >= y0) && (yin <= y1) && (x == xin)) begin
if (cm) begin
case (dot_mode)
2'b00: begin
writeout_r = col_r_gen;
writeout_g = col_g_gen;
writeout_b = col_b_gen;
end
2'b01: begin
if ((yin & 3) == 0) begin
writeout_r = col_r_gen;
writeout_g = col_g_gen;
writeout_b = col_b_gen;
end else begin
writeout_r = 8'bZZZZZZZZ;
writeout_g = 8'bZZZZZZZZ;
writeout_b = 8'bZZZZZZZZ;
end
end
2'b10: begin
if ((yin & 8'h08) == 0) begin
writeout_r = col_r_gen;
writeout_g = col_g_gen;
writeout_b = col_b_gen;
end else begin
writeout_r = 8'bZZZZZZZZ;
writeout_g = 8'bZZZZZZZZ;
writeout_b = 8'bZZZZZZZZ;
end
end
endcase
end else begin
writeout_r = 8'bZZZZZZZZ;
writeout_g = 8'bZZZZZZZZ;
writeout_b = 8'bZZZZZZZZ;
end
end else begin
writeout_r = 8'bZZZZZZZZ;
writeout_g = 8'bZZZZZZZZ;
writeout_b = 8'bZZZZZZZZ;
end
end
endmodule | 3 |
5,890 | data/full_repos/permissive/115035459/verilog/src/example001.v | 115,035,459 | example001.v | v | 11 | 34 | [] | [] | [] | [(4, 9)] | null | data/verilator_xmls/1d8d28bd-e343-4527-ac65-629594b02332.xml | null | 6,742 | module | module top (
input J1_3, J1_4,
output LED5
);
assign LED5 = J1_3 & J1_4;
endmodule | module top (
input J1_3, J1_4,
output LED5
); |
assign LED5 = J1_3 & J1_4;
endmodule | 2 |
5,891 | data/full_repos/permissive/115035459/verilog/src/example002.v | 115,035,459 | example002.v | v | 43 | 126 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/example002.v:17: Unsupported: Ignoring delay on this delayed statement.\n #41.7 CLK = ~CLK;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115035459/verilog/src/example002.v:23: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("work/example002.vcd");\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/example002.v:22: Unsupported: Ignoring delay on this delayed statement.\n #0\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/example002.v:24: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, testbench);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/example002.v:25: Unsupported: Ignoring delay on this delayed statement.\n #100000 $finish;\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,743 | module | module testbench;
reg [31:0] counter = 0;
wire [5:1] LED;
reg CLK = 0;
always
#41.7 CLK = ~CLK;
always @(posedge CLK) begin
counter <= counter + 1;
end
initial begin
#0
$dumpfile("work/example002.vcd");
$dumpvars(0, testbench);
#100000 $finish;
end
top #(.LOG2DELAY(1)) my_top_instance (.CLK(CLK), .LED1(LED[1]), .LED2(LED[2]), .LED3(LED[3]), .LED4(LED[4]), .LED5(LED[5]));
endmodule | module testbench; |
reg [31:0] counter = 0;
wire [5:1] LED;
reg CLK = 0;
always
#41.7 CLK = ~CLK;
always @(posedge CLK) begin
counter <= counter + 1;
end
initial begin
#0
$dumpfile("work/example002.vcd");
$dumpvars(0, testbench);
#100000 $finish;
end
top #(.LOG2DELAY(1)) my_top_instance (.CLK(CLK), .LED1(LED[1]), .LED2(LED[2]), .LED3(LED[3]), .LED4(LED[4]), .LED5(LED[5]));
endmodule | 2 |
5,892 | data/full_repos/permissive/115035459/verilog/src/example002.v | 115,035,459 | example002.v | v | 43 | 126 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/example002.v:17: Unsupported: Ignoring delay on this delayed statement.\n #41.7 CLK = ~CLK;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115035459/verilog/src/example002.v:23: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("work/example002.vcd");\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/example002.v:22: Unsupported: Ignoring delay on this delayed statement.\n #0\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/example002.v:24: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, testbench);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/example002.v:25: Unsupported: Ignoring delay on this delayed statement.\n #100000 $finish;\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,743 | module | module top #(parameter LOG2DELAY=20) (input CLK, output LED1, output LED2, output LED3, output LED4, output LED5);
localparam BITS = 5;
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt = 0;
always @(posedge CLK) begin
counter <= counter + 1;
outcnt <= counter >> LOG2DELAY;
end
assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1);
endmodule | module top #(parameter LOG2DELAY=20) (input CLK, output LED1, output LED2, output LED3, output LED4, output LED5); |
localparam BITS = 5;
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt = 0;
always @(posedge CLK) begin
counter <= counter + 1;
outcnt <= counter >> LOG2DELAY;
end
assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1);
endmodule | 2 |
5,894 | data/full_repos/permissive/115035459/verilog/src/example005.ring-oscillator.v | 115,035,459 | example005.ring-oscillator.v | v | 92 | 67 | [] | [] | [] | [(7, 90)] | null | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/example005.ring-oscillator.v:28: Cannot find file containing module: \'SB_LUT4\'\n SB_LUT4 #(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/SB_LUT4\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/SB_LUT4.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/SB_LUT4.sv\n SB_LUT4\n SB_LUT4.v\n SB_LUT4.sv\n obj_dir/SB_LUT4\n obj_dir/SB_LUT4.v\n obj_dir/SB_LUT4.sv\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/example005.ring-oscillator.v:77: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'debounce\' generates 3 bits.\n : ... In instance top\n if (!debounce)\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/example005.ring-oscillator.v:81: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'debounce\' generates 3 bits.\n : ... In instance top\n if (debounce)\n ^~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 6,746 | module | module top(input CLK, output J1_10, LED5, LED1, LED2, LED3, LED4);
wire chain_in, chain_out, resetn;
assign J1_10 = chain_out;
reg [7:0] reset_count = 0;
assign resetn = &reset_count;
always @(posedge CLK) begin
if (!(&reset_count))
reset_count <= reset_count + 1;
end
wire [99:0] buffers_in, buffers_out;
assign buffers_in = {buffers_out[98:0], chain_in};
assign chain_out = buffers_out[99];
assign chain_in = resetn ? !chain_out : 0;
SB_LUT4 #(
.LUT_INIT(16'd2)
) buffers [99:0] (
.O(buffers_out),
.I0(buffers_in),
.I1(1'b0),
.I2(1'b0),
.I3(1'b0)
);
reg [19:0] counter = 23;
reg do_count, do_reset;
always @(posedge chain_out) begin
if (do_reset)
counter <= 0;
else if (do_count)
counter <= counter + 1;
end
reg [1:0] state;
reg [15:0] wait_cnt;
reg [19:0] last_counter;
reg [19:0] this_counter;
reg [2:0] debounce;
reg [4:0] leds;
assign {LED4, LED3, LED2, LED1, LED5} = leds;
always @(posedge CLK) begin
wait_cnt <= wait_cnt + 1;
do_reset <= state == 0;
do_count <= state == 1;
if (!resetn) begin
state <= 0;
wait_cnt <= 0;
leds <= 1;
end else
if (&wait_cnt) begin
if (state == 2) begin
last_counter <= this_counter;
this_counter <= counter;
end
if (state == 3) begin
if (last_counter > this_counter+5) begin
if (!debounce)
leds <= {1'b1, leds[0], leds[3:1]};
debounce <= ~0;
end else begin
if (debounce)
debounce <= debounce-1;
else
leds[4] <= 0;
end
end
state <= state + 1;
end
end
endmodule | module top(input CLK, output J1_10, LED5, LED1, LED2, LED3, LED4); |
wire chain_in, chain_out, resetn;
assign J1_10 = chain_out;
reg [7:0] reset_count = 0;
assign resetn = &reset_count;
always @(posedge CLK) begin
if (!(&reset_count))
reset_count <= reset_count + 1;
end
wire [99:0] buffers_in, buffers_out;
assign buffers_in = {buffers_out[98:0], chain_in};
assign chain_out = buffers_out[99];
assign chain_in = resetn ? !chain_out : 0;
SB_LUT4 #(
.LUT_INIT(16'd2)
) buffers [99:0] (
.O(buffers_out),
.I0(buffers_in),
.I1(1'b0),
.I2(1'b0),
.I3(1'b0)
);
reg [19:0] counter = 23;
reg do_count, do_reset;
always @(posedge chain_out) begin
if (do_reset)
counter <= 0;
else if (do_count)
counter <= counter + 1;
end
reg [1:0] state;
reg [15:0] wait_cnt;
reg [19:0] last_counter;
reg [19:0] this_counter;
reg [2:0] debounce;
reg [4:0] leds;
assign {LED4, LED3, LED2, LED1, LED5} = leds;
always @(posedge CLK) begin
wait_cnt <= wait_cnt + 1;
do_reset <= state == 0;
do_count <= state == 1;
if (!resetn) begin
state <= 0;
wait_cnt <= 0;
leds <= 1;
end else
if (&wait_cnt) begin
if (state == 2) begin
last_counter <= this_counter;
this_counter <= counter;
end
if (state == 3) begin
if (last_counter > this_counter+5) begin
if (!debounce)
leds <= {1'b1, leds[0], leds[3:1]};
debounce <= ~0;
end else begin
if (debounce)
debounce <= debounce-1;
else
leds[4] <= 0;
end
end
state <= state + 1;
end
end
endmodule | 2 |
5,898 | data/full_repos/permissive/115035459/verilog/src/mza-test002.v | 115,035,459 | mza-test002.v | v | 34 | 88 | [] | [] | [] | [(5, 32)] | null | data/verilator_xmls/75ce7a7d-ecf7-4de9-966a-b64b160af966.xml | null | 6,751 | module | module top(input CLK, output LED1, output LED2, output LED3, output LED4, output LED5);
reg ready = 0;
reg [23:0] divider;
reg [3:0] rot;
always @(posedge CLK) begin
if (ready)
begin
if (divider == 12000000)
begin
divider <= 0;
rot <= {rot[2:0], rot[3]};
end
else
divider <= divider + 1;
end
else
begin
ready <= 1;
rot <= 4'b0011;
divider <= 0;
end
end
assign LED1 = rot[0];
assign LED2 = rot[1];
assign LED3 = rot[2];
assign LED4 = rot[3];
assign LED5 = 1;
endmodule | module top(input CLK, output LED1, output LED2, output LED3, output LED4, output LED5); |
reg ready = 0;
reg [23:0] divider;
reg [3:0] rot;
always @(posedge CLK) begin
if (ready)
begin
if (divider == 12000000)
begin
divider <= 0;
rot <= {rot[2:0], rot[3]};
end
else
divider <= divider + 1;
end
else
begin
ready <= 1;
rot <= 4'b0011;
divider <= 0;
end
end
assign LED1 = rot[0];
assign LED2 = rot[1];
assign LED3 = rot[2];
assign LED4 = rot[3];
assign LED5 = 1;
endmodule | 2 |
5,899 | data/full_repos/permissive/115035459/verilog/src/mza-test003.double-dabble.v | 115,035,459 | mza-test003.double-dabble.v | v | 86 | 203 | [] | [] | [] | null | line:30: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test003.double-dabble.v:6: Cannot find include file: lib/hex2bcd.v\n`include "lib/hex2bcd.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v.sv\n lib/hex2bcd.v\n lib/hex2bcd.v.v\n lib/hex2bcd.v.sv\n obj_dir/lib/hex2bcd.v\n obj_dir/lib/hex2bcd.v.v\n obj_dir/lib/hex2bcd.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test003.double-dabble.v:7: Cannot find include file: lib/segmented_display_driver.v\n`include "lib/segmented_display_driver.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 6,752 | module | module top (
input CLK,
output LED1, LED2, LED3, LED4, LED5,
output J1_3, J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10,
output J2_1, J2_2, J2_3, J2_4, J2_7, J2_8, J2_9, J2_10,
output J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10
);
reg [39:0] counter = 0;
reg reset = 1;
always @(posedge CLK) begin
if (reset) begin
if (counter[10]) begin
reset <= 0;
end
end
counter <= counter + 1'b1;
end
wire [23:0] bcd;
wire [15:0] data = counter[39:24];
hex2bcd #(.INPUT_SIZE_IN_NYBBLES(4)) h2binst ( .clock(CLK), .reset(reset), .hex_in(data), .bcd_out(bcd), .sync() );
if (1) begin
assign LED5 = bcd[4];
assign LED4 = bcd[3];
assign LED3 = bcd[2];
assign LED2 = bcd[1];
assign LED1 = bcd[0];
end else begin
assign LED5 = 0;
assign LED4 = bcd[7];
assign LED3 = bcd[6];
assign LED2 = bcd[5];
assign LED1 = bcd[4];
end
if (1) begin
wire [6:0] segment;
assign J1_4 = segment[0];
assign J3_8 = segment[1];
assign J3_5 = segment[2];
assign J3_3 = segment[3];
assign J2_1 = segment[4];
assign J1_5 = segment[5];
assign J3_6 = segment[6];
assign J3_4 = 1;
wire [3:0] anode;
assign J3_7 = anode[0];
assign J1_7 = anode[1];
assign J1_6 = anode[2];
assign J1_3 = anode[3];
segmented_display_driver #(.NUMBER_OF_SEGMENTS(7), .NUMBER_OF_NYBBLES(4)) my_instance_name (.clock(CLK), .data(bcd[15:0]), .dp(4'd0), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode());
end else begin
wire [15:0] segment;
assign J2_7 = segment[00];
assign J2_2 = segment[01];
assign J2_4 = segment[02];
assign J1_5 = segment[03];
assign J3_8 = segment[04];
assign J3_7 = segment[05];
assign J3_5 = segment[06];
assign J3_4 = segment[07];
assign J3_3 = segment[08];
assign J2_1 = segment[09];
assign J2_10 = segment[10];
assign J1_4 = segment[11];
assign J1_3 = segment[12];
assign J3_6 = segment[13];
assign J1_7 = segment[14];
assign J1_6 = segment[15];
assign J1_8 = 1;
wire [1:0] anode;
assign J2_9 = anode[0];
assign J1_9 = anode[0];
segmented_display_driver #(.NUMBER_OF_SEGMENTS(16), .NUMBER_OF_NYBBLES(2)) my_instance_name (.clock(CLK), .data(bcd[7:0]), .dp(2'd0), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode());
end
endmodule | module top (
input CLK,
output LED1, LED2, LED3, LED4, LED5,
output J1_3, J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10,
output J2_1, J2_2, J2_3, J2_4, J2_7, J2_8, J2_9, J2_10,
output J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10
); |
reg [39:0] counter = 0;
reg reset = 1;
always @(posedge CLK) begin
if (reset) begin
if (counter[10]) begin
reset <= 0;
end
end
counter <= counter + 1'b1;
end
wire [23:0] bcd;
wire [15:0] data = counter[39:24];
hex2bcd #(.INPUT_SIZE_IN_NYBBLES(4)) h2binst ( .clock(CLK), .reset(reset), .hex_in(data), .bcd_out(bcd), .sync() );
if (1) begin
assign LED5 = bcd[4];
assign LED4 = bcd[3];
assign LED3 = bcd[2];
assign LED2 = bcd[1];
assign LED1 = bcd[0];
end else begin
assign LED5 = 0;
assign LED4 = bcd[7];
assign LED3 = bcd[6];
assign LED2 = bcd[5];
assign LED1 = bcd[4];
end
if (1) begin
wire [6:0] segment;
assign J1_4 = segment[0];
assign J3_8 = segment[1];
assign J3_5 = segment[2];
assign J3_3 = segment[3];
assign J2_1 = segment[4];
assign J1_5 = segment[5];
assign J3_6 = segment[6];
assign J3_4 = 1;
wire [3:0] anode;
assign J3_7 = anode[0];
assign J1_7 = anode[1];
assign J1_6 = anode[2];
assign J1_3 = anode[3];
segmented_display_driver #(.NUMBER_OF_SEGMENTS(7), .NUMBER_OF_NYBBLES(4)) my_instance_name (.clock(CLK), .data(bcd[15:0]), .dp(4'd0), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode());
end else begin
wire [15:0] segment;
assign J2_7 = segment[00];
assign J2_2 = segment[01];
assign J2_4 = segment[02];
assign J1_5 = segment[03];
assign J3_8 = segment[04];
assign J3_7 = segment[05];
assign J3_5 = segment[06];
assign J3_4 = segment[07];
assign J3_3 = segment[08];
assign J2_1 = segment[09];
assign J2_10 = segment[10];
assign J1_4 = segment[11];
assign J1_3 = segment[12];
assign J3_6 = segment[13];
assign J1_7 = segment[14];
assign J1_6 = segment[15];
assign J1_8 = 1;
wire [1:0] anode;
assign J2_9 = anode[0];
assign J1_9 = anode[0];
segmented_display_driver #(.NUMBER_OF_SEGMENTS(16), .NUMBER_OF_NYBBLES(2)) my_instance_name (.clock(CLK), .data(bcd[7:0]), .dp(2'd0), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode());
end
endmodule | 2 |
5,900 | data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v | 115,035,459 | mza-test004.16-segment-driver.v | v | 149 | 125 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:63: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n reg [15:0] sequence = 0;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:63: syntax error, unexpected INTEGER NUMBER, expecting new or new-then-paren\n reg [15:0] sequence = 0;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:89: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h0 : sequence <= 16'b0000000011111111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:89: syntax error, unexpected <=\n 4'h0 : sequence <= 16'b0000000011111111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:90: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h1 : sequence <= 16'b1100111111111111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:90: syntax error, unexpected <=\n 4'h1 : sequence <= 16'b1100111111111111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:91: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h2 : sequence <= 16'b0001000111100111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:91: syntax error, unexpected <=\n 4'h2 : sequence <= 16'b0001000111100111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:92: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h3 : sequence <= 16'b0000001111100111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:92: syntax error, unexpected <=\n 4'h3 : sequence <= 16'b0000001111100111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:93: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h4 : sequence <= 16'b1100111011100111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:93: syntax error, unexpected <=\n 4'h4 : sequence <= 16'b1100111011100111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:94: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h5 : sequence <= 16'b0010001011100111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:94: syntax error, unexpected <=\n 4'h5 : sequence <= 16'b0010001011100111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:95: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h6 : sequence <= 16'b0010000011100111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:95: syntax error, unexpected <=\n 4'h6 : sequence <= 16'b0010000011100111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:96: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h7 : sequence <= 16'b0000111111111111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:96: syntax error, unexpected <=\n 4'h7 : sequence <= 16'b0000111111111111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:97: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h8 : sequence <= 16'b0000000011100111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:97: syntax error, unexpected <=\n 4'h8 : sequence <= 16'b0000000011100111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:98: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h9 : sequence <= 16'b0000001011100111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:98: syntax error, unexpected <=\n 4'h9 : sequence <= 16'b0000001011100111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:99: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'ha : sequence <= 16'b0000110011100111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:99: syntax error, unexpected <=\n 4'ha : sequence <= 16'b0000110011100111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:100: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'hb : sequence <= 16'b1110000011100111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:100: syntax error, unexpected <=\n 4'hb : sequence <= 16'b1110000011100111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:101: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'hc : sequence <= 16'b0011000011111111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:101: syntax error, unexpected <=\n 4'hc : sequence <= 16'b0011000011111111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:102: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'hd : sequence <= 16'b1100000111100111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:102: syntax error, unexpected <=\n 4'hd : sequence <= 16'b1100000111100111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:103: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'he : sequence <= 16'b0011000011101111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:103: syntax error, unexpected <=\n 4'he : sequence <= 16'b0011000011101111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:104: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n default : sequence <= 16'b0011110011101111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:104: syntax error, unexpected <=\n default : sequence <= 16'b0011110011101111;\n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:128: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h0 : begin segment_a <= sequence[15]; segment_r <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:128: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n 4'h0 : begin segment_a <= sequence[15]; segment_r <= 1; end \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:129: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h1 : begin segment_b <= sequence[14]; segment_a <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:129: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n 4'h1 : begin segment_b <= sequence[14]; segment_a <= 1; end \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:130: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h2 : begin segment_c <= sequence[13]; segment_b <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:130: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n 4'h2 : begin segment_c <= sequence[13]; segment_b <= 1; end \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:131: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h3 : begin segment_d <= sequence[12]; segment_c <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:131: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n 4'h3 : begin segment_d <= sequence[12]; segment_c <= 1; end \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:132: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h4 : begin segment_e <= sequence[11]; segment_d <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:132: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n 4'h4 : begin segment_e <= sequence[11]; segment_d <= 1; end \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:133: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h5 : begin segment_f <= sequence[10]; segment_e <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:133: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n 4'h5 : begin segment_f <= sequence[10]; segment_e <= 1; end \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:134: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h6 : begin segment_g <= sequence[09]; segment_f <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:134: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n 4'h6 : begin segment_g <= sequence[09]; segment_f <= 1; end \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:135: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h7 : begin segment_h <= sequence[08]; segment_g <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:135: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n 4'h7 : begin segment_h <= sequence[08]; segment_g <= 1; end \n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n" | 6,753 | module | module top (
input CLK,
output reg LED1 = 0,
output reg LED2 = 0,
output reg LED3 = 0,
output reg LED4 = 0,
output reg LED5 = 0,
output J1_3, J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10,
output J2_1, J2_2, J2_3, J2_4, J2_7, J2_8, J2_9, J2_10,
output J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10
);
reg segment_a = 0;
reg segment_b = 0;
reg segment_c = 0;
reg segment_d = 0;
reg segment_e = 0;
reg segment_f = 0;
reg segment_g = 0;
reg segment_h = 0;
reg segment_k = 0;
reg segment_m = 0;
reg segment_n = 0;
reg segment_u = 0;
reg segment_p = 0;
reg segment_t = 0;
reg segment_s = 0;
reg segment_r = 0;
reg segment_dp = 0;
assign J2_7 = segment_a;
assign J2_2 = segment_b;
assign J2_4 = segment_c;
assign J1_5 = segment_d;
assign J3_8 = segment_e;
assign J3_7 = segment_f;
assign J3_5 = segment_g;
assign J3_4 = segment_h;
assign J3_3 = segment_k;
assign J2_1 = segment_m;
assign J2_10 = segment_n;
assign J1_4 = segment_u;
assign J1_3 = segment_p;
assign J3_6 = segment_t;
assign J1_7 = segment_s;
assign J1_6 = segment_r;
assign J1_8 = segment_dp;
assign J2_9 = 1;
assign J1_9 = 1;
assign J2_3 = 1;
assign J1_10 = 1;
assign J2_8 = 1;
assign J3_9 = 1;
assign J3_10 = 1;
reg [31:0] raw_counter = 0;
reg dot_clock = 0;
reg [3:0] dot_counter = 0;
reg clock_1Hz = 0;
reg [3:0] counter_1Hz = 0;
reg [15:0] sequence = 0;
reg reset = 0;
always @(posedge CLK) begin
if (raw_counter[31:12]==0) begin
reset <= 1;
LED1 <= 0;
LED2 <= 0;
LED3 <= 0;
LED4 <= 0;
LED5 <= 0;
end else begin
LED5 <= dot_clock;
reset <= 0;
end
raw_counter++;
end
always begin
dot_clock <= raw_counter[12];
dot_counter <= raw_counter[16:13];
end
always begin
clock_1Hz <= raw_counter[23];
counter_1Hz <= raw_counter[27:24];
end
always @(posedge clock_1Hz) begin
case(counter_1Hz[3:0])
4'h0 : sequence <= 16'b0000000011111111;
4'h1 : sequence <= 16'b1100111111111111;
4'h2 : sequence <= 16'b0001000111100111;
4'h3 : sequence <= 16'b0000001111100111;
4'h4 : sequence <= 16'b1100111011100111;
4'h5 : sequence <= 16'b0010001011100111;
4'h6 : sequence <= 16'b0010000011100111;
4'h7 : sequence <= 16'b0000111111111111;
4'h8 : sequence <= 16'b0000000011100111;
4'h9 : sequence <= 16'b0000001011100111;
4'ha : sequence <= 16'b0000110011100111;
4'hb : sequence <= 16'b1110000011100111;
4'hc : sequence <= 16'b0011000011111111;
4'hd : sequence <= 16'b1100000111100111;
4'he : sequence <= 16'b0011000011101111;
default : sequence <= 16'b0011110011101111;
endcase
end
always @(posedge dot_clock) begin
if (reset==1) begin
segment_a <= 1;
segment_b <= 1;
segment_c <= 1;
segment_d <= 1;
segment_e <= 1;
segment_f <= 1;
segment_g <= 1;
segment_h <= 1;
segment_k <= 1;
segment_m <= 1;
segment_n <= 1;
segment_u <= 1;
segment_p <= 1;
segment_t <= 1;
segment_s <= 1;
segment_r <= 1;
segment_dp <= 1;
end else begin
case(dot_counter)
4'h0 : begin segment_a <= sequence[15]; segment_r <= 1; end
4'h1 : begin segment_b <= sequence[14]; segment_a <= 1; end
4'h2 : begin segment_c <= sequence[13]; segment_b <= 1; end
4'h3 : begin segment_d <= sequence[12]; segment_c <= 1; end
4'h4 : begin segment_e <= sequence[11]; segment_d <= 1; end
4'h5 : begin segment_f <= sequence[10]; segment_e <= 1; end
4'h6 : begin segment_g <= sequence[09]; segment_f <= 1; end
4'h7 : begin segment_h <= sequence[08]; segment_g <= 1; end
4'h8 : begin segment_k <= sequence[07]; segment_h <= 1; end
4'h9 : begin segment_m <= sequence[06]; segment_k <= 1; end
4'ha : begin segment_n <= sequence[05]; segment_m <= 1; end
4'hb : begin segment_u <= sequence[04]; segment_n <= 1; end
4'hc : begin segment_p <= sequence[03]; segment_u <= 1; end
4'hd : begin segment_t <= sequence[02]; segment_p <= 1; end
4'he : begin segment_s <= sequence[01]; segment_t <= 1; end
default : begin segment_r <= sequence[00]; segment_s <= 1; end
endcase
end
end
endmodule | module top (
input CLK,
output reg LED1 = 0,
output reg LED2 = 0,
output reg LED3 = 0,
output reg LED4 = 0,
output reg LED5 = 0,
output J1_3, J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10,
output J2_1, J2_2, J2_3, J2_4, J2_7, J2_8, J2_9, J2_10,
output J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10
); |
reg segment_a = 0;
reg segment_b = 0;
reg segment_c = 0;
reg segment_d = 0;
reg segment_e = 0;
reg segment_f = 0;
reg segment_g = 0;
reg segment_h = 0;
reg segment_k = 0;
reg segment_m = 0;
reg segment_n = 0;
reg segment_u = 0;
reg segment_p = 0;
reg segment_t = 0;
reg segment_s = 0;
reg segment_r = 0;
reg segment_dp = 0;
assign J2_7 = segment_a;
assign J2_2 = segment_b;
assign J2_4 = segment_c;
assign J1_5 = segment_d;
assign J3_8 = segment_e;
assign J3_7 = segment_f;
assign J3_5 = segment_g;
assign J3_4 = segment_h;
assign J3_3 = segment_k;
assign J2_1 = segment_m;
assign J2_10 = segment_n;
assign J1_4 = segment_u;
assign J1_3 = segment_p;
assign J3_6 = segment_t;
assign J1_7 = segment_s;
assign J1_6 = segment_r;
assign J1_8 = segment_dp;
assign J2_9 = 1;
assign J1_9 = 1;
assign J2_3 = 1;
assign J1_10 = 1;
assign J2_8 = 1;
assign J3_9 = 1;
assign J3_10 = 1;
reg [31:0] raw_counter = 0;
reg dot_clock = 0;
reg [3:0] dot_counter = 0;
reg clock_1Hz = 0;
reg [3:0] counter_1Hz = 0;
reg [15:0] sequence = 0;
reg reset = 0;
always @(posedge CLK) begin
if (raw_counter[31:12]==0) begin
reset <= 1;
LED1 <= 0;
LED2 <= 0;
LED3 <= 0;
LED4 <= 0;
LED5 <= 0;
end else begin
LED5 <= dot_clock;
reset <= 0;
end
raw_counter++;
end
always begin
dot_clock <= raw_counter[12];
dot_counter <= raw_counter[16:13];
end
always begin
clock_1Hz <= raw_counter[23];
counter_1Hz <= raw_counter[27:24];
end
always @(posedge clock_1Hz) begin
case(counter_1Hz[3:0])
4'h0 : sequence <= 16'b0000000011111111;
4'h1 : sequence <= 16'b1100111111111111;
4'h2 : sequence <= 16'b0001000111100111;
4'h3 : sequence <= 16'b0000001111100111;
4'h4 : sequence <= 16'b1100111011100111;
4'h5 : sequence <= 16'b0010001011100111;
4'h6 : sequence <= 16'b0010000011100111;
4'h7 : sequence <= 16'b0000111111111111;
4'h8 : sequence <= 16'b0000000011100111;
4'h9 : sequence <= 16'b0000001011100111;
4'ha : sequence <= 16'b0000110011100111;
4'hb : sequence <= 16'b1110000011100111;
4'hc : sequence <= 16'b0011000011111111;
4'hd : sequence <= 16'b1100000111100111;
4'he : sequence <= 16'b0011000011101111;
default : sequence <= 16'b0011110011101111;
endcase
end
always @(posedge dot_clock) begin
if (reset==1) begin
segment_a <= 1;
segment_b <= 1;
segment_c <= 1;
segment_d <= 1;
segment_e <= 1;
segment_f <= 1;
segment_g <= 1;
segment_h <= 1;
segment_k <= 1;
segment_m <= 1;
segment_n <= 1;
segment_u <= 1;
segment_p <= 1;
segment_t <= 1;
segment_s <= 1;
segment_r <= 1;
segment_dp <= 1;
end else begin
case(dot_counter)
4'h0 : begin segment_a <= sequence[15]; segment_r <= 1; end
4'h1 : begin segment_b <= sequence[14]; segment_a <= 1; end
4'h2 : begin segment_c <= sequence[13]; segment_b <= 1; end
4'h3 : begin segment_d <= sequence[12]; segment_c <= 1; end
4'h4 : begin segment_e <= sequence[11]; segment_d <= 1; end
4'h5 : begin segment_f <= sequence[10]; segment_e <= 1; end
4'h6 : begin segment_g <= sequence[09]; segment_f <= 1; end
4'h7 : begin segment_h <= sequence[08]; segment_g <= 1; end
4'h8 : begin segment_k <= sequence[07]; segment_h <= 1; end
4'h9 : begin segment_m <= sequence[06]; segment_k <= 1; end
4'ha : begin segment_n <= sequence[05]; segment_m <= 1; end
4'hb : begin segment_u <= sequence[04]; segment_n <= 1; end
4'hc : begin segment_p <= sequence[03]; segment_u <= 1; end
4'hd : begin segment_t <= sequence[02]; segment_p <= 1; end
4'he : begin segment_s <= sequence[01]; segment_t <= 1; end
default : begin segment_r <= sequence[00]; segment_s <= 1; end
endcase
end
end
endmodule | 2 |
5,902 | data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v | 115,035,459 | mza-test006.7-segment-driver.v | v | 139 | 127 | [] | [] | [] | null | line:9: before: "=" | null | 1: b"%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:48: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n reg [6:0] sequence = 0;\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:48: syntax error, unexpected INTEGER NUMBER, expecting new or new-then-paren\n reg [6:0] sequence = 0;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:107: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h0 : begin anode0001 <= 1; anode1000 <= 0; sequence <= sequence0001; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:107: syntax error, unexpected <=\n 4'h0 : begin anode0001 <= 1; anode1000 <= 0; sequence <= sequence0001; end \n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:108: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h1 : begin anode0010 <= 1; anode0001 <= 0; sequence <= sequence0010; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:108: syntax error, unexpected <=\n 4'h1 : begin anode0010 <= 1; anode0001 <= 0; sequence <= sequence0010; end \n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:109: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 4'h2 : begin anode0100 <= 1; anode0010 <= 0; sequence <= sequence0100; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:109: syntax error, unexpected <=\n 4'h2 : begin anode0100 <= 1; anode0010 <= 0; sequence <= sequence0100; end \n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:110: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n default : begin anode1000 <= 1; anode0100 <= 0; sequence <= sequence1000; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:110: syntax error, unexpected <=\n default : begin anode1000 <= 1; anode0100 <= 0; sequence <= sequence1000; end \n ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:126: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 7'b0000001 : begin segment_a <= sequence[6]; segment_g <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:126: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n 7'b0000001 : begin segment_a <= sequence[6]; segment_g <= 1; end \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:127: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 7'b0000010 : begin segment_b <= sequence[5]; segment_a <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:127: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n 7'b0000010 : begin segment_b <= sequence[5]; segment_a <= 1; end \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:128: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 7'b0000100 : begin segment_c <= sequence[4]; segment_b <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:128: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n 7'b0000100 : begin segment_c <= sequence[4]; segment_b <= 1; end \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:129: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 7'b0001000 : begin segment_d <= sequence[3]; segment_c <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:129: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n 7'b0001000 : begin segment_d <= sequence[3]; segment_c <= 1; end \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:130: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 7'b0010000 : begin segment_e <= sequence[2]; segment_d <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:130: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n 7'b0010000 : begin segment_e <= sequence[2]; segment_d <= 1; end \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:131: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n 7'b0100000 : begin segment_f <= sequence[1]; segment_e <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:131: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n 7'b0100000 : begin segment_f <= sequence[1]; segment_e <= 1; end \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:132: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n default : begin segment_g <= sequence[0]; segment_f <= 1; end \n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test006.7-segment-driver.v:132: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n default : begin segment_g <= sequence[0]; segment_f <= 1; end \n ^\n%Error: Exiting due to 24 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 6,755 | module | module top (
input CLK,
output reg LED1 = 0,
output reg LED2 = 0,
output reg LED3 = 0,
output reg LED4 = 0,
output reg LED5 = 0,
output J1_3, J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10,
output J2_1, J2_2, J2_3, J2_4, J2_7, J2_8, J2_9, J2_10,
output J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10
);
reg segment_a = 0;
reg segment_b = 0;
reg segment_c = 0;
reg segment_d = 0;
reg segment_e = 0;
reg segment_f = 0;
reg segment_g = 0;
assign J1_4 = segment_a;
assign J3_8 = segment_b;
assign J3_5 = segment_c;
assign J3_3 = segment_d;
assign J2_1 = segment_e;
assign J1_5 = segment_f;
assign J3_6 = segment_g;
assign J3_4 = 1;
reg anode0001 = 0;
reg anode0010 = 0;
reg anode0100 = 0;
reg anode1000 = 0;
assign J3_7 = anode0001;
assign J1_7 = anode0010;
assign J1_6 = anode0100;
assign J1_3 = anode1000;
reg [31:0] raw_counter = 0;
wire digit_clock;
wire [1:0] digit_counter;
wire dot_clock;
reg [6:0] dot_token = 0;
wire clock_1Hz;
wire [3:0] counter_1Hz;
reg [6:0] sequence = 0;
reg [6:0] sequence0001 = 0;
reg [6:0] sequence0010 = 0;
reg [6:0] sequence0100 = 0;
reg [6:0] sequence1000 = 0;
reg reset = 0;
always @(posedge CLK) begin
if (raw_counter[31:12]==0) begin
reset <= 1;
LED1 <= 0;
LED2 <= 0;
LED3 <= 0;
LED4 <= 0;
LED5 <= 0;
end else begin
reset <= 0;
LED4 <= digit_clock;
LED5 <= dot_clock;
end
raw_counter++;
end
localparam dot_clock_pickoff = 3;
localparam digit_clock_pickoff = dot_clock_pickoff + 4;
assign digit_clock = raw_counter[digit_clock_pickoff];
assign digit_counter = raw_counter[digit_clock_pickoff+2:digit_clock_pickoff+1];
assign dot_clock = raw_counter[dot_clock_pickoff];
assign clock_1Hz = raw_counter[23];
assign counter_1Hz = raw_counter[27:24];
always @(posedge clock_1Hz) begin
sequence1000 <= sequence0100;
sequence0100 <= sequence0010;
sequence0010 <= sequence0001;
case(counter_1Hz[3:0])
4'h0 : sequence0001 <= 7'b0000001;
4'h1 : sequence0001 <= 7'b1001111;
4'h2 : sequence0001 <= 7'b0010010;
4'h3 : sequence0001 <= 7'b0000110;
4'h4 : sequence0001 <= 7'b1001100;
4'h5 : sequence0001 <= 7'b0100100;
4'h6 : sequence0001 <= 7'b0100000;
4'h7 : sequence0001 <= 7'b0001111;
4'h8 : sequence0001 <= 7'b0000000;
4'h9 : sequence0001 <= 7'b0000100;
4'ha : sequence0001 <= 7'b0001000;
4'hb : sequence0001 <= 7'b1100000;
4'hc : sequence0001 <= 7'b1110010;
4'hd : sequence0001 <= 7'b1000010;
4'he : sequence0001 <= 7'b0110000;
default : sequence0001 <= 7'b0111000;
endcase
end
always @(posedge digit_clock) begin
if (reset==1) begin
anode0001 <= 0;
anode0010 <= 0;
anode0100 <= 0;
anode1000 <= 0;
end else begin
case(digit_counter)
4'h0 : begin anode0001 <= 1; anode1000 <= 0; sequence <= sequence0001; end
4'h1 : begin anode0010 <= 1; anode0001 <= 0; sequence <= sequence0010; end
4'h2 : begin anode0100 <= 1; anode0010 <= 0; sequence <= sequence0100; end
default : begin anode1000 <= 1; anode0100 <= 0; sequence <= sequence1000; end
endcase
end
end
always @(posedge dot_clock) begin
if (reset==1) begin
segment_a <= 1;
segment_b <= 1;
segment_c <= 1;
segment_d <= 1;
segment_e <= 1;
segment_f <= 1;
segment_g <= 1;
dot_token <= 7'b0000001;
end else begin
case(dot_token)
7'b0000001 : begin segment_a <= sequence[6]; segment_g <= 1; end
7'b0000010 : begin segment_b <= sequence[5]; segment_a <= 1; end
7'b0000100 : begin segment_c <= sequence[4]; segment_b <= 1; end
7'b0001000 : begin segment_d <= sequence[3]; segment_c <= 1; end
7'b0010000 : begin segment_e <= sequence[2]; segment_d <= 1; end
7'b0100000 : begin segment_f <= sequence[1]; segment_e <= 1; end
default : begin segment_g <= sequence[0]; segment_f <= 1; end
endcase
dot_token <= { dot_token[5:0], dot_token[6] };
end
end
endmodule | module top (
input CLK,
output reg LED1 = 0,
output reg LED2 = 0,
output reg LED3 = 0,
output reg LED4 = 0,
output reg LED5 = 0,
output J1_3, J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10,
output J2_1, J2_2, J2_3, J2_4, J2_7, J2_8, J2_9, J2_10,
output J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10
); |
reg segment_a = 0;
reg segment_b = 0;
reg segment_c = 0;
reg segment_d = 0;
reg segment_e = 0;
reg segment_f = 0;
reg segment_g = 0;
assign J1_4 = segment_a;
assign J3_8 = segment_b;
assign J3_5 = segment_c;
assign J3_3 = segment_d;
assign J2_1 = segment_e;
assign J1_5 = segment_f;
assign J3_6 = segment_g;
assign J3_4 = 1;
reg anode0001 = 0;
reg anode0010 = 0;
reg anode0100 = 0;
reg anode1000 = 0;
assign J3_7 = anode0001;
assign J1_7 = anode0010;
assign J1_6 = anode0100;
assign J1_3 = anode1000;
reg [31:0] raw_counter = 0;
wire digit_clock;
wire [1:0] digit_counter;
wire dot_clock;
reg [6:0] dot_token = 0;
wire clock_1Hz;
wire [3:0] counter_1Hz;
reg [6:0] sequence = 0;
reg [6:0] sequence0001 = 0;
reg [6:0] sequence0010 = 0;
reg [6:0] sequence0100 = 0;
reg [6:0] sequence1000 = 0;
reg reset = 0;
always @(posedge CLK) begin
if (raw_counter[31:12]==0) begin
reset <= 1;
LED1 <= 0;
LED2 <= 0;
LED3 <= 0;
LED4 <= 0;
LED5 <= 0;
end else begin
reset <= 0;
LED4 <= digit_clock;
LED5 <= dot_clock;
end
raw_counter++;
end
localparam dot_clock_pickoff = 3;
localparam digit_clock_pickoff = dot_clock_pickoff + 4;
assign digit_clock = raw_counter[digit_clock_pickoff];
assign digit_counter = raw_counter[digit_clock_pickoff+2:digit_clock_pickoff+1];
assign dot_clock = raw_counter[dot_clock_pickoff];
assign clock_1Hz = raw_counter[23];
assign counter_1Hz = raw_counter[27:24];
always @(posedge clock_1Hz) begin
sequence1000 <= sequence0100;
sequence0100 <= sequence0010;
sequence0010 <= sequence0001;
case(counter_1Hz[3:0])
4'h0 : sequence0001 <= 7'b0000001;
4'h1 : sequence0001 <= 7'b1001111;
4'h2 : sequence0001 <= 7'b0010010;
4'h3 : sequence0001 <= 7'b0000110;
4'h4 : sequence0001 <= 7'b1001100;
4'h5 : sequence0001 <= 7'b0100100;
4'h6 : sequence0001 <= 7'b0100000;
4'h7 : sequence0001 <= 7'b0001111;
4'h8 : sequence0001 <= 7'b0000000;
4'h9 : sequence0001 <= 7'b0000100;
4'ha : sequence0001 <= 7'b0001000;
4'hb : sequence0001 <= 7'b1100000;
4'hc : sequence0001 <= 7'b1110010;
4'hd : sequence0001 <= 7'b1000010;
4'he : sequence0001 <= 7'b0110000;
default : sequence0001 <= 7'b0111000;
endcase
end
always @(posedge digit_clock) begin
if (reset==1) begin
anode0001 <= 0;
anode0010 <= 0;
anode0100 <= 0;
anode1000 <= 0;
end else begin
case(digit_counter)
4'h0 : begin anode0001 <= 1; anode1000 <= 0; sequence <= sequence0001; end
4'h1 : begin anode0010 <= 1; anode0001 <= 0; sequence <= sequence0010; end
4'h2 : begin anode0100 <= 1; anode0010 <= 0; sequence <= sequence0100; end
default : begin anode1000 <= 1; anode0100 <= 0; sequence <= sequence1000; end
endcase
end
end
always @(posedge dot_clock) begin
if (reset==1) begin
segment_a <= 1;
segment_b <= 1;
segment_c <= 1;
segment_d <= 1;
segment_e <= 1;
segment_f <= 1;
segment_g <= 1;
dot_token <= 7'b0000001;
end else begin
case(dot_token)
7'b0000001 : begin segment_a <= sequence[6]; segment_g <= 1; end
7'b0000010 : begin segment_b <= sequence[5]; segment_a <= 1; end
7'b0000100 : begin segment_c <= sequence[4]; segment_b <= 1; end
7'b0001000 : begin segment_d <= sequence[3]; segment_c <= 1; end
7'b0010000 : begin segment_e <= sequence[2]; segment_d <= 1; end
7'b0100000 : begin segment_f <= sequence[1]; segment_e <= 1; end
default : begin segment_g <= sequence[0]; segment_f <= 1; end
endcase
dot_token <= { dot_token[5:0], dot_token[6] };
end
end
endmodule | 2 |
5,904 | data/full_repos/permissive/115035459/verilog/src/mza-test009.multi-segment-driver.v | 115,035,459 | mza-test009.multi-segment-driver.v | v | 129 | 236 | [] | [] | [] | null | line:31: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test009.multi-segment-driver.v:7: Cannot find include file: lib/hex2bcd.v\n`include "lib/hex2bcd.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v.sv\n lib/hex2bcd.v\n lib/hex2bcd.v.v\n lib/hex2bcd.v.sv\n obj_dir/lib/hex2bcd.v\n obj_dir/lib/hex2bcd.v.v\n obj_dir/lib/hex2bcd.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test009.multi-segment-driver.v:8: Cannot find include file: lib/segmented_display_driver.v\n`include "lib/segmented_display_driver.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 6,758 | module | module mytop (
input clock,
output [5:1] LED,
inout [7:0] J1,
inout [7:0] J2,
inout [7:0] J3
);
wire reset = 0;
wire [35:0] bcd;
wire [23:0] data = 24'd00112233;
if (1) begin
wire [7:0] segment;
assign { J3[3], J1[2], J2[0], J3[0], J3[2], J3[5], J1[1], J1[7] } = segment;
assign J3[1] = 1;
wire [3:0] anode;
assign J3[4] = anode[0];
assign J1[4] = anode[1];
assign J1[3] = anode[2];
assign J1[0] = anode[3];
segmented_display_driver #(.NUMBER_OF_SEGMENTS(8), .NUMBER_OF_NYBBLES(4)) my_instance_name (.clock(clock), .data(bcd[15:0]), .dp(4'h0), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode());
hex2bcd #(.INPUT_SIZE_IN_NYBBLES(4)) h2binst ( .clock(clock), .reset(reset), .hex_in(data[15:0]), .bcd_out(bcd[23:0]), .sync() );
assign J3[7] = 0;
assign J3[6] = 0;
assign J2[7] = 0;
assign J2[6] = 0;
assign J2[5] = 0;
assign J2[4] = 0;
assign J2[3] = 0;
assign J2[2] = 0;
assign J2[1] = 0;
assign J1[6] = 0;
assign J1[5] = 0;
end else if (0) begin
wire [15:0] segment;
assign { J1[3], J1[4], J1[4], J3[3], J1[0], J1[1], J2[7], J2[0], J3[0], J3[1], J3[2], J3[2], J3[4], J3[5], J1[2], J2[3], J2[1], J2[4] } = segment;
assign J1[5] = 1;
assign J2[6] = anode[0];
assign J1[6] = anode[0];
wire [1:0] anode;
segmented_display_driver #(.number_of_segments(16), .number_of_nybbles(2)) my_instance_name (.clock(clock), .data(bcd[7:0]), .dp(2'h0), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode());
hex2bcd #(.input_size_in_nybbles(4)) h2binst ( .clock(clock), .reset(reset), .hex_in(data), .bcd_out(bcd), .sync() );
end else begin
wire [7:0] segment;
assign { J1[4], J1[1], J3[4], J3[5], J1[2], J1[5], J1[3], J3[2] } = segment;
wire [7:0] anode;
assign { J2[7], J2[4], J2[5], J2[6], J3[6], J3[7], J3[3], J3[1] } = anode;
segmented_display_driver #(.number_of_segments(8), .number_of_nybbles(8)) my_segmented_display_driver (.clock(clock), .data(bcd[31:0]), .dp(8'b00010000), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode(signal_output));
assign J2[2] = 0;
assign J2[1] = 0;
assign J1[7] = 0;
assign J1[6] = 0;
hex2bcd #(.input_size_in_nybbles(6)) h2binst ( .clock(clock), .reset(reset), .hex_in(data), .bcd_out(bcd), .sync() );
wire signal_output;
assign J1[0] = signal_output;
end
assign LED = 0;
reg [40:0] raw_counter = 0;
reg [40:0] alternate_counter = 0;
wire [15:0] counter_1000Hz = alternate_counter[26:12];
wire [15:0] counter_10Hz = alternate_counter[34:19];
wire [15:0] counter_1Hz = alternate_counter[37:22];
reg [2:0] clock_token = 0;
always @(posedge clock) begin
if (raw_counter[40:10]==0) begin
clock_token <= 3'b001;
end else begin
clock_token <= { clock_token[1:0], clock_token[2] };
end
if (clock_token == 3'b001) begin
alternate_counter++;
end
raw_counter++;
end
endmodule | module mytop (
input clock,
output [5:1] LED,
inout [7:0] J1,
inout [7:0] J2,
inout [7:0] J3
); |
wire reset = 0;
wire [35:0] bcd;
wire [23:0] data = 24'd00112233;
if (1) begin
wire [7:0] segment;
assign { J3[3], J1[2], J2[0], J3[0], J3[2], J3[5], J1[1], J1[7] } = segment;
assign J3[1] = 1;
wire [3:0] anode;
assign J3[4] = anode[0];
assign J1[4] = anode[1];
assign J1[3] = anode[2];
assign J1[0] = anode[3];
segmented_display_driver #(.NUMBER_OF_SEGMENTS(8), .NUMBER_OF_NYBBLES(4)) my_instance_name (.clock(clock), .data(bcd[15:0]), .dp(4'h0), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode());
hex2bcd #(.INPUT_SIZE_IN_NYBBLES(4)) h2binst ( .clock(clock), .reset(reset), .hex_in(data[15:0]), .bcd_out(bcd[23:0]), .sync() );
assign J3[7] = 0;
assign J3[6] = 0;
assign J2[7] = 0;
assign J2[6] = 0;
assign J2[5] = 0;
assign J2[4] = 0;
assign J2[3] = 0;
assign J2[2] = 0;
assign J2[1] = 0;
assign J1[6] = 0;
assign J1[5] = 0;
end else if (0) begin
wire [15:0] segment;
assign { J1[3], J1[4], J1[4], J3[3], J1[0], J1[1], J2[7], J2[0], J3[0], J3[1], J3[2], J3[2], J3[4], J3[5], J1[2], J2[3], J2[1], J2[4] } = segment;
assign J1[5] = 1;
assign J2[6] = anode[0];
assign J1[6] = anode[0];
wire [1:0] anode;
segmented_display_driver #(.number_of_segments(16), .number_of_nybbles(2)) my_instance_name (.clock(clock), .data(bcd[7:0]), .dp(2'h0), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode());
hex2bcd #(.input_size_in_nybbles(4)) h2binst ( .clock(clock), .reset(reset), .hex_in(data), .bcd_out(bcd), .sync() );
end else begin
wire [7:0] segment;
assign { J1[4], J1[1], J3[4], J3[5], J1[2], J1[5], J1[3], J3[2] } = segment;
wire [7:0] anode;
assign { J2[7], J2[4], J2[5], J2[6], J3[6], J3[7], J3[3], J3[1] } = anode;
segmented_display_driver #(.number_of_segments(8), .number_of_nybbles(8)) my_segmented_display_driver (.clock(clock), .data(bcd[31:0]), .dp(8'b00010000), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode(signal_output));
assign J2[2] = 0;
assign J2[1] = 0;
assign J1[7] = 0;
assign J1[6] = 0;
hex2bcd #(.input_size_in_nybbles(6)) h2binst ( .clock(clock), .reset(reset), .hex_in(data), .bcd_out(bcd), .sync() );
wire signal_output;
assign J1[0] = signal_output;
end
assign LED = 0;
reg [40:0] raw_counter = 0;
reg [40:0] alternate_counter = 0;
wire [15:0] counter_1000Hz = alternate_counter[26:12];
wire [15:0] counter_10Hz = alternate_counter[34:19];
wire [15:0] counter_1Hz = alternate_counter[37:22];
reg [2:0] clock_token = 0;
always @(posedge clock) begin
if (raw_counter[40:10]==0) begin
clock_token <= 3'b001;
end else begin
clock_token <= { clock_token[1:0], clock_token[2] };
end
if (clock_token == 3'b001) begin
alternate_counter++;
end
raw_counter++;
end
endmodule | 2 |
5,905 | data/full_repos/permissive/115035459/verilog/src/mza-test009.multi-segment-driver.v | 115,035,459 | mza-test009.multi-segment-driver.v | v | 129 | 236 | [] | [] | [] | null | line:31: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test009.multi-segment-driver.v:7: Cannot find include file: lib/hex2bcd.v\n`include "lib/hex2bcd.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v.sv\n lib/hex2bcd.v\n lib/hex2bcd.v.v\n lib/hex2bcd.v.sv\n obj_dir/lib/hex2bcd.v\n obj_dir/lib/hex2bcd.v.v\n obj_dir/lib/hex2bcd.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test009.multi-segment-driver.v:8: Cannot find include file: lib/segmented_display_driver.v\n`include "lib/segmented_display_driver.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 6,758 | module | module top (
input CLK,
output LED1, LED2, LED3, LED4, LED5,
output J1_3, J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10,
output J2_1, J2_2, J2_3, J2_4, J2_7, J2_8, J2_9, J2_10,
output J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10,
output DCDn, DSRn, CTSn, TX, IR_TX, IR_SD,
input DTRn, RTSn, RX, IR_RX
);
wire [7:0] J1 = { J1_10, J1_9, J1_8, J1_7, J1_6, J1_5, J1_4, J1_3 };
wire [7:0] J2 = { J2_10, J2_9, J2_8, J2_7, J2_4, J2_3, J2_2, J2_1 };
wire [7:0] J3 = { J3_10, J3_9, J3_8, J3_7, J3_6, J3_5, J3_4, J3_3 };
wire [5:1] LED = { LED5, LED4, LED3, LED2, LED1 };
assign { DCDn, DSRn, CTSn } = 1;
assign { IR_TX, IR_SD } = 0;
assign TX = 0;
mytop mytop_instance (.clock(CLK), .LED(LED), .J1(J1), .J2(J2), .J3(J3));
endmodule | module top (
input CLK,
output LED1, LED2, LED3, LED4, LED5,
output J1_3, J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10,
output J2_1, J2_2, J2_3, J2_4, J2_7, J2_8, J2_9, J2_10,
output J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10,
output DCDn, DSRn, CTSn, TX, IR_TX, IR_SD,
input DTRn, RTSn, RX, IR_RX
); |
wire [7:0] J1 = { J1_10, J1_9, J1_8, J1_7, J1_6, J1_5, J1_4, J1_3 };
wire [7:0] J2 = { J2_10, J2_9, J2_8, J2_7, J2_4, J2_3, J2_2, J2_1 };
wire [7:0] J3 = { J3_10, J3_9, J3_8, J3_7, J3_6, J3_5, J3_4, J3_3 };
wire [5:1] LED = { LED5, LED4, LED3, LED2, LED1 };
assign { DCDn, DSRn, CTSn } = 1;
assign { IR_TX, IR_SD } = 0;
assign TX = 0;
mytop mytop_instance (.clock(CLK), .LED(LED), .J1(J1), .J2(J2), .J3(J3));
endmodule | 2 |
5,906 | data/full_repos/permissive/115035459/verilog/src/mza-test010.SB_PLL_CORE.easypll.v | 115,035,459 | mza-test010.SB_PLL_CORE.easypll.v | v | 51 | 206 | [] | [] | [] | null | line:106: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test010.SB_PLL_CORE.easypll.v:5: Cannot find include file: lib/easypll.v\n`include "lib/easypll.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/easypll.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/easypll.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/easypll.v.sv\n lib/easypll.v\n lib/easypll.v.v\n lib/easypll.v.sv\n obj_dir/lib/easypll.v\n obj_dir/lib/easypll.v.v\n obj_dir/lib/easypll.v.sv\n%Error: Exiting due to 1 error(s)\n' | 6,759 | module | module mypll (
input clock,
output fast_clock,
output pll_is_locked,
output divided_clock,
output reg [31:0] counter = 0
);
assign divided_clock = counter[15];
easypll my_96MHz_pll_instance (.clock_input(clock), .reset_active_low(1), .global_clock_output(fast_clock), .pll_is_locked(pll_is_locked));
always @(posedge fast_clock) begin
counter++;
end
endmodule | module mypll (
input clock,
output fast_clock,
output pll_is_locked,
output divided_clock,
output reg [31:0] counter = 0
); |
assign divided_clock = counter[15];
easypll my_96MHz_pll_instance (.clock_input(clock), .reset_active_low(1), .global_clock_output(fast_clock), .pll_is_locked(pll_is_locked));
always @(posedge fast_clock) begin
counter++;
end
endmodule | 2 |
5,907 | data/full_repos/permissive/115035459/verilog/src/mza-test010.SB_PLL_CORE.easypll.v | 115,035,459 | mza-test010.SB_PLL_CORE.easypll.v | v | 51 | 206 | [] | [] | [] | null | line:106: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test010.SB_PLL_CORE.easypll.v:5: Cannot find include file: lib/easypll.v\n`include "lib/easypll.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/easypll.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/easypll.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/easypll.v.sv\n lib/easypll.v\n lib/easypll.v.v\n lib/easypll.v.sv\n obj_dir/lib/easypll.v\n obj_dir/lib/easypll.v.v\n obj_dir/lib/easypll.v.sv\n%Error: Exiting due to 1 error(s)\n' | 6,759 | module | module top (
input CLK,
output LED1, LED2, LED3, LED4, LED5,
output J1_3, J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10,
output J2_1, J2_2, J2_3, J2_4, J2_7, J2_8, J2_9, J2_10,
output J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10,
output DCDn, DSRn, CTSn, TX, IR_TX, IR_SD,
input DTRn, RTSn, RX, IR_RX
);
wire [7:0] J1 = { J1_10, J1_9, J1_8, J1_7, J1_6, J1_5, J1_4, J1_3 };
wire [7:0] J2 = { J2_10, J2_9, J2_8, J2_7, J2_4, J2_3, J2_2, J2_1 };
wire [7:0] J3 = { J3_10, J3_9, J3_8, J3_7, J3_6, J3_5, J3_4, J3_3 };
wire [5:1] LED = { LED5, LED4, LED3, LED2, LED1 };
assign { DCDn, DSRn, CTSn, TX, IR_TX, IR_SD } = 0;
wire [31:0] counter;
assign J3 = counter[23:16];
assign J2 = counter[15:8];
assign J1 = counter[7:0];
assign LED[3] = counter[24];
assign LED[4] = counter[25];
mypll mypll_instance (.clock(CLK), .fast_clock(LED[1]), .pll_is_locked(LED[5]), .divided_clock(LED[2]), .counter(counter));
endmodule | module top (
input CLK,
output LED1, LED2, LED3, LED4, LED5,
output J1_3, J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10,
output J2_1, J2_2, J2_3, J2_4, J2_7, J2_8, J2_9, J2_10,
output J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10,
output DCDn, DSRn, CTSn, TX, IR_TX, IR_SD,
input DTRn, RTSn, RX, IR_RX
); |
wire [7:0] J1 = { J1_10, J1_9, J1_8, J1_7, J1_6, J1_5, J1_4, J1_3 };
wire [7:0] J2 = { J2_10, J2_9, J2_8, J2_7, J2_4, J2_3, J2_2, J2_1 };
wire [7:0] J3 = { J3_10, J3_9, J3_8, J3_7, J3_6, J3_5, J3_4, J3_3 };
wire [5:1] LED = { LED5, LED4, LED3, LED2, LED1 };
assign { DCDn, DSRn, CTSn, TX, IR_TX, IR_SD } = 0;
wire [31:0] counter;
assign J3 = counter[23:16];
assign J2 = counter[15:8];
assign J1 = counter[7:0];
assign LED[3] = counter[24];
assign LED[4] = counter[25];
mypll mypll_instance (.clock(CLK), .fast_clock(LED[1]), .pll_is_locked(LED[5]), .divided_clock(LED[2]), .counter(counter));
endmodule | 2 |
5,922 | data/full_repos/permissive/115035459/verilog/src/mza-test022.frequency-counter.uart.v | 115,035,459 | mza-test022.frequency-counter.uart.v | v | 207 | 252 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test022.frequency-counter.uart.v:8: Cannot find include file: lib/hex2bcd.v\n`include "lib/hex2bcd.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v.sv\n lib/hex2bcd.v\n lib/hex2bcd.v.v\n lib/hex2bcd.v.sv\n obj_dir/lib/hex2bcd.v\n obj_dir/lib/hex2bcd.v.v\n obj_dir/lib/hex2bcd.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test022.frequency-counter.uart.v:9: Cannot find include file: lib/segmented_display_driver.v\n`include "lib/segmented_display_driver.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test022.frequency-counter.uart.v:10: Cannot find include file: lib/frequency_counter.v\n`include "lib/frequency_counter.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 6,771 | module | module mytop (
input clock,
output [5:1] LED,
inout [7:0] J1,
inout [7:0] J2,
inout [7:0] J3,
input RX,
output TX
);
reg [31:0] counter = 0;
wire [31:0] result;
reg [31:0] result2 = 32'h87654321;
reg [23:0] value2 = 24'd12345678;
wire [31:0] bcd2;
reg [31:0] buffered_bcd2 = 32'h88888888;
wire external_reference_clock;
wire raw_external_clock_to_measure;
wire mirror_of_raw_external_clock_to_measure;
reg external_clock_to_measure = 0;
wire reference_clock;
wire signal_output;
assign signal_output = clock;
assign J2[1] = signal_output;
assign J2[2] = signal_output;
assign external_reference_clock = J1[6];
assign raw_external_clock_to_measure = J1[7];
assign reference_clock = external_reference_clock;
assign J1[0] = signal_output;
assign J3[0] = J1[7];
localparam N = 1;
wire frequency_counter_sync;
frequency_counter #(.FREQUENCY_OF_REFERENCE_CLOCK(25000000), .LOG2_OF_DIVIDE_RATIO(25), .N(N)) fc (.reference_clock(reference_clock), .unknown_clock(raw_external_clock_to_measure), .frequency_of_unknown_clock(result), .valid(frequency_counter_sync));
wire [7:0] segment;
assign { J1[4], J1[1], J3[4], J3[5], J1[2], J1[5], J1[3], J3[2] } = segment;
wire [7:0] anode;
assign { J2[7], J2[4], J2[5], J2[6], J3[6], J3[7], J3[3], J3[1] } = anode;
wire [7:0] dp = (N==1) ? 8'b01000000 : (N==10) ? 8'b00100000 : 8'b00010000;
wire segmented_display_driver_sync;
segmented_display_driver #(.NUMBER_OF_SEGMENTS(8), .NUMBER_OF_NYBBLES(8)) my_segmented_display_driver (.clock(clock), .data(buffered_bcd2), .dp(dp), .cathode(segment), .anode(anode), .sync_anode(segmented_display_driver_sync), .sync_cathode());
wire hex2bcd_sync;
assign LED[5] = 0;
assign LED[4] = signal_output;
assign LED[3] = segmented_display_driver_sync;
assign LED[2] = hex2bcd_sync;
assign LED[1] = frequency_counter_sync;
localparam uart_line_pickoff = 22;
localparam slow_clock_pickoff = 19;
reg reset = 1;
wire uart_resetb;
assign uart_resetb = ~reset;
always @(posedge clock) begin
counter <= counter + 1'b1;
if (reset) begin
if (counter[10]) begin
reset <= 0;
end
value2 <= 24'd12345678;
result2 <= 32'h87654321;
buffered_bcd2 <= 32'h88888888;
end
if (counter[slow_clock_pickoff:0]==0) begin
buffered_bcd2 <= bcd2;
end else if (counter[slow_clock_pickoff:0]==1) begin
value2 <= result2[23:0];
end else if (counter[slow_clock_pickoff:0]==2) begin
result2 <= result;
end
end
hex2bcd #(.INPUT_SIZE_IN_NYBBLES(6)) h2binst2 ( .clock(clock), .reset(~uart_resetb), .hex_in(value2), .bcd_out(bcd2), .sync(hex2bcd_sync) );
assign TX = 0;
endmodule | module mytop (
input clock,
output [5:1] LED,
inout [7:0] J1,
inout [7:0] J2,
inout [7:0] J3,
input RX,
output TX
); |
reg [31:0] counter = 0;
wire [31:0] result;
reg [31:0] result2 = 32'h87654321;
reg [23:0] value2 = 24'd12345678;
wire [31:0] bcd2;
reg [31:0] buffered_bcd2 = 32'h88888888;
wire external_reference_clock;
wire raw_external_clock_to_measure;
wire mirror_of_raw_external_clock_to_measure;
reg external_clock_to_measure = 0;
wire reference_clock;
wire signal_output;
assign signal_output = clock;
assign J2[1] = signal_output;
assign J2[2] = signal_output;
assign external_reference_clock = J1[6];
assign raw_external_clock_to_measure = J1[7];
assign reference_clock = external_reference_clock;
assign J1[0] = signal_output;
assign J3[0] = J1[7];
localparam N = 1;
wire frequency_counter_sync;
frequency_counter #(.FREQUENCY_OF_REFERENCE_CLOCK(25000000), .LOG2_OF_DIVIDE_RATIO(25), .N(N)) fc (.reference_clock(reference_clock), .unknown_clock(raw_external_clock_to_measure), .frequency_of_unknown_clock(result), .valid(frequency_counter_sync));
wire [7:0] segment;
assign { J1[4], J1[1], J3[4], J3[5], J1[2], J1[5], J1[3], J3[2] } = segment;
wire [7:0] anode;
assign { J2[7], J2[4], J2[5], J2[6], J3[6], J3[7], J3[3], J3[1] } = anode;
wire [7:0] dp = (N==1) ? 8'b01000000 : (N==10) ? 8'b00100000 : 8'b00010000;
wire segmented_display_driver_sync;
segmented_display_driver #(.NUMBER_OF_SEGMENTS(8), .NUMBER_OF_NYBBLES(8)) my_segmented_display_driver (.clock(clock), .data(buffered_bcd2), .dp(dp), .cathode(segment), .anode(anode), .sync_anode(segmented_display_driver_sync), .sync_cathode());
wire hex2bcd_sync;
assign LED[5] = 0;
assign LED[4] = signal_output;
assign LED[3] = segmented_display_driver_sync;
assign LED[2] = hex2bcd_sync;
assign LED[1] = frequency_counter_sync;
localparam uart_line_pickoff = 22;
localparam slow_clock_pickoff = 19;
reg reset = 1;
wire uart_resetb;
assign uart_resetb = ~reset;
always @(posedge clock) begin
counter <= counter + 1'b1;
if (reset) begin
if (counter[10]) begin
reset <= 0;
end
value2 <= 24'd12345678;
result2 <= 32'h87654321;
buffered_bcd2 <= 32'h88888888;
end
if (counter[slow_clock_pickoff:0]==0) begin
buffered_bcd2 <= bcd2;
end else if (counter[slow_clock_pickoff:0]==1) begin
value2 <= result2[23:0];
end else if (counter[slow_clock_pickoff:0]==2) begin
result2 <= result;
end
end
hex2bcd #(.INPUT_SIZE_IN_NYBBLES(6)) h2binst2 ( .clock(clock), .reset(~uart_resetb), .hex_in(value2), .bcd_out(bcd2), .sync(hex2bcd_sync) );
assign TX = 0;
endmodule | 2 |
5,923 | data/full_repos/permissive/115035459/verilog/src/mza-test022.frequency-counter.uart.v | 115,035,459 | mza-test022.frequency-counter.uart.v | v | 207 | 252 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test022.frequency-counter.uart.v:8: Cannot find include file: lib/hex2bcd.v\n`include "lib/hex2bcd.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v.sv\n lib/hex2bcd.v\n lib/hex2bcd.v.v\n lib/hex2bcd.v.sv\n obj_dir/lib/hex2bcd.v\n obj_dir/lib/hex2bcd.v.v\n obj_dir/lib/hex2bcd.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test022.frequency-counter.uart.v:9: Cannot find include file: lib/segmented_display_driver.v\n`include "lib/segmented_display_driver.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test022.frequency-counter.uart.v:10: Cannot find include file: lib/frequency_counter.v\n`include "lib/frequency_counter.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 6,771 | module | module top (
input CLK,
output LED1, LED2, LED3, LED4, LED5,
output J1_3, J1_4, J1_5, J1_6, J1_7, J1_8,
output J2_2, J2_3, J2_7, J2_8, J2_9, J2_10,
output J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10,
input J2_4, J2_1, J1_9, J1_10,
output DCDn, DSRn, CTSn, TX, IR_TX, IR_SD,
input DTRn, RTSn, RX, IR_RX
);
wire [7:0] J1 = { J1_10, J1_9, J1_8, J1_7, J1_6, J1_5, J1_4, J1_3 };
wire [7:0] J2 = { J2_10, J2_9, J2_8, J2_7, J2_4, J2_3, J2_2, J2_1 };
wire [7:0] J3 = { J3_10, J3_9, J3_8, J3_7, J3_6, J3_5, J3_4, J3_3 };
wire [5:1] LED = { LED5, LED4, LED3, LED2, LED1 };
assign { DCDn, DSRn, CTSn } = 1;
assign { IR_TX, IR_SD } = 0;
mytop mytop_instance (.clock(CLK), .LED(LED), .J1(J1), .J2(J2), .J3(J3), .TX(TX), .RX(RX));
endmodule | module top (
input CLK,
output LED1, LED2, LED3, LED4, LED5,
output J1_3, J1_4, J1_5, J1_6, J1_7, J1_8,
output J2_2, J2_3, J2_7, J2_8, J2_9, J2_10,
output J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10,
input J2_4, J2_1, J1_9, J1_10,
output DCDn, DSRn, CTSn, TX, IR_TX, IR_SD,
input DTRn, RTSn, RX, IR_RX
); |
wire [7:0] J1 = { J1_10, J1_9, J1_8, J1_7, J1_6, J1_5, J1_4, J1_3 };
wire [7:0] J2 = { J2_10, J2_9, J2_8, J2_7, J2_4, J2_3, J2_2, J2_1 };
wire [7:0] J3 = { J3_10, J3_9, J3_8, J3_7, J3_6, J3_5, J3_4, J3_3 };
wire [5:1] LED = { LED5, LED4, LED3, LED2, LED1 };
assign { DCDn, DSRn, CTSn } = 1;
assign { IR_TX, IR_SD } = 0;
mytop mytop_instance (.clock(CLK), .LED(LED), .J1(J1), .J2(J2), .J3(J3), .TX(TX), .RX(RX));
endmodule | 2 |
5,924 | data/full_repos/permissive/115035459/verilog/src/mza-test023.serdes-pll.althea.revA.v | 115,035,459 | mza-test023.serdes-pll.althea.revA.v | v | 146 | 230 | [] | [] | [] | null | line:179: before: "," | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test023.serdes-pll.althea.revA.v:10: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/serdes_pll.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/serdes_pll.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/serdes_pll.v.sv\n lib/serdes_pll.v\n lib/serdes_pll.v.v\n lib/serdes_pll.v.sv\n obj_dir/lib/serdes_pll.v\n obj_dir/lib/serdes_pll.v.v\n obj_dir/lib/serdes_pll.v.sv\n%Error: Exiting due to 1 error(s)\n' | 6,772 | module | module mza_test023_serdes_pll_althea (
input clock_p,
input clock_n,
output ttl_trig_output,
input self_triggered_mode_switch,
input lvds_trig_input_p,
input lvds_trig_input_n,
output led_0,
output led_1,
output led_2,
output led_3,
output led_4,
output led_5,
output led_6,
output led_7
);
localparam WIDTH = 8;
reg reset1 = 1;
reg reset2 = 1;
wire clock;
reg [31:0] counter = 0;
reg sync;
wire other_clock;
IBUFGDS coolcool (.I(clock_p), .IB(clock_n), .O(other_clock));
wire IOCLK0;
wire IOCE;
wire cascade_do;
wire cascade_to;
wire cascade_di;
wire cascade_ti;
reg [WIDTH-1:0] word;
localparam pickoff = 24;
wire [7:0] led_byte;
assign { led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0 } = led_byte;
assign led_byte = word;
OSERDES2 #(.DATA_RATE_OQ("SDR"), .DATA_RATE_OT("SDR"), .DATA_WIDTH(WIDTH),
.OUTPUT_MODE("SINGLE_ENDED"), .SERDES_MODE("MASTER"))
osirus_primary
(.OQ(ttl_trig_output), .TQ(), .CLK0(IOCLK0), .CLK1(1'b0), .CLKDIV(clock),
.D1(word[3]), .D2(word[2]), .D3(word[1]), .D4(word[0]),
.IOCE(IOCE), .OCE(1'b1), .RST(reset1), .TRAIN(1'b0),
.SHIFTIN1(1'b1), .SHIFTIN2(1'b1), .SHIFTIN3(cascade_do), .SHIFTIN4(cascade_to),
.SHIFTOUT1(cascade_di), .SHIFTOUT2(cascade_ti), .SHIFTOUT3(), .SHIFTOUT4(),
.TCE(1'b1), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0));
OSERDES2 #(.DATA_RATE_OQ("SDR"), .DATA_RATE_OT("SDR"), .DATA_WIDTH(WIDTH),
.OUTPUT_MODE("SINGLE_ENDED"), .SERDES_MODE("SLAVE"))
osirus_secondary
(.OQ(), .TQ(), .CLK0(IOCLK0), .CLK1(1'b0), .CLKDIV(clock),
.D1(word[7]), .D2(word[6]), .D3(word[5]), .D4(word[4]),
.IOCE(IOCE), .OCE(1'b1), .RST(reset1), .TRAIN(1'b0),
.SHIFTIN1(cascade_di), .SHIFTIN2(cascade_ti), .SHIFTIN3(1'b1), .SHIFTIN4(1'b1),
.SHIFTOUT1(), .SHIFTOUT2(), .SHIFTOUT3(cascade_do), .SHIFTOUT4(cascade_to),
.TCE(1'b1), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0));
reg [12:0] reset1_counter = 0;
always @(posedge other_clock) begin
if (reset1) begin
if (reset1_counter[10]) begin
reset1 <= 0;
end
end
reset1_counter <= reset1_counter + 1;
end
wire trigger_input;
IBUFDS angel (.I(lvds_trig_input_p), .IB(lvds_trig_input_n), .O(trigger_input));
reg [1:0] token;
reg [2:0] trigger_stream;
localparam first = 8'b11110000;
localparam second = 8'b10000001;
localparam third = 8'b10001000;
localparam forth = 8'b10101010;
always @(posedge clock) begin
if (reset2) begin
token <= 2'b00;
trigger_stream <= 0;
if (counter[10]) begin
reset2 <= 0;
end
end
word <= 8'b00000000;
if (self_triggered_mode_switch) begin
if (counter[pickoff:0]==0) begin
if (counter[pickoff+2:pickoff+1]==2'b00) begin
sync <= 1;
word <= first;
end else if (counter[pickoff+2:pickoff+1]==2'b01) begin
sync <= 0;
word <= second;
end else if (counter[pickoff+2:pickoff+1]==2'b10) begin
word <= third;
end else if (counter[pickoff+2:pickoff+1]==2'b11) begin
word <= forth;
end
end
end else if (trigger_stream==3'b001) begin
if (token==2'b00) begin
sync <= 1;
word <= first;
token <= 2'b01;
end else if (token==2'b01) begin
sync <= 0;
word <= second;
token <= 2'b10;
end else if (token==2'b10) begin
word <= third;
token <= 2'b11;
end else begin
word <= forth;
token <= 2'b00;
end
end
trigger_stream <= { trigger_stream[1:0], trigger_input };
counter <= counter + 1;
end
oserdes_pll #(.BIT_DEPTH(WIDTH), .CLKIN_PERIOD(20.0), .PLLD(2), .PLLX(40)) difficult_pll (
.reset(reset1), .clock_in(other_clock), .word_clock_out(clock),
.serializer_clock_out(IOCLK0), .serializer_strobe_out(IOCE), .locked()
);
endmodule | module mza_test023_serdes_pll_althea (
input clock_p,
input clock_n,
output ttl_trig_output,
input self_triggered_mode_switch,
input lvds_trig_input_p,
input lvds_trig_input_n,
output led_0,
output led_1,
output led_2,
output led_3,
output led_4,
output led_5,
output led_6,
output led_7
); |
localparam WIDTH = 8;
reg reset1 = 1;
reg reset2 = 1;
wire clock;
reg [31:0] counter = 0;
reg sync;
wire other_clock;
IBUFGDS coolcool (.I(clock_p), .IB(clock_n), .O(other_clock));
wire IOCLK0;
wire IOCE;
wire cascade_do;
wire cascade_to;
wire cascade_di;
wire cascade_ti;
reg [WIDTH-1:0] word;
localparam pickoff = 24;
wire [7:0] led_byte;
assign { led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0 } = led_byte;
assign led_byte = word;
OSERDES2 #(.DATA_RATE_OQ("SDR"), .DATA_RATE_OT("SDR"), .DATA_WIDTH(WIDTH),
.OUTPUT_MODE("SINGLE_ENDED"), .SERDES_MODE("MASTER"))
osirus_primary
(.OQ(ttl_trig_output), .TQ(), .CLK0(IOCLK0), .CLK1(1'b0), .CLKDIV(clock),
.D1(word[3]), .D2(word[2]), .D3(word[1]), .D4(word[0]),
.IOCE(IOCE), .OCE(1'b1), .RST(reset1), .TRAIN(1'b0),
.SHIFTIN1(1'b1), .SHIFTIN2(1'b1), .SHIFTIN3(cascade_do), .SHIFTIN4(cascade_to),
.SHIFTOUT1(cascade_di), .SHIFTOUT2(cascade_ti), .SHIFTOUT3(), .SHIFTOUT4(),
.TCE(1'b1), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0));
OSERDES2 #(.DATA_RATE_OQ("SDR"), .DATA_RATE_OT("SDR"), .DATA_WIDTH(WIDTH),
.OUTPUT_MODE("SINGLE_ENDED"), .SERDES_MODE("SLAVE"))
osirus_secondary
(.OQ(), .TQ(), .CLK0(IOCLK0), .CLK1(1'b0), .CLKDIV(clock),
.D1(word[7]), .D2(word[6]), .D3(word[5]), .D4(word[4]),
.IOCE(IOCE), .OCE(1'b1), .RST(reset1), .TRAIN(1'b0),
.SHIFTIN1(cascade_di), .SHIFTIN2(cascade_ti), .SHIFTIN3(1'b1), .SHIFTIN4(1'b1),
.SHIFTOUT1(), .SHIFTOUT2(), .SHIFTOUT3(cascade_do), .SHIFTOUT4(cascade_to),
.TCE(1'b1), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0));
reg [12:0] reset1_counter = 0;
always @(posedge other_clock) begin
if (reset1) begin
if (reset1_counter[10]) begin
reset1 <= 0;
end
end
reset1_counter <= reset1_counter + 1;
end
wire trigger_input;
IBUFDS angel (.I(lvds_trig_input_p), .IB(lvds_trig_input_n), .O(trigger_input));
reg [1:0] token;
reg [2:0] trigger_stream;
localparam first = 8'b11110000;
localparam second = 8'b10000001;
localparam third = 8'b10001000;
localparam forth = 8'b10101010;
always @(posedge clock) begin
if (reset2) begin
token <= 2'b00;
trigger_stream <= 0;
if (counter[10]) begin
reset2 <= 0;
end
end
word <= 8'b00000000;
if (self_triggered_mode_switch) begin
if (counter[pickoff:0]==0) begin
if (counter[pickoff+2:pickoff+1]==2'b00) begin
sync <= 1;
word <= first;
end else if (counter[pickoff+2:pickoff+1]==2'b01) begin
sync <= 0;
word <= second;
end else if (counter[pickoff+2:pickoff+1]==2'b10) begin
word <= third;
end else if (counter[pickoff+2:pickoff+1]==2'b11) begin
word <= forth;
end
end
end else if (trigger_stream==3'b001) begin
if (token==2'b00) begin
sync <= 1;
word <= first;
token <= 2'b01;
end else if (token==2'b01) begin
sync <= 0;
word <= second;
token <= 2'b10;
end else if (token==2'b10) begin
word <= third;
token <= 2'b11;
end else begin
word <= forth;
token <= 2'b00;
end
end
trigger_stream <= { trigger_stream[1:0], trigger_input };
counter <= counter + 1;
end
oserdes_pll #(.BIT_DEPTH(WIDTH), .CLKIN_PERIOD(20.0), .PLLD(2), .PLLX(40)) difficult_pll (
.reset(reset1), .clock_in(other_clock), .word_clock_out(clock),
.serializer_clock_out(IOCLK0), .serializer_strobe_out(IOCE), .locked()
);
endmodule | 2 |
5,929 | data/full_repos/permissive/115035459/verilog/src/mza-test027.pll_509divider.althea.revA.v | 115,035,459 | mza-test027.pll_509divider.althea.revA.v | v | 53 | 145 | [] | [] | [] | [(9, 51)] | null | null | 1: b"%Error: data/full_repos/permissive/115035459/verilog/src/mza-test027.pll_509divider.althea.revA.v:40: Cannot find file containing module: 'pll'\n pll pll_instance (.CLK_IN1(clock509), .CLK_OUT1(clock127), .RESET(reset), .LOCKED(led_0));\n ^~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/pll\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/pll.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test027.pll_509divider.althea.revA.v:42: Cannot find file containing module: 'ODDR2'\n ODDR2 doughnut (.C0(clock127), .C1(~clock127), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test027.pll_509divider.althea.revA.v:43: Cannot find file containing module: 'OBUFDS'\n OBUFDS supercool (.I(clock127oddr), .O(clock_p), .OB(clock_n));\n ^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 6,776 | module | module mza_test027_pll_509divider_althea (
output clock_p,
output clock_n,
input lemo,
output led_0,
output led_1,
output led_2,
output led_3,
output led_4,
output led_5,
output led_6,
output led_7
);
wire clock509;
assign clock509 = lemo;
reg reset = 1;
reg [12:0] reset_counter = 0;
always @(posedge clock509) begin
if (reset) begin
if (reset_counter[10]) begin
reset <= 0;
end
end
reset_counter <= reset_counter + 1;
end
wire clock127;
pll pll_instance (.CLK_IN1(clock509), .CLK_OUT1(clock127), .RESET(reset), .LOCKED(led_0));
wire clock127oddr;
ODDR2 doughnut (.C0(clock127), .C1(~clock127), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr));
OBUFDS supercool (.I(clock127oddr), .O(clock_p), .OB(clock_n));
assign led_7 = reset;
assign led_6 = 0;
assign led_5 = 0;
assign led_4 = 0;
assign led_3 = 0;
assign led_2 = 0;
assign led_1 = 0;
endmodule | module mza_test027_pll_509divider_althea (
output clock_p,
output clock_n,
input lemo,
output led_0,
output led_1,
output led_2,
output led_3,
output led_4,
output led_5,
output led_6,
output led_7
); |
wire clock509;
assign clock509 = lemo;
reg reset = 1;
reg [12:0] reset_counter = 0;
always @(posedge clock509) begin
if (reset) begin
if (reset_counter[10]) begin
reset <= 0;
end
end
reset_counter <= reset_counter + 1;
end
wire clock127;
pll pll_instance (.CLK_IN1(clock509), .CLK_OUT1(clock127), .RESET(reset), .LOCKED(led_0));
wire clock127oddr;
ODDR2 doughnut (.C0(clock127), .C1(~clock127), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr));
OBUFDS supercool (.I(clock127oddr), .O(clock_p), .OB(clock_n));
assign led_7 = reset;
assign led_6 = 0;
assign led_5 = 0;
assign led_4 = 0;
assign led_3 = 0;
assign led_2 = 0;
assign led_1 = 0;
endmodule | 2 |
5,930 | data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v | 115,035,459 | mza-test028.pll_509divider_and_revo_encoder.althea.revA.v | v | 226 | 289 | [] | [] | [] | [(9, 101), (103, 181), (183, 224)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:158: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:160: Unsupported: Ignoring delay on this delayed statement.\n #5000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:162: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:164: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:166: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:168: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:170: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:127: Cell has missing pin: \'local_clock509_in_p\'\n mza_test028_pll_509divider_and_revo_encoder_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:127: Cell has missing pin: \'local_clock509_in_n\'\n mza_test028_pll_509divider_and_revo_encoder_althea uut (\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:183: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mything_tb\'\nmodule mything_tb;\n ^~~~~~~~~~\n : ... Top module \'mza_test028_pll_509divider_and_revo_encoder_althea_top\'\nmodule mza_test028_pll_509divider_and_revo_encoder_althea_top (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:36: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS remote_input_clock_instance (.I(remote_clock509_in_p), .IB(remote_clock509_in_n), .O(remote_clock509));\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.sv\n IBUFGDS\n IBUFGDS.v\n IBUFGDS.sv\n obj_dir/IBUFGDS\n obj_dir/IBUFGDS.v\n obj_dir/IBUFGDS.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:37: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS local_input_clock_instance (.I(local_clock509_in_p), .IB(local_clock509_in_n), .O(local_clock509));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:42: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS trigger_input_instance (.I(remote_revo_in_p), .IB(remote_revo_in_n), .O(rawtrg));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:61: Cannot find file containing module: \'simplepll_BASE\'\n simplepll_BASE #(.OVERALL_DIVIDE(2), .MULTIPLY(4), .DIVIDE1(8), .DIVIDE2(4), .PERIOD(1.965), .COMPENSATION("INTERNAL")) mypll (.clockin(clock509), .reset(reset), .clock1out(rawclock127), .clock1out180(rawclock127b), .clock2out(rawclock254), .clock2out180(rawclock254b), .locked(locked));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:64: Cannot find file containing module: \'BUFG\'\n BUFG mybufg1 (.I(rawclock127), .O(clock127));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:65: Cannot find file containing module: \'BUFG\'\n BUFG mybufg2 (.I(rawclock127b), .O(clock127b));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:68: Cannot find file containing module: \'BUFG\'\n BUFG mybufg3 (.I(rawclock254), .O(clock254));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:69: Cannot find file containing module: \'BUFG\'\n BUFG mybufg4 (.I(rawclock254b), .O(clock254b));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:84: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut1 (.C0(clock127), .C1(clock127b), .CE(1\'b1), .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr1));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:85: Cannot find file containing module: \'OBUFDS\'\n OBUFDS supercool (.I(clock127oddr1), .O(clock127_out_p), .OB(clock127_out_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:87: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut2 (.C0(clock127), .C1(clock127b), .CE(~trg), .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr2));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:88: Cannot find file containing module: \'OBUFDS\'\n OBUFDS grouch2 (.I(clock127oddr2), .O(trg_out_p), .OB(trg_out_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:98: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut3 (.C0(clock127), .C1(clock127b), .CE(1\'b1), .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr3));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:99: Cannot find file containing module: \'OBUFDS\'\n OBUFDS outa (.I(clock127oddr3), .O(outa_p), .OB(outa_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:100: Cannot find file containing module: \'OBUFDS\'\n OBUFDS out1 (.I(trg), .O(out1_p), .OB(out1_n));\n ^~~~~~\n%Error: Exiting due to 15 error(s), 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,777 | module | module mza_test028_pll_509divider_and_revo_encoder_althea (
input local_clock509_in_p,
input local_clock509_in_n,
input remote_clock509_in_p,
input remote_clock509_in_n,
input remote_revo_in_p,
input remote_revo_in_n,
output clock127_out_p,
output clock127_out_n,
output trg_out_p,
output trg_out_n,
output out1_p,
output out1_n,
output outa_p,
output outa_n,
output led_0,
output led_1,
output led_2,
output led_3,
output led_4,
output led_5,
output led_6,
output led_7
);
wire remote_clock509;
wire local_clock509;
wire clock509;
IBUFGDS remote_input_clock_instance (.I(remote_clock509_in_p), .IB(remote_clock509_in_n), .O(remote_clock509));
IBUFGDS local_input_clock_instance (.I(local_clock509_in_p), .IB(local_clock509_in_n), .O(local_clock509));
assign clock509 = remote_clock509;
reg reset = 1;
reg [12:0] reset_counter = 0;
wire rawtrg;
IBUFGDS trigger_input_instance (.I(remote_revo_in_p), .IB(remote_revo_in_n), .O(rawtrg));
parameter TRGSTREAM_WIDTH = 16;
parameter TRG_MAX_DURATION = 8;
reg [TRGSTREAM_WIDTH-1:0] trgstream = 0;
reg [TRGSTREAM_WIDTH-TRG_MAX_DURATION-1:0] upper;
reg [TRG_MAX_DURATION-1:0] lower;
always @(posedge clock509) begin
if (reset) begin
if (reset_counter[10]) begin
reset <= 0;
end
reset_counter <= reset_counter + 1'b1;
end
end
wire rawclock127;
wire rawclock127b;
wire rawclock254;
wire rawclock254b;
wire locked;
simplepll_BASE #(.OVERALL_DIVIDE(2), .MULTIPLY(4), .DIVIDE1(8), .DIVIDE2(4), .PERIOD(1.965), .COMPENSATION("INTERNAL")) mypll (.clockin(clock509), .reset(reset), .clock1out(rawclock127), .clock1out180(rawclock127b), .clock2out(rawclock254), .clock2out180(rawclock254b), .locked(locked));
wire clock127;
wire clock127b;
BUFG mybufg1 (.I(rawclock127), .O(clock127));
BUFG mybufg2 (.I(rawclock127b), .O(clock127b));
wire clock254;
wire clock254b;
BUFG mybufg3 (.I(rawclock254), .O(clock254));
BUFG mybufg4 (.I(rawclock254b), .O(clock254b));
reg trg = 0;
always @(posedge clock254) begin
trgstream <= { trgstream[TRGSTREAM_WIDTH-2:0], rawtrg };
trg <= 0;
if (upper==0 & lower!=0) begin
trg <= 1;
end
upper <= trgstream[TRGSTREAM_WIDTH-1:TRG_MAX_DURATION];
lower <= trgstream[TRG_MAX_DURATION-1:0];
end
wire clock127oddr1;
ODDR2 doughnut1 (.C0(clock127), .C1(clock127b), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr1));
OBUFDS supercool (.I(clock127oddr1), .O(clock127_out_p), .OB(clock127_out_n));
wire clock127oddr2;
ODDR2 doughnut2 (.C0(clock127), .C1(clock127b), .CE(~trg), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr2));
OBUFDS grouch2 (.I(clock127oddr2), .O(trg_out_p), .OB(trg_out_n));
assign led_7 = reset;
assign led_6 = 0;
assign led_5 = 0;
assign led_4 = trg;
assign led_3 = 0;
assign led_2 = reset_counter[12];
assign led_1 = 0;
assign led_0 = locked;
wire clock127oddr3;
ODDR2 doughnut3 (.C0(clock127), .C1(clock127b), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr3));
OBUFDS outa (.I(clock127oddr3), .O(outa_p), .OB(outa_n));
OBUFDS out1 (.I(trg), .O(out1_p), .OB(out1_n));
endmodule | module mza_test028_pll_509divider_and_revo_encoder_althea (
input local_clock509_in_p,
input local_clock509_in_n,
input remote_clock509_in_p,
input remote_clock509_in_n,
input remote_revo_in_p,
input remote_revo_in_n,
output clock127_out_p,
output clock127_out_n,
output trg_out_p,
output trg_out_n,
output out1_p,
output out1_n,
output outa_p,
output outa_n,
output led_0,
output led_1,
output led_2,
output led_3,
output led_4,
output led_5,
output led_6,
output led_7
); |
wire remote_clock509;
wire local_clock509;
wire clock509;
IBUFGDS remote_input_clock_instance (.I(remote_clock509_in_p), .IB(remote_clock509_in_n), .O(remote_clock509));
IBUFGDS local_input_clock_instance (.I(local_clock509_in_p), .IB(local_clock509_in_n), .O(local_clock509));
assign clock509 = remote_clock509;
reg reset = 1;
reg [12:0] reset_counter = 0;
wire rawtrg;
IBUFGDS trigger_input_instance (.I(remote_revo_in_p), .IB(remote_revo_in_n), .O(rawtrg));
parameter TRGSTREAM_WIDTH = 16;
parameter TRG_MAX_DURATION = 8;
reg [TRGSTREAM_WIDTH-1:0] trgstream = 0;
reg [TRGSTREAM_WIDTH-TRG_MAX_DURATION-1:0] upper;
reg [TRG_MAX_DURATION-1:0] lower;
always @(posedge clock509) begin
if (reset) begin
if (reset_counter[10]) begin
reset <= 0;
end
reset_counter <= reset_counter + 1'b1;
end
end
wire rawclock127;
wire rawclock127b;
wire rawclock254;
wire rawclock254b;
wire locked;
simplepll_BASE #(.OVERALL_DIVIDE(2), .MULTIPLY(4), .DIVIDE1(8), .DIVIDE2(4), .PERIOD(1.965), .COMPENSATION("INTERNAL")) mypll (.clockin(clock509), .reset(reset), .clock1out(rawclock127), .clock1out180(rawclock127b), .clock2out(rawclock254), .clock2out180(rawclock254b), .locked(locked));
wire clock127;
wire clock127b;
BUFG mybufg1 (.I(rawclock127), .O(clock127));
BUFG mybufg2 (.I(rawclock127b), .O(clock127b));
wire clock254;
wire clock254b;
BUFG mybufg3 (.I(rawclock254), .O(clock254));
BUFG mybufg4 (.I(rawclock254b), .O(clock254b));
reg trg = 0;
always @(posedge clock254) begin
trgstream <= { trgstream[TRGSTREAM_WIDTH-2:0], rawtrg };
trg <= 0;
if (upper==0 & lower!=0) begin
trg <= 1;
end
upper <= trgstream[TRGSTREAM_WIDTH-1:TRG_MAX_DURATION];
lower <= trgstream[TRG_MAX_DURATION-1:0];
end
wire clock127oddr1;
ODDR2 doughnut1 (.C0(clock127), .C1(clock127b), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr1));
OBUFDS supercool (.I(clock127oddr1), .O(clock127_out_p), .OB(clock127_out_n));
wire clock127oddr2;
ODDR2 doughnut2 (.C0(clock127), .C1(clock127b), .CE(~trg), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr2));
OBUFDS grouch2 (.I(clock127oddr2), .O(trg_out_p), .OB(trg_out_n));
assign led_7 = reset;
assign led_6 = 0;
assign led_5 = 0;
assign led_4 = trg;
assign led_3 = 0;
assign led_2 = reset_counter[12];
assign led_1 = 0;
assign led_0 = locked;
wire clock127oddr3;
ODDR2 doughnut3 (.C0(clock127), .C1(clock127b), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr3));
OBUFDS outa (.I(clock127oddr3), .O(outa_p), .OB(outa_n));
OBUFDS out1 (.I(trg), .O(out1_p), .OB(out1_n));
endmodule | 2 |
5,931 | data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v | 115,035,459 | mza-test028.pll_509divider_and_revo_encoder.althea.revA.v | v | 226 | 289 | [] | [] | [] | [(9, 101), (103, 181), (183, 224)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:158: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:160: Unsupported: Ignoring delay on this delayed statement.\n #5000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:162: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:164: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:166: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:168: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:170: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:127: Cell has missing pin: \'local_clock509_in_p\'\n mza_test028_pll_509divider_and_revo_encoder_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:127: Cell has missing pin: \'local_clock509_in_n\'\n mza_test028_pll_509divider_and_revo_encoder_althea uut (\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:183: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mything_tb\'\nmodule mything_tb;\n ^~~~~~~~~~\n : ... Top module \'mza_test028_pll_509divider_and_revo_encoder_althea_top\'\nmodule mza_test028_pll_509divider_and_revo_encoder_althea_top (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:36: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS remote_input_clock_instance (.I(remote_clock509_in_p), .IB(remote_clock509_in_n), .O(remote_clock509));\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.sv\n IBUFGDS\n IBUFGDS.v\n IBUFGDS.sv\n obj_dir/IBUFGDS\n obj_dir/IBUFGDS.v\n obj_dir/IBUFGDS.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:37: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS local_input_clock_instance (.I(local_clock509_in_p), .IB(local_clock509_in_n), .O(local_clock509));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:42: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS trigger_input_instance (.I(remote_revo_in_p), .IB(remote_revo_in_n), .O(rawtrg));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:61: Cannot find file containing module: \'simplepll_BASE\'\n simplepll_BASE #(.OVERALL_DIVIDE(2), .MULTIPLY(4), .DIVIDE1(8), .DIVIDE2(4), .PERIOD(1.965), .COMPENSATION("INTERNAL")) mypll (.clockin(clock509), .reset(reset), .clock1out(rawclock127), .clock1out180(rawclock127b), .clock2out(rawclock254), .clock2out180(rawclock254b), .locked(locked));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:64: Cannot find file containing module: \'BUFG\'\n BUFG mybufg1 (.I(rawclock127), .O(clock127));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:65: Cannot find file containing module: \'BUFG\'\n BUFG mybufg2 (.I(rawclock127b), .O(clock127b));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:68: Cannot find file containing module: \'BUFG\'\n BUFG mybufg3 (.I(rawclock254), .O(clock254));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:69: Cannot find file containing module: \'BUFG\'\n BUFG mybufg4 (.I(rawclock254b), .O(clock254b));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:84: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut1 (.C0(clock127), .C1(clock127b), .CE(1\'b1), .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr1));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:85: Cannot find file containing module: \'OBUFDS\'\n OBUFDS supercool (.I(clock127oddr1), .O(clock127_out_p), .OB(clock127_out_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:87: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut2 (.C0(clock127), .C1(clock127b), .CE(~trg), .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr2));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:88: Cannot find file containing module: \'OBUFDS\'\n OBUFDS grouch2 (.I(clock127oddr2), .O(trg_out_p), .OB(trg_out_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:98: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut3 (.C0(clock127), .C1(clock127b), .CE(1\'b1), .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr3));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:99: Cannot find file containing module: \'OBUFDS\'\n OBUFDS outa (.I(clock127oddr3), .O(outa_p), .OB(outa_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:100: Cannot find file containing module: \'OBUFDS\'\n OBUFDS out1 (.I(trg), .O(out1_p), .OB(out1_n));\n ^~~~~~\n%Error: Exiting due to 15 error(s), 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,777 | module | module mything_tb;
reg remote_clock509_in_p;
reg remote_clock509_in_n;
reg remote_revo_in_p;
reg remote_revo_in_n;
wire clock127_out_p;
wire clock127_out_n;
wire trg_out_p;
wire trg_out_n;
wire out1_p;
wire out1_n;
wire outa_p;
wire outa_n;
wire led_0;
wire led_1;
wire led_2;
wire led_3;
wire led_4;
wire led_5;
wire led_6;
wire led_7;
mza_test028_pll_509divider_and_revo_encoder_althea uut (
.remote_clock509_in_p(remote_clock509_in_p),
.remote_clock509_in_n(remote_clock509_in_n),
.remote_revo_in_p(remote_revo_in_p),
.remote_revo_in_n(remote_revo_in_n),
.clock127_out_p(clock127_out_p),
.clock127_out_n(clock127_out_n),
.trg_out_p(trg_out_p),
.trg_out_n(trg_out_n),
.out1_p(out1_p),
.out1_n(out1_n),
.outa_p(outa_p),
.outa_n(outa_n),
.led_0(led_0),
.led_1(led_1),
.led_2(led_2),
.led_3(led_3),
.led_4(led_4),
.led_5(led_5),
.led_6(led_6),
.led_7(led_7)
);
wire raw_recovered_reco;
assign raw_recovered_reco = clock127_out_p ^ trg_out_p;
reg recovered_revo;
initial begin
remote_clock509_in_p = 0; remote_clock509_in_n = 1;
remote_revo_in_p = 0; remote_revo_in_n = 1;
recovered_revo = 0;
#100;
#5000;
remote_revo_in_p = 1; remote_revo_in_n = 0;
#2;
remote_revo_in_p = 0; remote_revo_in_n = 1;
#50;
remote_revo_in_p = 1; remote_revo_in_n = 0;
#8;
remote_revo_in_p = 0; remote_revo_in_n = 1;
#50;
remote_revo_in_p = 1; remote_revo_in_n = 0;
#30;
remote_revo_in_p = 0; remote_revo_in_n = 1;
end
always begin
#1;
remote_clock509_in_p = ~ remote_clock509_in_p;
remote_clock509_in_n = ~ remote_clock509_in_n;
end
always @(negedge clock127_out_p) begin
recovered_revo <= raw_recovered_reco;
end
endmodule | module mything_tb; |
reg remote_clock509_in_p;
reg remote_clock509_in_n;
reg remote_revo_in_p;
reg remote_revo_in_n;
wire clock127_out_p;
wire clock127_out_n;
wire trg_out_p;
wire trg_out_n;
wire out1_p;
wire out1_n;
wire outa_p;
wire outa_n;
wire led_0;
wire led_1;
wire led_2;
wire led_3;
wire led_4;
wire led_5;
wire led_6;
wire led_7;
mza_test028_pll_509divider_and_revo_encoder_althea uut (
.remote_clock509_in_p(remote_clock509_in_p),
.remote_clock509_in_n(remote_clock509_in_n),
.remote_revo_in_p(remote_revo_in_p),
.remote_revo_in_n(remote_revo_in_n),
.clock127_out_p(clock127_out_p),
.clock127_out_n(clock127_out_n),
.trg_out_p(trg_out_p),
.trg_out_n(trg_out_n),
.out1_p(out1_p),
.out1_n(out1_n),
.outa_p(outa_p),
.outa_n(outa_n),
.led_0(led_0),
.led_1(led_1),
.led_2(led_2),
.led_3(led_3),
.led_4(led_4),
.led_5(led_5),
.led_6(led_6),
.led_7(led_7)
);
wire raw_recovered_reco;
assign raw_recovered_reco = clock127_out_p ^ trg_out_p;
reg recovered_revo;
initial begin
remote_clock509_in_p = 0; remote_clock509_in_n = 1;
remote_revo_in_p = 0; remote_revo_in_n = 1;
recovered_revo = 0;
#100;
#5000;
remote_revo_in_p = 1; remote_revo_in_n = 0;
#2;
remote_revo_in_p = 0; remote_revo_in_n = 1;
#50;
remote_revo_in_p = 1; remote_revo_in_n = 0;
#8;
remote_revo_in_p = 0; remote_revo_in_n = 1;
#50;
remote_revo_in_p = 1; remote_revo_in_n = 0;
#30;
remote_revo_in_p = 0; remote_revo_in_n = 1;
end
always begin
#1;
remote_clock509_in_p = ~ remote_clock509_in_p;
remote_clock509_in_n = ~ remote_clock509_in_n;
end
always @(negedge clock127_out_p) begin
recovered_revo <= raw_recovered_reco;
end
endmodule | 2 |
5,932 | data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v | 115,035,459 | mza-test028.pll_509divider_and_revo_encoder.althea.revA.v | v | 226 | 289 | [] | [] | [] | [(9, 101), (103, 181), (183, 224)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:158: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:160: Unsupported: Ignoring delay on this delayed statement.\n #5000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:162: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:164: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:166: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:168: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:170: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:174: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:127: Cell has missing pin: \'local_clock509_in_p\'\n mza_test028_pll_509divider_and_revo_encoder_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:127: Cell has missing pin: \'local_clock509_in_n\'\n mza_test028_pll_509divider_and_revo_encoder_althea uut (\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:183: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mything_tb\'\nmodule mything_tb;\n ^~~~~~~~~~\n : ... Top module \'mza_test028_pll_509divider_and_revo_encoder_althea_top\'\nmodule mza_test028_pll_509divider_and_revo_encoder_althea_top (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:36: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS remote_input_clock_instance (.I(remote_clock509_in_p), .IB(remote_clock509_in_n), .O(remote_clock509));\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.sv\n IBUFGDS\n IBUFGDS.v\n IBUFGDS.sv\n obj_dir/IBUFGDS\n obj_dir/IBUFGDS.v\n obj_dir/IBUFGDS.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:37: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS local_input_clock_instance (.I(local_clock509_in_p), .IB(local_clock509_in_n), .O(local_clock509));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:42: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS trigger_input_instance (.I(remote_revo_in_p), .IB(remote_revo_in_n), .O(rawtrg));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:61: Cannot find file containing module: \'simplepll_BASE\'\n simplepll_BASE #(.OVERALL_DIVIDE(2), .MULTIPLY(4), .DIVIDE1(8), .DIVIDE2(4), .PERIOD(1.965), .COMPENSATION("INTERNAL")) mypll (.clockin(clock509), .reset(reset), .clock1out(rawclock127), .clock1out180(rawclock127b), .clock2out(rawclock254), .clock2out180(rawclock254b), .locked(locked));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:64: Cannot find file containing module: \'BUFG\'\n BUFG mybufg1 (.I(rawclock127), .O(clock127));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:65: Cannot find file containing module: \'BUFG\'\n BUFG mybufg2 (.I(rawclock127b), .O(clock127b));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:68: Cannot find file containing module: \'BUFG\'\n BUFG mybufg3 (.I(rawclock254), .O(clock254));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:69: Cannot find file containing module: \'BUFG\'\n BUFG mybufg4 (.I(rawclock254b), .O(clock254b));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:84: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut1 (.C0(clock127), .C1(clock127b), .CE(1\'b1), .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr1));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:85: Cannot find file containing module: \'OBUFDS\'\n OBUFDS supercool (.I(clock127oddr1), .O(clock127_out_p), .OB(clock127_out_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:87: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut2 (.C0(clock127), .C1(clock127b), .CE(~trg), .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr2));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:88: Cannot find file containing module: \'OBUFDS\'\n OBUFDS grouch2 (.I(clock127oddr2), .O(trg_out_p), .OB(trg_out_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:98: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut3 (.C0(clock127), .C1(clock127b), .CE(1\'b1), .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr3));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:99: Cannot find file containing module: \'OBUFDS\'\n OBUFDS outa (.I(clock127oddr3), .O(outa_p), .OB(outa_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:100: Cannot find file containing module: \'OBUFDS\'\n OBUFDS out1 (.I(trg), .O(out1_p), .OB(out1_n));\n ^~~~~~\n%Error: Exiting due to 15 error(s), 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,777 | module | module mza_test028_pll_509divider_and_revo_encoder_althea_top (
output a_p, a_n,
output b_p, b_n,
output d_p, d_n,
output e_p, e_n,
input j_p, j_n,
input k_p, k_n,
input m_p, m_n,
output led_0,
output led_1,
output led_2,
output led_3,
output led_4,
output led_5,
output led_6,
output led_7
);
mza_test028_pll_509divider_and_revo_encoder_althea mything (
.local_clock509_in_p(j_p),
.local_clock509_in_n(j_n),
.remote_clock509_in_p(k_p),
.remote_clock509_in_n(k_n),
.remote_revo_in_p(m_p),
.remote_revo_in_n(m_n),
.clock127_out_p(a_p),
.clock127_out_n(a_n),
.trg_out_p(d_p),
.trg_out_n(d_n),
.out1_p(e_p),
.out1_n(e_n),
.outa_p(b_p),
.outa_n(b_n),
.led_0(led_0),
.led_1(led_1),
.led_2(led_2),
.led_3(led_3),
.led_4(led_4),
.led_5(led_5),
.led_6(led_6),
.led_7(led_7)
);
endmodule | module mza_test028_pll_509divider_and_revo_encoder_althea_top (
output a_p, a_n,
output b_p, b_n,
output d_p, d_n,
output e_p, e_n,
input j_p, j_n,
input k_p, k_n,
input m_p, m_n,
output led_0,
output led_1,
output led_2,
output led_3,
output led_4,
output led_5,
output led_6,
output led_7
); |
mza_test028_pll_509divider_and_revo_encoder_althea mything (
.local_clock509_in_p(j_p),
.local_clock509_in_n(j_n),
.remote_clock509_in_p(k_p),
.remote_clock509_in_n(k_n),
.remote_revo_in_p(m_p),
.remote_revo_in_n(m_n),
.clock127_out_p(a_p),
.clock127_out_n(a_n),
.trg_out_p(d_p),
.trg_out_n(d_n),
.out1_p(e_p),
.out1_n(e_n),
.outa_p(b_p),
.outa_n(b_n),
.led_0(led_0),
.led_1(led_1),
.led_2(led_2),
.led_3(led_3),
.led_4(led_4),
.led_5(led_5),
.led_6(led_6),
.led_7(led_7)
);
endmodule | 2 |
5,933 | data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v | 115,035,459 | mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v | v | 508 | 207 | [] | [] | [] | [(11, 72), (74, 129), (131, 168), (170, 359), (361, 470), (472, 506)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:434: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:436: Unsupported: Ignoring delay on this delayed statement.\n #5000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:438: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:440: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:442: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:444: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:446: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:450: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:452: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:456: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:458: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:462: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:464: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock50_in_p\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock50_in_n\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock509_in_p\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock509_in_n\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:361: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'ssynchronizer_90_270\'\nmodule ssynchronizer_90_270 #(\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mything_tb\'\nmodule mything_tb;\n ^~~~~~~~~~\n : ... Top module \'mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top\'\nmodule mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:494: Signal definition not found, creating implicitly: \'f_p\'\n : ... Suggested alternative: \'e_p\'\n .trg_out_p(f_p), .trg_out_n(f_n),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:494: Signal definition not found, creating implicitly: \'f_n\'\n : ... Suggested alternative: \'d_n\'\n .trg_out_p(f_p), .trg_out_n(f_n),\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:399: Pin not found: \'remote_clock50_in_p\'\n : ... Suggested alternative: \'remote_clock509_in_p\'\n .remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:399: Pin not found: \'remote_clock50_in_n\'\n : ... Suggested alternative: \'remote_clock509_in_n\'\n .remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),\n ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:409: Signal definition not found, creating implicitly: \'l_p\'\n .led_revo(l_p),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:410: Signal definition not found, creating implicitly: \'l_n\'\n : ... Suggested alternative: \'l_p\'\n .led_rfclock(l_n),\n ^~~\n%Error: Exiting due to 2 error(s), 22 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,778 | module | module ssynchronizer_90_270 #(
parameter WIDTH=1
) (
input clock1,
input clock2, clock1_90, clock1_270,
input reset,
input [WIDTH-1:0] in1,
output [WIDTH-1:0] out2
);
reg [WIDTH-1:0] intermediate_f1;
reg [WIDTH-1:0] intermediate_f2;
reg [WIDTH-1:0] intermediate_f3;
reg [WIDTH-1:0] intermediate_f4;
reg [WIDTH-1:0] intermediate_s1;
reg [WIDTH-1:0] intermediate_s2;
always @(posedge clock1) begin
if (reset) begin
intermediate_f1 <= 0;
end else begin
intermediate_f1 <= in1;
end
end
always @(posedge clock1_270) begin
if (reset) begin
intermediate_f2 <= 0;
end else begin
intermediate_f2 <= intermediate_f1;
end
end
always @(negedge clock1) begin
if (reset) begin
intermediate_f3 <= 0;
end else begin
intermediate_f3 <= intermediate_f2;
end
end
always @(posedge clock1_90) begin
if (reset) begin
intermediate_f4 <= 0;
end else begin
intermediate_f4 <= intermediate_f3;
end
end
always @(negedge clock2) begin
if (reset) begin
intermediate_s1 <= 0;
end else begin
intermediate_s1 <= intermediate_f4;
end
end
always @(posedge clock2) begin
if (reset) begin
intermediate_s2 <= 0;
end else begin
intermediate_s2 <= intermediate_s1;
end
end
assign out2 = intermediate_s2;
endmodule | module ssynchronizer_90_270 #(
parameter WIDTH=1
) (
input clock1,
input clock2, clock1_90, clock1_270,
input reset,
input [WIDTH-1:0] in1,
output [WIDTH-1:0] out2
); |
reg [WIDTH-1:0] intermediate_f1;
reg [WIDTH-1:0] intermediate_f2;
reg [WIDTH-1:0] intermediate_f3;
reg [WIDTH-1:0] intermediate_f4;
reg [WIDTH-1:0] intermediate_s1;
reg [WIDTH-1:0] intermediate_s2;
always @(posedge clock1) begin
if (reset) begin
intermediate_f1 <= 0;
end else begin
intermediate_f1 <= in1;
end
end
always @(posedge clock1_270) begin
if (reset) begin
intermediate_f2 <= 0;
end else begin
intermediate_f2 <= intermediate_f1;
end
end
always @(negedge clock1) begin
if (reset) begin
intermediate_f3 <= 0;
end else begin
intermediate_f3 <= intermediate_f2;
end
end
always @(posedge clock1_90) begin
if (reset) begin
intermediate_f4 <= 0;
end else begin
intermediate_f4 <= intermediate_f3;
end
end
always @(negedge clock2) begin
if (reset) begin
intermediate_s1 <= 0;
end else begin
intermediate_s1 <= intermediate_f4;
end
end
always @(posedge clock2) begin
if (reset) begin
intermediate_s2 <= 0;
end else begin
intermediate_s2 <= intermediate_s1;
end
end
assign out2 = intermediate_s2;
endmodule | 2 |
5,934 | data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v | 115,035,459 | mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v | v | 508 | 207 | [] | [] | [] | [(11, 72), (74, 129), (131, 168), (170, 359), (361, 470), (472, 506)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:434: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:436: Unsupported: Ignoring delay on this delayed statement.\n #5000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:438: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:440: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:442: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:444: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:446: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:450: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:452: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:456: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:458: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:462: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:464: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock50_in_p\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock50_in_n\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock509_in_p\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock509_in_n\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:361: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'ssynchronizer_90_270\'\nmodule ssynchronizer_90_270 #(\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mything_tb\'\nmodule mything_tb;\n ^~~~~~~~~~\n : ... Top module \'mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top\'\nmodule mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:494: Signal definition not found, creating implicitly: \'f_p\'\n : ... Suggested alternative: \'e_p\'\n .trg_out_p(f_p), .trg_out_n(f_n),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:494: Signal definition not found, creating implicitly: \'f_n\'\n : ... Suggested alternative: \'d_n\'\n .trg_out_p(f_p), .trg_out_n(f_n),\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:399: Pin not found: \'remote_clock50_in_p\'\n : ... Suggested alternative: \'remote_clock509_in_p\'\n .remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:399: Pin not found: \'remote_clock50_in_n\'\n : ... Suggested alternative: \'remote_clock509_in_n\'\n .remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),\n ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:409: Signal definition not found, creating implicitly: \'l_p\'\n .led_revo(l_p),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:410: Signal definition not found, creating implicitly: \'l_n\'\n : ... Suggested alternative: \'l_p\'\n .led_rfclock(l_n),\n ^~~\n%Error: Exiting due to 2 error(s), 22 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,778 | module | module ssynchronizer_pnppp #(
parameter WIDTH=1
) (
input clock1, clock2,
input reset,
input [WIDTH-1:0] in1,
output [WIDTH-1:0] out2
);
reg [WIDTH-1:0] intermediate_f1;
reg [WIDTH-1:0] intermediate_f2;
reg [WIDTH-1:0] intermediate_f3;
reg [WIDTH-1:0] intermediate_s1;
reg [WIDTH-1:0] intermediate_s2;
(* KEEP = "TRUE" *) wire [WIDTH-1:0] cdc;
always @(posedge clock1) begin
if (reset) begin
intermediate_f1 <= 0;
end else begin
intermediate_f1 <= in1;
end
end
always @(negedge clock1) begin
if (reset) begin
intermediate_f2 <= 0;
end else begin
intermediate_f2 <= intermediate_f1;
end
end
always @(negedge clock1) begin
if (reset) begin
intermediate_f3 <= 0;
end else begin
intermediate_f3 <= intermediate_f2;
end
end
assign cdc = intermediate_f3;
always @(posedge clock2) begin
if (reset) begin
intermediate_s1 <= 0;
end else begin
intermediate_s1 <= cdc;
end
end
always @(posedge clock2) begin
if (reset) begin
intermediate_s2 <= 0;
end else begin
intermediate_s2 <= intermediate_s1;
end
end
assign out2 = intermediate_s2;
endmodule | module ssynchronizer_pnppp #(
parameter WIDTH=1
) (
input clock1, clock2,
input reset,
input [WIDTH-1:0] in1,
output [WIDTH-1:0] out2
); |
reg [WIDTH-1:0] intermediate_f1;
reg [WIDTH-1:0] intermediate_f2;
reg [WIDTH-1:0] intermediate_f3;
reg [WIDTH-1:0] intermediate_s1;
reg [WIDTH-1:0] intermediate_s2;
(* KEEP = "TRUE" *) wire [WIDTH-1:0] cdc;
always @(posedge clock1) begin
if (reset) begin
intermediate_f1 <= 0;
end else begin
intermediate_f1 <= in1;
end
end
always @(negedge clock1) begin
if (reset) begin
intermediate_f2 <= 0;
end else begin
intermediate_f2 <= intermediate_f1;
end
end
always @(negedge clock1) begin
if (reset) begin
intermediate_f3 <= 0;
end else begin
intermediate_f3 <= intermediate_f2;
end
end
assign cdc = intermediate_f3;
always @(posedge clock2) begin
if (reset) begin
intermediate_s1 <= 0;
end else begin
intermediate_s1 <= cdc;
end
end
always @(posedge clock2) begin
if (reset) begin
intermediate_s2 <= 0;
end else begin
intermediate_s2 <= intermediate_s1;
end
end
assign out2 = intermediate_s2;
endmodule | 2 |
5,935 | data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v | 115,035,459 | mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v | v | 508 | 207 | [] | [] | [] | [(11, 72), (74, 129), (131, 168), (170, 359), (361, 470), (472, 506)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:434: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:436: Unsupported: Ignoring delay on this delayed statement.\n #5000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:438: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:440: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:442: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:444: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:446: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:450: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:452: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:456: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:458: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:462: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:464: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock50_in_p\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock50_in_n\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock509_in_p\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock509_in_n\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:361: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'ssynchronizer_90_270\'\nmodule ssynchronizer_90_270 #(\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mything_tb\'\nmodule mything_tb;\n ^~~~~~~~~~\n : ... Top module \'mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top\'\nmodule mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:494: Signal definition not found, creating implicitly: \'f_p\'\n : ... Suggested alternative: \'e_p\'\n .trg_out_p(f_p), .trg_out_n(f_n),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:494: Signal definition not found, creating implicitly: \'f_n\'\n : ... Suggested alternative: \'d_n\'\n .trg_out_p(f_p), .trg_out_n(f_n),\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:399: Pin not found: \'remote_clock50_in_p\'\n : ... Suggested alternative: \'remote_clock509_in_p\'\n .remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:399: Pin not found: \'remote_clock50_in_n\'\n : ... Suggested alternative: \'remote_clock509_in_n\'\n .remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),\n ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:409: Signal definition not found, creating implicitly: \'l_p\'\n .led_revo(l_p),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:410: Signal definition not found, creating implicitly: \'l_n\'\n : ... Suggested alternative: \'l_p\'\n .led_rfclock(l_n),\n ^~~\n%Error: Exiting due to 2 error(s), 22 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,778 | module | module asynchronizer (
input clock,
input reset,
input async_in,
output reg sync_out
);
reg intermediate_s1;
reg intermediate_s2;
reg intermediate_s3;
wire randy;
assign randy = reset | ((~async_in) & intermediate_s3);
always @(posedge async_in) begin
if (randy) begin
intermediate_s1 <= 0;
end else begin
intermediate_s1 <= 1;
end
end
always @(posedge clock) begin
if (randy) begin
intermediate_s2 <= 0;
end else begin
intermediate_s2 <= intermediate_s1;
end
end
always @(posedge clock) begin
if (reset) begin
intermediate_s3 <= 0;
sync_out <= 0;
end else begin
sync_out <= intermediate_s3;
intermediate_s3 <= intermediate_s2;
end
end
endmodule | module asynchronizer (
input clock,
input reset,
input async_in,
output reg sync_out
); |
reg intermediate_s1;
reg intermediate_s2;
reg intermediate_s3;
wire randy;
assign randy = reset | ((~async_in) & intermediate_s3);
always @(posedge async_in) begin
if (randy) begin
intermediate_s1 <= 0;
end else begin
intermediate_s1 <= 1;
end
end
always @(posedge clock) begin
if (randy) begin
intermediate_s2 <= 0;
end else begin
intermediate_s2 <= intermediate_s1;
end
end
always @(posedge clock) begin
if (reset) begin
intermediate_s3 <= 0;
sync_out <= 0;
end else begin
sync_out <= intermediate_s3;
intermediate_s3 <= intermediate_s2;
end
end
endmodule | 2 |
5,936 | data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v | 115,035,459 | mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v | v | 508 | 207 | [] | [] | [] | [(11, 72), (74, 129), (131, 168), (170, 359), (361, 470), (472, 506)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:434: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:436: Unsupported: Ignoring delay on this delayed statement.\n #5000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:438: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:440: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:442: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:444: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:446: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:450: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:452: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:456: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:458: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:462: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:464: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock50_in_p\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock50_in_n\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock509_in_p\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock509_in_n\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:361: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'ssynchronizer_90_270\'\nmodule ssynchronizer_90_270 #(\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mything_tb\'\nmodule mything_tb;\n ^~~~~~~~~~\n : ... Top module \'mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top\'\nmodule mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:494: Signal definition not found, creating implicitly: \'f_p\'\n : ... Suggested alternative: \'e_p\'\n .trg_out_p(f_p), .trg_out_n(f_n),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:494: Signal definition not found, creating implicitly: \'f_n\'\n : ... Suggested alternative: \'d_n\'\n .trg_out_p(f_p), .trg_out_n(f_n),\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:399: Pin not found: \'remote_clock50_in_p\'\n : ... Suggested alternative: \'remote_clock509_in_p\'\n .remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:399: Pin not found: \'remote_clock50_in_n\'\n : ... Suggested alternative: \'remote_clock509_in_n\'\n .remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),\n ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:409: Signal definition not found, creating implicitly: \'l_p\'\n .led_revo(l_p),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:410: Signal definition not found, creating implicitly: \'l_n\'\n : ... Suggested alternative: \'l_p\'\n .led_rfclock(l_n),\n ^~~\n%Error: Exiting due to 2 error(s), 22 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,778 | module | module mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea (
input local_clock50_in_p, input local_clock50_in_n,
input local_clock509_in_p, input local_clock509_in_n,
input remote_clock509_in_p, input remote_clock509_in_n,
input remote_revo_in_p, input remote_revo_in_n,
output clock127_out_p, output clock127_out_n,
output trg_out_p, output trg_out_n,
output out1_p, output out1_n,
output outa_p, output outa_n,
output rsv_p, output rsv_n,
input lemo,
input ack_p, input ack_n,
output reg led_revo,
output reg led_rfclock,
output driven_high,
input clock_select,
output led_0, output led_1, output led_2, output led_3, output led_4, output led_5, output led_6, output led_7
);
wire ack;
IBUFGDS ackbuf (.I(ack_p), .IB(ack_n), .O(ack));
wire remote_clock509;
wire local_clock509;
wire clock509;
IBUFGDS remote_input_clock509_instance (.I(remote_clock509_in_p), .IB(remote_clock509_in_n), .O(remote_clock509));
IBUFGDS local_input_clock509_instance (.I(local_clock509_in_p), .IB(local_clock509_in_n), .O(local_clock509));
assign driven_high = 1;
BUFGMUX #(.CLK_SEL_TYPE("ASYNC")) clock_selection_instance (.I0(remote_clock509), .I1(local_clock509), .S(clock_select), .O(clock509));
reg reset = 1;
reg [11:0] reset_counter = 0;
wire local_clock50;
IBUFGDS local_input_clock50_instance (.I(local_clock50_in_p), .IB(local_clock50_in_n), .O(local_clock50));
always @(posedge local_clock50) begin
if (reset) begin
led_revo <= 0;
led_rfclock <= 0;
end
if (reset_counter[10]) begin
reset <= 0;
end
reset_counter <= reset_counter + 1'b1;
end
wire rawclock127;
wire rawclock127b;
wire rawclock254;
wire rawclock254b;
wire rawclock509_1;
wire rawclock509_3;
wire locked1;
simplepll_BASE #(.OVERALL_DIVIDE(2), .MULTIPLY(4), .PERIOD(1.965), .COMPENSATION("INTERNAL"),
.DIVIDE0(8), .DIVIDE1(8), .DIVIDE2(4), .DIVIDE3(4), .DIVIDE4(2), .DIVIDE5(2),
.PHASE0(0.0), .PHASE1(180.0), .PHASE2(0.0), .PHASE3(180.0), .PHASE4(90.0), .PHASE5(270.0)
) mypll (.clockin(clock509), .reset(reset), .locked(locked1),
.clock0out(rawclock127), .clock1out(rawclock127b),
.clock2out(rawclock254), .clock3out(rawclock254b),
.clock4out(rawclock509_90), .clock5out(rawclock509_270)
);
wire clock127;
wire clock127b;
BUFG mybufg0 (.I(rawclock127), .O(clock127));
BUFG mybufg1 (.I(rawclock127b), .O(clock127b));
wire clock254;
wire clock254b;
BUFG mybufg2 (.I(rawclock254), .O(clock254));
BUFG mybufg3 (.I(rawclock254b), .O(clock254b));
wire clock254_90;
wire clock254_270;
BUFG mybufg4 (.I(rawclock254_90), .O(clock254_90));
BUFG mybufg5 (.I(rawclock254_270), .O(clock254_270));
reg [3:0] phase;
reg trg, trg_inv1, should_trg;
parameter TRGSTREAM_WIDTH = 8'd16;
parameter TRG_MAX_DURATION = 8'd8;
reg [TRGSTREAM_WIDTH-1:0] trgstream509;
wire [TRGSTREAM_WIDTH-1:0] trgstream254;
reg [TRGSTREAM_WIDTH-TRG_MAX_DURATION-1:0] upper;
reg [TRG_MAX_DURATION-1:0] lower;
reg u, l;
wire rawtrg, rawtrg2;
IBUFGDS trigger_input_instance (.I(remote_revo_in_p), .IB(remote_revo_in_n), .O(rawtrg));
always @(posedge clock509) begin
if (reset) begin
trgstream509 <= 0;
end else begin
trgstream509 <= { trgstream509[TRGSTREAM_WIDTH-2:0], rawtrg2 };
end
end
ssynchronizer_pnppp #(.WIDTH(TRGSTREAM_WIDTH)) ts_sync (.clock1(clock509), .clock2(clock254), .reset(reset), .in1(trgstream509), .out2(trgstream254));
asynchronizer rawtrg_sync (.clock(clock509), .reset(reset), .async_in(rawtrg), .sync_out(rawtrg2));
always @(posedge clock127) begin
if (reset) begin
phase <= 4'b0001;
trg <= 0;
trg_inv1 <= 1;
should_trg <= 0;
upper <= 0;
lower <= 0;
u <= 0;
l <= 0;
end else begin
if (phase == 4'b0001) begin
if (should_trg) begin
trg <= 1;
trg_inv1 <= 0;
end else begin
trg <= 0;
trg_inv1 <= 1;
end
upper <= trgstream254[TRGSTREAM_WIDTH-1:TRG_MAX_DURATION];
lower <= trgstream254[TRG_MAX_DURATION-1:0];
end else if (phase == 4'b0010) begin
u <= |upper;
l <= |lower;
should_trg <= 0;
end else if (phase == 4'b0100) begin
if (l) begin
should_trg <= 1;
end
end else begin
if (u) begin
should_trg <= 0;
end
end
phase <= { phase[2:0], phase[3] };
end
end
wire locked2;
assign led_7 = locked2;
assign led_6 = 0;
assign led_5 = reset;
assign led_4 = 0;
assign led_3 = clock_select;
assign led_2 = trg;
assign led_1 = 0;
assign led_0 = locked1;
wire data;
wire word_clock;
reg [7:0] word;
wire [7:0] word_null = 8'b11000000;
wire [7:0] word_trg = 8'b00111111;
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(3.93), .DIVIDE(2), .MULTIPLY(8)) mylei (.clock_in(clock254), .reset(reset), .word_clock_out(word_clock), .word_in(word), .D_out(data), .locked(locked2));
always @(posedge word_clock) begin
if (reset) begin
word <= word_null;
end else begin
if (trg) begin
word <= word_trg;
end else begin
word <= word_null;
end
end
end
OBUFDS rsv (.I(data), .O(rsv_p), .OB(rsv_n));
wire clock127_oddr1;
ODDR2 doughnut0 (.C0(clock127), .C1(clock127b), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(reset), .S(1'b0), .Q(clock127_oddr1));
OBUFDS supercool1 (.I(clock127_oddr1), .O(clock127_out_p), .OB(clock127_out_n));
OBUFDS outa (.I(rawtrg), .O(outa_p), .OB(outa_n));
wire clock127_encoded_trg_oddr1;
ODDR2 doughnut2 (.C0(clock127), .C1(clock127b), .CE(trg_inv1), .D0(1'b0), .D1(1'b1), .R(reset), .S(1'b0), .Q(clock127_encoded_trg_oddr1));
OBUFDS supercool2 (.I(clock127_encoded_trg_oddr1), .O(trg_out_p), .OB(trg_out_n));
OBUFDS out1 (.I(trg), .O(out1_p), .OB(out1_n));
endmodule | module mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea (
input local_clock50_in_p, input local_clock50_in_n,
input local_clock509_in_p, input local_clock509_in_n,
input remote_clock509_in_p, input remote_clock509_in_n,
input remote_revo_in_p, input remote_revo_in_n,
output clock127_out_p, output clock127_out_n,
output trg_out_p, output trg_out_n,
output out1_p, output out1_n,
output outa_p, output outa_n,
output rsv_p, output rsv_n,
input lemo,
input ack_p, input ack_n,
output reg led_revo,
output reg led_rfclock,
output driven_high,
input clock_select,
output led_0, output led_1, output led_2, output led_3, output led_4, output led_5, output led_6, output led_7
); |
wire ack;
IBUFGDS ackbuf (.I(ack_p), .IB(ack_n), .O(ack));
wire remote_clock509;
wire local_clock509;
wire clock509;
IBUFGDS remote_input_clock509_instance (.I(remote_clock509_in_p), .IB(remote_clock509_in_n), .O(remote_clock509));
IBUFGDS local_input_clock509_instance (.I(local_clock509_in_p), .IB(local_clock509_in_n), .O(local_clock509));
assign driven_high = 1;
BUFGMUX #(.CLK_SEL_TYPE("ASYNC")) clock_selection_instance (.I0(remote_clock509), .I1(local_clock509), .S(clock_select), .O(clock509));
reg reset = 1;
reg [11:0] reset_counter = 0;
wire local_clock50;
IBUFGDS local_input_clock50_instance (.I(local_clock50_in_p), .IB(local_clock50_in_n), .O(local_clock50));
always @(posedge local_clock50) begin
if (reset) begin
led_revo <= 0;
led_rfclock <= 0;
end
if (reset_counter[10]) begin
reset <= 0;
end
reset_counter <= reset_counter + 1'b1;
end
wire rawclock127;
wire rawclock127b;
wire rawclock254;
wire rawclock254b;
wire rawclock509_1;
wire rawclock509_3;
wire locked1;
simplepll_BASE #(.OVERALL_DIVIDE(2), .MULTIPLY(4), .PERIOD(1.965), .COMPENSATION("INTERNAL"),
.DIVIDE0(8), .DIVIDE1(8), .DIVIDE2(4), .DIVIDE3(4), .DIVIDE4(2), .DIVIDE5(2),
.PHASE0(0.0), .PHASE1(180.0), .PHASE2(0.0), .PHASE3(180.0), .PHASE4(90.0), .PHASE5(270.0)
) mypll (.clockin(clock509), .reset(reset), .locked(locked1),
.clock0out(rawclock127), .clock1out(rawclock127b),
.clock2out(rawclock254), .clock3out(rawclock254b),
.clock4out(rawclock509_90), .clock5out(rawclock509_270)
);
wire clock127;
wire clock127b;
BUFG mybufg0 (.I(rawclock127), .O(clock127));
BUFG mybufg1 (.I(rawclock127b), .O(clock127b));
wire clock254;
wire clock254b;
BUFG mybufg2 (.I(rawclock254), .O(clock254));
BUFG mybufg3 (.I(rawclock254b), .O(clock254b));
wire clock254_90;
wire clock254_270;
BUFG mybufg4 (.I(rawclock254_90), .O(clock254_90));
BUFG mybufg5 (.I(rawclock254_270), .O(clock254_270));
reg [3:0] phase;
reg trg, trg_inv1, should_trg;
parameter TRGSTREAM_WIDTH = 8'd16;
parameter TRG_MAX_DURATION = 8'd8;
reg [TRGSTREAM_WIDTH-1:0] trgstream509;
wire [TRGSTREAM_WIDTH-1:0] trgstream254;
reg [TRGSTREAM_WIDTH-TRG_MAX_DURATION-1:0] upper;
reg [TRG_MAX_DURATION-1:0] lower;
reg u, l;
wire rawtrg, rawtrg2;
IBUFGDS trigger_input_instance (.I(remote_revo_in_p), .IB(remote_revo_in_n), .O(rawtrg));
always @(posedge clock509) begin
if (reset) begin
trgstream509 <= 0;
end else begin
trgstream509 <= { trgstream509[TRGSTREAM_WIDTH-2:0], rawtrg2 };
end
end
ssynchronizer_pnppp #(.WIDTH(TRGSTREAM_WIDTH)) ts_sync (.clock1(clock509), .clock2(clock254), .reset(reset), .in1(trgstream509), .out2(trgstream254));
asynchronizer rawtrg_sync (.clock(clock509), .reset(reset), .async_in(rawtrg), .sync_out(rawtrg2));
always @(posedge clock127) begin
if (reset) begin
phase <= 4'b0001;
trg <= 0;
trg_inv1 <= 1;
should_trg <= 0;
upper <= 0;
lower <= 0;
u <= 0;
l <= 0;
end else begin
if (phase == 4'b0001) begin
if (should_trg) begin
trg <= 1;
trg_inv1 <= 0;
end else begin
trg <= 0;
trg_inv1 <= 1;
end
upper <= trgstream254[TRGSTREAM_WIDTH-1:TRG_MAX_DURATION];
lower <= trgstream254[TRG_MAX_DURATION-1:0];
end else if (phase == 4'b0010) begin
u <= |upper;
l <= |lower;
should_trg <= 0;
end else if (phase == 4'b0100) begin
if (l) begin
should_trg <= 1;
end
end else begin
if (u) begin
should_trg <= 0;
end
end
phase <= { phase[2:0], phase[3] };
end
end
wire locked2;
assign led_7 = locked2;
assign led_6 = 0;
assign led_5 = reset;
assign led_4 = 0;
assign led_3 = clock_select;
assign led_2 = trg;
assign led_1 = 0;
assign led_0 = locked1;
wire data;
wire word_clock;
reg [7:0] word;
wire [7:0] word_null = 8'b11000000;
wire [7:0] word_trg = 8'b00111111;
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(3.93), .DIVIDE(2), .MULTIPLY(8)) mylei (.clock_in(clock254), .reset(reset), .word_clock_out(word_clock), .word_in(word), .D_out(data), .locked(locked2));
always @(posedge word_clock) begin
if (reset) begin
word <= word_null;
end else begin
if (trg) begin
word <= word_trg;
end else begin
word <= word_null;
end
end
end
OBUFDS rsv (.I(data), .O(rsv_p), .OB(rsv_n));
wire clock127_oddr1;
ODDR2 doughnut0 (.C0(clock127), .C1(clock127b), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(reset), .S(1'b0), .Q(clock127_oddr1));
OBUFDS supercool1 (.I(clock127_oddr1), .O(clock127_out_p), .OB(clock127_out_n));
OBUFDS outa (.I(rawtrg), .O(outa_p), .OB(outa_n));
wire clock127_encoded_trg_oddr1;
ODDR2 doughnut2 (.C0(clock127), .C1(clock127b), .CE(trg_inv1), .D0(1'b0), .D1(1'b1), .R(reset), .S(1'b0), .Q(clock127_encoded_trg_oddr1));
OBUFDS supercool2 (.I(clock127_encoded_trg_oddr1), .O(trg_out_p), .OB(trg_out_n));
OBUFDS out1 (.I(trg), .O(out1_p), .OB(out1_n));
endmodule | 2 |
5,937 | data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v | 115,035,459 | mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v | v | 508 | 207 | [] | [] | [] | [(11, 72), (74, 129), (131, 168), (170, 359), (361, 470), (472, 506)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:434: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:436: Unsupported: Ignoring delay on this delayed statement.\n #5000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:438: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:440: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:442: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:444: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:446: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:450: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:452: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:456: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:458: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:462: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:464: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock50_in_p\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock50_in_n\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock509_in_p\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock509_in_n\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:361: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'ssynchronizer_90_270\'\nmodule ssynchronizer_90_270 #(\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mything_tb\'\nmodule mything_tb;\n ^~~~~~~~~~\n : ... Top module \'mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top\'\nmodule mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:494: Signal definition not found, creating implicitly: \'f_p\'\n : ... Suggested alternative: \'e_p\'\n .trg_out_p(f_p), .trg_out_n(f_n),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:494: Signal definition not found, creating implicitly: \'f_n\'\n : ... Suggested alternative: \'d_n\'\n .trg_out_p(f_p), .trg_out_n(f_n),\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:399: Pin not found: \'remote_clock50_in_p\'\n : ... Suggested alternative: \'remote_clock509_in_p\'\n .remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:399: Pin not found: \'remote_clock50_in_n\'\n : ... Suggested alternative: \'remote_clock509_in_n\'\n .remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),\n ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:409: Signal definition not found, creating implicitly: \'l_p\'\n .led_revo(l_p),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:410: Signal definition not found, creating implicitly: \'l_n\'\n : ... Suggested alternative: \'l_p\'\n .led_rfclock(l_n),\n ^~~\n%Error: Exiting due to 2 error(s), 22 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,778 | module | module mything_tb;
reg remote_clock50_in_p;
reg remote_clock50_in_n;
reg remote_clock509_in_p;
reg remote_clock509_in_n;
reg local_clock509_in_p;
reg local_clock509_in_n;
reg remote_revo_in_p;
reg remote_revo_in_n;
wire clock127_out_p;
wire clock127_out_n;
wire trg_out_p;
wire trg_out_n;
wire out1_p;
wire out1_n;
wire outa_p;
wire outa_n;
wire rsv_p;
wire rsv_n;
reg lemo;
reg ack_p;
reg ack_n;
wire led_revo;
wire led_rfclock;
wire driven_high;
reg clock_select = 0;
wire led_0;
wire led_1;
wire led_2;
wire led_3;
wire led_4;
wire led_5;
wire led_6;
wire led_7;
mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (
.remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),
.remote_clock509_in_p(remote_clock509_in_p), .remote_clock509_in_n(remote_clock509_in_n),
.remote_revo_in_p(remote_revo_in_p), .remote_revo_in_n(remote_revo_in_n),
.clock127_out_p(clock127_out_p), .clock127_out_n(clock127_out_n),
.trg_out_p(trg_out_p), .trg_out_n(trg_out_n),
.rsv_p(rsv_p), .rsv_n(rsv_n),
.ack_p(ack_p), .ack_n(ack_n),
.out1_p(out1_p), .out1_n(out1_n),
.outa_p(outa_p), .outa_n(outa_n),
.lemo(lemo),
.led_revo(l_p),
.led_rfclock(l_n),
.clock_select(clock_select),
.driven_high(driven_high),
.led_0(led_0),
.led_1(led_1),
.led_2(led_2),
.led_3(led_3),
.led_4(led_4),
.led_5(led_5),
.led_6(led_6),
.led_7(led_7)
);
wire raw_recovered_revo;
assign raw_recovered_revo = clock127_out_p ^ trg_out_p;
reg recovered_revo;
initial begin
remote_clock50_in_p <= 0; remote_clock50_in_n <= 1;
remote_clock509_in_p <= 0; remote_clock509_in_n <= 1;
local_clock509_in_p <= 0; local_clock509_in_n <= 1;
remote_revo_in_p <= 0; remote_revo_in_n <= 1;
recovered_revo <= 0; lemo <= 0; ack_p <= 0; ack_n <= 1;
clock_select <= 0;
#100;
#5000;
remote_revo_in_p = 1; remote_revo_in_n = 0;
#2;
remote_revo_in_p = 0; remote_revo_in_n = 1;
#50;
remote_revo_in_p = 1; remote_revo_in_n = 0;
#8;
remote_revo_in_p = 0; remote_revo_in_n = 1;
#50;
remote_revo_in_p = 1; remote_revo_in_n = 0;
#30;
remote_revo_in_p = 0; remote_revo_in_n = 1;
end
always begin
#1;
local_clock509_in_p <= ~local_clock509_in_p;
#1;
local_clock509_in_n <= ~local_clock509_in_n;
end
always begin
#1;
remote_clock509_in_p <= ~remote_clock509_in_p;
#1;
remote_clock509_in_n <= ~remote_clock509_in_n;
end
always begin
#10;
remote_clock50_in_p <= ~remote_clock50_in_p;
#10;
remote_clock50_in_n <= ~remote_clock50_in_n;
end
always @(negedge clock127_out_p) begin
recovered_revo <= raw_recovered_revo;
end
endmodule | module mything_tb; |
reg remote_clock50_in_p;
reg remote_clock50_in_n;
reg remote_clock509_in_p;
reg remote_clock509_in_n;
reg local_clock509_in_p;
reg local_clock509_in_n;
reg remote_revo_in_p;
reg remote_revo_in_n;
wire clock127_out_p;
wire clock127_out_n;
wire trg_out_p;
wire trg_out_n;
wire out1_p;
wire out1_n;
wire outa_p;
wire outa_n;
wire rsv_p;
wire rsv_n;
reg lemo;
reg ack_p;
reg ack_n;
wire led_revo;
wire led_rfclock;
wire driven_high;
reg clock_select = 0;
wire led_0;
wire led_1;
wire led_2;
wire led_3;
wire led_4;
wire led_5;
wire led_6;
wire led_7;
mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (
.remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),
.remote_clock509_in_p(remote_clock509_in_p), .remote_clock509_in_n(remote_clock509_in_n),
.remote_revo_in_p(remote_revo_in_p), .remote_revo_in_n(remote_revo_in_n),
.clock127_out_p(clock127_out_p), .clock127_out_n(clock127_out_n),
.trg_out_p(trg_out_p), .trg_out_n(trg_out_n),
.rsv_p(rsv_p), .rsv_n(rsv_n),
.ack_p(ack_p), .ack_n(ack_n),
.out1_p(out1_p), .out1_n(out1_n),
.outa_p(outa_p), .outa_n(outa_n),
.lemo(lemo),
.led_revo(l_p),
.led_rfclock(l_n),
.clock_select(clock_select),
.driven_high(driven_high),
.led_0(led_0),
.led_1(led_1),
.led_2(led_2),
.led_3(led_3),
.led_4(led_4),
.led_5(led_5),
.led_6(led_6),
.led_7(led_7)
);
wire raw_recovered_revo;
assign raw_recovered_revo = clock127_out_p ^ trg_out_p;
reg recovered_revo;
initial begin
remote_clock50_in_p <= 0; remote_clock50_in_n <= 1;
remote_clock509_in_p <= 0; remote_clock509_in_n <= 1;
local_clock509_in_p <= 0; local_clock509_in_n <= 1;
remote_revo_in_p <= 0; remote_revo_in_n <= 1;
recovered_revo <= 0; lemo <= 0; ack_p <= 0; ack_n <= 1;
clock_select <= 0;
#100;
#5000;
remote_revo_in_p = 1; remote_revo_in_n = 0;
#2;
remote_revo_in_p = 0; remote_revo_in_n = 1;
#50;
remote_revo_in_p = 1; remote_revo_in_n = 0;
#8;
remote_revo_in_p = 0; remote_revo_in_n = 1;
#50;
remote_revo_in_p = 1; remote_revo_in_n = 0;
#30;
remote_revo_in_p = 0; remote_revo_in_n = 1;
end
always begin
#1;
local_clock509_in_p <= ~local_clock509_in_p;
#1;
local_clock509_in_n <= ~local_clock509_in_n;
end
always begin
#1;
remote_clock509_in_p <= ~remote_clock509_in_p;
#1;
remote_clock509_in_n <= ~remote_clock509_in_n;
end
always begin
#10;
remote_clock50_in_p <= ~remote_clock50_in_p;
#10;
remote_clock50_in_n <= ~remote_clock50_in_n;
end
always @(negedge clock127_out_p) begin
recovered_revo <= raw_recovered_revo;
end
endmodule | 2 |
5,938 | data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v | 115,035,459 | mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v | v | 508 | 207 | [] | [] | [] | [(11, 72), (74, 129), (131, 168), (170, 359), (361, 470), (472, 506)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:434: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:436: Unsupported: Ignoring delay on this delayed statement.\n #5000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:438: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:440: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:442: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:444: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:446: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:450: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:452: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:456: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:458: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:462: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:464: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock50_in_p\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock50_in_n\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock509_in_p\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock509_in_n\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:361: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'ssynchronizer_90_270\'\nmodule ssynchronizer_90_270 #(\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mything_tb\'\nmodule mything_tb;\n ^~~~~~~~~~\n : ... Top module \'mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top\'\nmodule mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:494: Signal definition not found, creating implicitly: \'f_p\'\n : ... Suggested alternative: \'e_p\'\n .trg_out_p(f_p), .trg_out_n(f_n),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:494: Signal definition not found, creating implicitly: \'f_n\'\n : ... Suggested alternative: \'d_n\'\n .trg_out_p(f_p), .trg_out_n(f_n),\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:399: Pin not found: \'remote_clock50_in_p\'\n : ... Suggested alternative: \'remote_clock509_in_p\'\n .remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:399: Pin not found: \'remote_clock50_in_n\'\n : ... Suggested alternative: \'remote_clock509_in_n\'\n .remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),\n ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:409: Signal definition not found, creating implicitly: \'l_p\'\n .led_revo(l_p),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:410: Signal definition not found, creating implicitly: \'l_n\'\n : ... Suggested alternative: \'l_p\'\n .led_rfclock(l_n),\n ^~~\n%Error: Exiting due to 2 error(s), 22 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,778 | module | module mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top (
input clock50_p, clock50_n,
input a_p, a_n,
output b_p, b_n,
output c_p, c_n,
output d_p, d_n,
output e_p, e_n,
input h_p, h_n,
input j_p, j_n,
input k_p, k_n,
input lemo,
output l_p, l_n,
input g_n, output g_p,
output led_0, output led_1, output led_2, output led_3,
output led_4, output led_5, output led_6, output led_7
);
mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea mything (
.local_clock50_in_p(clock50_p), .local_clock50_in_n(clock50_n),
.local_clock509_in_p(j_p), .local_clock509_in_n(j_n),
.remote_clock509_in_p(k_p), .remote_clock509_in_n(k_n),
.remote_revo_in_p(h_p), .remote_revo_in_n(h_n),
.clock127_out_p(d_p), .clock127_out_n(d_n),
.trg_out_p(f_p), .trg_out_n(f_n),
.rsv_p(c_p), .rsv_n(c_n),
.ack_p(a_p), .ack_n(a_n),
.out1_p(e_p), .out1_n(e_n),
.outa_p(b_p), .outa_n(b_n),
.lemo(lemo),
.led_revo(l_p),
.led_rfclock(l_n),
.driven_high(g_p), .clock_select(g_n),
.led_0(led_0), .led_1(led_1), .led_2(led_2), .led_3(led_3),
.led_4(led_4), .led_5(led_5), .led_6(led_6), .led_7(led_7)
);
endmodule | module mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top (
input clock50_p, clock50_n,
input a_p, a_n,
output b_p, b_n,
output c_p, c_n,
output d_p, d_n,
output e_p, e_n,
input h_p, h_n,
input j_p, j_n,
input k_p, k_n,
input lemo,
output l_p, l_n,
input g_n, output g_p,
output led_0, output led_1, output led_2, output led_3,
output led_4, output led_5, output led_6, output led_7
); |
mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea mything (
.local_clock50_in_p(clock50_p), .local_clock50_in_n(clock50_n),
.local_clock509_in_p(j_p), .local_clock509_in_n(j_n),
.remote_clock509_in_p(k_p), .remote_clock509_in_n(k_n),
.remote_revo_in_p(h_p), .remote_revo_in_n(h_n),
.clock127_out_p(d_p), .clock127_out_n(d_n),
.trg_out_p(f_p), .trg_out_n(f_n),
.rsv_p(c_p), .rsv_n(c_n),
.ack_p(a_p), .ack_n(a_n),
.out1_p(e_p), .out1_n(e_n),
.outa_p(b_p), .outa_n(b_n),
.lemo(lemo),
.led_revo(l_p),
.led_rfclock(l_n),
.driven_high(g_p), .clock_select(g_n),
.led_0(led_0), .led_1(led_1), .led_2(led_2), .led_3(led_3),
.led_4(led_4), .led_5(led_5), .led_6(led_6), .led_7(led_7)
);
endmodule | 2 |
5,939 | data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v | 115,035,459 | mza-test031.clock509_and_revo_generator.althea.revA.v | v | 125 | 291 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v:7: Cannot find include file: lib/superkekb.v\n`include "lib/superkekb.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/superkekb.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/superkekb.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/superkekb.v.sv\n lib/superkekb.v\n lib/superkekb.v.v\n lib/superkekb.v.sv\n obj_dir/lib/superkekb.v\n obj_dir/lib/superkekb.v.v\n obj_dir/lib/superkekb.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v:8: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v:94: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v:98: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 6,779 | module | module mza_test031_clock509_and_revo_generator_althea #(
parameter PHASE = 45.0
) (
input local_clock50_in_p, local_clock50_in_n,
input local_clock509_in_p, local_clock509_in_n,
output clk78_p, clk78_n,
output trg36_p, trg36_n,
output clk_se,
output trg_se,
output lemo,
output led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
);
wire clock50;
wire clock509;
IBUFGDS local_input_clock50_instance (.I(local_clock50_in_p), .IB(local_clock50_in_n), .O(clock50));
IBUFGDS local_input_clock509_instance (.I(local_clock509_in_p), .IB(local_clock509_in_n), .O(clock509));
reg reset = 1;
reg superkekb_reset = 1;
reg [25:0] counter = 0;
always @(posedge clock50) begin
if (counter[9]) begin
reset <= 0;
end
if (counter[11]) begin
superkekb_reset <= 0;
end
counter <= counter + 1'b1;
end
wire [7:0] clock_word = 8'b10101010;
wire [7:0] revo_word;
wire oserdes_pll_locked1;
wire oserdes_pll_locked2;
wire revo;
assign led_7 = oserdes_pll_locked1;
assign led_6 = oserdes_pll_locked2;
assign led_5 = 0;
assign led_4 = revo;
assign led_3 = 0;
assign led_2 = reset;
assign led_1 = superkekb_reset;
assign led_0 = counter[25];
wire clock509_oddr;
wire revo_oddr;
wire word_clock2;
superkekb skb (.clock(word_clock2), .reset(superkekb_reset), .revo(revo), .revo_word(revo_word));
wire rawclock127;
BUFIO2 #(
.DIVIDE(4), .USE_DOUBLER("FALSE"), .I_INVERT("FALSE"), .DIVIDE_BYPASS("FALSE")
) sally (
.I(clock509), .DIVCLK(rawclock127), .IOCLK(), .SERDESSTROBE()
);
wire clock127;
BUFG peter (.I(rawclock127), .O(clock127));
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(7.86), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .MODE("WORD_CLOCK_IN"), .PHASE(0.0)) mylei1 (.clock_in(clock127), .reset(reset), .word_clock_out(), .word_in(clock_word), .D_out(clock509_oddr), .locked(oserdes_pll_locked1));
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(7.86), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .MODE("WORD_CLOCK_IN"), .PHASE(PHASE)) mylei2 (.clock_in(clock127), .reset(reset), .word_clock_out(word_clock2), .word_in(revo_word), .D_out(revo_oddr), .locked(oserdes_pll_locked2));
OBUFDS out1 (.I(1'b0), .O(clk78_p), .OB(clk78_n));
OBUFDS out2 (.I(revo_oddr), .O(trg36_p), .OB(trg36_n));
assign lemo = clock509_oddr;
assign clk_se = 0;
assign trg_se = 0;
endmodule | module mza_test031_clock509_and_revo_generator_althea #(
parameter PHASE = 45.0
) (
input local_clock50_in_p, local_clock50_in_n,
input local_clock509_in_p, local_clock509_in_n,
output clk78_p, clk78_n,
output trg36_p, trg36_n,
output clk_se,
output trg_se,
output lemo,
output led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
); |
wire clock50;
wire clock509;
IBUFGDS local_input_clock50_instance (.I(local_clock50_in_p), .IB(local_clock50_in_n), .O(clock50));
IBUFGDS local_input_clock509_instance (.I(local_clock509_in_p), .IB(local_clock509_in_n), .O(clock509));
reg reset = 1;
reg superkekb_reset = 1;
reg [25:0] counter = 0;
always @(posedge clock50) begin
if (counter[9]) begin
reset <= 0;
end
if (counter[11]) begin
superkekb_reset <= 0;
end
counter <= counter + 1'b1;
end
wire [7:0] clock_word = 8'b10101010;
wire [7:0] revo_word;
wire oserdes_pll_locked1;
wire oserdes_pll_locked2;
wire revo;
assign led_7 = oserdes_pll_locked1;
assign led_6 = oserdes_pll_locked2;
assign led_5 = 0;
assign led_4 = revo;
assign led_3 = 0;
assign led_2 = reset;
assign led_1 = superkekb_reset;
assign led_0 = counter[25];
wire clock509_oddr;
wire revo_oddr;
wire word_clock2;
superkekb skb (.clock(word_clock2), .reset(superkekb_reset), .revo(revo), .revo_word(revo_word));
wire rawclock127;
BUFIO2 #(
.DIVIDE(4), .USE_DOUBLER("FALSE"), .I_INVERT("FALSE"), .DIVIDE_BYPASS("FALSE")
) sally (
.I(clock509), .DIVCLK(rawclock127), .IOCLK(), .SERDESSTROBE()
);
wire clock127;
BUFG peter (.I(rawclock127), .O(clock127));
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(7.86), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .MODE("WORD_CLOCK_IN"), .PHASE(0.0)) mylei1 (.clock_in(clock127), .reset(reset), .word_clock_out(), .word_in(clock_word), .D_out(clock509_oddr), .locked(oserdes_pll_locked1));
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(7.86), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .MODE("WORD_CLOCK_IN"), .PHASE(PHASE)) mylei2 (.clock_in(clock127), .reset(reset), .word_clock_out(word_clock2), .word_in(revo_word), .D_out(revo_oddr), .locked(oserdes_pll_locked2));
OBUFDS out1 (.I(1'b0), .O(clk78_p), .OB(clk78_n));
OBUFDS out2 (.I(revo_oddr), .O(trg36_p), .OB(trg36_n));
assign lemo = clock509_oddr;
assign clk_se = 0;
assign trg_se = 0;
endmodule | 2 |
5,940 | data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v | 115,035,459 | mza-test031.clock509_and_revo_generator.althea.revA.v | v | 125 | 291 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v:7: Cannot find include file: lib/superkekb.v\n`include "lib/superkekb.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/superkekb.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/superkekb.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/superkekb.v.sv\n lib/superkekb.v\n lib/superkekb.v.v\n lib/superkekb.v.sv\n obj_dir/lib/superkekb.v\n obj_dir/lib/superkekb.v.v\n obj_dir/lib/superkekb.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v:8: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v:94: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v:98: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 6,779 | module | module joestrummer_tb;
reg joestrummer_local_clock50_in_p = 0, joestrummer_local_clock50_in_n = 1;
reg joestrummer_local_clock509_in_p = 0, joestrummer_local_clock509_in_n = 1;
wire joestrummer_trg36_p, joestrummer_trg36_n;
wire joestrummer_lemo;
wire joestrummer_led_0, joestrummer_led_1, joestrummer_led_2, joestrummer_led_3, joestrummer_led_4, joestrummer_led_5, joestrummer_led_6, joestrummer_led_7;
mza_test031_clock509_and_revo_generator_althea joestrummer (
.local_clock50_in_p(joestrummer_local_clock50_in_p), .local_clock50_in_n(joestrummer_local_clock50_in_n),
.local_clock509_in_p(joestrummer_local_clock509_in_p), .local_clock509_in_n(joestrummer_local_clock509_in_n),
.clk78_p(), .clk78_n(),
.trg36_p(joestrummer_trg36_p), .trg36_n(joestrummer_trg36_n),
.lemo(joestrummer_lemo),
.led_0(joestrummer_led_0), .led_1(joestrummer_led_1), .led_2(joestrummer_led_2), .led_3(joestrummer_led_3),
.led_4(joestrummer_led_4), .led_5(joestrummer_led_5), .led_6(joestrummer_led_6), .led_7(joestrummer_led_7)
);
initial begin
joestrummer_local_clock509_in_p = 0; joestrummer_local_clock509_in_n = 1;
joestrummer_local_clock50_in_p = 0; joestrummer_local_clock50_in_n = 1;
end
always begin
#1;
joestrummer_local_clock509_in_p <= ~joestrummer_local_clock509_in_p; joestrummer_local_clock509_in_n <= ~joestrummer_local_clock509_in_n;
end
always begin
#10;
joestrummer_local_clock50_in_p <= ~joestrummer_local_clock50_in_p; joestrummer_local_clock50_in_n <= ~joestrummer_local_clock50_in_n;
end
endmodule | module joestrummer_tb; |
reg joestrummer_local_clock50_in_p = 0, joestrummer_local_clock50_in_n = 1;
reg joestrummer_local_clock509_in_p = 0, joestrummer_local_clock509_in_n = 1;
wire joestrummer_trg36_p, joestrummer_trg36_n;
wire joestrummer_lemo;
wire joestrummer_led_0, joestrummer_led_1, joestrummer_led_2, joestrummer_led_3, joestrummer_led_4, joestrummer_led_5, joestrummer_led_6, joestrummer_led_7;
mza_test031_clock509_and_revo_generator_althea joestrummer (
.local_clock50_in_p(joestrummer_local_clock50_in_p), .local_clock50_in_n(joestrummer_local_clock50_in_n),
.local_clock509_in_p(joestrummer_local_clock509_in_p), .local_clock509_in_n(joestrummer_local_clock509_in_n),
.clk78_p(), .clk78_n(),
.trg36_p(joestrummer_trg36_p), .trg36_n(joestrummer_trg36_n),
.lemo(joestrummer_lemo),
.led_0(joestrummer_led_0), .led_1(joestrummer_led_1), .led_2(joestrummer_led_2), .led_3(joestrummer_led_3),
.led_4(joestrummer_led_4), .led_5(joestrummer_led_5), .led_6(joestrummer_led_6), .led_7(joestrummer_led_7)
);
initial begin
joestrummer_local_clock509_in_p = 0; joestrummer_local_clock509_in_n = 1;
joestrummer_local_clock50_in_p = 0; joestrummer_local_clock50_in_n = 1;
end
always begin
#1;
joestrummer_local_clock509_in_p <= ~joestrummer_local_clock509_in_p; joestrummer_local_clock509_in_n <= ~joestrummer_local_clock509_in_n;
end
always begin
#10;
joestrummer_local_clock50_in_p <= ~joestrummer_local_clock50_in_p; joestrummer_local_clock50_in_n <= ~joestrummer_local_clock50_in_n;
end
endmodule | 2 |
5,941 | data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v | 115,035,459 | mza-test031.clock509_and_revo_generator.althea.revA.v | v | 125 | 291 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v:7: Cannot find include file: lib/superkekb.v\n`include "lib/superkekb.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/superkekb.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/superkekb.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/superkekb.v.sv\n lib/superkekb.v\n lib/superkekb.v.v\n lib/superkekb.v.sv\n obj_dir/lib/superkekb.v\n obj_dir/lib/superkekb.v.v\n obj_dir/lib/superkekb.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v:8: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v:94: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test031.clock509_and_revo_generator.althea.revA.v:98: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 6,779 | module | module mza_test031_clock509_and_revo_generator_althea_top (
input clock50_p, clock50_n,
output a_p, a_n,
output b_p, b_n,
input d_p, d_n,
output h_p, k_p,
output lemo,
output led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
);
mza_test031_clock509_and_revo_generator_althea mything (
.local_clock50_in_p(clock50_p), .local_clock50_in_n(clock50_n),
.local_clock509_in_p(d_p), .local_clock509_in_n(d_n),
.clk78_p(a_p), .clk78_n(a_n),
.trg36_p(b_p), .trg36_n(b_n),
.clk_se(k_p),
.trg_se(h_p),
.lemo(lemo),
.led_0(led_0), .led_1(led_1), .led_2(led_2), .led_3(led_3),
.led_4(led_4), .led_5(led_5), .led_6(led_6), .led_7(led_7)
);
endmodule | module mza_test031_clock509_and_revo_generator_althea_top (
input clock50_p, clock50_n,
output a_p, a_n,
output b_p, b_n,
input d_p, d_n,
output h_p, k_p,
output lemo,
output led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
); |
mza_test031_clock509_and_revo_generator_althea mything (
.local_clock50_in_p(clock50_p), .local_clock50_in_n(clock50_n),
.local_clock509_in_p(d_p), .local_clock509_in_n(d_n),
.clk78_p(a_p), .clk78_n(a_n),
.trg36_p(b_p), .trg36_n(b_n),
.clk_se(k_p),
.trg_se(h_p),
.lemo(lemo),
.led_0(led_0), .led_1(led_1), .led_2(led_2), .led_3(led_3),
.led_4(led_4), .led_5(led_5), .led_6(led_6), .led_7(led_7)
);
endmodule | 2 |
5,945 | data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v | 115,035,459 | mza-test033.clock50_sine500.althea.revA.v | v | 53 | 252 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v:11: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS local_input_clock50_instance (.I(local_clock50_in_p), .IB(local_clock50_in_n), .O(clock50));\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.sv\n IBUFGDS\n IBUFGDS.v\n IBUFGDS.sv\n obj_dir/IBUFGDS\n obj_dir/IBUFGDS.v\n obj_dir/IBUFGDS.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v:32: Cannot find file containing module: \'simplepll_BASE\'\n simplepll_BASE #(.OVERALL_DIVIDE(1), .MULTIPLY(10), .DIVIDE0(4), .PHASE0(0.0), .PERIOD(20.0)) other (.clockin(clock50), .reset(reset), .clock0out(rawclock125), .locked(other_pll_locked)); \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v:34: Cannot find file containing module: \'BUFG\'\n BUFG mrt (.I(rawclock125), .O(clock125));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v:36: Cannot find file containing module: \'ocyrus_single8\'\n ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .MODE("WORD_CLOCK_IN")) mylei (.clock_in(clock125), .reset(reset), .word_clock_out(), .word_in(clock_word), .D_out(clock500_oddr), .locked(oserdes_pll_locked));\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 6,781 | module | module mza_test033_clock50_sine500_althea (
input local_clock50_in_p, local_clock50_in_n,
output lemo,
output led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
);
wire clock50;
IBUFGDS local_input_clock50_instance (.I(local_clock50_in_p), .IB(local_clock50_in_n), .O(clock50));
reg reset = 1;
reg [25:0] counter = 0;
always @(posedge clock50) begin
if (counter[10]) begin
reset <= 0;
end
counter <= counter + 1'b1;
end
parameter clock_word = 8'b10101010;
wire other_pll_locked;
wire oserdes_pll_locked;
assign led_7 = other_pll_locked;
assign led_6 = oserdes_pll_locked;
assign led_5 = 0;
assign led_4 = 0;
assign led_3 = reset;
assign led_2 = 0;
assign led_1 = 0;
assign led_0 = counter[25];
wire rawclock125;
simplepll_BASE #(.OVERALL_DIVIDE(1), .MULTIPLY(10), .DIVIDE0(4), .PHASE0(0.0), .PERIOD(20.0)) other (.clockin(clock50), .reset(reset), .clock0out(rawclock125), .locked(other_pll_locked));
wire clock125;
BUFG mrt (.I(rawclock125), .O(clock125));
wire clock500_oddr;
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .MODE("WORD_CLOCK_IN")) mylei (.clock_in(clock125), .reset(reset), .word_clock_out(), .word_in(clock_word), .D_out(clock500_oddr), .locked(oserdes_pll_locked));
assign lemo = clock500_oddr;
endmodule | module mza_test033_clock50_sine500_althea (
input local_clock50_in_p, local_clock50_in_n,
output lemo,
output led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
); |
wire clock50;
IBUFGDS local_input_clock50_instance (.I(local_clock50_in_p), .IB(local_clock50_in_n), .O(clock50));
reg reset = 1;
reg [25:0] counter = 0;
always @(posedge clock50) begin
if (counter[10]) begin
reset <= 0;
end
counter <= counter + 1'b1;
end
parameter clock_word = 8'b10101010;
wire other_pll_locked;
wire oserdes_pll_locked;
assign led_7 = other_pll_locked;
assign led_6 = oserdes_pll_locked;
assign led_5 = 0;
assign led_4 = 0;
assign led_3 = reset;
assign led_2 = 0;
assign led_1 = 0;
assign led_0 = counter[25];
wire rawclock125;
simplepll_BASE #(.OVERALL_DIVIDE(1), .MULTIPLY(10), .DIVIDE0(4), .PHASE0(0.0), .PERIOD(20.0)) other (.clockin(clock50), .reset(reset), .clock0out(rawclock125), .locked(other_pll_locked));
wire clock125;
BUFG mrt (.I(rawclock125), .O(clock125));
wire clock500_oddr;
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .MODE("WORD_CLOCK_IN")) mylei (.clock_in(clock125), .reset(reset), .word_clock_out(), .word_in(clock_word), .D_out(clock500_oddr), .locked(oserdes_pll_locked));
assign lemo = clock500_oddr;
endmodule | 2 |
5,946 | data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v | 115,035,459 | mza-test033.clock50_sine500.althea.revA.v | v | 53 | 252 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v:11: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS local_input_clock50_instance (.I(local_clock50_in_p), .IB(local_clock50_in_n), .O(clock50));\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.sv\n IBUFGDS\n IBUFGDS.v\n IBUFGDS.sv\n obj_dir/IBUFGDS\n obj_dir/IBUFGDS.v\n obj_dir/IBUFGDS.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v:32: Cannot find file containing module: \'simplepll_BASE\'\n simplepll_BASE #(.OVERALL_DIVIDE(1), .MULTIPLY(10), .DIVIDE0(4), .PHASE0(0.0), .PERIOD(20.0)) other (.clockin(clock50), .reset(reset), .clock0out(rawclock125), .locked(other_pll_locked)); \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v:34: Cannot find file containing module: \'BUFG\'\n BUFG mrt (.I(rawclock125), .O(clock125));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v:36: Cannot find file containing module: \'ocyrus_single8\'\n ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .MODE("WORD_CLOCK_IN")) mylei (.clock_in(clock125), .reset(reset), .word_clock_out(), .word_in(clock_word), .D_out(clock500_oddr), .locked(oserdes_pll_locked));\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 6,781 | module | module mza_test033_clock50_sine500_althea_top (
input clock50_p, clock50_n,
output lemo,
output led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
);
mza_test033_clock50_sine500_althea sharona (
.local_clock50_in_p(clock50_p), .local_clock50_in_n(clock50_n),
.lemo(lemo),
.led_0(led_0), .led_1(led_1), .led_2(led_2), .led_3(led_3),
.led_4(led_4), .led_5(led_5), .led_6(led_6), .led_7(led_7)
);
endmodule | module mza_test033_clock50_sine500_althea_top (
input clock50_p, clock50_n,
output lemo,
output led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
); |
mza_test033_clock50_sine500_althea sharona (
.local_clock50_in_p(clock50_p), .local_clock50_in_n(clock50_n),
.lemo(lemo),
.led_0(led_0), .led_1(led_1), .led_2(led_2), .led_3(led_3),
.led_4(led_4), .led_5(led_5), .led_6(led_6), .led_7(led_7)
);
endmodule | 2 |
5,947 | data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v | 115,035,459 | mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v | v | 293 | 158 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:5: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:7: Cannot find include file: mza-test031.clock509_and_revo_generator.althea.v\n`include "mza-test031.clock509_and_revo_generator.althea.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:8: Cannot find include file: mza-test032.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.v\n`include "mza-test032.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:9: Cannot find include file: mza-test035.SCROD_XRM_clock_and_revo_receiver_frame9_and_trigger_generator.v\n`include "mza-test035.SCROD_XRM_clock_and_revo_receiver_frame9_and_trigger_generator.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:50: Unsupported: Ignoring delay on this delayed statement.\n #60000;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:52: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:56: Unsupported: Ignoring delay on this delayed statement.\n #8000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:58: Unsupported: Ignoring delay on this delayed statement.\n #2000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:71: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:75: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:128: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:132: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:180: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:182: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:191: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:195: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:249: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:253: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 4 error(s), 15 warning(s)\n' | 6,782 | module | module joestrummer_and_rafferty_tb;
reg joestrummer_local_clock50_in_p = 0, joestrummer_local_clock50_in_n = 1;
reg joestrummer_local_clock509_in_p = 0, joestrummer_local_clock509_in_n = 1;
wire joestrummer_trg36_p, joestrummer_trg36_n;
wire joestrummer_lemo;
wire joestrummer_led_0, joestrummer_led_1, joestrummer_led_2, joestrummer_led_3, joestrummer_led_4, joestrummer_led_5, joestrummer_led_6, joestrummer_led_7;
wire raw_recovered_revo;
wire rafferty_clk78_p;
wire rafferty_clk78_n;
wire rafferty_trg36_p;
wire rafferty_trg36_n;
assign raw_recovered_revo = rafferty_clk78_p ^ rafferty_trg36_p;
reg recovered_revo = 0;
mza_test031_clock509_and_revo_generator_althea joestrummer (
.local_clock50_in_p(joestrummer_local_clock50_in_p), .local_clock50_in_n(joestrummer_local_clock50_in_n),
.local_clock509_in_p(joestrummer_local_clock509_in_p), .local_clock509_in_n(joestrummer_local_clock509_in_n),
.clk78_p(), .clk78_n(),
.trg_se(),
.clk_se(),
.trg36_p(joestrummer_trg36_p), .trg36_n(joestrummer_trg36_n),
.lemo(joestrummer_lemo),
.led_0(joestrummer_led_0), .led_1(joestrummer_led_1), .led_2(joestrummer_led_2), .led_3(joestrummer_led_3),
.led_4(joestrummer_led_4), .led_5(joestrummer_led_5), .led_6(joestrummer_led_6), .led_7(joestrummer_led_7)
);
wire remote_clock_p, remote_clock_n;
wire flaky_clock;
reg flaky_clock_select = 0;
BUFGMUX forky (.I0(joestrummer_lemo), .I1(1'b0), .S(flaky_clock_select), .O(flaky_clock));
OBUFDS comparator (.I(flaky_clock), .O(remote_clock_p), .OB(remote_clock_n));
reg delay_select = 0;
initial begin
joestrummer_local_clock509_in_p = 0; joestrummer_local_clock509_in_n = 1;
joestrummer_local_clock50_in_p = 0; joestrummer_local_clock50_in_n = 1;
rafferty_local_clock50_in_p <= 0; rafferty_local_clock50_in_n <= 1;
rafferty_local_clock509_in_p <= 0; rafferty_local_clock509_in_n <= 1;
rafferty_clock_select <= 0;
recovered_revo <= 0;
flaky_clock_select <= 0;
delay_select <= 0;
#60000;
flaky_clock_select <= 1;
#4000;
flaky_clock_select <= 0;
#10000;
flaky_clock_select <= 1;
#8000;
delay_select <= 1;
#2000;
flaky_clock_select <= 0;
end
wire intermediate0_trg36_p, intermediate0_trg36_n;
clocked_1ns_delay snip0_p (.in(joestrummer_trg36_p), .out(intermediate0_trg36_p));
clocked_1ns_delay snip0_n (.in(joestrummer_trg36_n), .out(intermediate0_trg36_n));
wire intermediate1_trg36_p, intermediate1_trg36_n;
clocked_2ns_delay snip1_p (.in(joestrummer_trg36_p), .out(intermediate1_trg36_p));
clocked_2ns_delay snip1_n (.in(joestrummer_trg36_n), .out(intermediate1_trg36_n));
wire intermediate_trg36_p, intermediate_trg36_n;
mux mucks_p (.I0(intermediate0_trg36_p), .I1(intermediate1_trg36_p), .S(delay_select), .O(intermediate_trg36_p));
mux mucks_n (.I0(intermediate0_trg36_n), .I1(intermediate1_trg36_n), .S(delay_select), .O(intermediate_trg36_n));
always begin
#1;
joestrummer_local_clock509_in_p <= ~joestrummer_local_clock509_in_p; joestrummer_local_clock509_in_n <= ~joestrummer_local_clock509_in_n;
end
always begin
#10;
joestrummer_local_clock50_in_p <= ~joestrummer_local_clock50_in_p; joestrummer_local_clock50_in_n <= ~joestrummer_local_clock50_in_n;
end
reg rafferty_local_clock50_in_p = 0;
reg rafferty_local_clock50_in_n = 1;
reg rafferty_local_clock509_in_p = 0;
reg rafferty_local_clock509_in_n = 1;
wire rafferty_out1_p;
wire rafferty_out1_n;
wire rafferty_outa_p;
wire rafferty_outa_n;
wire rafferty_rsv54_p;
wire rafferty_rsv54_n;
wire rafferty_lemo;
wire rafferty_ack12_p;
wire rafferty_ack12_n;
wire rafferty_led_revo;
wire rafferty_led_rfclock;
wire rafferty_driven_high;
reg rafferty_clock_select = 0;
wire rafferty_led_0;
wire rafferty_led_1;
wire rafferty_led_2;
wire rafferty_led_3;
wire rafferty_led_4;
wire rafferty_led_5;
wire rafferty_led_6;
wire rafferty_led_7;
mza_test032_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea #(
.PLL_NOT_LOCKED_COUNTER_MAX(50),
.PULSE_COUNT_MIN(10)
) rafferty (
.local_clock50_in_p(rafferty_local_clock50_in_p), .local_clock50_in_n(rafferty_local_clock50_in_n),
.local_clock509_in_p(1'b0), .local_clock509_in_n(1'b1),
.remote_clock509_in_p(remote_clock_p), .remote_clock509_in_n(remote_clock_n),
.remote_revo_in_p(intermediate_trg36_p), .remote_revo_in_n(intermediate_trg36_n),
.clk78_p(rafferty_clk78_p), .clk78_n(rafferty_clk78_n),
.trg36_p(rafferty_trg36_p), .trg36_n(rafferty_trg36_n),
.rsv54_p(rafferty_rsv54_p), .rsv54_n(rafferty_rsv54_n),
.ack12_p(rafferty_ack12_p), .ack12_n(rafferty_ack12_n),
.out1_p(rafferty_out1_p), .out1_n(rafferty_out1_n),
.outa_p(rafferty_outa_p), .outa_n(rafferty_outa_n),
.lemo(rafferty_lemo),
.led_revo(rafferty_led_revo),
.led_rfclock(rafferty_led_rfclock),
.clock_select(rafferty_clock_select),
.driven_high(rafferty_driven_high),
.led_0(rafferty_led_0), .led_1(rafferty_led_1), .led_2(rafferty_led_2), .led_3(rafferty_led_3),
.led_4(rafferty_led_4), .led_5(rafferty_led_5), .led_6(rafferty_led_6), .led_7(rafferty_led_7)
);
always begin
#1;
rafferty_local_clock509_in_p <= ~rafferty_local_clock509_in_p; rafferty_local_clock509_in_n <= ~rafferty_local_clock509_in_n;
end
always begin
#10;
rafferty_local_clock50_in_p <= ~rafferty_local_clock50_in_p; rafferty_local_clock50_in_n <= ~rafferty_local_clock50_in_n;
end
always @(negedge rafferty_clk78_p) begin
recovered_revo <= raw_recovered_revo;
end
endmodule | module joestrummer_and_rafferty_tb; |
reg joestrummer_local_clock50_in_p = 0, joestrummer_local_clock50_in_n = 1;
reg joestrummer_local_clock509_in_p = 0, joestrummer_local_clock509_in_n = 1;
wire joestrummer_trg36_p, joestrummer_trg36_n;
wire joestrummer_lemo;
wire joestrummer_led_0, joestrummer_led_1, joestrummer_led_2, joestrummer_led_3, joestrummer_led_4, joestrummer_led_5, joestrummer_led_6, joestrummer_led_7;
wire raw_recovered_revo;
wire rafferty_clk78_p;
wire rafferty_clk78_n;
wire rafferty_trg36_p;
wire rafferty_trg36_n;
assign raw_recovered_revo = rafferty_clk78_p ^ rafferty_trg36_p;
reg recovered_revo = 0;
mza_test031_clock509_and_revo_generator_althea joestrummer (
.local_clock50_in_p(joestrummer_local_clock50_in_p), .local_clock50_in_n(joestrummer_local_clock50_in_n),
.local_clock509_in_p(joestrummer_local_clock509_in_p), .local_clock509_in_n(joestrummer_local_clock509_in_n),
.clk78_p(), .clk78_n(),
.trg_se(),
.clk_se(),
.trg36_p(joestrummer_trg36_p), .trg36_n(joestrummer_trg36_n),
.lemo(joestrummer_lemo),
.led_0(joestrummer_led_0), .led_1(joestrummer_led_1), .led_2(joestrummer_led_2), .led_3(joestrummer_led_3),
.led_4(joestrummer_led_4), .led_5(joestrummer_led_5), .led_6(joestrummer_led_6), .led_7(joestrummer_led_7)
);
wire remote_clock_p, remote_clock_n;
wire flaky_clock;
reg flaky_clock_select = 0;
BUFGMUX forky (.I0(joestrummer_lemo), .I1(1'b0), .S(flaky_clock_select), .O(flaky_clock));
OBUFDS comparator (.I(flaky_clock), .O(remote_clock_p), .OB(remote_clock_n));
reg delay_select = 0;
initial begin
joestrummer_local_clock509_in_p = 0; joestrummer_local_clock509_in_n = 1;
joestrummer_local_clock50_in_p = 0; joestrummer_local_clock50_in_n = 1;
rafferty_local_clock50_in_p <= 0; rafferty_local_clock50_in_n <= 1;
rafferty_local_clock509_in_p <= 0; rafferty_local_clock509_in_n <= 1;
rafferty_clock_select <= 0;
recovered_revo <= 0;
flaky_clock_select <= 0;
delay_select <= 0;
#60000;
flaky_clock_select <= 1;
#4000;
flaky_clock_select <= 0;
#10000;
flaky_clock_select <= 1;
#8000;
delay_select <= 1;
#2000;
flaky_clock_select <= 0;
end
wire intermediate0_trg36_p, intermediate0_trg36_n;
clocked_1ns_delay snip0_p (.in(joestrummer_trg36_p), .out(intermediate0_trg36_p));
clocked_1ns_delay snip0_n (.in(joestrummer_trg36_n), .out(intermediate0_trg36_n));
wire intermediate1_trg36_p, intermediate1_trg36_n;
clocked_2ns_delay snip1_p (.in(joestrummer_trg36_p), .out(intermediate1_trg36_p));
clocked_2ns_delay snip1_n (.in(joestrummer_trg36_n), .out(intermediate1_trg36_n));
wire intermediate_trg36_p, intermediate_trg36_n;
mux mucks_p (.I0(intermediate0_trg36_p), .I1(intermediate1_trg36_p), .S(delay_select), .O(intermediate_trg36_p));
mux mucks_n (.I0(intermediate0_trg36_n), .I1(intermediate1_trg36_n), .S(delay_select), .O(intermediate_trg36_n));
always begin
#1;
joestrummer_local_clock509_in_p <= ~joestrummer_local_clock509_in_p; joestrummer_local_clock509_in_n <= ~joestrummer_local_clock509_in_n;
end
always begin
#10;
joestrummer_local_clock50_in_p <= ~joestrummer_local_clock50_in_p; joestrummer_local_clock50_in_n <= ~joestrummer_local_clock50_in_n;
end
reg rafferty_local_clock50_in_p = 0;
reg rafferty_local_clock50_in_n = 1;
reg rafferty_local_clock509_in_p = 0;
reg rafferty_local_clock509_in_n = 1;
wire rafferty_out1_p;
wire rafferty_out1_n;
wire rafferty_outa_p;
wire rafferty_outa_n;
wire rafferty_rsv54_p;
wire rafferty_rsv54_n;
wire rafferty_lemo;
wire rafferty_ack12_p;
wire rafferty_ack12_n;
wire rafferty_led_revo;
wire rafferty_led_rfclock;
wire rafferty_driven_high;
reg rafferty_clock_select = 0;
wire rafferty_led_0;
wire rafferty_led_1;
wire rafferty_led_2;
wire rafferty_led_3;
wire rafferty_led_4;
wire rafferty_led_5;
wire rafferty_led_6;
wire rafferty_led_7;
mza_test032_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea #(
.PLL_NOT_LOCKED_COUNTER_MAX(50),
.PULSE_COUNT_MIN(10)
) rafferty (
.local_clock50_in_p(rafferty_local_clock50_in_p), .local_clock50_in_n(rafferty_local_clock50_in_n),
.local_clock509_in_p(1'b0), .local_clock509_in_n(1'b1),
.remote_clock509_in_p(remote_clock_p), .remote_clock509_in_n(remote_clock_n),
.remote_revo_in_p(intermediate_trg36_p), .remote_revo_in_n(intermediate_trg36_n),
.clk78_p(rafferty_clk78_p), .clk78_n(rafferty_clk78_n),
.trg36_p(rafferty_trg36_p), .trg36_n(rafferty_trg36_n),
.rsv54_p(rafferty_rsv54_p), .rsv54_n(rafferty_rsv54_n),
.ack12_p(rafferty_ack12_p), .ack12_n(rafferty_ack12_n),
.out1_p(rafferty_out1_p), .out1_n(rafferty_out1_n),
.outa_p(rafferty_outa_p), .outa_n(rafferty_outa_n),
.lemo(rafferty_lemo),
.led_revo(rafferty_led_revo),
.led_rfclock(rafferty_led_rfclock),
.clock_select(rafferty_clock_select),
.driven_high(rafferty_driven_high),
.led_0(rafferty_led_0), .led_1(rafferty_led_1), .led_2(rafferty_led_2), .led_3(rafferty_led_3),
.led_4(rafferty_led_4), .led_5(rafferty_led_5), .led_6(rafferty_led_6), .led_7(rafferty_led_7)
);
always begin
#1;
rafferty_local_clock509_in_p <= ~rafferty_local_clock509_in_p; rafferty_local_clock509_in_n <= ~rafferty_local_clock509_in_n;
end
always begin
#10;
rafferty_local_clock50_in_p <= ~rafferty_local_clock50_in_p; rafferty_local_clock50_in_n <= ~rafferty_local_clock50_in_n;
end
always @(negedge rafferty_clk78_p) begin
recovered_revo <= raw_recovered_revo;
end
endmodule | 2 |
5,948 | data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v | 115,035,459 | mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v | v | 293 | 158 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:5: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:7: Cannot find include file: mza-test031.clock509_and_revo_generator.althea.v\n`include "mza-test031.clock509_and_revo_generator.althea.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:8: Cannot find include file: mza-test032.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.v\n`include "mza-test032.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:9: Cannot find include file: mza-test035.SCROD_XRM_clock_and_revo_receiver_frame9_and_trigger_generator.v\n`include "mza-test035.SCROD_XRM_clock_and_revo_receiver_frame9_and_trigger_generator.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:50: Unsupported: Ignoring delay on this delayed statement.\n #60000;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:52: Unsupported: Ignoring delay on this delayed statement.\n #4000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:56: Unsupported: Ignoring delay on this delayed statement.\n #8000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:58: Unsupported: Ignoring delay on this delayed statement.\n #2000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:71: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:75: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:128: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:132: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:180: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:182: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:191: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:195: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:249: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test034.simulation_of_interaction_between_joestrummer_and_rafferty_and_scrod.v:253: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 4 error(s), 15 warning(s)\n' | 6,782 | module | module joestrummer_and_rafferty_and_scrod_tb;
reg joestrummer_local_clock50_in_p = 0, joestrummer_local_clock50_in_n = 1;
reg joestrummer_local_clock509_in_p = 0, joestrummer_local_clock509_in_n = 1;
wire joestrummer_trg36_p, joestrummer_trg36_n;
wire joestrummer_lemo;
wire joestrummer_led_0, joestrummer_led_1, joestrummer_led_2, joestrummer_led_3, joestrummer_led_4, joestrummer_led_5, joestrummer_led_6, joestrummer_led_7;
wire raw_recovered_revo;
wire rafferty_clk78_p;
wire rafferty_clk78_n;
wire rafferty_trg36_p;
wire rafferty_trg36_n;
assign raw_recovered_revo = rafferty_clk78_p ^ rafferty_trg36_p;
reg recovered_revo = 0;
mza_test031_clock509_and_revo_generator_althea joestrummer (
.local_clock50_in_p(joestrummer_local_clock50_in_p), .local_clock50_in_n(joestrummer_local_clock50_in_n),
.local_clock509_in_p(joestrummer_local_clock509_in_p), .local_clock509_in_n(joestrummer_local_clock509_in_n),
.clk78_p(), .clk78_n(),
.trg_se(),
.clk_se(),
.trg36_p(joestrummer_trg36_p), .trg36_n(joestrummer_trg36_n),
.lemo(joestrummer_lemo),
.led_0(joestrummer_led_0), .led_1(joestrummer_led_1), .led_2(joestrummer_led_2), .led_3(joestrummer_led_3),
.led_4(joestrummer_led_4), .led_5(joestrummer_led_5), .led_6(joestrummer_led_6), .led_7(joestrummer_led_7)
);
reg [24:0] scrod_bunch_marker_a_position = 0;
reg [24:0] scrod_bunch_marker_b_position = 1;
reg [24:0] scrod_bunch_marker_c_position = 2;
reg [24:0] scrod_bunch_marker_d_position = 3;
reg rafferty_clock_select = 0;
reg scrod_reset = 1;
reg scrod_xrm_trigger_enabled = 0;
reg [4:0] scrod_trig_prescale_N_log2 = 12;
initial begin
joestrummer_local_clock509_in_p = 0; joestrummer_local_clock509_in_n = 1;
joestrummer_local_clock50_in_p = 0; joestrummer_local_clock50_in_n = 1;
rafferty_local_clock50_in_p <= 0; rafferty_local_clock50_in_n <= 1;
rafferty_local_clock509_in_p <= 0; rafferty_local_clock509_in_n <= 1;
rafferty_clock_select <= 0;
recovered_revo <= 0;
scrod_reset <= 1;
#100;
scrod_reset <= 0;
#100;
scrod_xrm_trigger_enabled <= 1;
scrod_bunch_marker_a_position[12:2] <= 0; scrod_bunch_marker_a_position[24:16] <= 9'b111111111;
scrod_bunch_marker_b_position[12:2] <= 2; scrod_bunch_marker_b_position[24:16] <= 9'b000000001;
scrod_bunch_marker_c_position[12:2] <= 3; scrod_bunch_marker_c_position[24:16] <= 9'b100000000;
scrod_bunch_marker_d_position[12:2] <= 4; scrod_bunch_marker_d_position[24:16] <= 9'b000111000;
scrod_trig_prescale_N_log2 <= 2;
end
always begin
#1;
joestrummer_local_clock509_in_p <= ~joestrummer_local_clock509_in_p; joestrummer_local_clock509_in_n <= ~joestrummer_local_clock509_in_n;
end
always begin
#10;
joestrummer_local_clock50_in_p <= ~joestrummer_local_clock50_in_p; joestrummer_local_clock50_in_n <= ~joestrummer_local_clock50_in_n;
end
reg rafferty_local_clock50_in_p = 0;
reg rafferty_local_clock50_in_n = 1;
reg rafferty_local_clock509_in_p = 0;
reg rafferty_local_clock509_in_n = 1;
wire rafferty_out1_p;
wire rafferty_out1_n;
wire rafferty_outa_p;
wire rafferty_outa_n;
wire rafferty_rsv54_p = 0;
wire rafferty_rsv54_n = 1;
wire rafferty_lemo;
wire rafferty_ack12_p = 0;
wire rafferty_ack12_n = 1;
wire rafferty_led_revo;
wire rafferty_led_rfclock;
wire rafferty_driven_high;
wire rafferty_led_0;
wire rafferty_led_1;
wire rafferty_led_2;
wire rafferty_led_3;
wire rafferty_led_4;
wire rafferty_led_5;
wire rafferty_led_6;
wire rafferty_led_7;
wire remote_clock_p, remote_clock_n;
OBUFDS samwise (.I(joestrummer_lemo), .O(remote_clock_p), .OB(remote_clock_n));
mza_test032_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea #(
.PLL_NOT_LOCKED_COUNTER_MAX(50),
.PULSE_COUNT_MIN(10)
) rafferty (
.local_clock50_in_p(rafferty_local_clock50_in_p), .local_clock50_in_n(rafferty_local_clock50_in_n),
.local_clock509_in_p(1'b0), .local_clock509_in_n(1'b1),
.remote_clock509_in_p(remote_clock_p), .remote_clock509_in_n(remote_clock_n),
.remote_revo_in_p(joestrummer_trg36_p), .remote_revo_in_n(joestrummer_trg36_n),
.clk78_p(rafferty_clk78_p), .clk78_n(rafferty_clk78_n),
.trg36_p(rafferty_trg36_p), .trg36_n(rafferty_trg36_n),
.rsv54_p(rafferty_rsv54_p), .rsv54_n(rafferty_rsv54_n),
.ack12_p(rafferty_ack12_p), .ack12_n(rafferty_ack12_n),
.out1_p(rafferty_out1_p), .out1_n(rafferty_out1_n),
.outa_p(rafferty_outa_p), .outa_n(rafferty_outa_n),
.lemo(rafferty_lemo),
.led_revo(rafferty_led_revo),
.led_rfclock(rafferty_led_rfclock),
.clock_select(rafferty_clock_select),
.driven_high(rafferty_driven_high),
.led_0(rafferty_led_0), .led_1(rafferty_led_1), .led_2(rafferty_led_2), .led_3(rafferty_led_3),
.led_4(rafferty_led_4), .led_5(rafferty_led_5), .led_6(rafferty_led_6), .led_7(rafferty_led_7)
);
always begin
#1;
rafferty_local_clock509_in_p <= ~rafferty_local_clock509_in_p; rafferty_local_clock509_in_n <= ~rafferty_local_clock509_in_n;
end
always begin
#10;
rafferty_local_clock50_in_p <= ~rafferty_local_clock50_in_p; rafferty_local_clock50_in_n <= ~rafferty_local_clock50_in_n;
end
always @(negedge rafferty_clk78_p) begin
recovered_revo <= raw_recovered_revo;
end
wire scrod_xrm_trigger;
wire scrod_frame;
wire scrod_frame9;
XRM_clock_and_revo_receiver_frame9_and_trigger_generator scrod (
.remote_clock127_p(rafferty_clk78_p), .remote_clock127_n(rafferty_clk78_n),
.remote_revo_p(rafferty_trg36_p), .remote_revo_n(rafferty_trg36_n),
.rsv_p(), .rsv_n(),
.ack_p(), .ack_n(),
.reset(scrod_reset),
.xrm_trigger_enabled(scrod_xrm_trigger_enabled),
.trig_prescale_N_log2(scrod_trig_prescale_N_log2),
.config_bunch_marker_a_position(scrod_bunch_marker_a_position),
.config_bunch_marker_b_position(scrod_bunch_marker_b_position),
.config_bunch_marker_c_position(scrod_bunch_marker_c_position),
.config_bunch_marker_d_position(scrod_bunch_marker_d_position),
.config_desired_trigger_quantity_for_bunch_marker_a(32'b0),
.config_desired_trigger_quantity_for_bunch_marker_b(32'b0),
.config_desired_trigger_quantity_for_bunch_marker_c(32'b0),
.config_desired_trigger_quantity_for_bunch_marker_d(32'b0),
.config_clear_count_of_triggers_for_bunch_markers(4'b0),
.xrm_trigger(scrod_xrm_trigger),
.allTrigs(1'b0),
.frameCount(),
.frame9Count(),
.clockout(),
.oserdes_bit_clock(1'b0),
.oserdes_pulsetrain(),
.config_oserdes_word_trig(32'b0),
.triggerCount(),
.frame(scrod_frame),
.frame9(scrod_frame9)
);
endmodule | module joestrummer_and_rafferty_and_scrod_tb; |
reg joestrummer_local_clock50_in_p = 0, joestrummer_local_clock50_in_n = 1;
reg joestrummer_local_clock509_in_p = 0, joestrummer_local_clock509_in_n = 1;
wire joestrummer_trg36_p, joestrummer_trg36_n;
wire joestrummer_lemo;
wire joestrummer_led_0, joestrummer_led_1, joestrummer_led_2, joestrummer_led_3, joestrummer_led_4, joestrummer_led_5, joestrummer_led_6, joestrummer_led_7;
wire raw_recovered_revo;
wire rafferty_clk78_p;
wire rafferty_clk78_n;
wire rafferty_trg36_p;
wire rafferty_trg36_n;
assign raw_recovered_revo = rafferty_clk78_p ^ rafferty_trg36_p;
reg recovered_revo = 0;
mza_test031_clock509_and_revo_generator_althea joestrummer (
.local_clock50_in_p(joestrummer_local_clock50_in_p), .local_clock50_in_n(joestrummer_local_clock50_in_n),
.local_clock509_in_p(joestrummer_local_clock509_in_p), .local_clock509_in_n(joestrummer_local_clock509_in_n),
.clk78_p(), .clk78_n(),
.trg_se(),
.clk_se(),
.trg36_p(joestrummer_trg36_p), .trg36_n(joestrummer_trg36_n),
.lemo(joestrummer_lemo),
.led_0(joestrummer_led_0), .led_1(joestrummer_led_1), .led_2(joestrummer_led_2), .led_3(joestrummer_led_3),
.led_4(joestrummer_led_4), .led_5(joestrummer_led_5), .led_6(joestrummer_led_6), .led_7(joestrummer_led_7)
);
reg [24:0] scrod_bunch_marker_a_position = 0;
reg [24:0] scrod_bunch_marker_b_position = 1;
reg [24:0] scrod_bunch_marker_c_position = 2;
reg [24:0] scrod_bunch_marker_d_position = 3;
reg rafferty_clock_select = 0;
reg scrod_reset = 1;
reg scrod_xrm_trigger_enabled = 0;
reg [4:0] scrod_trig_prescale_N_log2 = 12;
initial begin
joestrummer_local_clock509_in_p = 0; joestrummer_local_clock509_in_n = 1;
joestrummer_local_clock50_in_p = 0; joestrummer_local_clock50_in_n = 1;
rafferty_local_clock50_in_p <= 0; rafferty_local_clock50_in_n <= 1;
rafferty_local_clock509_in_p <= 0; rafferty_local_clock509_in_n <= 1;
rafferty_clock_select <= 0;
recovered_revo <= 0;
scrod_reset <= 1;
#100;
scrod_reset <= 0;
#100;
scrod_xrm_trigger_enabled <= 1;
scrod_bunch_marker_a_position[12:2] <= 0; scrod_bunch_marker_a_position[24:16] <= 9'b111111111;
scrod_bunch_marker_b_position[12:2] <= 2; scrod_bunch_marker_b_position[24:16] <= 9'b000000001;
scrod_bunch_marker_c_position[12:2] <= 3; scrod_bunch_marker_c_position[24:16] <= 9'b100000000;
scrod_bunch_marker_d_position[12:2] <= 4; scrod_bunch_marker_d_position[24:16] <= 9'b000111000;
scrod_trig_prescale_N_log2 <= 2;
end
always begin
#1;
joestrummer_local_clock509_in_p <= ~joestrummer_local_clock509_in_p; joestrummer_local_clock509_in_n <= ~joestrummer_local_clock509_in_n;
end
always begin
#10;
joestrummer_local_clock50_in_p <= ~joestrummer_local_clock50_in_p; joestrummer_local_clock50_in_n <= ~joestrummer_local_clock50_in_n;
end
reg rafferty_local_clock50_in_p = 0;
reg rafferty_local_clock50_in_n = 1;
reg rafferty_local_clock509_in_p = 0;
reg rafferty_local_clock509_in_n = 1;
wire rafferty_out1_p;
wire rafferty_out1_n;
wire rafferty_outa_p;
wire rafferty_outa_n;
wire rafferty_rsv54_p = 0;
wire rafferty_rsv54_n = 1;
wire rafferty_lemo;
wire rafferty_ack12_p = 0;
wire rafferty_ack12_n = 1;
wire rafferty_led_revo;
wire rafferty_led_rfclock;
wire rafferty_driven_high;
wire rafferty_led_0;
wire rafferty_led_1;
wire rafferty_led_2;
wire rafferty_led_3;
wire rafferty_led_4;
wire rafferty_led_5;
wire rafferty_led_6;
wire rafferty_led_7;
wire remote_clock_p, remote_clock_n;
OBUFDS samwise (.I(joestrummer_lemo), .O(remote_clock_p), .OB(remote_clock_n));
mza_test032_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea #(
.PLL_NOT_LOCKED_COUNTER_MAX(50),
.PULSE_COUNT_MIN(10)
) rafferty (
.local_clock50_in_p(rafferty_local_clock50_in_p), .local_clock50_in_n(rafferty_local_clock50_in_n),
.local_clock509_in_p(1'b0), .local_clock509_in_n(1'b1),
.remote_clock509_in_p(remote_clock_p), .remote_clock509_in_n(remote_clock_n),
.remote_revo_in_p(joestrummer_trg36_p), .remote_revo_in_n(joestrummer_trg36_n),
.clk78_p(rafferty_clk78_p), .clk78_n(rafferty_clk78_n),
.trg36_p(rafferty_trg36_p), .trg36_n(rafferty_trg36_n),
.rsv54_p(rafferty_rsv54_p), .rsv54_n(rafferty_rsv54_n),
.ack12_p(rafferty_ack12_p), .ack12_n(rafferty_ack12_n),
.out1_p(rafferty_out1_p), .out1_n(rafferty_out1_n),
.outa_p(rafferty_outa_p), .outa_n(rafferty_outa_n),
.lemo(rafferty_lemo),
.led_revo(rafferty_led_revo),
.led_rfclock(rafferty_led_rfclock),
.clock_select(rafferty_clock_select),
.driven_high(rafferty_driven_high),
.led_0(rafferty_led_0), .led_1(rafferty_led_1), .led_2(rafferty_led_2), .led_3(rafferty_led_3),
.led_4(rafferty_led_4), .led_5(rafferty_led_5), .led_6(rafferty_led_6), .led_7(rafferty_led_7)
);
always begin
#1;
rafferty_local_clock509_in_p <= ~rafferty_local_clock509_in_p; rafferty_local_clock509_in_n <= ~rafferty_local_clock509_in_n;
end
always begin
#10;
rafferty_local_clock50_in_p <= ~rafferty_local_clock50_in_p; rafferty_local_clock50_in_n <= ~rafferty_local_clock50_in_n;
end
always @(negedge rafferty_clk78_p) begin
recovered_revo <= raw_recovered_revo;
end
wire scrod_xrm_trigger;
wire scrod_frame;
wire scrod_frame9;
XRM_clock_and_revo_receiver_frame9_and_trigger_generator scrod (
.remote_clock127_p(rafferty_clk78_p), .remote_clock127_n(rafferty_clk78_n),
.remote_revo_p(rafferty_trg36_p), .remote_revo_n(rafferty_trg36_n),
.rsv_p(), .rsv_n(),
.ack_p(), .ack_n(),
.reset(scrod_reset),
.xrm_trigger_enabled(scrod_xrm_trigger_enabled),
.trig_prescale_N_log2(scrod_trig_prescale_N_log2),
.config_bunch_marker_a_position(scrod_bunch_marker_a_position),
.config_bunch_marker_b_position(scrod_bunch_marker_b_position),
.config_bunch_marker_c_position(scrod_bunch_marker_c_position),
.config_bunch_marker_d_position(scrod_bunch_marker_d_position),
.config_desired_trigger_quantity_for_bunch_marker_a(32'b0),
.config_desired_trigger_quantity_for_bunch_marker_b(32'b0),
.config_desired_trigger_quantity_for_bunch_marker_c(32'b0),
.config_desired_trigger_quantity_for_bunch_marker_d(32'b0),
.config_clear_count_of_triggers_for_bunch_markers(4'b0),
.xrm_trigger(scrod_xrm_trigger),
.allTrigs(1'b0),
.frameCount(),
.frame9Count(),
.clockout(),
.oserdes_bit_clock(1'b0),
.oserdes_pulsetrain(),
.config_oserdes_word_trig(32'b0),
.triggerCount(),
.frame(scrod_frame),
.frame9(scrod_frame9)
);
endmodule | 2 |
5,957 | data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v | 115,035,459 | mza-test040.spi-pollable-memory.v | v | 508 | 247 | [] | [] | [] | null | line:44: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:12: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:452: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:456: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:458: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:463: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:465: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:470: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:472: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:476: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:499: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:503: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n' | 6,788 | module | module RAM_ice40_2k_32bit (
input reset,
input write_clock,
input [10:0] write_address,
input [31:0] write_data,
input write_enable,
input read_clock,
input [10:0] read_address,
output [31:0] read_data
);
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_15 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[31:30]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[31:30]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_14 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[29:28]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[29:28]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_13 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[27:26]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[27:26]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_12 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[25:24]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[25:24]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_11 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[23:22]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[23:22]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_10 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[21:20]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[21:20]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_09 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[19:18]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[19:18]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_08 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[17:16]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[17:16]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_07 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[15:14]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[15:14]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_06 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[13:12]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[13:12]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_05 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[11:10]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[11:10]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_04 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[9:8]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[9:8]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_03 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[7:6]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[7:6]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_02 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[5:4]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[5:4]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_01 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[3:2]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[3:2]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_00 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[1:0]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[1:0]));
endmodule | module RAM_ice40_2k_32bit (
input reset,
input write_clock,
input [10:0] write_address,
input [31:0] write_data,
input write_enable,
input read_clock,
input [10:0] read_address,
output [31:0] read_data
); |
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_15 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[31:30]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[31:30]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_14 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[29:28]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[29:28]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_13 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[27:26]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[27:26]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_12 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[25:24]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[25:24]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_11 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[23:22]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[23:22]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_10 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[21:20]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[21:20]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_09 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[19:18]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[19:18]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_08 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[17:16]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[17:16]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_07 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[15:14]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[15:14]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_06 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[13:12]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[13:12]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_05 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[11:10]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[11:10]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_04 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[9:8]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[9:8]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_03 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[7:6]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[7:6]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_02 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[5:4]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[5:4]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_01 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[3:2]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[3:2]));
RAM_ice40_2k_2bit RAM_ice40_2k_2bit_00 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[1:0]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[1:0]));
endmodule | 2 |
5,958 | data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v | 115,035,459 | mza-test040.spi-pollable-memory.v | v | 508 | 247 | [] | [] | [] | null | line:44: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:12: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:452: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:456: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:458: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:463: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:465: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:470: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:472: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:476: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:499: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:503: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n' | 6,788 | module | module RAM_ice40_1k_32bit (
input reset,
input write_clock,
input [9:0] write_address,
input [31:0] write_data,
input write_enable,
input read_clock,
input [9:0] read_address,
output [31:0] read_data
);
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_7 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[31:28]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[31:28]));
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_6 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[27:24]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[27:24]));
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_5 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[23:20]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[23:20]));
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_4 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[19:16]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[19:16]));
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_3 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[15:12]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[15:12]));
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_2 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[11:8]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[11:8]));
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_1 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[7:4]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[7:4]));
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_0 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[3:0]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[3:0]));
endmodule | module RAM_ice40_1k_32bit (
input reset,
input write_clock,
input [9:0] write_address,
input [31:0] write_data,
input write_enable,
input read_clock,
input [9:0] read_address,
output [31:0] read_data
); |
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_7 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[31:28]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[31:28]));
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_6 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[27:24]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[27:24]));
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_5 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[23:20]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[23:20]));
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_4 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[19:16]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[19:16]));
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_3 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[15:12]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[15:12]));
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_2 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[11:8]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[11:8]));
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_1 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[7:4]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[7:4]));
RAM_ice40_1k_4bit RAM_ice40_1k_4bit_0 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[3:0]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[3:0]));
endmodule | 2 |
5,959 | data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v | 115,035,459 | mza-test040.spi-pollable-memory.v | v | 508 | 247 | [] | [] | [] | null | line:44: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:12: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:452: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:456: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:458: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:463: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:465: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:470: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:472: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:476: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:499: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:503: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n' | 6,788 | module | module RAM_ice40_512_32bit (
input reset,
input write_clock,
input [8:0] write_address,
input [31:0] write_data,
input write_enable,
input read_clock,
input [8:0] read_address,
output [31:0] read_data
);
RAM_ice40_512_8bit RAM_ice40_512_8bit_3 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[31:24]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[31:24]));
RAM_ice40_512_8bit RAM_ice40_512_8bit_2 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[23:16]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[23:16]));
RAM_ice40_512_8bit RAM_ice40_512_8bit_1 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[15:8]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[15:8]));
RAM_ice40_512_8bit RAM_ice40_512_8bit_0 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[7:0]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[7:0]));
endmodule | module RAM_ice40_512_32bit (
input reset,
input write_clock,
input [8:0] write_address,
input [31:0] write_data,
input write_enable,
input read_clock,
input [8:0] read_address,
output [31:0] read_data
); |
RAM_ice40_512_8bit RAM_ice40_512_8bit_3 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[31:24]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[31:24]));
RAM_ice40_512_8bit RAM_ice40_512_8bit_2 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[23:16]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[23:16]));
RAM_ice40_512_8bit RAM_ice40_512_8bit_1 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[15:8]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[15:8]));
RAM_ice40_512_8bit RAM_ice40_512_8bit_0 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[7:0]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[7:0]));
endmodule | 2 |
5,960 | data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v | 115,035,459 | mza-test040.spi-pollable-memory.v | v | 508 | 247 | [] | [] | [] | null | line:44: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:12: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:452: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:456: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:458: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:463: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:465: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:470: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:472: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:476: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:499: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:503: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n' | 6,788 | module | module RAM_ice40_256_32bit (
input reset,
input write_clock,
input [7:0] write_address,
input [31:0] write_data,
input write_enable,
input read_clock,
input [7:0] read_address,
output [31:0] read_data
);
RAM_ice40_256_16bit RAM_ice40_256_16bit_1 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[31:16]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[31:16]));
RAM_ice40_256_16bit RAM_ice40_256_16bit_0 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[15:0]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[15:0]));
endmodule | module RAM_ice40_256_32bit (
input reset,
input write_clock,
input [7:0] write_address,
input [31:0] write_data,
input write_enable,
input read_clock,
input [7:0] read_address,
output [31:0] read_data
); |
RAM_ice40_256_16bit RAM_ice40_256_16bit_1 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[31:16]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[31:16]));
RAM_ice40_256_16bit RAM_ice40_256_16bit_0 (.reset(reset),
.write_clock(write_clock), .write_address(write_address), .write_data(write_data[15:0]), .write_enable(write_enable),
.read_clock(read_clock), .read_address(read_address), .read_data(read_data[15:0]));
endmodule | 2 |
5,961 | data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v | 115,035,459 | mza-test040.spi-pollable-memory.v | v | 508 | 247 | [] | [] | [] | null | line:44: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:12: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:452: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:456: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:458: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:463: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:465: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:470: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:472: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:476: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:499: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:503: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n' | 6,788 | module | module RAM_ice40_256_16bit (
input reset,
input write_clock,
input [7:0] write_address,
input [15:0] write_data,
input write_enable,
input read_clock,
input [7:0] read_address,
output [15:0] read_data
);
wire [10:0] write_address11 = { 3'b000, write_address };
wire [10:0] read_address11 = { 3'b000, read_address };
SB_RAM40_4K #(
.WRITE_MODE(0),
.READ_MODE(0)
) ram40_4k_inst (
.WCLK(write_clock),
.WADDR(write_address11),
.WDATA(write_data),
.WE(write_enable),
.WCLKE(1),
.MASK(16'b0),
.RCLK(read_clock),
.RADDR(read_address11),
.RDATA(read_data),
.RE(1),
.RCLKE(1)
);
endmodule | module RAM_ice40_256_16bit (
input reset,
input write_clock,
input [7:0] write_address,
input [15:0] write_data,
input write_enable,
input read_clock,
input [7:0] read_address,
output [15:0] read_data
); |
wire [10:0] write_address11 = { 3'b000, write_address };
wire [10:0] read_address11 = { 3'b000, read_address };
SB_RAM40_4K #(
.WRITE_MODE(0),
.READ_MODE(0)
) ram40_4k_inst (
.WCLK(write_clock),
.WADDR(write_address11),
.WDATA(write_data),
.WE(write_enable),
.WCLKE(1),
.MASK(16'b0),
.RCLK(read_clock),
.RADDR(read_address11),
.RDATA(read_data),
.RE(1),
.RCLKE(1)
);
endmodule | 2 |
5,962 | data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v | 115,035,459 | mza-test040.spi-pollable-memory.v | v | 508 | 247 | [] | [] | [] | null | line:44: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:12: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:452: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:456: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:458: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:463: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:465: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:470: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:472: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:476: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:499: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:503: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n' | 6,788 | module | module RAM_ice40_512_8bit (
input reset,
input write_clock,
input [8:0] write_address,
input [7:0] write_data,
input write_enable,
input read_clock,
input [8:0] read_address,
output [7:0] read_data
);
wire [10:0] write_address11 = { 2'b00, write_address };
wire [10:0] read_address11 = { 2'b00, read_address };
wire [15:0] write_data16 = { 8'h0, write_data };
wire [15:0] read_data16;
SB_RAM40_4K #(
.WRITE_MODE(1),
.READ_MODE(1)
) ram40_4k_inst (
.WCLK(write_clock),
.WADDR(write_address11),
.WDATA(write_data16),
.WE(write_enable),
.WCLKE(1),
.MASK(16'b0),
.RCLK(read_clock),
.RADDR(read_address11),
.RDATA(read_data16),
.RE(1),
.RCLKE(1)
);
assign read_data = read_data16[7:0];
endmodule | module RAM_ice40_512_8bit (
input reset,
input write_clock,
input [8:0] write_address,
input [7:0] write_data,
input write_enable,
input read_clock,
input [8:0] read_address,
output [7:0] read_data
); |
wire [10:0] write_address11 = { 2'b00, write_address };
wire [10:0] read_address11 = { 2'b00, read_address };
wire [15:0] write_data16 = { 8'h0, write_data };
wire [15:0] read_data16;
SB_RAM40_4K #(
.WRITE_MODE(1),
.READ_MODE(1)
) ram40_4k_inst (
.WCLK(write_clock),
.WADDR(write_address11),
.WDATA(write_data16),
.WE(write_enable),
.WCLKE(1),
.MASK(16'b0),
.RCLK(read_clock),
.RADDR(read_address11),
.RDATA(read_data16),
.RE(1),
.RCLKE(1)
);
assign read_data = read_data16[7:0];
endmodule | 2 |
5,963 | data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v | 115,035,459 | mza-test040.spi-pollable-memory.v | v | 508 | 247 | [] | [] | [] | null | line:44: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:12: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:452: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:456: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:458: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:463: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:465: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:470: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:472: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:476: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:499: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:503: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n' | 6,788 | module | module RAM_ice40_1k_4bit (
input reset,
input write_clock,
input [9:0] write_address,
input [3:0] write_data,
input write_enable,
input read_clock,
input [9:0] read_address,
output [3:0] read_data
);
wire [10:0] write_address11 = { 1'b0, write_address };
wire [10:0] read_address11 = { 1'b0, read_address };
wire [15:0] write_data16 = { 12'h0, write_data };
wire [15:0] read_data16;
SB_RAM40_4K #(
.WRITE_MODE(2),
.READ_MODE(2)
) ram40_1024x4_inst (
.WCLK(write_clock),
.WADDR(write_address11),
.WDATA(write_data16),
.WE(write_enable),
.WCLKE(1),
.RCLK(read_clock),
.RADDR(read_address11),
.RDATA(read_data16),
.RE(1),
.RCLKE(1)
);
assign read_data = read_data16[3:0];
endmodule | module RAM_ice40_1k_4bit (
input reset,
input write_clock,
input [9:0] write_address,
input [3:0] write_data,
input write_enable,
input read_clock,
input [9:0] read_address,
output [3:0] read_data
); |
wire [10:0] write_address11 = { 1'b0, write_address };
wire [10:0] read_address11 = { 1'b0, read_address };
wire [15:0] write_data16 = { 12'h0, write_data };
wire [15:0] read_data16;
SB_RAM40_4K #(
.WRITE_MODE(2),
.READ_MODE(2)
) ram40_1024x4_inst (
.WCLK(write_clock),
.WADDR(write_address11),
.WDATA(write_data16),
.WE(write_enable),
.WCLKE(1),
.RCLK(read_clock),
.RADDR(read_address11),
.RDATA(read_data16),
.RE(1),
.RCLKE(1)
);
assign read_data = read_data16[3:0];
endmodule | 2 |
5,964 | data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v | 115,035,459 | mza-test040.spi-pollable-memory.v | v | 508 | 247 | [] | [] | [] | null | line:44: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:12: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:452: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:456: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:458: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:463: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:465: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:470: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:472: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:476: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:499: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:503: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n' | 6,788 | module | module RAM_ice40_2k_2bit (
input reset,
input write_clock,
input [10:0] write_address,
input [1:0] write_data,
input write_enable,
input read_clock,
input [10:0] read_address,
output [1:0] read_data
);
wire [15:0] write_data16 = { 14'h0, write_data };
wire [15:0] read_data16;
SB_RAM40_4K #(
.WRITE_MODE(3),
.READ_MODE(3)
) ram40_1024x4_inst (
.WCLK(write_clock),
.WADDR(write_address),
.WDATA(write_data16),
.WE(write_enable),
.WCLKE(1),
.RCLK(read_clock),
.RADDR(read_address),
.RDATA(read_data16),
.RE(1),
.RCLKE(1)
);
assign read_data = read_data16[1:0];
endmodule | module RAM_ice40_2k_2bit (
input reset,
input write_clock,
input [10:0] write_address,
input [1:0] write_data,
input write_enable,
input read_clock,
input [10:0] read_address,
output [1:0] read_data
); |
wire [15:0] write_data16 = { 14'h0, write_data };
wire [15:0] read_data16;
SB_RAM40_4K #(
.WRITE_MODE(3),
.READ_MODE(3)
) ram40_1024x4_inst (
.WCLK(write_clock),
.WADDR(write_address),
.WDATA(write_data16),
.WE(write_enable),
.WCLKE(1),
.RCLK(read_clock),
.RADDR(read_address),
.RDATA(read_data16),
.RE(1),
.RCLKE(1)
);
assign read_data = read_data16[1:0];
endmodule | 2 |
5,965 | data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v | 115,035,459 | mza-test040.spi-pollable-memory.v | v | 508 | 247 | [] | [] | [] | null | line:44: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:12: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:452: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:456: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:458: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:463: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:465: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:470: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:472: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:476: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:499: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:503: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n' | 6,788 | module | module RAM_inferred #(
parameter addr_width = 9,
parameter data_width = 8
) (
input reset,
input [addr_width-1:0] waddr, raddr,
input [data_width-1:0] din,
input write_en, wclk, rclk,
output reg [data_width-1:0] dout = 0
);
reg [data_width-1:0] mem [(1<<addr_width)-1:0];
always @(posedge wclk) begin
if (reset) begin
end else begin
if (write_en) begin
mem[waddr] <= din;
end
end
end
always @(posedge rclk) begin
if (~reset) begin
dout <= mem[raddr];
end
end
endmodule | module RAM_inferred #(
parameter addr_width = 9,
parameter data_width = 8
) (
input reset,
input [addr_width-1:0] waddr, raddr,
input [data_width-1:0] din,
input write_en, wclk, rclk,
output reg [data_width-1:0] dout = 0
); |
reg [data_width-1:0] mem [(1<<addr_width)-1:0];
always @(posedge wclk) begin
if (reset) begin
end else begin
if (write_en) begin
mem[waddr] <= din;
end
end
end
always @(posedge rclk) begin
if (~reset) begin
dout <= mem[raddr];
end
end
endmodule | 2 |
5,966 | data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v | 115,035,459 | mza-test040.spi-pollable-memory.v | v | 508 | 247 | [] | [] | [] | null | line:44: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:12: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:452: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:456: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:458: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:463: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:465: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:470: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:472: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:476: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:499: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:503: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n' | 6,788 | module | module top (
input clock100,
input rpi_spi_sclk,
input rpi_spi_mosi,
output rpi_spi_miso,
input rpi_spi_ce0,
input rpi_spi_ce1,
output pmod4_5,
output pmod4_6,
output pmod4_7,
output pmod4_8,
output led1,
output led2,
output led3
);
reg reset1 = 1;
wire clock_ram;
wire clock_spi;
`ifdef USE_SLOW_CLOCK
wire clock16;
reg reset2 = 1;
wire pll_locked;
easypll #(.DIVR(4'd3), .DIVF(7'd40), .DIVQ(3'd6)) mp (.clock_input(clock100), .reset_active_low(~reset1), .global_clock_output(clock16), .pll_is_locked(pll_locked));
assign clock_ram = clock16;
assign clock_spi = clock16;
`else
assign clock_ram = clock100;
assign clock_spi = clock100;
`endif
reg [7:0] reset_counter = 0;
always @(posedge clock100) begin
if (reset1) begin
if (reset_counter[7]) begin
reset1 <= 0;
end else begin
reset_counter <= reset_counter + 1'b1;
end
`ifdef USE_SLOW_CLOCK
end else if (reset2) begin
if (pll_locked) begin
reset2 <= 0;
end
`endif
end
end
wire [7:0] command8;
wire [15:0] address16;
wire [31:0] data32;
wire [31:0] read_data32;
wire transaction_valid;
SPI_peripheral_command8_address16_data32 spi_c8_a16_d32 (.clock(clock_spi),
.SCK(rpi_spi_sclk), .MOSI(rpi_spi_mosi), .MISO(rpi_spi_miso), .SSEL(rpi_spi_ce1),
.transaction_valid(transaction_valid), .command8(command8), .address16(address16), .data32(data32), .data32_to_controller(read_data32));
`ifdef USE_INFERRED_RAM_16
wire [3:0] address4 = address16[3:0];
RAM_inferred #(.addr_width(4), .data_width(32)) myram (.reset(reset1),
.wclk(clock_ram), .waddr(address4), .din(data32), .write_en(transaction_valid),
.rclk(clock_ram), .raddr(address4), .dout(read_data32));
`elsif USE_BRAM_256
wire [7:0] address8 = address16[7:0];
RAM_ice40_256_32bit myram (.reset(reset1),
.write_clock(clock_ram), .write_address(address8), .write_data(data32), .write_enable(transaction_valid),
.read_clock(clock_ram), .read_address(address8), .read_data(read_data32));
`elsif USE_BRAM_512
wire [8:0] address9 = address16[8:0];
RAM_ice40_512_32bit myram (.reset(reset1),
.write_clock(clock_ram), .write_address(address9), .write_data(data32), .write_enable(transaction_valid),
.read_clock(clock_ram), .read_address(address9), .read_data(read_data32));
`elsif USE_BRAM_1K
wire [9:0] address10 = address16[9:0];
RAM_ice40_1k_32bit myram (.reset(reset1),
.write_clock(clock_ram), .write_address(address10), .write_data(data32), .write_enable(transaction_valid),
.read_clock(clock_ram), .read_address(address10), .read_data(read_data32));
`elsif USE_BRAM_2K
wire [10:0] address11 = address16[10:0];
RAM_ice40_2k_32bit myram (.reset(reset1),
.write_clock(clock_ram), .write_address(address11), .write_data(data32), .write_enable(transaction_valid),
.read_clock(clock_ram), .read_address(address11), .read_data(read_data32));
`endif
wire [2:0] leds = { led1, led2, led3 };
assign leds = data32[2:0];
assign pmod4_5 = rpi_spi_sclk;
assign pmod4_6 = rpi_spi_mosi;
assign pmod4_7 = rpi_spi_miso;
assign pmod4_8 = rpi_spi_ce1;
endmodule | module top (
input clock100,
input rpi_spi_sclk,
input rpi_spi_mosi,
output rpi_spi_miso,
input rpi_spi_ce0,
input rpi_spi_ce1,
output pmod4_5,
output pmod4_6,
output pmod4_7,
output pmod4_8,
output led1,
output led2,
output led3
); |
reg reset1 = 1;
wire clock_ram;
wire clock_spi;
`ifdef USE_SLOW_CLOCK
wire clock16;
reg reset2 = 1;
wire pll_locked;
easypll #(.DIVR(4'd3), .DIVF(7'd40), .DIVQ(3'd6)) mp (.clock_input(clock100), .reset_active_low(~reset1), .global_clock_output(clock16), .pll_is_locked(pll_locked));
assign clock_ram = clock16;
assign clock_spi = clock16;
`else
assign clock_ram = clock100;
assign clock_spi = clock100;
`endif
reg [7:0] reset_counter = 0;
always @(posedge clock100) begin
if (reset1) begin
if (reset_counter[7]) begin
reset1 <= 0;
end else begin
reset_counter <= reset_counter + 1'b1;
end
`ifdef USE_SLOW_CLOCK
end else if (reset2) begin
if (pll_locked) begin
reset2 <= 0;
end
`endif
end
end
wire [7:0] command8;
wire [15:0] address16;
wire [31:0] data32;
wire [31:0] read_data32;
wire transaction_valid;
SPI_peripheral_command8_address16_data32 spi_c8_a16_d32 (.clock(clock_spi),
.SCK(rpi_spi_sclk), .MOSI(rpi_spi_mosi), .MISO(rpi_spi_miso), .SSEL(rpi_spi_ce1),
.transaction_valid(transaction_valid), .command8(command8), .address16(address16), .data32(data32), .data32_to_controller(read_data32));
`ifdef USE_INFERRED_RAM_16
wire [3:0] address4 = address16[3:0];
RAM_inferred #(.addr_width(4), .data_width(32)) myram (.reset(reset1),
.wclk(clock_ram), .waddr(address4), .din(data32), .write_en(transaction_valid),
.rclk(clock_ram), .raddr(address4), .dout(read_data32));
`elsif USE_BRAM_256
wire [7:0] address8 = address16[7:0];
RAM_ice40_256_32bit myram (.reset(reset1),
.write_clock(clock_ram), .write_address(address8), .write_data(data32), .write_enable(transaction_valid),
.read_clock(clock_ram), .read_address(address8), .read_data(read_data32));
`elsif USE_BRAM_512
wire [8:0] address9 = address16[8:0];
RAM_ice40_512_32bit myram (.reset(reset1),
.write_clock(clock_ram), .write_address(address9), .write_data(data32), .write_enable(transaction_valid),
.read_clock(clock_ram), .read_address(address9), .read_data(read_data32));
`elsif USE_BRAM_1K
wire [9:0] address10 = address16[9:0];
RAM_ice40_1k_32bit myram (.reset(reset1),
.write_clock(clock_ram), .write_address(address10), .write_data(data32), .write_enable(transaction_valid),
.read_clock(clock_ram), .read_address(address10), .read_data(read_data32));
`elsif USE_BRAM_2K
wire [10:0] address11 = address16[10:0];
RAM_ice40_2k_32bit myram (.reset(reset1),
.write_clock(clock_ram), .write_address(address11), .write_data(data32), .write_enable(transaction_valid),
.read_clock(clock_ram), .read_address(address11), .read_data(read_data32));
`endif
wire [2:0] leds = { led1, led2, led3 };
assign leds = data32[2:0];
assign pmod4_5 = rpi_spi_sclk;
assign pmod4_6 = rpi_spi_mosi;
assign pmod4_7 = rpi_spi_miso;
assign pmod4_8 = rpi_spi_ce1;
endmodule | 2 |
5,967 | data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v | 115,035,459 | mza-test040.spi-pollable-memory.v | v | 508 | 247 | [] | [] | [] | null | line:44: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:12: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:452: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:456: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:458: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:463: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:465: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:470: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:472: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:476: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:499: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:503: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n' | 6,788 | module | module top_tb;
reg SCK = 0;
reg MOSI = 0;
reg SSEL = 1;
reg [7:0] i = 0;
reg [7:0] j = 0;
task automatic spi_c8_a16_d32_controller_transaction;
input [7:0] command8;
input [15:0] address16;
input [31:0] data32;
begin
#300;
SSEL <= 0;
for (i=8; i>0; i=i-1) begin : command
MOSI <= command8[i-1];
#100;
SCK <= 1;
#100;
SCK <= 0;
end
for (i=16; i>0; i=i-1) begin : address
MOSI <= address16[i-1];
#100;
SCK <= 1;
#100;
SCK <= 0;
end
for (i=32; i>0; i=i-1) begin : data
MOSI <= data32[i-1];
#100;
SCK <= 1;
#100;
SCK <= 0;
end
MOSI <= 0;
#100;
SSEL <= 1;
end
endtask
reg clock100 = 0;
reg rpi_spi_ce0 = 1;
wire MISO;
wire led1, led2, led3;
top mytop (.clock100(clock100), .rpi_spi_sclk(SCK), .rpi_spi_mosi(MOSI), .rpi_spi_miso(MISO), .rpi_spi_ce0(rpi_spi_ce0), .rpi_spi_ce1(SSEL), .led1(led1), .led2(led2), .led3(led3));
initial begin
SCK <= 0;
MOSI <= 0;
SSEL <= 1;
spi_c8_a16_d32_controller_transaction(8'h01, 16'h0001, 32'h01234567);
spi_c8_a16_d32_controller_transaction(8'h01, 16'h0001, 32'h01234567);
spi_c8_a16_d32_controller_transaction(8'h01, 16'h0101, 32'h89abcdef);
spi_c8_a16_d32_controller_transaction(8'h01, 16'h0101, 32'h89abcdef);
spi_c8_a16_d32_controller_transaction(8'h01, 16'h0001, 32'h01234567);
#200;
end
always begin
#10;
clock100 <= ~clock100;
end
endmodule | module top_tb; |
reg SCK = 0;
reg MOSI = 0;
reg SSEL = 1;
reg [7:0] i = 0;
reg [7:0] j = 0;
task automatic spi_c8_a16_d32_controller_transaction;
input [7:0] command8;
input [15:0] address16;
input [31:0] data32;
begin
#300;
SSEL <= 0;
for (i=8; i>0; i=i-1) begin : command
MOSI <= command8[i-1];
#100;
SCK <= 1;
#100;
SCK <= 0;
end
for (i=16; i>0; i=i-1) begin : address
MOSI <= address16[i-1];
#100;
SCK <= 1;
#100;
SCK <= 0;
end
for (i=32; i>0; i=i-1) begin : data
MOSI <= data32[i-1];
#100;
SCK <= 1;
#100;
SCK <= 0;
end
MOSI <= 0;
#100;
SSEL <= 1;
end
endtask
reg clock100 = 0;
reg rpi_spi_ce0 = 1;
wire MISO;
wire led1, led2, led3;
top mytop (.clock100(clock100), .rpi_spi_sclk(SCK), .rpi_spi_mosi(MOSI), .rpi_spi_miso(MISO), .rpi_spi_ce0(rpi_spi_ce0), .rpi_spi_ce1(SSEL), .led1(led1), .led2(led2), .led3(led3));
initial begin
SCK <= 0;
MOSI <= 0;
SSEL <= 1;
spi_c8_a16_d32_controller_transaction(8'h01, 16'h0001, 32'h01234567);
spi_c8_a16_d32_controller_transaction(8'h01, 16'h0001, 32'h01234567);
spi_c8_a16_d32_controller_transaction(8'h01, 16'h0101, 32'h89abcdef);
spi_c8_a16_d32_controller_transaction(8'h01, 16'h0101, 32'h89abcdef);
spi_c8_a16_d32_controller_transaction(8'h01, 16'h0001, 32'h01234567);
#200;
end
always begin
#10;
clock100 <= ~clock100;
end
endmodule | 2 |
5,968 | data/full_repos/permissive/115035459/verilog/src/mza-test041.spi-pollable-memory.althea.revA.v | 115,035,459 | mza-test041.spi-pollable-memory.althea.revA.v | v | 134 | 266 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test041.spi-pollable-memory.althea.revA.v:5: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test041.spi-pollable-memory.althea.revA.v:6: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test041.spi-pollable-memory.althea.revA.v:7: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test041.spi-pollable-memory.althea.revA.v:8: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 6,789 | module | module top (
input clock50_p, clock50_n,
output lemo,
input rpi_spi_sclk,
input rpi_spi_mosi,
output rpi_spi_miso,
input rpi_spi_ce0,
input rpi_spi_ce1,
output led_0, led_1, led_2, led_3,
output led_4, led_5, led_6, led_7
);
reg reset1 = 1;
reg reset2 = 1;
reg reset3 = 1;
wire clock50;
IBUFGDS mybuf (.I(clock50_p), .IB(clock50_n), .O(clock50));
wire rawclock125;
wire pll_locked;
simplepll_BASE #(.OVERALL_DIVIDE(1), .MULTIPLY(10), .DIVIDE0(4), .PHASE0(0.0), .PERIOD(20.0)) kronos (.clockin(clock50), .reset(reset1), .clock0out(rawclock125), .clock1out(), .clock2out(), .clock3out(), .clock4out(), .clock5out(), .locked(pll_locked));
wire clock125;
BUFG mrt (.I(rawclock125), .O(clock125));
wire word_clock;
wire [7:0] oserdes_word_out;
wire pll_oserdes_locked;
wire clock_ram;
wire clock_spi;
assign clock_ram = word_clock;
assign clock_spi = word_clock;
reg [7:0] reset_counter = 0;
always @(posedge clock50) begin
if (reset1) begin
if (reset_counter[7]) begin
reset1 <= 0;
end else begin
reset_counter <= reset_counter + 1'b1;
end
end else if (reset2) begin
if (pll_locked) begin
reset2 <= 0;
end
end else if (reset3) begin
if (pll_oserdes_locked) begin
reset3 <= 0;
end
end
end
wire [7:0] command8;
wire [15:0] address16;
wire [31:0] data32_0123;
wire [31:0] data32_3210;
assign data32_0123[7:0] = data32_3210[31:24];
assign data32_0123[15:8] = data32_3210[23:16];
assign data32_0123[23:16] = data32_3210[15:8];
assign data32_0123[31:24] = data32_3210[7:0];
wire [31:0] read_data32_0123;
wire [31:0] read_data32_3210;
assign read_data32_3210[7:0] = read_data32_0123[31:24];
assign read_data32_3210[15:8] = read_data32_0123[23:16];
assign read_data32_3210[23:16] = read_data32_0123[15:8];
assign read_data32_3210[31:24] = read_data32_0123[7:0];
wire transaction_valid;
SPI_peripheral_command8_address16_data32 spi_c8_a16_d32 (.clock(clock_spi),
.SCK(rpi_spi_sclk), .MOSI(rpi_spi_mosi), .MISO(rpi_spi_miso), .SSEL(rpi_spi_ce1),
.transaction_valid(transaction_valid), .command8(command8), .address16(address16), .data32(data32_3210), .data32_to_controller(read_data32_3210));
`ifdef USE_INFERRED_RAM_16
wire [3:0] address4 = address16[3:0];
RAM_inferred #(.addr_width(4), .data_width(32)) myram (.reset(reset3),
.wclk(clock_ram), .waddr(address4), .din(data32_0123), .write_en(transaction_valid),
.rclk(clock_ram), .raddr(address4), .dout(read_data32_0123));
`elsif USE_BRAM_512
wire [8:0] address9 = address16[8:0];
wire [10:0] read_address11 = read_address[10:0];
RAM_s6_512_32bit_8bit mem (.reset(reset3),
.clock_a(clock_ram), .address_a(address9), .data_in_a(data32_0123), .write_enable_a(transaction_valid), .data_out_a(read_data32_0123),
.clock_b(clock_ram), .address_b(read_address11), .data_out_b(oserdes_word_out));
`elsif USE_BRAM_4K
wire [11:0] address12 = address16[11:0];
wire [13:0] read_address14 = read_address[13:0];
RAM_s6_4k_32bit_8bit mem (.reset(reset3),
.clock_a(clock_ram), .address_a(address12), .data_in_a(data32_0123), .write_enable_a(transaction_valid), .data_out_a(read_data32_0123),
.clock_b(clock_ram), .address_b(read_address14), .data_out_b(oserdes_word_out));
`endif
reg [15:0] read_address = 0;
wire [7:0] leds;
assign { led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0 } = leds;
assign leds = oserdes_word_out;
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei (.clock_in(clock125), .reset(reset2), .word_clock_out(word_clock), .word_in(oserdes_word_out), .D_out(lemo), .locked(pll_oserdes_locked));
always @(posedge word_clock) begin
if (reset3) begin
read_address <= 0;
end else begin
read_address <= read_address + 1'b1;
end
end
endmodule | module top (
input clock50_p, clock50_n,
output lemo,
input rpi_spi_sclk,
input rpi_spi_mosi,
output rpi_spi_miso,
input rpi_spi_ce0,
input rpi_spi_ce1,
output led_0, led_1, led_2, led_3,
output led_4, led_5, led_6, led_7
); |
reg reset1 = 1;
reg reset2 = 1;
reg reset3 = 1;
wire clock50;
IBUFGDS mybuf (.I(clock50_p), .IB(clock50_n), .O(clock50));
wire rawclock125;
wire pll_locked;
simplepll_BASE #(.OVERALL_DIVIDE(1), .MULTIPLY(10), .DIVIDE0(4), .PHASE0(0.0), .PERIOD(20.0)) kronos (.clockin(clock50), .reset(reset1), .clock0out(rawclock125), .clock1out(), .clock2out(), .clock3out(), .clock4out(), .clock5out(), .locked(pll_locked));
wire clock125;
BUFG mrt (.I(rawclock125), .O(clock125));
wire word_clock;
wire [7:0] oserdes_word_out;
wire pll_oserdes_locked;
wire clock_ram;
wire clock_spi;
assign clock_ram = word_clock;
assign clock_spi = word_clock;
reg [7:0] reset_counter = 0;
always @(posedge clock50) begin
if (reset1) begin
if (reset_counter[7]) begin
reset1 <= 0;
end else begin
reset_counter <= reset_counter + 1'b1;
end
end else if (reset2) begin
if (pll_locked) begin
reset2 <= 0;
end
end else if (reset3) begin
if (pll_oserdes_locked) begin
reset3 <= 0;
end
end
end
wire [7:0] command8;
wire [15:0] address16;
wire [31:0] data32_0123;
wire [31:0] data32_3210;
assign data32_0123[7:0] = data32_3210[31:24];
assign data32_0123[15:8] = data32_3210[23:16];
assign data32_0123[23:16] = data32_3210[15:8];
assign data32_0123[31:24] = data32_3210[7:0];
wire [31:0] read_data32_0123;
wire [31:0] read_data32_3210;
assign read_data32_3210[7:0] = read_data32_0123[31:24];
assign read_data32_3210[15:8] = read_data32_0123[23:16];
assign read_data32_3210[23:16] = read_data32_0123[15:8];
assign read_data32_3210[31:24] = read_data32_0123[7:0];
wire transaction_valid;
SPI_peripheral_command8_address16_data32 spi_c8_a16_d32 (.clock(clock_spi),
.SCK(rpi_spi_sclk), .MOSI(rpi_spi_mosi), .MISO(rpi_spi_miso), .SSEL(rpi_spi_ce1),
.transaction_valid(transaction_valid), .command8(command8), .address16(address16), .data32(data32_3210), .data32_to_controller(read_data32_3210));
`ifdef USE_INFERRED_RAM_16
wire [3:0] address4 = address16[3:0];
RAM_inferred #(.addr_width(4), .data_width(32)) myram (.reset(reset3),
.wclk(clock_ram), .waddr(address4), .din(data32_0123), .write_en(transaction_valid),
.rclk(clock_ram), .raddr(address4), .dout(read_data32_0123));
`elsif USE_BRAM_512
wire [8:0] address9 = address16[8:0];
wire [10:0] read_address11 = read_address[10:0];
RAM_s6_512_32bit_8bit mem (.reset(reset3),
.clock_a(clock_ram), .address_a(address9), .data_in_a(data32_0123), .write_enable_a(transaction_valid), .data_out_a(read_data32_0123),
.clock_b(clock_ram), .address_b(read_address11), .data_out_b(oserdes_word_out));
`elsif USE_BRAM_4K
wire [11:0] address12 = address16[11:0];
wire [13:0] read_address14 = read_address[13:0];
RAM_s6_4k_32bit_8bit mem (.reset(reset3),
.clock_a(clock_ram), .address_a(address12), .data_in_a(data32_0123), .write_enable_a(transaction_valid), .data_out_a(read_data32_0123),
.clock_b(clock_ram), .address_b(read_address14), .data_out_b(oserdes_word_out));
`endif
reg [15:0] read_address = 0;
wire [7:0] leds;
assign { led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0 } = leds;
assign leds = oserdes_word_out;
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei (.clock_in(clock125), .reset(reset2), .word_clock_out(word_clock), .word_in(oserdes_word_out), .D_out(lemo), .locked(pll_oserdes_locked));
always @(posedge word_clock) begin
if (reset3) begin
read_address <= 0;
end else begin
read_address <= read_address + 1'b1;
end
end
endmodule | 2 |
5,969 | data/full_repos/permissive/115035459/verilog/src/mza-test041.spi-pollable-memory.althea.revA.v | 115,035,459 | mza-test041.spi-pollable-memory.althea.revA.v | v | 134 | 266 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test041.spi-pollable-memory.althea.revA.v:5: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test041.spi-pollable-memory.althea.revA.v:6: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test041.spi-pollable-memory.althea.revA.v:7: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test041.spi-pollable-memory.althea.revA.v:8: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 6,789 | module | module mza_test041_spi_pollable_memory_althea_top (
input clock50_p, clock50_n,
output lemo,
input a_p,
input c_n,
input c_p,
output d_n,
input d_p,
output led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
);
top mytop (
.clock50_p(clock50_p), .clock50_n(clock50_n),
.lemo(lemo),
.rpi_spi_mosi(d_p), .rpi_spi_miso(d_n), .rpi_spi_sclk(c_p), .rpi_spi_ce0(c_n), .rpi_spi_ce1(a_p),
.led_0(led_0), .led_1(led_1), .led_2(led_2), .led_3(led_3),
.led_4(led_4), .led_5(led_5), .led_6(led_6), .led_7(led_7)
);
endmodule | module mza_test041_spi_pollable_memory_althea_top (
input clock50_p, clock50_n,
output lemo,
input a_p,
input c_n,
input c_p,
output d_n,
input d_p,
output led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
); |
top mytop (
.clock50_p(clock50_p), .clock50_n(clock50_n),
.lemo(lemo),
.rpi_spi_mosi(d_p), .rpi_spi_miso(d_n), .rpi_spi_sclk(c_p), .rpi_spi_ce0(c_n), .rpi_spi_ce1(a_p),
.led_0(led_0), .led_1(led_1), .led_2(led_2), .led_3(led_3),
.led_4(led_4), .led_5(led_5), .led_6(led_6), .led_7(led_7)
);
endmodule | 2 |
5,970 | data/full_repos/permissive/115035459/verilog/src/mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v | 115,035,459 | mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v | v | 298 | 349 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v:6: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v:7: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v:8: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v:9: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v:10: Cannot find include file: lib/reset.v\n`include "lib/reset.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v:11: Cannot find include file: lib/frequency_counter.v\n`include "lib/frequency_counter.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n' | 6,790 | module | module top (
input clock50_p, clock50_n,
output lemo,
output other0,
output other1,
input rpi_spi_sclk,
input rpi_spi_mosi,
output rpi_spi_miso,
input rpi_spi_ce0,
input rpi_spi_ce1,
output rpi_gpio5,
input rpi_gpio6_gpclk2,
input rpi_gpio13,
input rpi_gpio19,
output led_0, led_1, led_2, led_3,
output led_4, led_5, led_6, led_7
);
localparam COUNTER_RO_PICKOFF = 23;
wire [31:0] frequency_counter0;
reg [31:0] frequency_counter1;
wire global_reset = rpi_gpio19;
wire clock_alt;
IBUFG mybuf_alt (.I(rpi_gpio6_gpclk2), .O(clock_alt));
wire reset1_clock_alt;
wire pll_locked_alt;
reset #(.FREQUENCY(10000000)) reset1 (.upstream_clock(clock_alt), .upstream_reset(global_reset), .downstream_pll_locked(pll_locked_alt), .downstream_reset(reset1_clock_alt));
wire clock_ro_raw, clock_ro_raw_a, clock_ro_raw_b, clock_ro, clock_ro_b, clock_ro_locked;
wire [31:0] ring_oscillator_select;
wire [31:0] ring_oscillator_enable;
ring_oscillator #(.number_of_bits_for_coarse_stages(4), .number_of_bits_for_medium_stages(4), .number_of_bits_for_fine_stages(4)) ro (.enable(ring_oscillator_enable[0]), .select(ring_oscillator_select[11:0]), .clock_out(clock_ro_raw));
simpledcm_CLKGEN #(.MULTIPLY(50), .DIVIDE(50), .PERIOD(100.0)) mydcm_ro (.clockin(clock_ro_raw), .reset(global_reset || (~ring_oscillator_enable[0])), .clockout(clock_ro_raw_a), .clockout180(clock_ro_raw_b), .locked(clock_ro_locked));
BUFG mybuf_roa (.I(clock_ro_raw_a), .O(clock_ro));
BUFG mybuf_rob (.I(clock_ro_raw_b), .O(clock_ro_b));
reg [COUNTER_RO_PICKOFF:0] counter_ro = 0;
always @(posedge clock_ro) begin
counter_ro <= counter_ro + 1'b1;
end
ODDR2 ro_out (.C0(clock_ro), .C1(clock_ro_b), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(global_reset), .S(1'b0), .Q(lemo));
wire clock50_0, clock50_1, clock50_12;
IBUFGDS mybuf0 (.I(clock50_p), .IB(clock50_n), .O(clock50_0));
wire clock50_raw1;
simpledcm_CLKGEN #(.MULTIPLY(50), .DIVIDE(10), .PERIOD(100.0)) mydcm_alt50 (.clockin(clock_alt), .reset(reset1_clock_alt), .clockout(clock50_raw1), .clockout180(), .locked(pll_locked_alt));
BUFG mybuf1 (.I(clock50_raw1), .O(clock50_1));
assign clock50_12 = clock50_1;
wire clock_select = rpi_gpio13;
wire clock50;
BUFGMUX sam0s (.I0(clock50_0), .I1(clock50_12), .S(clock_select), .O(clock50));
wire reset2_clock50;
wire pll_locked;
reset #(.FREQUENCY(50000000)) reset2 (.upstream_clock(clock50), .upstream_reset(global_reset||reset1_clock_alt), .downstream_pll_locked(pll_locked), .downstream_reset(reset2_clock50));
wire rawclock125;
wire clock125;
BUFG mrt (.I(rawclock125), .O(clock125));
if (0) begin
simplepll_BASE #(.OVERALL_DIVIDE(1), .MULTIPLY(10), .DIVIDE0(4), .PHASE0(0.0), .PERIOD(20.0)) kronos (.clockin(clock50), .reset(reset2_clock50), .clock0out(rawclock125), .clock1out(), .clock2out(), .clock3out(), .clock4out(), .clock5out(), .locked(pll_locked));
end else if (0) begin
simpledcm_SP #(.MULTIPLY(10), .DIVIDE(4), .ALT_CLOCKOUT_DIVIDE(2), .PERIOD(20.0)) mydcm (.clockin(clock50), .reset(reset2_clock50), .clockout(rawclock125), .clockout180(), .alt_clockout(), .locked(pll_locked));
end else begin
simpledcm_CLKGEN #(.MULTIPLY(10), .DIVIDE(4), .PERIOD(20.0)) mydcm_125 (.clockin(clock50), .reset(reset2_clock50), .clockout(rawclock125), .clockout180(), .locked(pll_locked));
end
wire reset3_clock125;
wire pll_oserdes_locked;
reset #(.FREQUENCY(125000000)) reset3 (.upstream_clock(clock125), .upstream_reset(global_reset||reset2_clock50), .downstream_pll_locked(pll_oserdes_locked), .downstream_reset(reset3_clock125));
wire word_clock;
wire clock_spi;
assign clock_spi = word_clock;
wire reset4_word_clock;
reset #(.FREQUENCY(125000000)) reset4 (.upstream_clock(word_clock), .upstream_reset(global_reset||reset3_clock125), .downstream_pll_locked(pll_oserdes_locked), .downstream_reset(reset4_word_clock));
reg sync_read_address = 0;
reg [15:0] read_address = 0;
wire [31:0] start_read_address;
wire [31:0] end_read_address;
reg [15:0] last_read_address = 16'd4095;
wire miso_ce0;
wire miso_ce1;
assign rpi_spi_miso = rpi_spi_ce0 ? miso_ce1 : miso_ce0;
wire [7:0] command8_ce0;
wire [15:0] address16_ce0;
wire [31:0] data32_ce0;
wire [31:0] read_data32_ce0;
wire transaction_valid_ce0;
SPI_peripheral_command8_address16_data32 spi_ce0 (.clock(clock_spi),
.SCK(rpi_spi_sclk), .MOSI(rpi_spi_mosi), .MISO(miso_ce0), .SSEL(rpi_spi_ce0),
.transaction_valid(transaction_valid_ce0), .command8(command8_ce0), .address16(address16_ce0), .data32(data32_ce0), .data32_to_controller(read_data32_ce0));
wire [3:0] address4_ce0 = address16_ce0[3:0];
RAM_inferred_with_register_outputs_and_inputs #(.addr_width(4), .data_width(32)) myram (.reset(reset4_word_clock),
.wclk(clock_spi), .waddr(address4_ce0), .din(data32_ce0), .write_en(transaction_valid_ce0),
.rclk(word_clock), .raddr(address4_ce0), .dout(read_data32_ce0),
.register0(start_read_address), .register1(end_read_address), .register2(ring_oscillator_enable), .register3(ring_oscillator_select),
.registerC(32'd0), .registerD(32'd0), .registerE(32'd0), .registerF(frequency_counter1));
always @(posedge word_clock) begin
frequency_counter1 <= frequency_counter0;
end
wire [7:0] command8;
wire [15:0] address16;
wire [31:0] data32_0123;
wire [31:0] data32_3210;
assign data32_0123[7:0] = data32_3210[31:24];
assign data32_0123[15:8] = data32_3210[23:16];
assign data32_0123[23:16] = data32_3210[15:8];
assign data32_0123[31:24] = data32_3210[7:0];
wire [31:0] read_data32_0123;
wire [31:0] read_data32_3210;
assign read_data32_3210[7:0] = read_data32_0123[31:24];
assign read_data32_3210[15:8] = read_data32_0123[23:16];
assign read_data32_3210[23:16] = read_data32_0123[15:8];
assign read_data32_3210[31:24] = read_data32_0123[7:0];
wire transaction_valid_ce1;
SPI_peripheral_command8_address16_data32 spi_ce1 (.clock(clock_spi),
.SCK(rpi_spi_sclk), .MOSI(rpi_spi_mosi), .MISO(miso_ce1), .SSEL(rpi_spi_ce1),
.transaction_valid(transaction_valid_ce1), .command8(command8), .address16(address16), .data32(data32_3210), .data32_to_controller(read_data32_3210));
wire [7:0] oserdes_word_out;
`ifdef USE_BRAM_512
wire [8:0] address9 = address16[8:0];
wire [10:0] read_address11 = read_address[10:0];
RAM_s6_512_32bit_8bit mem (.reset(reset4_word_clock),
.clock_a(clock_spi), .address_a(address9), .data_in_a(data32_0123), .write_enable_a(transaction_valid_ce1), .data_out_a(read_data32_0123),
.clock_b(word_clock), .address_b(read_address11), .data_out_b(oserdes_word_out));
`elsif USE_BRAM_4K
wire [11:0] address12 = address16[11:0];
wire [13:0] read_address14 = read_address[13:0];
RAM_s6_4k_32bit_8bit mem (.reset(reset4_word_clock),
.clock_a(clock_spi), .address_a(address12), .data_in_a(data32_0123), .write_enable_a(transaction_valid_ce1), .data_out_a(read_data32_0123),
.clock_b(word_clock), .address_b(read_address14), .data_out_b(oserdes_word_out));
`endif
reg sync_out_raw = 0;
reg [3:0] sync_out_stream = 0;
always @(posedge word_clock) begin
sync_out_raw <= 0;
if (reset4_word_clock) begin
read_address <= start_read_address[17:2];
last_read_address <= end_read_address[17:2] - 1'b1;
end else begin
if (read_address==last_read_address || sync_read_address) begin
read_address <= start_read_address[17:2];
last_read_address <= end_read_address[17:2] - 1'b1;
sync_out_raw <= 1;
end else begin
read_address <= read_address + 1'b1;
end
end
sync_out_stream <= { sync_out_stream[2:0], sync_out_raw };
end
wire bit_clock;
wire bit_strobe;
wire other1_raw;
if (0) begin
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei (.clock_in(clock125), .reset(reset3_clock125), .word_clock_out(word_clock), .word_in(oserdes_word_out), .D_out(lemo), .locked(pll_oserdes_locked));
assign other0 = 0;
assign other1 = sync_out_stream[2];
end else if (0) begin
wire pll_oserdes_locked_1;
wire pll_oserdes_locked_2;
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei0 (.clock_in(clock125), .reset(reset3_clock125), .word_clock_out(word_clock), .word_in(oserdes_word_out), .D_out(lemo), .locked(pll_oserdes_locked_1));
wire word_clock_1;
reg [7:0] oserdes_word_out_1 = 0;
reg [7:0] oserdes_word_out_2 = 0;
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei1 (.clock_in(clock125), .reset(reset3_clock125), .word_clock_out(word_clock_1), .word_in(oserdes_word_out_2), .D_out(other0), .locked(pll_oserdes_locked_2));
always @(posedge word_clock_1) begin
oserdes_word_out_1 <= oserdes_word_out;
oserdes_word_out_2 <= oserdes_word_out_1;
end
assign other1 = sync_out_stream[2];
assign pll_oserdes_locked = pll_oserdes_locked_1 && pll_oserdes_locked_2;
end else begin
ocyrus_double8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei2 (.clock_in(clock125), .reset(reset3_clock125), .word_clock_out(word_clock), .word0_in(oserdes_word_out), .word1_in(oserdes_word_out), .D0_out(other0), .D1_out(other1_raw), .locked(pll_oserdes_locked), .bit_clock(bit_clock), .bit_strobe(bit_strobe));
end
if (0) begin
odelay_fixed #(.AMOUNT(0)) twoturntables (.bit_in(other1_raw), .bit_out(other1));
end else if (0) begin
odelay_fixed #(.AMOUNT(255)) andamicrophone (.bit_in(other1_raw), .bit_out(other1));
end else begin
assign other1 = other1_raw;
end
wire not_ready = global_reset || reset1_clock_alt || reset2_clock50 || reset3_clock125 || reset4_word_clock;
assign rpi_gpio5 = ~not_ready;
if (0) begin
wire [7:0] leds;
assign { led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0 } = leds;
assign leds = oserdes_word_out;
end else begin
assign led_7 = reset1_clock_alt;
assign led_6 = reset2_clock50;
assign led_5 = reset3_clock125;
assign led_4 = reset4_word_clock;
assign led_3 = ~clock_ro_locked;
assign led_2 = counter_ro[COUNTER_RO_PICKOFF];
assign led_1 = ~rpi_spi_ce0 || ~rpi_spi_ce1;
assign led_0 = not_ready;
end
localparam N = 10;
wire fc_valid;
frequency_counter #(.FREQUENCY_OF_REFERENCE_CLOCK(125000000), .LOG2_OF_DIVIDE_RATIO(24), .N(N)) fc (.reference_clock(word_clock), .unknown_clock(clock_ro), .frequency_of_unknown_clock(frequency_counter0), .valid(fc_valid));
endmodule | module top (
input clock50_p, clock50_n,
output lemo,
output other0,
output other1,
input rpi_spi_sclk,
input rpi_spi_mosi,
output rpi_spi_miso,
input rpi_spi_ce0,
input rpi_spi_ce1,
output rpi_gpio5,
input rpi_gpio6_gpclk2,
input rpi_gpio13,
input rpi_gpio19,
output led_0, led_1, led_2, led_3,
output led_4, led_5, led_6, led_7
); |
localparam COUNTER_RO_PICKOFF = 23;
wire [31:0] frequency_counter0;
reg [31:0] frequency_counter1;
wire global_reset = rpi_gpio19;
wire clock_alt;
IBUFG mybuf_alt (.I(rpi_gpio6_gpclk2), .O(clock_alt));
wire reset1_clock_alt;
wire pll_locked_alt;
reset #(.FREQUENCY(10000000)) reset1 (.upstream_clock(clock_alt), .upstream_reset(global_reset), .downstream_pll_locked(pll_locked_alt), .downstream_reset(reset1_clock_alt));
wire clock_ro_raw, clock_ro_raw_a, clock_ro_raw_b, clock_ro, clock_ro_b, clock_ro_locked;
wire [31:0] ring_oscillator_select;
wire [31:0] ring_oscillator_enable;
ring_oscillator #(.number_of_bits_for_coarse_stages(4), .number_of_bits_for_medium_stages(4), .number_of_bits_for_fine_stages(4)) ro (.enable(ring_oscillator_enable[0]), .select(ring_oscillator_select[11:0]), .clock_out(clock_ro_raw));
simpledcm_CLKGEN #(.MULTIPLY(50), .DIVIDE(50), .PERIOD(100.0)) mydcm_ro (.clockin(clock_ro_raw), .reset(global_reset || (~ring_oscillator_enable[0])), .clockout(clock_ro_raw_a), .clockout180(clock_ro_raw_b), .locked(clock_ro_locked));
BUFG mybuf_roa (.I(clock_ro_raw_a), .O(clock_ro));
BUFG mybuf_rob (.I(clock_ro_raw_b), .O(clock_ro_b));
reg [COUNTER_RO_PICKOFF:0] counter_ro = 0;
always @(posedge clock_ro) begin
counter_ro <= counter_ro + 1'b1;
end
ODDR2 ro_out (.C0(clock_ro), .C1(clock_ro_b), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(global_reset), .S(1'b0), .Q(lemo));
wire clock50_0, clock50_1, clock50_12;
IBUFGDS mybuf0 (.I(clock50_p), .IB(clock50_n), .O(clock50_0));
wire clock50_raw1;
simpledcm_CLKGEN #(.MULTIPLY(50), .DIVIDE(10), .PERIOD(100.0)) mydcm_alt50 (.clockin(clock_alt), .reset(reset1_clock_alt), .clockout(clock50_raw1), .clockout180(), .locked(pll_locked_alt));
BUFG mybuf1 (.I(clock50_raw1), .O(clock50_1));
assign clock50_12 = clock50_1;
wire clock_select = rpi_gpio13;
wire clock50;
BUFGMUX sam0s (.I0(clock50_0), .I1(clock50_12), .S(clock_select), .O(clock50));
wire reset2_clock50;
wire pll_locked;
reset #(.FREQUENCY(50000000)) reset2 (.upstream_clock(clock50), .upstream_reset(global_reset||reset1_clock_alt), .downstream_pll_locked(pll_locked), .downstream_reset(reset2_clock50));
wire rawclock125;
wire clock125;
BUFG mrt (.I(rawclock125), .O(clock125));
if (0) begin
simplepll_BASE #(.OVERALL_DIVIDE(1), .MULTIPLY(10), .DIVIDE0(4), .PHASE0(0.0), .PERIOD(20.0)) kronos (.clockin(clock50), .reset(reset2_clock50), .clock0out(rawclock125), .clock1out(), .clock2out(), .clock3out(), .clock4out(), .clock5out(), .locked(pll_locked));
end else if (0) begin
simpledcm_SP #(.MULTIPLY(10), .DIVIDE(4), .ALT_CLOCKOUT_DIVIDE(2), .PERIOD(20.0)) mydcm (.clockin(clock50), .reset(reset2_clock50), .clockout(rawclock125), .clockout180(), .alt_clockout(), .locked(pll_locked));
end else begin
simpledcm_CLKGEN #(.MULTIPLY(10), .DIVIDE(4), .PERIOD(20.0)) mydcm_125 (.clockin(clock50), .reset(reset2_clock50), .clockout(rawclock125), .clockout180(), .locked(pll_locked));
end
wire reset3_clock125;
wire pll_oserdes_locked;
reset #(.FREQUENCY(125000000)) reset3 (.upstream_clock(clock125), .upstream_reset(global_reset||reset2_clock50), .downstream_pll_locked(pll_oserdes_locked), .downstream_reset(reset3_clock125));
wire word_clock;
wire clock_spi;
assign clock_spi = word_clock;
wire reset4_word_clock;
reset #(.FREQUENCY(125000000)) reset4 (.upstream_clock(word_clock), .upstream_reset(global_reset||reset3_clock125), .downstream_pll_locked(pll_oserdes_locked), .downstream_reset(reset4_word_clock));
reg sync_read_address = 0;
reg [15:0] read_address = 0;
wire [31:0] start_read_address;
wire [31:0] end_read_address;
reg [15:0] last_read_address = 16'd4095;
wire miso_ce0;
wire miso_ce1;
assign rpi_spi_miso = rpi_spi_ce0 ? miso_ce1 : miso_ce0;
wire [7:0] command8_ce0;
wire [15:0] address16_ce0;
wire [31:0] data32_ce0;
wire [31:0] read_data32_ce0;
wire transaction_valid_ce0;
SPI_peripheral_command8_address16_data32 spi_ce0 (.clock(clock_spi),
.SCK(rpi_spi_sclk), .MOSI(rpi_spi_mosi), .MISO(miso_ce0), .SSEL(rpi_spi_ce0),
.transaction_valid(transaction_valid_ce0), .command8(command8_ce0), .address16(address16_ce0), .data32(data32_ce0), .data32_to_controller(read_data32_ce0));
wire [3:0] address4_ce0 = address16_ce0[3:0];
RAM_inferred_with_register_outputs_and_inputs #(.addr_width(4), .data_width(32)) myram (.reset(reset4_word_clock),
.wclk(clock_spi), .waddr(address4_ce0), .din(data32_ce0), .write_en(transaction_valid_ce0),
.rclk(word_clock), .raddr(address4_ce0), .dout(read_data32_ce0),
.register0(start_read_address), .register1(end_read_address), .register2(ring_oscillator_enable), .register3(ring_oscillator_select),
.registerC(32'd0), .registerD(32'd0), .registerE(32'd0), .registerF(frequency_counter1));
always @(posedge word_clock) begin
frequency_counter1 <= frequency_counter0;
end
wire [7:0] command8;
wire [15:0] address16;
wire [31:0] data32_0123;
wire [31:0] data32_3210;
assign data32_0123[7:0] = data32_3210[31:24];
assign data32_0123[15:8] = data32_3210[23:16];
assign data32_0123[23:16] = data32_3210[15:8];
assign data32_0123[31:24] = data32_3210[7:0];
wire [31:0] read_data32_0123;
wire [31:0] read_data32_3210;
assign read_data32_3210[7:0] = read_data32_0123[31:24];
assign read_data32_3210[15:8] = read_data32_0123[23:16];
assign read_data32_3210[23:16] = read_data32_0123[15:8];
assign read_data32_3210[31:24] = read_data32_0123[7:0];
wire transaction_valid_ce1;
SPI_peripheral_command8_address16_data32 spi_ce1 (.clock(clock_spi),
.SCK(rpi_spi_sclk), .MOSI(rpi_spi_mosi), .MISO(miso_ce1), .SSEL(rpi_spi_ce1),
.transaction_valid(transaction_valid_ce1), .command8(command8), .address16(address16), .data32(data32_3210), .data32_to_controller(read_data32_3210));
wire [7:0] oserdes_word_out;
`ifdef USE_BRAM_512
wire [8:0] address9 = address16[8:0];
wire [10:0] read_address11 = read_address[10:0];
RAM_s6_512_32bit_8bit mem (.reset(reset4_word_clock),
.clock_a(clock_spi), .address_a(address9), .data_in_a(data32_0123), .write_enable_a(transaction_valid_ce1), .data_out_a(read_data32_0123),
.clock_b(word_clock), .address_b(read_address11), .data_out_b(oserdes_word_out));
`elsif USE_BRAM_4K
wire [11:0] address12 = address16[11:0];
wire [13:0] read_address14 = read_address[13:0];
RAM_s6_4k_32bit_8bit mem (.reset(reset4_word_clock),
.clock_a(clock_spi), .address_a(address12), .data_in_a(data32_0123), .write_enable_a(transaction_valid_ce1), .data_out_a(read_data32_0123),
.clock_b(word_clock), .address_b(read_address14), .data_out_b(oserdes_word_out));
`endif
reg sync_out_raw = 0;
reg [3:0] sync_out_stream = 0;
always @(posedge word_clock) begin
sync_out_raw <= 0;
if (reset4_word_clock) begin
read_address <= start_read_address[17:2];
last_read_address <= end_read_address[17:2] - 1'b1;
end else begin
if (read_address==last_read_address || sync_read_address) begin
read_address <= start_read_address[17:2];
last_read_address <= end_read_address[17:2] - 1'b1;
sync_out_raw <= 1;
end else begin
read_address <= read_address + 1'b1;
end
end
sync_out_stream <= { sync_out_stream[2:0], sync_out_raw };
end
wire bit_clock;
wire bit_strobe;
wire other1_raw;
if (0) begin
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei (.clock_in(clock125), .reset(reset3_clock125), .word_clock_out(word_clock), .word_in(oserdes_word_out), .D_out(lemo), .locked(pll_oserdes_locked));
assign other0 = 0;
assign other1 = sync_out_stream[2];
end else if (0) begin
wire pll_oserdes_locked_1;
wire pll_oserdes_locked_2;
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei0 (.clock_in(clock125), .reset(reset3_clock125), .word_clock_out(word_clock), .word_in(oserdes_word_out), .D_out(lemo), .locked(pll_oserdes_locked_1));
wire word_clock_1;
reg [7:0] oserdes_word_out_1 = 0;
reg [7:0] oserdes_word_out_2 = 0;
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei1 (.clock_in(clock125), .reset(reset3_clock125), .word_clock_out(word_clock_1), .word_in(oserdes_word_out_2), .D_out(other0), .locked(pll_oserdes_locked_2));
always @(posedge word_clock_1) begin
oserdes_word_out_1 <= oserdes_word_out;
oserdes_word_out_2 <= oserdes_word_out_1;
end
assign other1 = sync_out_stream[2];
assign pll_oserdes_locked = pll_oserdes_locked_1 && pll_oserdes_locked_2;
end else begin
ocyrus_double8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei2 (.clock_in(clock125), .reset(reset3_clock125), .word_clock_out(word_clock), .word0_in(oserdes_word_out), .word1_in(oserdes_word_out), .D0_out(other0), .D1_out(other1_raw), .locked(pll_oserdes_locked), .bit_clock(bit_clock), .bit_strobe(bit_strobe));
end
if (0) begin
odelay_fixed #(.AMOUNT(0)) twoturntables (.bit_in(other1_raw), .bit_out(other1));
end else if (0) begin
odelay_fixed #(.AMOUNT(255)) andamicrophone (.bit_in(other1_raw), .bit_out(other1));
end else begin
assign other1 = other1_raw;
end
wire not_ready = global_reset || reset1_clock_alt || reset2_clock50 || reset3_clock125 || reset4_word_clock;
assign rpi_gpio5 = ~not_ready;
if (0) begin
wire [7:0] leds;
assign { led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0 } = leds;
assign leds = oserdes_word_out;
end else begin
assign led_7 = reset1_clock_alt;
assign led_6 = reset2_clock50;
assign led_5 = reset3_clock125;
assign led_4 = reset4_word_clock;
assign led_3 = ~clock_ro_locked;
assign led_2 = counter_ro[COUNTER_RO_PICKOFF];
assign led_1 = ~rpi_spi_ce0 || ~rpi_spi_ce1;
assign led_0 = not_ready;
end
localparam N = 10;
wire fc_valid;
frequency_counter #(.FREQUENCY_OF_REFERENCE_CLOCK(125000000), .LOG2_OF_DIVIDE_RATIO(24), .N(N)) fc (.reference_clock(word_clock), .unknown_clock(clock_ro), .frequency_of_unknown_clock(frequency_counter0), .valid(fc_valid));
endmodule | 2 |
5,971 | data/full_repos/permissive/115035459/verilog/src/mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v | 115,035,459 | mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v | v | 298 | 349 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v:6: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v:7: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v:8: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v:9: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v:10: Cannot find include file: lib/reset.v\n`include "lib/reset.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test042.spi-pollable-memories-and-oserdes-function-generator.althea.revA.v:11: Cannot find include file: lib/frequency_counter.v\n`include "lib/frequency_counter.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n' | 6,790 | module | module myalthea (
input clock50_p, clock50_n,
output lemo,
input b_n,
output b_p,
output a_n,
input a_p,
input c_n,
input c_p,
output d_n,
input d_p,
input e_n,
input e_p,
output f_p,
output led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
);
top althea (
.clock50_p(clock50_p), .clock50_n(clock50_n),
.lemo(lemo),
.other0(b_p),
.other1(f_p),
.rpi_spi_mosi(b_n), .rpi_spi_miso(a_n), .rpi_spi_sclk(c_p), .rpi_spi_ce0(c_n), .rpi_spi_ce1(a_p),
.rpi_gpio5(d_n), .rpi_gpio6_gpclk2(d_p), .rpi_gpio13(e_n), .rpi_gpio19(e_p),
.led_0(led_0), .led_1(led_1), .led_2(led_2), .led_3(led_3),
.led_4(led_4), .led_5(led_5), .led_6(led_6), .led_7(led_7)
);
endmodule | module myalthea (
input clock50_p, clock50_n,
output lemo,
input b_n,
output b_p,
output a_n,
input a_p,
input c_n,
input c_p,
output d_n,
input d_p,
input e_n,
input e_p,
output f_p,
output led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
); |
top althea (
.clock50_p(clock50_p), .clock50_n(clock50_n),
.lemo(lemo),
.other0(b_p),
.other1(f_p),
.rpi_spi_mosi(b_n), .rpi_spi_miso(a_n), .rpi_spi_sclk(c_p), .rpi_spi_ce0(c_n), .rpi_spi_ce1(a_p),
.rpi_gpio5(d_n), .rpi_gpio6_gpclk2(d_p), .rpi_gpio13(e_n), .rpi_gpio19(e_p),
.led_0(led_0), .led_1(led_1), .led_2(led_2), .led_3(led_3),
.led_4(led_4), .led_5(led_5), .led_6(led_6), .led_7(led_7)
);
endmodule | 2 |
5,972 | data/full_repos/permissive/115035459/verilog/src/mza-test043.spi-pollable-memories-and-multiple-oserdes-function-generator-outputs.althea.revB.v | 115,035,459 | mza-test043.spi-pollable-memories-and-multiple-oserdes-function-generator-outputs.althea.revB.v | v | 255 | 267 | [] | [] | [] | null | line:38: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test043.spi-pollable-memories-and-multiple-oserdes-function-generator-outputs.althea.revB.v:6: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test043.spi-pollable-memories-and-multiple-oserdes-function-generator-outputs.althea.revB.v:7: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test043.spi-pollable-memories-and-multiple-oserdes-function-generator-outputs.althea.revB.v:8: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test043.spi-pollable-memories-and-multiple-oserdes-function-generator-outputs.althea.revB.v:9: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 6,791 | module | module top (
input clock50_p, clock50_n,
input rpi_spi_sclk,
input rpi_spi_mosi,
output rpi_spi_miso,
input rpi_spi_ce0,
input rpi_spi_ce1,
input button,
output [5:0] coax,
output [3:0] coax_led,
output [7:0] led
);
reg reset1 = 1;
reg reset2_clock125 = 1;
reg reset3_word_clock = 1;
wire clock50;
IBUFGDS mybuf (.I(clock50_p), .IB(clock50_n), .O(clock50));
wire pll_locked;
wire rawclock125;
wire clock125;
BUFG mrt (.I(rawclock125), .O(clock125));
if (0) begin
simplepll_BASE #(.OVERALL_DIVIDE(1), .MULTIPLY(10), .DIVIDE0(4), .PHASE0(0.0), .PERIOD(20.0)) kronos (.clockin(clock50), .reset(reset1), .clock0out(rawclock125), .clock1out(), .clock2out(), .clock3out(), .clock4out(), .clock5out(), .locked(pll_locked));
end else begin
simpledcm_SP #(.MULTIPLY(10), .DIVIDE(4), .ALT_CLOCKOUT_DIVIDE(2), .PERIOD(20.0)) mydcm (.clockin(clock50), .reset(reset1), .clockout(rawclock125), .clockout180(), .alt_clockout(), .locked(pll_locked));
end
wire word_clock;
wire [7:0] oserdes_word_out;
wire pll_oserdes_locked;
wire clock_ram;
wire clock_spi;
assign clock_ram = word_clock;
assign clock_spi = word_clock;
reg [7:0] reset_counter = 0;
always @(posedge clock50) begin
if (~button) begin
reset1 <= 1;
reset_counter <= 0;
end else if (reset1) begin
if (reset_counter[7]) begin
reset1 <= 0;
end else begin
reset_counter <= reset_counter + 1'b1;
end
end
end
always @(posedge clock125) begin
if (reset2_clock125) begin
if (pll_locked) begin
reset2_clock125 <= 0;
end
end
end
always @(posedge word_clock) begin
if (reset3_word_clock) begin
if (pll_oserdes_locked) begin
reset3_word_clock <= 0;
end
end
end
reg sync_read_address = 0;
reg [15:0] read_address = 0;
wire [31:0] start_read_address;
wire [31:0] end_read_address;
reg [15:0] last_read_address = 16'd4095;
wire miso_ce0;
wire miso_ce1;
assign rpi_spi_miso = rpi_spi_ce0 ? miso_ce1 : miso_ce0;
wire [7:0] command8_ce0;
wire [15:0] address16_ce0;
wire [31:0] data32_ce0;
wire [31:0] read_data32_ce0;
wire transaction_valid_ce0;
SPI_peripheral_command8_address16_data32 spi_ce0 (.clock(clock_spi),
.SCK(rpi_spi_sclk), .MOSI(rpi_spi_mosi), .MISO(miso_ce0), .SSEL(rpi_spi_ce0),
.transaction_valid(transaction_valid_ce0), .command8(command8_ce0), .address16(address16_ce0), .data32(data32_ce0), .data32_to_controller(read_data32_ce0));
wire [3:0] address4_ce0 = address16_ce0[3:0];
RAM_inferred_with_register_outputs #(.ADDR_WIDTH(4), .DATA_WIDTH(32)) myram (.reset(reset3_word_clock),
.clock(clock_ram), .waddress_a(address4_ce0), .data_in_a(data32_ce0), .write_strobe_a(transaction_valid_ce0),
.raddress_a(address4_ce0), .data_out_a(read_data32_ce0),
.data_out_b_0(start_read_address), .data_out_b_1(end_read_address), .data_out_b_2(), .data_out_b_3());
wire [7:0] command8;
wire [15:0] address16;
wire [31:0] data32_0123;
wire [31:0] data32_3210;
assign data32_0123[7:0] = data32_3210[31:24];
assign data32_0123[15:8] = data32_3210[23:16];
assign data32_0123[23:16] = data32_3210[15:8];
assign data32_0123[31:24] = data32_3210[7:0];
wire [31:0] read_data32_0123;
wire [31:0] read_data32_3210;
assign read_data32_3210[7:0] = read_data32_0123[31:24];
assign read_data32_3210[15:8] = read_data32_0123[23:16];
assign read_data32_3210[23:16] = read_data32_0123[15:8];
assign read_data32_3210[31:24] = read_data32_0123[7:0];
wire transaction_valid_ce1;
SPI_peripheral_command8_address16_data32 spi_ce1 (.clock(clock_spi),
.SCK(rpi_spi_sclk), .MOSI(rpi_spi_mosi), .MISO(miso_ce1), .SSEL(rpi_spi_ce1),
.transaction_valid(transaction_valid_ce1), .command8(command8), .address16(address16), .data32(data32_3210), .data32_to_controller(read_data32_3210));
`ifdef USE_BRAM_512
wire [8:0] address9 = address16[8:0];
wire [10:0] read_address11 = read_address[10:0];
RAM_s6_512_32bit_8bit mem (.reset(reset3_word_clock),
.clock_a(clock_ram), .address_a(address9), .data_in_a(data32_0123), .write_enable_a(transaction_valid_ce1), .data_out_a(read_data32_0123),
.clock_b(clock_ram), .address_b(read_address11), .data_out_b(oserdes_word_out));
`elsif USE_BRAM_4K
wire [11:0] address12 = address16[11:0];
wire [13:0] read_address14 = read_address[13:0];
RAM_s6_4k_32bit_8bit mem (.reset(reset3_word_clock),
.clock_a(clock_ram), .address_a(address12), .data_in_a(data32_0123), .write_enable_a(transaction_valid_ce1), .data_out_a(read_data32_0123),
.clock_b(clock_ram), .address_b(read_address14), .data_out_b(oserdes_word_out));
`endif
reg sync_out_raw = 0;
reg [3:0] sync_out_stream = 0;
always @(posedge word_clock) begin
sync_out_raw <= 0;
if (reset3_word_clock) begin
read_address <= start_read_address[17:2];
last_read_address <= end_read_address[17:2] - 1'b1;
end else begin
if (read_address==last_read_address || sync_read_address) begin
read_address <= start_read_address[17:2];
last_read_address <= end_read_address[17:2] - 1'b1;
sync_out_raw <= 1;
end else begin
read_address <= read_address + 1'b1;
end
end
sync_out_stream <= { sync_out_stream[2:0], sync_out_raw };
end
assign coax[4] = sync_out_stream[2];
if (0) begin
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei (.clock_in(clock125), .reset(reset2_clock125), .word_clock_out(word_clock), .word_in(oserdes_word_out), .D_out(coax[0]), .locked(pll_oserdes_locked));
assign coax[1] = 0;
assign coax[2] = 0;
assign coax[3] = 0;
assign coax[4] = 0;
assign coax[5] = 0;
end else if (0) begin
assign coax_led = 4'b0011;
ocyrus_double8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei (.clock_in(clock125), .reset(reset2_clock125), .word_clock_out(word_clock),
.word0_in(oserdes_word_out), .D0_out(coax[0]),
.word1_in(oserdes_word_out), .D1_out(coax[1]),
.locked(pll_oserdes_locked));
assign coax[2] = 0;
assign coax[3] = 0;
assign coax[4] = 0;
assign coax[5] = 0;
end else if (1) begin
assign coax_led = 4'b1111;
ocyrus_quad8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei (
.clock_in(clock125), .reset(reset2_clock125), .word_clock_out(word_clock), .locked(pll_oserdes_locked),
.word0_in(oserdes_word_out), .word1_in(oserdes_word_out), .word2_in(oserdes_word_out), .word3_in(oserdes_word_out),
.D0_out(coax[0]), .D1_out(coax[1]), .D2_out(coax[2]), .D3_out(coax[3]));
assign coax[5] = 0;
end else if (0) begin
assign coax_led = 4'b1111;
wire pll_oserdes_locked_1;
wire pll_oserdes_locked_2;
ocyrus_quad8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei4 (
.clock_in(clock125), .reset(reset2_clock125), .word_clock_out(word_clock), .locked(pll_oserdes_locked_1),
.word0_in(oserdes_word_out), .word1_in(oserdes_word_out), .word2_in(oserdes_word_out), .word3_in(oserdes_word_out),
.D0_out(coax[0]), .D1_out(coax[1]), .D2_out(coax[2]), .D3_out());
assign coax[3] = sync_out_stream[2];
ocyrus_double8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .PINTYPE1("n")) mylei2 (.clock_in(clock125), .reset(reset2_clock125), .word_clock_out(),
.word0_in(oserdes_word_out), .D0_out(coax[4]),
.word1_in(oserdes_word_out), .D1_out(coax[5]),
.locked(pll_oserdes_locked_2));
assign pll_oserdes_locked = pll_oserdes_locked_1 && pll_oserdes_locked_2;
end else begin
assign pll_oserdes_locked_1 = 1;
assign coax[0] = 0;
assign coax[1] = 0;
assign coax[2] = 0;
assign coax[3] = 0;
ocyrus_double8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .PINTYPE1("n")) mylei2 (.clock_in(clock125), .reset(reset2_clock125), .word_clock_out(word_clock),
.word0_in(oserdes_word_out), .D0_out(coax[4]),
.word1_in(oserdes_word_out), .D1_out(coax[5]),
.locked(pll_oserdes_locked_2));
assign pll_oserdes_locked = pll_oserdes_locked_1 && pll_oserdes_locked_2;
end
if (0) begin
assign led = oserdes_word_out;
end else begin
assign led[7] = ~pll_oserdes_locked;
assign led[6] = 0;
assign led[5] = reset1;
assign led[4] = reset2_clock125;
assign led[3] = reset3_word_clock;
assign led[2] = ~rpi_spi_ce0;
assign led[1] = ~rpi_spi_ce1;
assign led[0] = 0;
end
endmodule | module top (
input clock50_p, clock50_n,
input rpi_spi_sclk,
input rpi_spi_mosi,
output rpi_spi_miso,
input rpi_spi_ce0,
input rpi_spi_ce1,
input button,
output [5:0] coax,
output [3:0] coax_led,
output [7:0] led
); |
reg reset1 = 1;
reg reset2_clock125 = 1;
reg reset3_word_clock = 1;
wire clock50;
IBUFGDS mybuf (.I(clock50_p), .IB(clock50_n), .O(clock50));
wire pll_locked;
wire rawclock125;
wire clock125;
BUFG mrt (.I(rawclock125), .O(clock125));
if (0) begin
simplepll_BASE #(.OVERALL_DIVIDE(1), .MULTIPLY(10), .DIVIDE0(4), .PHASE0(0.0), .PERIOD(20.0)) kronos (.clockin(clock50), .reset(reset1), .clock0out(rawclock125), .clock1out(), .clock2out(), .clock3out(), .clock4out(), .clock5out(), .locked(pll_locked));
end else begin
simpledcm_SP #(.MULTIPLY(10), .DIVIDE(4), .ALT_CLOCKOUT_DIVIDE(2), .PERIOD(20.0)) mydcm (.clockin(clock50), .reset(reset1), .clockout(rawclock125), .clockout180(), .alt_clockout(), .locked(pll_locked));
end
wire word_clock;
wire [7:0] oserdes_word_out;
wire pll_oserdes_locked;
wire clock_ram;
wire clock_spi;
assign clock_ram = word_clock;
assign clock_spi = word_clock;
reg [7:0] reset_counter = 0;
always @(posedge clock50) begin
if (~button) begin
reset1 <= 1;
reset_counter <= 0;
end else if (reset1) begin
if (reset_counter[7]) begin
reset1 <= 0;
end else begin
reset_counter <= reset_counter + 1'b1;
end
end
end
always @(posedge clock125) begin
if (reset2_clock125) begin
if (pll_locked) begin
reset2_clock125 <= 0;
end
end
end
always @(posedge word_clock) begin
if (reset3_word_clock) begin
if (pll_oserdes_locked) begin
reset3_word_clock <= 0;
end
end
end
reg sync_read_address = 0;
reg [15:0] read_address = 0;
wire [31:0] start_read_address;
wire [31:0] end_read_address;
reg [15:0] last_read_address = 16'd4095;
wire miso_ce0;
wire miso_ce1;
assign rpi_spi_miso = rpi_spi_ce0 ? miso_ce1 : miso_ce0;
wire [7:0] command8_ce0;
wire [15:0] address16_ce0;
wire [31:0] data32_ce0;
wire [31:0] read_data32_ce0;
wire transaction_valid_ce0;
SPI_peripheral_command8_address16_data32 spi_ce0 (.clock(clock_spi),
.SCK(rpi_spi_sclk), .MOSI(rpi_spi_mosi), .MISO(miso_ce0), .SSEL(rpi_spi_ce0),
.transaction_valid(transaction_valid_ce0), .command8(command8_ce0), .address16(address16_ce0), .data32(data32_ce0), .data32_to_controller(read_data32_ce0));
wire [3:0] address4_ce0 = address16_ce0[3:0];
RAM_inferred_with_register_outputs #(.ADDR_WIDTH(4), .DATA_WIDTH(32)) myram (.reset(reset3_word_clock),
.clock(clock_ram), .waddress_a(address4_ce0), .data_in_a(data32_ce0), .write_strobe_a(transaction_valid_ce0),
.raddress_a(address4_ce0), .data_out_a(read_data32_ce0),
.data_out_b_0(start_read_address), .data_out_b_1(end_read_address), .data_out_b_2(), .data_out_b_3());
wire [7:0] command8;
wire [15:0] address16;
wire [31:0] data32_0123;
wire [31:0] data32_3210;
assign data32_0123[7:0] = data32_3210[31:24];
assign data32_0123[15:8] = data32_3210[23:16];
assign data32_0123[23:16] = data32_3210[15:8];
assign data32_0123[31:24] = data32_3210[7:0];
wire [31:0] read_data32_0123;
wire [31:0] read_data32_3210;
assign read_data32_3210[7:0] = read_data32_0123[31:24];
assign read_data32_3210[15:8] = read_data32_0123[23:16];
assign read_data32_3210[23:16] = read_data32_0123[15:8];
assign read_data32_3210[31:24] = read_data32_0123[7:0];
wire transaction_valid_ce1;
SPI_peripheral_command8_address16_data32 spi_ce1 (.clock(clock_spi),
.SCK(rpi_spi_sclk), .MOSI(rpi_spi_mosi), .MISO(miso_ce1), .SSEL(rpi_spi_ce1),
.transaction_valid(transaction_valid_ce1), .command8(command8), .address16(address16), .data32(data32_3210), .data32_to_controller(read_data32_3210));
`ifdef USE_BRAM_512
wire [8:0] address9 = address16[8:0];
wire [10:0] read_address11 = read_address[10:0];
RAM_s6_512_32bit_8bit mem (.reset(reset3_word_clock),
.clock_a(clock_ram), .address_a(address9), .data_in_a(data32_0123), .write_enable_a(transaction_valid_ce1), .data_out_a(read_data32_0123),
.clock_b(clock_ram), .address_b(read_address11), .data_out_b(oserdes_word_out));
`elsif USE_BRAM_4K
wire [11:0] address12 = address16[11:0];
wire [13:0] read_address14 = read_address[13:0];
RAM_s6_4k_32bit_8bit mem (.reset(reset3_word_clock),
.clock_a(clock_ram), .address_a(address12), .data_in_a(data32_0123), .write_enable_a(transaction_valid_ce1), .data_out_a(read_data32_0123),
.clock_b(clock_ram), .address_b(read_address14), .data_out_b(oserdes_word_out));
`endif
reg sync_out_raw = 0;
reg [3:0] sync_out_stream = 0;
always @(posedge word_clock) begin
sync_out_raw <= 0;
if (reset3_word_clock) begin
read_address <= start_read_address[17:2];
last_read_address <= end_read_address[17:2] - 1'b1;
end else begin
if (read_address==last_read_address || sync_read_address) begin
read_address <= start_read_address[17:2];
last_read_address <= end_read_address[17:2] - 1'b1;
sync_out_raw <= 1;
end else begin
read_address <= read_address + 1'b1;
end
end
sync_out_stream <= { sync_out_stream[2:0], sync_out_raw };
end
assign coax[4] = sync_out_stream[2];
if (0) begin
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei (.clock_in(clock125), .reset(reset2_clock125), .word_clock_out(word_clock), .word_in(oserdes_word_out), .D_out(coax[0]), .locked(pll_oserdes_locked));
assign coax[1] = 0;
assign coax[2] = 0;
assign coax[3] = 0;
assign coax[4] = 0;
assign coax[5] = 0;
end else if (0) begin
assign coax_led = 4'b0011;
ocyrus_double8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei (.clock_in(clock125), .reset(reset2_clock125), .word_clock_out(word_clock),
.word0_in(oserdes_word_out), .D0_out(coax[0]),
.word1_in(oserdes_word_out), .D1_out(coax[1]),
.locked(pll_oserdes_locked));
assign coax[2] = 0;
assign coax[3] = 0;
assign coax[4] = 0;
assign coax[5] = 0;
end else if (1) begin
assign coax_led = 4'b1111;
ocyrus_quad8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei (
.clock_in(clock125), .reset(reset2_clock125), .word_clock_out(word_clock), .locked(pll_oserdes_locked),
.word0_in(oserdes_word_out), .word1_in(oserdes_word_out), .word2_in(oserdes_word_out), .word3_in(oserdes_word_out),
.D0_out(coax[0]), .D1_out(coax[1]), .D2_out(coax[2]), .D3_out(coax[3]));
assign coax[5] = 0;
end else if (0) begin
assign coax_led = 4'b1111;
wire pll_oserdes_locked_1;
wire pll_oserdes_locked_2;
ocyrus_quad8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei4 (
.clock_in(clock125), .reset(reset2_clock125), .word_clock_out(word_clock), .locked(pll_oserdes_locked_1),
.word0_in(oserdes_word_out), .word1_in(oserdes_word_out), .word2_in(oserdes_word_out), .word3_in(oserdes_word_out),
.D0_out(coax[0]), .D1_out(coax[1]), .D2_out(coax[2]), .D3_out());
assign coax[3] = sync_out_stream[2];
ocyrus_double8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .PINTYPE1("n")) mylei2 (.clock_in(clock125), .reset(reset2_clock125), .word_clock_out(),
.word0_in(oserdes_word_out), .D0_out(coax[4]),
.word1_in(oserdes_word_out), .D1_out(coax[5]),
.locked(pll_oserdes_locked_2));
assign pll_oserdes_locked = pll_oserdes_locked_1 && pll_oserdes_locked_2;
end else begin
assign pll_oserdes_locked_1 = 1;
assign coax[0] = 0;
assign coax[1] = 0;
assign coax[2] = 0;
assign coax[3] = 0;
ocyrus_double8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .PINTYPE1("n")) mylei2 (.clock_in(clock125), .reset(reset2_clock125), .word_clock_out(word_clock),
.word0_in(oserdes_word_out), .D0_out(coax[4]),
.word1_in(oserdes_word_out), .D1_out(coax[5]),
.locked(pll_oserdes_locked_2));
assign pll_oserdes_locked = pll_oserdes_locked_1 && pll_oserdes_locked_2;
end
if (0) begin
assign led = oserdes_word_out;
end else begin
assign led[7] = ~pll_oserdes_locked;
assign led[6] = 0;
assign led[5] = reset1;
assign led[4] = reset2_clock125;
assign led[3] = reset3_word_clock;
assign led[2] = ~rpi_spi_ce0;
assign led[1] = ~rpi_spi_ce1;
assign led[0] = 0;
end
endmodule | 2 |
5,973 | data/full_repos/permissive/115035459/verilog/src/mza-test043.spi-pollable-memories-and-multiple-oserdes-function-generator-outputs.althea.revB.v | 115,035,459 | mza-test043.spi-pollable-memories-and-multiple-oserdes-function-generator-outputs.althea.revB.v | v | 255 | 267 | [] | [] | [] | null | line:38: before: "=" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test043.spi-pollable-memories-and-multiple-oserdes-function-generator-outputs.althea.revB.v:6: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n lib/spi.v\n lib/spi.v.v\n lib/spi.v.sv\n obj_dir/lib/spi.v\n obj_dir/lib/spi.v.v\n obj_dir/lib/spi.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test043.spi-pollable-memories-and-multiple-oserdes-function-generator-outputs.althea.revB.v:7: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test043.spi-pollable-memories-and-multiple-oserdes-function-generator-outputs.althea.revB.v:8: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test043.spi-pollable-memories-and-multiple-oserdes-function-generator-outputs.althea.revB.v:9: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 6,791 | module | module mza_test043_spi_pollable_memories_and_multiple_oserdes_function_generator_outputs_althea_top (
input clock50_p, clock50_n,
input rpi_spi_sclk,
input rpi_spi_ce0,
input rpi_spi_ce1,
input rpi_spi_mosi,
output rpi_spi_miso,
input button,
output [5:0] coax,
output [3:0] coax_led,
output [7:0] led
);
top mytop (
.clock50_p(clock50_p), .clock50_n(clock50_n),
.rpi_spi_mosi(rpi_spi_mosi), .rpi_spi_miso(rpi_spi_miso), .rpi_spi_sclk(rpi_spi_sclk), .rpi_spi_ce0(rpi_spi_ce0), .rpi_spi_ce1(rpi_spi_ce1),
.button(button),
.coax(coax),
.coax_led(coax_led),
.led(led)
);
endmodule | module mza_test043_spi_pollable_memories_and_multiple_oserdes_function_generator_outputs_althea_top (
input clock50_p, clock50_n,
input rpi_spi_sclk,
input rpi_spi_ce0,
input rpi_spi_ce1,
input rpi_spi_mosi,
output rpi_spi_miso,
input button,
output [5:0] coax,
output [3:0] coax_led,
output [7:0] led
); |
top mytop (
.clock50_p(clock50_p), .clock50_n(clock50_n),
.rpi_spi_mosi(rpi_spi_mosi), .rpi_spi_miso(rpi_spi_miso), .rpi_spi_sclk(rpi_spi_sclk), .rpi_spi_ce0(rpi_spi_ce0), .rpi_spi_ce1(rpi_spi_ce1),
.button(button),
.coax(coax),
.coax_led(coax_led),
.led(led)
);
endmodule | 2 |
5,977 | data/full_repos/permissive/115035459/verilog/src/mza-test045.nop.althea.revA.v | 115,035,459 | mza-test045.nop.althea.revA.v | v | 31 | 183 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/1e49b80d-7b0c-4abc-8dc7-f1a23b0e7dd6.xml | null | 6,793 | module | module top ();
endmodule | module top (); |
endmodule | 2 |
5,978 | data/full_repos/permissive/115035459/verilog/src/mza-test045.nop.althea.revA.v | 115,035,459 | mza-test045.nop.althea.revA.v | v | 31 | 183 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/1e49b80d-7b0c-4abc-8dc7-f1a23b0e7dd6.xml | null | 6,793 | module | module myalthea (
input clock50_p, clock50_n,
input lemo,
input a_p, a_n,
input b_p, b_n,
input c_p, c_n,
input d_p, d_n,
input e_p, e_n,
input f_p, f_n,
input g_p, g_n,
input h_p, h_n,
input j_p, j_n,
input k_p, k_n,
input l_p, l_n,
input m_p, m_n,
input led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
);
top althea ();
endmodule | module myalthea (
input clock50_p, clock50_n,
input lemo,
input a_p, a_n,
input b_p, b_n,
input c_p, c_n,
input d_p, d_n,
input e_p, e_n,
input f_p, f_n,
input g_p, g_n,
input h_p, h_n,
input j_p, j_n,
input k_p, k_n,
input l_p, l_n,
input m_p, m_n,
input led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
); |
top althea ();
endmodule | 2 |
5,979 | data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v | 115,035,459 | mza-test048.simple-counter-again.v | v | 74 | 69 | [] | [] | [] | [(3, 255), (258, 320)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:39: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:41: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:43: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:45: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:47: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:50: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:52: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:54: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:56: Unsupported: Ignoring delay on this delayed statement.\n #10000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:58: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:63: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD;\n ^\n%Error: Exiting due to 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,796 | module | module counter #(
parameter WIDTH = 8,
parameter LOAD_VALUE = 8'h45
) (
input clk,
input rst,
input load,
output [WIDTH-1:0] cnt_out
);
reg [WIDTH-1:0] counter = 0;
always @(posedge clk) begin
if (~rst) begin
counter <= 0;
end else if (load) begin
counter <= LOAD_VALUE;
end else begin
counter <= counter + 1'b1;
end
end
assign cnt_out = counter;
endmodule | module counter #(
parameter WIDTH = 8,
parameter LOAD_VALUE = 8'h45
) (
input clk,
input rst,
input load,
output [WIDTH-1:0] cnt_out
); |
reg [WIDTH-1:0] counter = 0;
always @(posedge clk) begin
if (~rst) begin
counter <= 0;
end else if (load) begin
counter <= LOAD_VALUE;
end else begin
counter <= counter + 1'b1;
end
end
assign cnt_out = counter;
endmodule | 2 |
5,980 | data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v | 115,035,459 | mza-test048.simple-counter-again.v | v | 74 | 69 | [] | [] | [] | [(3, 255), (258, 320)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:39: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:41: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:43: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:45: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:47: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:50: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:52: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:54: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:56: Unsupported: Ignoring delay on this delayed statement.\n #10000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:58: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:63: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD;\n ^\n%Error: Exiting due to 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,796 | module | module counter_tb;
parameter WIDTH = 8;
parameter HALF_PERIOD = 5;
parameter PERIOD = 2*HALF_PERIOD;
reg clk = 0;
reg pre_rst = 0;
reg rst = 0;
reg pre_load = 0;
reg load = 0;
wire [WIDTH-1:0] cnt;
initial begin
pre_rst <= 0;
pre_load <= 0;
#100;
pre_rst <= 1;
#PERIOD;
$display("%02x", cnt);
#PERIOD;
$display("%02x", cnt);
#1000;
$display("%02x", cnt);
#PERIOD;
$display("%02x", cnt);
pre_load <= 1;
#PERIOD;
pre_load <= 0;
#PERIOD;
$display("%02x", cnt);
#PERIOD;
$display("%02x", cnt);
#10000;
$display("%02x", cnt);
#PERIOD;
$display("%02x", cnt);
$finish;
end
always begin
#HALF_PERIOD;
clk <= ~clk;
end
always @(posedge clk) begin
rst <= pre_rst;
load <= pre_load;
end
counter counter1(.clk(clk), .rst(rst), .load(load), .cnt_out(cnt));
endmodule | module counter_tb; |
parameter WIDTH = 8;
parameter HALF_PERIOD = 5;
parameter PERIOD = 2*HALF_PERIOD;
reg clk = 0;
reg pre_rst = 0;
reg rst = 0;
reg pre_load = 0;
reg load = 0;
wire [WIDTH-1:0] cnt;
initial begin
pre_rst <= 0;
pre_load <= 0;
#100;
pre_rst <= 1;
#PERIOD;
$display("%02x", cnt);
#PERIOD;
$display("%02x", cnt);
#1000;
$display("%02x", cnt);
#PERIOD;
$display("%02x", cnt);
pre_load <= 1;
#PERIOD;
pre_load <= 0;
#PERIOD;
$display("%02x", cnt);
#PERIOD;
$display("%02x", cnt);
#10000;
$display("%02x", cnt);
#PERIOD;
$display("%02x", cnt);
$finish;
end
always begin
#HALF_PERIOD;
clk <= ~clk;
end
always @(posedge clk) begin
rst <= pre_rst;
load <= pre_load;
end
counter counter1(.clk(clk), .rst(rst), .load(load), .cnt_out(cnt));
endmodule | 2 |
5,981 | data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v | 115,035,459 | mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v | v | 604 | 262 | [] | [] | [] | null | line:305: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:7: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:8: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:9: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:10: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:11: Cannot find include file: lib/half_duplex_rpi_bus.v\n`include "lib/half_duplex_rpi_bus.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:248: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:303: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:312: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:342: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:447: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:447: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:448: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:449: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:531: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:531: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:532: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:541: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:546: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Error: Exiting due to 5 error(s), 13 warning(s)\n' | 6,797 | module | module top #(
parameter BUS_WIDTH = 16,
parameter LOG2_OF_BUS_WIDTH = $clog2(BUS_WIDTH),
parameter TRANSACTIONS_PER_DATA_WORD = 2,
parameter LOG2_OF_TRANSACTIONS_PER_DATA_WORD = $clog2(TRANSACTIONS_PER_DATA_WORD),
parameter BUS_WIDTH_OSERDES = 8,
parameter TRANSACTIONS_PER_ADDRESS_WORD = 1,
parameter ADDRESS_DEPTH = 14,
parameter OSERDES_DATA_WIDTH = 8,
parameter LOG2_OF_OSERDES_DATA_WIDTH = $clog2(OSERDES_DATA_WIDTH),
parameter ADDRESS_DEPTH_OSERDES = ADDRESS_DEPTH + LOG2_OF_BUS_WIDTH + LOG2_OF_TRANSACTIONS_PER_DATA_WORD - LOG2_OF_OSERDES_DATA_WIDTH,
parameter ADDRESS_AUTOINCREMENT_MODE = 1,
parameter TESTBENCH = 0,
parameter COUNTER50_BIT_PICKOFF = TESTBENCH ? 5 : 23,
parameter COUNTER125_BIT_PICKOFF = TESTBENCH ? 5 : 23
) (
input clock50_p, clock50_n,
input clock10,
input reset,
inout [5:0] coax,
inout [BUS_WIDTH-1:0] bus,
input read,
input register_select,
input enable,
output ack_valid,
output [11:0] diff_pair_left,
output [11:0] diff_pair_right,
output [5:0] single_ended_left,
output [5:0] single_ended_right,
output [3:0] coax_led,
output [7:0] led
);
genvar i;
wire pll_locked;
wire pll_oserdes_locked_1;
wire pll_oserdes_locked_2;
assign diff_pair_left[3] = 0;
assign diff_pair_left[2] = pll_oserdes_locked_1;
assign diff_pair_left[1] = pll_locked;
assign diff_pair_left[0] = write_strobe;
assign diff_pair_right[0] = read;
assign diff_pair_right[1] = register_select;
assign diff_pair_right[3] = ack_valid;
assign diff_pair_right[2] = enable;
assign diff_pair_left[11:4] = 8'h0;
assign diff_pair_right[11:4] = {4'h0, bus[3:0]};
for (i=0; i<6; i=i+1) begin : single_ended_array
assign single_ended_left[i] = 0;
assign single_ended_right[i] = 0;
end
reg [3:0] reset_counter = 0;
localparam RESET_PIPELINE_PICKOFF = 5;
reg [RESET_PIPELINE_PICKOFF:0] reset_pipeline50 = 0;
reg [RESET_PIPELINE_PICKOFF:0] reset_pipeline125 = 0;
reg reset50 = 1;
wire clock50;
IBUFGDS mybuf0 (.I(clock50_p), .IB(clock50_n), .O(clock50));
wire rawclock125;
wire clock125;
simpledcm_CLKGEN #(.MULTIPLY(10), .DIVIDE(4), .PERIOD(20.0)) mydcm_125 (.clockin(clock50), .reset(reset50), .clockout(rawclock125), .clockout180(), .locked(pll_locked));
BUFG mrt (.I(rawclock125), .O(clock125));
wire clock = clock125;
reg [COUNTER50_BIT_PICKOFF:0] counter50 = 0;
always @(posedge clock50) begin
if (reset_pipeline50[RESET_PIPELINE_PICKOFF:RESET_PIPELINE_PICKOFF-3]==4'b0011) begin
reset_counter <= reset_counter + 1'b1;
end else if (reset_pipeline50[RESET_PIPELINE_PICKOFF]) begin
counter50 <= 0;
reset50 <= 1;
end else if (reset50) begin
if (counter50[COUNTER50_BIT_PICKOFF]) begin
reset50 <= 0;
end
counter50 <= counter50 + 1'b1;
end
reset_pipeline50 <= { reset_pipeline50[RESET_PIPELINE_PICKOFF-1:0], reset };
end
reg [2:0] reset50_pipeline125 = 0;
localparam PLL_LOCKED_PIPELINE125_PICKOFF = 2;
reg [PLL_LOCKED_PIPELINE125_PICKOFF:0] pll_locked_pipeline125 = 0;
integer j;
always @(posedge clock125) begin
if (~pll_locked_pipeline125[PLL_LOCKED_PIPELINE125_PICKOFF]) begin
reset50_pipeline125 <= 0;
reset_pipeline125 <= 0;
end else begin
reset50_pipeline125 <= { reset50_pipeline125[1:0], reset50 };
reset_pipeline125 <= { reset_pipeline125[RESET_PIPELINE_PICKOFF-1:0], reset };
end
pll_locked_pipeline125 <= { pll_locked_pipeline125[PLL_LOCKED_PIPELINE125_PICKOFF-1:0], pll_locked };
end
reg [COUNTER125_BIT_PICKOFF:0] counter125 = 0;
reg reset125 = 1;
always @(posedge clock) begin
if (reset_pipeline125[RESET_PIPELINE_PICKOFF] || reset50_pipeline125[2] || ~pll_locked_pipeline125[PLL_LOCKED_PIPELINE125_PICKOFF]) begin
counter125 <= 0;
reset125 <= 1;
end else if (reset125) begin
if (counter125[COUNTER125_BIT_PICKOFF]) begin
reset125 <= 0;
end
counter125 <= counter125 + 1'b1;
end
end
wire [BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD-1:0] address_word_full;
wire [ADDRESS_DEPTH-1:0] address_word_narrow = address_word_full[ADDRESS_DEPTH-1:0];
wire [BUS_WIDTH*TRANSACTIONS_PER_DATA_WORD-1:0] write_data_word;
wire [BUS_WIDTH*TRANSACTIONS_PER_DATA_WORD-1:0] read_data_word;
half_duplex_rpi_bus #(
.BUS_WIDTH(BUS_WIDTH),
.TRANSACTIONS_PER_DATA_WORD(TRANSACTIONS_PER_DATA_WORD),
.TRANSACTIONS_PER_ADDRESS_WORD(TRANSACTIONS_PER_ADDRESS_WORD),
.ADDRESS_AUTOINCREMENT_MODE(ADDRESS_AUTOINCREMENT_MODE)
) hdrb (
.clock(clock),
.reset(reset125),
.bus(bus),
.read(read),
.register_select(register_select),
.enable(enable),
.ack_valid(ack_valid),
.write_strobe(write_strobe),
.write_data_word(write_data_word),
.read_data_word(read_data_word),
.address_word_reg(address_word_full)
);
wire word_clock;
wire [BUS_WIDTH_OSERDES-1:0] oserdes_word;
reg [ADDRESS_DEPTH_OSERDES-1:0] read_address = 0;
if (0) begin
RAM_inferred #(.addr_width(ADDRESS_DEPTH), .data_width(TRANSACTIONS_PER_DATA_WORD*BUS_WIDTH)) myram (.reset(reset125),
.wclk(clock), .waddr(address_word_narrow), .din(write_data_word), .write_en(write_strobe),
.rclk(clock), .raddr(address_word_narrow), .dout(read_data_word));
assign oserdes_word = 8'b11100100;
end else if (0) begin
RAM_inferred_dual_port_gearbox #(
.GEARBOX_RATIO(4),
.ADDR_WIDTH_A(ADDRESS_DEPTH), .ADDR_WIDTH_B(ADDRESS_DEPTH_OSERDES),
.DATA_WIDTH_A(TRANSACTIONS_PER_DATA_WORD*BUS_WIDTH), .DATA_WIDTH_B(BUS_WIDTH_OSERDES)
) myram (
.clk_a(clock), .addr_a(address_word_narrow), .din_a(write_data_word), .write_en_a(write_strobe), .dout_a(read_data_word),
.clk_b(word_clock), .addr_b(read_address), .dout_b(oserdes_word));
end else if (0) begin
RAM_inferred_dual_port #(
.addr_width_a(ADDRESS_DEPTH), .addr_width_b(ADDRESS_DEPTH_OSERDES),
.data_width_a(TRANSACTIONS_PER_DATA_WORD*BUS_WIDTH), .data_width_b(BUS_WIDTH_OSERDES)
) myram (
.clk_a(clock), .addr_a(address_word_narrow), .din_a(write_data_word), .write_en_a(write_strobe), .dout_a(read_data_word),
.clk_b(word_clock), .addr_b(read_address), .din_b({BUS_WIDTH_OSERDES{1'b0}}), .write_en_b(1'b0), .dout_b());
assign oserdes_word = 8'b11100000;
end else if (0) begin
RAM_s6_8k_16bit_8bit mem (.reset(reset125),
.clock_a(clock), .address_a(address_word_reg), .data_in_a(write_data_word), .write_enable_a(write_strobe), .data_out_a(read_data_word),
.clock_b(word_clock), .address_b(read_address), .data_out_b(oserdes_word));
end else if (0) begin
RAM_s6_4k_32bit_8bit mem (.reset(reset125),
.clock_a(clock), .address_a(address_word_reg), .data_in_a(write_data_word), .write_enable_a(write_strobe), .data_out_a(read_data_word),
.clock_b(word_clock), .address_b(read_address), .data_out_b(oserdes_word));
end else begin
RAM_s6_16k_32bit_8bit mem (.reset(reset125),
.clock_a(clock), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe), .data_out_a(read_data_word),
.clock_b(word_clock), .address_b(read_address), .data_out_b(oserdes_word));
end
wire sync_read_address;
ocyrus_quad8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei4 (
.clock_in(clock125), .reset(reset125), .word_clock_out(word_clock), .locked(pll_oserdes_locked_1),
.word3_in(oserdes_word), .word2_in(oserdes_word), .word1_in(oserdes_word), .word0_in(oserdes_word),
.D3_out(coax[3]), .D2_out(), .D1_out(), .D0_out(coax[0]));
assign coax[1] = enable;
assign coax[2] = 0;
assign coax_led = 4'b1001;
if (0) begin
assign coax[4] = enable;
assign coax[5] = write_strobe;
assign pll_oserdes_locked_2 = 1;
end else if (0) begin
ocyrus_double8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei2 (
.clock_in(clock125), .reset(reset125), .word_clock_out(),
.word1_in(oserdes_word), .D1_out(coax[5]),
.word0_in(oserdes_word), .D0_out(coax[4]),
.bit_clock(), .bit_strobe(),
.locked(pll_oserdes_locked_2));
assign sync_read_address = 0;
end else if (0) begin
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .PINTYPE("n")) mylei (.clock_in(clock125), .reset(reset125), .word_clock_out(), .word_in(oserdes_word), .D_out(coax[5]), .locked(pll_oserdes_locked_2));
assign coax[4] = sync_out_stream[2];
assign sync_read_address = 0;
end else if (0) begin
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei (.clock_in(clock125), .reset(reset125), .word_clock_out(), .word_in(oserdes_word), .D_out(coax[4]), .locked(pll_oserdes_locked_2));
assign sync_read_address = coax[5];
end else begin
assign coax[4] = sync_out_stream[2];
assign sync_read_address = coax[5];
assign pll_oserdes_locked_2 = 1;
end
wire [31:0] start_read_address = 32'd0;
wire [31:0] end_read_address = 32'd46080;
reg [ADDRESS_DEPTH_OSERDES-1:0] last_read_address = 14'd4095;
reg sync_out_raw = 0;
reg [3:0] sync_out_stream = 0;
always @(posedge word_clock) begin
sync_out_raw <= 0;
if (reset125) begin
read_address <= start_read_address[ADDRESS_DEPTH_OSERDES-1:ADDRESS_DEPTH_OSERDES-ADDRESS_DEPTH];
last_read_address <= end_read_address[ADDRESS_DEPTH_OSERDES-1:ADDRESS_DEPTH_OSERDES-ADDRESS_DEPTH] - 1'b1;
end else begin
if (read_address==last_read_address || sync_read_address) begin
read_address <= start_read_address[ADDRESS_DEPTH_OSERDES-1:ADDRESS_DEPTH_OSERDES-ADDRESS_DEPTH];
last_read_address <= end_read_address[ADDRESS_DEPTH_OSERDES-1:ADDRESS_DEPTH_OSERDES-ADDRESS_DEPTH] - 1'b1;
sync_out_raw <= 1;
end else begin
read_address <= read_address + 1'b1;
end
end
sync_out_stream <= { sync_out_stream[2:0], sync_out_raw };
end
if (1) begin
assign led[7] = reset50;
assign led[6] = ~pll_locked;
assign led[5] = reset125;
assign led[4] = ~pll_oserdes_locked_1;
assign led[3] = ack_valid;
assign led[2] = read;
assign led[1] = enable;
assign led[0] = register_select;
end
initial begin
#100;
$display("%d = %d + %d + %d - %d", ADDRESS_DEPTH_OSERDES, ADDRESS_DEPTH, LOG2_OF_BUS_WIDTH, LOG2_OF_TRANSACTIONS_PER_DATA_WORD, LOG2_OF_OSERDES_DATA_WIDTH);
$display("%d, %d, %d", BUS_WIDTH, TRANSACTIONS_PER_DATA_WORD, TRANSACTIONS_PER_ADDRESS_WORD);
end
endmodule | module top #(
parameter BUS_WIDTH = 16,
parameter LOG2_OF_BUS_WIDTH = $clog2(BUS_WIDTH),
parameter TRANSACTIONS_PER_DATA_WORD = 2,
parameter LOG2_OF_TRANSACTIONS_PER_DATA_WORD = $clog2(TRANSACTIONS_PER_DATA_WORD),
parameter BUS_WIDTH_OSERDES = 8,
parameter TRANSACTIONS_PER_ADDRESS_WORD = 1,
parameter ADDRESS_DEPTH = 14,
parameter OSERDES_DATA_WIDTH = 8,
parameter LOG2_OF_OSERDES_DATA_WIDTH = $clog2(OSERDES_DATA_WIDTH),
parameter ADDRESS_DEPTH_OSERDES = ADDRESS_DEPTH + LOG2_OF_BUS_WIDTH + LOG2_OF_TRANSACTIONS_PER_DATA_WORD - LOG2_OF_OSERDES_DATA_WIDTH,
parameter ADDRESS_AUTOINCREMENT_MODE = 1,
parameter TESTBENCH = 0,
parameter COUNTER50_BIT_PICKOFF = TESTBENCH ? 5 : 23,
parameter COUNTER125_BIT_PICKOFF = TESTBENCH ? 5 : 23
) (
input clock50_p, clock50_n,
input clock10,
input reset,
inout [5:0] coax,
inout [BUS_WIDTH-1:0] bus,
input read,
input register_select,
input enable,
output ack_valid,
output [11:0] diff_pair_left,
output [11:0] diff_pair_right,
output [5:0] single_ended_left,
output [5:0] single_ended_right,
output [3:0] coax_led,
output [7:0] led
); |
genvar i;
wire pll_locked;
wire pll_oserdes_locked_1;
wire pll_oserdes_locked_2;
assign diff_pair_left[3] = 0;
assign diff_pair_left[2] = pll_oserdes_locked_1;
assign diff_pair_left[1] = pll_locked;
assign diff_pair_left[0] = write_strobe;
assign diff_pair_right[0] = read;
assign diff_pair_right[1] = register_select;
assign diff_pair_right[3] = ack_valid;
assign diff_pair_right[2] = enable;
assign diff_pair_left[11:4] = 8'h0;
assign diff_pair_right[11:4] = {4'h0, bus[3:0]};
for (i=0; i<6; i=i+1) begin : single_ended_array
assign single_ended_left[i] = 0;
assign single_ended_right[i] = 0;
end
reg [3:0] reset_counter = 0;
localparam RESET_PIPELINE_PICKOFF = 5;
reg [RESET_PIPELINE_PICKOFF:0] reset_pipeline50 = 0;
reg [RESET_PIPELINE_PICKOFF:0] reset_pipeline125 = 0;
reg reset50 = 1;
wire clock50;
IBUFGDS mybuf0 (.I(clock50_p), .IB(clock50_n), .O(clock50));
wire rawclock125;
wire clock125;
simpledcm_CLKGEN #(.MULTIPLY(10), .DIVIDE(4), .PERIOD(20.0)) mydcm_125 (.clockin(clock50), .reset(reset50), .clockout(rawclock125), .clockout180(), .locked(pll_locked));
BUFG mrt (.I(rawclock125), .O(clock125));
wire clock = clock125;
reg [COUNTER50_BIT_PICKOFF:0] counter50 = 0;
always @(posedge clock50) begin
if (reset_pipeline50[RESET_PIPELINE_PICKOFF:RESET_PIPELINE_PICKOFF-3]==4'b0011) begin
reset_counter <= reset_counter + 1'b1;
end else if (reset_pipeline50[RESET_PIPELINE_PICKOFF]) begin
counter50 <= 0;
reset50 <= 1;
end else if (reset50) begin
if (counter50[COUNTER50_BIT_PICKOFF]) begin
reset50 <= 0;
end
counter50 <= counter50 + 1'b1;
end
reset_pipeline50 <= { reset_pipeline50[RESET_PIPELINE_PICKOFF-1:0], reset };
end
reg [2:0] reset50_pipeline125 = 0;
localparam PLL_LOCKED_PIPELINE125_PICKOFF = 2;
reg [PLL_LOCKED_PIPELINE125_PICKOFF:0] pll_locked_pipeline125 = 0;
integer j;
always @(posedge clock125) begin
if (~pll_locked_pipeline125[PLL_LOCKED_PIPELINE125_PICKOFF]) begin
reset50_pipeline125 <= 0;
reset_pipeline125 <= 0;
end else begin
reset50_pipeline125 <= { reset50_pipeline125[1:0], reset50 };
reset_pipeline125 <= { reset_pipeline125[RESET_PIPELINE_PICKOFF-1:0], reset };
end
pll_locked_pipeline125 <= { pll_locked_pipeline125[PLL_LOCKED_PIPELINE125_PICKOFF-1:0], pll_locked };
end
reg [COUNTER125_BIT_PICKOFF:0] counter125 = 0;
reg reset125 = 1;
always @(posedge clock) begin
if (reset_pipeline125[RESET_PIPELINE_PICKOFF] || reset50_pipeline125[2] || ~pll_locked_pipeline125[PLL_LOCKED_PIPELINE125_PICKOFF]) begin
counter125 <= 0;
reset125 <= 1;
end else if (reset125) begin
if (counter125[COUNTER125_BIT_PICKOFF]) begin
reset125 <= 0;
end
counter125 <= counter125 + 1'b1;
end
end
wire [BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD-1:0] address_word_full;
wire [ADDRESS_DEPTH-1:0] address_word_narrow = address_word_full[ADDRESS_DEPTH-1:0];
wire [BUS_WIDTH*TRANSACTIONS_PER_DATA_WORD-1:0] write_data_word;
wire [BUS_WIDTH*TRANSACTIONS_PER_DATA_WORD-1:0] read_data_word;
half_duplex_rpi_bus #(
.BUS_WIDTH(BUS_WIDTH),
.TRANSACTIONS_PER_DATA_WORD(TRANSACTIONS_PER_DATA_WORD),
.TRANSACTIONS_PER_ADDRESS_WORD(TRANSACTIONS_PER_ADDRESS_WORD),
.ADDRESS_AUTOINCREMENT_MODE(ADDRESS_AUTOINCREMENT_MODE)
) hdrb (
.clock(clock),
.reset(reset125),
.bus(bus),
.read(read),
.register_select(register_select),
.enable(enable),
.ack_valid(ack_valid),
.write_strobe(write_strobe),
.write_data_word(write_data_word),
.read_data_word(read_data_word),
.address_word_reg(address_word_full)
);
wire word_clock;
wire [BUS_WIDTH_OSERDES-1:0] oserdes_word;
reg [ADDRESS_DEPTH_OSERDES-1:0] read_address = 0;
if (0) begin
RAM_inferred #(.addr_width(ADDRESS_DEPTH), .data_width(TRANSACTIONS_PER_DATA_WORD*BUS_WIDTH)) myram (.reset(reset125),
.wclk(clock), .waddr(address_word_narrow), .din(write_data_word), .write_en(write_strobe),
.rclk(clock), .raddr(address_word_narrow), .dout(read_data_word));
assign oserdes_word = 8'b11100100;
end else if (0) begin
RAM_inferred_dual_port_gearbox #(
.GEARBOX_RATIO(4),
.ADDR_WIDTH_A(ADDRESS_DEPTH), .ADDR_WIDTH_B(ADDRESS_DEPTH_OSERDES),
.DATA_WIDTH_A(TRANSACTIONS_PER_DATA_WORD*BUS_WIDTH), .DATA_WIDTH_B(BUS_WIDTH_OSERDES)
) myram (
.clk_a(clock), .addr_a(address_word_narrow), .din_a(write_data_word), .write_en_a(write_strobe), .dout_a(read_data_word),
.clk_b(word_clock), .addr_b(read_address), .dout_b(oserdes_word));
end else if (0) begin
RAM_inferred_dual_port #(
.addr_width_a(ADDRESS_DEPTH), .addr_width_b(ADDRESS_DEPTH_OSERDES),
.data_width_a(TRANSACTIONS_PER_DATA_WORD*BUS_WIDTH), .data_width_b(BUS_WIDTH_OSERDES)
) myram (
.clk_a(clock), .addr_a(address_word_narrow), .din_a(write_data_word), .write_en_a(write_strobe), .dout_a(read_data_word),
.clk_b(word_clock), .addr_b(read_address), .din_b({BUS_WIDTH_OSERDES{1'b0}}), .write_en_b(1'b0), .dout_b());
assign oserdes_word = 8'b11100000;
end else if (0) begin
RAM_s6_8k_16bit_8bit mem (.reset(reset125),
.clock_a(clock), .address_a(address_word_reg), .data_in_a(write_data_word), .write_enable_a(write_strobe), .data_out_a(read_data_word),
.clock_b(word_clock), .address_b(read_address), .data_out_b(oserdes_word));
end else if (0) begin
RAM_s6_4k_32bit_8bit mem (.reset(reset125),
.clock_a(clock), .address_a(address_word_reg), .data_in_a(write_data_word), .write_enable_a(write_strobe), .data_out_a(read_data_word),
.clock_b(word_clock), .address_b(read_address), .data_out_b(oserdes_word));
end else begin
RAM_s6_16k_32bit_8bit mem (.reset(reset125),
.clock_a(clock), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe), .data_out_a(read_data_word),
.clock_b(word_clock), .address_b(read_address), .data_out_b(oserdes_word));
end
wire sync_read_address;
ocyrus_quad8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei4 (
.clock_in(clock125), .reset(reset125), .word_clock_out(word_clock), .locked(pll_oserdes_locked_1),
.word3_in(oserdes_word), .word2_in(oserdes_word), .word1_in(oserdes_word), .word0_in(oserdes_word),
.D3_out(coax[3]), .D2_out(), .D1_out(), .D0_out(coax[0]));
assign coax[1] = enable;
assign coax[2] = 0;
assign coax_led = 4'b1001;
if (0) begin
assign coax[4] = enable;
assign coax[5] = write_strobe;
assign pll_oserdes_locked_2 = 1;
end else if (0) begin
ocyrus_double8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei2 (
.clock_in(clock125), .reset(reset125), .word_clock_out(),
.word1_in(oserdes_word), .D1_out(coax[5]),
.word0_in(oserdes_word), .D0_out(coax[4]),
.bit_clock(), .bit_strobe(),
.locked(pll_oserdes_locked_2));
assign sync_read_address = 0;
end else if (0) begin
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .PINTYPE("n")) mylei (.clock_in(clock125), .reset(reset125), .word_clock_out(), .word_in(oserdes_word), .D_out(coax[5]), .locked(pll_oserdes_locked_2));
assign coax[4] = sync_out_stream[2];
assign sync_read_address = 0;
end else if (0) begin
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL")) mylei (.clock_in(clock125), .reset(reset125), .word_clock_out(), .word_in(oserdes_word), .D_out(coax[4]), .locked(pll_oserdes_locked_2));
assign sync_read_address = coax[5];
end else begin
assign coax[4] = sync_out_stream[2];
assign sync_read_address = coax[5];
assign pll_oserdes_locked_2 = 1;
end
wire [31:0] start_read_address = 32'd0;
wire [31:0] end_read_address = 32'd46080;
reg [ADDRESS_DEPTH_OSERDES-1:0] last_read_address = 14'd4095;
reg sync_out_raw = 0;
reg [3:0] sync_out_stream = 0;
always @(posedge word_clock) begin
sync_out_raw <= 0;
if (reset125) begin
read_address <= start_read_address[ADDRESS_DEPTH_OSERDES-1:ADDRESS_DEPTH_OSERDES-ADDRESS_DEPTH];
last_read_address <= end_read_address[ADDRESS_DEPTH_OSERDES-1:ADDRESS_DEPTH_OSERDES-ADDRESS_DEPTH] - 1'b1;
end else begin
if (read_address==last_read_address || sync_read_address) begin
read_address <= start_read_address[ADDRESS_DEPTH_OSERDES-1:ADDRESS_DEPTH_OSERDES-ADDRESS_DEPTH];
last_read_address <= end_read_address[ADDRESS_DEPTH_OSERDES-1:ADDRESS_DEPTH_OSERDES-ADDRESS_DEPTH] - 1'b1;
sync_out_raw <= 1;
end else begin
read_address <= read_address + 1'b1;
end
end
sync_out_stream <= { sync_out_stream[2:0], sync_out_raw };
end
if (1) begin
assign led[7] = reset50;
assign led[6] = ~pll_locked;
assign led[5] = reset125;
assign led[4] = ~pll_oserdes_locked_1;
assign led[3] = ack_valid;
assign led[2] = read;
assign led[1] = enable;
assign led[0] = register_select;
end
initial begin
#100;
$display("%d = %d + %d + %d - %d", ADDRESS_DEPTH_OSERDES, ADDRESS_DEPTH, LOG2_OF_BUS_WIDTH, LOG2_OF_TRANSACTIONS_PER_DATA_WORD, LOG2_OF_OSERDES_DATA_WIDTH);
$display("%d, %d, %d", BUS_WIDTH, TRANSACTIONS_PER_DATA_WORD, TRANSACTIONS_PER_ADDRESS_WORD);
end
endmodule | 2 |
5,982 | data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v | 115,035,459 | mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v | v | 604 | 262 | [] | [] | [] | null | line:305: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:7: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:8: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:9: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:10: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:11: Cannot find include file: lib/half_duplex_rpi_bus.v\n`include "lib/half_duplex_rpi_bus.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:248: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:303: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:312: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:342: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:447: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:447: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:448: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:449: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:531: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:531: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:532: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:541: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:546: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Error: Exiting due to 5 error(s), 13 warning(s)\n' | 6,797 | module | module top_tb;
localparam HALF_PERIOD_OF_CONTROLLER = 1;
localparam HALF_PERIOD_OF_PERIPHERAL = 10;
localparam NUMBER_OF_PERIODS_OF_CONTROLLER_IN_A_DELAY = 1;
localparam NUMBER_OF_PERIODS_OF_CONTROLLER_WHILE_WAITING_FOR_ACK = 2000;
reg clock = 0;
localparam BUS_WIDTH = 16;
localparam ADDRESS_DEPTH = 14;
localparam TRANSACTIONS_PER_DATA_WORD = 2;
localparam TRANSACTIONS_PER_ADDRESS_WORD = 1;
localparam ADDRESS_AUTOINCREMENT_MODE = 1;
reg clock50_p = 0;
reg clock50_n = 1;
reg clock10 = 0;
reg reset = 0;
wire [5:0] coax;
wire [3:0] coax_led;
wire [7:0] led;
reg pre_register_select = 0;
reg register_select = 0;
reg pre_read = 0;
reg read = 0;
reg [BUS_WIDTH-1:0] pre_bus = 0;
wire [BUS_WIDTH-1:0] bus;
reg [BUS_WIDTH-1:0] eye_center = 0;
reg pre_enable = 0;
reg enable = 0;
wire a_n, a_p, c_n, c_p, d_n, d_p, f_n, f_p, b_n, b_p, e_n, e_p;
wire m_p, m_n, l_p, l_n, j_p, j_n, g_p, g_n, k_p, k_n, h_p, h_n;
wire z, y, x, w, v, u;
wire n, p, q, r, s, t;
reg [TRANSACTIONS_PER_DATA_WORD*BUS_WIDTH-1:0] wdata = 0;
reg [TRANSACTIONS_PER_DATA_WORD*BUS_WIDTH-1:0] rdata = 0;
bus_entry_3state #(.WIDTH(BUS_WIDTH)) my3sbe (.I(pre_bus), .O(bus), .T(~read));
top #(.BUS_WIDTH(BUS_WIDTH), .ADDRESS_DEPTH(ADDRESS_DEPTH), .TRANSACTIONS_PER_DATA_WORD(TRANSACTIONS_PER_DATA_WORD), .TRANSACTIONS_PER_ADDRESS_WORD(TRANSACTIONS_PER_ADDRESS_WORD), .ADDRESS_AUTOINCREMENT_MODE(ADDRESS_AUTOINCREMENT_MODE), .TESTBENCH(1)) althea (
.clock50_p(clock50_p), .clock50_n(clock50_n), .clock10(clock10), .reset(reset),
.coax(coax),
.diff_pair_left({ a_n, a_p, c_n, c_p, d_n, d_p, f_n, f_p, b_n, b_p, e_n, e_p }),
.diff_pair_right({ m_p, m_n, l_p, l_n, j_p, j_n, g_p, g_n, k_p, k_n, h_p, h_n }),
.single_ended_left({ z, y, x, w, v, u }),
.single_ended_right({ n, p, q, r, s, t }),
.bus(bus), .register_select(register_select), .read(read), .enable(enable), .ack_valid(ack_valid),
.led(led), .coax_led(coax_led)
);
task automatic peripheral_clock_delay;
input integer number_of_cycles;
integer j;
begin
for (j=0; j<2*number_of_cycles; j=j+1) begin : delay_thing_s
#HALF_PERIOD_OF_PERIPHERAL;
end
end
endtask
task automatic controller_clock_delay;
input integer number_of_cycles;
integer j;
begin
for (j=0; j<2*number_of_cycles; j=j+1) begin : delay_thing_m
#HALF_PERIOD_OF_CONTROLLER;
end
end
endtask
task automatic delay;
controller_clock_delay(NUMBER_OF_PERIODS_OF_CONTROLLER_IN_A_DELAY);
endtask
task automatic pulse_enable;
integer i;
integer j;
begin
i = 0;
pre_enable <= 1;
for (j=0; j<2*NUMBER_OF_PERIODS_OF_CONTROLLER_WHILE_WAITING_FOR_ACK; j=j+1) begin : delay_thing_1
if (ack_valid) begin
if (2==i) begin
eye_center <= bus;
end
i = i + 1;
j = 2*NUMBER_OF_PERIODS_OF_CONTROLLER_WHILE_WAITING_FOR_ACK - 100;
end
if (64<i) begin
pre_enable <= 0;
end
#HALF_PERIOD_OF_CONTROLLER;
end
if (pre_enable==1) begin
$finish;
end
end
endtask
task automatic a16_d32_controller_write_transaction;
input [15:0] address16;
input [31:0] data32;
begin
controller_set_address16(address16);
controller_write_data32(data32);
end
endtask
task automatic a16_controller_read_transaction;
input [15:0] address16;
integer j;
begin
controller_set_address16(address16);
end
endtask
task automatic controller_set_address16;
input [15:0] address16;
integer j;
begin
delay();
pre_read <= 0;
pre_register_select <= 0;
pre_bus <= address16[BUS_WIDTH-1:0];
pulse_enable();
delay();
$display("%t address: %04x", $time, address16);
end
endtask
task automatic controller_write_data32;
input [31:0] data32;
integer j;
begin
delay();
pre_read <= 0;
pre_register_select <= 1;
if (3<TRANSACTIONS_PER_DATA_WORD) begin
pre_bus <= data32[4*BUS_WIDTH-1:3*BUS_WIDTH];
pulse_enable();
wdata[4*BUS_WIDTH-1:3*BUS_WIDTH] <= eye_center;
end
if (2<TRANSACTIONS_PER_DATA_WORD) begin
pre_bus <= data32[3*BUS_WIDTH-1:2*BUS_WIDTH];
pulse_enable();
wdata[3*BUS_WIDTH-1:2*BUS_WIDTH] <= eye_center;
end
if (1<TRANSACTIONS_PER_DATA_WORD) begin
pre_bus <= data32[2*BUS_WIDTH-1:BUS_WIDTH];
pulse_enable();
wdata[2*BUS_WIDTH-1:BUS_WIDTH] <= eye_center;
end
pre_bus <= data32[BUS_WIDTH-1:0];
pulse_enable();
wdata[BUS_WIDTH-1:0] <= eye_center;
delay();
$display("%t wdata: %08x", $time, wdata);
end
endtask
task automatic controller_read_data32;
integer j;
begin
delay();
pre_read <= 1;
pre_register_select <= 1;
for (j=TRANSACTIONS_PER_DATA_WORD-1; j>=0; j=j-1) begin : read_data_multiple_2
pulse_enable();
if (3==j) begin
rdata[4*BUS_WIDTH-1:3*BUS_WIDTH] <= eye_center;
end else if (2==j) begin
rdata[3*BUS_WIDTH-1:2*BUS_WIDTH] <= eye_center;
end else if (1==j) begin
rdata[2*BUS_WIDTH-1:BUS_WIDTH] <= eye_center;
end else begin
rdata[BUS_WIDTH-1:0] <= eye_center;
end
end
delay();
$display("%t rdata: %08x", $time, rdata);
end
endtask
initial begin
#300; reset <= 1; #300; reset <= 0;
#512;
#512;
if (ADDRESS_AUTOINCREMENT_MODE) begin
controller_clock_delay(64);
peripheral_clock_delay(64);
controller_set_address16(16'h_2b4c);
controller_write_data32(32'h_3123_1507);
controller_write_data32(32'h_3123_1508);
controller_write_data32(32'h_3123_1509);
controller_write_data32(32'h_3123_150a);
controller_clock_delay(64);
peripheral_clock_delay(64);
controller_set_address16(16'h_2b4c);
controller_read_data32();
controller_read_data32();
controller_read_data32();
controller_read_data32();
end else begin
controller_clock_delay(64);
peripheral_clock_delay(64);
a16_d32_controller_write_transaction(.address16(16'h2b4c), .data32(32'h3123_1507));
controller_read_data32();
a16_d32_controller_write_transaction(.address16(16'h2b4d), .data32(32'h3123_1508));
controller_read_data32();
a16_d32_controller_write_transaction(.address16(16'h2b4e), .data32(32'h3123_1509));
controller_read_data32();
a16_d32_controller_write_transaction(.address16(16'h2b4f), .data32(32'h3123_150a));
controller_read_data32();
controller_clock_delay(64);
peripheral_clock_delay(64);
a16_controller_read_transaction(.address16(16'h2b4c));
a16_controller_read_transaction(.address16(16'h2b4d));
a16_controller_read_transaction(.address16(16'h2b4e));
a16_controller_read_transaction(.address16(16'h2b4f));
end
controller_clock_delay(64);
peripheral_clock_delay(64);
pre_register_select <= 1;
pre_read <= 1;
pre_bus <= 8'h33;
pulse_enable();
controller_set_address16(16'h1b4f);
controller_read_data32();
controller_clock_delay(64);
peripheral_clock_delay(64);
pre_register_select <= 1;
pre_read <= 0;
pre_bus <= 8'h66;
pulse_enable();
controller_set_address16(16'h4f1b);
controller_write_data32(32'h3123_2d78);
controller_clock_delay(64);
peripheral_clock_delay(64);
pre_register_select <= 0;
pre_read <= 0;
pre_bus <= 8'h99;
pulse_enable();
controller_set_address16(16'h1b4f);
controller_read_data32();
pre_register_select <= 0;
pre_read <= 0;
pre_enable <= 0;
controller_clock_delay(64);
peripheral_clock_delay(64);
#300; reset <= 1; #300; reset <= 0;
#300;
end
always @(posedge clock) begin
register_select <= #1 pre_register_select;
read <= #1 pre_read;
enable <= #1 pre_enable;
end
always begin
#HALF_PERIOD_OF_PERIPHERAL;
clock50_p <= #1.5 ~clock50_p;
clock50_n <= #2.5 ~clock50_n;
end
always begin
#HALF_PERIOD_OF_CONTROLLER;
clock <= #0.625 ~clock;
end
endmodule | module top_tb; |
localparam HALF_PERIOD_OF_CONTROLLER = 1;
localparam HALF_PERIOD_OF_PERIPHERAL = 10;
localparam NUMBER_OF_PERIODS_OF_CONTROLLER_IN_A_DELAY = 1;
localparam NUMBER_OF_PERIODS_OF_CONTROLLER_WHILE_WAITING_FOR_ACK = 2000;
reg clock = 0;
localparam BUS_WIDTH = 16;
localparam ADDRESS_DEPTH = 14;
localparam TRANSACTIONS_PER_DATA_WORD = 2;
localparam TRANSACTIONS_PER_ADDRESS_WORD = 1;
localparam ADDRESS_AUTOINCREMENT_MODE = 1;
reg clock50_p = 0;
reg clock50_n = 1;
reg clock10 = 0;
reg reset = 0;
wire [5:0] coax;
wire [3:0] coax_led;
wire [7:0] led;
reg pre_register_select = 0;
reg register_select = 0;
reg pre_read = 0;
reg read = 0;
reg [BUS_WIDTH-1:0] pre_bus = 0;
wire [BUS_WIDTH-1:0] bus;
reg [BUS_WIDTH-1:0] eye_center = 0;
reg pre_enable = 0;
reg enable = 0;
wire a_n, a_p, c_n, c_p, d_n, d_p, f_n, f_p, b_n, b_p, e_n, e_p;
wire m_p, m_n, l_p, l_n, j_p, j_n, g_p, g_n, k_p, k_n, h_p, h_n;
wire z, y, x, w, v, u;
wire n, p, q, r, s, t;
reg [TRANSACTIONS_PER_DATA_WORD*BUS_WIDTH-1:0] wdata = 0;
reg [TRANSACTIONS_PER_DATA_WORD*BUS_WIDTH-1:0] rdata = 0;
bus_entry_3state #(.WIDTH(BUS_WIDTH)) my3sbe (.I(pre_bus), .O(bus), .T(~read));
top #(.BUS_WIDTH(BUS_WIDTH), .ADDRESS_DEPTH(ADDRESS_DEPTH), .TRANSACTIONS_PER_DATA_WORD(TRANSACTIONS_PER_DATA_WORD), .TRANSACTIONS_PER_ADDRESS_WORD(TRANSACTIONS_PER_ADDRESS_WORD), .ADDRESS_AUTOINCREMENT_MODE(ADDRESS_AUTOINCREMENT_MODE), .TESTBENCH(1)) althea (
.clock50_p(clock50_p), .clock50_n(clock50_n), .clock10(clock10), .reset(reset),
.coax(coax),
.diff_pair_left({ a_n, a_p, c_n, c_p, d_n, d_p, f_n, f_p, b_n, b_p, e_n, e_p }),
.diff_pair_right({ m_p, m_n, l_p, l_n, j_p, j_n, g_p, g_n, k_p, k_n, h_p, h_n }),
.single_ended_left({ z, y, x, w, v, u }),
.single_ended_right({ n, p, q, r, s, t }),
.bus(bus), .register_select(register_select), .read(read), .enable(enable), .ack_valid(ack_valid),
.led(led), .coax_led(coax_led)
);
task automatic peripheral_clock_delay;
input integer number_of_cycles;
integer j;
begin
for (j=0; j<2*number_of_cycles; j=j+1) begin : delay_thing_s
#HALF_PERIOD_OF_PERIPHERAL;
end
end
endtask
task automatic controller_clock_delay;
input integer number_of_cycles;
integer j;
begin
for (j=0; j<2*number_of_cycles; j=j+1) begin : delay_thing_m
#HALF_PERIOD_OF_CONTROLLER;
end
end
endtask
task automatic delay;
controller_clock_delay(NUMBER_OF_PERIODS_OF_CONTROLLER_IN_A_DELAY);
endtask
task automatic pulse_enable;
integer i;
integer j;
begin
i = 0;
pre_enable <= 1;
for (j=0; j<2*NUMBER_OF_PERIODS_OF_CONTROLLER_WHILE_WAITING_FOR_ACK; j=j+1) begin : delay_thing_1
if (ack_valid) begin
if (2==i) begin
eye_center <= bus;
end
i = i + 1;
j = 2*NUMBER_OF_PERIODS_OF_CONTROLLER_WHILE_WAITING_FOR_ACK - 100;
end
if (64<i) begin
pre_enable <= 0;
end
#HALF_PERIOD_OF_CONTROLLER;
end
if (pre_enable==1) begin
$finish;
end
end
endtask
task automatic a16_d32_controller_write_transaction;
input [15:0] address16;
input [31:0] data32;
begin
controller_set_address16(address16);
controller_write_data32(data32);
end
endtask
task automatic a16_controller_read_transaction;
input [15:0] address16;
integer j;
begin
controller_set_address16(address16);
end
endtask
task automatic controller_set_address16;
input [15:0] address16;
integer j;
begin
delay();
pre_read <= 0;
pre_register_select <= 0;
pre_bus <= address16[BUS_WIDTH-1:0];
pulse_enable();
delay();
$display("%t address: %04x", $time, address16);
end
endtask
task automatic controller_write_data32;
input [31:0] data32;
integer j;
begin
delay();
pre_read <= 0;
pre_register_select <= 1;
if (3<TRANSACTIONS_PER_DATA_WORD) begin
pre_bus <= data32[4*BUS_WIDTH-1:3*BUS_WIDTH];
pulse_enable();
wdata[4*BUS_WIDTH-1:3*BUS_WIDTH] <= eye_center;
end
if (2<TRANSACTIONS_PER_DATA_WORD) begin
pre_bus <= data32[3*BUS_WIDTH-1:2*BUS_WIDTH];
pulse_enable();
wdata[3*BUS_WIDTH-1:2*BUS_WIDTH] <= eye_center;
end
if (1<TRANSACTIONS_PER_DATA_WORD) begin
pre_bus <= data32[2*BUS_WIDTH-1:BUS_WIDTH];
pulse_enable();
wdata[2*BUS_WIDTH-1:BUS_WIDTH] <= eye_center;
end
pre_bus <= data32[BUS_WIDTH-1:0];
pulse_enable();
wdata[BUS_WIDTH-1:0] <= eye_center;
delay();
$display("%t wdata: %08x", $time, wdata);
end
endtask
task automatic controller_read_data32;
integer j;
begin
delay();
pre_read <= 1;
pre_register_select <= 1;
for (j=TRANSACTIONS_PER_DATA_WORD-1; j>=0; j=j-1) begin : read_data_multiple_2
pulse_enable();
if (3==j) begin
rdata[4*BUS_WIDTH-1:3*BUS_WIDTH] <= eye_center;
end else if (2==j) begin
rdata[3*BUS_WIDTH-1:2*BUS_WIDTH] <= eye_center;
end else if (1==j) begin
rdata[2*BUS_WIDTH-1:BUS_WIDTH] <= eye_center;
end else begin
rdata[BUS_WIDTH-1:0] <= eye_center;
end
end
delay();
$display("%t rdata: %08x", $time, rdata);
end
endtask
initial begin
#300; reset <= 1; #300; reset <= 0;
#512;
#512;
if (ADDRESS_AUTOINCREMENT_MODE) begin
controller_clock_delay(64);
peripheral_clock_delay(64);
controller_set_address16(16'h_2b4c);
controller_write_data32(32'h_3123_1507);
controller_write_data32(32'h_3123_1508);
controller_write_data32(32'h_3123_1509);
controller_write_data32(32'h_3123_150a);
controller_clock_delay(64);
peripheral_clock_delay(64);
controller_set_address16(16'h_2b4c);
controller_read_data32();
controller_read_data32();
controller_read_data32();
controller_read_data32();
end else begin
controller_clock_delay(64);
peripheral_clock_delay(64);
a16_d32_controller_write_transaction(.address16(16'h2b4c), .data32(32'h3123_1507));
controller_read_data32();
a16_d32_controller_write_transaction(.address16(16'h2b4d), .data32(32'h3123_1508));
controller_read_data32();
a16_d32_controller_write_transaction(.address16(16'h2b4e), .data32(32'h3123_1509));
controller_read_data32();
a16_d32_controller_write_transaction(.address16(16'h2b4f), .data32(32'h3123_150a));
controller_read_data32();
controller_clock_delay(64);
peripheral_clock_delay(64);
a16_controller_read_transaction(.address16(16'h2b4c));
a16_controller_read_transaction(.address16(16'h2b4d));
a16_controller_read_transaction(.address16(16'h2b4e));
a16_controller_read_transaction(.address16(16'h2b4f));
end
controller_clock_delay(64);
peripheral_clock_delay(64);
pre_register_select <= 1;
pre_read <= 1;
pre_bus <= 8'h33;
pulse_enable();
controller_set_address16(16'h1b4f);
controller_read_data32();
controller_clock_delay(64);
peripheral_clock_delay(64);
pre_register_select <= 1;
pre_read <= 0;
pre_bus <= 8'h66;
pulse_enable();
controller_set_address16(16'h4f1b);
controller_write_data32(32'h3123_2d78);
controller_clock_delay(64);
peripheral_clock_delay(64);
pre_register_select <= 0;
pre_read <= 0;
pre_bus <= 8'h99;
pulse_enable();
controller_set_address16(16'h1b4f);
controller_read_data32();
pre_register_select <= 0;
pre_read <= 0;
pre_enable <= 0;
controller_clock_delay(64);
peripheral_clock_delay(64);
#300; reset <= 1; #300; reset <= 0;
#300;
end
always @(posedge clock) begin
register_select <= #1 pre_register_select;
read <= #1 pre_read;
enable <= #1 pre_enable;
end
always begin
#HALF_PERIOD_OF_PERIPHERAL;
clock50_p <= #1.5 ~clock50_p;
clock50_n <= #2.5 ~clock50_n;
end
always begin
#HALF_PERIOD_OF_CONTROLLER;
clock <= #0.625 ~clock;
end
endmodule | 2 |
5,983 | data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v | 115,035,459 | mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v | v | 604 | 262 | [] | [] | [] | null | line:305: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:7: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:8: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:9: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:10: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:11: Cannot find include file: lib/half_duplex_rpi_bus.v\n`include "lib/half_duplex_rpi_bus.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:248: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:303: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:312: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:342: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:447: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:447: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:448: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:449: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:531: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:531: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:532: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:541: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test049.simple-parallel-interface-and-pollable-memory.althea.revB.rpi1-26pin.v:546: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Error: Exiting due to 5 error(s), 13 warning(s)\n' | 6,797 | module | module myalthea (
input clock50_p, clock50_n,
inout [5:0] coax,
output rpi_gpio2_i2c1_sda,
input rpi_gpio3_i2c1_scl,
input rpi_gpio4_gpclk0,
input rpi_gpio7_spi_ce1,
inout rpi_gpio8_spi_ce0, rpi_gpio9_spi_miso, rpi_gpio10_spi_mosi, rpi_gpio11_spi_sclk,
inout
a_p, a_n, b_p, b_n, c_p, c_n,
d_p, d_n, e_p, e_n, f_p, f_n,
g_p, g_n, h_p, h_n, j_p, j_n,
k_p, k_n, l_p, l_n, m_p, m_n,
n, p, q, r, s, t,
u, v, w, x, y, z,
input button,
output [3:0] coax_led,
output [7:0] led
);
localparam BUS_WIDTH = 4;
localparam ADDRESS_DEPTH = 14;
localparam TRANSACTIONS_PER_DATA_WORD = 8;
localparam TRANSACTIONS_PER_ADDRESS_WORD = 4;
localparam ADDRESS_AUTOINCREMENT_MODE = 1;
wire clock10 = 0;
top #(
.TESTBENCH(0),
.BUS_WIDTH(BUS_WIDTH), .ADDRESS_DEPTH(ADDRESS_DEPTH),
.TRANSACTIONS_PER_DATA_WORD(TRANSACTIONS_PER_DATA_WORD),
.TRANSACTIONS_PER_ADDRESS_WORD(TRANSACTIONS_PER_ADDRESS_WORD),
.ADDRESS_AUTOINCREMENT_MODE(ADDRESS_AUTOINCREMENT_MODE)
) althea (
.clock50_p(clock50_p), .clock50_n(clock50_n), .clock10(clock10), .reset(~button),
.coax(coax),
.bus({ rpi_gpio11_spi_sclk, rpi_gpio10_spi_mosi, rpi_gpio9_spi_miso, rpi_gpio8_spi_ce0 }),
.diff_pair_left({ a_n, a_p, c_n, c_p, d_n, d_p, f_n, f_p, b_n, b_p, e_n, e_p }),
.diff_pair_right({ g_n, g_p, j_n, j_p, l_n, l_p, m_n, m_p, h_n, h_p, k_n, k_p }),
.single_ended_left({ z, y, x, w, v, u }),
.single_ended_right({ n, p, q, r, s, t }),
.register_select(rpi_gpio3_i2c1_scl), .read(rpi_gpio7_spi_ce1),
.enable(rpi_gpio4_gpclk0), .ack_valid(rpi_gpio2_i2c1_sda),
.coax_led(coax_led),
.led(led)
);
endmodule | module myalthea (
input clock50_p, clock50_n,
inout [5:0] coax,
output rpi_gpio2_i2c1_sda,
input rpi_gpio3_i2c1_scl,
input rpi_gpio4_gpclk0,
input rpi_gpio7_spi_ce1,
inout rpi_gpio8_spi_ce0, rpi_gpio9_spi_miso, rpi_gpio10_spi_mosi, rpi_gpio11_spi_sclk,
inout
a_p, a_n, b_p, b_n, c_p, c_n,
d_p, d_n, e_p, e_n, f_p, f_n,
g_p, g_n, h_p, h_n, j_p, j_n,
k_p, k_n, l_p, l_n, m_p, m_n,
n, p, q, r, s, t,
u, v, w, x, y, z,
input button,
output [3:0] coax_led,
output [7:0] led
); |
localparam BUS_WIDTH = 4;
localparam ADDRESS_DEPTH = 14;
localparam TRANSACTIONS_PER_DATA_WORD = 8;
localparam TRANSACTIONS_PER_ADDRESS_WORD = 4;
localparam ADDRESS_AUTOINCREMENT_MODE = 1;
wire clock10 = 0;
top #(
.TESTBENCH(0),
.BUS_WIDTH(BUS_WIDTH), .ADDRESS_DEPTH(ADDRESS_DEPTH),
.TRANSACTIONS_PER_DATA_WORD(TRANSACTIONS_PER_DATA_WORD),
.TRANSACTIONS_PER_ADDRESS_WORD(TRANSACTIONS_PER_ADDRESS_WORD),
.ADDRESS_AUTOINCREMENT_MODE(ADDRESS_AUTOINCREMENT_MODE)
) althea (
.clock50_p(clock50_p), .clock50_n(clock50_n), .clock10(clock10), .reset(~button),
.coax(coax),
.bus({ rpi_gpio11_spi_sclk, rpi_gpio10_spi_mosi, rpi_gpio9_spi_miso, rpi_gpio8_spi_ce0 }),
.diff_pair_left({ a_n, a_p, c_n, c_p, d_n, d_p, f_n, f_p, b_n, b_p, e_n, e_p }),
.diff_pair_right({ g_n, g_p, j_n, j_p, l_n, l_p, m_n, m_p, h_n, h_p, k_n, k_p }),
.single_ended_left({ z, y, x, w, v, u }),
.single_ended_right({ n, p, q, r, s, t }),
.register_select(rpi_gpio3_i2c1_scl), .read(rpi_gpio7_spi_ce1),
.enable(rpi_gpio4_gpclk0), .ack_valid(rpi_gpio2_i2c1_sda),
.coax_led(coax_led),
.led(led)
);
endmodule | 2 |
5,984 | data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v | 115,035,459 | mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v | v | 743 | 357 | [] | [] | [] | null | line:304: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:6: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:7: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:9: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:10: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:11: Cannot find include file: lib/half_duplex_rpi_bus.v\n`include "lib/half_duplex_rpi_bus.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:12: Cannot find include file: lib/sequencer.v\n`include "lib/sequencer.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:13: Cannot find include file: lib/reset.v\n`include "lib/reset.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:14: Cannot find include file: lib/histogram.v\n`include "lib/histogram.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:15: Cannot find include file: lib/fifo.v\n`include "lib/fifo.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:198: Define or directive not defined: \'`LOG2_OF_BASE_BLOCK_MEMORY_SIZE\'\n localparam PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + LOG2_OF_OSERDES_DATA_WIDTH - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:198: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + LOG2_OF_OSERDES_DATA_WIDTH - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:372: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:428: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:437: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:467: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:572: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:572: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:573: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:574: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:659: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:659: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:660: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:669: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:674: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Error: Exiting due to 11 error(s), 13 warning(s)\n' | 6,800 | module | module top #(
parameter BUS_WIDTH = 16,
parameter LOG2_OF_BUS_WIDTH = $clog2(BUS_WIDTH),
parameter TRANSACTIONS_PER_DATA_WORD = 2,
parameter LOG2_OF_TRANSACTIONS_PER_DATA_WORD = $clog2(TRANSACTIONS_PER_DATA_WORD),
parameter OSERDES_DATA_WIDTH = 8,
parameter TRANSACTIONS_PER_ADDRESS_WORD = 1,
parameter BANK_ADDRESS_DEPTH = 14,
parameter LOG2_OF_NUMBER_OF_BANKS = BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD - BANK_ADDRESS_DEPTH,
parameter NUMBER_OF_BANKS = 1<<LOG2_OF_NUMBER_OF_BANKS,
parameter LOG2_OF_OSERDES_DATA_WIDTH = $clog2(OSERDES_DATA_WIDTH),
parameter ADDRESS_DEPTH_OSERDES = BANK_ADDRESS_DEPTH + LOG2_OF_BUS_WIDTH + LOG2_OF_TRANSACTIONS_PER_DATA_WORD - LOG2_OF_OSERDES_DATA_WIDTH,
parameter ADDRESS_AUTOINCREMENT_MODE = 1,
parameter TESTBENCH = 0,
parameter WRITE_STROBE_PICKOFF = 17,
parameter COUNTER100_BIT_PICKOFF = TESTBENCH ? 5 : 23,
parameter COUNTERWORD_BIT_PICKOFF = TESTBENCH ? 5 : 23
) (
input clock100_p, clock100_n,
input clock10,
input reset,
inout [5:0] coax,
input [2:0] rot,
inout [BUS_WIDTH-1:0] bus,
input read,
input register_select,
input enable,
output ack_valid,
output [11:0] diff_pair_left,
output [11:0] diff_pair_right,
inout [5:0] single_ended_left,
inout [5:0] single_ended_right,
output [3:0] coax_led,
output [7:0] led
);
localparam ERROR_COUNT_PICKOFF = 7;
wire [3:0] status4;
wire [7:0] status8;
genvar i;
wire pll_oserdes_locked;
wire pll_oserdes_locked_2;
for (i=0; i<12; i=i+1) begin : diff_pair_array
assign diff_pair_left[i] = 0;
assign diff_pair_right[i] = 0;
end
assign single_ended_left[5:2] = 0;
assign single_ended_left[0] = 0;
assign single_ended_right[5:4] = 0;
assign single_ended_right[1:0] = 0;
wire reset100;
wire clock100;
IBUFGDS mybuf0 (.I(clock100_p), .IB(clock100_n), .O(clock100));
wire word_clock0;
wire word_clock1;
wire clock = word_clock0;
reset_wait4pll #(.COUNTER_BIT_PICKOFF(COUNTER100_BIT_PICKOFF)) reset100_wait4pll (.reset_input(reset), .pll_locked_input(1'b1), .clock_input(clock100), .reset_output(reset100));
wire reset_word0;
wire reset_word1;
reset_wait4pll #(.COUNTER_BIT_PICKOFF(COUNTERWORD_BIT_PICKOFF)) resetword_wait4pll (.reset_input(reset100), .pll_locked_input(pll_oserdes_locked), .clock_input(word_clock0), .reset_output(reset_word0));
reset_wait4pll #(.COUNTER_BIT_PICKOFF(COUNTERWORD_BIT_PICKOFF)) resetword1_wait4pll (.reset_input(reset100), .pll_locked_input(pll_oserdes_locked), .clock_input(word_clock1), .reset_output(reset_word1));
wire [BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD-1:0] address_word_full;
wire [BANK_ADDRESS_DEPTH-1:0] address_word_narrow = address_word_full[BANK_ADDRESS_DEPTH-1:0];
wire [BUS_WIDTH*TRANSACTIONS_PER_DATA_WORD-1:0] write_data_word;
wire [BUS_WIDTH*TRANSACTIONS_PER_DATA_WORD-1:0] read_data_word [NUMBER_OF_BANKS-1:0];
wire [LOG2_OF_NUMBER_OF_BANKS-1:0] bank;
wire [LOG2_OF_NUMBER_OF_BANKS-1:0] write_strobe;
wire [ERROR_COUNT_PICKOFF:0] hdrb_read_errors;
wire [ERROR_COUNT_PICKOFF:0] hdrb_write_errors;
wire [ERROR_COUNT_PICKOFF:0] hdrb_address_errors;
half_duplex_rpi_bus #(
.BUS_WIDTH(BUS_WIDTH),
.TRANSACTIONS_PER_DATA_WORD(TRANSACTIONS_PER_DATA_WORD),
.TRANSACTIONS_PER_ADDRESS_WORD(TRANSACTIONS_PER_ADDRESS_WORD),
.BANK_ADDRESS_DEPTH(BANK_ADDRESS_DEPTH),
.ADDRESS_AUTOINCREMENT_MODE(ADDRESS_AUTOINCREMENT_MODE)
) hdrb (
.clock(word_clock0),
.reset(reset_word0),
.bus(bus),
.read(read),
.register_select(register_select),
.enable(enable),
.ack_valid(ack_valid),
.write_strobe(write_strobe),
.write_data_word(write_data_word),
.read_data_word(read_data_word[bank]),
.address_word_reg(address_word_full),
.read_errors(hdrb_read_errors),
.write_errors(hdrb_write_errors),
.address_errors(hdrb_address_errors),
.bank(bank)
);
wire [OSERDES_DATA_WIDTH-1:0] potential_oserdes_word [NUMBER_OF_BANKS-1:0];
wire [OSERDES_DATA_WIDTH-1:0] oserdes_word [NUMBER_OF_BANKS-1:0];
wire [7:0] oserdes_word_delayed;
wire [7:0] oserdes_word1_buffer;
wire [7:0] oserdes_word1_buffer_delayed;
wire [7:0] iserdes_word;
wire [7:0] iserdes_word_buffer;
wire [7:0] iserdes_word_buffer0;
wire [7:0] iserdes_word_buffer_delayed;
wire [ADDRESS_DEPTH_OSERDES-1:0] read_address;
wire [31:0] bank1 [15:0];
wire [31:0] bank2 [15:0];
reg [WRITE_STROBE_PICKOFF:0] counter = 0;
reg write_strobe_b = 0;
always @(posedge word_clock0) begin
write_strobe_b <= 0;
if (reset_word0) begin
counter <= 0;
end else begin
if (counter[WRITE_STROBE_PICKOFF:0]==0) begin
write_strobe_b <= 1;
end
counter <= counter + 1'b1;
end
end
if (0) begin
if (BANK_ADDRESS_DEPTH==12) begin
RAM_s6_4k_32bit_8bit #(.ENDIANNESS("BIG")) mem0 (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[0]), .data_out_a(read_data_word[0]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[0]));
RAM_s6_4k_32bit_8bit #(.ENDIANNESS("BIG")) mem1 (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[1]), .data_out_a(read_data_word[1]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[1]));
RAM_s6_4k_32bit_8bit #(.ENDIANNESS("BIG")) mem2 (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[2]), .data_out_a(read_data_word[2]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[2]));
RAM_s6_4k_32bit_8bit #(.ENDIANNESS("BIG")) mem3 (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[3]), .data_out_a(read_data_word[3]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[3]));
end else if (BANK_ADDRESS_DEPTH==13) begin
RAM_s6_8k_32bit_8bit #(.ENDIANNESS("BIG")) mem0 (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[0]), .data_out_a(read_data_word[0]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[0]));
RAM_s6_8k_32bit_8bit #(.ENDIANNESS("BIG")) mem1 (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[1]), .data_out_a(read_data_word[1]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[1]));
end else begin
RAM_s6_16k_32bit_8bit #(.ENDIANNESS("BIG")) mem (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[0]), .data_out_a(read_data_word[0]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[0]));
end
end else begin
for (i=3; i<NUMBER_OF_BANKS; i=i+1) begin : fakebanks
assign read_data_word[i] = 0;
end
for (i=1; i<NUMBER_OF_BANKS; i=i+1) begin : banksfake
assign potential_oserdes_word[i] = 0;
end
RAM_s6_4k_32bit_8bit #(.ENDIANNESS("BIG")) mem_bank0 (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[0]), .data_out_a(read_data_word[0]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[0]));
RAM_inferred_with_register_inputs #(.ADDR_WIDTH(4), .DATA_WIDTH(32)) riwri_bank1 (.clock(word_clock0), .reset(reset_word0),
.raddress_a(address_word_full[3:0]), .data_out_a(read_data_word[1]),
.data_in_b_0(bank1[0]), .data_in_b_1(bank1[1]), .data_in_b_2(bank1[2]), .data_in_b_3(bank1[3]),
.data_in_b_4(bank1[4]), .data_in_b_5(bank1[5]), .data_in_b_6(bank1[6]), .data_in_b_7(bank1[7]),
.data_in_b_8(bank1[8]), .data_in_b_9(bank1[9]), .data_in_b_a(bank1[10]), .data_in_b_b(bank1[11]),
.data_in_b_c(bank1[12]), .data_in_b_d(bank1[13]), .data_in_b_e(bank1[14]), .data_in_b_f(bank1[15]),
.write_strobe_b(write_strobe_b));
RAM_inferred_with_register_outputs #(.ADDR_WIDTH(4), .DATA_WIDTH(32)) riwro_bank2 (.clock(word_clock0), .reset(reset_word0),
.waddress_a(address_word_full[3:0]), .data_in_a(write_data_word), .write_strobe_a(write_strobe[2]),
.raddress_a(address_word_full[3:0]), .data_out_a(read_data_word[2]),
.data_out_b_0(bank2[0]), .data_out_b_1(bank2[1]), .data_out_b_2(bank2[2]), .data_out_b_3(bank2[3]),
.data_out_b_4(bank2[4]), .data_out_b_5(bank2[5]), .data_out_b_6(bank2[6]), .data_out_b_7(bank2[7]),
.data_out_b_8(bank2[8]), .data_out_b_9(bank2[9]), .data_out_b_a(bank2[10]), .data_out_b_b(bank2[11]),
.data_out_b_c(bank2[12]), .data_out_b_d(bank2[13]), .data_out_b_e(bank2[14]), .data_out_b_f(bank2[15]));
end
wire [2:0] rot_pipeline;
localparam LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE = 24;
localparam PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + LOG2_OF_OSERDES_DATA_WIDTH - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE;
localparam LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO < 0 ? 0 : PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO;
localparam PADDING = 24 - LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE;
wire [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count [3:0];
wire [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] pipelined_count [3:0];
reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] previous_count [3:0];
wire [OSERDES_DATA_WIDTH-1:0] result [3:0];
wire [OSERDES_DATA_WIDTH-1:0] pipelined_result [3:0];
reg [OSERDES_DATA_WIDTH-1:0] previous_result [3:0];
wire [LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO-1:0] capture_completion;
wire partial_count_reached;
wire max_count_reached;
wire adding_finished;
wire result_valid;
assign coax[1] = partial_count_reached;
assign coax[2] = adding_finished;
assign coax[3] = result_valid;
wire [3:0] histogram_status4 = { result_valid, adding_finished, max_count_reached, partial_count_reached };
wire [31:0] histogram_error_count;
assign bank1[0] = { oserdes_word[3], oserdes_word[2], oserdes_word[1], oserdes_word[0] };
assign bank1[1] = { oserdes_word_delayed, 8'd0, oserdes_word1_buffer, oserdes_word1_buffer_delayed };
assign bank1[2] = { iserdes_word, 8'd0, iserdes_word_buffer, iserdes_word_buffer_delayed };
assign bank1[3] = hdrb_read_errors;
assign bank1[4] = hdrb_write_errors;
assign bank1[5] = hdrb_address_errors;
assign bank1[6] = { capture_completion, histogram_status4, rot_pipeline, status4, status8 };
assign bank1[7] = histogram_error_count;
assign bank1[8] = { {PADDING{1'b0}}, previous_count[0], previous_result[0] };
assign bank1[9] = { {PADDING{1'b0}}, previous_count[1], previous_result[1] };
assign bank1[10] = { {PADDING{1'b0}}, previous_count[2], previous_result[2] };
assign bank1[11] = { {PADDING{1'b0}}, previous_count[3], previous_result[3] };
assign bank1[12] = { {PADDING{1'b0}}, count[0], result[0] };
assign bank1[13] = { {PADDING{1'b0}}, count[1], result[1] };
assign bank1[14] = { {PADDING{1'b0}}, count[2], result[2] };
assign bank1[15] = { {PADDING{1'b0}}, count[3], result[3] };
wire [2:0] bitslip_iserdes = bank2[0][2:0];
wire [2:0] bitslip_oserdes1 = bank2[1][2:0];
(* KEEP = "TRUE" *)
wire [1:0] word_clock_sel = bank2[3][1:0];
wire train_oserdes = bank2[4][0];
wire [7:0] train_oserdes_pattern = bank2[5][7:0];
wire [31:0] start_sample = bank2[6][31:0];
wire [31:0] end_sample = bank2[7][31:0];
wire enable_histogram_sampling = bank2[8][0];
wire clear_histogram_results = bank2[8][1];
pipeline #(.WIDTH(8), .DEPTH(3)) kings (.clock(word_clock0), .in(iserdes_word_buffer), .out(iserdes_word_buffer0));
localparam RESULT_VALID_PIPELINE_PICKOFF = 1;
reg [RESULT_VALID_PIPELINE_PICKOFF:0] result_valid_pipeline = 0;
pipeline #(.WIDTH(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) kongs0 (.clock(word_clock0), .in(count[0]), .out(pipelined_count[0]));
pipeline #(.WIDTH(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) kongs1 (.clock(word_clock0), .in(count[1]), .out(pipelined_count[1]));
pipeline #(.WIDTH(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) kongs2 (.clock(word_clock0), .in(count[2]), .out(pipelined_count[2]));
pipeline #(.WIDTH(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) kongs3 (.clock(word_clock0), .in(count[3]), .out(pipelined_count[3]));
pipeline #(.WIDTH(OSERDES_DATA_WIDTH), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) mothra0 (.clock(word_clock0), .in(result[0]), .out(pipelined_result[0]));
pipeline #(.WIDTH(OSERDES_DATA_WIDTH), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) mothra1 (.clock(word_clock0), .in(result[1]), .out(pipelined_result[1]));
pipeline #(.WIDTH(OSERDES_DATA_WIDTH), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) mothra2 (.clock(word_clock0), .in(result[2]), .out(pipelined_result[2]));
pipeline #(.WIDTH(OSERDES_DATA_WIDTH), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) mothra3 (.clock(word_clock0), .in(result[3]), .out(pipelined_result[3]));
for (i=0; i<4; i=i+1) begin : previous_histogram
always @(posedge word_clock0) begin
if (reset_word0) begin
previous_count[i] <= 0;
previous_result[i] <= 0;
end else begin
if (result_valid_pipeline[RESULT_VALID_PIPELINE_PICKOFF -: 2]==2'b10) begin
previous_count[i] <= pipelined_count[i];
previous_result[i] <= pipelined_result[i];
end
end
end
end
always @(posedge word_clock0) begin
if (reset_word0) begin
result_valid_pipeline <= 0;
end else begin
result_valid_pipeline <= { result_valid_pipeline[RESULT_VALID_PIPELINE_PICKOFF-1:0], result_valid };
end
end
histogram #(.DATA_WIDTH(OSERDES_DATA_WIDTH), .LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE), .USE_BLOCK_MEMORY(1)) h1n1 (
.clock(word_clock0), .reset(reset_word0), .clear_results(clear_histogram_results), .data_in(iserdes_word_buffer0), .sample(enable_histogram_sampling),
.result00(result[0]), .result01(result[1]), .result02(result[2]), .result03(result[3]),
.count00(count[0]), .count01(count[1]), .count02(count[2]), .count03(count[3]),
.capture_completion(capture_completion), .partial_count_reached(partial_count_reached), .max_count_reached(max_count_reached),
.adding_finished(adding_finished), .result_valid(result_valid), .error_count(histogram_error_count));
for (i=0; i<NUMBER_OF_BANKS; i=i+1) begin : train_or_regular
assign oserdes_word[i] = train_oserdes ? train_oserdes_pattern : potential_oserdes_word[i];
end
wire sync_read_address;
wire [3:0] sync_out_stream;
wire [7:0] sync_out_word;
wire [7:0] sync_out_word_delayed;
sequencer_sync #(.ADDRESS_DEPTH_OSERDES(ADDRESS_DEPTH_OSERDES), .LOG2_OF_OSERDES_DATA_WIDTH(LOG2_OF_OSERDES_DATA_WIDTH)) ss (.clock(word_clock0), .reset(reset_word0), .sync_read_address(sync_read_address), .start_sample(start_sample), .end_sample(end_sample), .read_address(read_address), .sync_out_stream(sync_out_stream), .sync_out_word(sync_out_word));
cdc_pipeline #(.WIDTH(3), .DEPTH(3)) tongs (.clock(word_clock0), .in(~rot), .out(rot_pipeline));
cdc_pipeline #(.WIDTH(8), .DEPTH(3)) publics (.clock(word_clock1), .in(iserdes_word), .out(iserdes_word_buffer));
bitslip #(.WIDTH(8)) bsi (.clock(word_clock1), .bitslip(bitslip_iserdes), .data_in(iserdes_word_buffer), .data_out(iserdes_word_buffer_delayed));
localparam DELAY = 7;
pipeline #(.WIDTH(8), .DEPTH(DELAY+4)) queens (.clock(word_clock0), .in(oserdes_word[0]), .out(oserdes_word_delayed));
pipeline #(.WIDTH(8), .DEPTH(DELAY+4)) diamond_head (.clock(word_clock0), .in(sync_out_word), .out(sync_out_word_delayed));
bitslip #(.WIDTH(8)) bso1 (.clock(word_clock1), .bitslip(bitslip_oserdes1), .data_in(oserdes_word[0]), .data_out(oserdes_word1_buffer));
pipeline #(.WIDTH(8), .DEPTH(DELAY)) kewalos (.clock(word_clock1), .in(oserdes_word1_buffer), .out(oserdes_word1_buffer_delayed));
wire pre_coax_4;
ocyrus_hex8_split_4_2 #(.BIT_DEPTH(8), .PERIOD(10.0), .MULTIPLY(10), .DIVIDE(1), .SCOPE("BUFPLL"), .PHASE45(0.0)) mylei6 (
.clock_in(clock100), .reset(reset100), .word_clock0123_out(word_clock1), .locked(pll_oserdes_locked),
.word_clock45_sel(word_clock_sel[1:0]), .word_clock45_out(word_clock0),
.word0_in(oserdes_word1_buffer_delayed), .word1_in(oserdes_word1_buffer), .word2_in(oserdes_word1_buffer), .word3_in(iserdes_word_buffer_delayed),
.word4_in(oserdes_word_delayed), .word5_in(sync_out_word_delayed),
.D0_out(pre_coax_4), .D1_out(single_ended_left[1]), .D2_out(single_ended_right[2]), .D3_out(coax[5]),
.D4_out(coax[0]), .D5_out(),
.iserdes_bit_input(single_ended_right[3]), .iserdes_word_out(iserdes_word));
assign coax[4] = pre_coax_4;
if (0) begin
assign coax[4] = enable;
assign coax[5] = write_strobe[0];
assign pll_oserdes_locked_2 = 1;
end else if (0) begin
ocyrus_double8 #(.BIT_DEPTH(8), .PERIOD(10.0), .MULTIPLY(10), .DIVIDE(1), .SCOPE("BUFPLL")) mylei2 (
.clock_in(clock100), .reset(reset100), .word_clock_out(),
.word1_in(oserdes_word[0]), .D1_out(coax[5]),
.word0_in(oserdes_word[0]), .D0_out(coax[4]),
.bit_clock(), .bit_strobe(),
.locked(pll_oserdes_locked_2));
assign sync_read_address = 0;
end else if (0) begin
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(10.0), .MULTIPLY(10), .DIVIDE(1), .SCOPE("BUFPLL")) mylei (.clock_in(clock100), .reset(reset100), .word_clock_out(), .word_in(oserdes_word[0]), .D_out(coax[5]), .locked(pll_oserdes_locked_2));
assign coax[4] = sync_out_stream[2];
assign sync_read_address = 0;
end else if (1) begin
assign sync_read_address = 0;
assign pll_oserdes_locked_2 = 1;
end else begin
assign coax[4] = sync_out_stream[2];
assign sync_read_address = coax[5];
assign pll_oserdes_locked_2 = 1;
end
assign status4[3:0] = bank;
assign status8[7] = reset100;
assign status8[6] = ~pll_oserdes_locked;
assign status8[5] = reset_word0;
assign status8[4] = reset_word1;
assign status8[3] = ack_valid;
assign status8[2] = read;
assign status8[1] = enable;
assign status8[0] = register_select;
if (1) begin
cdc_pipeline #(.WIDTH(8), .DEPTH(2)) blinx (.clock(clock100), .in(status8), .out(led));
end
if (1) begin
cdc_pipeline #(.WIDTH(4), .DEPTH(2)) jarjar (.clock(clock100), .in(status4), .out(coax_led));
end
initial begin
#100;
$display("%d = %d + %d + %d - %d", ADDRESS_DEPTH_OSERDES, BANK_ADDRESS_DEPTH, LOG2_OF_BUS_WIDTH, LOG2_OF_TRANSACTIONS_PER_DATA_WORD, LOG2_OF_OSERDES_DATA_WIDTH);
$display("BUS_WIDTH=%d, TRANSACTIONS_PER_DATA_WORD=%d, TRANSACTIONS_PER_ADDRESS_WORD=%d", BUS_WIDTH, TRANSACTIONS_PER_DATA_WORD, TRANSACTIONS_PER_ADDRESS_WORD);
$display("%d banks", NUMBER_OF_BANKS);
end
endmodule | module top #(
parameter BUS_WIDTH = 16,
parameter LOG2_OF_BUS_WIDTH = $clog2(BUS_WIDTH),
parameter TRANSACTIONS_PER_DATA_WORD = 2,
parameter LOG2_OF_TRANSACTIONS_PER_DATA_WORD = $clog2(TRANSACTIONS_PER_DATA_WORD),
parameter OSERDES_DATA_WIDTH = 8,
parameter TRANSACTIONS_PER_ADDRESS_WORD = 1,
parameter BANK_ADDRESS_DEPTH = 14,
parameter LOG2_OF_NUMBER_OF_BANKS = BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD - BANK_ADDRESS_DEPTH,
parameter NUMBER_OF_BANKS = 1<<LOG2_OF_NUMBER_OF_BANKS,
parameter LOG2_OF_OSERDES_DATA_WIDTH = $clog2(OSERDES_DATA_WIDTH),
parameter ADDRESS_DEPTH_OSERDES = BANK_ADDRESS_DEPTH + LOG2_OF_BUS_WIDTH + LOG2_OF_TRANSACTIONS_PER_DATA_WORD - LOG2_OF_OSERDES_DATA_WIDTH,
parameter ADDRESS_AUTOINCREMENT_MODE = 1,
parameter TESTBENCH = 0,
parameter WRITE_STROBE_PICKOFF = 17,
parameter COUNTER100_BIT_PICKOFF = TESTBENCH ? 5 : 23,
parameter COUNTERWORD_BIT_PICKOFF = TESTBENCH ? 5 : 23
) (
input clock100_p, clock100_n,
input clock10,
input reset,
inout [5:0] coax,
input [2:0] rot,
inout [BUS_WIDTH-1:0] bus,
input read,
input register_select,
input enable,
output ack_valid,
output [11:0] diff_pair_left,
output [11:0] diff_pair_right,
inout [5:0] single_ended_left,
inout [5:0] single_ended_right,
output [3:0] coax_led,
output [7:0] led
); |
localparam ERROR_COUNT_PICKOFF = 7;
wire [3:0] status4;
wire [7:0] status8;
genvar i;
wire pll_oserdes_locked;
wire pll_oserdes_locked_2;
for (i=0; i<12; i=i+1) begin : diff_pair_array
assign diff_pair_left[i] = 0;
assign diff_pair_right[i] = 0;
end
assign single_ended_left[5:2] = 0;
assign single_ended_left[0] = 0;
assign single_ended_right[5:4] = 0;
assign single_ended_right[1:0] = 0;
wire reset100;
wire clock100;
IBUFGDS mybuf0 (.I(clock100_p), .IB(clock100_n), .O(clock100));
wire word_clock0;
wire word_clock1;
wire clock = word_clock0;
reset_wait4pll #(.COUNTER_BIT_PICKOFF(COUNTER100_BIT_PICKOFF)) reset100_wait4pll (.reset_input(reset), .pll_locked_input(1'b1), .clock_input(clock100), .reset_output(reset100));
wire reset_word0;
wire reset_word1;
reset_wait4pll #(.COUNTER_BIT_PICKOFF(COUNTERWORD_BIT_PICKOFF)) resetword_wait4pll (.reset_input(reset100), .pll_locked_input(pll_oserdes_locked), .clock_input(word_clock0), .reset_output(reset_word0));
reset_wait4pll #(.COUNTER_BIT_PICKOFF(COUNTERWORD_BIT_PICKOFF)) resetword1_wait4pll (.reset_input(reset100), .pll_locked_input(pll_oserdes_locked), .clock_input(word_clock1), .reset_output(reset_word1));
wire [BUS_WIDTH*TRANSACTIONS_PER_ADDRESS_WORD-1:0] address_word_full;
wire [BANK_ADDRESS_DEPTH-1:0] address_word_narrow = address_word_full[BANK_ADDRESS_DEPTH-1:0];
wire [BUS_WIDTH*TRANSACTIONS_PER_DATA_WORD-1:0] write_data_word;
wire [BUS_WIDTH*TRANSACTIONS_PER_DATA_WORD-1:0] read_data_word [NUMBER_OF_BANKS-1:0];
wire [LOG2_OF_NUMBER_OF_BANKS-1:0] bank;
wire [LOG2_OF_NUMBER_OF_BANKS-1:0] write_strobe;
wire [ERROR_COUNT_PICKOFF:0] hdrb_read_errors;
wire [ERROR_COUNT_PICKOFF:0] hdrb_write_errors;
wire [ERROR_COUNT_PICKOFF:0] hdrb_address_errors;
half_duplex_rpi_bus #(
.BUS_WIDTH(BUS_WIDTH),
.TRANSACTIONS_PER_DATA_WORD(TRANSACTIONS_PER_DATA_WORD),
.TRANSACTIONS_PER_ADDRESS_WORD(TRANSACTIONS_PER_ADDRESS_WORD),
.BANK_ADDRESS_DEPTH(BANK_ADDRESS_DEPTH),
.ADDRESS_AUTOINCREMENT_MODE(ADDRESS_AUTOINCREMENT_MODE)
) hdrb (
.clock(word_clock0),
.reset(reset_word0),
.bus(bus),
.read(read),
.register_select(register_select),
.enable(enable),
.ack_valid(ack_valid),
.write_strobe(write_strobe),
.write_data_word(write_data_word),
.read_data_word(read_data_word[bank]),
.address_word_reg(address_word_full),
.read_errors(hdrb_read_errors),
.write_errors(hdrb_write_errors),
.address_errors(hdrb_address_errors),
.bank(bank)
);
wire [OSERDES_DATA_WIDTH-1:0] potential_oserdes_word [NUMBER_OF_BANKS-1:0];
wire [OSERDES_DATA_WIDTH-1:0] oserdes_word [NUMBER_OF_BANKS-1:0];
wire [7:0] oserdes_word_delayed;
wire [7:0] oserdes_word1_buffer;
wire [7:0] oserdes_word1_buffer_delayed;
wire [7:0] iserdes_word;
wire [7:0] iserdes_word_buffer;
wire [7:0] iserdes_word_buffer0;
wire [7:0] iserdes_word_buffer_delayed;
wire [ADDRESS_DEPTH_OSERDES-1:0] read_address;
wire [31:0] bank1 [15:0];
wire [31:0] bank2 [15:0];
reg [WRITE_STROBE_PICKOFF:0] counter = 0;
reg write_strobe_b = 0;
always @(posedge word_clock0) begin
write_strobe_b <= 0;
if (reset_word0) begin
counter <= 0;
end else begin
if (counter[WRITE_STROBE_PICKOFF:0]==0) begin
write_strobe_b <= 1;
end
counter <= counter + 1'b1;
end
end
if (0) begin
if (BANK_ADDRESS_DEPTH==12) begin
RAM_s6_4k_32bit_8bit #(.ENDIANNESS("BIG")) mem0 (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[0]), .data_out_a(read_data_word[0]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[0]));
RAM_s6_4k_32bit_8bit #(.ENDIANNESS("BIG")) mem1 (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[1]), .data_out_a(read_data_word[1]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[1]));
RAM_s6_4k_32bit_8bit #(.ENDIANNESS("BIG")) mem2 (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[2]), .data_out_a(read_data_word[2]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[2]));
RAM_s6_4k_32bit_8bit #(.ENDIANNESS("BIG")) mem3 (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[3]), .data_out_a(read_data_word[3]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[3]));
end else if (BANK_ADDRESS_DEPTH==13) begin
RAM_s6_8k_32bit_8bit #(.ENDIANNESS("BIG")) mem0 (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[0]), .data_out_a(read_data_word[0]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[0]));
RAM_s6_8k_32bit_8bit #(.ENDIANNESS("BIG")) mem1 (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[1]), .data_out_a(read_data_word[1]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[1]));
end else begin
RAM_s6_16k_32bit_8bit #(.ENDIANNESS("BIG")) mem (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[0]), .data_out_a(read_data_word[0]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[0]));
end
end else begin
for (i=3; i<NUMBER_OF_BANKS; i=i+1) begin : fakebanks
assign read_data_word[i] = 0;
end
for (i=1; i<NUMBER_OF_BANKS; i=i+1) begin : banksfake
assign potential_oserdes_word[i] = 0;
end
RAM_s6_4k_32bit_8bit #(.ENDIANNESS("BIG")) mem_bank0 (.reset(reset_word0),
.clock_a(word_clock0), .address_a(address_word_narrow), .data_in_a(write_data_word), .write_enable_a(write_strobe[0]), .data_out_a(read_data_word[0]),
.clock_b(word_clock0), .address_b(read_address), .data_out_b(potential_oserdes_word[0]));
RAM_inferred_with_register_inputs #(.ADDR_WIDTH(4), .DATA_WIDTH(32)) riwri_bank1 (.clock(word_clock0), .reset(reset_word0),
.raddress_a(address_word_full[3:0]), .data_out_a(read_data_word[1]),
.data_in_b_0(bank1[0]), .data_in_b_1(bank1[1]), .data_in_b_2(bank1[2]), .data_in_b_3(bank1[3]),
.data_in_b_4(bank1[4]), .data_in_b_5(bank1[5]), .data_in_b_6(bank1[6]), .data_in_b_7(bank1[7]),
.data_in_b_8(bank1[8]), .data_in_b_9(bank1[9]), .data_in_b_a(bank1[10]), .data_in_b_b(bank1[11]),
.data_in_b_c(bank1[12]), .data_in_b_d(bank1[13]), .data_in_b_e(bank1[14]), .data_in_b_f(bank1[15]),
.write_strobe_b(write_strobe_b));
RAM_inferred_with_register_outputs #(.ADDR_WIDTH(4), .DATA_WIDTH(32)) riwro_bank2 (.clock(word_clock0), .reset(reset_word0),
.waddress_a(address_word_full[3:0]), .data_in_a(write_data_word), .write_strobe_a(write_strobe[2]),
.raddress_a(address_word_full[3:0]), .data_out_a(read_data_word[2]),
.data_out_b_0(bank2[0]), .data_out_b_1(bank2[1]), .data_out_b_2(bank2[2]), .data_out_b_3(bank2[3]),
.data_out_b_4(bank2[4]), .data_out_b_5(bank2[5]), .data_out_b_6(bank2[6]), .data_out_b_7(bank2[7]),
.data_out_b_8(bank2[8]), .data_out_b_9(bank2[9]), .data_out_b_a(bank2[10]), .data_out_b_b(bank2[11]),
.data_out_b_c(bank2[12]), .data_out_b_d(bank2[13]), .data_out_b_e(bank2[14]), .data_out_b_f(bank2[15]));
end
wire [2:0] rot_pipeline;
localparam LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE = 24;
localparam PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + LOG2_OF_OSERDES_DATA_WIDTH - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE;
localparam LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO < 0 ? 0 : PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO;
localparam PADDING = 24 - LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE;
wire [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count [3:0];
wire [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] pipelined_count [3:0];
reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] previous_count [3:0];
wire [OSERDES_DATA_WIDTH-1:0] result [3:0];
wire [OSERDES_DATA_WIDTH-1:0] pipelined_result [3:0];
reg [OSERDES_DATA_WIDTH-1:0] previous_result [3:0];
wire [LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO-1:0] capture_completion;
wire partial_count_reached;
wire max_count_reached;
wire adding_finished;
wire result_valid;
assign coax[1] = partial_count_reached;
assign coax[2] = adding_finished;
assign coax[3] = result_valid;
wire [3:0] histogram_status4 = { result_valid, adding_finished, max_count_reached, partial_count_reached };
wire [31:0] histogram_error_count;
assign bank1[0] = { oserdes_word[3], oserdes_word[2], oserdes_word[1], oserdes_word[0] };
assign bank1[1] = { oserdes_word_delayed, 8'd0, oserdes_word1_buffer, oserdes_word1_buffer_delayed };
assign bank1[2] = { iserdes_word, 8'd0, iserdes_word_buffer, iserdes_word_buffer_delayed };
assign bank1[3] = hdrb_read_errors;
assign bank1[4] = hdrb_write_errors;
assign bank1[5] = hdrb_address_errors;
assign bank1[6] = { capture_completion, histogram_status4, rot_pipeline, status4, status8 };
assign bank1[7] = histogram_error_count;
assign bank1[8] = { {PADDING{1'b0}}, previous_count[0], previous_result[0] };
assign bank1[9] = { {PADDING{1'b0}}, previous_count[1], previous_result[1] };
assign bank1[10] = { {PADDING{1'b0}}, previous_count[2], previous_result[2] };
assign bank1[11] = { {PADDING{1'b0}}, previous_count[3], previous_result[3] };
assign bank1[12] = { {PADDING{1'b0}}, count[0], result[0] };
assign bank1[13] = { {PADDING{1'b0}}, count[1], result[1] };
assign bank1[14] = { {PADDING{1'b0}}, count[2], result[2] };
assign bank1[15] = { {PADDING{1'b0}}, count[3], result[3] };
wire [2:0] bitslip_iserdes = bank2[0][2:0];
wire [2:0] bitslip_oserdes1 = bank2[1][2:0];
(* KEEP = "TRUE" *)
wire [1:0] word_clock_sel = bank2[3][1:0];
wire train_oserdes = bank2[4][0];
wire [7:0] train_oserdes_pattern = bank2[5][7:0];
wire [31:0] start_sample = bank2[6][31:0];
wire [31:0] end_sample = bank2[7][31:0];
wire enable_histogram_sampling = bank2[8][0];
wire clear_histogram_results = bank2[8][1];
pipeline #(.WIDTH(8), .DEPTH(3)) kings (.clock(word_clock0), .in(iserdes_word_buffer), .out(iserdes_word_buffer0));
localparam RESULT_VALID_PIPELINE_PICKOFF = 1;
reg [RESULT_VALID_PIPELINE_PICKOFF:0] result_valid_pipeline = 0;
pipeline #(.WIDTH(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) kongs0 (.clock(word_clock0), .in(count[0]), .out(pipelined_count[0]));
pipeline #(.WIDTH(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) kongs1 (.clock(word_clock0), .in(count[1]), .out(pipelined_count[1]));
pipeline #(.WIDTH(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) kongs2 (.clock(word_clock0), .in(count[2]), .out(pipelined_count[2]));
pipeline #(.WIDTH(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) kongs3 (.clock(word_clock0), .in(count[3]), .out(pipelined_count[3]));
pipeline #(.WIDTH(OSERDES_DATA_WIDTH), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) mothra0 (.clock(word_clock0), .in(result[0]), .out(pipelined_result[0]));
pipeline #(.WIDTH(OSERDES_DATA_WIDTH), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) mothra1 (.clock(word_clock0), .in(result[1]), .out(pipelined_result[1]));
pipeline #(.WIDTH(OSERDES_DATA_WIDTH), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) mothra2 (.clock(word_clock0), .in(result[2]), .out(pipelined_result[2]));
pipeline #(.WIDTH(OSERDES_DATA_WIDTH), .DEPTH(RESULT_VALID_PIPELINE_PICKOFF+1)) mothra3 (.clock(word_clock0), .in(result[3]), .out(pipelined_result[3]));
for (i=0; i<4; i=i+1) begin : previous_histogram
always @(posedge word_clock0) begin
if (reset_word0) begin
previous_count[i] <= 0;
previous_result[i] <= 0;
end else begin
if (result_valid_pipeline[RESULT_VALID_PIPELINE_PICKOFF -: 2]==2'b10) begin
previous_count[i] <= pipelined_count[i];
previous_result[i] <= pipelined_result[i];
end
end
end
end
always @(posedge word_clock0) begin
if (reset_word0) begin
result_valid_pipeline <= 0;
end else begin
result_valid_pipeline <= { result_valid_pipeline[RESULT_VALID_PIPELINE_PICKOFF-1:0], result_valid };
end
end
histogram #(.DATA_WIDTH(OSERDES_DATA_WIDTH), .LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE), .USE_BLOCK_MEMORY(1)) h1n1 (
.clock(word_clock0), .reset(reset_word0), .clear_results(clear_histogram_results), .data_in(iserdes_word_buffer0), .sample(enable_histogram_sampling),
.result00(result[0]), .result01(result[1]), .result02(result[2]), .result03(result[3]),
.count00(count[0]), .count01(count[1]), .count02(count[2]), .count03(count[3]),
.capture_completion(capture_completion), .partial_count_reached(partial_count_reached), .max_count_reached(max_count_reached),
.adding_finished(adding_finished), .result_valid(result_valid), .error_count(histogram_error_count));
for (i=0; i<NUMBER_OF_BANKS; i=i+1) begin : train_or_regular
assign oserdes_word[i] = train_oserdes ? train_oserdes_pattern : potential_oserdes_word[i];
end
wire sync_read_address;
wire [3:0] sync_out_stream;
wire [7:0] sync_out_word;
wire [7:0] sync_out_word_delayed;
sequencer_sync #(.ADDRESS_DEPTH_OSERDES(ADDRESS_DEPTH_OSERDES), .LOG2_OF_OSERDES_DATA_WIDTH(LOG2_OF_OSERDES_DATA_WIDTH)) ss (.clock(word_clock0), .reset(reset_word0), .sync_read_address(sync_read_address), .start_sample(start_sample), .end_sample(end_sample), .read_address(read_address), .sync_out_stream(sync_out_stream), .sync_out_word(sync_out_word));
cdc_pipeline #(.WIDTH(3), .DEPTH(3)) tongs (.clock(word_clock0), .in(~rot), .out(rot_pipeline));
cdc_pipeline #(.WIDTH(8), .DEPTH(3)) publics (.clock(word_clock1), .in(iserdes_word), .out(iserdes_word_buffer));
bitslip #(.WIDTH(8)) bsi (.clock(word_clock1), .bitslip(bitslip_iserdes), .data_in(iserdes_word_buffer), .data_out(iserdes_word_buffer_delayed));
localparam DELAY = 7;
pipeline #(.WIDTH(8), .DEPTH(DELAY+4)) queens (.clock(word_clock0), .in(oserdes_word[0]), .out(oserdes_word_delayed));
pipeline #(.WIDTH(8), .DEPTH(DELAY+4)) diamond_head (.clock(word_clock0), .in(sync_out_word), .out(sync_out_word_delayed));
bitslip #(.WIDTH(8)) bso1 (.clock(word_clock1), .bitslip(bitslip_oserdes1), .data_in(oserdes_word[0]), .data_out(oserdes_word1_buffer));
pipeline #(.WIDTH(8), .DEPTH(DELAY)) kewalos (.clock(word_clock1), .in(oserdes_word1_buffer), .out(oserdes_word1_buffer_delayed));
wire pre_coax_4;
ocyrus_hex8_split_4_2 #(.BIT_DEPTH(8), .PERIOD(10.0), .MULTIPLY(10), .DIVIDE(1), .SCOPE("BUFPLL"), .PHASE45(0.0)) mylei6 (
.clock_in(clock100), .reset(reset100), .word_clock0123_out(word_clock1), .locked(pll_oserdes_locked),
.word_clock45_sel(word_clock_sel[1:0]), .word_clock45_out(word_clock0),
.word0_in(oserdes_word1_buffer_delayed), .word1_in(oserdes_word1_buffer), .word2_in(oserdes_word1_buffer), .word3_in(iserdes_word_buffer_delayed),
.word4_in(oserdes_word_delayed), .word5_in(sync_out_word_delayed),
.D0_out(pre_coax_4), .D1_out(single_ended_left[1]), .D2_out(single_ended_right[2]), .D3_out(coax[5]),
.D4_out(coax[0]), .D5_out(),
.iserdes_bit_input(single_ended_right[3]), .iserdes_word_out(iserdes_word));
assign coax[4] = pre_coax_4;
if (0) begin
assign coax[4] = enable;
assign coax[5] = write_strobe[0];
assign pll_oserdes_locked_2 = 1;
end else if (0) begin
ocyrus_double8 #(.BIT_DEPTH(8), .PERIOD(10.0), .MULTIPLY(10), .DIVIDE(1), .SCOPE("BUFPLL")) mylei2 (
.clock_in(clock100), .reset(reset100), .word_clock_out(),
.word1_in(oserdes_word[0]), .D1_out(coax[5]),
.word0_in(oserdes_word[0]), .D0_out(coax[4]),
.bit_clock(), .bit_strobe(),
.locked(pll_oserdes_locked_2));
assign sync_read_address = 0;
end else if (0) begin
ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(10.0), .MULTIPLY(10), .DIVIDE(1), .SCOPE("BUFPLL")) mylei (.clock_in(clock100), .reset(reset100), .word_clock_out(), .word_in(oserdes_word[0]), .D_out(coax[5]), .locked(pll_oserdes_locked_2));
assign coax[4] = sync_out_stream[2];
assign sync_read_address = 0;
end else if (1) begin
assign sync_read_address = 0;
assign pll_oserdes_locked_2 = 1;
end else begin
assign coax[4] = sync_out_stream[2];
assign sync_read_address = coax[5];
assign pll_oserdes_locked_2 = 1;
end
assign status4[3:0] = bank;
assign status8[7] = reset100;
assign status8[6] = ~pll_oserdes_locked;
assign status8[5] = reset_word0;
assign status8[4] = reset_word1;
assign status8[3] = ack_valid;
assign status8[2] = read;
assign status8[1] = enable;
assign status8[0] = register_select;
if (1) begin
cdc_pipeline #(.WIDTH(8), .DEPTH(2)) blinx (.clock(clock100), .in(status8), .out(led));
end
if (1) begin
cdc_pipeline #(.WIDTH(4), .DEPTH(2)) jarjar (.clock(clock100), .in(status4), .out(coax_led));
end
initial begin
#100;
$display("%d = %d + %d + %d - %d", ADDRESS_DEPTH_OSERDES, BANK_ADDRESS_DEPTH, LOG2_OF_BUS_WIDTH, LOG2_OF_TRANSACTIONS_PER_DATA_WORD, LOG2_OF_OSERDES_DATA_WIDTH);
$display("BUS_WIDTH=%d, TRANSACTIONS_PER_DATA_WORD=%d, TRANSACTIONS_PER_ADDRESS_WORD=%d", BUS_WIDTH, TRANSACTIONS_PER_DATA_WORD, TRANSACTIONS_PER_ADDRESS_WORD);
$display("%d banks", NUMBER_OF_BANKS);
end
endmodule | 2 |
5,985 | data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v | 115,035,459 | mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v | v | 743 | 357 | [] | [] | [] | null | line:304: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:6: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:7: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:9: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:10: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:11: Cannot find include file: lib/half_duplex_rpi_bus.v\n`include "lib/half_duplex_rpi_bus.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:12: Cannot find include file: lib/sequencer.v\n`include "lib/sequencer.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:13: Cannot find include file: lib/reset.v\n`include "lib/reset.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:14: Cannot find include file: lib/histogram.v\n`include "lib/histogram.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:15: Cannot find include file: lib/fifo.v\n`include "lib/fifo.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:198: Define or directive not defined: \'`LOG2_OF_BASE_BLOCK_MEMORY_SIZE\'\n localparam PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + LOG2_OF_OSERDES_DATA_WIDTH - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:198: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + LOG2_OF_OSERDES_DATA_WIDTH - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:372: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:428: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:437: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:467: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:572: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:572: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:573: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:574: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:659: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:659: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:660: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:669: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:674: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Error: Exiting due to 11 error(s), 13 warning(s)\n' | 6,800 | module | module top_tb;
localparam HALF_PERIOD_OF_CONTROLLER = 1;
localparam HALF_PERIOD_OF_PERIPHERAL = 10;
localparam NUMBER_OF_PERIODS_OF_CONTROLLER_IN_A_DELAY = 1;
localparam NUMBER_OF_PERIODS_OF_CONTROLLER_WHILE_WAITING_FOR_ACK = 2000;
reg clock = 0;
localparam BUS_WIDTH = 16;
localparam BANK_ADDRESS_DEPTH = 14;
localparam TRANSACTIONS_PER_DATA_WORD = 2;
localparam TRANSACTIONS_PER_ADDRESS_WORD = 1;
localparam ADDRESS_AUTOINCREMENT_MODE = 1;
reg clock100_p = 0;
reg clock100_n = 1;
reg clock10 = 0;
reg reset = 0;
wire [5:0] coax;
wire [3:0] coax_led;
wire [7:0] led;
reg pre_register_select = 0;
reg register_select = 0;
reg pre_read = 0;
reg read = 0;
reg [BUS_WIDTH-1:0] pre_bus = 0;
wire [BUS_WIDTH-1:0] bus;
reg [BUS_WIDTH-1:0] eye_center = 0;
reg pre_enable = 0;
reg enable = 0;
wire a_n, a_p, c_n, c_p, d_n, d_p, f_n, f_p, b_n, b_p, e_n, e_p;
wire m_p, m_n, l_p, l_n, j_p, j_n, g_p, g_n, k_p, k_n, h_p, h_n;
wire z, y, x, w, v, u;
wire n, p, q, r, s, t;
reg [TRANSACTIONS_PER_DATA_WORD*BUS_WIDTH-1:0] wdata = 0;
reg [TRANSACTIONS_PER_DATA_WORD*BUS_WIDTH-1:0] rdata = 0;
bus_entry_3state #(.WIDTH(BUS_WIDTH)) my3sbe (.I(pre_bus), .O(bus), .T(~read));
top #(.BUS_WIDTH(BUS_WIDTH), .BANK_ADDRESS_DEPTH(BANK_ADDRESS_DEPTH), .TRANSACTIONS_PER_DATA_WORD(TRANSACTIONS_PER_DATA_WORD), .TRANSACTIONS_PER_ADDRESS_WORD(TRANSACTIONS_PER_ADDRESS_WORD), .ADDRESS_AUTOINCREMENT_MODE(ADDRESS_AUTOINCREMENT_MODE), .TESTBENCH(1)) althea (
.clock100_p(clock100_p), .clock100_n(clock100_n), .clock10(clock10), .reset(reset),
.coax(coax),
.diff_pair_left({ a_n, a_p, c_n, c_p, d_n, d_p, f_n, f_p, b_n, b_p, e_n, e_p }),
.diff_pair_right({ m_p, m_n, l_p, l_n, j_p, j_n, g_p, g_n, k_p, k_n, h_p, h_n }),
.single_ended_left({ z, y, x, w, v, u }),
.single_ended_right({ n, p, q, r, s, t }),
.bus(bus), .register_select(register_select), .read(read), .enable(enable), .ack_valid(ack_valid),
.led(led), .coax_led(coax_led)
);
task automatic peripheral_clock_delay;
input integer number_of_cycles;
integer j;
begin
for (j=0; j<2*number_of_cycles; j=j+1) begin : delay_thing_s
#HALF_PERIOD_OF_PERIPHERAL;
end
end
endtask
task automatic controller_clock_delay;
input integer number_of_cycles;
integer j;
begin
for (j=0; j<2*number_of_cycles; j=j+1) begin : delay_thing_m
#HALF_PERIOD_OF_CONTROLLER;
end
end
endtask
task automatic delay;
controller_clock_delay(NUMBER_OF_PERIODS_OF_CONTROLLER_IN_A_DELAY);
endtask
task automatic pulse_enable;
integer i;
integer j;
begin
i = 0;
pre_enable <= 1;
for (j=0; j<2*NUMBER_OF_PERIODS_OF_CONTROLLER_WHILE_WAITING_FOR_ACK; j=j+1) begin : delay_thing_1
if (ack_valid) begin
if (2==i) begin
eye_center <= bus;
end
i = i + 1;
j = 2*NUMBER_OF_PERIODS_OF_CONTROLLER_WHILE_WAITING_FOR_ACK - 100;
end
if (64<i) begin
pre_enable <= 0;
end
#HALF_PERIOD_OF_CONTROLLER;
end
if (pre_enable==1) begin
$finish;
end
end
endtask
task automatic a16_d32_controller_write_transaction;
input [15:0] address16;
input [31:0] data32;
begin
controller_set_address16(address16);
controller_write_data32(data32);
end
endtask
task automatic a16_controller_read_transaction;
input [15:0] address16;
integer j;
begin
controller_set_address16(address16);
end
endtask
task automatic controller_set_address16;
input [15:0] address16;
integer j;
begin
delay();
pre_read <= 0;
pre_register_select <= 0;
pre_bus <= address16[BUS_WIDTH-1:0];
pulse_enable();
delay();
$display("%t address: %04x", $time, address16);
end
endtask
task automatic controller_write_data32;
input [31:0] data32;
integer j;
begin
delay();
pre_read <= 0;
pre_register_select <= 1;
if (3<TRANSACTIONS_PER_DATA_WORD) begin
pre_bus <= data32[4*BUS_WIDTH-1:3*BUS_WIDTH];
pulse_enable();
wdata[4*BUS_WIDTH-1:3*BUS_WIDTH] <= eye_center;
end
if (2<TRANSACTIONS_PER_DATA_WORD) begin
pre_bus <= data32[3*BUS_WIDTH-1:2*BUS_WIDTH];
pulse_enable();
wdata[3*BUS_WIDTH-1:2*BUS_WIDTH] <= eye_center;
end
if (1<TRANSACTIONS_PER_DATA_WORD) begin
pre_bus <= data32[2*BUS_WIDTH-1:BUS_WIDTH];
pulse_enable();
wdata[2*BUS_WIDTH-1:BUS_WIDTH] <= eye_center;
end
pre_bus <= data32[BUS_WIDTH-1:0];
pulse_enable();
wdata[BUS_WIDTH-1:0] <= eye_center;
delay();
$display("%t wdata: %08x", $time, wdata);
end
endtask
task automatic controller_read_data32;
integer j;
begin
delay();
pre_read <= 1;
pre_register_select <= 1;
for (j=TRANSACTIONS_PER_DATA_WORD-1; j>=0; j=j-1) begin : read_data_multiple_2
pulse_enable();
if (3==j) begin
rdata[4*BUS_WIDTH-1:3*BUS_WIDTH] <= eye_center;
end else if (2==j) begin
rdata[3*BUS_WIDTH-1:2*BUS_WIDTH] <= eye_center;
end else if (1==j) begin
rdata[2*BUS_WIDTH-1:BUS_WIDTH] <= eye_center;
end else begin
rdata[BUS_WIDTH-1:0] <= eye_center;
end
end
delay();
$display("%t rdata: %08x", $time, rdata);
end
endtask
initial begin
#300; reset <= 1; #300; reset <= 0;
#512;
#512;
if (ADDRESS_AUTOINCREMENT_MODE) begin
controller_clock_delay(64);
peripheral_clock_delay(64);
controller_set_address16(16'h_2b4c);
controller_write_data32(32'h_3123_1507);
controller_write_data32(32'h_3123_1508);
controller_write_data32(32'h_3123_1509);
controller_write_data32(32'h_3123_150a);
controller_clock_delay(64);
peripheral_clock_delay(64);
controller_set_address16(16'h_2b4c);
controller_read_data32();
controller_read_data32();
controller_read_data32();
controller_read_data32();
end else begin
controller_clock_delay(64);
peripheral_clock_delay(64);
a16_d32_controller_write_transaction(.address16(16'h2b4c), .data32(32'h3123_1507));
controller_read_data32();
a16_d32_controller_write_transaction(.address16(16'h2b4d), .data32(32'h3123_1508));
controller_read_data32();
a16_d32_controller_write_transaction(.address16(16'h2b4e), .data32(32'h3123_1509));
controller_read_data32();
a16_d32_controller_write_transaction(.address16(16'h2b4f), .data32(32'h3123_150a));
controller_read_data32();
controller_clock_delay(64);
peripheral_clock_delay(64);
a16_controller_read_transaction(.address16(16'h2b4c));
a16_controller_read_transaction(.address16(16'h2b4d));
a16_controller_read_transaction(.address16(16'h2b4e));
a16_controller_read_transaction(.address16(16'h2b4f));
end
controller_clock_delay(64);
peripheral_clock_delay(64);
pre_register_select <= 1;
pre_read <= 1;
pre_bus <= 8'h33;
pulse_enable();
controller_set_address16(16'h1b4f);
controller_read_data32();
controller_clock_delay(64);
peripheral_clock_delay(64);
pre_register_select <= 1;
pre_read <= 0;
pre_bus <= 8'h66;
pulse_enable();
controller_set_address16(16'h4f1b);
controller_write_data32(32'h3123_2d78);
controller_clock_delay(64);
peripheral_clock_delay(64);
pre_register_select <= 0;
pre_read <= 0;
pre_bus <= 8'h99;
pulse_enable();
controller_set_address16(16'h1b4f);
controller_read_data32();
pre_register_select <= 0;
pre_read <= 0;
pre_enable <= 0;
controller_clock_delay(64);
peripheral_clock_delay(64);
#300; reset <= 1; #300; reset <= 0;
#300;
end
always @(posedge clock) begin
register_select <= #1 pre_register_select;
read <= #1 pre_read;
enable <= #1 pre_enable;
end
always begin
#HALF_PERIOD_OF_PERIPHERAL;
clock100_p <= #1.5 ~clock100_p;
clock100_n <= #2.5 ~clock100_n;
end
always begin
#HALF_PERIOD_OF_CONTROLLER;
clock <= #0.625 ~clock;
end
endmodule | module top_tb; |
localparam HALF_PERIOD_OF_CONTROLLER = 1;
localparam HALF_PERIOD_OF_PERIPHERAL = 10;
localparam NUMBER_OF_PERIODS_OF_CONTROLLER_IN_A_DELAY = 1;
localparam NUMBER_OF_PERIODS_OF_CONTROLLER_WHILE_WAITING_FOR_ACK = 2000;
reg clock = 0;
localparam BUS_WIDTH = 16;
localparam BANK_ADDRESS_DEPTH = 14;
localparam TRANSACTIONS_PER_DATA_WORD = 2;
localparam TRANSACTIONS_PER_ADDRESS_WORD = 1;
localparam ADDRESS_AUTOINCREMENT_MODE = 1;
reg clock100_p = 0;
reg clock100_n = 1;
reg clock10 = 0;
reg reset = 0;
wire [5:0] coax;
wire [3:0] coax_led;
wire [7:0] led;
reg pre_register_select = 0;
reg register_select = 0;
reg pre_read = 0;
reg read = 0;
reg [BUS_WIDTH-1:0] pre_bus = 0;
wire [BUS_WIDTH-1:0] bus;
reg [BUS_WIDTH-1:0] eye_center = 0;
reg pre_enable = 0;
reg enable = 0;
wire a_n, a_p, c_n, c_p, d_n, d_p, f_n, f_p, b_n, b_p, e_n, e_p;
wire m_p, m_n, l_p, l_n, j_p, j_n, g_p, g_n, k_p, k_n, h_p, h_n;
wire z, y, x, w, v, u;
wire n, p, q, r, s, t;
reg [TRANSACTIONS_PER_DATA_WORD*BUS_WIDTH-1:0] wdata = 0;
reg [TRANSACTIONS_PER_DATA_WORD*BUS_WIDTH-1:0] rdata = 0;
bus_entry_3state #(.WIDTH(BUS_WIDTH)) my3sbe (.I(pre_bus), .O(bus), .T(~read));
top #(.BUS_WIDTH(BUS_WIDTH), .BANK_ADDRESS_DEPTH(BANK_ADDRESS_DEPTH), .TRANSACTIONS_PER_DATA_WORD(TRANSACTIONS_PER_DATA_WORD), .TRANSACTIONS_PER_ADDRESS_WORD(TRANSACTIONS_PER_ADDRESS_WORD), .ADDRESS_AUTOINCREMENT_MODE(ADDRESS_AUTOINCREMENT_MODE), .TESTBENCH(1)) althea (
.clock100_p(clock100_p), .clock100_n(clock100_n), .clock10(clock10), .reset(reset),
.coax(coax),
.diff_pair_left({ a_n, a_p, c_n, c_p, d_n, d_p, f_n, f_p, b_n, b_p, e_n, e_p }),
.diff_pair_right({ m_p, m_n, l_p, l_n, j_p, j_n, g_p, g_n, k_p, k_n, h_p, h_n }),
.single_ended_left({ z, y, x, w, v, u }),
.single_ended_right({ n, p, q, r, s, t }),
.bus(bus), .register_select(register_select), .read(read), .enable(enable), .ack_valid(ack_valid),
.led(led), .coax_led(coax_led)
);
task automatic peripheral_clock_delay;
input integer number_of_cycles;
integer j;
begin
for (j=0; j<2*number_of_cycles; j=j+1) begin : delay_thing_s
#HALF_PERIOD_OF_PERIPHERAL;
end
end
endtask
task automatic controller_clock_delay;
input integer number_of_cycles;
integer j;
begin
for (j=0; j<2*number_of_cycles; j=j+1) begin : delay_thing_m
#HALF_PERIOD_OF_CONTROLLER;
end
end
endtask
task automatic delay;
controller_clock_delay(NUMBER_OF_PERIODS_OF_CONTROLLER_IN_A_DELAY);
endtask
task automatic pulse_enable;
integer i;
integer j;
begin
i = 0;
pre_enable <= 1;
for (j=0; j<2*NUMBER_OF_PERIODS_OF_CONTROLLER_WHILE_WAITING_FOR_ACK; j=j+1) begin : delay_thing_1
if (ack_valid) begin
if (2==i) begin
eye_center <= bus;
end
i = i + 1;
j = 2*NUMBER_OF_PERIODS_OF_CONTROLLER_WHILE_WAITING_FOR_ACK - 100;
end
if (64<i) begin
pre_enable <= 0;
end
#HALF_PERIOD_OF_CONTROLLER;
end
if (pre_enable==1) begin
$finish;
end
end
endtask
task automatic a16_d32_controller_write_transaction;
input [15:0] address16;
input [31:0] data32;
begin
controller_set_address16(address16);
controller_write_data32(data32);
end
endtask
task automatic a16_controller_read_transaction;
input [15:0] address16;
integer j;
begin
controller_set_address16(address16);
end
endtask
task automatic controller_set_address16;
input [15:0] address16;
integer j;
begin
delay();
pre_read <= 0;
pre_register_select <= 0;
pre_bus <= address16[BUS_WIDTH-1:0];
pulse_enable();
delay();
$display("%t address: %04x", $time, address16);
end
endtask
task automatic controller_write_data32;
input [31:0] data32;
integer j;
begin
delay();
pre_read <= 0;
pre_register_select <= 1;
if (3<TRANSACTIONS_PER_DATA_WORD) begin
pre_bus <= data32[4*BUS_WIDTH-1:3*BUS_WIDTH];
pulse_enable();
wdata[4*BUS_WIDTH-1:3*BUS_WIDTH] <= eye_center;
end
if (2<TRANSACTIONS_PER_DATA_WORD) begin
pre_bus <= data32[3*BUS_WIDTH-1:2*BUS_WIDTH];
pulse_enable();
wdata[3*BUS_WIDTH-1:2*BUS_WIDTH] <= eye_center;
end
if (1<TRANSACTIONS_PER_DATA_WORD) begin
pre_bus <= data32[2*BUS_WIDTH-1:BUS_WIDTH];
pulse_enable();
wdata[2*BUS_WIDTH-1:BUS_WIDTH] <= eye_center;
end
pre_bus <= data32[BUS_WIDTH-1:0];
pulse_enable();
wdata[BUS_WIDTH-1:0] <= eye_center;
delay();
$display("%t wdata: %08x", $time, wdata);
end
endtask
task automatic controller_read_data32;
integer j;
begin
delay();
pre_read <= 1;
pre_register_select <= 1;
for (j=TRANSACTIONS_PER_DATA_WORD-1; j>=0; j=j-1) begin : read_data_multiple_2
pulse_enable();
if (3==j) begin
rdata[4*BUS_WIDTH-1:3*BUS_WIDTH] <= eye_center;
end else if (2==j) begin
rdata[3*BUS_WIDTH-1:2*BUS_WIDTH] <= eye_center;
end else if (1==j) begin
rdata[2*BUS_WIDTH-1:BUS_WIDTH] <= eye_center;
end else begin
rdata[BUS_WIDTH-1:0] <= eye_center;
end
end
delay();
$display("%t rdata: %08x", $time, rdata);
end
endtask
initial begin
#300; reset <= 1; #300; reset <= 0;
#512;
#512;
if (ADDRESS_AUTOINCREMENT_MODE) begin
controller_clock_delay(64);
peripheral_clock_delay(64);
controller_set_address16(16'h_2b4c);
controller_write_data32(32'h_3123_1507);
controller_write_data32(32'h_3123_1508);
controller_write_data32(32'h_3123_1509);
controller_write_data32(32'h_3123_150a);
controller_clock_delay(64);
peripheral_clock_delay(64);
controller_set_address16(16'h_2b4c);
controller_read_data32();
controller_read_data32();
controller_read_data32();
controller_read_data32();
end else begin
controller_clock_delay(64);
peripheral_clock_delay(64);
a16_d32_controller_write_transaction(.address16(16'h2b4c), .data32(32'h3123_1507));
controller_read_data32();
a16_d32_controller_write_transaction(.address16(16'h2b4d), .data32(32'h3123_1508));
controller_read_data32();
a16_d32_controller_write_transaction(.address16(16'h2b4e), .data32(32'h3123_1509));
controller_read_data32();
a16_d32_controller_write_transaction(.address16(16'h2b4f), .data32(32'h3123_150a));
controller_read_data32();
controller_clock_delay(64);
peripheral_clock_delay(64);
a16_controller_read_transaction(.address16(16'h2b4c));
a16_controller_read_transaction(.address16(16'h2b4d));
a16_controller_read_transaction(.address16(16'h2b4e));
a16_controller_read_transaction(.address16(16'h2b4f));
end
controller_clock_delay(64);
peripheral_clock_delay(64);
pre_register_select <= 1;
pre_read <= 1;
pre_bus <= 8'h33;
pulse_enable();
controller_set_address16(16'h1b4f);
controller_read_data32();
controller_clock_delay(64);
peripheral_clock_delay(64);
pre_register_select <= 1;
pre_read <= 0;
pre_bus <= 8'h66;
pulse_enable();
controller_set_address16(16'h4f1b);
controller_write_data32(32'h3123_2d78);
controller_clock_delay(64);
peripheral_clock_delay(64);
pre_register_select <= 0;
pre_read <= 0;
pre_bus <= 8'h99;
pulse_enable();
controller_set_address16(16'h1b4f);
controller_read_data32();
pre_register_select <= 0;
pre_read <= 0;
pre_enable <= 0;
controller_clock_delay(64);
peripheral_clock_delay(64);
#300; reset <= 1; #300; reset <= 0;
#300;
end
always @(posedge clock) begin
register_select <= #1 pre_register_select;
read <= #1 pre_read;
enable <= #1 pre_enable;
end
always begin
#HALF_PERIOD_OF_PERIPHERAL;
clock100_p <= #1.5 ~clock100_p;
clock100_n <= #2.5 ~clock100_n;
end
always begin
#HALF_PERIOD_OF_CONTROLLER;
clock <= #0.625 ~clock;
end
endmodule | 2 |
5,986 | data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v | 115,035,459 | mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v | v | 743 | 357 | [] | [] | [] | null | line:304: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:6: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:7: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:9: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:10: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:11: Cannot find include file: lib/half_duplex_rpi_bus.v\n`include "lib/half_duplex_rpi_bus.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:12: Cannot find include file: lib/sequencer.v\n`include "lib/sequencer.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:13: Cannot find include file: lib/reset.v\n`include "lib/reset.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:14: Cannot find include file: lib/histogram.v\n`include "lib/histogram.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:15: Cannot find include file: lib/fifo.v\n`include "lib/fifo.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:198: Define or directive not defined: \'`LOG2_OF_BASE_BLOCK_MEMORY_SIZE\'\n localparam PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + LOG2_OF_OSERDES_DATA_WIDTH - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:198: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + LOG2_OF_OSERDES_DATA_WIDTH - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:372: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:428: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:437: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:467: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:572: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:572: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:573: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:574: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:659: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:659: Unsupported: Ignoring delay on this delayed statement.\n #300; reset <= 1; #300; reset <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:660: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:669: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test052.simple-parallel-interface-and-pollable-memory.althea.revBLM.v:674: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Error: Exiting due to 11 error(s), 13 warning(s)\n' | 6,800 | module | module myalthea (
input clock100_p, clock100_n,
inout [5:0] coax,
output rpi_gpio2_i2c1_sda,
input rpi_gpio3_i2c1_scl,
input rpi_gpio4_gpclk0,
input rpi_gpio5,
inout rpi_gpio6_gpclk2, rpi_gpio7_spi_ce1, rpi_gpio8_spi_ce0, rpi_gpio9_spi_miso,
inout rpi_gpio10_spi_mosi, rpi_gpio11_spi_sclk, rpi_gpio12, rpi_gpio13,
inout rpi_gpio14, rpi_gpio15, rpi_gpio16, rpi_gpio17,
inout rpi_gpio18, rpi_gpio19, rpi_gpio20, rpi_gpio21,
a_p, a_n, b_p, b_n, c_p, c_n,
d_p, d_n, e_p, e_n, f_p, f_n,
g_p, g_n, h_p, h_n, j_p, j_n,
k_p, k_n, l_p, l_n, m_p, m_n,
n, p, q, r, s, t,
u, v, w, x, y, z,
input button,
output [3:0] coax_led,
input [2:0] rot
);
localparam BUS_WIDTH = 16;
localparam BANK_ADDRESS_DEPTH = 12;
localparam TRANSACTIONS_PER_DATA_WORD = 2;
localparam TRANSACTIONS_PER_ADDRESS_WORD = 1;
localparam ADDRESS_AUTOINCREMENT_MODE = 1;
wire clock10 = 0;
wire [3:0] internal_coax_led;
wire [7:0] internal_led;
assign coax_led = internal_coax_led;
top #(
.TESTBENCH(0),
.BUS_WIDTH(BUS_WIDTH), .BANK_ADDRESS_DEPTH(BANK_ADDRESS_DEPTH),
.TRANSACTIONS_PER_DATA_WORD(TRANSACTIONS_PER_DATA_WORD),
.TRANSACTIONS_PER_ADDRESS_WORD(TRANSACTIONS_PER_ADDRESS_WORD),
.ADDRESS_AUTOINCREMENT_MODE(ADDRESS_AUTOINCREMENT_MODE)
) althea (
.clock100_p(clock100_p), .clock100_n(clock100_n), .clock10(clock10), .reset(~button),
.coax(coax),
.bus({
rpi_gpio21, rpi_gpio20, rpi_gpio19, rpi_gpio18,
rpi_gpio17, rpi_gpio16, rpi_gpio15, rpi_gpio14,
rpi_gpio13, rpi_gpio12, rpi_gpio11_spi_sclk, rpi_gpio10_spi_mosi,
rpi_gpio9_spi_miso, rpi_gpio8_spi_ce0, rpi_gpio7_spi_ce1, rpi_gpio6_gpclk2
}),
.diff_pair_left({ a_n, a_p, c_n, c_p, d_n, d_p, f_n, f_p, b_n, b_p, e_n, e_p }),
.diff_pair_right({ g_n, g_p, j_n, j_p, l_n, l_p, m_n, m_p, h_n, h_p, k_n, k_p }),
.single_ended_left({ z, y, x, w, v, u }),
.single_ended_right({ n, p, q, r, s, t }),
.register_select(rpi_gpio3_i2c1_scl), .read(rpi_gpio5),
.enable(rpi_gpio4_gpclk0), .ack_valid(rpi_gpio2_i2c1_sda),
.coax_led(internal_coax_led),
.led(internal_led),
.rot(rot)
);
endmodule | module myalthea (
input clock100_p, clock100_n,
inout [5:0] coax,
output rpi_gpio2_i2c1_sda,
input rpi_gpio3_i2c1_scl,
input rpi_gpio4_gpclk0,
input rpi_gpio5,
inout rpi_gpio6_gpclk2, rpi_gpio7_spi_ce1, rpi_gpio8_spi_ce0, rpi_gpio9_spi_miso,
inout rpi_gpio10_spi_mosi, rpi_gpio11_spi_sclk, rpi_gpio12, rpi_gpio13,
inout rpi_gpio14, rpi_gpio15, rpi_gpio16, rpi_gpio17,
inout rpi_gpio18, rpi_gpio19, rpi_gpio20, rpi_gpio21,
a_p, a_n, b_p, b_n, c_p, c_n,
d_p, d_n, e_p, e_n, f_p, f_n,
g_p, g_n, h_p, h_n, j_p, j_n,
k_p, k_n, l_p, l_n, m_p, m_n,
n, p, q, r, s, t,
u, v, w, x, y, z,
input button,
output [3:0] coax_led,
input [2:0] rot
); |
localparam BUS_WIDTH = 16;
localparam BANK_ADDRESS_DEPTH = 12;
localparam TRANSACTIONS_PER_DATA_WORD = 2;
localparam TRANSACTIONS_PER_ADDRESS_WORD = 1;
localparam ADDRESS_AUTOINCREMENT_MODE = 1;
wire clock10 = 0;
wire [3:0] internal_coax_led;
wire [7:0] internal_led;
assign coax_led = internal_coax_led;
top #(
.TESTBENCH(0),
.BUS_WIDTH(BUS_WIDTH), .BANK_ADDRESS_DEPTH(BANK_ADDRESS_DEPTH),
.TRANSACTIONS_PER_DATA_WORD(TRANSACTIONS_PER_DATA_WORD),
.TRANSACTIONS_PER_ADDRESS_WORD(TRANSACTIONS_PER_ADDRESS_WORD),
.ADDRESS_AUTOINCREMENT_MODE(ADDRESS_AUTOINCREMENT_MODE)
) althea (
.clock100_p(clock100_p), .clock100_n(clock100_n), .clock10(clock10), .reset(~button),
.coax(coax),
.bus({
rpi_gpio21, rpi_gpio20, rpi_gpio19, rpi_gpio18,
rpi_gpio17, rpi_gpio16, rpi_gpio15, rpi_gpio14,
rpi_gpio13, rpi_gpio12, rpi_gpio11_spi_sclk, rpi_gpio10_spi_mosi,
rpi_gpio9_spi_miso, rpi_gpio8_spi_ce0, rpi_gpio7_spi_ce1, rpi_gpio6_gpclk2
}),
.diff_pair_left({ a_n, a_p, c_n, c_p, d_n, d_p, f_n, f_p, b_n, b_p, e_n, e_p }),
.diff_pair_right({ g_n, g_p, j_n, j_p, l_n, l_p, m_n, m_p, h_n, h_p, k_n, k_p }),
.single_ended_left({ z, y, x, w, v, u }),
.single_ended_right({ n, p, q, r, s, t }),
.register_select(rpi_gpio3_i2c1_scl), .read(rpi_gpio5),
.enable(rpi_gpio4_gpclk0), .ack_valid(rpi_gpio2_i2c1_sda),
.coax_led(internal_coax_led),
.led(internal_led),
.rot(rot)
);
endmodule | 2 |
5,990 | data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v | 115,035,459 | mza-test056.palimpsest.cylon.althea.revA.v | v | 290 | 202 | [] | [] | [] | null | line:304: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:6: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:7: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:9: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:10: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:11: Cannot find include file: lib/half_duplex_rpi_bus.v\n`include "lib/half_duplex_rpi_bus.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:12: Cannot find include file: lib/sequencer.v\n`include "lib/sequencer.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:13: Cannot find include file: lib/reset.v\n`include "lib/reset.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:14: Cannot find include file: lib/edge_to_pulse.v\n`include "lib/edge_to_pulse.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:49: syntax error, unexpected null, expecting IDENTIFIER or do or final\n wire [7:0] null = 0;\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:51: syntax error, unexpected \'=\', expecting \',\' or \';\'\n wire [7:0] pat [COUNTER_SIZE-COUNTER_PICKOFF-1:0] = { 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111 };\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:180: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:215: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:216: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:222: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:227: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Error: Exiting due to 10 error(s), 5 warning(s)\n' | 6,804 | module | module top #(
parameter OSERDES_DATA_WIDTH = 8,
parameter LOG2_OF_OSERDES_DATA_WIDTH = $clog2(OSERDES_DATA_WIDTH),
parameter LOG2_OF_OSERDES_EXTENDED_DATA_WIDTH = $clog2(64),
parameter TESTBENCH = 0,
parameter COUNTER_PICKOFF = TESTBENCH ? 6 : $clog2(2500000) - LOG2_OF_OSERDES_DATA_WIDTH,
parameter COUNTER_SIZE = COUNTER_PICKOFF + 3,
parameter COUNTER100_BIT_PICKOFF = TESTBENCH ? 5 : 23,
parameter COUNTERWORD_BIT_PICKOFF = TESTBENCH ? 5 : 23
) (
input clock50_p, clock50_n,
inout [5:0] coax,
output [12:1] signal,
output [7:0] led,
output [3:0] coax_led
);
localparam PERIOD = 10.0;
localparam MULTIPLY = 8;
localparam DIVIDE = 2;
localparam EXTRA_DIVIDE = 3;
localparam SCOPE = "BUFPLL";
reg [7:0] pattern [12:1];
wire [7:0] null = 0;
wire [7:0] pat [COUNTER_SIZE-COUNTER_PICKOFF-1:0] = { 8'b11111111, 8'b11111111, 8'b11111111, 8'b11111111, 8'b11111111, 8'b11111111, 8'b11111111, 8'b11111111 };
wire [3:0] status4;
wire [7:0] status8;
wire reset;
assign reset = 0;
reg [7:0] sync_out_word_alternate = 0;
genvar i;
reg [COUNTER_SIZE:0] counter = 0;
wire word_clock;
wire reset_word;
always @(posedge word_clock) begin
if (reset_word) begin
counter <= 0;
end else begin
counter <= counter + 1'b1;
end
end
always @(posedge word_clock) begin
pattern[1] <= null;
pattern[2] <= null;
pattern[3] <= null;
pattern[4] <= null;
pattern[5] <= null;
pattern[6] <= null;
pattern[7] <= null;
pattern[8] <= null;
pattern[9] <= null;
pattern[10] <= null;
pattern[11] <= null;
pattern[12] <= null;
sync_out_word_alternate <= null;
if (reset_word) begin
end else begin
if (counter[COUNTER_PICKOFF:0]==1) begin
sync_out_word_alternate <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
pattern[1] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==2) begin
pattern[2] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==3) begin
pattern[3] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==4) begin
pattern[4] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==5) begin
pattern[5] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==6) begin
pattern[6] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==7) begin
pattern[7] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==8) begin
pattern[8] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==9) begin
pattern[9] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==10) begin
pattern[10] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==11) begin
pattern[11] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==12) begin
pattern[12] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end
end
end
wire pll_oserdes_locked;
wire clock100;
wire clock50_locked;
wire reset100;
if (1) begin
wire clock50_raw;
IBUFGDS mybuf50_raw1 (.I(clock50_p), .IB(clock50_n), .O(clock50_raw));
wire clock100_raw;
simpledcm_CLKGEN #(.MULTIPLY(2), .DIVIDE(1), .PERIOD(20.0)) mydcm50 (.clockin(clock50_raw), .reset(reset), .clockout(clock100_raw), .clockout180(), .locked(clock50_locked));
BUFG mybuf50_raw2 (.I(clock100_raw), .O(clock100));
reset_wait4pll #(.COUNTER_BIT_PICKOFF(COUNTER100_BIT_PICKOFF)) reset100_wait4pll (.reset_input(reset), .pll_locked_input(clock50_locked), .clock_input(clock100), .reset_output(reset100));
end else begin
wire clock100_locked;
dummy_dcm_diff_input lollipop (.clock_p(clock100_p), .clock_n(clock100_n), .reset(reset), .clock_out(clock100), .clock_locked(clock100_locked));
reset_wait4pll #(.COUNTER_BIT_PICKOFF(COUNTER100_BIT_PICKOFF)) reset100_wait4pll (.reset_input(reset), .pll_locked_input(clock100_locked), .clock_input(clock100), .reset_output(reset100));
end
reset_wait4pll #(.COUNTER_BIT_PICKOFF(COUNTERWORD_BIT_PICKOFF)) resetword_wait4pll (.reset_input(reset100), .pll_locked_input(pll_oserdes_locked), .clock_input(word_clock), .reset_output(reset_word));
wire [7:0] dummy = 0;
wire strobe_is_alignedA, strobe_is_alignedB, strobe_is_alignedC, strobe_is_alignedD;
ocyrus_triacontahedron8_split_12_6_6_4_2_D0input #(
.BIT_DEPTH(8), .PERIOD(PERIOD), .MULTIPLY(MULTIPLY), .DIVIDE(DIVIDE), .EXTRA_DIVIDE(EXTRA_DIVIDE), .SCOPE(SCOPE)
) orama (
.clock_in(clock100), .reset(reset100),
.word_A11_in(dummy), .word_A10_in(dummy), .word_A09_in(dummy), .word_A08_in(dummy), .word_A07_in(dummy), .word_A06_in(dummy),
.word_A05_in(dummy), .word_A04_in(dummy), .word_A03_in(dummy), .word_A02_in(dummy), .word_A01_in(dummy), .word_A00_in(dummy),
.word_B5_in(pattern[12]), .word_B4_in(pattern[11]), .word_B3_in(pattern[10]), .word_B2_in(pattern[6]), .word_B1_in(pattern[5]), .word_B0_in(pattern[4]),
.word_C5_in(pattern[9]), .word_C4_in(pattern[8]), .word_C3_in(pattern[7]), .word_C2_in(pattern[3]), .word_C1_in(pattern[2]), .word_C0_in(pattern[1]),
.word_D3_in(dummy), .word_D2_in(dummy), .word_D1_in(dummy), .word_D0_out(),
.word_E1_in(dummy), .word_E0_in(sync_out_word_alternate),
.word_clockA_out(word_clock), .word_clockB_out(), .word_clockC_out(), .word_clockD_out(), .word_clockE_out(),
.A11_out(), .A10_out(), .A09_out(), .A08_out(), .A07_out(), .A06_out(),
.A05_out(), .A04_out(), .A03_out(), .A02_out(), .A01_out(), .A00_out(),
.B5_out(signal[12]), .B4_out(signal[11]), .B3_out(signal[10]), .B2_out(signal[6]), .B1_out(signal[5]), .B0_out(signal[4]),
.C5_out(signal[9]), .C4_out(signal[8]), .C3_out(signal[7]), .C2_out(signal[3]), .C1_out(signal[2]), .C0_out(signal[1]),
.D3_out(coax[3]), .D2_out(coax[2]), .D1_out(coax[1]), .D0_in(coax[0]),
.E1_out(coax[5]), .E0_out(coax[4]),
.strobe_is_alignedA(strobe_is_alignedA), .strobe_is_alignedB(strobe_is_alignedB), .strobe_is_alignedC(strobe_is_alignedC), .strobe_is_alignedD(strobe_is_alignedD),
.locked(pll_oserdes_locked)
);
if (0) begin
assign status4 = 0;
assign status8 = 0;
end else begin
assign status4[3] = ~pll_oserdes_locked;
assign status4[2] = 0;
assign status4[1] = 0;
assign status4[0] = 0;
assign status8[7] = ~clock50_locked;
assign status8[6] = reset100;
assign status8[5] = ~pll_oserdes_locked;
assign status8[4] = reset_word;
assign status8[3] = ~strobe_is_alignedA;
assign status8[2] = ~strobe_is_alignedB;
assign status8[1] = ~strobe_is_alignedC;
assign status8[0] = ~strobe_is_alignedD;
end
assign coax_led = status4;
assign led = status8;
initial begin
#100;
end
endmodule | module top #(
parameter OSERDES_DATA_WIDTH = 8,
parameter LOG2_OF_OSERDES_DATA_WIDTH = $clog2(OSERDES_DATA_WIDTH),
parameter LOG2_OF_OSERDES_EXTENDED_DATA_WIDTH = $clog2(64),
parameter TESTBENCH = 0,
parameter COUNTER_PICKOFF = TESTBENCH ? 6 : $clog2(2500000) - LOG2_OF_OSERDES_DATA_WIDTH,
parameter COUNTER_SIZE = COUNTER_PICKOFF + 3,
parameter COUNTER100_BIT_PICKOFF = TESTBENCH ? 5 : 23,
parameter COUNTERWORD_BIT_PICKOFF = TESTBENCH ? 5 : 23
) (
input clock50_p, clock50_n,
inout [5:0] coax,
output [12:1] signal,
output [7:0] led,
output [3:0] coax_led
); |
localparam PERIOD = 10.0;
localparam MULTIPLY = 8;
localparam DIVIDE = 2;
localparam EXTRA_DIVIDE = 3;
localparam SCOPE = "BUFPLL";
reg [7:0] pattern [12:1];
wire [7:0] null = 0;
wire [7:0] pat [COUNTER_SIZE-COUNTER_PICKOFF-1:0] = { 8'b11111111, 8'b11111111, 8'b11111111, 8'b11111111, 8'b11111111, 8'b11111111, 8'b11111111, 8'b11111111 };
wire [3:0] status4;
wire [7:0] status8;
wire reset;
assign reset = 0;
reg [7:0] sync_out_word_alternate = 0;
genvar i;
reg [COUNTER_SIZE:0] counter = 0;
wire word_clock;
wire reset_word;
always @(posedge word_clock) begin
if (reset_word) begin
counter <= 0;
end else begin
counter <= counter + 1'b1;
end
end
always @(posedge word_clock) begin
pattern[1] <= null;
pattern[2] <= null;
pattern[3] <= null;
pattern[4] <= null;
pattern[5] <= null;
pattern[6] <= null;
pattern[7] <= null;
pattern[8] <= null;
pattern[9] <= null;
pattern[10] <= null;
pattern[11] <= null;
pattern[12] <= null;
sync_out_word_alternate <= null;
if (reset_word) begin
end else begin
if (counter[COUNTER_PICKOFF:0]==1) begin
sync_out_word_alternate <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
pattern[1] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==2) begin
pattern[2] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==3) begin
pattern[3] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==4) begin
pattern[4] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==5) begin
pattern[5] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==6) begin
pattern[6] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==7) begin
pattern[7] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==8) begin
pattern[8] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==9) begin
pattern[9] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==10) begin
pattern[10] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==11) begin
pattern[11] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end else if (counter[COUNTER_PICKOFF:0]==12) begin
pattern[12] <= pat[counter[COUNTER_SIZE:COUNTER_PICKOFF+1]];
end
end
end
wire pll_oserdes_locked;
wire clock100;
wire clock50_locked;
wire reset100;
if (1) begin
wire clock50_raw;
IBUFGDS mybuf50_raw1 (.I(clock50_p), .IB(clock50_n), .O(clock50_raw));
wire clock100_raw;
simpledcm_CLKGEN #(.MULTIPLY(2), .DIVIDE(1), .PERIOD(20.0)) mydcm50 (.clockin(clock50_raw), .reset(reset), .clockout(clock100_raw), .clockout180(), .locked(clock50_locked));
BUFG mybuf50_raw2 (.I(clock100_raw), .O(clock100));
reset_wait4pll #(.COUNTER_BIT_PICKOFF(COUNTER100_BIT_PICKOFF)) reset100_wait4pll (.reset_input(reset), .pll_locked_input(clock50_locked), .clock_input(clock100), .reset_output(reset100));
end else begin
wire clock100_locked;
dummy_dcm_diff_input lollipop (.clock_p(clock100_p), .clock_n(clock100_n), .reset(reset), .clock_out(clock100), .clock_locked(clock100_locked));
reset_wait4pll #(.COUNTER_BIT_PICKOFF(COUNTER100_BIT_PICKOFF)) reset100_wait4pll (.reset_input(reset), .pll_locked_input(clock100_locked), .clock_input(clock100), .reset_output(reset100));
end
reset_wait4pll #(.COUNTER_BIT_PICKOFF(COUNTERWORD_BIT_PICKOFF)) resetword_wait4pll (.reset_input(reset100), .pll_locked_input(pll_oserdes_locked), .clock_input(word_clock), .reset_output(reset_word));
wire [7:0] dummy = 0;
wire strobe_is_alignedA, strobe_is_alignedB, strobe_is_alignedC, strobe_is_alignedD;
ocyrus_triacontahedron8_split_12_6_6_4_2_D0input #(
.BIT_DEPTH(8), .PERIOD(PERIOD), .MULTIPLY(MULTIPLY), .DIVIDE(DIVIDE), .EXTRA_DIVIDE(EXTRA_DIVIDE), .SCOPE(SCOPE)
) orama (
.clock_in(clock100), .reset(reset100),
.word_A11_in(dummy), .word_A10_in(dummy), .word_A09_in(dummy), .word_A08_in(dummy), .word_A07_in(dummy), .word_A06_in(dummy),
.word_A05_in(dummy), .word_A04_in(dummy), .word_A03_in(dummy), .word_A02_in(dummy), .word_A01_in(dummy), .word_A00_in(dummy),
.word_B5_in(pattern[12]), .word_B4_in(pattern[11]), .word_B3_in(pattern[10]), .word_B2_in(pattern[6]), .word_B1_in(pattern[5]), .word_B0_in(pattern[4]),
.word_C5_in(pattern[9]), .word_C4_in(pattern[8]), .word_C3_in(pattern[7]), .word_C2_in(pattern[3]), .word_C1_in(pattern[2]), .word_C0_in(pattern[1]),
.word_D3_in(dummy), .word_D2_in(dummy), .word_D1_in(dummy), .word_D0_out(),
.word_E1_in(dummy), .word_E0_in(sync_out_word_alternate),
.word_clockA_out(word_clock), .word_clockB_out(), .word_clockC_out(), .word_clockD_out(), .word_clockE_out(),
.A11_out(), .A10_out(), .A09_out(), .A08_out(), .A07_out(), .A06_out(),
.A05_out(), .A04_out(), .A03_out(), .A02_out(), .A01_out(), .A00_out(),
.B5_out(signal[12]), .B4_out(signal[11]), .B3_out(signal[10]), .B2_out(signal[6]), .B1_out(signal[5]), .B0_out(signal[4]),
.C5_out(signal[9]), .C4_out(signal[8]), .C3_out(signal[7]), .C2_out(signal[3]), .C1_out(signal[2]), .C0_out(signal[1]),
.D3_out(coax[3]), .D2_out(coax[2]), .D1_out(coax[1]), .D0_in(coax[0]),
.E1_out(coax[5]), .E0_out(coax[4]),
.strobe_is_alignedA(strobe_is_alignedA), .strobe_is_alignedB(strobe_is_alignedB), .strobe_is_alignedC(strobe_is_alignedC), .strobe_is_alignedD(strobe_is_alignedD),
.locked(pll_oserdes_locked)
);
if (0) begin
assign status4 = 0;
assign status8 = 0;
end else begin
assign status4[3] = ~pll_oserdes_locked;
assign status4[2] = 0;
assign status4[1] = 0;
assign status4[0] = 0;
assign status8[7] = ~clock50_locked;
assign status8[6] = reset100;
assign status8[5] = ~pll_oserdes_locked;
assign status8[4] = reset_word;
assign status8[3] = ~strobe_is_alignedA;
assign status8[2] = ~strobe_is_alignedB;
assign status8[1] = ~strobe_is_alignedC;
assign status8[0] = ~strobe_is_alignedD;
end
assign coax_led = status4;
assign led = status8;
initial begin
#100;
end
endmodule | 2 |
5,991 | data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v | 115,035,459 | mza-test056.palimpsest.cylon.althea.revA.v | v | 290 | 202 | [] | [] | [] | null | line:304: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:6: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:7: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:9: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:10: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:11: Cannot find include file: lib/half_duplex_rpi_bus.v\n`include "lib/half_duplex_rpi_bus.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:12: Cannot find include file: lib/sequencer.v\n`include "lib/sequencer.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:13: Cannot find include file: lib/reset.v\n`include "lib/reset.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:14: Cannot find include file: lib/edge_to_pulse.v\n`include "lib/edge_to_pulse.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:49: syntax error, unexpected null, expecting IDENTIFIER or do or final\n wire [7:0] null = 0;\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:51: syntax error, unexpected \'=\', expecting \',\' or \';\'\n wire [7:0] pat [COUNTER_SIZE-COUNTER_PICKOFF-1:0] = { 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111 };\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:180: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:215: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:216: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:222: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:227: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Error: Exiting due to 10 error(s), 5 warning(s)\n' | 6,804 | module | module top_tb;
localparam HALF_PERIOD_OF_CONTROLLER = 1;
localparam HALF_PERIOD_OF_PERIPHERAL = 10;
localparam NUMBER_OF_PERIODS_OF_CONTROLLER_IN_A_DELAY = 1;
localparam NUMBER_OF_PERIODS_OF_CONTROLLER_WHILE_WAITING_FOR_ACK = 2000;
reg clock = 0;
reg clock50_p = 0;
reg clock50_n = 1;
wire [5:0] coax;
wire [3:0] coax_led;
wire [7:0] led;
wire a_n, a_p, c_n, c_p, d_n, d_p, f_n, f_p, b_n, b_p, e_n, e_p;
wire m_p, m_n, l_p, l_n, j_p, j_n, g_p, g_n, k_p, k_n, h_p, h_n;
wire z, y, x, w, v, u;
wire n, p, q, r, s, t;
wire [12:1] signal;
top #(
.TESTBENCH(1)
) althea (
.clock50_p(clock50_p), .clock50_n(clock50_n),
.coax(coax),
.signal(signal),
.led(led), .coax_led(coax_led)
);
initial begin
#512;
#512;
end
always begin
#HALF_PERIOD_OF_PERIPHERAL;
clock50_p <= #1.5 ~clock50_p;
clock50_n <= #2.5 ~clock50_n;
end
always begin
#HALF_PERIOD_OF_CONTROLLER;
clock <= #0.625 ~clock;
end
endmodule | module top_tb; |
localparam HALF_PERIOD_OF_CONTROLLER = 1;
localparam HALF_PERIOD_OF_PERIPHERAL = 10;
localparam NUMBER_OF_PERIODS_OF_CONTROLLER_IN_A_DELAY = 1;
localparam NUMBER_OF_PERIODS_OF_CONTROLLER_WHILE_WAITING_FOR_ACK = 2000;
reg clock = 0;
reg clock50_p = 0;
reg clock50_n = 1;
wire [5:0] coax;
wire [3:0] coax_led;
wire [7:0] led;
wire a_n, a_p, c_n, c_p, d_n, d_p, f_n, f_p, b_n, b_p, e_n, e_p;
wire m_p, m_n, l_p, l_n, j_p, j_n, g_p, g_n, k_p, k_n, h_p, h_n;
wire z, y, x, w, v, u;
wire n, p, q, r, s, t;
wire [12:1] signal;
top #(
.TESTBENCH(1)
) althea (
.clock50_p(clock50_p), .clock50_n(clock50_n),
.coax(coax),
.signal(signal),
.led(led), .coax_led(coax_led)
);
initial begin
#512;
#512;
end
always begin
#HALF_PERIOD_OF_PERIPHERAL;
clock50_p <= #1.5 ~clock50_p;
clock50_n <= #2.5 ~clock50_n;
end
always begin
#HALF_PERIOD_OF_CONTROLLER;
clock <= #0.625 ~clock;
end
endmodule | 2 |
5,992 | data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v | 115,035,459 | mza-test056.palimpsest.cylon.althea.revA.v | v | 290 | 202 | [] | [] | [] | null | line:304: before: "if" | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:6: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:7: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:9: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:10: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:11: Cannot find include file: lib/half_duplex_rpi_bus.v\n`include "lib/half_duplex_rpi_bus.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:12: Cannot find include file: lib/sequencer.v\n`include "lib/sequencer.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:13: Cannot find include file: lib/reset.v\n`include "lib/reset.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:14: Cannot find include file: lib/edge_to_pulse.v\n`include "lib/edge_to_pulse.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:49: syntax error, unexpected null, expecting IDENTIFIER or do or final\n wire [7:0] null = 0;\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:51: syntax error, unexpected \'=\', expecting \',\' or \';\'\n wire [7:0] pat [COUNTER_SIZE-COUNTER_PICKOFF-1:0] = { 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111 };\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:180: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:215: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:216: Unsupported: Ignoring delay on this delayed statement.\n #512; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:222: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_PERIPHERAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:227: Unsupported: Ignoring delay on this delayed statement.\n #HALF_PERIOD_OF_CONTROLLER;\n ^\n%Error: Exiting due to 10 error(s), 5 warning(s)\n' | 6,804 | module | module myalthea #(
) (
input clock50_p, clock50_n,
inout coax4,
a_p, b_p, c_p, d_p, e_p, f_p,
g_p, h_p, j_p, k_p, l_p, m_p,
output [7:0] led
);
wire [3:0] internal_coax_led;
wire [7:0] internal_led;
assign led = internal_led;
wire [5:0] diff_pair_left;
assign { a_n, c_n, d_n, f_n, b_n, e_n } = diff_pair_left;
wire coax5, coax3, coax2, coax1, coax0;
wire [12:1] signal;
assign { b_p, d_p, f_p, h_p, l_p, m_p, a_p, c_p, e_p, g_p, j_p, k_p } = signal;
top #(
.TESTBENCH(0)
) althea (
.clock50_p(clock50_p), .clock50_n(clock50_n),
.coax({coax5, coax4, coax3, coax2, coax1, coax0}),
.signal(signal),
.led(internal_led),
.coax_led(internal_coax_led)
);
endmodule | module myalthea #(
) (
input clock50_p, clock50_n,
inout coax4,
a_p, b_p, c_p, d_p, e_p, f_p,
g_p, h_p, j_p, k_p, l_p, m_p,
output [7:0] led
); |
wire [3:0] internal_coax_led;
wire [7:0] internal_led;
assign led = internal_led;
wire [5:0] diff_pair_left;
assign { a_n, c_n, d_n, f_n, b_n, e_n } = diff_pair_left;
wire coax5, coax3, coax2, coax1, coax0;
wire [12:1] signal;
assign { b_p, d_p, f_p, h_p, l_p, m_p, a_p, c_p, e_p, g_p, j_p, k_p } = signal;
top #(
.TESTBENCH(0)
) althea (
.clock50_p(clock50_p), .clock50_n(clock50_n),
.coax({coax5, coax4, coax3, coax2, coax1, coax0}),
.signal(signal),
.led(internal_led),
.coax_led(internal_coax_led)
);
endmodule | 2 |
5,996 | data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv | 115,035,459 | axi4.sv | sv | 942 | 223 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:5: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:6: Cannot find include file: lib/DebugInfoWarningError.sv\n`include "lib/DebugInfoWarningError.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:341: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:344: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:738: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:741: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:905: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:908: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:7: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport DebugInfoWarningError::*;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:99: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:105: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:106: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:107: syntax error, unexpected \'.\', expecting ::\n wire wbeat = axi.wready & axi.wvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:108: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:109: syntax error, unexpected \'.\', expecting ::\n wire bbeat = axi.bready & axi.bvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:112: syntax error, unexpected \'.\', expecting ::\n always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:113: syntax error, unexpected \'.\', expecting ::\n always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:118: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:121: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:128: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:131: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:135: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:142: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:143: Unsupported: Dynamic array new\n data = new[1];\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:148: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:153: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY; $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:157: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:190: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:208: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:347: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:348: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:376: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:386: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:387: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:388: syntax error, unexpected \'.\', expecting ::\n wire wbeat = axi.wready & axi.wvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:389: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:390: syntax error, unexpected \'.\', expecting ::\n wire bbeat = axi.bready & axi.bvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:393: syntax error, unexpected \'.\', expecting ::\n always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:394: syntax error, unexpected \'.\', expecting ::\n always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:399: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:403: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:407: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:410: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_READ_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:418: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:422: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:428: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:436: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:440: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:446: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:449: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:453: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:454: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:455: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:456: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:465: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:466: Unsupported: Dynamic array new\n data = new[2**LEN_WIDTH];\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:490: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:502: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY; $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:506: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:546: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:566: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:744: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:745: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:753: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.peripheral axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:766: syntax error, unexpected IDENTIFIER\n axi4 modified_copy(clock, reset);\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:768: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: Exiting due to 38 error(s), 28 warning(s)\n' | 6,806 | module | module parallel_peripheral_axi4_controller__pollable_memory_axi4_peripheral__tb;
localparam ADDRESS_WIDTH = 4;
localparam DATA_WIDTH = 32;
localparam LEN_WIDTH = 5;
localparam FREQUENCY_OF_CLOCK_HZ = 10000000;
localparam PERIOD_OF_CLOCK_NS = 1000000000.0/FREQUENCY_OF_CLOCK_HZ;
localparam DELAY_BETWEEN_TRANSACTIONS = 4*PERIOD_OF_CLOCK_NS;
localparam DELAY_BETWEEN_WRITE_BEATS = 1*PERIOD_OF_CLOCK_NS;
localparam DELAY_BETWEEN_READ_BEATS = 1*PERIOD_OF_CLOCK_NS;
localparam LONG_DELAY = 8*PERIOD_OF_CLOCK_NS;
wire clock;
clock #(.FREQUENCY_OF_CLOCK_HZ(FREQUENCY_OF_CLOCK_HZ)) clockmod (.clock(clock));
reg reset = 1;
reg [ADDRESS_WIDTH-1:0] pre_parallel_write_address = 0;
reg [ADDRESS_WIDTH-1:0] parallel_write_address = 0;
reg pre_parallel_write_address_valid = 0;
reg parallel_write_address_valid = 0;
reg [DATA_WIDTH-1:0] pre_parallel_write_data = 0;
reg [DATA_WIDTH-1:0] parallel_write_data = 0;
reg [ADDRESS_WIDTH-1:0] pre_parallel_read_address = 0;
reg [ADDRESS_WIDTH-1:0] parallel_read_address = 0;
reg pre_parallel_read_address_valid = 0;
reg parallel_read_address_valid = 0;
wire [DATA_WIDTH-1:0] parallel_read_data;
axi4 axi(clock, reset);
reg pre_parallel_write_data_valid = 0;
reg parallel_write_data_valid = 0;
wire parallel_read_data_valid;
parallel_peripheral__axi4_controller #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) spac (.*);
pollable_memory__axi4_peripheral #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH), .LEN_WIDTH(LEN_WIDTH)) pmap (.*);
wire awbeat = axi.awready & axi.awvalid;
wire arbeat = axi.arready & axi.arvalid;
wire wbeat = axi.wready & axi.wvalid;
wire rbeat = axi.rready & axi.rvalid;
wire bbeat = axi.bready & axi.bvalid;
always @(posedge awbeat) begin $display("%t, awbeat %08x", $time, parallel_write_address); end
always @(posedge arbeat) begin $display("%t, arbeat %08x", $time, parallel_read_address); end
always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end
always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end
always @(posedge bbeat) begin $display("%t, bbeat", $time); end
task automatic controller_read_transaction(input [ADDRESS_WIDTH-1:0] address);
reg [ADDRESS_WIDTH:0] i;
begin
#DELAY_BETWEEN_TRANSACTIONS;
pre_parallel_read_address <= address;
pre_parallel_read_address_valid <= 1;
#PERIOD_OF_CLOCK_NS;
pre_parallel_read_address_valid <= 0;
end
endtask
task automatic controller_write_transaction(input [ADDRESS_WIDTH-1:0] address, input [DATA_WIDTH-1:0] data []);
reg [ADDRESS_WIDTH:0] i;
begin
#DELAY_BETWEEN_TRANSACTIONS;
pre_parallel_write_address <= address;
pre_parallel_write_address_valid <= 1;
#PERIOD_OF_CLOCK_NS;
pre_parallel_write_address_valid <= 0;
pre_parallel_write_data <= data[0];
pre_parallel_write_data_valid <= 1;
#PERIOD_OF_CLOCK_NS;
pre_parallel_write_data_valid <= 0;
end
endtask
reg [DATA_WIDTH-1:0] data [];
reg [31:0] i = 0;
initial begin
#DELAY_BETWEEN_TRANSACTIONS; reset <= 0;
data = new[1];
data[0] = 32'd0; controller_write_transaction(4'h0, data); controller_read_transaction(4'h0);
data[0] = 32'd1; controller_write_transaction(4'h1, data); controller_read_transaction(4'h1);
data[0] = 32'd2; controller_write_transaction(4'h2, data); controller_read_transaction(4'h2);
data[0] = 32'd3; controller_write_transaction(4'h3, data); controller_read_transaction(4'h3);
#LONG_DELAY;
data[0] = 32'd8; controller_write_transaction(4'h7, data); controller_read_transaction(4'h7);
data[0] = 32'd7; controller_write_transaction(4'h6, data); controller_read_transaction(4'h6);
data[0] = 32'd6; controller_write_transaction(4'h5, data); controller_read_transaction(4'h5);
data[0] = 32'd5; controller_write_transaction(4'h4, data); controller_read_transaction(4'h4);
#LONG_DELAY; $finish;
end
localparam DELAY = 0;
always @(posedge clock) begin
#DELAY;
if (reset) begin
parallel_write_address <= 0;
parallel_write_address_valid <= 0;
parallel_write_data <= 0;
parallel_write_data_valid <= 0;
parallel_read_address <= 0;
parallel_read_address_valid <= 0;
end else begin
parallel_write_address <= pre_parallel_write_address;
parallel_write_address_valid <= pre_parallel_write_address_valid;
parallel_write_data <= pre_parallel_write_data;
parallel_write_data_valid <= pre_parallel_write_data_valid;
parallel_read_address <= pre_parallel_read_address;
parallel_read_address_valid <= pre_parallel_read_address_valid;
end
end
endmodule | module parallel_peripheral_axi4_controller__pollable_memory_axi4_peripheral__tb; |
localparam ADDRESS_WIDTH = 4;
localparam DATA_WIDTH = 32;
localparam LEN_WIDTH = 5;
localparam FREQUENCY_OF_CLOCK_HZ = 10000000;
localparam PERIOD_OF_CLOCK_NS = 1000000000.0/FREQUENCY_OF_CLOCK_HZ;
localparam DELAY_BETWEEN_TRANSACTIONS = 4*PERIOD_OF_CLOCK_NS;
localparam DELAY_BETWEEN_WRITE_BEATS = 1*PERIOD_OF_CLOCK_NS;
localparam DELAY_BETWEEN_READ_BEATS = 1*PERIOD_OF_CLOCK_NS;
localparam LONG_DELAY = 8*PERIOD_OF_CLOCK_NS;
wire clock;
clock #(.FREQUENCY_OF_CLOCK_HZ(FREQUENCY_OF_CLOCK_HZ)) clockmod (.clock(clock));
reg reset = 1;
reg [ADDRESS_WIDTH-1:0] pre_parallel_write_address = 0;
reg [ADDRESS_WIDTH-1:0] parallel_write_address = 0;
reg pre_parallel_write_address_valid = 0;
reg parallel_write_address_valid = 0;
reg [DATA_WIDTH-1:0] pre_parallel_write_data = 0;
reg [DATA_WIDTH-1:0] parallel_write_data = 0;
reg [ADDRESS_WIDTH-1:0] pre_parallel_read_address = 0;
reg [ADDRESS_WIDTH-1:0] parallel_read_address = 0;
reg pre_parallel_read_address_valid = 0;
reg parallel_read_address_valid = 0;
wire [DATA_WIDTH-1:0] parallel_read_data;
axi4 axi(clock, reset);
reg pre_parallel_write_data_valid = 0;
reg parallel_write_data_valid = 0;
wire parallel_read_data_valid;
parallel_peripheral__axi4_controller #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) spac (.*);
pollable_memory__axi4_peripheral #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH), .LEN_WIDTH(LEN_WIDTH)) pmap (.*);
wire awbeat = axi.awready & axi.awvalid;
wire arbeat = axi.arready & axi.arvalid;
wire wbeat = axi.wready & axi.wvalid;
wire rbeat = axi.rready & axi.rvalid;
wire bbeat = axi.bready & axi.bvalid;
always @(posedge awbeat) begin $display("%t, awbeat %08x", $time, parallel_write_address); end
always @(posedge arbeat) begin $display("%t, arbeat %08x", $time, parallel_read_address); end
always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end
always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end
always @(posedge bbeat) begin $display("%t, bbeat", $time); end
task automatic controller_read_transaction(input [ADDRESS_WIDTH-1:0] address);
reg [ADDRESS_WIDTH:0] i;
begin
#DELAY_BETWEEN_TRANSACTIONS;
pre_parallel_read_address <= address;
pre_parallel_read_address_valid <= 1;
#PERIOD_OF_CLOCK_NS;
pre_parallel_read_address_valid <= 0;
end
endtask
task automatic controller_write_transaction(input [ADDRESS_WIDTH-1:0] address, input [DATA_WIDTH-1:0] data []);
reg [ADDRESS_WIDTH:0] i;
begin
#DELAY_BETWEEN_TRANSACTIONS;
pre_parallel_write_address <= address;
pre_parallel_write_address_valid <= 1;
#PERIOD_OF_CLOCK_NS;
pre_parallel_write_address_valid <= 0;
pre_parallel_write_data <= data[0];
pre_parallel_write_data_valid <= 1;
#PERIOD_OF_CLOCK_NS;
pre_parallel_write_data_valid <= 0;
end
endtask
reg [DATA_WIDTH-1:0] data [];
reg [31:0] i = 0;
initial begin
#DELAY_BETWEEN_TRANSACTIONS; reset <= 0;
data = new[1];
data[0] = 32'd0; controller_write_transaction(4'h0, data); controller_read_transaction(4'h0);
data[0] = 32'd1; controller_write_transaction(4'h1, data); controller_read_transaction(4'h1);
data[0] = 32'd2; controller_write_transaction(4'h2, data); controller_read_transaction(4'h2);
data[0] = 32'd3; controller_write_transaction(4'h3, data); controller_read_transaction(4'h3);
#LONG_DELAY;
data[0] = 32'd8; controller_write_transaction(4'h7, data); controller_read_transaction(4'h7);
data[0] = 32'd7; controller_write_transaction(4'h6, data); controller_read_transaction(4'h6);
data[0] = 32'd6; controller_write_transaction(4'h5, data); controller_read_transaction(4'h5);
data[0] = 32'd5; controller_write_transaction(4'h4, data); controller_read_transaction(4'h4);
#LONG_DELAY; $finish;
end
localparam DELAY = 0;
always @(posedge clock) begin
#DELAY;
if (reset) begin
parallel_write_address <= 0;
parallel_write_address_valid <= 0;
parallel_write_data <= 0;
parallel_write_data_valid <= 0;
parallel_read_address <= 0;
parallel_read_address_valid <= 0;
end else begin
parallel_write_address <= pre_parallel_write_address;
parallel_write_address_valid <= pre_parallel_write_address_valid;
parallel_write_data <= pre_parallel_write_data;
parallel_write_data_valid <= pre_parallel_write_data_valid;
parallel_read_address <= pre_parallel_read_address;
parallel_read_address_valid <= pre_parallel_read_address_valid;
end
end
endmodule | 2 |
5,997 | data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv | 115,035,459 | axi4.sv | sv | 942 | 223 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:5: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:6: Cannot find include file: lib/DebugInfoWarningError.sv\n`include "lib/DebugInfoWarningError.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:341: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:344: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:738: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:741: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:905: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:908: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:7: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport DebugInfoWarningError::*;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:99: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:105: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:106: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:107: syntax error, unexpected \'.\', expecting ::\n wire wbeat = axi.wready & axi.wvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:108: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:109: syntax error, unexpected \'.\', expecting ::\n wire bbeat = axi.bready & axi.bvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:112: syntax error, unexpected \'.\', expecting ::\n always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:113: syntax error, unexpected \'.\', expecting ::\n always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:118: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:121: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:128: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:131: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:135: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:142: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:143: Unsupported: Dynamic array new\n data = new[1];\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:148: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:153: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY; $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:157: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:190: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:208: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:347: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:348: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:376: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:386: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:387: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:388: syntax error, unexpected \'.\', expecting ::\n wire wbeat = axi.wready & axi.wvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:389: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:390: syntax error, unexpected \'.\', expecting ::\n wire bbeat = axi.bready & axi.bvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:393: syntax error, unexpected \'.\', expecting ::\n always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:394: syntax error, unexpected \'.\', expecting ::\n always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:399: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:403: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:407: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:410: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_READ_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:418: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:422: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:428: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:436: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:440: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:446: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:449: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:453: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:454: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:455: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:456: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:465: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:466: Unsupported: Dynamic array new\n data = new[2**LEN_WIDTH];\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:490: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:502: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY; $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:506: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:546: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:566: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:744: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:745: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:753: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.peripheral axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:766: syntax error, unexpected IDENTIFIER\n axi4 modified_copy(clock, reset);\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:768: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: Exiting due to 38 error(s), 28 warning(s)\n' | 6,806 | module | module parallel_peripheral__axi4_controller #(
parameter ADDRESS_WIDTH = 4,
parameter DATA_WIDTH = 32
) (
input [ADDRESS_WIDTH-1:0] parallel_write_address,
input parallel_write_address_valid,
input [DATA_WIDTH-1:0] parallel_write_data,
input parallel_write_data_valid,
input [ADDRESS_WIDTH-1:0] parallel_read_address,
input parallel_read_address_valid,
output reg [DATA_WIDTH-1:0] parallel_read_data = 0,
output reg parallel_read_data_valid = 0,
axi4.controller axi
);
assign axi.awburst = axi::FIXED;
assign axi.arburst = axi::FIXED;
assign axi.awlen = 0;
assign axi.arlen = 0;
reg [1:0] rstate = 0;
reg [2:0] wstate = 0;
reg last_write_was_succecssful = 0;
reg our_rlast = 0;
axi::state_t cw_state;
axi::state_t cr_state;
reg [31:0] error_count = 0;
localparam DELAY = 0;
always @(posedge axi.clock) begin
#DELAY;
if (axi.reset) begin
axi.awaddr <= 0;
axi.awvalid <= 0;
axi.wdata <= 0;
axi.wvalid <= 0;
axi.araddr <= 0;
axi.arvalid <= 0;
axi.wlast <= 0;
axi.bready <= 0;
axi.rready <= 0;
wstate <= 0;
rstate <= 0;
last_write_was_succecssful <= 0;
parallel_read_data <= 0;
our_rlast <= 0;
cw_state <= axi::IDLE;
cr_state <= axi::IDLE;
end else begin
case (cw_state)
axi::IDLE: begin
axi.awvalid <= 0;
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 0;
if (parallel_write_address_valid) begin
axi.awaddr <= parallel_write_address;
axi.awvalid <= 1;
axi.wlast <= 1;
if (axi.awready) begin
cw_state <= axi::WAITING_FOR_WREADY;
end else begin
cw_state <= axi::WAITING_FOR_AWREADY;
end
end
end
axi::WAITING_FOR_AWREADY: begin
axi.awvalid <= 1;
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 0;
if (axi.awready) begin
axi.awvalid <= 0;
if (parallel_write_data_valid) begin
axi.wdata <= parallel_write_data;
axi.wvalid <= 1;
axi.wlast <= 1;
end
cw_state <= axi::WAITING_FOR_WREADY;
end
end
axi::WAITING_FOR_WREADY: begin
axi.awvalid <= 0;
if (parallel_write_data_valid) begin
axi.wdata <= parallel_write_data;
axi.wvalid <= 1'b1;
end
axi.wlast <= 1;
axi.bready <= 0;
if (axi.wready) begin
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 1;
cw_state <= axi::WAITING_FOR_BVALID;
end
end
axi::WAITING_FOR_BVALID: begin
axi.awvalid <= 0;
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 1;
if (axi.bvalid) begin
axi.bready <= 0;
cw_state <= axi::IDLE;
end
end
default: begin
error_count <= error_count + 1'b1;
cw_state <= axi::IDLE;
end
endcase
case (cr_state)
axi::IDLE: begin
axi.arvalid <= 0;
axi.rready <= 0;
our_rlast <= 0;
parallel_read_data_valid <= 0;
if (parallel_read_address_valid) begin
axi.araddr <= parallel_read_address;
axi.arvalid <= 1;
cr_state <= axi::WAITING_FOR_ARREADY;
end
end
axi::WAITING_FOR_ARREADY: begin
axi.arvalid <= 1;
axi.rready <= 0;
our_rlast <= 0;
parallel_read_data_valid <= 0;
if (axi.arready) begin
axi.arvalid <= 0;
axi.rready <= 1;
our_rlast <= 1;
cr_state <= axi::WAITING_FOR_RVALID;
end
end
axi::WAITING_FOR_RVALID: begin
axi.arvalid <= 0;
axi.rready <= 1;
our_rlast <= 1;
parallel_read_data_valid <= 0;
if (axi.rvalid) begin
parallel_read_data <= axi.rdata;
parallel_read_data_valid <= 1;
axi.arvalid <= 0;
axi.rready <= 0;
our_rlast <= 0;
cr_state <= axi::IDLE;
end
end
default: begin
error_count <= error_count + 1'b1;
cr_state <= axi::IDLE;
end
endcase
end
end
initial begin
#0;
assert (^axi.awburst!==1'bx && axi.awburst==axi::FIXED || axi.awburst==axi::INCR) else begin
`error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name);
end
assert (^axi.arburst!==1'bx && axi.arburst==axi::FIXED || axi.arburst==axi::INCR) else begin
`error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name);
end
end
wire rbeat = axi.rready & axi.rvalid;
wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;
endmodule | module parallel_peripheral__axi4_controller #(
parameter ADDRESS_WIDTH = 4,
parameter DATA_WIDTH = 32
) (
input [ADDRESS_WIDTH-1:0] parallel_write_address,
input parallel_write_address_valid,
input [DATA_WIDTH-1:0] parallel_write_data,
input parallel_write_data_valid,
input [ADDRESS_WIDTH-1:0] parallel_read_address,
input parallel_read_address_valid,
output reg [DATA_WIDTH-1:0] parallel_read_data = 0,
output reg parallel_read_data_valid = 0,
axi4.controller axi
); |
assign axi.awburst = axi::FIXED;
assign axi.arburst = axi::FIXED;
assign axi.awlen = 0;
assign axi.arlen = 0;
reg [1:0] rstate = 0;
reg [2:0] wstate = 0;
reg last_write_was_succecssful = 0;
reg our_rlast = 0;
axi::state_t cw_state;
axi::state_t cr_state;
reg [31:0] error_count = 0;
localparam DELAY = 0;
always @(posedge axi.clock) begin
#DELAY;
if (axi.reset) begin
axi.awaddr <= 0;
axi.awvalid <= 0;
axi.wdata <= 0;
axi.wvalid <= 0;
axi.araddr <= 0;
axi.arvalid <= 0;
axi.wlast <= 0;
axi.bready <= 0;
axi.rready <= 0;
wstate <= 0;
rstate <= 0;
last_write_was_succecssful <= 0;
parallel_read_data <= 0;
our_rlast <= 0;
cw_state <= axi::IDLE;
cr_state <= axi::IDLE;
end else begin
case (cw_state)
axi::IDLE: begin
axi.awvalid <= 0;
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 0;
if (parallel_write_address_valid) begin
axi.awaddr <= parallel_write_address;
axi.awvalid <= 1;
axi.wlast <= 1;
if (axi.awready) begin
cw_state <= axi::WAITING_FOR_WREADY;
end else begin
cw_state <= axi::WAITING_FOR_AWREADY;
end
end
end
axi::WAITING_FOR_AWREADY: begin
axi.awvalid <= 1;
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 0;
if (axi.awready) begin
axi.awvalid <= 0;
if (parallel_write_data_valid) begin
axi.wdata <= parallel_write_data;
axi.wvalid <= 1;
axi.wlast <= 1;
end
cw_state <= axi::WAITING_FOR_WREADY;
end
end
axi::WAITING_FOR_WREADY: begin
axi.awvalid <= 0;
if (parallel_write_data_valid) begin
axi.wdata <= parallel_write_data;
axi.wvalid <= 1'b1;
end
axi.wlast <= 1;
axi.bready <= 0;
if (axi.wready) begin
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 1;
cw_state <= axi::WAITING_FOR_BVALID;
end
end
axi::WAITING_FOR_BVALID: begin
axi.awvalid <= 0;
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 1;
if (axi.bvalid) begin
axi.bready <= 0;
cw_state <= axi::IDLE;
end
end
default: begin
error_count <= error_count + 1'b1;
cw_state <= axi::IDLE;
end
endcase
case (cr_state)
axi::IDLE: begin
axi.arvalid <= 0;
axi.rready <= 0;
our_rlast <= 0;
parallel_read_data_valid <= 0;
if (parallel_read_address_valid) begin
axi.araddr <= parallel_read_address;
axi.arvalid <= 1;
cr_state <= axi::WAITING_FOR_ARREADY;
end
end
axi::WAITING_FOR_ARREADY: begin
axi.arvalid <= 1;
axi.rready <= 0;
our_rlast <= 0;
parallel_read_data_valid <= 0;
if (axi.arready) begin
axi.arvalid <= 0;
axi.rready <= 1;
our_rlast <= 1;
cr_state <= axi::WAITING_FOR_RVALID;
end
end
axi::WAITING_FOR_RVALID: begin
axi.arvalid <= 0;
axi.rready <= 1;
our_rlast <= 1;
parallel_read_data_valid <= 0;
if (axi.rvalid) begin
parallel_read_data <= axi.rdata;
parallel_read_data_valid <= 1;
axi.arvalid <= 0;
axi.rready <= 0;
our_rlast <= 0;
cr_state <= axi::IDLE;
end
end
default: begin
error_count <= error_count + 1'b1;
cr_state <= axi::IDLE;
end
endcase
end
end
initial begin
#0;
assert (^axi.awburst!==1'bx && axi.awburst==axi::FIXED || axi.awburst==axi::INCR) else begin
`error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name);
end
assert (^axi.arburst!==1'bx && axi.arburst==axi::FIXED || axi.arburst==axi::INCR) else begin
`error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name);
end
end
wire rbeat = axi.rready & axi.rvalid;
wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;
endmodule | 2 |
5,998 | data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv | 115,035,459 | axi4.sv | sv | 942 | 223 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:5: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:6: Cannot find include file: lib/DebugInfoWarningError.sv\n`include "lib/DebugInfoWarningError.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:341: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:344: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:738: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:741: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:905: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:908: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:7: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport DebugInfoWarningError::*;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:99: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:105: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:106: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:107: syntax error, unexpected \'.\', expecting ::\n wire wbeat = axi.wready & axi.wvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:108: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:109: syntax error, unexpected \'.\', expecting ::\n wire bbeat = axi.bready & axi.bvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:112: syntax error, unexpected \'.\', expecting ::\n always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:113: syntax error, unexpected \'.\', expecting ::\n always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:118: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:121: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:128: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:131: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:135: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:142: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:143: Unsupported: Dynamic array new\n data = new[1];\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:148: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:153: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY; $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:157: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:190: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:208: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:347: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:348: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:376: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:386: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:387: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:388: syntax error, unexpected \'.\', expecting ::\n wire wbeat = axi.wready & axi.wvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:389: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:390: syntax error, unexpected \'.\', expecting ::\n wire bbeat = axi.bready & axi.bvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:393: syntax error, unexpected \'.\', expecting ::\n always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:394: syntax error, unexpected \'.\', expecting ::\n always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:399: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:403: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:407: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:410: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_READ_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:418: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:422: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:428: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:436: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:440: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:446: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:449: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:453: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:454: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:455: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:456: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:465: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:466: Unsupported: Dynamic array new\n data = new[2**LEN_WIDTH];\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:490: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:502: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY; $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:506: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:546: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:566: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:744: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:745: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:753: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.peripheral axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:766: syntax error, unexpected IDENTIFIER\n axi4 modified_copy(clock, reset);\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:768: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: Exiting due to 38 error(s), 28 warning(s)\n' | 6,806 | module | module axi4_peripheral_axi4_controller__pollable_memory_axi4_peripheral__tb;
localparam ADDRESS_WIDTH = 4;
localparam DATA_WIDTH = 32;
localparam LEN_WIDTH = 5;
localparam FREQUENCY_OF_CLOCK_HZ = 10000000;
localparam PERIOD_OF_CLOCK_NS = 1000000000.0/FREQUENCY_OF_CLOCK_HZ;
localparam DELAY_BETWEEN_TRANSACTIONS = 4*PERIOD_OF_CLOCK_NS;
localparam DELAY_BETWEEN_WRITE_BEATS = 1*PERIOD_OF_CLOCK_NS;
localparam DELAY_BETWEEN_READ_BEATS = 1*PERIOD_OF_CLOCK_NS;
localparam LONG_DELAY = 8*PERIOD_OF_CLOCK_NS;
wire clock;
clock #(.FREQUENCY_OF_CLOCK_HZ(FREQUENCY_OF_CLOCK_HZ)) clockmod (.clock(clock));
reg reset = 1;
reg [ADDRESS_WIDTH-1:0] pre_axi4_write_address = 0;
reg [ADDRESS_WIDTH-1:0] axi4_write_address = 0;
reg pre_axi4_write_address_valid = 0;
reg axi4_write_address_valid = 0;
reg [DATA_WIDTH-1:0] pre_axi4_write_data = 0;
reg [DATA_WIDTH-1:0] axi4_write_data = 0;
reg [ADDRESS_WIDTH-1:0] pre_axi4_read_address = 0;
reg [ADDRESS_WIDTH-1:0] axi4_read_address = 0;
reg pre_axi4_read_address_valid = 0;
reg axi4_read_address_valid = 0;
wire [DATA_WIDTH-1:0] axi4_read_data;
axi4 axi(clock, reset);
reg [LEN_WIDTH-1:0] pre_axi4_write_burst_length = 1;
reg [LEN_WIDTH-1:0] axi4_write_burst_length = 1;
reg pre_axi4_write_data_valid = 0;
reg axi4_write_data_valid = 0;
reg [LEN_WIDTH-1:0] pre_axi4_read_burst_length = 1;
reg [LEN_WIDTH-1:0] axi4_read_burst_length = 1;
wire axi4_read_data_valid;
axi4_peripheral__axi4_controller #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH), .LEN_WIDTH(LEN_WIDTH)) spac (.*);
pollable_memory__axi4_peripheral #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH), .LEN_WIDTH(LEN_WIDTH)) pmap (.*);
wire awbeat = axi.awready & axi.awvalid;
wire arbeat = axi.arready & axi.arvalid;
wire wbeat = axi.wready & axi.wvalid;
wire rbeat = axi.rready & axi.rvalid;
wire bbeat = axi.bready & axi.bvalid;
always @(posedge awbeat) begin $display("%t, awbeat %08x", $time, axi4_write_address); end
always @(posedge arbeat) begin $display("%t, arbeat %08x", $time, axi4_read_address); end
always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end
always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end
always @(posedge bbeat) begin $display("%t, bbeat", $time); end
task automatic controller_read_transaction(input [ADDRESS_WIDTH-1:0] address, input [LEN_WIDTH:0] len);
reg [ADDRESS_WIDTH:0] i;
begin
#DELAY_BETWEEN_TRANSACTIONS;
pre_axi4_read_burst_length <= len[LEN_WIDTH-1:0];
pre_axi4_read_address <= address;
pre_axi4_read_address_valid <= 1;
#PERIOD_OF_CLOCK_NS;
pre_axi4_read_address_valid <= 0;
for (i=0; i<len; i++) begin
#PERIOD_OF_CLOCK_NS;
if (i==2) begin
#DELAY_BETWEEN_READ_BEATS;
end
end
end
endtask
task automatic controller_write_transaction(input [ADDRESS_WIDTH-1:0] address, input [LEN_WIDTH:0] len, input [DATA_WIDTH-1:0] data []);
reg [ADDRESS_WIDTH:0] i;
begin
#DELAY_BETWEEN_TRANSACTIONS;
pre_axi4_write_burst_length <= len[LEN_WIDTH-1:0];
pre_axi4_write_address <= address;
pre_axi4_write_address_valid <= 1;
#PERIOD_OF_CLOCK_NS;
pre_axi4_write_address_valid <= 0;
for (i=0; i<len; i++) begin
pre_axi4_write_data <= data[i];
pre_axi4_write_data_valid <= 1;
#PERIOD_OF_CLOCK_NS;
end
pre_axi4_write_data_valid <= 0;
end
endtask
task automatic controller_write_transaction_with_handshaking(input [ADDRESS_WIDTH-1:0] address, input [LEN_WIDTH:0] len, input [DATA_WIDTH-1:0] data []);
reg [ADDRESS_WIDTH:0] i;
begin
#DELAY_BETWEEN_TRANSACTIONS;
pre_axi4_write_burst_length <= len[LEN_WIDTH-1:0];
pre_axi4_write_address <= address;
pre_axi4_write_address_valid <= 1;
#PERIOD_OF_CLOCK_NS;
pre_axi4_write_address_valid <= 0;
for (i=0; i<len; i++) begin
pre_axi4_write_data <= data[i];
pre_axi4_write_data_valid <= 1;
#PERIOD_OF_CLOCK_NS;
if (i==2) begin
pre_axi4_write_data_valid <= 0;
#DELAY_BETWEEN_WRITE_BEATS;
end
if (i==7) begin
pre_axi4_write_data_valid <= 0;
#DELAY_BETWEEN_WRITE_BEATS;
#DELAY_BETWEEN_WRITE_BEATS;
#DELAY_BETWEEN_WRITE_BEATS;
#DELAY_BETWEEN_WRITE_BEATS;
end
end
pre_axi4_write_data_valid <= 0;
end
endtask
reg [DATA_WIDTH-1:0] data [];
reg [31:0] i = 0;
initial begin
#DELAY_BETWEEN_TRANSACTIONS; reset <= 0;
data = new[2**LEN_WIDTH];
for (i=0; i<2**LEN_WIDTH; i++) begin
data[i] = i;
end
for (i=0; i<2**LEN_WIDTH; i++) begin
data[i] = i;
end
controller_write_transaction(4'h0, 1, data);
controller_read_transaction(4'h0, 1);
controller_write_transaction(4'h0, 2, data);
controller_read_transaction(4'h0, 2);
controller_write_transaction(4'h0, 4, data);
controller_read_transaction(4'h0, 4);
controller_write_transaction(4'h0, 16, data);
controller_read_transaction(4'h0, 16);
#LONG_DELAY;
for (i=0; i<2**LEN_WIDTH; i++) begin
data[i] = 2**LEN_WIDTH - i;
end
controller_write_transaction_with_handshaking(4'h0, 1, data);
controller_read_transaction(4'h0, 1);
controller_write_transaction_with_handshaking(4'h0, 2, data);
controller_read_transaction(4'h0, 2);
controller_write_transaction_with_handshaking(4'h0, 4, data);
controller_read_transaction(4'h0, 4);
controller_write_transaction_with_handshaking(4'h0, 16, data);
controller_read_transaction(4'h0, 16);
#LONG_DELAY; $finish;
end
localparam DELAY = 0;
always @(posedge clock) begin
#DELAY;
if (reset) begin
axi4_write_address <= 0;
axi4_write_address_valid <= 0;
axi4_write_data <= 0;
axi4_write_burst_length <= 1;
axi4_write_data_valid <= 0;
axi4_read_address <= 0;
axi4_read_address_valid <= 0;
axi4_read_burst_length <= 1;
end else begin
axi4_write_address <= pre_axi4_write_address;
axi4_write_address_valid <= pre_axi4_write_address_valid;
axi4_write_data <= pre_axi4_write_data;
axi4_write_burst_length <= pre_axi4_write_burst_length;
axi4_write_data_valid <= pre_axi4_write_data_valid;
axi4_read_address <= pre_axi4_read_address;
axi4_read_address_valid <= pre_axi4_read_address_valid;
axi4_read_burst_length <= pre_axi4_read_burst_length;
end
end
endmodule | module axi4_peripheral_axi4_controller__pollable_memory_axi4_peripheral__tb; |
localparam ADDRESS_WIDTH = 4;
localparam DATA_WIDTH = 32;
localparam LEN_WIDTH = 5;
localparam FREQUENCY_OF_CLOCK_HZ = 10000000;
localparam PERIOD_OF_CLOCK_NS = 1000000000.0/FREQUENCY_OF_CLOCK_HZ;
localparam DELAY_BETWEEN_TRANSACTIONS = 4*PERIOD_OF_CLOCK_NS;
localparam DELAY_BETWEEN_WRITE_BEATS = 1*PERIOD_OF_CLOCK_NS;
localparam DELAY_BETWEEN_READ_BEATS = 1*PERIOD_OF_CLOCK_NS;
localparam LONG_DELAY = 8*PERIOD_OF_CLOCK_NS;
wire clock;
clock #(.FREQUENCY_OF_CLOCK_HZ(FREQUENCY_OF_CLOCK_HZ)) clockmod (.clock(clock));
reg reset = 1;
reg [ADDRESS_WIDTH-1:0] pre_axi4_write_address = 0;
reg [ADDRESS_WIDTH-1:0] axi4_write_address = 0;
reg pre_axi4_write_address_valid = 0;
reg axi4_write_address_valid = 0;
reg [DATA_WIDTH-1:0] pre_axi4_write_data = 0;
reg [DATA_WIDTH-1:0] axi4_write_data = 0;
reg [ADDRESS_WIDTH-1:0] pre_axi4_read_address = 0;
reg [ADDRESS_WIDTH-1:0] axi4_read_address = 0;
reg pre_axi4_read_address_valid = 0;
reg axi4_read_address_valid = 0;
wire [DATA_WIDTH-1:0] axi4_read_data;
axi4 axi(clock, reset);
reg [LEN_WIDTH-1:0] pre_axi4_write_burst_length = 1;
reg [LEN_WIDTH-1:0] axi4_write_burst_length = 1;
reg pre_axi4_write_data_valid = 0;
reg axi4_write_data_valid = 0;
reg [LEN_WIDTH-1:0] pre_axi4_read_burst_length = 1;
reg [LEN_WIDTH-1:0] axi4_read_burst_length = 1;
wire axi4_read_data_valid;
axi4_peripheral__axi4_controller #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH), .LEN_WIDTH(LEN_WIDTH)) spac (.*);
pollable_memory__axi4_peripheral #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH), .LEN_WIDTH(LEN_WIDTH)) pmap (.*);
wire awbeat = axi.awready & axi.awvalid;
wire arbeat = axi.arready & axi.arvalid;
wire wbeat = axi.wready & axi.wvalid;
wire rbeat = axi.rready & axi.rvalid;
wire bbeat = axi.bready & axi.bvalid;
always @(posedge awbeat) begin $display("%t, awbeat %08x", $time, axi4_write_address); end
always @(posedge arbeat) begin $display("%t, arbeat %08x", $time, axi4_read_address); end
always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end
always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end
always @(posedge bbeat) begin $display("%t, bbeat", $time); end
task automatic controller_read_transaction(input [ADDRESS_WIDTH-1:0] address, input [LEN_WIDTH:0] len);
reg [ADDRESS_WIDTH:0] i;
begin
#DELAY_BETWEEN_TRANSACTIONS;
pre_axi4_read_burst_length <= len[LEN_WIDTH-1:0];
pre_axi4_read_address <= address;
pre_axi4_read_address_valid <= 1;
#PERIOD_OF_CLOCK_NS;
pre_axi4_read_address_valid <= 0;
for (i=0; i<len; i++) begin
#PERIOD_OF_CLOCK_NS;
if (i==2) begin
#DELAY_BETWEEN_READ_BEATS;
end
end
end
endtask
task automatic controller_write_transaction(input [ADDRESS_WIDTH-1:0] address, input [LEN_WIDTH:0] len, input [DATA_WIDTH-1:0] data []);
reg [ADDRESS_WIDTH:0] i;
begin
#DELAY_BETWEEN_TRANSACTIONS;
pre_axi4_write_burst_length <= len[LEN_WIDTH-1:0];
pre_axi4_write_address <= address;
pre_axi4_write_address_valid <= 1;
#PERIOD_OF_CLOCK_NS;
pre_axi4_write_address_valid <= 0;
for (i=0; i<len; i++) begin
pre_axi4_write_data <= data[i];
pre_axi4_write_data_valid <= 1;
#PERIOD_OF_CLOCK_NS;
end
pre_axi4_write_data_valid <= 0;
end
endtask
task automatic controller_write_transaction_with_handshaking(input [ADDRESS_WIDTH-1:0] address, input [LEN_WIDTH:0] len, input [DATA_WIDTH-1:0] data []);
reg [ADDRESS_WIDTH:0] i;
begin
#DELAY_BETWEEN_TRANSACTIONS;
pre_axi4_write_burst_length <= len[LEN_WIDTH-1:0];
pre_axi4_write_address <= address;
pre_axi4_write_address_valid <= 1;
#PERIOD_OF_CLOCK_NS;
pre_axi4_write_address_valid <= 0;
for (i=0; i<len; i++) begin
pre_axi4_write_data <= data[i];
pre_axi4_write_data_valid <= 1;
#PERIOD_OF_CLOCK_NS;
if (i==2) begin
pre_axi4_write_data_valid <= 0;
#DELAY_BETWEEN_WRITE_BEATS;
end
if (i==7) begin
pre_axi4_write_data_valid <= 0;
#DELAY_BETWEEN_WRITE_BEATS;
#DELAY_BETWEEN_WRITE_BEATS;
#DELAY_BETWEEN_WRITE_BEATS;
#DELAY_BETWEEN_WRITE_BEATS;
end
end
pre_axi4_write_data_valid <= 0;
end
endtask
reg [DATA_WIDTH-1:0] data [];
reg [31:0] i = 0;
initial begin
#DELAY_BETWEEN_TRANSACTIONS; reset <= 0;
data = new[2**LEN_WIDTH];
for (i=0; i<2**LEN_WIDTH; i++) begin
data[i] = i;
end
for (i=0; i<2**LEN_WIDTH; i++) begin
data[i] = i;
end
controller_write_transaction(4'h0, 1, data);
controller_read_transaction(4'h0, 1);
controller_write_transaction(4'h0, 2, data);
controller_read_transaction(4'h0, 2);
controller_write_transaction(4'h0, 4, data);
controller_read_transaction(4'h0, 4);
controller_write_transaction(4'h0, 16, data);
controller_read_transaction(4'h0, 16);
#LONG_DELAY;
for (i=0; i<2**LEN_WIDTH; i++) begin
data[i] = 2**LEN_WIDTH - i;
end
controller_write_transaction_with_handshaking(4'h0, 1, data);
controller_read_transaction(4'h0, 1);
controller_write_transaction_with_handshaking(4'h0, 2, data);
controller_read_transaction(4'h0, 2);
controller_write_transaction_with_handshaking(4'h0, 4, data);
controller_read_transaction(4'h0, 4);
controller_write_transaction_with_handshaking(4'h0, 16, data);
controller_read_transaction(4'h0, 16);
#LONG_DELAY; $finish;
end
localparam DELAY = 0;
always @(posedge clock) begin
#DELAY;
if (reset) begin
axi4_write_address <= 0;
axi4_write_address_valid <= 0;
axi4_write_data <= 0;
axi4_write_burst_length <= 1;
axi4_write_data_valid <= 0;
axi4_read_address <= 0;
axi4_read_address_valid <= 0;
axi4_read_burst_length <= 1;
end else begin
axi4_write_address <= pre_axi4_write_address;
axi4_write_address_valid <= pre_axi4_write_address_valid;
axi4_write_data <= pre_axi4_write_data;
axi4_write_burst_length <= pre_axi4_write_burst_length;
axi4_write_data_valid <= pre_axi4_write_data_valid;
axi4_read_address <= pre_axi4_read_address;
axi4_read_address_valid <= pre_axi4_read_address_valid;
axi4_read_burst_length <= pre_axi4_read_burst_length;
end
end
endmodule | 2 |
5,999 | data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv | 115,035,459 | axi4.sv | sv | 942 | 223 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:5: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:6: Cannot find include file: lib/DebugInfoWarningError.sv\n`include "lib/DebugInfoWarningError.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:341: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:344: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:738: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:741: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:905: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:908: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:7: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport DebugInfoWarningError::*;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:99: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:105: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:106: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:107: syntax error, unexpected \'.\', expecting ::\n wire wbeat = axi.wready & axi.wvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:108: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:109: syntax error, unexpected \'.\', expecting ::\n wire bbeat = axi.bready & axi.bvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:112: syntax error, unexpected \'.\', expecting ::\n always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:113: syntax error, unexpected \'.\', expecting ::\n always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:118: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:121: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:128: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:131: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:135: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:142: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:143: Unsupported: Dynamic array new\n data = new[1];\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:148: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:153: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY; $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:157: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:190: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:208: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:347: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:348: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:376: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:386: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:387: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:388: syntax error, unexpected \'.\', expecting ::\n wire wbeat = axi.wready & axi.wvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:389: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:390: syntax error, unexpected \'.\', expecting ::\n wire bbeat = axi.bready & axi.bvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:393: syntax error, unexpected \'.\', expecting ::\n always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:394: syntax error, unexpected \'.\', expecting ::\n always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:399: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:403: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:407: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:410: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_READ_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:418: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:422: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:428: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:436: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:440: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:446: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:449: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:453: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:454: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:455: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:456: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:465: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:466: Unsupported: Dynamic array new\n data = new[2**LEN_WIDTH];\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:490: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:502: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY; $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:506: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:546: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:566: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:744: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:745: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:753: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.peripheral axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:766: syntax error, unexpected IDENTIFIER\n axi4 modified_copy(clock, reset);\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:768: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: Exiting due to 38 error(s), 28 warning(s)\n' | 6,806 | module | module axi4_peripheral__axi4_controller #(
parameter ADDRESS_WIDTH = 4,
parameter DATA_WIDTH = 32,
parameter LEN_WIDTH = 5
) (
input [ADDRESS_WIDTH-1:0] axi4_write_address,
input axi4_write_address_valid,
input [DATA_WIDTH-1:0] axi4_write_data,
input [LEN_WIDTH-1:0] axi4_write_burst_length,
input axi4_write_data_valid,
input [ADDRESS_WIDTH-1:0] axi4_read_address,
input axi4_read_address_valid,
output reg [DATA_WIDTH-1:0] axi4_read_data = 0,
input [LEN_WIDTH-1:0] axi4_read_burst_length,
output reg axi4_read_data_valid = 0,
axi4.controller axi
);
assign axi.awburst = axi::INCR;
assign axi.arburst = axi::INCR;
reg [1:0] rstate = 0;
reg [2:0] wstate = 0;
reg last_write_was_succecssful = 0;
reg [LEN_WIDTH-1:0] write_transaction_counter = 0;
reg [LEN_WIDTH-1:0] read_transaction_counter = 0;
reg our_rlast = 0;
axi::state_t cw_state;
axi::state_t cr_state;
reg [31:0] error_count = 0;
reg [LEN_WIDTH-1:0] internal_copy_of_awlen = 0;
reg [LEN_WIDTH-1:0] internal_copy_of_arlen = 0;
localparam DELAY = 0;
always @(posedge axi.clock) begin
#DELAY;
if (axi.reset) begin
axi.awaddr <= 0;
axi.awvalid <= 0;
axi.wdata <= 0;
axi.wvalid <= 0;
axi.awlen <= 0;
axi.araddr <= 0;
axi.arvalid <= 0;
axi.arlen <= 0;
axi.wlast <= 0;
axi.bready <= 0;
axi.rready <= 0;
wstate <= 0;
rstate <= 0;
last_write_was_succecssful <= 0;
axi4_read_data <= 0;
write_transaction_counter <= 0;
read_transaction_counter <= 0;
our_rlast <= 0;
cw_state <= axi::IDLE;
cr_state <= axi::IDLE;
internal_copy_of_awlen <= 0;
internal_copy_of_arlen <= 0;
end else begin
case (cw_state)
axi::IDLE: begin
axi.awvalid <= 0;
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 0;
if (axi4_write_address_valid) begin
axi.awaddr <= axi4_write_address;
axi.awlen <= axi4_write_burst_length - 1'b1;
internal_copy_of_awlen <= axi4_write_burst_length - 1'b1;
axi.awvalid <= 1;
if (axi4_write_burst_length==1) begin
axi.wlast <= 1;
end else begin
axi.wlast <= 0;
end
if (axi.awready) begin
cw_state <= axi::WAITING_FOR_WREADY;
end else begin
cw_state <= axi::WAITING_FOR_AWREADY;
end
end
end
axi::WAITING_FOR_AWREADY: begin
axi.awvalid <= 1;
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 0;
if (axi.awready) begin
axi.awvalid <= 0;
if (axi4_write_data_valid) begin
axi.wdata <= axi4_write_data;
axi.wvalid <= 1;
if (internal_copy_of_awlen==0) begin
axi.wlast <= 1;
end
end
cw_state <= axi::WAITING_FOR_WREADY;
end
end
axi::WAITING_FOR_WREADY: begin
axi.awvalid <= 0;
axi.wdata <= axi4_write_data;
axi.wvalid <= 1'b1;
if (internal_copy_of_awlen==1) begin
axi.wlast <= 1;
end
axi.bready <= 0;
if (axi.wready) begin
if (internal_copy_of_awlen>0) begin
internal_copy_of_awlen <= internal_copy_of_awlen - 1'b1;
end else begin
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 1;
cw_state <= axi::WAITING_FOR_BVALID;
end
end
end
axi::WAITING_FOR_BVALID: begin
axi.awvalid <= 0;
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 1;
if (axi.bvalid) begin
axi.bready <= 0;
cw_state <= axi::IDLE;
end
end
default: begin
error_count <= error_count + 1'b1;
cw_state <= axi::IDLE;
end
endcase
case (cr_state)
axi::IDLE: begin
axi.arvalid <= 0;
axi.rready <= 0;
our_rlast <= 0;
axi4_read_data_valid <= 0;
if (axi4_read_address_valid) begin
axi.araddr <= axi4_read_address;
axi.arlen <= axi4_read_burst_length - 1'b1;
internal_copy_of_arlen <= axi4_read_burst_length - 1'b1;
axi.arvalid <= 1;
cr_state <= axi::WAITING_FOR_ARREADY;
end
end
axi::WAITING_FOR_ARREADY: begin
axi.arvalid <= 1;
axi.rready <= 0;
our_rlast <= 0;
axi4_read_data_valid <= 0;
if (axi.arready) begin
axi.arvalid <= 0;
axi.rready <= 1;
if (internal_copy_of_arlen==0) begin
our_rlast <= 1;
end
cr_state <= axi::WAITING_FOR_RVALID;
end
end
axi::WAITING_FOR_RVALID: begin
axi.arvalid <= 0;
axi.rready <= 1;
if (internal_copy_of_arlen==0) begin
our_rlast <= 1;
end else begin
our_rlast <= 0;
end
axi4_read_data_valid <= 0;
if (axi.rvalid) begin
axi4_read_data <= axi.rdata;
axi4_read_data_valid <= 1;
if (internal_copy_of_arlen>0) begin
if (internal_copy_of_arlen==1) begin
our_rlast <= 1;
end
internal_copy_of_arlen <= internal_copy_of_arlen - 1'b1;
end else begin
axi.arvalid <= 0;
axi.rready <= 0;
our_rlast <= 0;
cr_state <= axi::IDLE;
end
end
end
default: begin
error_count <= error_count + 1'b1;
cr_state <= axi::IDLE;
end
endcase
end
end
initial begin
#0;
assert (^axi.awburst!==1'bx && axi.awburst==axi::FIXED || axi.awburst==axi::INCR) else begin
`error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name);
end
assert (^axi.arburst!==1'bx && axi.arburst==axi::FIXED || axi.arburst==axi::INCR) else begin
`error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name);
end
end
wire rbeat = axi.rready & axi.rvalid;
wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;
endmodule | module axi4_peripheral__axi4_controller #(
parameter ADDRESS_WIDTH = 4,
parameter DATA_WIDTH = 32,
parameter LEN_WIDTH = 5
) (
input [ADDRESS_WIDTH-1:0] axi4_write_address,
input axi4_write_address_valid,
input [DATA_WIDTH-1:0] axi4_write_data,
input [LEN_WIDTH-1:0] axi4_write_burst_length,
input axi4_write_data_valid,
input [ADDRESS_WIDTH-1:0] axi4_read_address,
input axi4_read_address_valid,
output reg [DATA_WIDTH-1:0] axi4_read_data = 0,
input [LEN_WIDTH-1:0] axi4_read_burst_length,
output reg axi4_read_data_valid = 0,
axi4.controller axi
); |
assign axi.awburst = axi::INCR;
assign axi.arburst = axi::INCR;
reg [1:0] rstate = 0;
reg [2:0] wstate = 0;
reg last_write_was_succecssful = 0;
reg [LEN_WIDTH-1:0] write_transaction_counter = 0;
reg [LEN_WIDTH-1:0] read_transaction_counter = 0;
reg our_rlast = 0;
axi::state_t cw_state;
axi::state_t cr_state;
reg [31:0] error_count = 0;
reg [LEN_WIDTH-1:0] internal_copy_of_awlen = 0;
reg [LEN_WIDTH-1:0] internal_copy_of_arlen = 0;
localparam DELAY = 0;
always @(posedge axi.clock) begin
#DELAY;
if (axi.reset) begin
axi.awaddr <= 0;
axi.awvalid <= 0;
axi.wdata <= 0;
axi.wvalid <= 0;
axi.awlen <= 0;
axi.araddr <= 0;
axi.arvalid <= 0;
axi.arlen <= 0;
axi.wlast <= 0;
axi.bready <= 0;
axi.rready <= 0;
wstate <= 0;
rstate <= 0;
last_write_was_succecssful <= 0;
axi4_read_data <= 0;
write_transaction_counter <= 0;
read_transaction_counter <= 0;
our_rlast <= 0;
cw_state <= axi::IDLE;
cr_state <= axi::IDLE;
internal_copy_of_awlen <= 0;
internal_copy_of_arlen <= 0;
end else begin
case (cw_state)
axi::IDLE: begin
axi.awvalid <= 0;
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 0;
if (axi4_write_address_valid) begin
axi.awaddr <= axi4_write_address;
axi.awlen <= axi4_write_burst_length - 1'b1;
internal_copy_of_awlen <= axi4_write_burst_length - 1'b1;
axi.awvalid <= 1;
if (axi4_write_burst_length==1) begin
axi.wlast <= 1;
end else begin
axi.wlast <= 0;
end
if (axi.awready) begin
cw_state <= axi::WAITING_FOR_WREADY;
end else begin
cw_state <= axi::WAITING_FOR_AWREADY;
end
end
end
axi::WAITING_FOR_AWREADY: begin
axi.awvalid <= 1;
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 0;
if (axi.awready) begin
axi.awvalid <= 0;
if (axi4_write_data_valid) begin
axi.wdata <= axi4_write_data;
axi.wvalid <= 1;
if (internal_copy_of_awlen==0) begin
axi.wlast <= 1;
end
end
cw_state <= axi::WAITING_FOR_WREADY;
end
end
axi::WAITING_FOR_WREADY: begin
axi.awvalid <= 0;
axi.wdata <= axi4_write_data;
axi.wvalid <= 1'b1;
if (internal_copy_of_awlen==1) begin
axi.wlast <= 1;
end
axi.bready <= 0;
if (axi.wready) begin
if (internal_copy_of_awlen>0) begin
internal_copy_of_awlen <= internal_copy_of_awlen - 1'b1;
end else begin
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 1;
cw_state <= axi::WAITING_FOR_BVALID;
end
end
end
axi::WAITING_FOR_BVALID: begin
axi.awvalid <= 0;
axi.wvalid <= 0;
axi.wlast <= 0;
axi.bready <= 1;
if (axi.bvalid) begin
axi.bready <= 0;
cw_state <= axi::IDLE;
end
end
default: begin
error_count <= error_count + 1'b1;
cw_state <= axi::IDLE;
end
endcase
case (cr_state)
axi::IDLE: begin
axi.arvalid <= 0;
axi.rready <= 0;
our_rlast <= 0;
axi4_read_data_valid <= 0;
if (axi4_read_address_valid) begin
axi.araddr <= axi4_read_address;
axi.arlen <= axi4_read_burst_length - 1'b1;
internal_copy_of_arlen <= axi4_read_burst_length - 1'b1;
axi.arvalid <= 1;
cr_state <= axi::WAITING_FOR_ARREADY;
end
end
axi::WAITING_FOR_ARREADY: begin
axi.arvalid <= 1;
axi.rready <= 0;
our_rlast <= 0;
axi4_read_data_valid <= 0;
if (axi.arready) begin
axi.arvalid <= 0;
axi.rready <= 1;
if (internal_copy_of_arlen==0) begin
our_rlast <= 1;
end
cr_state <= axi::WAITING_FOR_RVALID;
end
end
axi::WAITING_FOR_RVALID: begin
axi.arvalid <= 0;
axi.rready <= 1;
if (internal_copy_of_arlen==0) begin
our_rlast <= 1;
end else begin
our_rlast <= 0;
end
axi4_read_data_valid <= 0;
if (axi.rvalid) begin
axi4_read_data <= axi.rdata;
axi4_read_data_valid <= 1;
if (internal_copy_of_arlen>0) begin
if (internal_copy_of_arlen==1) begin
our_rlast <= 1;
end
internal_copy_of_arlen <= internal_copy_of_arlen - 1'b1;
end else begin
axi.arvalid <= 0;
axi.rready <= 0;
our_rlast <= 0;
cr_state <= axi::IDLE;
end
end
end
default: begin
error_count <= error_count + 1'b1;
cr_state <= axi::IDLE;
end
endcase
end
end
initial begin
#0;
assert (^axi.awburst!==1'bx && axi.awburst==axi::FIXED || axi.awburst==axi::INCR) else begin
`error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name);
end
assert (^axi.arburst!==1'bx && axi.arburst==axi::FIXED || axi.arburst==axi::INCR) else begin
`error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name);
end
end
wire rbeat = axi.rready & axi.rvalid;
wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;
endmodule | 2 |
6,000 | data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv | 115,035,459 | axi4.sv | sv | 942 | 223 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:5: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:6: Cannot find include file: lib/DebugInfoWarningError.sv\n`include "lib/DebugInfoWarningError.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:341: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:344: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:738: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:741: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:905: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:908: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:7: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport DebugInfoWarningError::*;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:99: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:105: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:106: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:107: syntax error, unexpected \'.\', expecting ::\n wire wbeat = axi.wready & axi.wvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:108: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:109: syntax error, unexpected \'.\', expecting ::\n wire bbeat = axi.bready & axi.bvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:112: syntax error, unexpected \'.\', expecting ::\n always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:113: syntax error, unexpected \'.\', expecting ::\n always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:118: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:121: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:128: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:131: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:135: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:142: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:143: Unsupported: Dynamic array new\n data = new[1];\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:148: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:153: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY; $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:157: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:190: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:208: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:347: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:348: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:376: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:386: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:387: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:388: syntax error, unexpected \'.\', expecting ::\n wire wbeat = axi.wready & axi.wvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:389: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:390: syntax error, unexpected \'.\', expecting ::\n wire bbeat = axi.bready & axi.bvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:393: syntax error, unexpected \'.\', expecting ::\n always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:394: syntax error, unexpected \'.\', expecting ::\n always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:399: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:403: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:407: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:410: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_READ_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:418: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:422: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:428: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:436: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:440: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:446: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:449: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:453: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:454: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:455: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:456: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:465: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:466: Unsupported: Dynamic array new\n data = new[2**LEN_WIDTH];\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:490: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:502: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY; $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:506: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:546: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:566: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:744: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:745: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:753: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.peripheral axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:766: syntax error, unexpected IDENTIFIER\n axi4 modified_copy(clock, reset);\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:768: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: Exiting due to 38 error(s), 28 warning(s)\n' | 6,806 | module | module pollable_memory__axi4_peripheral #(
parameter ADDRESS_WIDTH = 4,
parameter DATA_WIDTH = 32,
parameter LEN_WIDTH = 5
) (
axi4.peripheral axi
);
reg [3:0] wstate = 0;
reg [ADDRESS_WIDTH-1:0] local_awaddr = 0;
reg [DATA_WIDTH-1:0] local_wdata = 0;
reg [1:0] rstate = 0;
logic [DATA_WIDTH-1:0] mem [2**ADDRESS_WIDTH-1:0];
reg [LEN_WIDTH-1:0] write_transaction_counter = 0;
reg [LEN_WIDTH-1:0] read_transaction_counter = 0;
reg [31:0] error_count = 0;
axi::state_t pw_state;
axi::state_t pr_state;
axi4 modified_copy(clock, reset);
localparam DELAY = 0;
always @(posedge axi.clock) begin
#DELAY;
if (axi.reset) begin
axi.arready <= 1;
axi.rdata <= 0;
axi.rvalid <= 0;
axi.rlast <= 0;
local_awaddr <= 0;
local_wdata <= 0;
write_transaction_counter <= 0;
read_transaction_counter <= 0;
wstate <= 0;
rstate <= 0;
pw_state <= axi::WAITING_FOR_AWVALID;
pr_state <= axi::WAITING_FOR_ARVALID;
modified_copy.awaddr <= 0;
modified_copy.awlen <= 0;
modified_copy.wdata <= 0;
axi.awready <= 1;
axi.wready <= 0;
axi.bresp <= 0;
axi.bvalid <= 0;
modified_copy.araddr <= 0;
modified_copy.arlen <= 0;
modified_copy.arburst <= 0;
end else begin
case (pw_state)
axi::WAITING_FOR_AWVALID: begin
axi.awready <= 1;
axi.wready <= 0;
axi.bresp <= 0;
axi.bvalid <= 0;
if (axi.awvalid) begin
modified_copy.awaddr <= axi.awaddr;
modified_copy.awlen <= axi.awlen;
modified_copy.awburst <= axi.awburst;
axi.awready <= 0;
axi.wready <= 1;
pw_state <= axi::WAITING_FOR_WVALID;
end
end
axi::WAITING_FOR_WVALID: begin
axi.awready <= 0;
axi.wready <= 1;
axi.bresp <= 0;
axi.bvalid <= 0;
if (axi.wvalid) begin
axi.awready <= 0;
axi.wready <= 1;
mem[modified_copy.awaddr] <= axi.wdata;
modified_copy.wdata <= axi.wdata;
if (modified_copy.awlen>0) begin
modified_copy.awlen <= modified_copy.awlen - 1'b1;
if (modified_copy.awburst==axi::INCR) begin
modified_copy.awaddr <= modified_copy.awaddr + 1'b1;
end
end else begin
axi.wready <= 0;
axi.bresp <= 1;
axi.bvalid <= 1;
pw_state <= axi::WAITING_FOR_BREADY;
end
end
end
axi::WAITING_FOR_BREADY: begin
axi.awready <= 0;
axi.wready <= 0;
axi.bresp <= 1;
axi.bvalid <= 1;
if (axi.bready) begin
axi.awready <= 1;
axi.bresp <= 0;
axi.bvalid <= 0;
pw_state <= axi::WAITING_FOR_AWVALID;
end
end
default: begin
error_count <= error_count + 1'b1;
pw_state <= axi::WAITING_FOR_AWVALID;
end
endcase
case (pr_state)
axi::WAITING_FOR_ARVALID: begin
axi.arready <= 1;
axi.rvalid <= 0;
axi.rlast <= 0;
if (axi.arvalid) begin
modified_copy.araddr <= axi.araddr + 1'b1;
modified_copy.arlen <= axi.arlen;
modified_copy.arburst <= axi.arburst;
axi.arready <= 0;
axi.rdata <= mem[axi.araddr];
axi.rvalid <= 1;
if (axi.arlen==0) begin
axi.rlast <= 1;
end
pr_state <= axi::WAITING_FOR_RREADY;
end
end
axi::WAITING_FOR_RREADY: begin
axi.arready <= 0;
axi.rdata <= mem[modified_copy.araddr];
axi.rvalid <= 1;
axi.rlast <= 0;
if (modified_copy.arlen==1) begin
axi.rlast <= 1;
end else begin
axi.rlast <= 0;
end
if (axi.rready) begin
if (modified_copy.arlen>0) begin
modified_copy.arlen <= modified_copy.arlen - 1'b1;
if (modified_copy.arburst==axi::INCR) begin
modified_copy.araddr <= modified_copy.araddr + 1'b1;
end
end else begin
axi.arready <= 1;
axi.rvalid <= 0;
axi.rlast <= 0;
pr_state <= axi::WAITING_FOR_ARVALID;
end
end
end
default: begin
error_count <= error_count + 1'b1;
pr_state <= axi::WAITING_FOR_ARVALID;
end
endcase
end
end
initial begin
#0;
assert (^axi.awburst!==1'bx && axi.awburst==axi::FIXED || axi.awburst==axi::INCR) else begin
`error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name);
end
assert (^axi.arburst!==1'bx && axi.arburst==axi::FIXED || axi.arburst==axi::INCR) else begin
`error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name);
end
end
endmodule | module pollable_memory__axi4_peripheral #(
parameter ADDRESS_WIDTH = 4,
parameter DATA_WIDTH = 32,
parameter LEN_WIDTH = 5
) (
axi4.peripheral axi
); |
reg [3:0] wstate = 0;
reg [ADDRESS_WIDTH-1:0] local_awaddr = 0;
reg [DATA_WIDTH-1:0] local_wdata = 0;
reg [1:0] rstate = 0;
logic [DATA_WIDTH-1:0] mem [2**ADDRESS_WIDTH-1:0];
reg [LEN_WIDTH-1:0] write_transaction_counter = 0;
reg [LEN_WIDTH-1:0] read_transaction_counter = 0;
reg [31:0] error_count = 0;
axi::state_t pw_state;
axi::state_t pr_state;
axi4 modified_copy(clock, reset);
localparam DELAY = 0;
always @(posedge axi.clock) begin
#DELAY;
if (axi.reset) begin
axi.arready <= 1;
axi.rdata <= 0;
axi.rvalid <= 0;
axi.rlast <= 0;
local_awaddr <= 0;
local_wdata <= 0;
write_transaction_counter <= 0;
read_transaction_counter <= 0;
wstate <= 0;
rstate <= 0;
pw_state <= axi::WAITING_FOR_AWVALID;
pr_state <= axi::WAITING_FOR_ARVALID;
modified_copy.awaddr <= 0;
modified_copy.awlen <= 0;
modified_copy.wdata <= 0;
axi.awready <= 1;
axi.wready <= 0;
axi.bresp <= 0;
axi.bvalid <= 0;
modified_copy.araddr <= 0;
modified_copy.arlen <= 0;
modified_copy.arburst <= 0;
end else begin
case (pw_state)
axi::WAITING_FOR_AWVALID: begin
axi.awready <= 1;
axi.wready <= 0;
axi.bresp <= 0;
axi.bvalid <= 0;
if (axi.awvalid) begin
modified_copy.awaddr <= axi.awaddr;
modified_copy.awlen <= axi.awlen;
modified_copy.awburst <= axi.awburst;
axi.awready <= 0;
axi.wready <= 1;
pw_state <= axi::WAITING_FOR_WVALID;
end
end
axi::WAITING_FOR_WVALID: begin
axi.awready <= 0;
axi.wready <= 1;
axi.bresp <= 0;
axi.bvalid <= 0;
if (axi.wvalid) begin
axi.awready <= 0;
axi.wready <= 1;
mem[modified_copy.awaddr] <= axi.wdata;
modified_copy.wdata <= axi.wdata;
if (modified_copy.awlen>0) begin
modified_copy.awlen <= modified_copy.awlen - 1'b1;
if (modified_copy.awburst==axi::INCR) begin
modified_copy.awaddr <= modified_copy.awaddr + 1'b1;
end
end else begin
axi.wready <= 0;
axi.bresp <= 1;
axi.bvalid <= 1;
pw_state <= axi::WAITING_FOR_BREADY;
end
end
end
axi::WAITING_FOR_BREADY: begin
axi.awready <= 0;
axi.wready <= 0;
axi.bresp <= 1;
axi.bvalid <= 1;
if (axi.bready) begin
axi.awready <= 1;
axi.bresp <= 0;
axi.bvalid <= 0;
pw_state <= axi::WAITING_FOR_AWVALID;
end
end
default: begin
error_count <= error_count + 1'b1;
pw_state <= axi::WAITING_FOR_AWVALID;
end
endcase
case (pr_state)
axi::WAITING_FOR_ARVALID: begin
axi.arready <= 1;
axi.rvalid <= 0;
axi.rlast <= 0;
if (axi.arvalid) begin
modified_copy.araddr <= axi.araddr + 1'b1;
modified_copy.arlen <= axi.arlen;
modified_copy.arburst <= axi.arburst;
axi.arready <= 0;
axi.rdata <= mem[axi.araddr];
axi.rvalid <= 1;
if (axi.arlen==0) begin
axi.rlast <= 1;
end
pr_state <= axi::WAITING_FOR_RREADY;
end
end
axi::WAITING_FOR_RREADY: begin
axi.arready <= 0;
axi.rdata <= mem[modified_copy.araddr];
axi.rvalid <= 1;
axi.rlast <= 0;
if (modified_copy.arlen==1) begin
axi.rlast <= 1;
end else begin
axi.rlast <= 0;
end
if (axi.rready) begin
if (modified_copy.arlen>0) begin
modified_copy.arlen <= modified_copy.arlen - 1'b1;
if (modified_copy.arburst==axi::INCR) begin
modified_copy.araddr <= modified_copy.araddr + 1'b1;
end
end else begin
axi.arready <= 1;
axi.rvalid <= 0;
axi.rlast <= 0;
pr_state <= axi::WAITING_FOR_ARVALID;
end
end
end
default: begin
error_count <= error_count + 1'b1;
pr_state <= axi::WAITING_FOR_ARVALID;
end
endcase
end
end
initial begin
#0;
assert (^axi.awburst!==1'bx && axi.awburst==axi::FIXED || axi.awburst==axi::INCR) else begin
`error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name);
end
assert (^axi.arburst!==1'bx && axi.arburst==axi::FIXED || axi.arburst==axi::INCR) else begin
`error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name);
end
end
endmodule | 2 |
6,001 | data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv | 115,035,459 | axi4.sv | sv | 942 | 223 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:5: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.v\n data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.sv\n lib/generic.v\n lib/generic.v.v\n lib/generic.v.sv\n obj_dir/lib/generic.v\n obj_dir/lib/generic.v.v\n obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:6: Cannot find include file: lib/DebugInfoWarningError.sv\n`include "lib/DebugInfoWarningError.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:341: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:344: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:738: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:741: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:905: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:908: Expecting `error string. Found: TEXT\n `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:7: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport DebugInfoWarningError::*;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:99: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:105: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:106: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:107: syntax error, unexpected \'.\', expecting ::\n wire wbeat = axi.wready & axi.wvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:108: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:109: syntax error, unexpected \'.\', expecting ::\n wire bbeat = axi.bready & axi.bvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:112: syntax error, unexpected \'.\', expecting ::\n always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:113: syntax error, unexpected \'.\', expecting ::\n always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:118: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:121: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:128: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:131: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:135: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:142: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:143: Unsupported: Dynamic array new\n data = new[1];\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:148: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:153: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY; $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:157: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:190: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:208: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:347: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:348: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:376: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:386: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:387: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:388: syntax error, unexpected \'.\', expecting ::\n wire wbeat = axi.wready & axi.wvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:389: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:390: syntax error, unexpected \'.\', expecting ::\n wire bbeat = axi.bready & axi.bvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:393: syntax error, unexpected \'.\', expecting ::\n always @(posedge wbeat) begin $display("%t, wbeat %08x", $time, axi.wdata); end\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:394: syntax error, unexpected \'.\', expecting ::\n always @(posedge rbeat) begin $display("%t, rbeat %08x", $time, axi.rdata); end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:399: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:403: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:407: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:410: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_READ_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:418: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:422: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:428: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:436: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:440: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:446: Unsupported: Ignoring delay on this delayed statement.\n #PERIOD_OF_CLOCK_NS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:449: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:453: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:454: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:455: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:456: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_WRITE_BEATS;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:465: Unsupported: Ignoring delay on this delayed statement.\n #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:466: Unsupported: Dynamic array new\n data = new[2**LEN_WIDTH];\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:490: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:502: Unsupported: Ignoring delay on this delayed statement.\n #LONG_DELAY; $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:506: Unsupported: Ignoring delay on this delayed statement.\n #DELAY;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:546: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:566: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:744: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:745: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:753: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.peripheral axi\n ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:766: syntax error, unexpected IDENTIFIER\n axi4 modified_copy(clock, reset);\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:768: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: Exiting due to 38 error(s), 28 warning(s)\n' | 6,806 | module | module axi4_handshake (
input clock,
input reset,
input ready,
input valid_in,
output reg valid_out = 0
);
reg state = 0;
always @(posedge clock) begin
if (reset) begin
valid_out <= 0;
state <= 0;
end else begin
if (state==0) begin
if (valid_in) begin
valid_out <= 1;
state <= 1;
end
end else begin
if (ready) begin
valid_out <= 0;
state <= 0;
end
end
end
end
endmodule | module axi4_handshake (
input clock,
input reset,
input ready,
input valid_in,
output reg valid_out = 0
); |
reg state = 0;
always @(posedge clock) begin
if (reset) begin
valid_out <= 0;
state <= 0;
end else begin
if (state==0) begin
if (valid_in) begin
valid_out <= 1;
state <= 1;
end
end else begin
if (ready) begin
valid_out <= 0;
state <= 0;
end
end
end
end
endmodule | 2 |
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