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//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v2_3_poc_top.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 15 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: Phaser out calibration top. //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_poc_top # (parameter MMCM_SAMP_WAIT = 10, parameter PCT_SAMPS_SOLID = 95, parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter TCQ = 100, parameter CCENABLE = 0, parameter SCANFROMRIGHT = 0, parameter SAMPCNTRWIDTH = 8, parameter SAMPLES = 128, parameter TAPCNTRWIDTH = 7, parameter TAPSPERKCLK =112) (/*AUTOARG*/ // Outputs psincdec, poc_error, poc_backup, psen, rise_lead_right, rise_trail_right, mmcm_edge_detect_done, mmcm_lbclk_edge_aligned, // Inputs use_noise_window, rst, psdone, poc_sample_pd, pd_out, ninety_offsets, mmcm_edge_detect_rdy, ktap_at_right_edge, ktap_at_left_edge, clk ); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input clk; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v, ... input ktap_at_left_edge; // To u_poc_meta of mig_7series_v2_3_poc_meta.v, ... input ktap_at_right_edge; // To u_poc_meta of mig_7series_v2_3_poc_meta.v, ... input mmcm_edge_detect_rdy; // To u_poc_meta of mig_7series_v2_3_poc_meta.v input [1:0] ninety_offsets; // To u_poc_meta of mig_7series_v2_3_poc_meta.v input pd_out; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v input poc_sample_pd; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v input psdone; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v input rst; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v, ... input use_noise_window; // To u_poc_meta of mig_7series_v2_3_poc_meta.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output poc_backup; // From u_poc_meta of mig_7series_v2_3_poc_meta.v output poc_error; // From u_poc_cc of mig_7series_v2_3_poc_cc.v output psincdec; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v // End of automatics /*AUTOwire*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [TAPCNTRWIDTH-1:0] fall_lead_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_lead_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_lead_right; // From u_edge_right of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_right; // From u_edge_right of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_lead_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_lead_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_trail_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_trail_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] run; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire run_end; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire run_polarity; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire [SAMPCNTRWIDTH:0] samples; // From u_poc_cc of mig_7series_v2_3_poc_cc.v wire [SAMPCNTRWIDTH:0] samps_hi_held; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire [SAMPCNTRWIDTH:0] samps_solid_thresh; // From u_poc_cc of mig_7series_v2_3_poc_cc.v wire [TAPCNTRWIDTH-1:0] tap; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v // End of automatics output psen; output [TAPCNTRWIDTH-1:0] rise_lead_right; output [TAPCNTRWIDTH-1:0] rise_trail_right; output mmcm_edge_detect_done; output mmcm_lbclk_edge_aligned; mig_7series_v2_3_poc_tap_base # (/*AUTOINSTPARAM*/ // Parameters .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_poc_tap_base (/*AUTOINST*/ // Outputs .psen (psen), .psincdec (psincdec), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]), .tap (tap[TAPCNTRWIDTH-1:0]), // Inputs .clk (clk), .pd_out (pd_out), .poc_sample_pd (poc_sample_pd), .psdone (psdone), .rst (rst), .samples (samples[SAMPCNTRWIDTH:0]), .samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0])); mig_7series_v2_3_poc_meta # (/*AUTOINSTPARAM*/ // Parameters .SCANFROMRIGHT (SCANFROMRIGHT), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_poc_meta (/*AUTOINST*/ // Outputs .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .poc_backup (poc_backup), // Inputs .clk (clk), .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), .ninety_offsets (ninety_offsets[1:0]), .rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]), .rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]), .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), .rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]), .rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]), .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), .rst (rst), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .use_noise_window (use_noise_window)); /*mig_7series_v2_3_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" ( .\(.*\)lead (\1lead_@@"vl-bits"), .\(.*\)trail (\1trail_@@"vl-bits"), .select0 (ktap_at_@_edge), .select1 (1'b1),)*/ mig_7series_v2_3_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_right (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_right[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_right[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_right[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_right[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (ktap_at_right_edge), // Templated .select1 (1'b1), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); mig_7series_v2_3_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_left (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_left[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_left[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_left[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_left[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (ktap_at_left_edge), // Templated .select1 (1'b1), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); wire not_ktap_at_right_edge = ~ktap_at_right_edge; wire not_ktap_at_left_edge = ~ktap_at_left_edge; /*mig_7series_v2_3_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" ( .\(.*\)lead (\1lead_@@"vl-bits"), .\(.*\)trail (\1trail_@@"vl-bits"), .select0 (not_ktap_at_right_edge), .select1 (not_ktap_at_left_edge),)*/ mig_7series_v2_3_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_center (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_center[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_center[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_center[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_center[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (not_ktap_at_right_edge), // Templated .select1 (not_ktap_at_left_edge), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); mig_7series_v2_3_poc_cc # (/*AUTOINSTPARAM*/ // Parameters .CCENABLE (CCENABLE), .PCT_SAMPS_SOLID (PCT_SAMPS_SOLID), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .SAMPLES (SAMPLES), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TCQ (TCQ)) u_poc_cc (/*AUTOINST*/ // Outputs .poc_error (poc_error), .samples (samples[SAMPCNTRWIDTH:0]), .samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0]), // Inputs .clk (clk), .fall_lead_center (fall_lead_center[TAPCNTRWIDTH-1:0]), .fall_lead_left (fall_lead_left[TAPCNTRWIDTH-1:0]), .fall_lead_right (fall_lead_right[TAPCNTRWIDTH-1:0]), .fall_trail_center (fall_trail_center[TAPCNTRWIDTH-1:0]), .fall_trail_left (fall_trail_left[TAPCNTRWIDTH-1:0]), .fall_trail_right (fall_trail_right[TAPCNTRWIDTH-1:0]), .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .psen (psen), .rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]), .rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]), .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), .rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]), .rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]), .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), .rst (rst), .samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]), .tap (tap[TAPCNTRWIDTH-1:0])); endmodule // mig_7series_v2_3_poc_top // Local Variables: // verilog-library-directories:(".") // verilog-library-extensions:(".v") // End:
//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v2_3_poc_top.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 15 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: Phaser out calibration top. //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_poc_top # (parameter MMCM_SAMP_WAIT = 10, parameter PCT_SAMPS_SOLID = 95, parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter TCQ = 100, parameter CCENABLE = 0, parameter SCANFROMRIGHT = 0, parameter SAMPCNTRWIDTH = 8, parameter SAMPLES = 128, parameter TAPCNTRWIDTH = 7, parameter TAPSPERKCLK =112) (/*AUTOARG*/ // Outputs psincdec, poc_error, poc_backup, psen, rise_lead_right, rise_trail_right, mmcm_edge_detect_done, mmcm_lbclk_edge_aligned, // Inputs use_noise_window, rst, psdone, poc_sample_pd, pd_out, ninety_offsets, mmcm_edge_detect_rdy, ktap_at_right_edge, ktap_at_left_edge, clk ); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input clk; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v, ... input ktap_at_left_edge; // To u_poc_meta of mig_7series_v2_3_poc_meta.v, ... input ktap_at_right_edge; // To u_poc_meta of mig_7series_v2_3_poc_meta.v, ... input mmcm_edge_detect_rdy; // To u_poc_meta of mig_7series_v2_3_poc_meta.v input [1:0] ninety_offsets; // To u_poc_meta of mig_7series_v2_3_poc_meta.v input pd_out; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v input poc_sample_pd; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v input psdone; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v input rst; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v, ... input use_noise_window; // To u_poc_meta of mig_7series_v2_3_poc_meta.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output poc_backup; // From u_poc_meta of mig_7series_v2_3_poc_meta.v output poc_error; // From u_poc_cc of mig_7series_v2_3_poc_cc.v output psincdec; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v // End of automatics /*AUTOwire*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [TAPCNTRWIDTH-1:0] fall_lead_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_lead_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_lead_right; // From u_edge_right of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_right; // From u_edge_right of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_lead_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_lead_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_trail_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_trail_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] run; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire run_end; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire run_polarity; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire [SAMPCNTRWIDTH:0] samples; // From u_poc_cc of mig_7series_v2_3_poc_cc.v wire [SAMPCNTRWIDTH:0] samps_hi_held; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire [SAMPCNTRWIDTH:0] samps_solid_thresh; // From u_poc_cc of mig_7series_v2_3_poc_cc.v wire [TAPCNTRWIDTH-1:0] tap; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v // End of automatics output psen; output [TAPCNTRWIDTH-1:0] rise_lead_right; output [TAPCNTRWIDTH-1:0] rise_trail_right; output mmcm_edge_detect_done; output mmcm_lbclk_edge_aligned; mig_7series_v2_3_poc_tap_base # (/*AUTOINSTPARAM*/ // Parameters .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_poc_tap_base (/*AUTOINST*/ // Outputs .psen (psen), .psincdec (psincdec), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]), .tap (tap[TAPCNTRWIDTH-1:0]), // Inputs .clk (clk), .pd_out (pd_out), .poc_sample_pd (poc_sample_pd), .psdone (psdone), .rst (rst), .samples (samples[SAMPCNTRWIDTH:0]), .samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0])); mig_7series_v2_3_poc_meta # (/*AUTOINSTPARAM*/ // Parameters .SCANFROMRIGHT (SCANFROMRIGHT), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_poc_meta (/*AUTOINST*/ // Outputs .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .poc_backup (poc_backup), // Inputs .clk (clk), .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), .ninety_offsets (ninety_offsets[1:0]), .rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]), .rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]), .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), .rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]), .rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]), .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), .rst (rst), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .use_noise_window (use_noise_window)); /*mig_7series_v2_3_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" ( .\(.*\)lead (\1lead_@@"vl-bits"), .\(.*\)trail (\1trail_@@"vl-bits"), .select0 (ktap_at_@_edge), .select1 (1'b1),)*/ mig_7series_v2_3_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_right (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_right[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_right[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_right[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_right[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (ktap_at_right_edge), // Templated .select1 (1'b1), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); mig_7series_v2_3_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_left (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_left[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_left[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_left[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_left[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (ktap_at_left_edge), // Templated .select1 (1'b1), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); wire not_ktap_at_right_edge = ~ktap_at_right_edge; wire not_ktap_at_left_edge = ~ktap_at_left_edge; /*mig_7series_v2_3_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" ( .\(.*\)lead (\1lead_@@"vl-bits"), .\(.*\)trail (\1trail_@@"vl-bits"), .select0 (not_ktap_at_right_edge), .select1 (not_ktap_at_left_edge),)*/ mig_7series_v2_3_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_center (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_center[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_center[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_center[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_center[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (not_ktap_at_right_edge), // Templated .select1 (not_ktap_at_left_edge), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); mig_7series_v2_3_poc_cc # (/*AUTOINSTPARAM*/ // Parameters .CCENABLE (CCENABLE), .PCT_SAMPS_SOLID (PCT_SAMPS_SOLID), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .SAMPLES (SAMPLES), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TCQ (TCQ)) u_poc_cc (/*AUTOINST*/ // Outputs .poc_error (poc_error), .samples (samples[SAMPCNTRWIDTH:0]), .samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0]), // Inputs .clk (clk), .fall_lead_center (fall_lead_center[TAPCNTRWIDTH-1:0]), .fall_lead_left (fall_lead_left[TAPCNTRWIDTH-1:0]), .fall_lead_right (fall_lead_right[TAPCNTRWIDTH-1:0]), .fall_trail_center (fall_trail_center[TAPCNTRWIDTH-1:0]), .fall_trail_left (fall_trail_left[TAPCNTRWIDTH-1:0]), .fall_trail_right (fall_trail_right[TAPCNTRWIDTH-1:0]), .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .psen (psen), .rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]), .rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]), .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), .rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]), .rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]), .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), .rst (rst), .samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]), .tap (tap[TAPCNTRWIDTH-1:0])); endmodule // mig_7series_v2_3_poc_top // Local Variables: // verilog-library-directories:(".") // verilog-library-extensions:(".v") // End:
//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v2_3_poc_top.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 15 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: Phaser out calibration top. //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_poc_top # (parameter MMCM_SAMP_WAIT = 10, parameter PCT_SAMPS_SOLID = 95, parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter TCQ = 100, parameter CCENABLE = 0, parameter SCANFROMRIGHT = 0, parameter SAMPCNTRWIDTH = 8, parameter SAMPLES = 128, parameter TAPCNTRWIDTH = 7, parameter TAPSPERKCLK =112) (/*AUTOARG*/ // Outputs psincdec, poc_error, poc_backup, psen, rise_lead_right, rise_trail_right, mmcm_edge_detect_done, mmcm_lbclk_edge_aligned, // Inputs use_noise_window, rst, psdone, poc_sample_pd, pd_out, ninety_offsets, mmcm_edge_detect_rdy, ktap_at_right_edge, ktap_at_left_edge, clk ); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input clk; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v, ... input ktap_at_left_edge; // To u_poc_meta of mig_7series_v2_3_poc_meta.v, ... input ktap_at_right_edge; // To u_poc_meta of mig_7series_v2_3_poc_meta.v, ... input mmcm_edge_detect_rdy; // To u_poc_meta of mig_7series_v2_3_poc_meta.v input [1:0] ninety_offsets; // To u_poc_meta of mig_7series_v2_3_poc_meta.v input pd_out; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v input poc_sample_pd; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v input psdone; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v input rst; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v, ... input use_noise_window; // To u_poc_meta of mig_7series_v2_3_poc_meta.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output poc_backup; // From u_poc_meta of mig_7series_v2_3_poc_meta.v output poc_error; // From u_poc_cc of mig_7series_v2_3_poc_cc.v output psincdec; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v // End of automatics /*AUTOwire*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [TAPCNTRWIDTH-1:0] fall_lead_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_lead_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_lead_right; // From u_edge_right of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_right; // From u_edge_right of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_lead_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_lead_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_trail_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_trail_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] run; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire run_end; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire run_polarity; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire [SAMPCNTRWIDTH:0] samples; // From u_poc_cc of mig_7series_v2_3_poc_cc.v wire [SAMPCNTRWIDTH:0] samps_hi_held; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire [SAMPCNTRWIDTH:0] samps_solid_thresh; // From u_poc_cc of mig_7series_v2_3_poc_cc.v wire [TAPCNTRWIDTH-1:0] tap; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v // End of automatics output psen; output [TAPCNTRWIDTH-1:0] rise_lead_right; output [TAPCNTRWIDTH-1:0] rise_trail_right; output mmcm_edge_detect_done; output mmcm_lbclk_edge_aligned; mig_7series_v2_3_poc_tap_base # (/*AUTOINSTPARAM*/ // Parameters .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_poc_tap_base (/*AUTOINST*/ // Outputs .psen (psen), .psincdec (psincdec), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]), .tap (tap[TAPCNTRWIDTH-1:0]), // Inputs .clk (clk), .pd_out (pd_out), .poc_sample_pd (poc_sample_pd), .psdone (psdone), .rst (rst), .samples (samples[SAMPCNTRWIDTH:0]), .samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0])); mig_7series_v2_3_poc_meta # (/*AUTOINSTPARAM*/ // Parameters .SCANFROMRIGHT (SCANFROMRIGHT), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_poc_meta (/*AUTOINST*/ // Outputs .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .poc_backup (poc_backup), // Inputs .clk (clk), .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), .ninety_offsets (ninety_offsets[1:0]), .rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]), .rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]), .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), .rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]), .rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]), .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), .rst (rst), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .use_noise_window (use_noise_window)); /*mig_7series_v2_3_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" ( .\(.*\)lead (\1lead_@@"vl-bits"), .\(.*\)trail (\1trail_@@"vl-bits"), .select0 (ktap_at_@_edge), .select1 (1'b1),)*/ mig_7series_v2_3_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_right (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_right[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_right[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_right[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_right[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (ktap_at_right_edge), // Templated .select1 (1'b1), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); mig_7series_v2_3_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_left (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_left[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_left[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_left[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_left[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (ktap_at_left_edge), // Templated .select1 (1'b1), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); wire not_ktap_at_right_edge = ~ktap_at_right_edge; wire not_ktap_at_left_edge = ~ktap_at_left_edge; /*mig_7series_v2_3_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" ( .\(.*\)lead (\1lead_@@"vl-bits"), .\(.*\)trail (\1trail_@@"vl-bits"), .select0 (not_ktap_at_right_edge), .select1 (not_ktap_at_left_edge),)*/ mig_7series_v2_3_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_center (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_center[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_center[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_center[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_center[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (not_ktap_at_right_edge), // Templated .select1 (not_ktap_at_left_edge), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); mig_7series_v2_3_poc_cc # (/*AUTOINSTPARAM*/ // Parameters .CCENABLE (CCENABLE), .PCT_SAMPS_SOLID (PCT_SAMPS_SOLID), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .SAMPLES (SAMPLES), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TCQ (TCQ)) u_poc_cc (/*AUTOINST*/ // Outputs .poc_error (poc_error), .samples (samples[SAMPCNTRWIDTH:0]), .samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0]), // Inputs .clk (clk), .fall_lead_center (fall_lead_center[TAPCNTRWIDTH-1:0]), .fall_lead_left (fall_lead_left[TAPCNTRWIDTH-1:0]), .fall_lead_right (fall_lead_right[TAPCNTRWIDTH-1:0]), .fall_trail_center (fall_trail_center[TAPCNTRWIDTH-1:0]), .fall_trail_left (fall_trail_left[TAPCNTRWIDTH-1:0]), .fall_trail_right (fall_trail_right[TAPCNTRWIDTH-1:0]), .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .psen (psen), .rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]), .rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]), .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), .rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]), .rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]), .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), .rst (rst), .samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]), .tap (tap[TAPCNTRWIDTH-1:0])); endmodule // mig_7series_v2_3_poc_top // Local Variables: // verilog-library-directories:(".") // verilog-library-extensions:(".v") // End:
//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v2_3_poc_top.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 15 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: Phaser out calibration top. //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_poc_top # (parameter MMCM_SAMP_WAIT = 10, parameter PCT_SAMPS_SOLID = 95, parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter TCQ = 100, parameter CCENABLE = 0, parameter SCANFROMRIGHT = 0, parameter SAMPCNTRWIDTH = 8, parameter SAMPLES = 128, parameter TAPCNTRWIDTH = 7, parameter TAPSPERKCLK =112) (/*AUTOARG*/ // Outputs psincdec, poc_error, poc_backup, psen, rise_lead_right, rise_trail_right, mmcm_edge_detect_done, mmcm_lbclk_edge_aligned, // Inputs use_noise_window, rst, psdone, poc_sample_pd, pd_out, ninety_offsets, mmcm_edge_detect_rdy, ktap_at_right_edge, ktap_at_left_edge, clk ); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input clk; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v, ... input ktap_at_left_edge; // To u_poc_meta of mig_7series_v2_3_poc_meta.v, ... input ktap_at_right_edge; // To u_poc_meta of mig_7series_v2_3_poc_meta.v, ... input mmcm_edge_detect_rdy; // To u_poc_meta of mig_7series_v2_3_poc_meta.v input [1:0] ninety_offsets; // To u_poc_meta of mig_7series_v2_3_poc_meta.v input pd_out; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v input poc_sample_pd; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v input psdone; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v input rst; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v, ... input use_noise_window; // To u_poc_meta of mig_7series_v2_3_poc_meta.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output poc_backup; // From u_poc_meta of mig_7series_v2_3_poc_meta.v output poc_error; // From u_poc_cc of mig_7series_v2_3_poc_cc.v output psincdec; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v // End of automatics /*AUTOwire*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [TAPCNTRWIDTH-1:0] fall_lead_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_lead_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_lead_right; // From u_edge_right of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] fall_trail_right; // From u_edge_right of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_lead_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_lead_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_trail_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] rise_trail_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v wire [TAPCNTRWIDTH-1:0] run; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire run_end; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire run_polarity; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire [SAMPCNTRWIDTH:0] samples; // From u_poc_cc of mig_7series_v2_3_poc_cc.v wire [SAMPCNTRWIDTH:0] samps_hi_held; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v wire [SAMPCNTRWIDTH:0] samps_solid_thresh; // From u_poc_cc of mig_7series_v2_3_poc_cc.v wire [TAPCNTRWIDTH-1:0] tap; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v // End of automatics output psen; output [TAPCNTRWIDTH-1:0] rise_lead_right; output [TAPCNTRWIDTH-1:0] rise_trail_right; output mmcm_edge_detect_done; output mmcm_lbclk_edge_aligned; mig_7series_v2_3_poc_tap_base # (/*AUTOINSTPARAM*/ // Parameters .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_poc_tap_base (/*AUTOINST*/ // Outputs .psen (psen), .psincdec (psincdec), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]), .tap (tap[TAPCNTRWIDTH-1:0]), // Inputs .clk (clk), .pd_out (pd_out), .poc_sample_pd (poc_sample_pd), .psdone (psdone), .rst (rst), .samples (samples[SAMPCNTRWIDTH:0]), .samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0])); mig_7series_v2_3_poc_meta # (/*AUTOINSTPARAM*/ // Parameters .SCANFROMRIGHT (SCANFROMRIGHT), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_poc_meta (/*AUTOINST*/ // Outputs .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .poc_backup (poc_backup), // Inputs .clk (clk), .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), .ninety_offsets (ninety_offsets[1:0]), .rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]), .rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]), .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), .rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]), .rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]), .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), .rst (rst), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .use_noise_window (use_noise_window)); /*mig_7series_v2_3_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" ( .\(.*\)lead (\1lead_@@"vl-bits"), .\(.*\)trail (\1trail_@@"vl-bits"), .select0 (ktap_at_@_edge), .select1 (1'b1),)*/ mig_7series_v2_3_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_right (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_right[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_right[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_right[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_right[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (ktap_at_right_edge), // Templated .select1 (1'b1), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); mig_7series_v2_3_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_left (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_left[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_left[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_left[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_left[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (ktap_at_left_edge), // Templated .select1 (1'b1), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); wire not_ktap_at_right_edge = ~ktap_at_right_edge; wire not_ktap_at_left_edge = ~ktap_at_left_edge; /*mig_7series_v2_3_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" ( .\(.*\)lead (\1lead_@@"vl-bits"), .\(.*\)trail (\1trail_@@"vl-bits"), .select0 (not_ktap_at_right_edge), .select1 (not_ktap_at_left_edge),)*/ mig_7series_v2_3_poc_edge_store # (/*AUTOINSTPARAM*/ // Parameters .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_edge_center (/*AUTOINST*/ // Outputs .fall_lead (fall_lead_center[TAPCNTRWIDTH-1:0]), // Templated .fall_trail (fall_trail_center[TAPCNTRWIDTH-1:0]), // Templated .rise_lead (rise_lead_center[TAPCNTRWIDTH-1:0]), // Templated .rise_trail (rise_trail_center[TAPCNTRWIDTH-1:0]), // Templated // Inputs .clk (clk), .run (run[TAPCNTRWIDTH-1:0]), .run_end (run_end), .run_polarity (run_polarity), .select0 (not_ktap_at_right_edge), // Templated .select1 (not_ktap_at_left_edge), // Templated .tap (tap[TAPCNTRWIDTH-1:0])); mig_7series_v2_3_poc_cc # (/*AUTOINSTPARAM*/ // Parameters .CCENABLE (CCENABLE), .PCT_SAMPS_SOLID (PCT_SAMPS_SOLID), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .SAMPLES (SAMPLES), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TCQ (TCQ)) u_poc_cc (/*AUTOINST*/ // Outputs .poc_error (poc_error), .samples (samples[SAMPCNTRWIDTH:0]), .samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0]), // Inputs .clk (clk), .fall_lead_center (fall_lead_center[TAPCNTRWIDTH-1:0]), .fall_lead_left (fall_lead_left[TAPCNTRWIDTH-1:0]), .fall_lead_right (fall_lead_right[TAPCNTRWIDTH-1:0]), .fall_trail_center (fall_trail_center[TAPCNTRWIDTH-1:0]), .fall_trail_left (fall_trail_left[TAPCNTRWIDTH-1:0]), .fall_trail_right (fall_trail_right[TAPCNTRWIDTH-1:0]), .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .psen (psen), .rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]), .rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]), .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), .rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]), .rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]), .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), .rst (rst), .samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]), .tap (tap[TAPCNTRWIDTH-1:0])); endmodule // mig_7series_v2_3_poc_top // Local Variables: // verilog-library-directories:(".") // verilog-library-extensions:(".v") // End:
//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_oclkdelay_cal.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3 // delay //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_ocd_lim # (parameter TAPCNTRWIDTH = 7, parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 9, parameter TCQ = 100, parameter TAPSPERKCLK = 56, parameter TDQSS_DEGREES = 60, parameter BYPASS_COMPLEX_OCAL = "FALSE") (/*AUTOARG*/ // Outputs lim2init_write_request, lim2init_prech_req, lim2poc_rdy, lim2poc_ktap_right, lim2stg3_inc, lim2stg3_dec, lim2stg2_inc, lim2stg2_dec, lim_done, lim2ocal_stg3_right_lim, lim2ocal_stg3_left_lim, dbg_ocd_lim, // Inputs clk, rst, lim_start, po_rdy, poc2lim_rise_align_taps_lead, poc2lim_rise_align_taps_trail, poc2lim_fall_align_taps_lead, poc2lim_fall_align_taps_trail, oclkdelay_init_val, wl_po_fine_cnt, simp_stg3_final_sel, oclkdelay_calib_done, poc2lim_detect_done, prech_done, oclkdelay_calib_cnt ); function [TAPCNTRWIDTH:0] mod_sub (input [TAPCNTRWIDTH-1:0] a, input [TAPCNTRWIDTH-1:0] b, input integer base); begin mod_sub = (a>=b) ? a-b : a+base[TAPCNTRWIDTH-1:0]-b; end endfunction // mod_sub input clk; input rst; input lim_start; input po_rdy; input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_lead; input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_trail; input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_lead; input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_trail; input [5:0] oclkdelay_init_val; input [5:0] wl_po_fine_cnt; input [5:0] simp_stg3_final_sel; input oclkdelay_calib_done; input poc2lim_detect_done; input prech_done; input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; output lim2init_write_request; output lim2init_prech_req; output lim2poc_rdy; output lim2poc_ktap_right; // I think this can be defaulted. output lim2stg3_inc; output lim2stg3_dec; output lim2stg2_inc; output lim2stg2_dec; output lim_done; output [5:0] lim2ocal_stg3_right_lim; output [5:0] lim2ocal_stg3_left_lim; output [255:0] dbg_ocd_lim; // Stage 3 taps can move an additional + or - 60 degrees from the write level position // Convert 60 degrees to MMCM taps. 360/60=6. //localparam real DIV_FACTOR = 360/TDQSS_DEGREES; //localparam real TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR; localparam DIV_FACTOR = 360/TDQSS_DEGREES; localparam TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR; localparam WAIT_CNT = 15; localparam IDLE = 14'b00_0000_0000_0001; localparam INIT = 14'b00_0000_0000_0010; localparam WAIT_WR_REQ = 14'b00_0000_0000_0100; localparam WAIT_POC_DONE = 14'b00_0000_0000_1000; localparam WAIT_STG3 = 14'b00_0000_0001_0000; localparam STAGE3_INC = 14'b00_0000_0010_0000; localparam STAGE3_DEC = 14'b00_0000_0100_0000; localparam STAGE2_INC = 14'b00_0000_1000_0000; localparam STAGE2_DEC = 14'b00_0001_0000_0000; localparam STG3_INCDEC_WAIT = 14'b00_0010_0000_0000; localparam STG2_INCDEC_WAIT = 14'b00_0100_0000_0000; localparam STAGE2_TAP_CHK = 14'b00_1000_0000_0000; localparam PRECH_REQUEST = 14'b01_0000_0000_0000; localparam LIMIT_DONE = 14'b10_0000_0000_0000; // Flip-flops reg [5:0] stg3_init_val; reg [13:0] lim_state; reg lim_start_r; reg ktap_right_r; reg write_request_r; reg prech_req_r; reg poc_ready_r; reg wait_cnt_en_r; reg wait_cnt_done; reg [3:0] wait_cnt_r; reg [5:0] stg3_tap_cnt; reg [5:0] stg2_tap_cnt; reg [5:0] stg3_left_lim; reg [5:0] stg3_right_lim; reg [DQS_WIDTH*6-1:0] cmplx_stg3_left_lim; reg [DQS_WIDTH*6-1:0] simp_stg3_left_lim; reg [DQS_WIDTH*6-1:0] cmplx_stg3_right_lim; reg [DQS_WIDTH*6-1:0] simp_stg3_right_lim; reg [5:0] stg3_dec_val; reg [5:0] stg3_inc_val; reg detect_done_r; reg stg3_dec_r; reg stg2_inc_r; reg stg3_inc2init_val_r; reg stg3_inc2init_val_r1; reg stg3_dec2init_val_r; reg stg3_dec2init_val_r1; reg stg3_dec_req_r; reg stg3_inc_req_r; reg stg2_dec_req_r; reg stg2_inc_req_r; reg stg3_init_dec_r; reg [TAPCNTRWIDTH:0] mmcm_current; reg [TAPCNTRWIDTH:0] mmcm_init_trail; reg [TAPCNTRWIDTH:0] mmcm_init_lead; reg done_r; reg [13:0] lim_nxt_state; reg ktap_right; reg write_request; reg prech_req; reg poc_ready; reg stg3_dec; reg stg2_inc; reg stg3_inc2init_val; reg stg3_dec2init_val; reg stg3_dec_req; reg stg3_inc_req; reg stg2_dec_req; reg stg2_inc_req; reg stg3_init_dec; reg done; reg oclkdelay_calib_done_r; wire [TAPCNTRWIDTH:0] mmcm_sub_dec = mod_sub (mmcm_init_trail, mmcm_current, TAPSPERKCLK); wire [TAPCNTRWIDTH:0] mmcm_sub_inc = mod_sub (mmcm_current, mmcm_init_lead, TAPSPERKCLK); /***************************************************************************/ // Debug signals /***************************************************************************/ assign dbg_ocd_lim[0+:DQS_WIDTH*6] = simp_stg3_left_lim[DQS_WIDTH*6-1:0]; assign dbg_ocd_lim[54+:DQS_WIDTH*6] = simp_stg3_right_lim[DQS_WIDTH*6-1:0]; assign dbg_ocd_lim[255:108] = 'd0; assign lim2init_write_request = write_request_r; assign lim2init_prech_req = prech_req_r; assign lim2poc_ktap_right = ktap_right_r; assign lim2poc_rdy = poc_ready_r; assign lim2ocal_stg3_left_lim = stg3_left_lim; assign lim2ocal_stg3_right_lim = stg3_right_lim; assign lim2stg3_dec = stg3_dec_req_r; assign lim2stg3_inc = stg3_inc_req_r; assign lim2stg2_dec = stg2_dec_req_r; assign lim2stg2_inc = stg2_inc_req_r; assign lim_done = done_r; /**************************Wait Counter Start*********************************/ // Wait counter enable for wait states WAIT_WR_REQ and WAIT_STG3 // To avoid DQS toggling when stage2 and 3 taps are moving always @(posedge clk) begin if ((lim_state == WAIT_WR_REQ) || (lim_state == WAIT_STG3) || (lim_state == INIT)) wait_cnt_en_r <= #TCQ 1'b1; else wait_cnt_en_r <= #TCQ 1'b0; end // Wait counter for wait states WAIT_WR_REQ and WAIT_STG3 // To avoid DQS toggling when stage2 and 3 taps are moving always @(posedge clk) begin if (!wait_cnt_en_r) begin wait_cnt_r <= #TCQ 'b0; wait_cnt_done <= #TCQ 1'b0; end else begin if (wait_cnt_r != WAIT_CNT - 1) begin wait_cnt_r <= #TCQ wait_cnt_r + 1; wait_cnt_done <= #TCQ 1'b0; end else begin wait_cnt_r <= #TCQ 'b0; wait_cnt_done <= #TCQ 1'b1; end end end /**************************Wait Counter End***********************************/ // Flip-flops always @(posedge clk) begin if (rst) oclkdelay_calib_done_r <= #TCQ 1'b0; else oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done; end always @(posedge clk) begin if (rst) stg3_init_val <= #TCQ oclkdelay_init_val; else if (oclkdelay_calib_done) stg3_init_val <= #TCQ simp_stg3_final_sel; else stg3_init_val <= #TCQ oclkdelay_init_val; end always @(posedge clk) begin if (rst) begin lim_state <= #TCQ IDLE; lim_start_r <= #TCQ 1'b0; ktap_right_r <= #TCQ 1'b0; write_request_r <= #TCQ 1'b0; prech_req_r <= #TCQ 1'b0; poc_ready_r <= #TCQ 1'b0; detect_done_r <= #TCQ 1'b0; stg3_dec_r <= #TCQ 1'b0; stg2_inc_r <= #TCQ 1'b0; stg3_inc2init_val_r <= #TCQ 1'b0; stg3_inc2init_val_r1<= #TCQ 1'b0; stg3_dec2init_val_r <= #TCQ 1'b0; stg3_dec2init_val_r1<= #TCQ 1'b0; stg3_dec_req_r <= #TCQ 1'b0; stg3_inc_req_r <= #TCQ 1'b0; stg2_dec_req_r <= #TCQ 1'b0; stg2_inc_req_r <= #TCQ 1'b0; done_r <= #TCQ 1'b0; stg3_dec_val <= #TCQ 'd0; stg3_inc_val <= #TCQ 'd0; stg3_init_dec_r <= #TCQ 1'b0; end else begin lim_state <= #TCQ lim_nxt_state; lim_start_r <= #TCQ lim_start; ktap_right_r <= #TCQ ktap_right; write_request_r <= #TCQ write_request; prech_req_r <= #TCQ prech_req; poc_ready_r <= #TCQ poc_ready; detect_done_r <= #TCQ poc2lim_detect_done; stg3_dec_r <= #TCQ stg3_dec; stg2_inc_r <= #TCQ stg2_inc; stg3_inc2init_val_r <= #TCQ stg3_inc2init_val; stg3_inc2init_val_r1<= #TCQ stg3_inc2init_val_r; stg3_dec2init_val_r <= #TCQ stg3_dec2init_val; stg3_dec2init_val_r1<= #TCQ stg3_dec2init_val_r; stg3_dec_req_r <= #TCQ stg3_dec_req; stg3_inc_req_r <= #TCQ stg3_inc_req; stg2_dec_req_r <= #TCQ stg2_dec_req; stg2_inc_req_r <= #TCQ stg2_inc_req; stg3_init_dec_r <= #TCQ stg3_init_dec; done_r <= #TCQ done; if (stg3_init_val > (('d63 - wl_po_fine_cnt)/2)) stg3_dec_val <= #TCQ (stg3_init_val - ('d63 - wl_po_fine_cnt)/2); else stg3_dec_val <= #TCQ 'd0; if (stg3_init_val < 'd63 - ((wl_po_fine_cnt)/2)) stg3_inc_val <= #TCQ (stg3_init_val + (wl_po_fine_cnt)/2); else stg3_inc_val <= #TCQ 'd63; end end // Keeping track of stage 3 tap count always @(posedge clk) begin if (rst) stg3_tap_cnt <= #TCQ stg3_init_val; else if ((lim_state == IDLE) || (lim_state == INIT)) stg3_tap_cnt <= #TCQ stg3_init_val; else if (lim_state == STAGE3_INC) stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1; else if (lim_state == STAGE3_DEC) stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1; end // Keeping track of stage 2 tap count always @(posedge clk) begin if (rst) stg2_tap_cnt <= #TCQ 'd0; else if ((lim_state == IDLE) || (lim_state == INIT)) stg2_tap_cnt <= #TCQ wl_po_fine_cnt; else if (lim_state == STAGE2_INC) stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1; else if (lim_state == STAGE2_DEC) stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1; end // Keeping track of MMCM tap count always @(posedge clk) begin if (rst) begin mmcm_init_trail <= #TCQ 'd0; mmcm_init_lead <= #TCQ 'd0; end else if (poc2lim_detect_done && !detect_done_r) begin if (stg3_tap_cnt == stg3_dec_val) mmcm_init_trail <= #TCQ poc2lim_rise_align_taps_trail; if (stg3_tap_cnt == stg3_inc_val) mmcm_init_lead <= #TCQ poc2lim_rise_align_taps_lead; end end always @(posedge clk) begin if (rst) begin mmcm_current <= #TCQ 'd0; end else if (stg3_dec_r) begin if (stg3_tap_cnt == stg3_dec_val) mmcm_current <= #TCQ mmcm_init_trail; else mmcm_current <= #TCQ poc2lim_rise_align_taps_lead; end else begin if (stg3_tap_cnt == stg3_inc_val) mmcm_current <= #TCQ mmcm_init_lead; else mmcm_current <= #TCQ poc2lim_rise_align_taps_trail; end end // Record Stage3 Left Limit always @(posedge clk) begin if (rst) begin stg3_left_lim <= #TCQ 'd0; simp_stg3_left_lim <= #TCQ 'd0; cmplx_stg3_left_lim <= #TCQ 'd0; end else if (stg3_inc2init_val_r && !stg3_inc2init_val_r1) begin stg3_left_lim <= #TCQ stg3_tap_cnt; if (oclkdelay_calib_done) cmplx_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; else simp_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; end else if (lim_start && !lim_start_r) stg3_left_lim <= #TCQ 'd0; end // Record Stage3 Right Limit always @(posedge clk) begin if (rst) begin stg3_right_lim <= #TCQ 'd0; cmplx_stg3_right_lim <= #TCQ 'd0; simp_stg3_right_lim <= #TCQ 'd0; end else if (stg3_dec2init_val_r && !stg3_dec2init_val_r1) begin stg3_right_lim <= #TCQ stg3_tap_cnt; if (oclkdelay_calib_done) cmplx_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; else simp_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; end else if (lim_start && !lim_start_r) stg3_right_lim <= #TCQ 'd0; end always @(*) begin lim_nxt_state = lim_state; ktap_right = ktap_right_r; write_request = write_request_r; prech_req = prech_req_r; poc_ready = poc_ready_r; stg3_dec = stg3_dec_r; stg2_inc = stg2_inc_r; stg3_inc2init_val = stg3_inc2init_val_r; stg3_dec2init_val = stg3_dec2init_val_r; stg3_dec_req = stg3_dec_req_r; stg3_inc_req = stg3_inc_req_r; stg2_inc_req = stg2_inc_req_r; stg2_dec_req = stg2_dec_req_r; stg3_init_dec = stg3_init_dec_r; done = done_r; case(lim_state) IDLE: begin if (lim_start && !lim_start_r) begin lim_nxt_state = INIT; stg3_dec = 1'b1; stg2_inc = 1'b1; stg3_init_dec = 1'b1; done = 1'b0; end //New start of limit module for complex oclkdelay calib else if (oclkdelay_calib_done && !oclkdelay_calib_done_r && (BYPASS_COMPLEX_OCAL == "FALSE")) begin done = 1'b0; end end INIT: begin ktap_right = 1'b1; // Initial stage 2 increment to 63 for left limit if (wait_cnt_done) lim_nxt_state = STAGE2_TAP_CHK; end // Wait for DQS to toggle before asserting poc_ready WAIT_WR_REQ: begin write_request = 1'b1; if (wait_cnt_done) begin poc_ready = 1'b1; lim_nxt_state = WAIT_POC_DONE; end end // Wait for POC detect done signal WAIT_POC_DONE: begin if (poc2lim_detect_done) begin write_request = 1'b0; poc_ready = 1'b0; lim_nxt_state = WAIT_STG3; end end // Wait for DQS to stop toggling before stage3 inc/dec WAIT_STG3: begin if (wait_cnt_done) begin if (stg3_dec_r) begin // Check for Stage 3 underflow and MMCM tap limit if ((stg3_tap_cnt > 'd0) && (mmcm_sub_dec < TDQSS_LIM_MMCM_TAPS)) lim_nxt_state = STAGE3_DEC; else begin stg3_dec = 1'b0; stg3_inc2init_val = 1'b1; lim_nxt_state = STAGE3_INC; end end else begin // Stage 3 being incremented // Check for Stage 3 overflow and MMCM tap limit if ((stg3_tap_cnt < 'd63) && (mmcm_sub_inc < TDQSS_LIM_MMCM_TAPS)) lim_nxt_state = STAGE3_INC; else begin stg3_dec2init_val = 1'b1; lim_nxt_state = STAGE3_DEC; end end end end STAGE3_INC: begin stg3_inc_req = 1'b1; lim_nxt_state = STG3_INCDEC_WAIT; end STAGE3_DEC: begin stg3_dec_req = 1'b1; lim_nxt_state = STG3_INCDEC_WAIT; end // Wait for stage3 inc/dec to complete (po_rdy) STG3_INCDEC_WAIT: begin stg3_dec_req = 1'b0; stg3_inc_req = 1'b0; if (!stg3_dec_req_r && !stg3_inc_req_r && po_rdy) begin if (stg3_init_dec_r) begin // Initial decrement of stage 3 if (stg3_tap_cnt > stg3_dec_val) lim_nxt_state = STAGE3_DEC; else begin lim_nxt_state = WAIT_WR_REQ; stg3_init_dec = 1'b0; end end else if (stg3_dec2init_val_r) begin if (stg3_tap_cnt > stg3_init_val) lim_nxt_state = STAGE3_DEC; else lim_nxt_state = STAGE2_TAP_CHK; end else if (stg3_inc2init_val_r) begin if (stg3_tap_cnt < stg3_inc_val) lim_nxt_state = STAGE3_INC; else lim_nxt_state = STAGE2_TAP_CHK; end else begin lim_nxt_state = WAIT_WR_REQ; end end end // Check for overflow and underflow of stage2 taps STAGE2_TAP_CHK: begin if (stg3_dec2init_val_r) begin // Increment stage 2 to write level tap value at the end of limit detection if (stg2_tap_cnt < wl_po_fine_cnt) lim_nxt_state = STAGE2_INC; else begin lim_nxt_state = PRECH_REQUEST; end end else if (stg3_inc2init_val_r) begin // Decrement stage 2 to '0' to determine right limit if (stg2_tap_cnt > 'd0) lim_nxt_state = STAGE2_DEC; else begin lim_nxt_state = PRECH_REQUEST; stg3_inc2init_val = 1'b0; end end else if (stg2_inc_r && (stg2_tap_cnt < 'd63)) begin // Initial increment to 63 lim_nxt_state = STAGE2_INC; end else begin lim_nxt_state = STG3_INCDEC_WAIT; stg2_inc = 1'b0; end end STAGE2_INC: begin stg2_inc_req = 1'b1; lim_nxt_state = STG2_INCDEC_WAIT; end STAGE2_DEC: begin stg2_dec_req = 1'b1; lim_nxt_state = STG2_INCDEC_WAIT; end // Wait for stage3 inc/dec to complete (po_rdy) STG2_INCDEC_WAIT: begin stg2_inc_req = 1'b0; stg2_dec_req = 1'b0; if (!stg2_inc_req_r && !stg2_dec_req_r && po_rdy) lim_nxt_state = STAGE2_TAP_CHK; end PRECH_REQUEST: begin prech_req = 1'b1; if (prech_done) begin prech_req = 1'b0; if (stg3_dec2init_val_r) lim_nxt_state = LIMIT_DONE; else lim_nxt_state = WAIT_WR_REQ; end end LIMIT_DONE: begin done = 1'b1; ktap_right = 1'b0; stg3_dec2init_val = 1'b0; lim_nxt_state = IDLE; end default: begin lim_nxt_state = IDLE; end endcase end endmodule //mig_7_series_v2_3_ddr_phy_ocd_lim
//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2.3 // \ \ Application : MIG // / / Filename : dram.v // /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $ // \ \ / \ Date Created : Wed Feb 01 2012 // \___\/\___\ // // Device : 7 Series // Design Name : DDR3 SDRAM // Purpose : // Wrapper module for the user design top level file. This module can be // instantiated in the system and interconnect as shown in example design // (example_top module). // Revision History : //***************************************************************************** `timescale 1ps/1ps module dram ( // Inouts inout [63:0] ddr3_dq, inout [7:0] ddr3_dqs_n, inout [7:0] ddr3_dqs_p, // Outputs output [15:0] ddr3_addr, output [2:0] ddr3_ba, output ddr3_ras_n, output ddr3_cas_n, output ddr3_we_n, output ddr3_reset_n, output [0:0] ddr3_ck_p, output [0:0] ddr3_ck_n, output [0:0] ddr3_cke, output [0:0] ddr3_cs_n, output [7:0] ddr3_dm, output [0:0] ddr3_odt, // Inputs // Differential system clocks input sys_clk_p, input sys_clk_n, // user interface signals input [29:0] app_addr, input [2:0] app_cmd, input app_en, input [511:0] app_wdf_data, input app_wdf_end, input [63:0] app_wdf_mask, input app_wdf_wren, output [511:0] app_rd_data, output app_rd_data_end, output app_rd_data_valid, output app_rdy, output app_wdf_rdy, input app_sr_req, input app_ref_req, input app_zq_req, output app_sr_active, output app_ref_ack, output app_zq_ack, output ui_clk, output ui_clk_sync_rst, output init_calib_complete, input sys_rst ); // Start of IP top instance dram_mig u_dram_mig ( // Memory interface ports .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), .ddr3_cas_n (ddr3_cas_n), .ddr3_ck_n (ddr3_ck_n), .ddr3_ck_p (ddr3_ck_p), .ddr3_cke (ddr3_cke), .ddr3_ras_n (ddr3_ras_n), .ddr3_reset_n (ddr3_reset_n), .ddr3_we_n (ddr3_we_n), .ddr3_dq (ddr3_dq), .ddr3_dqs_n (ddr3_dqs_n), .ddr3_dqs_p (ddr3_dqs_p), .init_calib_complete (init_calib_complete), .ddr3_cs_n (ddr3_cs_n), .ddr3_dm (ddr3_dm), .ddr3_odt (ddr3_odt), // Application interface ports .app_addr (app_addr), .app_cmd (app_cmd), .app_en (app_en), .app_wdf_data (app_wdf_data), .app_wdf_end (app_wdf_end), .app_wdf_wren (app_wdf_wren), .app_rd_data (app_rd_data), .app_rd_data_end (app_rd_data_end), .app_rd_data_valid (app_rd_data_valid), .app_rdy (app_rdy), .app_wdf_rdy (app_wdf_rdy), .app_sr_req (app_sr_req), .app_ref_req (app_ref_req), .app_zq_req (app_zq_req), .app_sr_active (app_sr_active), .app_ref_ack (app_ref_ack), .app_zq_ack (app_zq_ack), .ui_clk (ui_clk), .ui_clk_sync_rst (ui_clk_sync_rst), .app_wdf_mask (app_wdf_mask), // System Clock Ports .sys_clk_p (sys_clk_p), .sys_clk_n (sys_clk_n), .sys_rst (sys_rst) ); // End of IP top instance endmodule
//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2.3 // \ \ Application : MIG // / / Filename : dram.v // /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $ // \ \ / \ Date Created : Wed Feb 01 2012 // \___\/\___\ // // Device : 7 Series // Design Name : DDR3 SDRAM // Purpose : // Wrapper module for the user design top level file. This module can be // instantiated in the system and interconnect as shown in example design // (example_top module). // Revision History : //***************************************************************************** `timescale 1ps/1ps module dram ( // Inouts inout [63:0] ddr3_dq, inout [7:0] ddr3_dqs_n, inout [7:0] ddr3_dqs_p, // Outputs output [15:0] ddr3_addr, output [2:0] ddr3_ba, output ddr3_ras_n, output ddr3_cas_n, output ddr3_we_n, output ddr3_reset_n, output [0:0] ddr3_ck_p, output [0:0] ddr3_ck_n, output [0:0] ddr3_cke, output [0:0] ddr3_cs_n, output [7:0] ddr3_dm, output [0:0] ddr3_odt, // Inputs // Differential system clocks input sys_clk_p, input sys_clk_n, // user interface signals input [29:0] app_addr, input [2:0] app_cmd, input app_en, input [511:0] app_wdf_data, input app_wdf_end, input [63:0] app_wdf_mask, input app_wdf_wren, output [511:0] app_rd_data, output app_rd_data_end, output app_rd_data_valid, output app_rdy, output app_wdf_rdy, input app_sr_req, input app_ref_req, input app_zq_req, output app_sr_active, output app_ref_ack, output app_zq_ack, output ui_clk, output ui_clk_sync_rst, output init_calib_complete, input sys_rst ); // Start of IP top instance dram_mig u_dram_mig ( // Memory interface ports .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), .ddr3_cas_n (ddr3_cas_n), .ddr3_ck_n (ddr3_ck_n), .ddr3_ck_p (ddr3_ck_p), .ddr3_cke (ddr3_cke), .ddr3_ras_n (ddr3_ras_n), .ddr3_reset_n (ddr3_reset_n), .ddr3_we_n (ddr3_we_n), .ddr3_dq (ddr3_dq), .ddr3_dqs_n (ddr3_dqs_n), .ddr3_dqs_p (ddr3_dqs_p), .init_calib_complete (init_calib_complete), .ddr3_cs_n (ddr3_cs_n), .ddr3_dm (ddr3_dm), .ddr3_odt (ddr3_odt), // Application interface ports .app_addr (app_addr), .app_cmd (app_cmd), .app_en (app_en), .app_wdf_data (app_wdf_data), .app_wdf_end (app_wdf_end), .app_wdf_wren (app_wdf_wren), .app_rd_data (app_rd_data), .app_rd_data_end (app_rd_data_end), .app_rd_data_valid (app_rd_data_valid), .app_rdy (app_rdy), .app_wdf_rdy (app_wdf_rdy), .app_sr_req (app_sr_req), .app_ref_req (app_ref_req), .app_zq_req (app_zq_req), .app_sr_active (app_sr_active), .app_ref_ack (app_ref_ack), .app_zq_ack (app_zq_ack), .ui_clk (ui_clk), .ui_clk_sync_rst (ui_clk_sync_rst), .app_wdf_mask (app_wdf_mask), // System Clock Ports .sys_clk_p (sys_clk_p), .sys_clk_n (sys_clk_n), .sys_rst (sys_rst) ); // End of IP top instance endmodule
//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2.3 // \ \ Application : MIG // / / Filename : dram.v // /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $ // \ \ / \ Date Created : Wed Feb 01 2012 // \___\/\___\ // // Device : 7 Series // Design Name : DDR3 SDRAM // Purpose : // Wrapper module for the user design top level file. This module can be // instantiated in the system and interconnect as shown in example design // (example_top module). // Revision History : //***************************************************************************** `timescale 1ps/1ps module dram ( // Inouts inout [63:0] ddr3_dq, inout [7:0] ddr3_dqs_n, inout [7:0] ddr3_dqs_p, // Outputs output [15:0] ddr3_addr, output [2:0] ddr3_ba, output ddr3_ras_n, output ddr3_cas_n, output ddr3_we_n, output ddr3_reset_n, output [0:0] ddr3_ck_p, output [0:0] ddr3_ck_n, output [0:0] ddr3_cke, output [0:0] ddr3_cs_n, output [7:0] ddr3_dm, output [0:0] ddr3_odt, // Inputs // Differential system clocks input sys_clk_p, input sys_clk_n, // user interface signals input [29:0] app_addr, input [2:0] app_cmd, input app_en, input [511:0] app_wdf_data, input app_wdf_end, input [63:0] app_wdf_mask, input app_wdf_wren, output [511:0] app_rd_data, output app_rd_data_end, output app_rd_data_valid, output app_rdy, output app_wdf_rdy, input app_sr_req, input app_ref_req, input app_zq_req, output app_sr_active, output app_ref_ack, output app_zq_ack, output ui_clk, output ui_clk_sync_rst, output init_calib_complete, input sys_rst ); // Start of IP top instance dram_mig u_dram_mig ( // Memory interface ports .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), .ddr3_cas_n (ddr3_cas_n), .ddr3_ck_n (ddr3_ck_n), .ddr3_ck_p (ddr3_ck_p), .ddr3_cke (ddr3_cke), .ddr3_ras_n (ddr3_ras_n), .ddr3_reset_n (ddr3_reset_n), .ddr3_we_n (ddr3_we_n), .ddr3_dq (ddr3_dq), .ddr3_dqs_n (ddr3_dqs_n), .ddr3_dqs_p (ddr3_dqs_p), .init_calib_complete (init_calib_complete), .ddr3_cs_n (ddr3_cs_n), .ddr3_dm (ddr3_dm), .ddr3_odt (ddr3_odt), // Application interface ports .app_addr (app_addr), .app_cmd (app_cmd), .app_en (app_en), .app_wdf_data (app_wdf_data), .app_wdf_end (app_wdf_end), .app_wdf_wren (app_wdf_wren), .app_rd_data (app_rd_data), .app_rd_data_end (app_rd_data_end), .app_rd_data_valid (app_rd_data_valid), .app_rdy (app_rdy), .app_wdf_rdy (app_wdf_rdy), .app_sr_req (app_sr_req), .app_ref_req (app_ref_req), .app_zq_req (app_zq_req), .app_sr_active (app_sr_active), .app_ref_ack (app_ref_ack), .app_zq_ack (app_zq_ack), .ui_clk (ui_clk), .ui_clk_sync_rst (ui_clk_sync_rst), .app_wdf_mask (app_wdf_mask), // System Clock Ports .sys_clk_p (sys_clk_p), .sys_clk_n (sys_clk_n), .sys_rst (sys_rst) ); // End of IP top instance endmodule
//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2.3 // \ \ Application : MIG // / / Filename : dram.v // /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $ // \ \ / \ Date Created : Wed Feb 01 2012 // \___\/\___\ // // Device : 7 Series // Design Name : DDR3 SDRAM // Purpose : // Wrapper module for the user design top level file. This module can be // instantiated in the system and interconnect as shown in example design // (example_top module). // Revision History : //***************************************************************************** `timescale 1ps/1ps module dram ( // Inouts inout [63:0] ddr3_dq, inout [7:0] ddr3_dqs_n, inout [7:0] ddr3_dqs_p, // Outputs output [15:0] ddr3_addr, output [2:0] ddr3_ba, output ddr3_ras_n, output ddr3_cas_n, output ddr3_we_n, output ddr3_reset_n, output [0:0] ddr3_ck_p, output [0:0] ddr3_ck_n, output [0:0] ddr3_cke, output [0:0] ddr3_cs_n, output [7:0] ddr3_dm, output [0:0] ddr3_odt, // Inputs // Differential system clocks input sys_clk_p, input sys_clk_n, // user interface signals input [29:0] app_addr, input [2:0] app_cmd, input app_en, input [511:0] app_wdf_data, input app_wdf_end, input [63:0] app_wdf_mask, input app_wdf_wren, output [511:0] app_rd_data, output app_rd_data_end, output app_rd_data_valid, output app_rdy, output app_wdf_rdy, input app_sr_req, input app_ref_req, input app_zq_req, output app_sr_active, output app_ref_ack, output app_zq_ack, output ui_clk, output ui_clk_sync_rst, output init_calib_complete, input sys_rst ); // Start of IP top instance dram_mig u_dram_mig ( // Memory interface ports .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), .ddr3_cas_n (ddr3_cas_n), .ddr3_ck_n (ddr3_ck_n), .ddr3_ck_p (ddr3_ck_p), .ddr3_cke (ddr3_cke), .ddr3_ras_n (ddr3_ras_n), .ddr3_reset_n (ddr3_reset_n), .ddr3_we_n (ddr3_we_n), .ddr3_dq (ddr3_dq), .ddr3_dqs_n (ddr3_dqs_n), .ddr3_dqs_p (ddr3_dqs_p), .init_calib_complete (init_calib_complete), .ddr3_cs_n (ddr3_cs_n), .ddr3_dm (ddr3_dm), .ddr3_odt (ddr3_odt), // Application interface ports .app_addr (app_addr), .app_cmd (app_cmd), .app_en (app_en), .app_wdf_data (app_wdf_data), .app_wdf_end (app_wdf_end), .app_wdf_wren (app_wdf_wren), .app_rd_data (app_rd_data), .app_rd_data_end (app_rd_data_end), .app_rd_data_valid (app_rd_data_valid), .app_rdy (app_rdy), .app_wdf_rdy (app_wdf_rdy), .app_sr_req (app_sr_req), .app_ref_req (app_ref_req), .app_zq_req (app_zq_req), .app_sr_active (app_sr_active), .app_ref_ack (app_ref_ack), .app_zq_ack (app_zq_ack), .ui_clk (ui_clk), .ui_clk_sync_rst (ui_clk_sync_rst), .app_wdf_mask (app_wdf_mask), // System Clock Ports .sys_clk_p (sys_clk_p), .sys_clk_n (sys_clk_n), .sys_rst (sys_rst) ); // End of IP top instance endmodule
//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_ck_addr_cmd_delay.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Shift CK/Address/Commands/Controls //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay # ( parameter TCQ = 100, parameter tCK = 3636, parameter DQS_CNT_WIDTH = 3, parameter N_CTL_LANES = 3, parameter SIM_CAL_OPTION = "NONE" ) ( input clk, input rst, // Start only after PO_CIRC_BUF_DELAY decremented input cmd_delay_start, // Control lane being shifted using Phaser_Out fine delay taps output reg [N_CTL_LANES-1:0] ctl_lane_cnt, // Inc/dec Phaser_Out fine delay line output reg po_stg2_f_incdec, output reg po_en_stg2_f, output reg po_stg2_c_incdec, output reg po_en_stg2_c, // Completed delaying CK/Address/Commands/Controls output po_ck_addr_cmd_delay_done ); localparam TAP_CNT_LIMIT = 63; //Calculate the tap resolution of the PHASER based on the clock period localparam FREQ_REF_DIV = (tCK > 5000 ? 4 : tCK > 2500 ? 2 : 1); localparam integer PHASER_TAP_RES = ((tCK/2)/64); // Determine whether 300 ps or 350 ps delay required localparam CALC_TAP_CNT = (tCK >= 1250) ? 350 : 300; // Determine the number of Phaser_Out taps required to delay by 300 ps // 300 ps is the PCB trace uncertainty between CK and DQS byte groups // Increment control byte lanes localparam TAP_CNT = 0; //localparam TAP_CNT = (CALC_TAP_CNT + PHASER_TAP_RES - 1)/PHASER_TAP_RES; //Decrement control byte lanes localparam TAP_DEC = (SIM_CAL_OPTION == "FAST_CAL") ? 0 : 29; reg delay_dec_done; reg delay_done_r1; reg delay_done_r2; reg delay_done_r3; reg delay_done_r4 /* synthesis syn_maxfan = 10 */; reg [5:0] delay_cnt_r; reg [5:0] delaydec_cnt_r; reg po_cnt_inc; reg po_cnt_dec; reg [3:0] wait_cnt_r; assign po_ck_addr_cmd_delay_done = ((TAP_CNT == 0) && (TAP_DEC == 0)) ? 1'b1 : delay_done_r4; always @(posedge clk) begin if (rst || po_cnt_dec || po_cnt_inc) wait_cnt_r <= #TCQ 'd8; else if (cmd_delay_start && (wait_cnt_r > 'd0)) wait_cnt_r <= #TCQ wait_cnt_r - 1; end always @(posedge clk) begin if (rst || (delaydec_cnt_r > 6'd0) || (delay_cnt_r == 'd0) || (TAP_DEC == 0)) po_cnt_inc <= #TCQ 1'b0; else if ((delay_cnt_r > 'd0) && (wait_cnt_r == 'd1)) po_cnt_inc <= #TCQ 1'b1; else po_cnt_inc <= #TCQ 1'b0; end //Tap decrement always @(posedge clk) begin if (rst || (delaydec_cnt_r == 'd0)) po_cnt_dec <= #TCQ 1'b0; else if (cmd_delay_start && (delaydec_cnt_r > 'd0) && (wait_cnt_r == 'd1)) po_cnt_dec <= #TCQ 1'b1; else po_cnt_dec <= #TCQ 1'b0; end //po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane //the alignment is started once the always @(posedge clk) begin if (rst) begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b0; po_stg2_c_incdec <= #TCQ 1'b0; po_en_stg2_c <= #TCQ 1'b0; end else begin if (po_cnt_dec) begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b1; end else begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b0; end if (po_cnt_inc) begin po_stg2_c_incdec <= #TCQ 1'b1; po_en_stg2_c <= #TCQ 1'b1; end else begin po_stg2_c_incdec <= #TCQ 1'b0; po_en_stg2_c <= #TCQ 1'b0; end end end // delay counter to count 2 cycles // Increment coarse taps by 2 for all control byte lanes // to mitigate late writes always @(posedge clk) begin // load delay counter with init value if (rst || (tCK > 2500) || (SIM_CAL_OPTION == "FAST_CAL")) delay_cnt_r <= #TCQ 'd0; else if ((delaydec_cnt_r > 6'd0) ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1))) delay_cnt_r <= #TCQ 'd1; else if (po_cnt_inc && (delay_cnt_r > 6'd0)) delay_cnt_r <= #TCQ delay_cnt_r - 1; end // delay counter to count TAP_DEC cycles always @(posedge clk) begin // load delay counter with init value of TAP_DEC if (rst || ~cmd_delay_start ||((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1))) delaydec_cnt_r <= #TCQ TAP_DEC; else if (po_cnt_dec && (delaydec_cnt_r > 6'd0)) delaydec_cnt_r <= #TCQ delaydec_cnt_r - 1; end //ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle //This ensures all ctrl byte lanes have had their output phase shifted. always @(posedge clk) begin if (rst || ~cmd_delay_start ) ctl_lane_cnt <= #TCQ 6'b0; else if (~delay_dec_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delaydec_cnt_r == 6'd1)) ctl_lane_cnt <= #TCQ ctl_lane_cnt; else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0)) ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; end // All control lanes have decremented to 31 fine taps from 46 always @(posedge clk) begin if (rst || ~cmd_delay_start) begin delay_dec_done <= #TCQ 1'b0; end else if (((TAP_CNT == 0) && (TAP_DEC == 0)) || ((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0) && (ctl_lane_cnt == N_CTL_LANES-1))) begin delay_dec_done <= #TCQ 1'b1; end end always @(posedge clk) begin delay_done_r1 <= #TCQ delay_dec_done; delay_done_r2 <= #TCQ delay_done_r1; delay_done_r3 <= #TCQ delay_done_r2; delay_done_r4 <= #TCQ delay_done_r3; end endmodule
//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_ck_addr_cmd_delay.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Shift CK/Address/Commands/Controls //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay # ( parameter TCQ = 100, parameter tCK = 3636, parameter DQS_CNT_WIDTH = 3, parameter N_CTL_LANES = 3, parameter SIM_CAL_OPTION = "NONE" ) ( input clk, input rst, // Start only after PO_CIRC_BUF_DELAY decremented input cmd_delay_start, // Control lane being shifted using Phaser_Out fine delay taps output reg [N_CTL_LANES-1:0] ctl_lane_cnt, // Inc/dec Phaser_Out fine delay line output reg po_stg2_f_incdec, output reg po_en_stg2_f, output reg po_stg2_c_incdec, output reg po_en_stg2_c, // Completed delaying CK/Address/Commands/Controls output po_ck_addr_cmd_delay_done ); localparam TAP_CNT_LIMIT = 63; //Calculate the tap resolution of the PHASER based on the clock period localparam FREQ_REF_DIV = (tCK > 5000 ? 4 : tCK > 2500 ? 2 : 1); localparam integer PHASER_TAP_RES = ((tCK/2)/64); // Determine whether 300 ps or 350 ps delay required localparam CALC_TAP_CNT = (tCK >= 1250) ? 350 : 300; // Determine the number of Phaser_Out taps required to delay by 300 ps // 300 ps is the PCB trace uncertainty between CK and DQS byte groups // Increment control byte lanes localparam TAP_CNT = 0; //localparam TAP_CNT = (CALC_TAP_CNT + PHASER_TAP_RES - 1)/PHASER_TAP_RES; //Decrement control byte lanes localparam TAP_DEC = (SIM_CAL_OPTION == "FAST_CAL") ? 0 : 29; reg delay_dec_done; reg delay_done_r1; reg delay_done_r2; reg delay_done_r3; reg delay_done_r4 /* synthesis syn_maxfan = 10 */; reg [5:0] delay_cnt_r; reg [5:0] delaydec_cnt_r; reg po_cnt_inc; reg po_cnt_dec; reg [3:0] wait_cnt_r; assign po_ck_addr_cmd_delay_done = ((TAP_CNT == 0) && (TAP_DEC == 0)) ? 1'b1 : delay_done_r4; always @(posedge clk) begin if (rst || po_cnt_dec || po_cnt_inc) wait_cnt_r <= #TCQ 'd8; else if (cmd_delay_start && (wait_cnt_r > 'd0)) wait_cnt_r <= #TCQ wait_cnt_r - 1; end always @(posedge clk) begin if (rst || (delaydec_cnt_r > 6'd0) || (delay_cnt_r == 'd0) || (TAP_DEC == 0)) po_cnt_inc <= #TCQ 1'b0; else if ((delay_cnt_r > 'd0) && (wait_cnt_r == 'd1)) po_cnt_inc <= #TCQ 1'b1; else po_cnt_inc <= #TCQ 1'b0; end //Tap decrement always @(posedge clk) begin if (rst || (delaydec_cnt_r == 'd0)) po_cnt_dec <= #TCQ 1'b0; else if (cmd_delay_start && (delaydec_cnt_r > 'd0) && (wait_cnt_r == 'd1)) po_cnt_dec <= #TCQ 1'b1; else po_cnt_dec <= #TCQ 1'b0; end //po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane //the alignment is started once the always @(posedge clk) begin if (rst) begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b0; po_stg2_c_incdec <= #TCQ 1'b0; po_en_stg2_c <= #TCQ 1'b0; end else begin if (po_cnt_dec) begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b1; end else begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b0; end if (po_cnt_inc) begin po_stg2_c_incdec <= #TCQ 1'b1; po_en_stg2_c <= #TCQ 1'b1; end else begin po_stg2_c_incdec <= #TCQ 1'b0; po_en_stg2_c <= #TCQ 1'b0; end end end // delay counter to count 2 cycles // Increment coarse taps by 2 for all control byte lanes // to mitigate late writes always @(posedge clk) begin // load delay counter with init value if (rst || (tCK > 2500) || (SIM_CAL_OPTION == "FAST_CAL")) delay_cnt_r <= #TCQ 'd0; else if ((delaydec_cnt_r > 6'd0) ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1))) delay_cnt_r <= #TCQ 'd1; else if (po_cnt_inc && (delay_cnt_r > 6'd0)) delay_cnt_r <= #TCQ delay_cnt_r - 1; end // delay counter to count TAP_DEC cycles always @(posedge clk) begin // load delay counter with init value of TAP_DEC if (rst || ~cmd_delay_start ||((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1))) delaydec_cnt_r <= #TCQ TAP_DEC; else if (po_cnt_dec && (delaydec_cnt_r > 6'd0)) delaydec_cnt_r <= #TCQ delaydec_cnt_r - 1; end //ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle //This ensures all ctrl byte lanes have had their output phase shifted. always @(posedge clk) begin if (rst || ~cmd_delay_start ) ctl_lane_cnt <= #TCQ 6'b0; else if (~delay_dec_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delaydec_cnt_r == 6'd1)) ctl_lane_cnt <= #TCQ ctl_lane_cnt; else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0)) ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; end // All control lanes have decremented to 31 fine taps from 46 always @(posedge clk) begin if (rst || ~cmd_delay_start) begin delay_dec_done <= #TCQ 1'b0; end else if (((TAP_CNT == 0) && (TAP_DEC == 0)) || ((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0) && (ctl_lane_cnt == N_CTL_LANES-1))) begin delay_dec_done <= #TCQ 1'b1; end end always @(posedge clk) begin delay_done_r1 <= #TCQ delay_dec_done; delay_done_r2 <= #TCQ delay_done_r1; delay_done_r3 <= #TCQ delay_done_r2; delay_done_r4 <= #TCQ delay_done_r3; end endmodule
//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_ck_addr_cmd_delay.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Shift CK/Address/Commands/Controls //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay # ( parameter TCQ = 100, parameter tCK = 3636, parameter DQS_CNT_WIDTH = 3, parameter N_CTL_LANES = 3, parameter SIM_CAL_OPTION = "NONE" ) ( input clk, input rst, // Start only after PO_CIRC_BUF_DELAY decremented input cmd_delay_start, // Control lane being shifted using Phaser_Out fine delay taps output reg [N_CTL_LANES-1:0] ctl_lane_cnt, // Inc/dec Phaser_Out fine delay line output reg po_stg2_f_incdec, output reg po_en_stg2_f, output reg po_stg2_c_incdec, output reg po_en_stg2_c, // Completed delaying CK/Address/Commands/Controls output po_ck_addr_cmd_delay_done ); localparam TAP_CNT_LIMIT = 63; //Calculate the tap resolution of the PHASER based on the clock period localparam FREQ_REF_DIV = (tCK > 5000 ? 4 : tCK > 2500 ? 2 : 1); localparam integer PHASER_TAP_RES = ((tCK/2)/64); // Determine whether 300 ps or 350 ps delay required localparam CALC_TAP_CNT = (tCK >= 1250) ? 350 : 300; // Determine the number of Phaser_Out taps required to delay by 300 ps // 300 ps is the PCB trace uncertainty between CK and DQS byte groups // Increment control byte lanes localparam TAP_CNT = 0; //localparam TAP_CNT = (CALC_TAP_CNT + PHASER_TAP_RES - 1)/PHASER_TAP_RES; //Decrement control byte lanes localparam TAP_DEC = (SIM_CAL_OPTION == "FAST_CAL") ? 0 : 29; reg delay_dec_done; reg delay_done_r1; reg delay_done_r2; reg delay_done_r3; reg delay_done_r4 /* synthesis syn_maxfan = 10 */; reg [5:0] delay_cnt_r; reg [5:0] delaydec_cnt_r; reg po_cnt_inc; reg po_cnt_dec; reg [3:0] wait_cnt_r; assign po_ck_addr_cmd_delay_done = ((TAP_CNT == 0) && (TAP_DEC == 0)) ? 1'b1 : delay_done_r4; always @(posedge clk) begin if (rst || po_cnt_dec || po_cnt_inc) wait_cnt_r <= #TCQ 'd8; else if (cmd_delay_start && (wait_cnt_r > 'd0)) wait_cnt_r <= #TCQ wait_cnt_r - 1; end always @(posedge clk) begin if (rst || (delaydec_cnt_r > 6'd0) || (delay_cnt_r == 'd0) || (TAP_DEC == 0)) po_cnt_inc <= #TCQ 1'b0; else if ((delay_cnt_r > 'd0) && (wait_cnt_r == 'd1)) po_cnt_inc <= #TCQ 1'b1; else po_cnt_inc <= #TCQ 1'b0; end //Tap decrement always @(posedge clk) begin if (rst || (delaydec_cnt_r == 'd0)) po_cnt_dec <= #TCQ 1'b0; else if (cmd_delay_start && (delaydec_cnt_r > 'd0) && (wait_cnt_r == 'd1)) po_cnt_dec <= #TCQ 1'b1; else po_cnt_dec <= #TCQ 1'b0; end //po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane //the alignment is started once the always @(posedge clk) begin if (rst) begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b0; po_stg2_c_incdec <= #TCQ 1'b0; po_en_stg2_c <= #TCQ 1'b0; end else begin if (po_cnt_dec) begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b1; end else begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b0; end if (po_cnt_inc) begin po_stg2_c_incdec <= #TCQ 1'b1; po_en_stg2_c <= #TCQ 1'b1; end else begin po_stg2_c_incdec <= #TCQ 1'b0; po_en_stg2_c <= #TCQ 1'b0; end end end // delay counter to count 2 cycles // Increment coarse taps by 2 for all control byte lanes // to mitigate late writes always @(posedge clk) begin // load delay counter with init value if (rst || (tCK > 2500) || (SIM_CAL_OPTION == "FAST_CAL")) delay_cnt_r <= #TCQ 'd0; else if ((delaydec_cnt_r > 6'd0) ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1))) delay_cnt_r <= #TCQ 'd1; else if (po_cnt_inc && (delay_cnt_r > 6'd0)) delay_cnt_r <= #TCQ delay_cnt_r - 1; end // delay counter to count TAP_DEC cycles always @(posedge clk) begin // load delay counter with init value of TAP_DEC if (rst || ~cmd_delay_start ||((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1))) delaydec_cnt_r <= #TCQ TAP_DEC; else if (po_cnt_dec && (delaydec_cnt_r > 6'd0)) delaydec_cnt_r <= #TCQ delaydec_cnt_r - 1; end //ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle //This ensures all ctrl byte lanes have had their output phase shifted. always @(posedge clk) begin if (rst || ~cmd_delay_start ) ctl_lane_cnt <= #TCQ 6'b0; else if (~delay_dec_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delaydec_cnt_r == 6'd1)) ctl_lane_cnt <= #TCQ ctl_lane_cnt; else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0)) ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; end // All control lanes have decremented to 31 fine taps from 46 always @(posedge clk) begin if (rst || ~cmd_delay_start) begin delay_dec_done <= #TCQ 1'b0; end else if (((TAP_CNT == 0) && (TAP_DEC == 0)) || ((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0) && (ctl_lane_cnt == N_CTL_LANES-1))) begin delay_dec_done <= #TCQ 1'b1; end end always @(posedge clk) begin delay_done_r1 <= #TCQ delay_dec_done; delay_done_r2 <= #TCQ delay_done_r1; delay_done_r3 <= #TCQ delay_done_r2; delay_done_r4 <= #TCQ delay_done_r3; end endmodule
//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_ck_addr_cmd_delay.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Shift CK/Address/Commands/Controls //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay # ( parameter TCQ = 100, parameter tCK = 3636, parameter DQS_CNT_WIDTH = 3, parameter N_CTL_LANES = 3, parameter SIM_CAL_OPTION = "NONE" ) ( input clk, input rst, // Start only after PO_CIRC_BUF_DELAY decremented input cmd_delay_start, // Control lane being shifted using Phaser_Out fine delay taps output reg [N_CTL_LANES-1:0] ctl_lane_cnt, // Inc/dec Phaser_Out fine delay line output reg po_stg2_f_incdec, output reg po_en_stg2_f, output reg po_stg2_c_incdec, output reg po_en_stg2_c, // Completed delaying CK/Address/Commands/Controls output po_ck_addr_cmd_delay_done ); localparam TAP_CNT_LIMIT = 63; //Calculate the tap resolution of the PHASER based on the clock period localparam FREQ_REF_DIV = (tCK > 5000 ? 4 : tCK > 2500 ? 2 : 1); localparam integer PHASER_TAP_RES = ((tCK/2)/64); // Determine whether 300 ps or 350 ps delay required localparam CALC_TAP_CNT = (tCK >= 1250) ? 350 : 300; // Determine the number of Phaser_Out taps required to delay by 300 ps // 300 ps is the PCB trace uncertainty between CK and DQS byte groups // Increment control byte lanes localparam TAP_CNT = 0; //localparam TAP_CNT = (CALC_TAP_CNT + PHASER_TAP_RES - 1)/PHASER_TAP_RES; //Decrement control byte lanes localparam TAP_DEC = (SIM_CAL_OPTION == "FAST_CAL") ? 0 : 29; reg delay_dec_done; reg delay_done_r1; reg delay_done_r2; reg delay_done_r3; reg delay_done_r4 /* synthesis syn_maxfan = 10 */; reg [5:0] delay_cnt_r; reg [5:0] delaydec_cnt_r; reg po_cnt_inc; reg po_cnt_dec; reg [3:0] wait_cnt_r; assign po_ck_addr_cmd_delay_done = ((TAP_CNT == 0) && (TAP_DEC == 0)) ? 1'b1 : delay_done_r4; always @(posedge clk) begin if (rst || po_cnt_dec || po_cnt_inc) wait_cnt_r <= #TCQ 'd8; else if (cmd_delay_start && (wait_cnt_r > 'd0)) wait_cnt_r <= #TCQ wait_cnt_r - 1; end always @(posedge clk) begin if (rst || (delaydec_cnt_r > 6'd0) || (delay_cnt_r == 'd0) || (TAP_DEC == 0)) po_cnt_inc <= #TCQ 1'b0; else if ((delay_cnt_r > 'd0) && (wait_cnt_r == 'd1)) po_cnt_inc <= #TCQ 1'b1; else po_cnt_inc <= #TCQ 1'b0; end //Tap decrement always @(posedge clk) begin if (rst || (delaydec_cnt_r == 'd0)) po_cnt_dec <= #TCQ 1'b0; else if (cmd_delay_start && (delaydec_cnt_r > 'd0) && (wait_cnt_r == 'd1)) po_cnt_dec <= #TCQ 1'b1; else po_cnt_dec <= #TCQ 1'b0; end //po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane //the alignment is started once the always @(posedge clk) begin if (rst) begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b0; po_stg2_c_incdec <= #TCQ 1'b0; po_en_stg2_c <= #TCQ 1'b0; end else begin if (po_cnt_dec) begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b1; end else begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b0; end if (po_cnt_inc) begin po_stg2_c_incdec <= #TCQ 1'b1; po_en_stg2_c <= #TCQ 1'b1; end else begin po_stg2_c_incdec <= #TCQ 1'b0; po_en_stg2_c <= #TCQ 1'b0; end end end // delay counter to count 2 cycles // Increment coarse taps by 2 for all control byte lanes // to mitigate late writes always @(posedge clk) begin // load delay counter with init value if (rst || (tCK > 2500) || (SIM_CAL_OPTION == "FAST_CAL")) delay_cnt_r <= #TCQ 'd0; else if ((delaydec_cnt_r > 6'd0) ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1))) delay_cnt_r <= #TCQ 'd1; else if (po_cnt_inc && (delay_cnt_r > 6'd0)) delay_cnt_r <= #TCQ delay_cnt_r - 1; end // delay counter to count TAP_DEC cycles always @(posedge clk) begin // load delay counter with init value of TAP_DEC if (rst || ~cmd_delay_start ||((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1))) delaydec_cnt_r <= #TCQ TAP_DEC; else if (po_cnt_dec && (delaydec_cnt_r > 6'd0)) delaydec_cnt_r <= #TCQ delaydec_cnt_r - 1; end //ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle //This ensures all ctrl byte lanes have had their output phase shifted. always @(posedge clk) begin if (rst || ~cmd_delay_start ) ctl_lane_cnt <= #TCQ 6'b0; else if (~delay_dec_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delaydec_cnt_r == 6'd1)) ctl_lane_cnt <= #TCQ ctl_lane_cnt; else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0)) ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; end // All control lanes have decremented to 31 fine taps from 46 always @(posedge clk) begin if (rst || ~cmd_delay_start) begin delay_dec_done <= #TCQ 1'b0; end else if (((TAP_CNT == 0) && (TAP_DEC == 0)) || ((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0) && (ctl_lane_cnt == N_CTL_LANES-1))) begin delay_dec_done <= #TCQ 1'b1; end end always @(posedge clk) begin delay_done_r1 <= #TCQ delay_dec_done; delay_done_r2 <= #TCQ delay_done_r1; delay_done_r3 <= #TCQ delay_done_r2; delay_done_r4 <= #TCQ delay_done_r3; end endmodule
//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ecc_merge_enc.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ecc_merge_enc #( parameter TCQ = 100, parameter PAYLOAD_WIDTH = 64, parameter CODE_WIDTH = 72, parameter DATA_BUF_ADDR_WIDTH = 4, parameter DATA_BUF_OFFSET_WIDTH = 1, parameter DATA_WIDTH = 64, parameter DQ_WIDTH = 72, parameter ECC_WIDTH = 8, parameter nCK_PER_CLK = 4 ) ( /*AUTOARG*/ // Outputs mc_wrdata, mc_wrdata_mask, // Inputs clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc ); input clk; input rst; input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data; input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask; input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data; reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r; reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r; reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r; always @(posedge clk) wr_data_r <= #TCQ wr_data; always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask; always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data; // Merge new data with memory read data. wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data; genvar h; genvar i; generate for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer for (i=0; i<DATA_WIDTH/8; i=i+1) begin : merge_data_inner assign merged_data[h*PAYLOAD_WIDTH+i*8+:8] = wr_data_mask[h*DATA_WIDTH/8+i] ? rd_merge_data[h*DATA_WIDTH+i*8+:8] : wr_data[h*PAYLOAD_WIDTH+i*8+:8]; end if (PAYLOAD_WIDTH > DATA_WIDTH) assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]= wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]; end endgenerate // Generate ECC and overlay onto mc_wrdata. input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; input [2*nCK_PER_CLK-1:0] raw_not_ecc; reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r; always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc; output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata; reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c; genvar j; integer k; generate for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] = {{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}}, merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]}; for (k=0; k<ECC_WIDTH; k=k+1) if (~raw_not_ecc_r[j]) mc_wrdata_c[j*DQ_WIDTH+CODE_WIDTH-k-1] = ^(merged_data[j*PAYLOAD_WIDTH+:DATA_WIDTH] & h_rows[k*CODE_WIDTH+:DATA_WIDTH]); end end endgenerate always @(posedge clk) mc_wrdata <= mc_wrdata_c; // Set all DRAM masks to zero. output wire[2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask; assign mc_wrdata_mask = {2*nCK_PER_CLK*DQ_WIDTH/8{1'b0}}; endmodule
//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ecc_merge_enc.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ecc_merge_enc #( parameter TCQ = 100, parameter PAYLOAD_WIDTH = 64, parameter CODE_WIDTH = 72, parameter DATA_BUF_ADDR_WIDTH = 4, parameter DATA_BUF_OFFSET_WIDTH = 1, parameter DATA_WIDTH = 64, parameter DQ_WIDTH = 72, parameter ECC_WIDTH = 8, parameter nCK_PER_CLK = 4 ) ( /*AUTOARG*/ // Outputs mc_wrdata, mc_wrdata_mask, // Inputs clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc ); input clk; input rst; input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data; input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask; input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data; reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r; reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r; reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r; always @(posedge clk) wr_data_r <= #TCQ wr_data; always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask; always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data; // Merge new data with memory read data. wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data; genvar h; genvar i; generate for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer for (i=0; i<DATA_WIDTH/8; i=i+1) begin : merge_data_inner assign merged_data[h*PAYLOAD_WIDTH+i*8+:8] = wr_data_mask[h*DATA_WIDTH/8+i] ? rd_merge_data[h*DATA_WIDTH+i*8+:8] : wr_data[h*PAYLOAD_WIDTH+i*8+:8]; end if (PAYLOAD_WIDTH > DATA_WIDTH) assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]= wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]; end endgenerate // Generate ECC and overlay onto mc_wrdata. input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; input [2*nCK_PER_CLK-1:0] raw_not_ecc; reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r; always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc; output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata; reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c; genvar j; integer k; generate for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] = {{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}}, merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]}; for (k=0; k<ECC_WIDTH; k=k+1) if (~raw_not_ecc_r[j]) mc_wrdata_c[j*DQ_WIDTH+CODE_WIDTH-k-1] = ^(merged_data[j*PAYLOAD_WIDTH+:DATA_WIDTH] & h_rows[k*CODE_WIDTH+:DATA_WIDTH]); end end endgenerate always @(posedge clk) mc_wrdata <= mc_wrdata_c; // Set all DRAM masks to zero. output wire[2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask; assign mc_wrdata_mask = {2*nCK_PER_CLK*DQ_WIDTH/8{1'b0}}; endmodule
//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ecc_merge_enc.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ecc_merge_enc #( parameter TCQ = 100, parameter PAYLOAD_WIDTH = 64, parameter CODE_WIDTH = 72, parameter DATA_BUF_ADDR_WIDTH = 4, parameter DATA_BUF_OFFSET_WIDTH = 1, parameter DATA_WIDTH = 64, parameter DQ_WIDTH = 72, parameter ECC_WIDTH = 8, parameter nCK_PER_CLK = 4 ) ( /*AUTOARG*/ // Outputs mc_wrdata, mc_wrdata_mask, // Inputs clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc ); input clk; input rst; input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data; input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask; input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data; reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r; reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r; reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r; always @(posedge clk) wr_data_r <= #TCQ wr_data; always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask; always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data; // Merge new data with memory read data. wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data; genvar h; genvar i; generate for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer for (i=0; i<DATA_WIDTH/8; i=i+1) begin : merge_data_inner assign merged_data[h*PAYLOAD_WIDTH+i*8+:8] = wr_data_mask[h*DATA_WIDTH/8+i] ? rd_merge_data[h*DATA_WIDTH+i*8+:8] : wr_data[h*PAYLOAD_WIDTH+i*8+:8]; end if (PAYLOAD_WIDTH > DATA_WIDTH) assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]= wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]; end endgenerate // Generate ECC and overlay onto mc_wrdata. input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; input [2*nCK_PER_CLK-1:0] raw_not_ecc; reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r; always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc; output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata; reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c; genvar j; integer k; generate for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] = {{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}}, merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]}; for (k=0; k<ECC_WIDTH; k=k+1) if (~raw_not_ecc_r[j]) mc_wrdata_c[j*DQ_WIDTH+CODE_WIDTH-k-1] = ^(merged_data[j*PAYLOAD_WIDTH+:DATA_WIDTH] & h_rows[k*CODE_WIDTH+:DATA_WIDTH]); end end endgenerate always @(posedge clk) mc_wrdata <= mc_wrdata_c; // Set all DRAM masks to zero. output wire[2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask; assign mc_wrdata_mask = {2*nCK_PER_CLK*DQ_WIDTH/8{1'b0}}; endmodule
//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : bank_queue.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Bank machine queue controller. // // Bank machines are always associated with a queue. When the system is // idle, all bank machines are in the idle queue. As requests are // received, the bank machine at the head of the idle queue accepts // the request, removes itself from the idle queue and places itself // in a queue associated with the rank-bank of the new request. // // If the new request is to an idle rank-bank, a new queue is created // for that rank-bank. If the rank-bank is not idle, then the new // request is added to the end of the existing rank-bank queue. // // When the head of the idle queue accepts a new request, all other // bank machines move down one in the idle queue. When the idle queue // is empty, the memory interface deasserts its accept signal. // // When new requests are received, the first step is to classify them // as to whether the request targets an already open rank-bank, and if // so, does the new request also hit on the already open page? As mentioned // above, a new request places itself in the existing queue for a // rank-bank hit. If it is also detected that the last entry in the // existing rank-bank queue has the same page, then the current tail // sets a bit telling itself to pass the open row when the column // command is issued. The "passee" knows its in the head minus one // position and hence takes control of the rank-bank. // // Requests are retired out of order to optimize DRAM array resources. // However it is required that the user cannot "observe" this out of // order processing as a data corruption. An ordering queue is // used to enforce some ordering rules. As controlled by a paramter, // there can be no ordering (RELAXED), ordering of writes only (NORM), and // strict (STRICT) ordering whereby input request ordering is // strictly adhered to. // // Note that ordering applies only to column commands. Row commands // such as activate and precharge are allowed to proceed in any order // with the proviso that within a rank-bank row commands are processed in // the request order. // // When a bank machine accepts a new request, it looks at the ordering // mode. If no ordering, nothing is done. If strict ordering, then // it always places itself at the end of the ordering queue. If "normal" // or write ordering, the row machine places itself in the ordering // queue only if the new request is a write. The bank state machine // looks at the ordering queue, and will only issue a column // command when it sees itself at the head of the ordering queue. // // When a bank machine has completed its request, it must re-enter the // idle queue. This is done by setting the idle_r bit, and setting q_entry_r // to the idle count. // // There are several situations where more than one bank machine // will enter the idle queue simultaneously. If two or more // simply use the idle count to place themselves in the idle queue, multiple // bank machines will end up at the same location in the idle queue, which // is illegal. // // Based on the bank machine instance numbers, a count is made of // the number of bank machines entering idle "below" this instance. This // number is added to the idle count to compute the location in // idle queue. // // There is also a single bit computed that says there were bank machines // entering the idle queue "above" this instance. This is used to // compute the tail bit. // // The word "queue" is used frequently to describe the behavior of the // bank_queue block. In reality, there are no queues in the ordinary sense. // As instantiated in this block, each bank machine has a q_entry_r number. // This number represents the position of the bank machine in its current // queue. At any given time, a bank machine may be in the idle queue, // one of the dynamic rank-bank queues, or a single entry manitenance queue. // A complete description of which queue a bank machine is currently in is // given by idle_r, its rank-bank, mainteance status and its q_entry_r number. // // DRAM refresh and ZQ have a private single entry queue/channel. However, // when a refresh request is made, it must be injected into the main queue // properly. At the time of injection, the refresh rank is compared against // all entryies in the queue. For those that match, if timing allows, and // they are the tail of the rank-bank queue, then the auto_pre bit is set. // Otherwise precharge is in progress. This results in a fully precharged // rank. // // At the time of injection, the refresh channel builds a bit // vector of queue entries that hit on the refresh rank. Once all // of these entries finish, the refresh is forced in at the row arbiter. // // New requests that come after the refresh request will notice that // a refresh is in progress for their rank and wait for the refresh // to finish before attempting to arbitrate to send an activate. // // Injection of a refresh sets the q_has_rd bit for all queues hitting // on the refresh rank. This insures a starved write request will not // indefinitely hold off a refresh. // // Periodic reads are required to compare themselves against requests // that are in progress. Adding a unique compare channel for this // is not worthwhile. Periodic read requests inhibit the accept // signal and override any new request that might be trying to // enter the queue. // // Once a periodic read has entered the queue it is nearly indistinguishable // from a normal read request. The req_periodic_rd_r bit is set for // queue entry. This signal is used to inhibit the rd_data_en signal. `timescale 1ps/1ps `define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1) module mig_7series_v2_3_bank_queue # ( parameter TCQ = 100, parameter BM_CNT_WIDTH = 2, parameter nBANK_MACHS = 4, parameter ORDERING = "NORM", parameter ID = 0 ) (/*AUTOARG*/ // Outputs head_r, tail_r, idle_ns, idle_r, pass_open_bank_ns, pass_open_bank_r, auto_pre_r, bm_end, passing_open_bank, ordered_issued, ordered_r, order_q_zero, rcv_open_bank, rb_hit_busies_r, q_has_rd, q_has_priority, wait_for_maint_r, // Inputs clk, rst, accept_internal_r, use_addr, periodic_rd_ack_r, bm_end_in, idle_cnt, rb_hit_busy_cnt, accept_req, rb_hit_busy_r, maint_idle, maint_hit, row_hit_r, pre_wait_r, allow_auto_pre, sending_col, bank_wait_in_progress, precharge_bm_end, req_wr_r, rd_wr_r, adv_order_q, order_cnt, rb_hit_busy_ns_in, passing_open_bank_in, was_wr, maint_req_r, was_priority ); localparam ZERO = 0; localparam ONE = 1; localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH]; localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH]; input clk; input rst; // Decide if this bank machine should accept a new request. reg idle_r_lcl; reg head_r_lcl; input accept_internal_r; wire bm_ready = idle_r_lcl && head_r_lcl && accept_internal_r; // Accept request in this bank machine. Could be maintenance or // regular request. input use_addr; input periodic_rd_ack_r; wire accept_this_bm = bm_ready && (use_addr || periodic_rd_ack_r); // Multiple machines may enter the idle queue in a single state. // Based on bank machine instance number, compute how many // bank machines with lower instance numbers are entering // the idle queue. input [(nBANK_MACHS*2)-1:0] bm_end_in; reg [BM_CNT_WIDTH-1:0] idlers_below; integer i; always @(/*AS*/bm_end_in) begin idlers_below = BM_CNT_ZERO; for (i=0; i<ID; i=i+1) idlers_below = idlers_below + bm_end_in[i]; end reg idlers_above; always @(/*AS*/bm_end_in) begin idlers_above = 1'b0; for (i=ID+1; i<ID+nBANK_MACHS; i=i+1) idlers_above = idlers_above || bm_end_in[i]; end `ifdef MC_SVA bm_end_and_idlers_above: cover property (@(posedge clk) (~rst && bm_end && idlers_above)); bm_end_and_idlers_below: cover property (@(posedge clk) (~rst && bm_end && |idlers_below)); `endif // Compute the q_entry number. input [BM_CNT_WIDTH-1:0] idle_cnt; input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; input accept_req; wire bm_end_lcl; reg adv_queue = 1'b0; reg [BM_CNT_WIDTH-1:0] q_entry_r; reg [BM_CNT_WIDTH-1:0] q_entry_ns; wire [BM_CNT_WIDTH-1:0] temp; // always @(/*AS*/accept_req or accept_this_bm or adv_queue // or bm_end_lcl or idle_cnt or idle_r_lcl or idlers_below // or q_entry_r or rb_hit_busy_cnt /*or rst*/) begin //// if (rst) q_entry_ns = ID[BM_CNT_WIDTH-1:0]; //// else begin // q_entry_ns = q_entry_r; // if ((~idle_r_lcl && adv_queue) || // (idle_r_lcl && accept_req && ~accept_this_bm)) // q_entry_ns = q_entry_r - BM_CNT_ONE; // if (accept_this_bm) //// q_entry_ns = rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO); // q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO); // if (bm_end_lcl) begin // q_entry_ns = idle_cnt + idlers_below; // if (accept_req) q_entry_ns = q_entry_ns - BM_CNT_ONE; //// end // end // end assign temp = idle_cnt + idlers_below; always @ (*) begin if (accept_req & bm_end_lcl) q_entry_ns = temp - BM_CNT_ONE; else if (bm_end_lcl) q_entry_ns = temp; else if (accept_this_bm) q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO); else if ((!idle_r_lcl & adv_queue) | (idle_r_lcl & accept_req & !accept_this_bm)) q_entry_ns = q_entry_r - BM_CNT_ONE; else q_entry_ns = q_entry_r; end always @(posedge clk) if (rst) q_entry_r <= #TCQ ID[BM_CNT_WIDTH-1:0]; else q_entry_r <= #TCQ q_entry_ns; // Determine if this entry is the head of its queue. reg head_ns; always @(/*AS*/accept_req or accept_this_bm or adv_queue or bm_end_lcl or head_r_lcl or idle_cnt or idle_r_lcl or idlers_below or q_entry_r or rb_hit_busy_cnt or rst) begin if (rst) head_ns = ~|ID[BM_CNT_WIDTH-1:0]; else begin head_ns = head_r_lcl; if (accept_this_bm) head_ns = ~|(rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO)); if ((~idle_r_lcl && adv_queue) || (idle_r_lcl && accept_req && ~accept_this_bm)) head_ns = ~|(q_entry_r - BM_CNT_ONE); if (bm_end_lcl) begin head_ns = ~|(idle_cnt - (accept_req ? BM_CNT_ONE : BM_CNT_ZERO)) && ~|idlers_below; end end end always @(posedge clk) head_r_lcl <= #TCQ head_ns; output wire head_r; assign head_r = head_r_lcl; // Determine if this entry is the tail of its queue. Note that // an entry can be both head and tail. input rb_hit_busy_r; reg tail_r_lcl = 1'b1; generate if (nBANK_MACHS > 1) begin : compute_tail reg tail_ns; always @(accept_req or accept_this_bm or bm_end_in or bm_end_lcl or idle_r_lcl or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin if (rst) tail_ns = (ID == nBANK_MACHS); // The order of the statements below is important in the case where // another bank machine is retiring and this bank machine is accepting. else begin tail_ns = tail_r_lcl; if ((accept_req && rb_hit_busy_r) || (|bm_end_in[`BM_SHARED_BV] && idle_r_lcl)) tail_ns = 1'b0; if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1; end end always @(posedge clk) tail_r_lcl <= #TCQ tail_ns; end // if (nBANK_MACHS > 1) endgenerate output wire tail_r; assign tail_r = tail_r_lcl; wire clear_req = bm_end_lcl || rst; // Is this entry in the idle queue? reg idle_ns_lcl; always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin idle_ns_lcl = idle_r_lcl; if (accept_this_bm) idle_ns_lcl = 1'b0; if (clear_req) idle_ns_lcl = 1'b1; end always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl; output wire idle_ns; assign idle_ns = idle_ns_lcl; output wire idle_r; assign idle_r = idle_r_lcl; // Maintenance hitting on this active bank machine is in progress. input maint_idle; input maint_hit; wire maint_hit_this_bm = ~maint_idle && maint_hit; // Does new request hit on this bank machine while it is able to pass the // open bank? input row_hit_r; input pre_wait_r; wire pass_open_bank_eligible = tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r; // Set pass open bank bit, but not if request preceded active maintenance. reg wait_for_maint_r_lcl; reg pass_open_bank_r_lcl; wire pass_open_bank_ns_lcl = ~clear_req && (pass_open_bank_r_lcl || (accept_req && pass_open_bank_eligible && (~maint_hit_this_bm || wait_for_maint_r_lcl))); always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl; output wire pass_open_bank_ns; assign pass_open_bank_ns = pass_open_bank_ns_lcl; output wire pass_open_bank_r; assign pass_open_bank_r = pass_open_bank_r_lcl; `ifdef MC_SVA pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns)); pass_open_bank_killed_by_maint: cover property (@(posedge clk) (~rst && accept_req && pass_open_bank_eligible && maint_hit_this_bm && ~wait_for_maint_r_lcl)); pass_open_bank_following_maint: cover property (@(posedge clk) (~rst && accept_req && pass_open_bank_eligible && maint_hit_this_bm && wait_for_maint_r_lcl)); `endif // Should the column command be sent with the auto precharge bit set? This // will happen when it is detected that next request is to a different row, // or the next reqest is the next request is refresh to this rank. reg auto_pre_r_lcl; reg auto_pre_ns; input allow_auto_pre; always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl or clear_req or maint_hit_this_bm or rb_hit_busy_r or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin auto_pre_ns = auto_pre_r_lcl; if (clear_req) auto_pre_ns = 1'b0; else if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r && (~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl))) auto_pre_ns = 1'b1; end always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns; output wire auto_pre_r; assign auto_pre_r = auto_pre_r_lcl; `ifdef MC_SVA auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns)); maint_triggers_auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns && ~auto_pre_r && row_hit_r)); `endif // Determine when the current request is finished. input sending_col; input req_wr_r; input rd_wr_r; wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r); input bank_wait_in_progress; input precharge_bm_end; reg pre_bm_end_r; wire pre_bm_end_ns = precharge_bm_end || (bank_wait_in_progress && pass_open_bank_ns_lcl); always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns; assign bm_end_lcl = pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl); output wire bm_end; assign bm_end = bm_end_lcl; // Determine that the open bank should be passed to the successor bank machine. reg pre_passing_open_bank_r; wire pre_passing_open_bank_ns = bank_wait_in_progress && pass_open_bank_ns_lcl; always @(posedge clk) pre_passing_open_bank_r <= #TCQ pre_passing_open_bank_ns; output wire passing_open_bank; assign passing_open_bank = pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl); reg ordered_ns; wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r)) && accept_this_bm; wire ordered_issued_lcl = sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) && ((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r)); output wire ordered_issued; assign ordered_issued = ordered_issued_lcl; reg ordered_r_lcl; always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst or set_order_q) begin if (rst) ordered_ns = 1'b0; else begin ordered_ns = ordered_r_lcl; // Should never see accept_this_bm and adv_order_q at the same time. if (set_order_q) ordered_ns = 1'b1; if (ordered_issued_lcl) ordered_ns = 1'b0; end end always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns; output wire ordered_r; assign ordered_r = ordered_r_lcl; // Figure out when to advance the ordering queue. input adv_order_q; input [BM_CNT_WIDTH-1:0] order_cnt; reg [BM_CNT_WIDTH-1:0] order_q_r; reg [BM_CNT_WIDTH-1:0] order_q_ns; always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst or set_order_q) begin order_q_ns = order_q_r; if (rst) order_q_ns = BM_CNT_ZERO; if (set_order_q) if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE; else order_q_ns = order_cnt; if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE; end always @(posedge clk) order_q_r <= #TCQ order_q_ns; output wire order_q_zero; assign order_q_zero = ~|order_q_r || (adv_order_q && (order_q_r == BM_CNT_ONE)) || ((ORDERING == "NORM") && rd_wr_r); // Keep track of which other bank machine are ahead of this one in a // rank-bank queue. This is necessary to know when to advance this bank // machine in the queue, and when to update bank state machine counter upon // passing a bank. input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in; reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}}; input [(nBANK_MACHS*2)-1:0] passing_open_bank_in; output reg rcv_open_bank = 1'b0; generate if (nBANK_MACHS > 1) begin : rb_hit_busies // The clear_vector resets bits in the rb_hit_busies vector as bank machines // completes requests. rst also resets all the bits. wire [nBANK_MACHS-2:0] clear_vector = ({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]); // As this bank machine takes on a new request, capture the vector of // which other bank machines are in the same queue. wire [`BM_SHARED_BV] rb_hit_busies_ns = ~clear_vector & (idle_ns_lcl ? rb_hit_busy_ns_in[`BM_SHARED_BV] : rb_hit_busies_r_lcl[`BM_SHARED_BV]); always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <= #TCQ rb_hit_busies_ns; // Compute when to advance this queue entry based on seeing other bank machines // in the same queue finish. always @(bm_end_in or rb_hit_busies_r_lcl) adv_queue = |(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]); // Decide when to receive an open bank based on knowing this bank machine is // one entry from the head, and a passing_open_bank hits on the // rb_hit_busies vector. always @(idle_r_lcl or passing_open_bank_in or q_entry_r or rb_hit_busies_r_lcl) rcv_open_bank = |(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV]) && (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl; end endgenerate output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; assign rb_hit_busies_r = rb_hit_busies_r_lcl; // Keep track if the queue this entry is in has priority content. input was_wr; input maint_req_r; reg q_has_rd_r; wire q_has_rd_ns = ~clear_req && (q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) || (maint_req_r && maint_hit && ~idle_r_lcl)); always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns; output wire q_has_rd; assign q_has_rd = q_has_rd_r; input was_priority; reg q_has_priority_r; wire q_has_priority_ns = ~clear_req && (q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority)); always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns; output wire q_has_priority; assign q_has_priority = q_has_priority_r; // Figure out if this entry should wait for maintenance to end. wire wait_for_maint_ns = ~rst && ~maint_idle && (wait_for_maint_r_lcl || (maint_hit && accept_this_bm)); always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns; output wire wait_for_maint_r; assign wait_for_maint_r = wait_for_maint_r_lcl; endmodule // bank_queue
//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : bank_queue.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Bank machine queue controller. // // Bank machines are always associated with a queue. When the system is // idle, all bank machines are in the idle queue. As requests are // received, the bank machine at the head of the idle queue accepts // the request, removes itself from the idle queue and places itself // in a queue associated with the rank-bank of the new request. // // If the new request is to an idle rank-bank, a new queue is created // for that rank-bank. If the rank-bank is not idle, then the new // request is added to the end of the existing rank-bank queue. // // When the head of the idle queue accepts a new request, all other // bank machines move down one in the idle queue. When the idle queue // is empty, the memory interface deasserts its accept signal. // // When new requests are received, the first step is to classify them // as to whether the request targets an already open rank-bank, and if // so, does the new request also hit on the already open page? As mentioned // above, a new request places itself in the existing queue for a // rank-bank hit. If it is also detected that the last entry in the // existing rank-bank queue has the same page, then the current tail // sets a bit telling itself to pass the open row when the column // command is issued. The "passee" knows its in the head minus one // position and hence takes control of the rank-bank. // // Requests are retired out of order to optimize DRAM array resources. // However it is required that the user cannot "observe" this out of // order processing as a data corruption. An ordering queue is // used to enforce some ordering rules. As controlled by a paramter, // there can be no ordering (RELAXED), ordering of writes only (NORM), and // strict (STRICT) ordering whereby input request ordering is // strictly adhered to. // // Note that ordering applies only to column commands. Row commands // such as activate and precharge are allowed to proceed in any order // with the proviso that within a rank-bank row commands are processed in // the request order. // // When a bank machine accepts a new request, it looks at the ordering // mode. If no ordering, nothing is done. If strict ordering, then // it always places itself at the end of the ordering queue. If "normal" // or write ordering, the row machine places itself in the ordering // queue only if the new request is a write. The bank state machine // looks at the ordering queue, and will only issue a column // command when it sees itself at the head of the ordering queue. // // When a bank machine has completed its request, it must re-enter the // idle queue. This is done by setting the idle_r bit, and setting q_entry_r // to the idle count. // // There are several situations where more than one bank machine // will enter the idle queue simultaneously. If two or more // simply use the idle count to place themselves in the idle queue, multiple // bank machines will end up at the same location in the idle queue, which // is illegal. // // Based on the bank machine instance numbers, a count is made of // the number of bank machines entering idle "below" this instance. This // number is added to the idle count to compute the location in // idle queue. // // There is also a single bit computed that says there were bank machines // entering the idle queue "above" this instance. This is used to // compute the tail bit. // // The word "queue" is used frequently to describe the behavior of the // bank_queue block. In reality, there are no queues in the ordinary sense. // As instantiated in this block, each bank machine has a q_entry_r number. // This number represents the position of the bank machine in its current // queue. At any given time, a bank machine may be in the idle queue, // one of the dynamic rank-bank queues, or a single entry manitenance queue. // A complete description of which queue a bank machine is currently in is // given by idle_r, its rank-bank, mainteance status and its q_entry_r number. // // DRAM refresh and ZQ have a private single entry queue/channel. However, // when a refresh request is made, it must be injected into the main queue // properly. At the time of injection, the refresh rank is compared against // all entryies in the queue. For those that match, if timing allows, and // they are the tail of the rank-bank queue, then the auto_pre bit is set. // Otherwise precharge is in progress. This results in a fully precharged // rank. // // At the time of injection, the refresh channel builds a bit // vector of queue entries that hit on the refresh rank. Once all // of these entries finish, the refresh is forced in at the row arbiter. // // New requests that come after the refresh request will notice that // a refresh is in progress for their rank and wait for the refresh // to finish before attempting to arbitrate to send an activate. // // Injection of a refresh sets the q_has_rd bit for all queues hitting // on the refresh rank. This insures a starved write request will not // indefinitely hold off a refresh. // // Periodic reads are required to compare themselves against requests // that are in progress. Adding a unique compare channel for this // is not worthwhile. Periodic read requests inhibit the accept // signal and override any new request that might be trying to // enter the queue. // // Once a periodic read has entered the queue it is nearly indistinguishable // from a normal read request. The req_periodic_rd_r bit is set for // queue entry. This signal is used to inhibit the rd_data_en signal. `timescale 1ps/1ps `define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1) module mig_7series_v2_3_bank_queue # ( parameter TCQ = 100, parameter BM_CNT_WIDTH = 2, parameter nBANK_MACHS = 4, parameter ORDERING = "NORM", parameter ID = 0 ) (/*AUTOARG*/ // Outputs head_r, tail_r, idle_ns, idle_r, pass_open_bank_ns, pass_open_bank_r, auto_pre_r, bm_end, passing_open_bank, ordered_issued, ordered_r, order_q_zero, rcv_open_bank, rb_hit_busies_r, q_has_rd, q_has_priority, wait_for_maint_r, // Inputs clk, rst, accept_internal_r, use_addr, periodic_rd_ack_r, bm_end_in, idle_cnt, rb_hit_busy_cnt, accept_req, rb_hit_busy_r, maint_idle, maint_hit, row_hit_r, pre_wait_r, allow_auto_pre, sending_col, bank_wait_in_progress, precharge_bm_end, req_wr_r, rd_wr_r, adv_order_q, order_cnt, rb_hit_busy_ns_in, passing_open_bank_in, was_wr, maint_req_r, was_priority ); localparam ZERO = 0; localparam ONE = 1; localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH]; localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH]; input clk; input rst; // Decide if this bank machine should accept a new request. reg idle_r_lcl; reg head_r_lcl; input accept_internal_r; wire bm_ready = idle_r_lcl && head_r_lcl && accept_internal_r; // Accept request in this bank machine. Could be maintenance or // regular request. input use_addr; input periodic_rd_ack_r; wire accept_this_bm = bm_ready && (use_addr || periodic_rd_ack_r); // Multiple machines may enter the idle queue in a single state. // Based on bank machine instance number, compute how many // bank machines with lower instance numbers are entering // the idle queue. input [(nBANK_MACHS*2)-1:0] bm_end_in; reg [BM_CNT_WIDTH-1:0] idlers_below; integer i; always @(/*AS*/bm_end_in) begin idlers_below = BM_CNT_ZERO; for (i=0; i<ID; i=i+1) idlers_below = idlers_below + bm_end_in[i]; end reg idlers_above; always @(/*AS*/bm_end_in) begin idlers_above = 1'b0; for (i=ID+1; i<ID+nBANK_MACHS; i=i+1) idlers_above = idlers_above || bm_end_in[i]; end `ifdef MC_SVA bm_end_and_idlers_above: cover property (@(posedge clk) (~rst && bm_end && idlers_above)); bm_end_and_idlers_below: cover property (@(posedge clk) (~rst && bm_end && |idlers_below)); `endif // Compute the q_entry number. input [BM_CNT_WIDTH-1:0] idle_cnt; input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; input accept_req; wire bm_end_lcl; reg adv_queue = 1'b0; reg [BM_CNT_WIDTH-1:0] q_entry_r; reg [BM_CNT_WIDTH-1:0] q_entry_ns; wire [BM_CNT_WIDTH-1:0] temp; // always @(/*AS*/accept_req or accept_this_bm or adv_queue // or bm_end_lcl or idle_cnt or idle_r_lcl or idlers_below // or q_entry_r or rb_hit_busy_cnt /*or rst*/) begin //// if (rst) q_entry_ns = ID[BM_CNT_WIDTH-1:0]; //// else begin // q_entry_ns = q_entry_r; // if ((~idle_r_lcl && adv_queue) || // (idle_r_lcl && accept_req && ~accept_this_bm)) // q_entry_ns = q_entry_r - BM_CNT_ONE; // if (accept_this_bm) //// q_entry_ns = rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO); // q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO); // if (bm_end_lcl) begin // q_entry_ns = idle_cnt + idlers_below; // if (accept_req) q_entry_ns = q_entry_ns - BM_CNT_ONE; //// end // end // end assign temp = idle_cnt + idlers_below; always @ (*) begin if (accept_req & bm_end_lcl) q_entry_ns = temp - BM_CNT_ONE; else if (bm_end_lcl) q_entry_ns = temp; else if (accept_this_bm) q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO); else if ((!idle_r_lcl & adv_queue) | (idle_r_lcl & accept_req & !accept_this_bm)) q_entry_ns = q_entry_r - BM_CNT_ONE; else q_entry_ns = q_entry_r; end always @(posedge clk) if (rst) q_entry_r <= #TCQ ID[BM_CNT_WIDTH-1:0]; else q_entry_r <= #TCQ q_entry_ns; // Determine if this entry is the head of its queue. reg head_ns; always @(/*AS*/accept_req or accept_this_bm or adv_queue or bm_end_lcl or head_r_lcl or idle_cnt or idle_r_lcl or idlers_below or q_entry_r or rb_hit_busy_cnt or rst) begin if (rst) head_ns = ~|ID[BM_CNT_WIDTH-1:0]; else begin head_ns = head_r_lcl; if (accept_this_bm) head_ns = ~|(rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO)); if ((~idle_r_lcl && adv_queue) || (idle_r_lcl && accept_req && ~accept_this_bm)) head_ns = ~|(q_entry_r - BM_CNT_ONE); if (bm_end_lcl) begin head_ns = ~|(idle_cnt - (accept_req ? BM_CNT_ONE : BM_CNT_ZERO)) && ~|idlers_below; end end end always @(posedge clk) head_r_lcl <= #TCQ head_ns; output wire head_r; assign head_r = head_r_lcl; // Determine if this entry is the tail of its queue. Note that // an entry can be both head and tail. input rb_hit_busy_r; reg tail_r_lcl = 1'b1; generate if (nBANK_MACHS > 1) begin : compute_tail reg tail_ns; always @(accept_req or accept_this_bm or bm_end_in or bm_end_lcl or idle_r_lcl or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin if (rst) tail_ns = (ID == nBANK_MACHS); // The order of the statements below is important in the case where // another bank machine is retiring and this bank machine is accepting. else begin tail_ns = tail_r_lcl; if ((accept_req && rb_hit_busy_r) || (|bm_end_in[`BM_SHARED_BV] && idle_r_lcl)) tail_ns = 1'b0; if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1; end end always @(posedge clk) tail_r_lcl <= #TCQ tail_ns; end // if (nBANK_MACHS > 1) endgenerate output wire tail_r; assign tail_r = tail_r_lcl; wire clear_req = bm_end_lcl || rst; // Is this entry in the idle queue? reg idle_ns_lcl; always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin idle_ns_lcl = idle_r_lcl; if (accept_this_bm) idle_ns_lcl = 1'b0; if (clear_req) idle_ns_lcl = 1'b1; end always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl; output wire idle_ns; assign idle_ns = idle_ns_lcl; output wire idle_r; assign idle_r = idle_r_lcl; // Maintenance hitting on this active bank machine is in progress. input maint_idle; input maint_hit; wire maint_hit_this_bm = ~maint_idle && maint_hit; // Does new request hit on this bank machine while it is able to pass the // open bank? input row_hit_r; input pre_wait_r; wire pass_open_bank_eligible = tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r; // Set pass open bank bit, but not if request preceded active maintenance. reg wait_for_maint_r_lcl; reg pass_open_bank_r_lcl; wire pass_open_bank_ns_lcl = ~clear_req && (pass_open_bank_r_lcl || (accept_req && pass_open_bank_eligible && (~maint_hit_this_bm || wait_for_maint_r_lcl))); always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl; output wire pass_open_bank_ns; assign pass_open_bank_ns = pass_open_bank_ns_lcl; output wire pass_open_bank_r; assign pass_open_bank_r = pass_open_bank_r_lcl; `ifdef MC_SVA pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns)); pass_open_bank_killed_by_maint: cover property (@(posedge clk) (~rst && accept_req && pass_open_bank_eligible && maint_hit_this_bm && ~wait_for_maint_r_lcl)); pass_open_bank_following_maint: cover property (@(posedge clk) (~rst && accept_req && pass_open_bank_eligible && maint_hit_this_bm && wait_for_maint_r_lcl)); `endif // Should the column command be sent with the auto precharge bit set? This // will happen when it is detected that next request is to a different row, // or the next reqest is the next request is refresh to this rank. reg auto_pre_r_lcl; reg auto_pre_ns; input allow_auto_pre; always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl or clear_req or maint_hit_this_bm or rb_hit_busy_r or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin auto_pre_ns = auto_pre_r_lcl; if (clear_req) auto_pre_ns = 1'b0; else if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r && (~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl))) auto_pre_ns = 1'b1; end always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns; output wire auto_pre_r; assign auto_pre_r = auto_pre_r_lcl; `ifdef MC_SVA auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns)); maint_triggers_auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns && ~auto_pre_r && row_hit_r)); `endif // Determine when the current request is finished. input sending_col; input req_wr_r; input rd_wr_r; wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r); input bank_wait_in_progress; input precharge_bm_end; reg pre_bm_end_r; wire pre_bm_end_ns = precharge_bm_end || (bank_wait_in_progress && pass_open_bank_ns_lcl); always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns; assign bm_end_lcl = pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl); output wire bm_end; assign bm_end = bm_end_lcl; // Determine that the open bank should be passed to the successor bank machine. reg pre_passing_open_bank_r; wire pre_passing_open_bank_ns = bank_wait_in_progress && pass_open_bank_ns_lcl; always @(posedge clk) pre_passing_open_bank_r <= #TCQ pre_passing_open_bank_ns; output wire passing_open_bank; assign passing_open_bank = pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl); reg ordered_ns; wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r)) && accept_this_bm; wire ordered_issued_lcl = sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) && ((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r)); output wire ordered_issued; assign ordered_issued = ordered_issued_lcl; reg ordered_r_lcl; always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst or set_order_q) begin if (rst) ordered_ns = 1'b0; else begin ordered_ns = ordered_r_lcl; // Should never see accept_this_bm and adv_order_q at the same time. if (set_order_q) ordered_ns = 1'b1; if (ordered_issued_lcl) ordered_ns = 1'b0; end end always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns; output wire ordered_r; assign ordered_r = ordered_r_lcl; // Figure out when to advance the ordering queue. input adv_order_q; input [BM_CNT_WIDTH-1:0] order_cnt; reg [BM_CNT_WIDTH-1:0] order_q_r; reg [BM_CNT_WIDTH-1:0] order_q_ns; always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst or set_order_q) begin order_q_ns = order_q_r; if (rst) order_q_ns = BM_CNT_ZERO; if (set_order_q) if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE; else order_q_ns = order_cnt; if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE; end always @(posedge clk) order_q_r <= #TCQ order_q_ns; output wire order_q_zero; assign order_q_zero = ~|order_q_r || (adv_order_q && (order_q_r == BM_CNT_ONE)) || ((ORDERING == "NORM") && rd_wr_r); // Keep track of which other bank machine are ahead of this one in a // rank-bank queue. This is necessary to know when to advance this bank // machine in the queue, and when to update bank state machine counter upon // passing a bank. input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in; reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}}; input [(nBANK_MACHS*2)-1:0] passing_open_bank_in; output reg rcv_open_bank = 1'b0; generate if (nBANK_MACHS > 1) begin : rb_hit_busies // The clear_vector resets bits in the rb_hit_busies vector as bank machines // completes requests. rst also resets all the bits. wire [nBANK_MACHS-2:0] clear_vector = ({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]); // As this bank machine takes on a new request, capture the vector of // which other bank machines are in the same queue. wire [`BM_SHARED_BV] rb_hit_busies_ns = ~clear_vector & (idle_ns_lcl ? rb_hit_busy_ns_in[`BM_SHARED_BV] : rb_hit_busies_r_lcl[`BM_SHARED_BV]); always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <= #TCQ rb_hit_busies_ns; // Compute when to advance this queue entry based on seeing other bank machines // in the same queue finish. always @(bm_end_in or rb_hit_busies_r_lcl) adv_queue = |(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]); // Decide when to receive an open bank based on knowing this bank machine is // one entry from the head, and a passing_open_bank hits on the // rb_hit_busies vector. always @(idle_r_lcl or passing_open_bank_in or q_entry_r or rb_hit_busies_r_lcl) rcv_open_bank = |(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV]) && (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl; end endgenerate output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; assign rb_hit_busies_r = rb_hit_busies_r_lcl; // Keep track if the queue this entry is in has priority content. input was_wr; input maint_req_r; reg q_has_rd_r; wire q_has_rd_ns = ~clear_req && (q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) || (maint_req_r && maint_hit && ~idle_r_lcl)); always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns; output wire q_has_rd; assign q_has_rd = q_has_rd_r; input was_priority; reg q_has_priority_r; wire q_has_priority_ns = ~clear_req && (q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority)); always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns; output wire q_has_priority; assign q_has_priority = q_has_priority_r; // Figure out if this entry should wait for maintenance to end. wire wait_for_maint_ns = ~rst && ~maint_idle && (wait_for_maint_r_lcl || (maint_hit && accept_this_bm)); always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns; output wire wait_for_maint_r; assign wait_for_maint_r = wait_for_maint_r_lcl; endmodule // bank_queue
//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : bank_queue.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Bank machine queue controller. // // Bank machines are always associated with a queue. When the system is // idle, all bank machines are in the idle queue. As requests are // received, the bank machine at the head of the idle queue accepts // the request, removes itself from the idle queue and places itself // in a queue associated with the rank-bank of the new request. // // If the new request is to an idle rank-bank, a new queue is created // for that rank-bank. If the rank-bank is not idle, then the new // request is added to the end of the existing rank-bank queue. // // When the head of the idle queue accepts a new request, all other // bank machines move down one in the idle queue. When the idle queue // is empty, the memory interface deasserts its accept signal. // // When new requests are received, the first step is to classify them // as to whether the request targets an already open rank-bank, and if // so, does the new request also hit on the already open page? As mentioned // above, a new request places itself in the existing queue for a // rank-bank hit. If it is also detected that the last entry in the // existing rank-bank queue has the same page, then the current tail // sets a bit telling itself to pass the open row when the column // command is issued. The "passee" knows its in the head minus one // position and hence takes control of the rank-bank. // // Requests are retired out of order to optimize DRAM array resources. // However it is required that the user cannot "observe" this out of // order processing as a data corruption. An ordering queue is // used to enforce some ordering rules. As controlled by a paramter, // there can be no ordering (RELAXED), ordering of writes only (NORM), and // strict (STRICT) ordering whereby input request ordering is // strictly adhered to. // // Note that ordering applies only to column commands. Row commands // such as activate and precharge are allowed to proceed in any order // with the proviso that within a rank-bank row commands are processed in // the request order. // // When a bank machine accepts a new request, it looks at the ordering // mode. If no ordering, nothing is done. If strict ordering, then // it always places itself at the end of the ordering queue. If "normal" // or write ordering, the row machine places itself in the ordering // queue only if the new request is a write. The bank state machine // looks at the ordering queue, and will only issue a column // command when it sees itself at the head of the ordering queue. // // When a bank machine has completed its request, it must re-enter the // idle queue. This is done by setting the idle_r bit, and setting q_entry_r // to the idle count. // // There are several situations where more than one bank machine // will enter the idle queue simultaneously. If two or more // simply use the idle count to place themselves in the idle queue, multiple // bank machines will end up at the same location in the idle queue, which // is illegal. // // Based on the bank machine instance numbers, a count is made of // the number of bank machines entering idle "below" this instance. This // number is added to the idle count to compute the location in // idle queue. // // There is also a single bit computed that says there were bank machines // entering the idle queue "above" this instance. This is used to // compute the tail bit. // // The word "queue" is used frequently to describe the behavior of the // bank_queue block. In reality, there are no queues in the ordinary sense. // As instantiated in this block, each bank machine has a q_entry_r number. // This number represents the position of the bank machine in its current // queue. At any given time, a bank machine may be in the idle queue, // one of the dynamic rank-bank queues, or a single entry manitenance queue. // A complete description of which queue a bank machine is currently in is // given by idle_r, its rank-bank, mainteance status and its q_entry_r number. // // DRAM refresh and ZQ have a private single entry queue/channel. However, // when a refresh request is made, it must be injected into the main queue // properly. At the time of injection, the refresh rank is compared against // all entryies in the queue. For those that match, if timing allows, and // they are the tail of the rank-bank queue, then the auto_pre bit is set. // Otherwise precharge is in progress. This results in a fully precharged // rank. // // At the time of injection, the refresh channel builds a bit // vector of queue entries that hit on the refresh rank. Once all // of these entries finish, the refresh is forced in at the row arbiter. // // New requests that come after the refresh request will notice that // a refresh is in progress for their rank and wait for the refresh // to finish before attempting to arbitrate to send an activate. // // Injection of a refresh sets the q_has_rd bit for all queues hitting // on the refresh rank. This insures a starved write request will not // indefinitely hold off a refresh. // // Periodic reads are required to compare themselves against requests // that are in progress. Adding a unique compare channel for this // is not worthwhile. Periodic read requests inhibit the accept // signal and override any new request that might be trying to // enter the queue. // // Once a periodic read has entered the queue it is nearly indistinguishable // from a normal read request. The req_periodic_rd_r bit is set for // queue entry. This signal is used to inhibit the rd_data_en signal. `timescale 1ps/1ps `define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1) module mig_7series_v2_3_bank_queue # ( parameter TCQ = 100, parameter BM_CNT_WIDTH = 2, parameter nBANK_MACHS = 4, parameter ORDERING = "NORM", parameter ID = 0 ) (/*AUTOARG*/ // Outputs head_r, tail_r, idle_ns, idle_r, pass_open_bank_ns, pass_open_bank_r, auto_pre_r, bm_end, passing_open_bank, ordered_issued, ordered_r, order_q_zero, rcv_open_bank, rb_hit_busies_r, q_has_rd, q_has_priority, wait_for_maint_r, // Inputs clk, rst, accept_internal_r, use_addr, periodic_rd_ack_r, bm_end_in, idle_cnt, rb_hit_busy_cnt, accept_req, rb_hit_busy_r, maint_idle, maint_hit, row_hit_r, pre_wait_r, allow_auto_pre, sending_col, bank_wait_in_progress, precharge_bm_end, req_wr_r, rd_wr_r, adv_order_q, order_cnt, rb_hit_busy_ns_in, passing_open_bank_in, was_wr, maint_req_r, was_priority ); localparam ZERO = 0; localparam ONE = 1; localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH]; localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH]; input clk; input rst; // Decide if this bank machine should accept a new request. reg idle_r_lcl; reg head_r_lcl; input accept_internal_r; wire bm_ready = idle_r_lcl && head_r_lcl && accept_internal_r; // Accept request in this bank machine. Could be maintenance or // regular request. input use_addr; input periodic_rd_ack_r; wire accept_this_bm = bm_ready && (use_addr || periodic_rd_ack_r); // Multiple machines may enter the idle queue in a single state. // Based on bank machine instance number, compute how many // bank machines with lower instance numbers are entering // the idle queue. input [(nBANK_MACHS*2)-1:0] bm_end_in; reg [BM_CNT_WIDTH-1:0] idlers_below; integer i; always @(/*AS*/bm_end_in) begin idlers_below = BM_CNT_ZERO; for (i=0; i<ID; i=i+1) idlers_below = idlers_below + bm_end_in[i]; end reg idlers_above; always @(/*AS*/bm_end_in) begin idlers_above = 1'b0; for (i=ID+1; i<ID+nBANK_MACHS; i=i+1) idlers_above = idlers_above || bm_end_in[i]; end `ifdef MC_SVA bm_end_and_idlers_above: cover property (@(posedge clk) (~rst && bm_end && idlers_above)); bm_end_and_idlers_below: cover property (@(posedge clk) (~rst && bm_end && |idlers_below)); `endif // Compute the q_entry number. input [BM_CNT_WIDTH-1:0] idle_cnt; input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; input accept_req; wire bm_end_lcl; reg adv_queue = 1'b0; reg [BM_CNT_WIDTH-1:0] q_entry_r; reg [BM_CNT_WIDTH-1:0] q_entry_ns; wire [BM_CNT_WIDTH-1:0] temp; // always @(/*AS*/accept_req or accept_this_bm or adv_queue // or bm_end_lcl or idle_cnt or idle_r_lcl or idlers_below // or q_entry_r or rb_hit_busy_cnt /*or rst*/) begin //// if (rst) q_entry_ns = ID[BM_CNT_WIDTH-1:0]; //// else begin // q_entry_ns = q_entry_r; // if ((~idle_r_lcl && adv_queue) || // (idle_r_lcl && accept_req && ~accept_this_bm)) // q_entry_ns = q_entry_r - BM_CNT_ONE; // if (accept_this_bm) //// q_entry_ns = rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO); // q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO); // if (bm_end_lcl) begin // q_entry_ns = idle_cnt + idlers_below; // if (accept_req) q_entry_ns = q_entry_ns - BM_CNT_ONE; //// end // end // end assign temp = idle_cnt + idlers_below; always @ (*) begin if (accept_req & bm_end_lcl) q_entry_ns = temp - BM_CNT_ONE; else if (bm_end_lcl) q_entry_ns = temp; else if (accept_this_bm) q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO); else if ((!idle_r_lcl & adv_queue) | (idle_r_lcl & accept_req & !accept_this_bm)) q_entry_ns = q_entry_r - BM_CNT_ONE; else q_entry_ns = q_entry_r; end always @(posedge clk) if (rst) q_entry_r <= #TCQ ID[BM_CNT_WIDTH-1:0]; else q_entry_r <= #TCQ q_entry_ns; // Determine if this entry is the head of its queue. reg head_ns; always @(/*AS*/accept_req or accept_this_bm or adv_queue or bm_end_lcl or head_r_lcl or idle_cnt or idle_r_lcl or idlers_below or q_entry_r or rb_hit_busy_cnt or rst) begin if (rst) head_ns = ~|ID[BM_CNT_WIDTH-1:0]; else begin head_ns = head_r_lcl; if (accept_this_bm) head_ns = ~|(rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO)); if ((~idle_r_lcl && adv_queue) || (idle_r_lcl && accept_req && ~accept_this_bm)) head_ns = ~|(q_entry_r - BM_CNT_ONE); if (bm_end_lcl) begin head_ns = ~|(idle_cnt - (accept_req ? BM_CNT_ONE : BM_CNT_ZERO)) && ~|idlers_below; end end end always @(posedge clk) head_r_lcl <= #TCQ head_ns; output wire head_r; assign head_r = head_r_lcl; // Determine if this entry is the tail of its queue. Note that // an entry can be both head and tail. input rb_hit_busy_r; reg tail_r_lcl = 1'b1; generate if (nBANK_MACHS > 1) begin : compute_tail reg tail_ns; always @(accept_req or accept_this_bm or bm_end_in or bm_end_lcl or idle_r_lcl or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin if (rst) tail_ns = (ID == nBANK_MACHS); // The order of the statements below is important in the case where // another bank machine is retiring and this bank machine is accepting. else begin tail_ns = tail_r_lcl; if ((accept_req && rb_hit_busy_r) || (|bm_end_in[`BM_SHARED_BV] && idle_r_lcl)) tail_ns = 1'b0; if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1; end end always @(posedge clk) tail_r_lcl <= #TCQ tail_ns; end // if (nBANK_MACHS > 1) endgenerate output wire tail_r; assign tail_r = tail_r_lcl; wire clear_req = bm_end_lcl || rst; // Is this entry in the idle queue? reg idle_ns_lcl; always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin idle_ns_lcl = idle_r_lcl; if (accept_this_bm) idle_ns_lcl = 1'b0; if (clear_req) idle_ns_lcl = 1'b1; end always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl; output wire idle_ns; assign idle_ns = idle_ns_lcl; output wire idle_r; assign idle_r = idle_r_lcl; // Maintenance hitting on this active bank machine is in progress. input maint_idle; input maint_hit; wire maint_hit_this_bm = ~maint_idle && maint_hit; // Does new request hit on this bank machine while it is able to pass the // open bank? input row_hit_r; input pre_wait_r; wire pass_open_bank_eligible = tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r; // Set pass open bank bit, but not if request preceded active maintenance. reg wait_for_maint_r_lcl; reg pass_open_bank_r_lcl; wire pass_open_bank_ns_lcl = ~clear_req && (pass_open_bank_r_lcl || (accept_req && pass_open_bank_eligible && (~maint_hit_this_bm || wait_for_maint_r_lcl))); always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl; output wire pass_open_bank_ns; assign pass_open_bank_ns = pass_open_bank_ns_lcl; output wire pass_open_bank_r; assign pass_open_bank_r = pass_open_bank_r_lcl; `ifdef MC_SVA pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns)); pass_open_bank_killed_by_maint: cover property (@(posedge clk) (~rst && accept_req && pass_open_bank_eligible && maint_hit_this_bm && ~wait_for_maint_r_lcl)); pass_open_bank_following_maint: cover property (@(posedge clk) (~rst && accept_req && pass_open_bank_eligible && maint_hit_this_bm && wait_for_maint_r_lcl)); `endif // Should the column command be sent with the auto precharge bit set? This // will happen when it is detected that next request is to a different row, // or the next reqest is the next request is refresh to this rank. reg auto_pre_r_lcl; reg auto_pre_ns; input allow_auto_pre; always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl or clear_req or maint_hit_this_bm or rb_hit_busy_r or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin auto_pre_ns = auto_pre_r_lcl; if (clear_req) auto_pre_ns = 1'b0; else if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r && (~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl))) auto_pre_ns = 1'b1; end always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns; output wire auto_pre_r; assign auto_pre_r = auto_pre_r_lcl; `ifdef MC_SVA auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns)); maint_triggers_auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns && ~auto_pre_r && row_hit_r)); `endif // Determine when the current request is finished. input sending_col; input req_wr_r; input rd_wr_r; wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r); input bank_wait_in_progress; input precharge_bm_end; reg pre_bm_end_r; wire pre_bm_end_ns = precharge_bm_end || (bank_wait_in_progress && pass_open_bank_ns_lcl); always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns; assign bm_end_lcl = pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl); output wire bm_end; assign bm_end = bm_end_lcl; // Determine that the open bank should be passed to the successor bank machine. reg pre_passing_open_bank_r; wire pre_passing_open_bank_ns = bank_wait_in_progress && pass_open_bank_ns_lcl; always @(posedge clk) pre_passing_open_bank_r <= #TCQ pre_passing_open_bank_ns; output wire passing_open_bank; assign passing_open_bank = pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl); reg ordered_ns; wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r)) && accept_this_bm; wire ordered_issued_lcl = sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) && ((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r)); output wire ordered_issued; assign ordered_issued = ordered_issued_lcl; reg ordered_r_lcl; always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst or set_order_q) begin if (rst) ordered_ns = 1'b0; else begin ordered_ns = ordered_r_lcl; // Should never see accept_this_bm and adv_order_q at the same time. if (set_order_q) ordered_ns = 1'b1; if (ordered_issued_lcl) ordered_ns = 1'b0; end end always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns; output wire ordered_r; assign ordered_r = ordered_r_lcl; // Figure out when to advance the ordering queue. input adv_order_q; input [BM_CNT_WIDTH-1:0] order_cnt; reg [BM_CNT_WIDTH-1:0] order_q_r; reg [BM_CNT_WIDTH-1:0] order_q_ns; always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst or set_order_q) begin order_q_ns = order_q_r; if (rst) order_q_ns = BM_CNT_ZERO; if (set_order_q) if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE; else order_q_ns = order_cnt; if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE; end always @(posedge clk) order_q_r <= #TCQ order_q_ns; output wire order_q_zero; assign order_q_zero = ~|order_q_r || (adv_order_q && (order_q_r == BM_CNT_ONE)) || ((ORDERING == "NORM") && rd_wr_r); // Keep track of which other bank machine are ahead of this one in a // rank-bank queue. This is necessary to know when to advance this bank // machine in the queue, and when to update bank state machine counter upon // passing a bank. input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in; reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}}; input [(nBANK_MACHS*2)-1:0] passing_open_bank_in; output reg rcv_open_bank = 1'b0; generate if (nBANK_MACHS > 1) begin : rb_hit_busies // The clear_vector resets bits in the rb_hit_busies vector as bank machines // completes requests. rst also resets all the bits. wire [nBANK_MACHS-2:0] clear_vector = ({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]); // As this bank machine takes on a new request, capture the vector of // which other bank machines are in the same queue. wire [`BM_SHARED_BV] rb_hit_busies_ns = ~clear_vector & (idle_ns_lcl ? rb_hit_busy_ns_in[`BM_SHARED_BV] : rb_hit_busies_r_lcl[`BM_SHARED_BV]); always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <= #TCQ rb_hit_busies_ns; // Compute when to advance this queue entry based on seeing other bank machines // in the same queue finish. always @(bm_end_in or rb_hit_busies_r_lcl) adv_queue = |(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]); // Decide when to receive an open bank based on knowing this bank machine is // one entry from the head, and a passing_open_bank hits on the // rb_hit_busies vector. always @(idle_r_lcl or passing_open_bank_in or q_entry_r or rb_hit_busies_r_lcl) rcv_open_bank = |(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV]) && (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl; end endgenerate output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; assign rb_hit_busies_r = rb_hit_busies_r_lcl; // Keep track if the queue this entry is in has priority content. input was_wr; input maint_req_r; reg q_has_rd_r; wire q_has_rd_ns = ~clear_req && (q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) || (maint_req_r && maint_hit && ~idle_r_lcl)); always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns; output wire q_has_rd; assign q_has_rd = q_has_rd_r; input was_priority; reg q_has_priority_r; wire q_has_priority_ns = ~clear_req && (q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority)); always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns; output wire q_has_priority; assign q_has_priority = q_has_priority_r; // Figure out if this entry should wait for maintenance to end. wire wait_for_maint_ns = ~rst && ~maint_idle && (wait_for_maint_r_lcl || (maint_hit && accept_this_bm)); always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns; output wire wait_for_maint_r; assign wait_for_maint_r = wait_for_maint_r_lcl; endmodule // bank_queue
//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : rank_cntrl.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** //***************************************************************************** // This block is responsible for managing various rank level timing // parameters. For now, only Four Activate Window (FAW) and Write // To Read delay are implemented here. // // Each rank machine generates its own inhbt_act_faw_r and inhbt_rd. // These per rank machines are driven into the bank machines. Each // bank machines selects the correct inhibits based on the rank // of its current request. //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_rank_cntrl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter BURST_MODE = "8", // Burst length parameter DQRD2DQWR_DLY = 2, // RD->WR DQ Bus Delay parameter CL = 5, // Read CAS latency parameter CWL = 5, // Write CAS latency parameter ID = 0, // Unique ID for each instance parameter nBANK_MACHS = 4, // # bank machines in MC parameter nCK_PER_CLK = 2, // DRAM clock : MC clock parameter nFAW = 30, // four activate window (CKs) parameter nREFRESH_BANK = 8, // # REF commands to pull-in parameter nRRD = 4, // ACT->ACT period (CKs) parameter nWTR = 4, // Internal write->read // delay (CKs) parameter PERIODIC_RD_TIMER_DIV = 20, // Maintenance prescaler divisor // for periodic read timer parameter RANK_BM_BV_WIDTH = 16, // Width required to broadcast a // single bit rank signal among // all the bank machines parameter RANK_WIDTH = 2, // # of bits to count ranks parameter RANKS = 4, // # of ranks of DRAM parameter REFRESH_TIMER_DIV = 39 // Maintenance prescaler divivor // for refresh timer ) ( // Maintenance requests output periodic_rd_request, output wire refresh_request, // Inhibit signals output reg inhbt_act_faw_r, output reg inhbt_rd, output reg inhbt_wr, // System Inputs input clk, input rst, // User maintenance requests input app_periodic_rd_req, input app_ref_req, // Inputs input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r, input clear_periodic_rd_request, input col_rd_wr, input init_calib_complete, input insert_maint_r1, input maint_prescaler_tick_r, input [RANK_WIDTH-1:0] maint_rank_r, input maint_zq_r, input maint_sre_r, input maint_srx_r, input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r, input refresh_tick, input [nBANK_MACHS-1:0] sending_col, input [nBANK_MACHS-1:0] sending_row, input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r, input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r ); //*************************************************************************** // RRD configuration. The bank machines have a mechanism to prevent RAS to // RAS on adjacent fabric CLK states to the same rank. When // nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, 4 for nRRD // when nCK_PER_CLK == 2 and 8 for nRRD when nCK_PER_CLK == 4. Some of the // higher clock rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit // is worked into the inhbt_faw signal. //*************************************************************************** localparam nADD_RRD = nRRD - ( (nCK_PER_CLK == 1) ? 2 : (nCK_PER_CLK == 2) ? 4 : /*(nCK_PER_CLK == 4)*/ 8 ); // divide by nCK_PER_CLK and add a cycle if there's a remainder localparam nRRD_CLKS = (nCK_PER_CLK == 1) ? nADD_RRD : (nCK_PER_CLK == 2) ? ((nADD_RRD/2)+(nADD_RRD%2)) : /*(nCK_PER_CLK == 4)*/ ((nADD_RRD/4)+((nADD_RRD%4) ? 1 : 0)); // take binary log to obtain counter width and add a tick for the idle cycle localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /* idle state */ 1); //*************************************************************************** // Internal signals //*************************************************************************** reg act_this_rank; integer i; // loop invariant //*************************************************************************** // Function clogb2 // Description: // This function performs binary logarithm and rounds up // Inputs: // size: integer to perform binary log upon // Outputs: // clogb2: result of binary logarithm, rounded up //*************************************************************************** function integer clogb2 (input integer size); begin size = size - 1; // increment clogb2 from 1 for each bit in size for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1) size = size >> 1; end endfunction // clogb2 //*************************************************************************** // Determine if this rank has been activated. act_this_rank_r is a // registered bit vector from individual bank machines indicating the // corresponding bank machine is sending // an activate. Timing is improved with this method. //*************************************************************************** always @(/*AS*/act_this_rank_r or sending_row) begin act_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) act_this_rank = act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]); end reg add_rrd_inhbt = 1'b0; generate if (nADD_RRD > 0 && ADD_RRD_CNTR_WIDTH > 1) begin :add_rdd1 reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns; reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r; always @(/*AS*/act_this_rank or add_rrd_r or rst) begin add_rrd_ns = add_rrd_r; if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}}; else if (act_this_rank) add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH]; else if (|add_rrd_r) add_rrd_ns = add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1}; end always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns; always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns; end // add_rdd1 else if (nADD_RRD > 0) begin :add_rdd0 reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns; reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r; always @(/*AS*/act_this_rank or add_rrd_r or rst) begin add_rrd_ns = add_rrd_r; if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}}; else if (act_this_rank) add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH]; else if (|add_rrd_r) add_rrd_ns = add_rrd_r - {1'b1}; end always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns; always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns; end // add_rdd0 endgenerate // Compute inhbt_act_faw_r. Only allow a limited number of activates // in a window. Both the number of activates and the window are // configurable. This depends on the RRD mechanism to prevent // two consecutive activates to the same rank. // // Subtract three from the specified nFAW. Subtract three because: // -Zero for the delay into the SRL is really one state. // -Sending_row is used to trigger the delay. Sending_row is one // state delayed from the arb. // -inhbt_act_faw_r is registered to make timing work, hence the // generation needs to be one state early. localparam nFAW_CLKS = (nCK_PER_CLK == 1) ? nFAW : (nCK_PER_CLK == 2) ? ((nFAW/2) + (nFAW%2)) : ((nFAW/4) + ((nFAW%4) ? 1 : 0)); generate begin : inhbt_act_faw wire act_delayed; wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3; SRLC32E #(.INIT(32'h00000000) ) SRLC32E0 (.Q(act_delayed), // SRL data output .Q31(), // SRL cascade output pin .A(shift_depth), // 5-bit shift depth select input .CE(1'b1), // Clock enable input .CLK(clk), // Clock input .D(act_this_rank) // SRL data input ); reg [2:0] faw_cnt_ns; reg [2:0] faw_cnt_r; reg inhbt_act_faw_ns; always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt or faw_cnt_r or rst) begin if (rst) faw_cnt_ns = 3'b0; else begin faw_cnt_ns = faw_cnt_r; if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1; if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1; end inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt; end always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns; always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns; end // block: inhbt_act_faw endgenerate // In the DRAM spec, tWTR starts from CK following the end of the data // burst. Since we don't directly have that spec, the wtr timer is // based on when the CAS write command is sent to the DRAM. // // To compute the wtr timer value, first compute the time from the write command // to the read command. This is CWL + data_time + nWTR. // // Two is subtracted from the required wtr time since the timer // starts two states after the arbitration cycle. localparam ONE = 1; localparam TWO = 2; localparam CASWR2CASRD = CWL + (BURST_MODE == "4" ? 2 : 4) + nWTR; localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1) ? CASWR2CASRD : (nCK_PER_CLK == 2) ? ((CASWR2CASRD / 2) + (CASWR2CASRD % 2)) : ((CASWR2CASRD / 4) + ((CASWR2CASRD % 4) ? 1 :0)); localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS); generate begin : wtr_timer reg write_this_rank; always @(/*AS*/sending_col or wr_this_rank_r) begin write_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) write_this_rank = write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]); end reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r; reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns; always @(/*AS*/rst or write_this_rank or wtr_cnt_r) if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}}; else begin wtr_cnt_ns = wtr_cnt_r; if (write_this_rank) wtr_cnt_ns = CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - ONE[WTR_CNT_WIDTH-1:0]; else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0]; end wire inhbt_rd_ns = |wtr_cnt_ns; always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns; always @(inhbt_rd_ns) inhbt_rd = inhbt_rd_ns; end endgenerate // In the DRAM spec (with AL = 0), the read-to-write command delay is implied to // be CL + data_time + 2 tCK - CWL. The CL + data_time - CWL terms ensure the // read and write data do not collide on the DQ bus. The 2 tCK ensures a gap // between them. Here, we allow the user to tune this fixed term via the // DQRD2DQWR_DLY parameter. There's a potential for optimization by relocating // this to the rank_common module, since this is a DQ/DQS bus-level requirement, // not a per-rank requirement. localparam CASRD2CASWR = CL + (BURST_MODE == "4" ? 2 : 4) + DQRD2DQWR_DLY - CWL; localparam CASRD2CASWR_CLKS = (nCK_PER_CLK == 1) ? CASRD2CASWR : (nCK_PER_CLK == 2) ? ((CASRD2CASWR / 2) + (CASRD2CASWR % 2)) : ((CASRD2CASWR / 4) + ((CASRD2CASWR % 4) ? 1 :0)); localparam RTW_CNT_WIDTH = clogb2(CASRD2CASWR_CLKS); generate begin : rtw_timer reg read_this_rank; always @(/*AS*/sending_col or rd_this_rank_r) begin read_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) read_this_rank = read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]); end reg [RTW_CNT_WIDTH-1:0] rtw_cnt_r; reg [RTW_CNT_WIDTH-1:0] rtw_cnt_ns; always @(/*AS*/rst or col_rd_wr or sending_col or rtw_cnt_r) if (rst) rtw_cnt_ns = {RTW_CNT_WIDTH{1'b0}}; else begin rtw_cnt_ns = rtw_cnt_r; if (col_rd_wr && |sending_col) rtw_cnt_ns = CASRD2CASWR_CLKS[RTW_CNT_WIDTH-1:0] - ONE[RTW_CNT_WIDTH-1:0]; else if (|rtw_cnt_r) rtw_cnt_ns = rtw_cnt_r - ONE[RTW_CNT_WIDTH-1:0]; end wire inhbt_wr_ns = |rtw_cnt_ns; always @(posedge clk) rtw_cnt_r <= #TCQ rtw_cnt_ns; always @(inhbt_wr_ns) inhbt_wr = inhbt_wr_ns; end endgenerate // Refresh request generation. Implement a "refresh bank". Referred // to as pullin-in refresh in the JEDEC spec. // The refresh_rank_r counter increments when a refresh to this // rank has been decoded. In the up direction, the count saturates // at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK // is normally eight. The counter decrements with each refresh_tick, // saturating at zero. A refresh will be requests when the rank is // not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r // equals zero. localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1); generate begin : refresh_generation reg my_rank_busy; always @(/*AS*/rank_busy_r) begin my_rank_busy = 1'b0; for (i=0; i < nBANK_MACHS; i=i+1) my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID]; end wire my_refresh = insert_maint_r1 && ~maint_zq_r && ~maint_sre_r && ~maint_srx_r && (maint_rank_r == ID[RANK_WIDTH-1:0]); reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r; reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns; always @(/*AS*/app_ref_req or init_calib_complete or my_refresh or refresh_bank_r or refresh_tick) if (~init_calib_complete) if (REFRESH_TIMER_DIV == 0) refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]; else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}}; else case ({my_refresh, refresh_tick, app_ref_req}) 3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r; 3'b010, 3'b001, 3'b011 : refresh_bank_ns = (|refresh_bank_r)? refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]: refresh_bank_r; 3'b100 : refresh_bank_ns = refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH]; endcase // case ({my_refresh, refresh_tick}) always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns; `ifdef MC_SVA refresh_bank_overflow: assert property (@(posedge clk) (rst || (refresh_bank_r <= nREFRESH_BANK))); refresh_bank_underflow: assert property (@(posedge clk) (rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick))); refresh_hi_priority: cover property (@(posedge clk) (rst && ~|refresh_bank_ns && (refresh_bank_r == ONE[0+:REFRESH_BANK_WIDTH]))); refresh_bank_full: cover property (@(posedge clk) (rst && (refresh_bank_r == nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]))); `endif assign refresh_request = init_calib_complete && (~|refresh_bank_r || ((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy)); end endgenerate // Periodic read request generation. localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1); generate begin : periodic_rd_generation if ( PERIODIC_RD_TIMER_DIV != 0 ) begin // enable periodic reads reg read_this_rank; always @(/*AS*/rd_this_rank_r or sending_col) begin read_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) read_this_rank = read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]); end reg read_this_rank_r; reg read_this_rank_r1; always @(posedge clk) read_this_rank_r <= #TCQ read_this_rank; always @(posedge clk) read_this_rank_r1 <= #TCQ read_this_rank_r; wire int_read_this_rank = read_this_rank && (((nCK_PER_CLK == 4) && read_this_rank_r) || ((nCK_PER_CLK != 4) && read_this_rank_r1)); reg periodic_rd_cntr1_ns; reg periodic_rd_cntr1_r; always @(/*AS*/clear_periodic_rd_request or periodic_rd_cntr1_r) begin periodic_rd_cntr1_ns = periodic_rd_cntr1_r; if (clear_periodic_rd_request) periodic_rd_cntr1_ns = periodic_rd_cntr1_r + 1'b1; end always @(posedge clk) begin if (rst) periodic_rd_cntr1_r <= #TCQ 1'b0; else periodic_rd_cntr1_r <= #TCQ periodic_rd_cntr1_ns; end reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r; reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns; always @(/*AS*/init_calib_complete or maint_prescaler_tick_r or periodic_rd_timer_r or int_read_this_rank) begin periodic_rd_timer_ns = periodic_rd_timer_r; if (~init_calib_complete) periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}}; else if (int_read_this_rank) periodic_rd_timer_ns = PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH]; else if (|periodic_rd_timer_r && maint_prescaler_tick_r) periodic_rd_timer_ns = periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH]; end always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns; wire periodic_rd_timer_one = maint_prescaler_tick_r && (periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]); reg periodic_rd_request_r; wire periodic_rd_request_ns = ~rst && ((app_periodic_rd_req && init_calib_complete) || ((PERIODIC_RD_TIMER_DIV != 0) && ~init_calib_complete) || // (~(read_this_rank || clear_periodic_rd_request) && (~((int_read_this_rank) || (clear_periodic_rd_request && periodic_rd_cntr1_r)) && (periodic_rd_request_r || periodic_rd_timer_one))); always @(posedge clk) periodic_rd_request_r <= #TCQ periodic_rd_request_ns; `ifdef MC_SVA read_clears_periodic_rd_request: cover property (@(posedge clk) (rst && (periodic_rd_request_r && read_this_rank))); `endif assign periodic_rd_request = init_calib_complete && periodic_rd_request_r; end else assign periodic_rd_request = 1'b0; //to disable periodic reads end endgenerate endmodule
//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : rank_cntrl.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** //***************************************************************************** // This block is responsible for managing various rank level timing // parameters. For now, only Four Activate Window (FAW) and Write // To Read delay are implemented here. // // Each rank machine generates its own inhbt_act_faw_r and inhbt_rd. // These per rank machines are driven into the bank machines. Each // bank machines selects the correct inhibits based on the rank // of its current request. //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_rank_cntrl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter BURST_MODE = "8", // Burst length parameter DQRD2DQWR_DLY = 2, // RD->WR DQ Bus Delay parameter CL = 5, // Read CAS latency parameter CWL = 5, // Write CAS latency parameter ID = 0, // Unique ID for each instance parameter nBANK_MACHS = 4, // # bank machines in MC parameter nCK_PER_CLK = 2, // DRAM clock : MC clock parameter nFAW = 30, // four activate window (CKs) parameter nREFRESH_BANK = 8, // # REF commands to pull-in parameter nRRD = 4, // ACT->ACT period (CKs) parameter nWTR = 4, // Internal write->read // delay (CKs) parameter PERIODIC_RD_TIMER_DIV = 20, // Maintenance prescaler divisor // for periodic read timer parameter RANK_BM_BV_WIDTH = 16, // Width required to broadcast a // single bit rank signal among // all the bank machines parameter RANK_WIDTH = 2, // # of bits to count ranks parameter RANKS = 4, // # of ranks of DRAM parameter REFRESH_TIMER_DIV = 39 // Maintenance prescaler divivor // for refresh timer ) ( // Maintenance requests output periodic_rd_request, output wire refresh_request, // Inhibit signals output reg inhbt_act_faw_r, output reg inhbt_rd, output reg inhbt_wr, // System Inputs input clk, input rst, // User maintenance requests input app_periodic_rd_req, input app_ref_req, // Inputs input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r, input clear_periodic_rd_request, input col_rd_wr, input init_calib_complete, input insert_maint_r1, input maint_prescaler_tick_r, input [RANK_WIDTH-1:0] maint_rank_r, input maint_zq_r, input maint_sre_r, input maint_srx_r, input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r, input refresh_tick, input [nBANK_MACHS-1:0] sending_col, input [nBANK_MACHS-1:0] sending_row, input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r, input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r ); //*************************************************************************** // RRD configuration. The bank machines have a mechanism to prevent RAS to // RAS on adjacent fabric CLK states to the same rank. When // nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, 4 for nRRD // when nCK_PER_CLK == 2 and 8 for nRRD when nCK_PER_CLK == 4. Some of the // higher clock rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit // is worked into the inhbt_faw signal. //*************************************************************************** localparam nADD_RRD = nRRD - ( (nCK_PER_CLK == 1) ? 2 : (nCK_PER_CLK == 2) ? 4 : /*(nCK_PER_CLK == 4)*/ 8 ); // divide by nCK_PER_CLK and add a cycle if there's a remainder localparam nRRD_CLKS = (nCK_PER_CLK == 1) ? nADD_RRD : (nCK_PER_CLK == 2) ? ((nADD_RRD/2)+(nADD_RRD%2)) : /*(nCK_PER_CLK == 4)*/ ((nADD_RRD/4)+((nADD_RRD%4) ? 1 : 0)); // take binary log to obtain counter width and add a tick for the idle cycle localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /* idle state */ 1); //*************************************************************************** // Internal signals //*************************************************************************** reg act_this_rank; integer i; // loop invariant //*************************************************************************** // Function clogb2 // Description: // This function performs binary logarithm and rounds up // Inputs: // size: integer to perform binary log upon // Outputs: // clogb2: result of binary logarithm, rounded up //*************************************************************************** function integer clogb2 (input integer size); begin size = size - 1; // increment clogb2 from 1 for each bit in size for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1) size = size >> 1; end endfunction // clogb2 //*************************************************************************** // Determine if this rank has been activated. act_this_rank_r is a // registered bit vector from individual bank machines indicating the // corresponding bank machine is sending // an activate. Timing is improved with this method. //*************************************************************************** always @(/*AS*/act_this_rank_r or sending_row) begin act_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) act_this_rank = act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]); end reg add_rrd_inhbt = 1'b0; generate if (nADD_RRD > 0 && ADD_RRD_CNTR_WIDTH > 1) begin :add_rdd1 reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns; reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r; always @(/*AS*/act_this_rank or add_rrd_r or rst) begin add_rrd_ns = add_rrd_r; if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}}; else if (act_this_rank) add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH]; else if (|add_rrd_r) add_rrd_ns = add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1}; end always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns; always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns; end // add_rdd1 else if (nADD_RRD > 0) begin :add_rdd0 reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns; reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r; always @(/*AS*/act_this_rank or add_rrd_r or rst) begin add_rrd_ns = add_rrd_r; if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}}; else if (act_this_rank) add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH]; else if (|add_rrd_r) add_rrd_ns = add_rrd_r - {1'b1}; end always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns; always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns; end // add_rdd0 endgenerate // Compute inhbt_act_faw_r. Only allow a limited number of activates // in a window. Both the number of activates and the window are // configurable. This depends on the RRD mechanism to prevent // two consecutive activates to the same rank. // // Subtract three from the specified nFAW. Subtract three because: // -Zero for the delay into the SRL is really one state. // -Sending_row is used to trigger the delay. Sending_row is one // state delayed from the arb. // -inhbt_act_faw_r is registered to make timing work, hence the // generation needs to be one state early. localparam nFAW_CLKS = (nCK_PER_CLK == 1) ? nFAW : (nCK_PER_CLK == 2) ? ((nFAW/2) + (nFAW%2)) : ((nFAW/4) + ((nFAW%4) ? 1 : 0)); generate begin : inhbt_act_faw wire act_delayed; wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3; SRLC32E #(.INIT(32'h00000000) ) SRLC32E0 (.Q(act_delayed), // SRL data output .Q31(), // SRL cascade output pin .A(shift_depth), // 5-bit shift depth select input .CE(1'b1), // Clock enable input .CLK(clk), // Clock input .D(act_this_rank) // SRL data input ); reg [2:0] faw_cnt_ns; reg [2:0] faw_cnt_r; reg inhbt_act_faw_ns; always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt or faw_cnt_r or rst) begin if (rst) faw_cnt_ns = 3'b0; else begin faw_cnt_ns = faw_cnt_r; if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1; if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1; end inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt; end always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns; always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns; end // block: inhbt_act_faw endgenerate // In the DRAM spec, tWTR starts from CK following the end of the data // burst. Since we don't directly have that spec, the wtr timer is // based on when the CAS write command is sent to the DRAM. // // To compute the wtr timer value, first compute the time from the write command // to the read command. This is CWL + data_time + nWTR. // // Two is subtracted from the required wtr time since the timer // starts two states after the arbitration cycle. localparam ONE = 1; localparam TWO = 2; localparam CASWR2CASRD = CWL + (BURST_MODE == "4" ? 2 : 4) + nWTR; localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1) ? CASWR2CASRD : (nCK_PER_CLK == 2) ? ((CASWR2CASRD / 2) + (CASWR2CASRD % 2)) : ((CASWR2CASRD / 4) + ((CASWR2CASRD % 4) ? 1 :0)); localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS); generate begin : wtr_timer reg write_this_rank; always @(/*AS*/sending_col or wr_this_rank_r) begin write_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) write_this_rank = write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]); end reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r; reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns; always @(/*AS*/rst or write_this_rank or wtr_cnt_r) if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}}; else begin wtr_cnt_ns = wtr_cnt_r; if (write_this_rank) wtr_cnt_ns = CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - ONE[WTR_CNT_WIDTH-1:0]; else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0]; end wire inhbt_rd_ns = |wtr_cnt_ns; always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns; always @(inhbt_rd_ns) inhbt_rd = inhbt_rd_ns; end endgenerate // In the DRAM spec (with AL = 0), the read-to-write command delay is implied to // be CL + data_time + 2 tCK - CWL. The CL + data_time - CWL terms ensure the // read and write data do not collide on the DQ bus. The 2 tCK ensures a gap // between them. Here, we allow the user to tune this fixed term via the // DQRD2DQWR_DLY parameter. There's a potential for optimization by relocating // this to the rank_common module, since this is a DQ/DQS bus-level requirement, // not a per-rank requirement. localparam CASRD2CASWR = CL + (BURST_MODE == "4" ? 2 : 4) + DQRD2DQWR_DLY - CWL; localparam CASRD2CASWR_CLKS = (nCK_PER_CLK == 1) ? CASRD2CASWR : (nCK_PER_CLK == 2) ? ((CASRD2CASWR / 2) + (CASRD2CASWR % 2)) : ((CASRD2CASWR / 4) + ((CASRD2CASWR % 4) ? 1 :0)); localparam RTW_CNT_WIDTH = clogb2(CASRD2CASWR_CLKS); generate begin : rtw_timer reg read_this_rank; always @(/*AS*/sending_col or rd_this_rank_r) begin read_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) read_this_rank = read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]); end reg [RTW_CNT_WIDTH-1:0] rtw_cnt_r; reg [RTW_CNT_WIDTH-1:0] rtw_cnt_ns; always @(/*AS*/rst or col_rd_wr or sending_col or rtw_cnt_r) if (rst) rtw_cnt_ns = {RTW_CNT_WIDTH{1'b0}}; else begin rtw_cnt_ns = rtw_cnt_r; if (col_rd_wr && |sending_col) rtw_cnt_ns = CASRD2CASWR_CLKS[RTW_CNT_WIDTH-1:0] - ONE[RTW_CNT_WIDTH-1:0]; else if (|rtw_cnt_r) rtw_cnt_ns = rtw_cnt_r - ONE[RTW_CNT_WIDTH-1:0]; end wire inhbt_wr_ns = |rtw_cnt_ns; always @(posedge clk) rtw_cnt_r <= #TCQ rtw_cnt_ns; always @(inhbt_wr_ns) inhbt_wr = inhbt_wr_ns; end endgenerate // Refresh request generation. Implement a "refresh bank". Referred // to as pullin-in refresh in the JEDEC spec. // The refresh_rank_r counter increments when a refresh to this // rank has been decoded. In the up direction, the count saturates // at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK // is normally eight. The counter decrements with each refresh_tick, // saturating at zero. A refresh will be requests when the rank is // not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r // equals zero. localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1); generate begin : refresh_generation reg my_rank_busy; always @(/*AS*/rank_busy_r) begin my_rank_busy = 1'b0; for (i=0; i < nBANK_MACHS; i=i+1) my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID]; end wire my_refresh = insert_maint_r1 && ~maint_zq_r && ~maint_sre_r && ~maint_srx_r && (maint_rank_r == ID[RANK_WIDTH-1:0]); reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r; reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns; always @(/*AS*/app_ref_req or init_calib_complete or my_refresh or refresh_bank_r or refresh_tick) if (~init_calib_complete) if (REFRESH_TIMER_DIV == 0) refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]; else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}}; else case ({my_refresh, refresh_tick, app_ref_req}) 3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r; 3'b010, 3'b001, 3'b011 : refresh_bank_ns = (|refresh_bank_r)? refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]: refresh_bank_r; 3'b100 : refresh_bank_ns = refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH]; endcase // case ({my_refresh, refresh_tick}) always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns; `ifdef MC_SVA refresh_bank_overflow: assert property (@(posedge clk) (rst || (refresh_bank_r <= nREFRESH_BANK))); refresh_bank_underflow: assert property (@(posedge clk) (rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick))); refresh_hi_priority: cover property (@(posedge clk) (rst && ~|refresh_bank_ns && (refresh_bank_r == ONE[0+:REFRESH_BANK_WIDTH]))); refresh_bank_full: cover property (@(posedge clk) (rst && (refresh_bank_r == nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]))); `endif assign refresh_request = init_calib_complete && (~|refresh_bank_r || ((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy)); end endgenerate // Periodic read request generation. localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1); generate begin : periodic_rd_generation if ( PERIODIC_RD_TIMER_DIV != 0 ) begin // enable periodic reads reg read_this_rank; always @(/*AS*/rd_this_rank_r or sending_col) begin read_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) read_this_rank = read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]); end reg read_this_rank_r; reg read_this_rank_r1; always @(posedge clk) read_this_rank_r <= #TCQ read_this_rank; always @(posedge clk) read_this_rank_r1 <= #TCQ read_this_rank_r; wire int_read_this_rank = read_this_rank && (((nCK_PER_CLK == 4) && read_this_rank_r) || ((nCK_PER_CLK != 4) && read_this_rank_r1)); reg periodic_rd_cntr1_ns; reg periodic_rd_cntr1_r; always @(/*AS*/clear_periodic_rd_request or periodic_rd_cntr1_r) begin periodic_rd_cntr1_ns = periodic_rd_cntr1_r; if (clear_periodic_rd_request) periodic_rd_cntr1_ns = periodic_rd_cntr1_r + 1'b1; end always @(posedge clk) begin if (rst) periodic_rd_cntr1_r <= #TCQ 1'b0; else periodic_rd_cntr1_r <= #TCQ periodic_rd_cntr1_ns; end reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r; reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns; always @(/*AS*/init_calib_complete or maint_prescaler_tick_r or periodic_rd_timer_r or int_read_this_rank) begin periodic_rd_timer_ns = periodic_rd_timer_r; if (~init_calib_complete) periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}}; else if (int_read_this_rank) periodic_rd_timer_ns = PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH]; else if (|periodic_rd_timer_r && maint_prescaler_tick_r) periodic_rd_timer_ns = periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH]; end always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns; wire periodic_rd_timer_one = maint_prescaler_tick_r && (periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]); reg periodic_rd_request_r; wire periodic_rd_request_ns = ~rst && ((app_periodic_rd_req && init_calib_complete) || ((PERIODIC_RD_TIMER_DIV != 0) && ~init_calib_complete) || // (~(read_this_rank || clear_periodic_rd_request) && (~((int_read_this_rank) || (clear_periodic_rd_request && periodic_rd_cntr1_r)) && (periodic_rd_request_r || periodic_rd_timer_one))); always @(posedge clk) periodic_rd_request_r <= #TCQ periodic_rd_request_ns; `ifdef MC_SVA read_clears_periodic_rd_request: cover property (@(posedge clk) (rst && (periodic_rd_request_r && read_this_rank))); `endif assign periodic_rd_request = init_calib_complete && periodic_rd_request_r; end else assign periodic_rd_request = 1'b0; //to disable periodic reads end endgenerate endmodule
//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : rank_cntrl.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** //***************************************************************************** // This block is responsible for managing various rank level timing // parameters. For now, only Four Activate Window (FAW) and Write // To Read delay are implemented here. // // Each rank machine generates its own inhbt_act_faw_r and inhbt_rd. // These per rank machines are driven into the bank machines. Each // bank machines selects the correct inhibits based on the rank // of its current request. //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_rank_cntrl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter BURST_MODE = "8", // Burst length parameter DQRD2DQWR_DLY = 2, // RD->WR DQ Bus Delay parameter CL = 5, // Read CAS latency parameter CWL = 5, // Write CAS latency parameter ID = 0, // Unique ID for each instance parameter nBANK_MACHS = 4, // # bank machines in MC parameter nCK_PER_CLK = 2, // DRAM clock : MC clock parameter nFAW = 30, // four activate window (CKs) parameter nREFRESH_BANK = 8, // # REF commands to pull-in parameter nRRD = 4, // ACT->ACT period (CKs) parameter nWTR = 4, // Internal write->read // delay (CKs) parameter PERIODIC_RD_TIMER_DIV = 20, // Maintenance prescaler divisor // for periodic read timer parameter RANK_BM_BV_WIDTH = 16, // Width required to broadcast a // single bit rank signal among // all the bank machines parameter RANK_WIDTH = 2, // # of bits to count ranks parameter RANKS = 4, // # of ranks of DRAM parameter REFRESH_TIMER_DIV = 39 // Maintenance prescaler divivor // for refresh timer ) ( // Maintenance requests output periodic_rd_request, output wire refresh_request, // Inhibit signals output reg inhbt_act_faw_r, output reg inhbt_rd, output reg inhbt_wr, // System Inputs input clk, input rst, // User maintenance requests input app_periodic_rd_req, input app_ref_req, // Inputs input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r, input clear_periodic_rd_request, input col_rd_wr, input init_calib_complete, input insert_maint_r1, input maint_prescaler_tick_r, input [RANK_WIDTH-1:0] maint_rank_r, input maint_zq_r, input maint_sre_r, input maint_srx_r, input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r, input refresh_tick, input [nBANK_MACHS-1:0] sending_col, input [nBANK_MACHS-1:0] sending_row, input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r, input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r ); //*************************************************************************** // RRD configuration. The bank machines have a mechanism to prevent RAS to // RAS on adjacent fabric CLK states to the same rank. When // nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, 4 for nRRD // when nCK_PER_CLK == 2 and 8 for nRRD when nCK_PER_CLK == 4. Some of the // higher clock rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit // is worked into the inhbt_faw signal. //*************************************************************************** localparam nADD_RRD = nRRD - ( (nCK_PER_CLK == 1) ? 2 : (nCK_PER_CLK == 2) ? 4 : /*(nCK_PER_CLK == 4)*/ 8 ); // divide by nCK_PER_CLK and add a cycle if there's a remainder localparam nRRD_CLKS = (nCK_PER_CLK == 1) ? nADD_RRD : (nCK_PER_CLK == 2) ? ((nADD_RRD/2)+(nADD_RRD%2)) : /*(nCK_PER_CLK == 4)*/ ((nADD_RRD/4)+((nADD_RRD%4) ? 1 : 0)); // take binary log to obtain counter width and add a tick for the idle cycle localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /* idle state */ 1); //*************************************************************************** // Internal signals //*************************************************************************** reg act_this_rank; integer i; // loop invariant //*************************************************************************** // Function clogb2 // Description: // This function performs binary logarithm and rounds up // Inputs: // size: integer to perform binary log upon // Outputs: // clogb2: result of binary logarithm, rounded up //*************************************************************************** function integer clogb2 (input integer size); begin size = size - 1; // increment clogb2 from 1 for each bit in size for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1) size = size >> 1; end endfunction // clogb2 //*************************************************************************** // Determine if this rank has been activated. act_this_rank_r is a // registered bit vector from individual bank machines indicating the // corresponding bank machine is sending // an activate. Timing is improved with this method. //*************************************************************************** always @(/*AS*/act_this_rank_r or sending_row) begin act_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) act_this_rank = act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]); end reg add_rrd_inhbt = 1'b0; generate if (nADD_RRD > 0 && ADD_RRD_CNTR_WIDTH > 1) begin :add_rdd1 reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns; reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r; always @(/*AS*/act_this_rank or add_rrd_r or rst) begin add_rrd_ns = add_rrd_r; if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}}; else if (act_this_rank) add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH]; else if (|add_rrd_r) add_rrd_ns = add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1}; end always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns; always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns; end // add_rdd1 else if (nADD_RRD > 0) begin :add_rdd0 reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns; reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r; always @(/*AS*/act_this_rank or add_rrd_r or rst) begin add_rrd_ns = add_rrd_r; if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}}; else if (act_this_rank) add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH]; else if (|add_rrd_r) add_rrd_ns = add_rrd_r - {1'b1}; end always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns; always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns; end // add_rdd0 endgenerate // Compute inhbt_act_faw_r. Only allow a limited number of activates // in a window. Both the number of activates and the window are // configurable. This depends on the RRD mechanism to prevent // two consecutive activates to the same rank. // // Subtract three from the specified nFAW. Subtract three because: // -Zero for the delay into the SRL is really one state. // -Sending_row is used to trigger the delay. Sending_row is one // state delayed from the arb. // -inhbt_act_faw_r is registered to make timing work, hence the // generation needs to be one state early. localparam nFAW_CLKS = (nCK_PER_CLK == 1) ? nFAW : (nCK_PER_CLK == 2) ? ((nFAW/2) + (nFAW%2)) : ((nFAW/4) + ((nFAW%4) ? 1 : 0)); generate begin : inhbt_act_faw wire act_delayed; wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3; SRLC32E #(.INIT(32'h00000000) ) SRLC32E0 (.Q(act_delayed), // SRL data output .Q31(), // SRL cascade output pin .A(shift_depth), // 5-bit shift depth select input .CE(1'b1), // Clock enable input .CLK(clk), // Clock input .D(act_this_rank) // SRL data input ); reg [2:0] faw_cnt_ns; reg [2:0] faw_cnt_r; reg inhbt_act_faw_ns; always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt or faw_cnt_r or rst) begin if (rst) faw_cnt_ns = 3'b0; else begin faw_cnt_ns = faw_cnt_r; if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1; if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1; end inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt; end always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns; always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns; end // block: inhbt_act_faw endgenerate // In the DRAM spec, tWTR starts from CK following the end of the data // burst. Since we don't directly have that spec, the wtr timer is // based on when the CAS write command is sent to the DRAM. // // To compute the wtr timer value, first compute the time from the write command // to the read command. This is CWL + data_time + nWTR. // // Two is subtracted from the required wtr time since the timer // starts two states after the arbitration cycle. localparam ONE = 1; localparam TWO = 2; localparam CASWR2CASRD = CWL + (BURST_MODE == "4" ? 2 : 4) + nWTR; localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1) ? CASWR2CASRD : (nCK_PER_CLK == 2) ? ((CASWR2CASRD / 2) + (CASWR2CASRD % 2)) : ((CASWR2CASRD / 4) + ((CASWR2CASRD % 4) ? 1 :0)); localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS); generate begin : wtr_timer reg write_this_rank; always @(/*AS*/sending_col or wr_this_rank_r) begin write_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) write_this_rank = write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]); end reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r; reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns; always @(/*AS*/rst or write_this_rank or wtr_cnt_r) if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}}; else begin wtr_cnt_ns = wtr_cnt_r; if (write_this_rank) wtr_cnt_ns = CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - ONE[WTR_CNT_WIDTH-1:0]; else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0]; end wire inhbt_rd_ns = |wtr_cnt_ns; always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns; always @(inhbt_rd_ns) inhbt_rd = inhbt_rd_ns; end endgenerate // In the DRAM spec (with AL = 0), the read-to-write command delay is implied to // be CL + data_time + 2 tCK - CWL. The CL + data_time - CWL terms ensure the // read and write data do not collide on the DQ bus. The 2 tCK ensures a gap // between them. Here, we allow the user to tune this fixed term via the // DQRD2DQWR_DLY parameter. There's a potential for optimization by relocating // this to the rank_common module, since this is a DQ/DQS bus-level requirement, // not a per-rank requirement. localparam CASRD2CASWR = CL + (BURST_MODE == "4" ? 2 : 4) + DQRD2DQWR_DLY - CWL; localparam CASRD2CASWR_CLKS = (nCK_PER_CLK == 1) ? CASRD2CASWR : (nCK_PER_CLK == 2) ? ((CASRD2CASWR / 2) + (CASRD2CASWR % 2)) : ((CASRD2CASWR / 4) + ((CASRD2CASWR % 4) ? 1 :0)); localparam RTW_CNT_WIDTH = clogb2(CASRD2CASWR_CLKS); generate begin : rtw_timer reg read_this_rank; always @(/*AS*/sending_col or rd_this_rank_r) begin read_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) read_this_rank = read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]); end reg [RTW_CNT_WIDTH-1:0] rtw_cnt_r; reg [RTW_CNT_WIDTH-1:0] rtw_cnt_ns; always @(/*AS*/rst or col_rd_wr or sending_col or rtw_cnt_r) if (rst) rtw_cnt_ns = {RTW_CNT_WIDTH{1'b0}}; else begin rtw_cnt_ns = rtw_cnt_r; if (col_rd_wr && |sending_col) rtw_cnt_ns = CASRD2CASWR_CLKS[RTW_CNT_WIDTH-1:0] - ONE[RTW_CNT_WIDTH-1:0]; else if (|rtw_cnt_r) rtw_cnt_ns = rtw_cnt_r - ONE[RTW_CNT_WIDTH-1:0]; end wire inhbt_wr_ns = |rtw_cnt_ns; always @(posedge clk) rtw_cnt_r <= #TCQ rtw_cnt_ns; always @(inhbt_wr_ns) inhbt_wr = inhbt_wr_ns; end endgenerate // Refresh request generation. Implement a "refresh bank". Referred // to as pullin-in refresh in the JEDEC spec. // The refresh_rank_r counter increments when a refresh to this // rank has been decoded. In the up direction, the count saturates // at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK // is normally eight. The counter decrements with each refresh_tick, // saturating at zero. A refresh will be requests when the rank is // not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r // equals zero. localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1); generate begin : refresh_generation reg my_rank_busy; always @(/*AS*/rank_busy_r) begin my_rank_busy = 1'b0; for (i=0; i < nBANK_MACHS; i=i+1) my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID]; end wire my_refresh = insert_maint_r1 && ~maint_zq_r && ~maint_sre_r && ~maint_srx_r && (maint_rank_r == ID[RANK_WIDTH-1:0]); reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r; reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns; always @(/*AS*/app_ref_req or init_calib_complete or my_refresh or refresh_bank_r or refresh_tick) if (~init_calib_complete) if (REFRESH_TIMER_DIV == 0) refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]; else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}}; else case ({my_refresh, refresh_tick, app_ref_req}) 3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r; 3'b010, 3'b001, 3'b011 : refresh_bank_ns = (|refresh_bank_r)? refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]: refresh_bank_r; 3'b100 : refresh_bank_ns = refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH]; endcase // case ({my_refresh, refresh_tick}) always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns; `ifdef MC_SVA refresh_bank_overflow: assert property (@(posedge clk) (rst || (refresh_bank_r <= nREFRESH_BANK))); refresh_bank_underflow: assert property (@(posedge clk) (rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick))); refresh_hi_priority: cover property (@(posedge clk) (rst && ~|refresh_bank_ns && (refresh_bank_r == ONE[0+:REFRESH_BANK_WIDTH]))); refresh_bank_full: cover property (@(posedge clk) (rst && (refresh_bank_r == nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]))); `endif assign refresh_request = init_calib_complete && (~|refresh_bank_r || ((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy)); end endgenerate // Periodic read request generation. localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1); generate begin : periodic_rd_generation if ( PERIODIC_RD_TIMER_DIV != 0 ) begin // enable periodic reads reg read_this_rank; always @(/*AS*/rd_this_rank_r or sending_col) begin read_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) read_this_rank = read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]); end reg read_this_rank_r; reg read_this_rank_r1; always @(posedge clk) read_this_rank_r <= #TCQ read_this_rank; always @(posedge clk) read_this_rank_r1 <= #TCQ read_this_rank_r; wire int_read_this_rank = read_this_rank && (((nCK_PER_CLK == 4) && read_this_rank_r) || ((nCK_PER_CLK != 4) && read_this_rank_r1)); reg periodic_rd_cntr1_ns; reg periodic_rd_cntr1_r; always @(/*AS*/clear_periodic_rd_request or periodic_rd_cntr1_r) begin periodic_rd_cntr1_ns = periodic_rd_cntr1_r; if (clear_periodic_rd_request) periodic_rd_cntr1_ns = periodic_rd_cntr1_r + 1'b1; end always @(posedge clk) begin if (rst) periodic_rd_cntr1_r <= #TCQ 1'b0; else periodic_rd_cntr1_r <= #TCQ periodic_rd_cntr1_ns; end reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r; reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns; always @(/*AS*/init_calib_complete or maint_prescaler_tick_r or periodic_rd_timer_r or int_read_this_rank) begin periodic_rd_timer_ns = periodic_rd_timer_r; if (~init_calib_complete) periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}}; else if (int_read_this_rank) periodic_rd_timer_ns = PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH]; else if (|periodic_rd_timer_r && maint_prescaler_tick_r) periodic_rd_timer_ns = periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH]; end always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns; wire periodic_rd_timer_one = maint_prescaler_tick_r && (periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]); reg periodic_rd_request_r; wire periodic_rd_request_ns = ~rst && ((app_periodic_rd_req && init_calib_complete) || ((PERIODIC_RD_TIMER_DIV != 0) && ~init_calib_complete) || // (~(read_this_rank || clear_periodic_rd_request) && (~((int_read_this_rank) || (clear_periodic_rd_request && periodic_rd_cntr1_r)) && (periodic_rd_request_r || periodic_rd_timer_one))); always @(posedge clk) periodic_rd_request_r <= #TCQ periodic_rd_request_ns; `ifdef MC_SVA read_clears_periodic_rd_request: cover property (@(posedge clk) (rst && (periodic_rd_request_r && read_this_rank))); `endif assign periodic_rd_request = init_calib_complete && periodic_rd_request_r; end else assign periodic_rd_request = 1'b0; //to disable periodic reads end endgenerate endmodule
//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : rank_cntrl.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** //***************************************************************************** // This block is responsible for managing various rank level timing // parameters. For now, only Four Activate Window (FAW) and Write // To Read delay are implemented here. // // Each rank machine generates its own inhbt_act_faw_r and inhbt_rd. // These per rank machines are driven into the bank machines. Each // bank machines selects the correct inhibits based on the rank // of its current request. //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_rank_cntrl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter BURST_MODE = "8", // Burst length parameter DQRD2DQWR_DLY = 2, // RD->WR DQ Bus Delay parameter CL = 5, // Read CAS latency parameter CWL = 5, // Write CAS latency parameter ID = 0, // Unique ID for each instance parameter nBANK_MACHS = 4, // # bank machines in MC parameter nCK_PER_CLK = 2, // DRAM clock : MC clock parameter nFAW = 30, // four activate window (CKs) parameter nREFRESH_BANK = 8, // # REF commands to pull-in parameter nRRD = 4, // ACT->ACT period (CKs) parameter nWTR = 4, // Internal write->read // delay (CKs) parameter PERIODIC_RD_TIMER_DIV = 20, // Maintenance prescaler divisor // for periodic read timer parameter RANK_BM_BV_WIDTH = 16, // Width required to broadcast a // single bit rank signal among // all the bank machines parameter RANK_WIDTH = 2, // # of bits to count ranks parameter RANKS = 4, // # of ranks of DRAM parameter REFRESH_TIMER_DIV = 39 // Maintenance prescaler divivor // for refresh timer ) ( // Maintenance requests output periodic_rd_request, output wire refresh_request, // Inhibit signals output reg inhbt_act_faw_r, output reg inhbt_rd, output reg inhbt_wr, // System Inputs input clk, input rst, // User maintenance requests input app_periodic_rd_req, input app_ref_req, // Inputs input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r, input clear_periodic_rd_request, input col_rd_wr, input init_calib_complete, input insert_maint_r1, input maint_prescaler_tick_r, input [RANK_WIDTH-1:0] maint_rank_r, input maint_zq_r, input maint_sre_r, input maint_srx_r, input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r, input refresh_tick, input [nBANK_MACHS-1:0] sending_col, input [nBANK_MACHS-1:0] sending_row, input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r, input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r ); //*************************************************************************** // RRD configuration. The bank machines have a mechanism to prevent RAS to // RAS on adjacent fabric CLK states to the same rank. When // nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, 4 for nRRD // when nCK_PER_CLK == 2 and 8 for nRRD when nCK_PER_CLK == 4. Some of the // higher clock rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit // is worked into the inhbt_faw signal. //*************************************************************************** localparam nADD_RRD = nRRD - ( (nCK_PER_CLK == 1) ? 2 : (nCK_PER_CLK == 2) ? 4 : /*(nCK_PER_CLK == 4)*/ 8 ); // divide by nCK_PER_CLK and add a cycle if there's a remainder localparam nRRD_CLKS = (nCK_PER_CLK == 1) ? nADD_RRD : (nCK_PER_CLK == 2) ? ((nADD_RRD/2)+(nADD_RRD%2)) : /*(nCK_PER_CLK == 4)*/ ((nADD_RRD/4)+((nADD_RRD%4) ? 1 : 0)); // take binary log to obtain counter width and add a tick for the idle cycle localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /* idle state */ 1); //*************************************************************************** // Internal signals //*************************************************************************** reg act_this_rank; integer i; // loop invariant //*************************************************************************** // Function clogb2 // Description: // This function performs binary logarithm and rounds up // Inputs: // size: integer to perform binary log upon // Outputs: // clogb2: result of binary logarithm, rounded up //*************************************************************************** function integer clogb2 (input integer size); begin size = size - 1; // increment clogb2 from 1 for each bit in size for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1) size = size >> 1; end endfunction // clogb2 //*************************************************************************** // Determine if this rank has been activated. act_this_rank_r is a // registered bit vector from individual bank machines indicating the // corresponding bank machine is sending // an activate. Timing is improved with this method. //*************************************************************************** always @(/*AS*/act_this_rank_r or sending_row) begin act_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) act_this_rank = act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]); end reg add_rrd_inhbt = 1'b0; generate if (nADD_RRD > 0 && ADD_RRD_CNTR_WIDTH > 1) begin :add_rdd1 reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns; reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r; always @(/*AS*/act_this_rank or add_rrd_r or rst) begin add_rrd_ns = add_rrd_r; if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}}; else if (act_this_rank) add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH]; else if (|add_rrd_r) add_rrd_ns = add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1}; end always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns; always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns; end // add_rdd1 else if (nADD_RRD > 0) begin :add_rdd0 reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns; reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r; always @(/*AS*/act_this_rank or add_rrd_r or rst) begin add_rrd_ns = add_rrd_r; if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}}; else if (act_this_rank) add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH]; else if (|add_rrd_r) add_rrd_ns = add_rrd_r - {1'b1}; end always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns; always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns; end // add_rdd0 endgenerate // Compute inhbt_act_faw_r. Only allow a limited number of activates // in a window. Both the number of activates and the window are // configurable. This depends on the RRD mechanism to prevent // two consecutive activates to the same rank. // // Subtract three from the specified nFAW. Subtract three because: // -Zero for the delay into the SRL is really one state. // -Sending_row is used to trigger the delay. Sending_row is one // state delayed from the arb. // -inhbt_act_faw_r is registered to make timing work, hence the // generation needs to be one state early. localparam nFAW_CLKS = (nCK_PER_CLK == 1) ? nFAW : (nCK_PER_CLK == 2) ? ((nFAW/2) + (nFAW%2)) : ((nFAW/4) + ((nFAW%4) ? 1 : 0)); generate begin : inhbt_act_faw wire act_delayed; wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3; SRLC32E #(.INIT(32'h00000000) ) SRLC32E0 (.Q(act_delayed), // SRL data output .Q31(), // SRL cascade output pin .A(shift_depth), // 5-bit shift depth select input .CE(1'b1), // Clock enable input .CLK(clk), // Clock input .D(act_this_rank) // SRL data input ); reg [2:0] faw_cnt_ns; reg [2:0] faw_cnt_r; reg inhbt_act_faw_ns; always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt or faw_cnt_r or rst) begin if (rst) faw_cnt_ns = 3'b0; else begin faw_cnt_ns = faw_cnt_r; if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1; if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1; end inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt; end always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns; always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns; end // block: inhbt_act_faw endgenerate // In the DRAM spec, tWTR starts from CK following the end of the data // burst. Since we don't directly have that spec, the wtr timer is // based on when the CAS write command is sent to the DRAM. // // To compute the wtr timer value, first compute the time from the write command // to the read command. This is CWL + data_time + nWTR. // // Two is subtracted from the required wtr time since the timer // starts two states after the arbitration cycle. localparam ONE = 1; localparam TWO = 2; localparam CASWR2CASRD = CWL + (BURST_MODE == "4" ? 2 : 4) + nWTR; localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1) ? CASWR2CASRD : (nCK_PER_CLK == 2) ? ((CASWR2CASRD / 2) + (CASWR2CASRD % 2)) : ((CASWR2CASRD / 4) + ((CASWR2CASRD % 4) ? 1 :0)); localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS); generate begin : wtr_timer reg write_this_rank; always @(/*AS*/sending_col or wr_this_rank_r) begin write_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) write_this_rank = write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]); end reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r; reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns; always @(/*AS*/rst or write_this_rank or wtr_cnt_r) if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}}; else begin wtr_cnt_ns = wtr_cnt_r; if (write_this_rank) wtr_cnt_ns = CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - ONE[WTR_CNT_WIDTH-1:0]; else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0]; end wire inhbt_rd_ns = |wtr_cnt_ns; always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns; always @(inhbt_rd_ns) inhbt_rd = inhbt_rd_ns; end endgenerate // In the DRAM spec (with AL = 0), the read-to-write command delay is implied to // be CL + data_time + 2 tCK - CWL. The CL + data_time - CWL terms ensure the // read and write data do not collide on the DQ bus. The 2 tCK ensures a gap // between them. Here, we allow the user to tune this fixed term via the // DQRD2DQWR_DLY parameter. There's a potential for optimization by relocating // this to the rank_common module, since this is a DQ/DQS bus-level requirement, // not a per-rank requirement. localparam CASRD2CASWR = CL + (BURST_MODE == "4" ? 2 : 4) + DQRD2DQWR_DLY - CWL; localparam CASRD2CASWR_CLKS = (nCK_PER_CLK == 1) ? CASRD2CASWR : (nCK_PER_CLK == 2) ? ((CASRD2CASWR / 2) + (CASRD2CASWR % 2)) : ((CASRD2CASWR / 4) + ((CASRD2CASWR % 4) ? 1 :0)); localparam RTW_CNT_WIDTH = clogb2(CASRD2CASWR_CLKS); generate begin : rtw_timer reg read_this_rank; always @(/*AS*/sending_col or rd_this_rank_r) begin read_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) read_this_rank = read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]); end reg [RTW_CNT_WIDTH-1:0] rtw_cnt_r; reg [RTW_CNT_WIDTH-1:0] rtw_cnt_ns; always @(/*AS*/rst or col_rd_wr or sending_col or rtw_cnt_r) if (rst) rtw_cnt_ns = {RTW_CNT_WIDTH{1'b0}}; else begin rtw_cnt_ns = rtw_cnt_r; if (col_rd_wr && |sending_col) rtw_cnt_ns = CASRD2CASWR_CLKS[RTW_CNT_WIDTH-1:0] - ONE[RTW_CNT_WIDTH-1:0]; else if (|rtw_cnt_r) rtw_cnt_ns = rtw_cnt_r - ONE[RTW_CNT_WIDTH-1:0]; end wire inhbt_wr_ns = |rtw_cnt_ns; always @(posedge clk) rtw_cnt_r <= #TCQ rtw_cnt_ns; always @(inhbt_wr_ns) inhbt_wr = inhbt_wr_ns; end endgenerate // Refresh request generation. Implement a "refresh bank". Referred // to as pullin-in refresh in the JEDEC spec. // The refresh_rank_r counter increments when a refresh to this // rank has been decoded. In the up direction, the count saturates // at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK // is normally eight. The counter decrements with each refresh_tick, // saturating at zero. A refresh will be requests when the rank is // not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r // equals zero. localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1); generate begin : refresh_generation reg my_rank_busy; always @(/*AS*/rank_busy_r) begin my_rank_busy = 1'b0; for (i=0; i < nBANK_MACHS; i=i+1) my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID]; end wire my_refresh = insert_maint_r1 && ~maint_zq_r && ~maint_sre_r && ~maint_srx_r && (maint_rank_r == ID[RANK_WIDTH-1:0]); reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r; reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns; always @(/*AS*/app_ref_req or init_calib_complete or my_refresh or refresh_bank_r or refresh_tick) if (~init_calib_complete) if (REFRESH_TIMER_DIV == 0) refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]; else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}}; else case ({my_refresh, refresh_tick, app_ref_req}) 3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r; 3'b010, 3'b001, 3'b011 : refresh_bank_ns = (|refresh_bank_r)? refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]: refresh_bank_r; 3'b100 : refresh_bank_ns = refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH]; endcase // case ({my_refresh, refresh_tick}) always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns; `ifdef MC_SVA refresh_bank_overflow: assert property (@(posedge clk) (rst || (refresh_bank_r <= nREFRESH_BANK))); refresh_bank_underflow: assert property (@(posedge clk) (rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick))); refresh_hi_priority: cover property (@(posedge clk) (rst && ~|refresh_bank_ns && (refresh_bank_r == ONE[0+:REFRESH_BANK_WIDTH]))); refresh_bank_full: cover property (@(posedge clk) (rst && (refresh_bank_r == nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]))); `endif assign refresh_request = init_calib_complete && (~|refresh_bank_r || ((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy)); end endgenerate // Periodic read request generation. localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1); generate begin : periodic_rd_generation if ( PERIODIC_RD_TIMER_DIV != 0 ) begin // enable periodic reads reg read_this_rank; always @(/*AS*/rd_this_rank_r or sending_col) begin read_this_rank = 1'b0; for (i = 0; i < nBANK_MACHS; i = i + 1) read_this_rank = read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]); end reg read_this_rank_r; reg read_this_rank_r1; always @(posedge clk) read_this_rank_r <= #TCQ read_this_rank; always @(posedge clk) read_this_rank_r1 <= #TCQ read_this_rank_r; wire int_read_this_rank = read_this_rank && (((nCK_PER_CLK == 4) && read_this_rank_r) || ((nCK_PER_CLK != 4) && read_this_rank_r1)); reg periodic_rd_cntr1_ns; reg periodic_rd_cntr1_r; always @(/*AS*/clear_periodic_rd_request or periodic_rd_cntr1_r) begin periodic_rd_cntr1_ns = periodic_rd_cntr1_r; if (clear_periodic_rd_request) periodic_rd_cntr1_ns = periodic_rd_cntr1_r + 1'b1; end always @(posedge clk) begin if (rst) periodic_rd_cntr1_r <= #TCQ 1'b0; else periodic_rd_cntr1_r <= #TCQ periodic_rd_cntr1_ns; end reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r; reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns; always @(/*AS*/init_calib_complete or maint_prescaler_tick_r or periodic_rd_timer_r or int_read_this_rank) begin periodic_rd_timer_ns = periodic_rd_timer_r; if (~init_calib_complete) periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}}; else if (int_read_this_rank) periodic_rd_timer_ns = PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH]; else if (|periodic_rd_timer_r && maint_prescaler_tick_r) periodic_rd_timer_ns = periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH]; end always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns; wire periodic_rd_timer_one = maint_prescaler_tick_r && (periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]); reg periodic_rd_request_r; wire periodic_rd_request_ns = ~rst && ((app_periodic_rd_req && init_calib_complete) || ((PERIODIC_RD_TIMER_DIV != 0) && ~init_calib_complete) || // (~(read_this_rank || clear_periodic_rd_request) && (~((int_read_this_rank) || (clear_periodic_rd_request && periodic_rd_cntr1_r)) && (periodic_rd_request_r || periodic_rd_timer_one))); always @(posedge clk) periodic_rd_request_r <= #TCQ periodic_rd_request_ns; `ifdef MC_SVA read_clears_periodic_rd_request: cover property (@(posedge clk) (rst && (periodic_rd_request_r && read_this_rank))); `endif assign periodic_rd_request = init_calib_complete && periodic_rd_request_r; end else assign periodic_rd_request = 1'b0; //to disable periodic reads end endgenerate endmodule
//***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_rdlvl.v // /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Read leveling Stage1 calibration logic // NOTES: // 1. Window detection with PRBS pattern. //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $ **$Date: 2011/06/24 14:49:00 $ **$Author: mgeorge $ **$Revision: 1.2 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_rdlvl.v,v $ ******************************************************************************/ `timescale 1ps/1ps (* use_dsp48 = "no" *) module mig_7series_v2_3_ddr_phy_rdlvl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter CLK_PERIOD = 3333, // Internal clock period (in ps) parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter RANKS = 1, // # of DRAM ranks parameter PER_BIT_DESKEW = "ON", // Enable per-bit DQ deskew parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps parameter DEBUG_PORT = "OFF", // Enable debug port parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" parameter OCAL_EN = "ON", parameter IDELAY_ADJ = "ON" ) ( input clk, input rst, // Calibration status, control signals input mpr_rdlvl_start, output mpr_rdlvl_done, output reg mpr_last_byte_done, output mpr_rnk_done, input rdlvl_stg1_start, output reg rdlvl_stg1_done /* synthesis syn_maxfan = 30 */, output rdlvl_stg1_rnk_done, output reg rdlvl_stg1_err, output mpr_rdlvl_err, output rdlvl_err, output reg rdlvl_prech_req, output reg rdlvl_last_byte_done, output reg rdlvl_assrt_common, input prech_done, input phy_if_empty, input [4:0] idelaye2_init_val, // Captured data in fabric clock domain input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Decrement initial Phaser_IN Fine tap delay input dqs_po_dec_done, input [5:0] pi_counter_read_val, // Stage 1 calibration outputs output reg pi_fine_dly_dec_done, output reg pi_en_stg2_f, output reg pi_stg2_f_incdec, output reg pi_stg2_load, output reg [5:0] pi_stg2_reg_l, output [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt, // To DQ IDELAY required to find left edge of // valid window output idelay_ce, output idelay_inc, input idelay_ld, input [DQS_CNT_WIDTH:0] wrcal_cnt, // Only output if Per-bit de-skew enabled output reg [5*RANKS*DQ_WIDTH-1:0] dlyval_dq, // Debug Port output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, input dbg_idel_up_all, input dbg_idel_down_all, input dbg_idel_up_cpt, input dbg_idel_down_cpt, input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, input dbg_sel_all_idel_cpt, output [255:0] dbg_phy_rdlvl ); // minimum time (in IDELAY taps) for which capture data must be stable for // algorithm to consider a valid data eye to be found. The read leveling // logic will ignore any window found smaller than this value. Limitations // on how small this number can be is determined by: (1) the algorithmic // limitation of how many taps wide the data eye can be (3 taps), and (2) // how wide regions of "instability" that occur around the edges of the // read valid window can be (i.e. need to be able to filter out "false" // windows that occur for a short # of taps around the edges of the true // data window, although with multi-sampling during read leveling, this is // not as much a concern) - the larger the value, the more protection // against "false" windows localparam MIN_EYE_SIZE = 16; // Length of calibration sequence (in # of words) localparam CAL_PAT_LEN = 8; // Read data shift register length localparam RD_SHIFT_LEN = CAL_PAT_LEN / (2*nCK_PER_CLK); // # of cycles required to perform read data shift register compare // This is defined as from the cycle the new data is loaded until // signal found_edge_r is valid localparam RD_SHIFT_COMP_DELAY = 5; // worst-case # of cycles to wait to ensure that both the SR and // PREV_SR shift registers have valid data, and that the comparison // of the two shift register values is valid. The "+1" at the end of // this equation is a fudge factor, I freely admit that localparam SR_VALID_DELAY = (2 * RD_SHIFT_LEN) + RD_SHIFT_COMP_DELAY + 1; // # of clock cycles to wait after changing tap value or read data MUX // to allow: (1) tap chain to settle, (2) for delayed input to propagate // thru ISERDES, (3) for the read data comparison logic to have time to // output the comparison of two consecutive samples of the settled read data // The minimum delay is 16 cycles, which should be good enough to handle all // three of the above conditions for the simulation-only case with a short // training pattern. For H/W (or for simulation with longer training // pattern), it will take longer to store and compare two consecutive // samples, and the value of this parameter will reflect that localparam PIPE_WAIT_CNT = (SR_VALID_DELAY < 8) ? 16 : (SR_VALID_DELAY + 8); // # of read data samples to examine when detecting whether an edge has // occured during stage 1 calibration. Width of local param must be // changed as appropriate. Note that there are two counters used, each // counter can be changed independently of the other - they are used in // cascade to create a larger counter localparam [11:0] DETECT_EDGE_SAMPLE_CNT0 = 12'h001; //12'hFFF; localparam [11:0] DETECT_EDGE_SAMPLE_CNT1 = 12'h001; // 12'h1FF Must be > 0 localparam [5:0] CAL1_IDLE = 6'h00; localparam [5:0] CAL1_NEW_DQS_WAIT = 6'h01; localparam [5:0] CAL1_STORE_FIRST_WAIT = 6'h02; localparam [5:0] CAL1_PAT_DETECT = 6'h03; localparam [5:0] CAL1_DQ_IDEL_TAP_INC = 6'h04; localparam [5:0] CAL1_DQ_IDEL_TAP_INC_WAIT = 6'h05; localparam [5:0] CAL1_DQ_IDEL_TAP_DEC = 6'h06; localparam [5:0] CAL1_DQ_IDEL_TAP_DEC_WAIT = 6'h07; localparam [5:0] CAL1_DETECT_EDGE = 6'h08; localparam [5:0] CAL1_IDEL_INC_CPT = 6'h09; localparam [5:0] CAL1_IDEL_INC_CPT_WAIT = 6'h0A; localparam [5:0] CAL1_CALC_IDEL = 6'h0B; localparam [5:0] CAL1_IDEL_DEC_CPT = 6'h0C; localparam [5:0] CAL1_IDEL_DEC_CPT_WAIT = 6'h0D; localparam [5:0] CAL1_NEXT_DQS = 6'h0E; localparam [5:0] CAL1_DONE = 6'h0F; localparam [5:0] CAL1_PB_STORE_FIRST_WAIT = 6'h10; localparam [5:0] CAL1_PB_DETECT_EDGE = 6'h11; localparam [5:0] CAL1_PB_INC_CPT = 6'h12; localparam [5:0] CAL1_PB_INC_CPT_WAIT = 6'h13; localparam [5:0] CAL1_PB_DEC_CPT_LEFT = 6'h14; localparam [5:0] CAL1_PB_DEC_CPT_LEFT_WAIT = 6'h15; localparam [5:0] CAL1_PB_DETECT_EDGE_DQ = 6'h16; localparam [5:0] CAL1_PB_INC_DQ = 6'h17; localparam [5:0] CAL1_PB_INC_DQ_WAIT = 6'h18; localparam [5:0] CAL1_PB_DEC_CPT = 6'h19; localparam [5:0] CAL1_PB_DEC_CPT_WAIT = 6'h1A; localparam [5:0] CAL1_REGL_LOAD = 6'h1B; localparam [5:0] CAL1_RDLVL_ERR = 6'h1C; localparam [5:0] CAL1_MPR_NEW_DQS_WAIT = 6'h1D; localparam [5:0] CAL1_VALID_WAIT = 6'h1E; localparam [5:0] CAL1_MPR_PAT_DETECT = 6'h1F; localparam [5:0] CAL1_NEW_DQS_PREWAIT = 6'h20; integer a; integer b; integer d; integer e; integer f; integer h; integer g; integer i; integer j; integer k; integer l; integer m; integer n; integer r; integer p; integer q; integer s; integer t; integer u; integer w; integer ce_i; integer ce_rnk_i; integer aa; integer bb; integer cc; integer dd; genvar x; genvar z; reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_r; wire [DQS_CNT_WIDTH+2:0]cal1_cnt_cpt_timing; reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_timing_r; reg cal1_dq_idel_ce; reg cal1_dq_idel_inc; reg cal1_dlyce_cpt_r; reg cal1_dlyinc_cpt_r; reg cal1_dlyce_dq_r; reg cal1_dlyinc_dq_r; reg cal1_wait_cnt_en_r; reg [4:0] cal1_wait_cnt_r; reg cal1_wait_r; reg [DQ_WIDTH-1:0] dlyce_dq_r; reg dlyinc_dq_r; reg [4:0] dlyval_dq_reg_r [0:RANKS-1][0:DQ_WIDTH-1]; reg cal1_prech_req_r; reg [5:0] cal1_state_r; reg [5:0] cal1_state_r1; reg [5:0] cnt_idel_dec_cpt_r; reg [3:0] cnt_shift_r; reg detect_edge_done_r; reg [5:0] right_edge_taps_r; reg [5:0] first_edge_taps_r; reg found_edge_r; reg found_first_edge_r; reg found_second_edge_r; reg found_stable_eye_r; reg found_stable_eye_last_r; reg found_edge_all_r; reg [5:0] tap_cnt_cpt_r; reg tap_limit_cpt_r; reg [4:0] idel_tap_cnt_dq_pb_r; reg idel_tap_limit_dq_pb_r; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r; reg mux_rd_valid_r; reg new_cnt_cpt_r; reg [RD_SHIFT_LEN-1:0] old_sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise3_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] old_sr_match_fall0_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall1_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise0_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise1_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall2_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall3_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise2_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise3_r; reg [4:0] pb_cnt_eye_size_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] pb_detect_edge_done_r; reg [DRAM_WIDTH-1:0] pb_found_edge_last_r; reg [DRAM_WIDTH-1:0] pb_found_edge_r; reg [DRAM_WIDTH-1:0] pb_found_first_edge_r; reg [DRAM_WIDTH-1:0] pb_found_stable_eye_r; reg [DRAM_WIDTH-1:0] pb_last_tap_jitter_r; reg pi_en_stg2_f_timing; reg pi_stg2_f_incdec_timing; reg pi_stg2_load_timing; reg [5:0] pi_stg2_reg_l_timing; reg [DRAM_WIDTH-1:0] prev_sr_diff_r; reg [RD_SHIFT_LEN-1:0] prev_sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise3_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] prev_sr_match_cyc2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall0_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall1_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise0_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise1_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall3_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise3_r; wire [DQ_WIDTH-1:0] rd_data_rise0; wire [DQ_WIDTH-1:0] rd_data_fall0; wire [DQ_WIDTH-1:0] rd_data_rise1; wire [DQ_WIDTH-1:0] rd_data_fall1; wire [DQ_WIDTH-1:0] rd_data_rise2; wire [DQ_WIDTH-1:0] rd_data_fall2; wire [DQ_WIDTH-1:0] rd_data_rise3; wire [DQ_WIDTH-1:0] rd_data_fall3; reg samp_cnt_done_r; reg samp_edge_cnt0_en_r; reg [11:0] samp_edge_cnt0_r; reg samp_edge_cnt1_en_r; reg [11:0] samp_edge_cnt1_r; reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; reg [5:0] second_edge_taps_r; reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0]; reg store_sr_r; reg store_sr_req_pulsed_r; reg store_sr_req_r; reg sr_valid_r; reg sr_valid_r1; reg sr_valid_r2; reg [DRAM_WIDTH-1:0] old_sr_diff_r; reg [DRAM_WIDTH-1:0] old_sr_match_cyc2_r; reg pat0_data_match_r; reg pat1_data_match_r; wire pat_data_match_r; wire [RD_SHIFT_LEN-1:0] pat0_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall3 [3:0]; reg [DRAM_WIDTH-1:0] pat0_match_fall0_r; reg pat0_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall1_r; reg pat0_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall2_r; reg pat0_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall3_r; reg pat0_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise0_r; reg pat0_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise1_r; reg pat0_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise2_r; reg pat0_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise3_r; reg pat0_match_rise3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall0_r; reg pat1_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall1_r; reg pat1_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall2_r; reg pat1_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall3_r; reg pat1_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise0_r; reg pat1_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise1_r; reg pat1_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise2_r; reg pat1_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise3_r; reg pat1_match_rise3_and_r; reg [4:0] idelay_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1]; reg [5*DQS_WIDTH*RANKS-1:0] idelay_tap_cnt_w; reg [4:0] idelay_tap_cnt_slice_r; reg idelay_tap_limit_r; wire [RD_SHIFT_LEN-1:0] pat0_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall3 [3:0]; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise0_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall0_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise1_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall1_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise2_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall2_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise3_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall3_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise0_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall0_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise1_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall1_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise2_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall2_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise3_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall3_r; reg idel_pat0_match_rise0_and_r; reg idel_pat0_match_fall0_and_r; reg idel_pat0_match_rise1_and_r; reg idel_pat0_match_fall1_and_r; reg idel_pat0_match_rise2_and_r; reg idel_pat0_match_fall2_and_r; reg idel_pat0_match_rise3_and_r; reg idel_pat0_match_fall3_and_r; reg idel_pat1_match_rise0_and_r; reg idel_pat1_match_fall0_and_r; reg idel_pat1_match_rise1_and_r; reg idel_pat1_match_fall1_and_r; reg idel_pat1_match_rise2_and_r; reg idel_pat1_match_fall2_and_r; reg idel_pat1_match_rise3_and_r; reg idel_pat1_match_fall3_and_r; reg idel_pat0_data_match_r; reg idel_pat1_data_match_r; reg idel_pat_data_match; reg idel_pat_data_match_r; reg [4:0] idel_dec_cnt; reg [5:0] rdlvl_dqs_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1]; reg [1:0] rnk_cnt_r; reg rdlvl_rank_done_r; reg [3:0] done_cnt; reg [1:0] regl_rank_cnt; reg [DQS_CNT_WIDTH:0] regl_dqs_cnt; reg [DQS_CNT_WIDTH:0] regl_dqs_cnt_r; wire [DQS_CNT_WIDTH+2:0]regl_dqs_cnt_timing; reg regl_rank_done_r; reg rdlvl_stg1_start_r; reg dqs_po_dec_done_r1; reg dqs_po_dec_done_r2; reg fine_dly_dec_done_r1; reg fine_dly_dec_done_r2; reg [3:0] wait_cnt_r; reg [5:0] pi_rdval_cnt; reg pi_cnt_dec; reg mpr_valid_r; reg mpr_valid_r1; reg mpr_valid_r2; reg mpr_rd_rise0_prev_r; reg mpr_rd_fall0_prev_r; reg mpr_rd_rise1_prev_r; reg mpr_rd_fall1_prev_r; reg mpr_rd_rise2_prev_r; reg mpr_rd_fall2_prev_r; reg mpr_rd_rise3_prev_r; reg mpr_rd_fall3_prev_r; reg mpr_rdlvl_done_r; reg mpr_rdlvl_done_r1; reg mpr_rdlvl_done_r2; reg mpr_rdlvl_start_r; reg mpr_rank_done_r; reg [2:0] stable_idel_cnt; reg inhibit_edge_detect_r; reg idel_pat_detect_valid_r; reg idel_mpr_pat_detect_r; reg mpr_pat_detect_r; reg mpr_dec_cpt_r; reg idel_adj_inc; //IDELAY adjustment wire [1:0] idelay_adj; wire pb_detect_edge_setup; wire pb_detect_edge; // Debug reg [6*DQS_WIDTH-1:0] dbg_cpt_first_edge_taps; reg [6*DQS_WIDTH-1:0] dbg_cpt_second_edge_taps; reg [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt_w; //IDELAY adjustment setting for -1 //2'b10 : IDELAY - 1 //2'b01 : IDELAY + 1 //2'b00 : No IDELAY adjustment assign idelay_adj = (IDELAY_ADJ == "ON") ? 2'b10: 2'b00; //*************************************************************************** // Debug //*************************************************************************** always @(*) begin for (d = 0; d < RANKS; d = d + 1) begin for (e = 0; e < DQS_WIDTH; e = e + 1) begin idelay_tap_cnt_w[(5*e+5*DQS_WIDTH*d)+:5] = idelay_tap_cnt_r[d][e]; dbg_cpt_tap_cnt_w[(6*e+6*DQS_WIDTH*d)+:6] = rdlvl_dqs_tap_cnt_r[d][e]; end end end assign mpr_rdlvl_err = rdlvl_stg1_err & (!mpr_rdlvl_done); assign rdlvl_err = rdlvl_stg1_err & (mpr_rdlvl_done); assign dbg_phy_rdlvl[0] = rdlvl_stg1_start; assign dbg_phy_rdlvl[1] = pat_data_match_r; assign dbg_phy_rdlvl[2] = mux_rd_valid_r; assign dbg_phy_rdlvl[3] = idelay_tap_limit_r; assign dbg_phy_rdlvl[8:4] = 'b0; assign dbg_phy_rdlvl[14:9] = cal1_state_r[5:0]; assign dbg_phy_rdlvl[20:15] = cnt_idel_dec_cpt_r; assign dbg_phy_rdlvl[21] = found_first_edge_r; assign dbg_phy_rdlvl[22] = found_second_edge_r; assign dbg_phy_rdlvl[23] = found_edge_r; assign dbg_phy_rdlvl[24] = store_sr_r; // [40:25] previously used for sr, old_sr shift registers. If connecting // these signals again, don't forget to parameterize based on RD_SHIFT_LEN assign dbg_phy_rdlvl[40:25] = 'b0; assign dbg_phy_rdlvl[41] = sr_valid_r; assign dbg_phy_rdlvl[42] = found_stable_eye_r; assign dbg_phy_rdlvl[48:43] = tap_cnt_cpt_r; assign dbg_phy_rdlvl[54:49] = first_edge_taps_r; assign dbg_phy_rdlvl[60:55] = second_edge_taps_r; assign dbg_phy_rdlvl[64:61] = cal1_cnt_cpt_timing_r; assign dbg_phy_rdlvl[65] = cal1_dlyce_cpt_r; assign dbg_phy_rdlvl[66] = cal1_dlyinc_cpt_r; assign dbg_phy_rdlvl[67] = found_edge_r; assign dbg_phy_rdlvl[68] = found_first_edge_r; assign dbg_phy_rdlvl[73:69] = 'b0; assign dbg_phy_rdlvl[74] = idel_pat_data_match; assign dbg_phy_rdlvl[75] = idel_pat0_data_match_r; assign dbg_phy_rdlvl[76] = idel_pat1_data_match_r; assign dbg_phy_rdlvl[77] = pat0_data_match_r; assign dbg_phy_rdlvl[78] = pat1_data_match_r; assign dbg_phy_rdlvl[79+:5*DQS_WIDTH*RANKS] = idelay_tap_cnt_w; assign dbg_phy_rdlvl[170+:8] = mux_rd_rise0_r; assign dbg_phy_rdlvl[178+:8] = mux_rd_fall0_r; assign dbg_phy_rdlvl[186+:8] = mux_rd_rise1_r; assign dbg_phy_rdlvl[194+:8] = mux_rd_fall1_r; assign dbg_phy_rdlvl[202+:8] = mux_rd_rise2_r; assign dbg_phy_rdlvl[210+:8] = mux_rd_fall2_r; assign dbg_phy_rdlvl[218+:8] = mux_rd_rise3_r; assign dbg_phy_rdlvl[226+:8] = mux_rd_fall3_r; //*************************************************************************** // Debug output //*************************************************************************** // CPT taps assign dbg_cpt_first_edge_cnt = dbg_cpt_first_edge_taps; assign dbg_cpt_second_edge_cnt = dbg_cpt_second_edge_taps; assign dbg_cpt_tap_cnt = dbg_cpt_tap_cnt_w; assign dbg_dq_idelay_tap_cnt = idelay_tap_cnt_w; // Record first and second edges found during CPT calibration generate always @(posedge clk) if (rst) begin dbg_cpt_first_edge_taps <= #TCQ 'b0; dbg_cpt_second_edge_taps <= #TCQ 'b0; end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_CALC_IDEL)) begin //for (ce_rnk_i = 0; ce_rnk_i < RANKS; ce_rnk_i = ce_rnk_i + 1) begin: gen_dbg_cpt_rnk for (ce_i = 0; ce_i < DQS_WIDTH; ce_i = ce_i + 1) begin: gen_dbg_cpt_edge if (found_first_edge_r) dbg_cpt_first_edge_taps[(6*ce_i)+:6] <= #TCQ first_edge_taps_r; if (found_second_edge_r) dbg_cpt_second_edge_taps[(6*ce_i)+:6] <= #TCQ second_edge_taps_r; end //end end else if (cal1_state_r == CAL1_CALC_IDEL) begin // Record tap counts of first and second edge edges during // CPT calibration for each DQS group. If neither edge has // been found, then those taps will remain 0 if (found_first_edge_r) dbg_cpt_first_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6] <= #TCQ first_edge_taps_r; if (found_second_edge_r) dbg_cpt_second_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6] <= #TCQ second_edge_taps_r; end endgenerate assign rdlvl_stg1_rnk_done = rdlvl_rank_done_r;// || regl_rank_done_r; assign mpr_rnk_done = mpr_rank_done_r; assign mpr_rdlvl_done = ((DRAM_TYPE == "DDR3") && (OCAL_EN == "ON")) ? //&& (SIM_CAL_OPTION == "NONE") mpr_rdlvl_done_r : 1'b1; //************************************************************************** // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 // coarse delay //************************************************************************** assign pi_stg2_rdlvl_cnt = (cal1_state_r == CAL1_REGL_LOAD) ? regl_dqs_cnt_r : cal1_cnt_cpt_r; assign idelay_ce = cal1_dq_idel_ce; assign idelay_inc = cal1_dq_idel_inc; //*************************************************************************** // Assert calib_in_common in FAST_CAL mode for IDELAY tap increments to all // DQs simultaneously //*************************************************************************** always @(posedge clk) begin if (rst) rdlvl_assrt_common <= #TCQ 1'b0; else if ((SIM_CAL_OPTION == "FAST_CAL") & rdlvl_stg1_start & !rdlvl_stg1_start_r) rdlvl_assrt_common <= #TCQ 1'b1; else if (!idel_pat_data_match_r & idel_pat_data_match) rdlvl_assrt_common <= #TCQ 1'b0; end //*************************************************************************** // Data mux to route appropriate bit to calibration logic - i.e. calibration // is done sequentially, one bit (or DQS group) at a time //*************************************************************************** generate if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; end else begin: rd_data_div2_logic_clk assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; end endgenerate always @(posedge clk) begin rd_mux_sel_r <= #TCQ cal1_cnt_cpt_r; end // Register outputs for improved timing. // NOTE: Will need to change when per-bit DQ deskew is supported. // Currenly all bits in DQS group are checked in aggregate generate genvar mux_i; for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end endgenerate //*************************************************************************** // MPR Read Leveling //*************************************************************************** // storing the previous read data for checking later. Only bit 0 is used // since MPR contents (01010101) are available generally on DQ[0] per // JEDEC spec. always @(posedge clk)begin if ((cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) || ((cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r)))begin mpr_rd_rise0_prev_r <= #TCQ mux_rd_rise0_r[0]; mpr_rd_fall0_prev_r <= #TCQ mux_rd_fall0_r[0]; mpr_rd_rise1_prev_r <= #TCQ mux_rd_rise1_r[0]; mpr_rd_fall1_prev_r <= #TCQ mux_rd_fall1_r[0]; mpr_rd_rise2_prev_r <= #TCQ mux_rd_rise2_r[0]; mpr_rd_fall2_prev_r <= #TCQ mux_rd_fall2_r[0]; mpr_rd_rise3_prev_r <= #TCQ mux_rd_rise3_r[0]; mpr_rd_fall3_prev_r <= #TCQ mux_rd_fall3_r[0]; end end generate if (nCK_PER_CLK == 4) begin: mpr_4to1 // changed stable count of 2 IDELAY taps at 78 ps resolution always @(posedge clk) begin if (rst | (cal1_state_r == CAL1_NEW_DQS_PREWAIT) | //(cal1_state_r == CAL1_DETECT_EDGE) | (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) | (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) | (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) | (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) | (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) | (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) | (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) | (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0])) stable_idel_cnt <= #TCQ 3'd0; else if ((|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) & ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) begin if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) & (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) & (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) & (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) & (mpr_rd_rise2_prev_r == mux_rd_rise2_r[0]) & (mpr_rd_fall2_prev_r == mux_rd_fall2_r[0]) & (mpr_rd_rise3_prev_r == mux_rd_rise3_r[0]) & (mpr_rd_fall3_prev_r == mux_rd_fall3_r[0]) & (stable_idel_cnt < 3'd2)) stable_idel_cnt <= #TCQ stable_idel_cnt + 1; end end always @(posedge clk) begin if (rst | (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r & mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r & mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r)) inhibit_edge_detect_r <= 1'b1; // Wait for settling time after idelay tap increment before // de-asserting inhibit_edge_detect_r else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) & (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r & ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r & ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r)) inhibit_edge_detect_r <= 1'b0; end //checking for transition from 01010101 to 10101010 always @(posedge clk)begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | inhibit_edge_detect_r) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 10101010 is not the correct pattern else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r & mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r & mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r) || ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r))) //|| (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2)) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 01010101 to 10101010 is the correct transition else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r & ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r & ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r) & (stable_idel_cnt == 3'd2) & ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) || (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) || (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) || (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) || (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) || (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) || (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) || (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0]))) idel_mpr_pat_detect_r <= #TCQ 1'b1; end end else if (nCK_PER_CLK == 2) begin: mpr_2to1 // changed stable count of 2 IDELAY taps at 78 ps resolution always @(posedge clk) begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) | (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) | (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) | (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0])) stable_idel_cnt <= #TCQ 3'd0; else if ((idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd0) & ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) begin if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) & (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) & (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) & (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) & (stable_idel_cnt < 3'd2)) stable_idel_cnt <= #TCQ stable_idel_cnt + 1; end end always @(posedge clk) begin if (rst | (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r)) inhibit_edge_detect_r <= 1'b1; else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) & (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r)) inhibit_edge_detect_r <= 1'b0; end //checking for transition from 01010101 to 10101010 always @(posedge clk)begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | inhibit_edge_detect_r) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 1010 is not the correct pattern else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r) || ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) // ||(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2)) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 0101 to 1010 is the correct transition else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r) & (stable_idel_cnt == 3'd2) & ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) || (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) || (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) || (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]))) idel_mpr_pat_detect_r <= #TCQ 1'b1; end end endgenerate // Registered signal indicates when mux_rd_rise/fall_r is valid always @(posedge clk) mux_rd_valid_r <= #TCQ ~phy_if_empty; //*************************************************************************** // Decrement initial Phaser_IN fine delay value before proceeding with // read calibration //*************************************************************************** always @(posedge clk) begin dqs_po_dec_done_r1 <= #TCQ dqs_po_dec_done; dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1; fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1; pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r2; end always @(posedge clk) begin if (rst || pi_cnt_dec) wait_cnt_r <= #TCQ 'd8; else if (dqs_po_dec_done_r2 && (wait_cnt_r > 'd0)) wait_cnt_r <= #TCQ wait_cnt_r - 1; end always @(posedge clk) begin if (rst) begin pi_rdval_cnt <= #TCQ 'd0; end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin pi_rdval_cnt <= #TCQ pi_counter_read_val; end else if (pi_rdval_cnt > 'd0) begin if (pi_cnt_dec) pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1; else pi_rdval_cnt <= #TCQ pi_rdval_cnt; end else if (pi_rdval_cnt == 'd0) begin pi_rdval_cnt <= #TCQ pi_rdval_cnt; end end always @(posedge clk) begin if (rst || (pi_rdval_cnt == 'd0)) pi_cnt_dec <= #TCQ 1'b0; else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0) && (wait_cnt_r == 'd1)) pi_cnt_dec <= #TCQ 1'b1; else pi_cnt_dec <= #TCQ 1'b0; end always @(posedge clk) begin if (rst) begin fine_dly_dec_done_r1 <= #TCQ 1'b0; end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) || (dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin fine_dly_dec_done_r1 <= #TCQ 1'b1; end end //*************************************************************************** // Demultiplexor to control Phaser_IN delay values //*************************************************************************** // Read DQS always @(posedge clk) begin if (rst) begin pi_en_stg2_f_timing <= #TCQ 'b0; pi_stg2_f_incdec_timing <= #TCQ 'b0; end else if (pi_cnt_dec) begin pi_en_stg2_f_timing <= #TCQ 'b1; pi_stg2_f_incdec_timing <= #TCQ 'b0; end else if (cal1_dlyce_cpt_r) begin if ((SIM_CAL_OPTION == "NONE") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin // Change only specified DQS pi_en_stg2_f_timing <= #TCQ 1'b1; pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r; end else if (SIM_CAL_OPTION == "FAST_CAL") begin // if simulating, and "shortcuts" for calibration enabled, apply // results to all DQSs (i.e. assume same delay on all // DQSs). pi_en_stg2_f_timing <= #TCQ 1'b1; pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r; end end else begin pi_en_stg2_f_timing <= #TCQ 'b0; pi_stg2_f_incdec_timing <= #TCQ 'b0; end end // registered for timing always @(posedge clk) begin pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing; pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing; end // This counter used to implement settling time between // Phaser_IN rank register loads to different DQSs always @(posedge clk) begin if (rst) done_cnt <= #TCQ 'b0; else if (((cal1_state_r == CAL1_REGL_LOAD) && (cal1_state_r1 == CAL1_NEXT_DQS)) || ((done_cnt == 4'd1) && (cal1_state_r != CAL1_DONE))) done_cnt <= #TCQ 4'b1010; else if (done_cnt > 'b0) done_cnt <= #TCQ done_cnt - 1; end // During rank register loading the rank count must be sent to // Phaser_IN via the phy_ctl_wd?? If so phy_init will have to // issue NOPs during rank register loading with the appropriate // rank count always @(posedge clk) begin if (rst || (regl_rank_done_r == 1'b1)) regl_rank_done_r <= #TCQ 1'b0; else if ((regl_dqs_cnt == DQS_WIDTH-1) && (regl_rank_cnt != RANKS-1) && (done_cnt == 4'd1)) regl_rank_done_r <= #TCQ 1'b1; end // Temp wire for timing. // The following in the always block below causes timing issues // due to DSP block inference // 6*regl_dqs_cnt. // replacing this with two left shifts + 1 left shift to avoid // DSP multiplier. assign regl_dqs_cnt_timing = {2'd0, regl_dqs_cnt}; // Load Phaser_OUT rank register with rdlvl delay value // for each DQS per rank. always @(posedge clk) begin if (rst || (done_cnt == 4'd0)) begin pi_stg2_load_timing <= #TCQ 'b0; pi_stg2_reg_l_timing <= #TCQ 'b0; end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt <= DQS_WIDTH-1) && (done_cnt == 4'd1)) begin pi_stg2_load_timing <= #TCQ 'b1; pi_stg2_reg_l_timing <= #TCQ rdlvl_dqs_tap_cnt_r[rnk_cnt_r][regl_dqs_cnt]; end else begin pi_stg2_load_timing <= #TCQ 'b0; pi_stg2_reg_l_timing <= #TCQ 'b0; end end // registered for timing always @(posedge clk) begin pi_stg2_load <= #TCQ pi_stg2_load_timing; pi_stg2_reg_l <= #TCQ pi_stg2_reg_l_timing; end always @(posedge clk) begin if (rst || (done_cnt == 4'd0) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) regl_rank_cnt <= #TCQ 2'b00; else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin if (regl_rank_cnt == RANKS-1) regl_rank_cnt <= #TCQ regl_rank_cnt; else regl_rank_cnt <= #TCQ regl_rank_cnt + 1; end end always @(posedge clk) begin if (rst || (done_cnt == 4'd0) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) regl_dqs_cnt <= #TCQ {DQS_CNT_WIDTH+1{1'b0}}; else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin if (regl_rank_cnt == RANKS-1) regl_dqs_cnt <= #TCQ regl_dqs_cnt; else regl_dqs_cnt <= #TCQ 'b0; end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt != DQS_WIDTH-1) && (done_cnt == 4'd1)) regl_dqs_cnt <= #TCQ regl_dqs_cnt + 1; else regl_dqs_cnt <= #TCQ regl_dqs_cnt; end always @(posedge clk) regl_dqs_cnt_r <= #TCQ regl_dqs_cnt; //***************************************************************** // DQ Stage 1 CALIBRATION INCREMENT/DECREMENT LOGIC: // The actual IDELAY elements for each of the DQ bits is set via the // DLYVAL parallel load port. However, the stage 1 calibration // algorithm (well most of it) only needs to increment or decrement the DQ // IDELAY value by 1 at any one time. //***************************************************************** // Chip-select generation for each of the individual counters tracking // IDELAY tap values for each DQ generate for (z = 0; z < DQS_WIDTH; z = z + 1) begin: gen_dlyce_dq always @(posedge clk) if (rst) dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; else if (SIM_CAL_OPTION == "SKIP_CAL") // If skipping calibration altogether (only for simulation), no // need to set DQ IODELAY values - they are hardcoded dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; else if (SIM_CAL_OPTION == "FAST_CAL") begin // If fast calibration option (simulation only) selected, DQ // IODELAYs across all bytes are updated simultaneously // (although per-bit deskew within DQS[0] is still supported) for (h = 0; h < DRAM_WIDTH; h = h + 1) begin dlyce_dq_r[DRAM_WIDTH*z + h] <= #TCQ cal1_dlyce_dq_r; end end else if ((SIM_CAL_OPTION == "NONE") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin if (cal1_cnt_cpt_r == z) begin for (g = 0; g < DRAM_WIDTH; g = g + 1) begin dlyce_dq_r[DRAM_WIDTH*z + g] <= #TCQ cal1_dlyce_dq_r; end end else dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; end end endgenerate // Also delay increment/decrement control to match delay on DLYCE always @(posedge clk) if (rst) dlyinc_dq_r <= #TCQ 1'b0; else dlyinc_dq_r <= #TCQ cal1_dlyinc_dq_r; // Each DQ has a counter associated with it to record current read-leveling // delay value always @(posedge clk) // Reset or skipping calibration all together if (rst | (SIM_CAL_OPTION == "SKIP_CAL")) begin for (aa = 0; aa < RANKS; aa = aa + 1) begin: rst_dlyval_dq_reg_r for (bb = 0; bb < DQ_WIDTH; bb = bb + 1) dlyval_dq_reg_r[aa][bb] <= #TCQ 'b0; end end else if (SIM_CAL_OPTION == "FAST_CAL") begin for (n = 0; n < RANKS; n = n + 1) begin: gen_dlyval_dq_reg_rnk for (r = 0; r < DQ_WIDTH; r = r + 1) begin: gen_dlyval_dq_reg if (dlyce_dq_r[r]) begin if (dlyinc_dq_r) dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] + 5'h01; else dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] - 5'h01; end end end end else begin if (dlyce_dq_r[cal1_cnt_cpt_r]) begin if (dlyinc_dq_r) dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] + 5'h01; else dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] - 5'h01; end end // Register for timing (help with logic placement) always @(posedge clk) begin for (cc = 0; cc < RANKS; cc = cc + 1) begin: dlyval_dq_assgn for (dd = 0; dd < DQ_WIDTH; dd = dd + 1) dlyval_dq[((5*dd)+(cc*DQ_WIDTH*5))+:5] <= #TCQ dlyval_dq_reg_r[cc][dd]; end end //*************************************************************************** // Generate signal used to delay calibration state machine - used when: // (1) IDELAY value changed // (2) RD_MUX_SEL value changed // Use when a delay is necessary to give the change time to propagate // through the data pipeline (through IDELAY and ISERDES, and fabric // pipeline stages) //*************************************************************************** // List all the stage 1 calibration wait states here. // verilint STARC-2.7.3.3b off always @(posedge clk) if ((cal1_state_r == CAL1_NEW_DQS_WAIT) || (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) || (cal1_state_r == CAL1_NEW_DQS_PREWAIT) || (cal1_state_r == CAL1_VALID_WAIT) || (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_INC_CPT_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT) || (cal1_state_r == CAL1_PB_INC_DQ_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_WAIT) || (cal1_state_r == CAL1_IDEL_INC_CPT_WAIT) || (cal1_state_r == CAL1_IDEL_DEC_CPT_WAIT) || (cal1_state_r == CAL1_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_DQ_IDEL_TAP_INC_WAIT) || (cal1_state_r == CAL1_DQ_IDEL_TAP_DEC_WAIT)) cal1_wait_cnt_en_r <= #TCQ 1'b1; else cal1_wait_cnt_en_r <= #TCQ 1'b0; // verilint STARC-2.7.3.3b on always @(posedge clk) if (!cal1_wait_cnt_en_r) begin cal1_wait_cnt_r <= #TCQ 5'b00000; cal1_wait_r <= #TCQ 1'b1; end else begin if (cal1_wait_cnt_r != PIPE_WAIT_CNT - 1) begin cal1_wait_cnt_r <= #TCQ cal1_wait_cnt_r + 1; cal1_wait_r <= #TCQ 1'b1; end else begin // Need to reset to 0 to handle the case when there are two // different WAIT states back-to-back cal1_wait_cnt_r <= #TCQ 5'b00000; cal1_wait_r <= #TCQ 1'b0; end end //*************************************************************************** // generate request to PHY_INIT logic to issue precharged. Required when // calibration can take a long time (during which there are only constant // reads present on this bus). In this case need to issue perioidic // precharges to avoid tRAS violation. This signal must meet the following // requirements: (1) only transition from 0->1 when prech is first needed, // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted //*************************************************************************** always @(posedge clk) if (rst) rdlvl_prech_req <= #TCQ 1'b0; else rdlvl_prech_req <= #TCQ cal1_prech_req_r; //*************************************************************************** // Serial-to-parallel register to store last RDDATA_SHIFT_LEN cycles of // data from ISERDES. The value of this register is also stored, so that // previous and current values of the ISERDES data can be compared while // varying the IODELAY taps to see if an "edge" of the data valid window // has been encountered since the last IODELAY tap adjustment //*************************************************************************** //*************************************************************************** // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES // NOTE: Written using discrete flops, but SRL can be used if the matching // logic does the comparison sequentially, rather than parallel //*************************************************************************** generate genvar rd_i; if (nCK_PER_CLK == 4) begin: gen_sr_div4 if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i]; sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i]; sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i]; sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i]; end end end end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall1_r[rd_i]}; sr_rise2_r[rd_i] <= #TCQ {sr_rise2_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise2_r[rd_i]}; sr_fall2_r[rd_i] <= #TCQ {sr_fall2_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall2_r[rd_i]}; sr_rise3_r[rd_i] <= #TCQ {sr_rise3_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise3_r[rd_i]}; sr_fall3_r[rd_i] <= #TCQ {sr_fall3_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall3_r[rd_i]}; end end end end end else if (nCK_PER_CLK == 2) begin: gen_sr_div2 if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {mux_rd_fall1_r[rd_i]}; end end end end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall1_r[rd_i]}; end end end end end endgenerate //*************************************************************************** // Conversion to pattern calibration //*************************************************************************** // Pattern for DQ IDELAY calibration //***************************************************************** // Expected data pattern when DQ shifted to the right such that // DQS before the left edge of the DVW: // Based on pattern of ({rise,fall}) = // 0x1, 0xB, 0x4, 0x4, 0xB, 0x9 // Each nibble will look like: // bit3: 0, 1, 0, 0, 1, 1 // bit2: 0, 0, 1, 1, 0, 0 // bit1: 0, 1, 0, 0, 1, 0 // bit0: 1, 1, 0, 0, 1, 1 // Or if the write is early it could look like: // 0x4, 0x4, 0xB, 0x9, 0x6, 0xE // bit3: 0, 0, 1, 1, 0, 1 // bit2: 1, 1, 0, 0, 1, 1 // bit1: 0, 0, 1, 0, 1, 1 // bit0: 0, 0, 1, 1, 0, 0 // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN // and the actual training pattern contents change //***************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_pat_div4 // Pattern for DQ IDELAY increment // Target pattern for "early write" assign {idel_pat0_rise0[3], idel_pat0_rise0[2], idel_pat0_rise0[1], idel_pat0_rise0[0]} = 4'h1; assign {idel_pat0_fall0[3], idel_pat0_fall0[2], idel_pat0_fall0[1], idel_pat0_fall0[0]} = 4'h7; assign {idel_pat0_rise1[3], idel_pat0_rise1[2], idel_pat0_rise1[1], idel_pat0_rise1[0]} = 4'hE; assign {idel_pat0_fall1[3], idel_pat0_fall1[2], idel_pat0_fall1[1], idel_pat0_fall1[0]} = 4'hC; assign {idel_pat0_rise2[3], idel_pat0_rise2[2], idel_pat0_rise2[1], idel_pat0_rise2[0]} = 4'h9; assign {idel_pat0_fall2[3], idel_pat0_fall2[2], idel_pat0_fall2[1], idel_pat0_fall2[0]} = 4'h2; assign {idel_pat0_rise3[3], idel_pat0_rise3[2], idel_pat0_rise3[1], idel_pat0_rise3[0]} = 4'h4; assign {idel_pat0_fall3[3], idel_pat0_fall3[2], idel_pat0_fall3[1], idel_pat0_fall3[0]} = 4'hB; // Target pattern for "on-time write" assign {idel_pat1_rise0[3], idel_pat1_rise0[2], idel_pat1_rise0[1], idel_pat1_rise0[0]} = 4'h4; assign {idel_pat1_fall0[3], idel_pat1_fall0[2], idel_pat1_fall0[1], idel_pat1_fall0[0]} = 4'h9; assign {idel_pat1_rise1[3], idel_pat1_rise1[2], idel_pat1_rise1[1], idel_pat1_rise1[0]} = 4'h3; assign {idel_pat1_fall1[3], idel_pat1_fall1[2], idel_pat1_fall1[1], idel_pat1_fall1[0]} = 4'h7; assign {idel_pat1_rise2[3], idel_pat1_rise2[2], idel_pat1_rise2[1], idel_pat1_rise2[0]} = 4'hE; assign {idel_pat1_fall2[3], idel_pat1_fall2[2], idel_pat1_fall2[1], idel_pat1_fall2[0]} = 4'hC; assign {idel_pat1_rise3[3], idel_pat1_rise3[2], idel_pat1_rise3[1], idel_pat1_rise3[0]} = 4'h9; assign {idel_pat1_fall3[3], idel_pat1_fall3[2], idel_pat1_fall3[1], idel_pat1_fall3[0]} = 4'h2; // Correct data valid window for "early write" assign {pat0_rise0[3], pat0_rise0[2], pat0_rise0[1], pat0_rise0[0]} = 4'h7; assign {pat0_fall0[3], pat0_fall0[2], pat0_fall0[1], pat0_fall0[0]} = 4'hE; assign {pat0_rise1[3], pat0_rise1[2], pat0_rise1[1], pat0_rise1[0]} = 4'hC; assign {pat0_fall1[3], pat0_fall1[2], pat0_fall1[1], pat0_fall1[0]} = 4'h9; assign {pat0_rise2[3], pat0_rise2[2], pat0_rise2[1], pat0_rise2[0]} = 4'h2; assign {pat0_fall2[3], pat0_fall2[2], pat0_fall2[1], pat0_fall2[0]} = 4'h4; assign {pat0_rise3[3], pat0_rise3[2], pat0_rise3[1], pat0_rise3[0]} = 4'hB; assign {pat0_fall3[3], pat0_fall3[2], pat0_fall3[1], pat0_fall3[0]} = 4'h1; // Correct data valid window for "on-time write" assign {pat1_rise0[3], pat1_rise0[2], pat1_rise0[1], pat1_rise0[0]} = 4'h9; assign {pat1_fall0[3], pat1_fall0[2], pat1_fall0[1], pat1_fall0[0]} = 4'h3; assign {pat1_rise1[3], pat1_rise1[2], pat1_rise1[1], pat1_rise1[0]} = 4'h7; assign {pat1_fall1[3], pat1_fall1[2], pat1_fall1[1], pat1_fall1[0]} = 4'hE; assign {pat1_rise2[3], pat1_rise2[2], pat1_rise2[1], pat1_rise2[0]} = 4'hC; assign {pat1_fall2[3], pat1_fall2[2], pat1_fall2[1], pat1_fall2[0]} = 4'h9; assign {pat1_rise3[3], pat1_rise3[2], pat1_rise3[1], pat1_rise3[0]} = 4'h2; assign {pat1_fall3[3], pat1_fall3[2], pat1_fall3[1], pat1_fall3[0]} = 4'h4; end else if (nCK_PER_CLK == 2) begin: gen_pat_div2 // Pattern for DQ IDELAY increment // Target pattern for "early write" assign idel_pat0_rise0[3] = 2'b01; assign idel_pat0_fall0[3] = 2'b00; assign idel_pat0_rise1[3] = 2'b10; assign idel_pat0_fall1[3] = 2'b11; assign idel_pat0_rise0[2] = 2'b00; assign idel_pat0_fall0[2] = 2'b10; assign idel_pat0_rise1[2] = 2'b11; assign idel_pat0_fall1[2] = 2'b10; assign idel_pat0_rise0[1] = 2'b00; assign idel_pat0_fall0[1] = 2'b11; assign idel_pat0_rise1[1] = 2'b10; assign idel_pat0_fall1[1] = 2'b01; assign idel_pat0_rise0[0] = 2'b11; assign idel_pat0_fall0[0] = 2'b10; assign idel_pat0_rise1[0] = 2'b00; assign idel_pat0_fall1[0] = 2'b01; // Target pattern for "on-time write" assign idel_pat1_rise0[3] = 2'b01; assign idel_pat1_fall0[3] = 2'b11; assign idel_pat1_rise1[3] = 2'b01; assign idel_pat1_fall1[3] = 2'b00; assign idel_pat1_rise0[2] = 2'b11; assign idel_pat1_fall0[2] = 2'b01; assign idel_pat1_rise1[2] = 2'b00; assign idel_pat1_fall1[2] = 2'b10; assign idel_pat1_rise0[1] = 2'b01; assign idel_pat1_fall0[1] = 2'b00; assign idel_pat1_rise1[1] = 2'b10; assign idel_pat1_fall1[1] = 2'b11; assign idel_pat1_rise0[0] = 2'b00; assign idel_pat1_fall0[0] = 2'b10; assign idel_pat1_rise1[0] = 2'b11; assign idel_pat1_fall1[0] = 2'b10; // Correct data valid window for "early write" assign pat0_rise0[3] = 2'b00; assign pat0_fall0[3] = 2'b10; assign pat0_rise1[3] = 2'b11; assign pat0_fall1[3] = 2'b10; assign pat0_rise0[2] = 2'b10; assign pat0_fall0[2] = 2'b11; assign pat0_rise1[2] = 2'b10; assign pat0_fall1[2] = 2'b00; assign pat0_rise0[1] = 2'b11; assign pat0_fall0[1] = 2'b10; assign pat0_rise1[1] = 2'b01; assign pat0_fall1[1] = 2'b00; assign pat0_rise0[0] = 2'b10; assign pat0_fall0[0] = 2'b00; assign pat0_rise1[0] = 2'b01; assign pat0_fall1[0] = 2'b11; // Correct data valid window for "on-time write" assign pat1_rise0[3] = 2'b11; assign pat1_fall0[3] = 2'b01; assign pat1_rise1[3] = 2'b00; assign pat1_fall1[3] = 2'b10; assign pat1_rise0[2] = 2'b01; assign pat1_fall0[2] = 2'b00; assign pat1_rise1[2] = 2'b10; assign pat1_fall1[2] = 2'b11; assign pat1_rise0[1] = 2'b00; assign pat1_fall0[1] = 2'b10; assign pat1_rise1[1] = 2'b11; assign pat1_fall1[1] = 2'b10; assign pat1_rise0[0] = 2'b10; assign pat1_fall0[0] = 2'b11; assign pat1_rise1[0] = 2'b10; assign pat1_fall1[0] = 2'b00; end endgenerate // Each bit of each byte is compared to expected pattern. // This was done to prevent (and "drastically decrease") the chance that // invalid data clocked in when the DQ bus is tri-state (along with a // combination of the correct data) will resemble the expected data // pattern. A better fix for this is to change the training pattern and/or // make the pattern longer. generate genvar pt_i; if (nCK_PER_CLK == 4) begin: gen_pat_match_div4 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match // DQ IDELAY pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4]) idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4]) idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4]) idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4]) idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == idel_pat0_rise2[pt_i%4]) idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == idel_pat0_fall2[pt_i%4]) idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == idel_pat0_rise3[pt_i%4]) idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == idel_pat0_fall3[pt_i%4]) idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4]) idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4]) idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4]) idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4]) idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == idel_pat1_rise2[pt_i%4]) idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == idel_pat1_fall2[pt_i%4]) idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == idel_pat1_rise3[pt_i%4]) idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == idel_pat1_fall3[pt_i%4]) idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b0; end // DQS DVW pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4]) pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4]) pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat0_rise2[pt_i%4]) pat0_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat0_fall2[pt_i%4]) pat0_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat0_rise3[pt_i%4]) pat0_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat0_fall3[pt_i%4]) pat0_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat1_rise2[pt_i%4]) pat1_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat1_fall2[pt_i%4]) pat1_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat1_rise3[pt_i%4]) pat1_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat1_fall3[pt_i%4]) pat1_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall3_r[pt_i] <= #TCQ 1'b0; end end // Combine pattern match "subterms" for DQ-IDELAY stage always @(posedge clk) begin idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r; idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r; idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r; idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r; idel_pat0_match_rise2_and_r <= #TCQ &idel_pat0_match_rise2_r; idel_pat0_match_fall2_and_r <= #TCQ &idel_pat0_match_fall2_r; idel_pat0_match_rise3_and_r <= #TCQ &idel_pat0_match_rise3_r; idel_pat0_match_fall3_and_r <= #TCQ &idel_pat0_match_fall3_r; idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r && idel_pat0_match_fall0_and_r && idel_pat0_match_rise1_and_r && idel_pat0_match_fall1_and_r && idel_pat0_match_rise2_and_r && idel_pat0_match_fall2_and_r && idel_pat0_match_rise3_and_r && idel_pat0_match_fall3_and_r); end always @(posedge clk) begin idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r; idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r; idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r; idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r; idel_pat1_match_rise2_and_r <= #TCQ &idel_pat1_match_rise2_r; idel_pat1_match_fall2_and_r <= #TCQ &idel_pat1_match_fall2_r; idel_pat1_match_rise3_and_r <= #TCQ &idel_pat1_match_rise3_r; idel_pat1_match_fall3_and_r <= #TCQ &idel_pat1_match_fall3_r; idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r && idel_pat1_match_fall0_and_r && idel_pat1_match_rise1_and_r && idel_pat1_match_fall1_and_r && idel_pat1_match_rise2_and_r && idel_pat1_match_fall2_and_r && idel_pat1_match_rise3_and_r && idel_pat1_match_fall3_and_r); end always @(*) idel_pat_data_match <= #TCQ idel_pat0_data_match_r | idel_pat1_data_match_r; always @(posedge clk) idel_pat_data_match_r <= #TCQ idel_pat_data_match; // Combine pattern match "subterms" for DQS-PHASER_IN stage always @(posedge clk) begin pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r; pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r; pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r; pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r; pat0_match_rise2_and_r <= #TCQ &pat0_match_rise2_r; pat0_match_fall2_and_r <= #TCQ &pat0_match_fall2_r; pat0_match_rise3_and_r <= #TCQ &pat0_match_rise3_r; pat0_match_fall3_and_r <= #TCQ &pat0_match_fall3_r; pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r && pat0_match_fall0_and_r && pat0_match_rise1_and_r && pat0_match_fall1_and_r && pat0_match_rise2_and_r && pat0_match_fall2_and_r && pat0_match_rise3_and_r && pat0_match_fall3_and_r); end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_match_rise2_and_r <= #TCQ &pat1_match_rise2_r; pat1_match_fall2_and_r <= #TCQ &pat1_match_fall2_r; pat1_match_rise3_and_r <= #TCQ &pat1_match_rise3_r; pat1_match_fall3_and_r <= #TCQ &pat1_match_fall3_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r && pat1_match_rise2_and_r && pat1_match_fall2_and_r && pat1_match_rise3_and_r && pat1_match_fall3_and_r); end assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r; end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match // DQ IDELAY pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4]) idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4]) idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4]) idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4]) idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4]) idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4]) idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4]) idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4]) idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end // DQS DVW pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4]) pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4]) pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end end // Combine pattern match "subterms" for DQ-IDELAY stage always @(posedge clk) begin idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r; idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r; idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r; idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r; idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r && idel_pat0_match_fall0_and_r && idel_pat0_match_rise1_and_r && idel_pat0_match_fall1_and_r); end always @(posedge clk) begin idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r; idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r; idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r; idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r; idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r && idel_pat1_match_fall0_and_r && idel_pat1_match_rise1_and_r && idel_pat1_match_fall1_and_r); end always @(posedge clk) begin if (sr_valid_r2) idel_pat_data_match <= #TCQ idel_pat0_data_match_r | idel_pat1_data_match_r; end //assign idel_pat_data_match = idel_pat0_data_match_r | // idel_pat1_data_match_r; always @(posedge clk) idel_pat_data_match_r <= #TCQ idel_pat_data_match; // Combine pattern match "subterms" for DQS-PHASER_IN stage always @(posedge clk) begin pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r; pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r; pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r; pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r; pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r && pat0_match_fall0_and_r && pat0_match_rise1_and_r && pat0_match_fall1_and_r); end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r); end assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r; end endgenerate always @(posedge clk) begin rdlvl_stg1_start_r <= #TCQ rdlvl_stg1_start; mpr_rdlvl_done_r1 <= #TCQ mpr_rdlvl_done_r; mpr_rdlvl_done_r2 <= #TCQ mpr_rdlvl_done_r1; mpr_rdlvl_start_r <= #TCQ mpr_rdlvl_start; end //*************************************************************************** // First stage calibration: Capture clock //*************************************************************************** //***************************************************************** // Keep track of how many samples have been written to shift registers // Every time RD_SHIFT_LEN samples have been written, then we have a // full read training pattern loaded into the sr_* registers. Then assert // sr_valid_r to indicate that: (1) comparison between the sr_* and // old_sr_* and prev_sr_* registers can take place, (2) transfer of // the contents of sr_* to old_sr_* and prev_sr_* registers can also // take place //***************************************************************** // verilint STARC-2.2.3.3 off always @(posedge clk) if (rst || (mpr_rdlvl_done_r && ~rdlvl_stg1_start)) begin cnt_shift_r <= #TCQ 'b1; sr_valid_r <= #TCQ 1'b0; mpr_valid_r <= #TCQ 1'b0; end else begin if (mux_rd_valid_r && mpr_rdlvl_start && ~mpr_rdlvl_done_r) begin if (cnt_shift_r == 'b0) mpr_valid_r <= #TCQ 1'b1; else begin mpr_valid_r <= #TCQ 1'b0; cnt_shift_r <= #TCQ cnt_shift_r + 1; end end else mpr_valid_r <= #TCQ 1'b0; if (mux_rd_valid_r && rdlvl_stg1_start) begin if (cnt_shift_r == RD_SHIFT_LEN-1) begin sr_valid_r <= #TCQ 1'b1; cnt_shift_r <= #TCQ 'b0; end else begin sr_valid_r <= #TCQ 1'b0; cnt_shift_r <= #TCQ cnt_shift_r + 1; end end else // When the current mux_rd_* contents are not valid, then // retain the current value of cnt_shift_r, and make sure // that sr_valid_r = 0 to prevent any downstream loads or // comparisons sr_valid_r <= #TCQ 1'b0; end // verilint STARC-2.2.3.3 on //***************************************************************** // Logic to determine when either edge of the data eye encountered // Pre- and post-IDELAY update data pattern is compared, if they // differ, than an edge has been encountered. Currently no attempt // made to determine if the data pattern itself is "correct", only // whether it changes after incrementing the IDELAY (possible // future enhancement) //***************************************************************** // One-way control for ensuring that state machine request to store // current read data into OLD SR shift register only occurs on a // valid clock cycle. The FSM provides a one-cycle request pulse. // It is the responsibility of the FSM to wait the worst-case time // before relying on any downstream results of this load. always @(posedge clk) if (rst) store_sr_r <= #TCQ 1'b0; else begin if (store_sr_req_r) store_sr_r <= #TCQ 1'b1; else if ((sr_valid_r || mpr_valid_r) && store_sr_r) store_sr_r <= #TCQ 1'b0; end // Transfer current data to old data, prior to incrementing delay // Also store data from current sampling window - so that we can detect // if the current delay tap yields data that is "jittery" generate if (nCK_PER_CLK == 4) begin: gen_old_sr_div4 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr always @(posedge clk) begin if (sr_valid_r || mpr_valid_r) begin // Load last sample (i.e. from current sampling interval) prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; prev_sr_rise2_r[z] <= #TCQ sr_rise2_r[z]; prev_sr_fall2_r[z] <= #TCQ sr_fall2_r[z]; prev_sr_rise3_r[z] <= #TCQ sr_rise3_r[z]; prev_sr_fall3_r[z] <= #TCQ sr_fall3_r[z]; end if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; old_sr_rise2_r[z] <= #TCQ sr_rise2_r[z]; old_sr_fall2_r[z] <= #TCQ sr_fall2_r[z]; old_sr_rise3_r[z] <= #TCQ sr_rise3_r[z]; old_sr_fall3_r[z] <= #TCQ sr_fall3_r[z]; end end end end else if (nCK_PER_CLK == 2) begin: gen_old_sr_div2 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr always @(posedge clk) begin if (sr_valid_r || mpr_valid_r) begin prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; end if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; end end end end endgenerate //******************************************************* // Match determination occurs over 3 cycles - pipelined for better timing //******************************************************* // Match valid with # of cycles of pipelining in match determination always @(posedge clk) begin sr_valid_r1 <= #TCQ sr_valid_r; sr_valid_r2 <= #TCQ sr_valid_r1; mpr_valid_r1 <= #TCQ mpr_valid_r; mpr_valid_r2 <= #TCQ mpr_valid_r1; end generate if (nCK_PER_CLK == 4) begin: gen_sr_match_div4 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match always @(posedge clk) begin // CYCLE1: Compare all bits in DQS grp, generate separate term for // each bit over four bit times. For example, if there are 8-bits // per DQS group, 32 terms are generated on cycle 1 // NOTE: Structure HDL such that X on data bus will result in a // mismatch. This is required for memory models that can drive the // bus with X's to model uncertainty regions (e.g. Denali) if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z])) old_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z]; else old_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z])) old_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z]; else old_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z])) old_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z]; else old_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z])) old_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z]; else old_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == old_sr_rise2_r[z])) old_sr_match_rise2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise2_r[z] <= #TCQ old_sr_match_rise2_r[z]; else old_sr_match_rise2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == old_sr_fall2_r[z])) old_sr_match_fall2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall2_r[z] <= #TCQ old_sr_match_fall2_r[z]; else old_sr_match_fall2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == old_sr_rise3_r[z])) old_sr_match_rise3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise3_r[z] <= #TCQ old_sr_match_rise3_r[z]; else old_sr_match_rise3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == old_sr_fall3_r[z])) old_sr_match_fall3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall3_r[z] <= #TCQ old_sr_match_fall3_r[z]; else old_sr_match_fall3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z])) prev_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z]; else prev_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z])) prev_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z]; else prev_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z])) prev_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z]; else prev_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z])) prev_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z]; else prev_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == prev_sr_rise2_r[z])) prev_sr_match_rise2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise2_r[z] <= #TCQ prev_sr_match_rise2_r[z]; else prev_sr_match_rise2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == prev_sr_fall2_r[z])) prev_sr_match_fall2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall2_r[z] <= #TCQ prev_sr_match_fall2_r[z]; else prev_sr_match_fall2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == prev_sr_rise3_r[z])) prev_sr_match_rise3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise3_r[z] <= #TCQ prev_sr_match_rise3_r[z]; else prev_sr_match_rise3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == prev_sr_fall3_r[z])) prev_sr_match_fall3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall3_r[z] <= #TCQ prev_sr_match_fall3_r[z]; else prev_sr_match_fall3_r[z] <= #TCQ 1'b0; // CYCLE2: Combine all the comparisons for every 8 words (rise0, // fall0,rise1, fall1) in the calibration sequence. Now we're down // to DRAM_WIDTH terms old_sr_match_cyc2_r[z] <= #TCQ old_sr_match_rise0_r[z] & old_sr_match_fall0_r[z] & old_sr_match_rise1_r[z] & old_sr_match_fall1_r[z] & old_sr_match_rise2_r[z] & old_sr_match_fall2_r[z] & old_sr_match_rise3_r[z] & old_sr_match_fall3_r[z]; prev_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_rise0_r[z] & prev_sr_match_fall0_r[z] & prev_sr_match_rise1_r[z] & prev_sr_match_fall1_r[z] & prev_sr_match_rise2_r[z] & prev_sr_match_fall2_r[z] & prev_sr_match_rise3_r[z] & prev_sr_match_fall3_r[z]; // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen), // and qualify with pipelined valid signal) - probably don't need // a cycle just do do this.... if (sr_valid_r2 || mpr_valid_r2) begin old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z]; prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z]; end else begin old_sr_diff_r[z] <= #TCQ 'b0; prev_sr_diff_r[z] <= #TCQ 'b0; end end end end if (nCK_PER_CLK == 2) begin: gen_sr_match_div2 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match always @(posedge clk) begin if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z])) old_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z]; else old_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z])) old_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z]; else old_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z])) old_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z]; else old_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z])) old_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z]; else old_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z])) prev_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z]; else prev_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z])) prev_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z]; else prev_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z])) prev_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z]; else prev_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z])) prev_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z]; else prev_sr_match_fall1_r[z] <= #TCQ 1'b0; old_sr_match_cyc2_r[z] <= #TCQ old_sr_match_rise0_r[z] & old_sr_match_fall0_r[z] & old_sr_match_rise1_r[z] & old_sr_match_fall1_r[z]; prev_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_rise0_r[z] & prev_sr_match_fall0_r[z] & prev_sr_match_rise1_r[z] & prev_sr_match_fall1_r[z]; // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen), // and qualify with pipelined valid signal) - probably don't need // a cycle just do do this.... if (sr_valid_r2 || mpr_valid_r2) begin old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z]; prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z]; end else begin old_sr_diff_r[z] <= #TCQ 'b0; prev_sr_diff_r[z] <= #TCQ 'b0; end end end end endgenerate //*************************************************************************** // First stage calibration: DQS Capture //*************************************************************************** //******************************************************* // Counters for tracking # of samples compared // For each comparision point (i.e. to determine if an edge has // occurred after each IODELAY increment when read leveling), // multiple samples are compared in order to average out the effects // of jitter. If any one of these samples is different than the "old" // sample corresponding to the previous IODELAY value, then an edge // is declared to be detected. //******************************************************* // Two cascaded counters are used to keep track of # of samples compared, // in order to make it easier to meeting timing on these paths. Once // optimal sampling interval is determined, it may be possible to remove // the second counter always @(posedge clk) samp_edge_cnt0_en_r <= #TCQ (cal1_state_r == CAL1_PAT_DETECT) || (cal1_state_r == CAL1_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ); // First counter counts # of samples compared always @(posedge clk) if (rst) samp_edge_cnt0_r <= #TCQ 'b0; else begin if (!samp_edge_cnt0_en_r) // Reset sample counter when not in any of the "sampling" states samp_edge_cnt0_r <= #TCQ 'b0; else if (sr_valid_r2 || mpr_valid_r2) // Otherwise, count # of samples compared samp_edge_cnt0_r <= #TCQ samp_edge_cnt0_r + 1; end // Counter #2 enable generation always @(posedge clk) if (rst) samp_edge_cnt1_en_r <= #TCQ 1'b0; else begin // Assert pulse when correct number of samples compared if ((samp_edge_cnt0_r == DETECT_EDGE_SAMPLE_CNT0) && (sr_valid_r2 || mpr_valid_r2)) samp_edge_cnt1_en_r <= #TCQ 1'b1; else samp_edge_cnt1_en_r <= #TCQ 1'b0; end // Counter #2 always @(posedge clk) if (rst) samp_edge_cnt1_r <= #TCQ 'b0; else if (!samp_edge_cnt0_en_r) samp_edge_cnt1_r <= #TCQ 'b0; else if (samp_edge_cnt1_en_r) samp_edge_cnt1_r <= #TCQ samp_edge_cnt1_r + 1; always @(posedge clk) if (rst) samp_cnt_done_r <= #TCQ 1'b0; else begin if (!samp_edge_cnt0_en_r) samp_cnt_done_r <= #TCQ 'b0; else if ((SIM_CAL_OPTION == "FAST_CAL") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin if (samp_edge_cnt0_r == SR_VALID_DELAY-1) // For simulation only, stay in edge detection mode a minimum // amount of time - just enough for two data compares to finish samp_cnt_done_r <= #TCQ 1'b1; end else begin if (samp_edge_cnt1_r == DETECT_EDGE_SAMPLE_CNT1) samp_cnt_done_r <= #TCQ 1'b1; end end //***************************************************************** // Logic to keep track of (on per-bit basis): // 1. When a region of stability preceded by a known edge occurs // 2. If for the current tap, the read data jitters // 3. If an edge occured between the current and previous tap // 4. When the current edge detection/sampling interval can end // Essentially, these are a series of status bits - the stage 1 // calibration FSM monitors these to determine when an edge is // found. Additional information is provided to help the FSM // determine if a left or right edge has been found. //**************************************************************** assign pb_detect_edge_setup = (cal1_state_r == CAL1_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT); assign pb_detect_edge = (cal1_state_r == CAL1_PAT_DETECT) || (cal1_state_r == CAL1_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ); generate for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_track_left_edge always @(posedge clk) begin if (pb_detect_edge_setup) begin // Reset eye size, stable eye marker, and jitter marker before // starting new edge detection iteration pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_detect_edge_done_r[z] <= #TCQ 1'b0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_last_tap_jitter_r[z] <= #TCQ 1'b0; pb_found_edge_last_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b0; pb_found_first_edge_r[z] <= #TCQ 1'b0; end else if (pb_detect_edge) begin // Save information on which DQ bits are already out of the // data valid window - those DQ bits will later not have their // IDELAY tap value incremented pb_found_edge_last_r[z] <= #TCQ pb_found_edge_r[z]; if (!pb_detect_edge_done_r[z]) begin if (samp_cnt_done_r) begin // If we've reached end of sampling interval, no jitter on // current tap has been found (although an edge could have // been found between the current and previous taps), and // the sampling interval is complete. Increment the stable // eye counter if no edge found, and always clear the jitter // flag in preparation for the next tap. pb_last_tap_jitter_r[z] <= #TCQ 1'b0; pb_detect_edge_done_r[z] <= #TCQ 1'b1; if (!pb_found_edge_r[z] && !pb_last_tap_jitter_r[z]) begin // If the data was completely stable during this tap and // no edge was found between this and the previous tap // then increment the stable eye counter "as appropriate" if (pb_cnt_eye_size_r[z] != MIN_EYE_SIZE-1) pb_cnt_eye_size_r[z] <= #TCQ pb_cnt_eye_size_r[z] + 1; else //if (pb_found_first_edge_r[z]) // We've reached minimum stable eye width pb_found_stable_eye_r[z] <= #TCQ 1'b1; end else begin // Otherwise, an edge was found, either because of a // difference between this and the previous tap's read // data, and/or because the previous tap's data jittered // (but not the current tap's data), then just set the // edge found flag, and enable the stable eye counter pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b1; pb_detect_edge_done_r[z] <= #TCQ 1'b1; end end else if (prev_sr_diff_r[z]) begin // If we find that the current tap read data jitters, then // set edge and jitter found flags, "enable" the eye size // counter, and stop sampling interval for this bit pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_last_tap_jitter_r[z] <= #TCQ 1'b1; pb_found_edge_r[z] <= #TCQ 1'b1; pb_found_first_edge_r[z] <= #TCQ 1'b1; pb_detect_edge_done_r[z] <= #TCQ 1'b1; end else if (old_sr_diff_r[z] || pb_last_tap_jitter_r[z]) begin // If either an edge was found (i.e. difference between // current tap and previous tap read data), or the previous // tap exhibited jitter (which means by definition that the // current tap cannot match the previous tap because the // previous tap gave unstable data), then set the edge found // flag, and "enable" eye size counter. But do not stop // sampling interval - we still need to check if the current // tap exhibits jitter pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b1; pb_found_first_edge_r[z] <= #TCQ 1'b1; end end end else begin // Before every edge detection interval, reset "intra-tap" flags pb_found_edge_r[z] <= #TCQ 1'b0; pb_detect_edge_done_r[z] <= #TCQ 1'b0; end end end endgenerate // Combine the above per-bit status flags into combined terms when // performing deskew on the aggregate data window always @(posedge clk) begin detect_edge_done_r <= #TCQ &pb_detect_edge_done_r; found_edge_r <= #TCQ |pb_found_edge_r; found_edge_all_r <= #TCQ &pb_found_edge_r; found_stable_eye_r <= #TCQ &pb_found_stable_eye_r; end // last IODELAY "stable eye" indicator is updated only after // detect_edge_done_r is asserted - so that when we do find the "right edge" // of the data valid window, found_edge_r = 1, AND found_stable_eye_r = 1 // when detect_edge_done_r = 1 (otherwise, if found_stable_eye_r updates // immediately, then it never possible to have found_stable_eye_r = 1 // when we detect an edge - and we'll never know whether we've found // a "right edge") always @(posedge clk) if (pb_detect_edge_setup) found_stable_eye_last_r <= #TCQ 1'b0; else if (detect_edge_done_r) found_stable_eye_last_r <= #TCQ found_stable_eye_r; //***************************************************************** // Keep track of DQ IDELAYE2 taps used //***************************************************************** // Added additional register stage to improve timing always @(posedge clk) if (rst) idelay_tap_cnt_slice_r <= 5'h0; else idelay_tap_cnt_slice_r <= idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]; always @(posedge clk) if (rst || (SIM_CAL_OPTION == "SKIP_CAL")) begin //|| new_cnt_cpt_r for (s = 0; s < RANKS; s = s + 1) begin for (t = 0; t < DQS_WIDTH; t = t + 1) begin idelay_tap_cnt_r[s][t] <= #TCQ idelaye2_init_val; end end end else if (SIM_CAL_OPTION == "FAST_CAL") begin for (u = 0; u < RANKS; u = u + 1) begin for (w = 0; w < DQS_WIDTH; w = w + 1) begin if (cal1_dq_idel_ce) begin if (cal1_dq_idel_inc) idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] + 1; else idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] - 1; end end end end else if ((rnk_cnt_r == RANKS-1) && (RANKS == 2) && rdlvl_rank_done_r && (cal1_state_r == CAL1_IDLE)) begin for (f = 0; f < DQS_WIDTH; f = f + 1) begin idelay_tap_cnt_r[rnk_cnt_r][f] <= #TCQ idelay_tap_cnt_r[(rnk_cnt_r-1)][f]; end end else if (cal1_dq_idel_ce) begin if (cal1_dq_idel_inc) idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r + 5'h1; else idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r - 5'h1; end else if (idelay_ld) idelay_tap_cnt_r[0][wrcal_cnt] <= #TCQ 5'b00000; always @(posedge clk) if (rst || new_cnt_cpt_r) idelay_tap_limit_r <= #TCQ 1'b0; else if (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_r] == 'd31) idelay_tap_limit_r <= #TCQ 1'b1; //***************************************************************** // keep track of edge tap counts found, and current capture clock // tap count //***************************************************************** always @(posedge clk) if (rst || new_cnt_cpt_r || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) tap_cnt_cpt_r <= #TCQ 'b0; else if (cal1_dlyce_cpt_r) begin if (cal1_dlyinc_cpt_r) tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r + 1; else if (tap_cnt_cpt_r != 'd0) tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r - 1; end always @(posedge clk) if (rst || new_cnt_cpt_r || (cal1_state_r1 == CAL1_DQ_IDEL_TAP_INC) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) tap_limit_cpt_r <= #TCQ 1'b0; else if (tap_cnt_cpt_r == 6'd63) tap_limit_cpt_r <= #TCQ 1'b1; always @(posedge clk) cal1_cnt_cpt_timing_r <= #TCQ cal1_cnt_cpt_r; assign cal1_cnt_cpt_timing = {2'b00, cal1_cnt_cpt_r}; // Storing DQS tap values at the end of each DQS read leveling always @(posedge clk) begin if (rst) begin for (a = 0; a < RANKS; a = a + 1) begin: rst_rdlvl_dqs_tap_count_loop for (b = 0; b < DQS_WIDTH; b = b + 1) rdlvl_dqs_tap_cnt_r[a][b] <= #TCQ 'b0; end end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_NEXT_DQS)) begin for (p = 0; p < RANKS; p = p +1) begin: rdlvl_dqs_tap_rank_cnt for(q = 0; q < DQS_WIDTH; q = q +1) begin: rdlvl_dqs_tap_cnt rdlvl_dqs_tap_cnt_r[p][q] <= #TCQ tap_cnt_cpt_r; end end end else if (SIM_CAL_OPTION == "SKIP_CAL") begin for (j = 0; j < RANKS; j = j +1) begin: rdlvl_dqs_tap_rnk_cnt for(i = 0; i < DQS_WIDTH; i = i +1) begin: rdlvl_dqs_cnt rdlvl_dqs_tap_cnt_r[j][i] <= #TCQ 6'd31; end end end else if (cal1_state_r1 == CAL1_NEXT_DQS) begin rdlvl_dqs_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing_r] <= #TCQ tap_cnt_cpt_r; end end // Counter to track maximum DQ IODELAY tap usage during the per-bit // deskew portion of stage 1 calibration always @(posedge clk) if (rst) begin idel_tap_cnt_dq_pb_r <= #TCQ 'b0; idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end else if (new_cnt_cpt_r) begin idel_tap_cnt_dq_pb_r <= #TCQ 'b0; idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end else if (|cal1_dlyce_dq_r) begin if (cal1_dlyinc_dq_r) idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r + 1; else idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r - 1; if (idel_tap_cnt_dq_pb_r == 31) idel_tap_limit_dq_pb_r <= #TCQ 1'b1; else idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end //***************************************************************** always @(posedge clk) cal1_state_r1 <= #TCQ cal1_state_r; always @(posedge clk) if (rst) begin cal1_cnt_cpt_r <= #TCQ 'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_IDLE; cnt_idel_dec_cpt_r <= #TCQ 6'bxxxxxx; found_first_edge_r <= #TCQ 1'b0; found_second_edge_r <= #TCQ 1'b0; right_edge_taps_r <= #TCQ 6'bxxxxxx; first_edge_taps_r <= #TCQ 6'bxxxxxx; new_cnt_cpt_r <= #TCQ 1'b0; rdlvl_stg1_done <= #TCQ 1'b0; rdlvl_stg1_err <= #TCQ 1'b0; second_edge_taps_r <= #TCQ 6'bxxxxxx; store_sr_req_pulsed_r <= #TCQ 1'b0; store_sr_req_r <= #TCQ 1'b0; rnk_cnt_r <= #TCQ 2'b00; rdlvl_rank_done_r <= #TCQ 1'b0; idel_dec_cnt <= #TCQ 'd0; rdlvl_last_byte_done <= #TCQ 1'b0; idel_pat_detect_valid_r <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; idel_adj_inc <= #TCQ 1'b0; if (OCAL_EN == "ON") mpr_rdlvl_done_r <= #TCQ 1'b0; else mpr_rdlvl_done_r <= #TCQ 1'b1; mpr_dec_cpt_r <= #TCQ 1'b0; end else begin // default (inactive) states for all "pulse" outputs // verilint STARC-2.2.3.3 off cal1_prech_req_r <= #TCQ 1'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; new_cnt_cpt_r <= #TCQ 1'b0; store_sr_req_pulsed_r <= #TCQ 1'b0; store_sr_req_r <= #TCQ 1'b0; case (cal1_state_r) CAL1_IDLE: begin rdlvl_rank_done_r <= #TCQ 1'b0; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; if (mpr_rdlvl_start && ~mpr_rdlvl_start_r) begin cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT; end else if (rdlvl_stg1_start && ~rdlvl_stg1_start_r) begin if (SIM_CAL_OPTION == "SKIP_CAL") cal1_state_r <= #TCQ CAL1_REGL_LOAD; else if (SIM_CAL_OPTION == "FAST_CAL") cal1_state_r <= #TCQ CAL1_NEXT_DQS; else begin new_cnt_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT; end end end CAL1_MPR_NEW_DQS_WAIT: begin cal1_prech_req_r <= #TCQ 1'b0; if (!cal1_wait_r && mpr_valid_r) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; end // Wait for the new DQS group to change // also gives time for the read data IN_FIFO to // output the updated data for the new DQS group CAL1_NEW_DQS_WAIT: begin rdlvl_rank_done_r <= #TCQ 1'b0; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; if (|pi_counter_read_val) begin //VK_REVIEW mpr_dec_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; cnt_idel_dec_cpt_r <= #TCQ pi_counter_read_val; end else if (!cal1_wait_r) begin //if (!cal1_wait_r) begin // Store "previous tap" read data. Technically there is no // "previous" read data, since we are starting a new DQS // group, so we'll never find an edge at tap 0 unless the // data is fluctuating/jittering store_sr_req_r <= #TCQ 1'b1; // If per-bit deskew is disabled, then skip the first // portion of stage 1 calibration if (PER_BIT_DESKEW == "OFF") cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; else if (PER_BIT_DESKEW == "ON") cal1_state_r <= #TCQ CAL1_PB_STORE_FIRST_WAIT; end end //***************************************************************** // Per-bit deskew states //***************************************************************** // Wait state following storage of initial read data CAL1_PB_STORE_FIRST_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE; // Look for an edge on all DQ bits in current DQS group CAL1_PB_DETECT_EDGE: if (detect_edge_done_r) begin if (found_stable_eye_r) begin // If we've found the left edge for all bits (or more precisely, // we've found the left edge, and then part of the stable // window thereafter), then proceed to positioning the CPT clock // right before the left margin cnt_idel_dec_cpt_r <= #TCQ MIN_EYE_SIZE + 1; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT; end else begin // If we've reached the end of the sampling time, and haven't // yet found the left margin of all the DQ bits, then: if (!tap_limit_cpt_r) begin // If we still have taps left to use, then store current value // of read data, increment the capture clock, and continue to // look for (left) edges store_sr_req_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_CPT; end else begin // If we ran out of taps moving the capture clock, and we // haven't finished edge detection, then reset the capture // clock taps to 0 (gradually, one tap at a time... // then exit the per-bit portion of the algorithm - // i.e. proceed to adjust the capture clock and DQ IODELAYs as cnt_idel_dec_cpt_r <= #TCQ 6'd63; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end end end // Increment delay for DQS CAL1_PB_INC_CPT: begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_CPT_WAIT; end // Wait for IODELAY for both capture and internal nodes within // ISERDES to settle, before checking again for an edge CAL1_PB_INC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE; end // We've found the left edges of the windows for all DQ bits // (actually, we found it MIN_EYE_SIZE taps ago) Decrement capture // clock IDELAY to position just outside left edge of data window CAL1_PB_DEC_CPT_LEFT: if (cnt_idel_dec_cpt_r == 6'b000000) cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT_WAIT; else begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; end CAL1_PB_DEC_CPT_LEFT_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ; // If there is skew between individual DQ bits, then after we've // positioned the CPT clock, we will be "in the window" for some // DQ bits ("early" DQ bits), and "out of the window" for others // ("late" DQ bits). Increase DQ taps until we are out of the // window for all DQ bits CAL1_PB_DETECT_EDGE_DQ: if (detect_edge_done_r) if (found_edge_all_r) begin // We're out of the window for all DQ bits in this DQS group // We're done with per-bit deskew for this group - now decr // capture clock IODELAY tap count back to 0, and proceed // with the rest of stage 1 calibration for this DQS group cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end else if (!idel_tap_limit_dq_pb_r) // If we still have DQ taps available for deskew, keep // incrementing IODELAY tap count for the appropriate DQ bits cal1_state_r <= #TCQ CAL1_PB_INC_DQ; else begin // Otherwise, stop immediately (we've done the best we can) // and proceed with rest of stage 1 calibration cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end CAL1_PB_INC_DQ: begin // Increment only those DQ for which an edge hasn't been found yet cal1_dlyce_dq_r <= #TCQ ~pb_found_edge_last_r; cal1_dlyinc_dq_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_DQ_WAIT; end CAL1_PB_INC_DQ_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ; // Decrement capture clock taps back to initial value CAL1_PB_DEC_CPT: if (cnt_idel_dec_cpt_r == 6'b000000) cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_WAIT; else begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; end // Wait for capture clock to settle, then proceed to rest of // state 1 calibration for this DQS group CAL1_PB_DEC_CPT_WAIT: if (!cal1_wait_r) begin store_sr_req_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; end // When first starting calibration for a DQS group, save the // current value of the read data shift register, and use this // as a reference. Note that for the first iteration of the // edge detection loop, we will in effect be checking for an edge // at IODELAY taps = 0 - normally, we are comparing the read data // for IODELAY taps = N, with the read data for IODELAY taps = N-1 // An edge can only be found at IODELAY taps = 0 if the read data // is changing during this time (possible due to jitter) CAL1_STORE_FIRST_WAIT: begin mpr_dec_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PAT_DETECT; end CAL1_VALID_WAIT: begin if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; end CAL1_MPR_PAT_DETECT: begin // MPR read leveling for centering DQS in valid window before // OCLKDELAYED calibration begins in order to eliminate read issues if (idel_pat_detect_valid_r == 1'b0) begin cal1_state_r <= #TCQ CAL1_VALID_WAIT; idel_pat_detect_valid_r <= #TCQ 1'b1; end else if (idel_pat_detect_valid_r && idel_mpr_pat_detect_r) begin cal1_state_r <= #TCQ CAL1_DETECT_EDGE; idel_dec_cnt <= #TCQ 'd0; end else if (!idelay_tap_limit_r) cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC; else cal1_state_r <= #TCQ CAL1_RDLVL_ERR; end CAL1_PAT_DETECT: begin // All DQ bits associated with a DQS are pushed to the right one IDELAY // tap at a time until first rising DQS is in the tri-state region // before first rising edge window. // The detect_edge_done_r condition included to support averaging // during IDELAY tap increments if (detect_edge_done_r) begin if (idel_pat_data_match) begin case (idelay_adj) 2'b01: begin cal1_state_r <= CAL1_DQ_IDEL_TAP_INC; idel_dec_cnt <= #TCQ 1'b0; idel_adj_inc <= #TCQ 1'b1; end 2'b10: begin //DEC by 1 cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC ; idel_dec_cnt <= #TCQ 1'b1; idel_adj_inc <= #TCQ 1'b0; end default: begin cal1_state_r <= #TCQ CAL1_DETECT_EDGE; idel_dec_cnt <= #TCQ 1'b0; idel_adj_inc <= #TCQ 1'b0; end endcase end else if (!idelay_tap_limit_r) begin cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC; end else begin cal1_state_r <= #TCQ CAL1_RDLVL_ERR; end end end // Increment IDELAY tap by 1 for DQ bits in the byte being calibrated // until left edge of valid window detected CAL1_DQ_IDEL_TAP_INC: begin cal1_dq_idel_ce <= #TCQ 1'b1; cal1_dq_idel_inc <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC_WAIT; idel_pat_detect_valid_r <= #TCQ 1'b0; end CAL1_DQ_IDEL_TAP_INC_WAIT: begin cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; if (!cal1_wait_r) begin idel_adj_inc <= #TCQ 1'b0; if (idel_adj_inc) cal1_state_r <= #TCQ CAL1_DETECT_EDGE; else if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3")) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; else cal1_state_r <= #TCQ CAL1_PAT_DETECT; end end // Decrement by 2 IDELAY taps once idel_pat_data_match detected CAL1_DQ_IDEL_TAP_DEC: begin cal1_dq_idel_inc <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC_WAIT; if (idel_dec_cnt >= 'd0) cal1_dq_idel_ce <= #TCQ 1'b1; else cal1_dq_idel_ce <= #TCQ 1'b0; if (idel_dec_cnt > 'd0) idel_dec_cnt <= #TCQ idel_dec_cnt - 1; else idel_dec_cnt <= #TCQ idel_dec_cnt; end CAL1_DQ_IDEL_TAP_DEC_WAIT: begin cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; if (!cal1_wait_r) begin if ((idel_dec_cnt > 'd0) || (pi_rdval_cnt > 'd0)) cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC; else if (mpr_dec_cpt_r) cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; else cal1_state_r <= #TCQ CAL1_DETECT_EDGE; end end // Check for presence of data eye edge. During this state, we // sample the read data multiple times, and look for changes // in the read data, specifically: // 1. A change in the read data compared with the value of // read data from the previous delay tap. This indicates // that the most recent tap delay increment has moved us // into either a new window, or moved/kept us in the // transition/jitter region between windows. Note that this // condition only needs to be checked for once, and for // logistical purposes, we check this soon after entering // this state (see comment in CAL1_DETECT_EDGE below for // why this is done) // 2. A change in the read data while we are in this state // (i.e. in the absence of a tap delay increment). This // indicates that we're close enough to a window edge that // jitter will cause the read data to change even in the // absence of a tap delay change CAL1_DETECT_EDGE: begin // Essentially wait for the first comparision to finish, then // store current data into "old" data register. This store // happens now, rather than later (e.g. when we've have already // left this state) in order to avoid the situation the data that // is stored as "old" data has not been used in an "active // comparison" - i.e. data is stored after the last comparison // of this state. In this case, we can miss an edge if the // following sequence occurs: // 1. Comparison completes in this state - no edge found // 2. "Momentary jitter" occurs which "pushes" the data out the // equivalent of one delay tap // 3. We store this jittered data as the "old" data // 4. "Jitter" no longer present // 5. We increment the delay tap by one // 6. Now we compare the current with the "old" data - they're // the same, and no edge is detected // NOTE: Given the large # of comparisons done in this state, it's // highly unlikely the above sequence will occur in actual H/W // Wait for the first load of read data into the comparison // shift register to finish, then load the current read data // into the "old" data register. This allows us to do one // initial comparision between the current read data, and // stored data corresponding to the previous delay tap idel_pat_detect_valid_r <= #TCQ 1'b0; if (!store_sr_req_pulsed_r) begin // Pulse store_sr_req_r only once in this state store_sr_req_r <= #TCQ 1'b1; store_sr_req_pulsed_r <= #TCQ 1'b1; end else begin store_sr_req_r <= #TCQ 1'b0; store_sr_req_pulsed_r <= #TCQ 1'b1; end // Continue to sample read data and look for edges until the // appropriate time interval (shorter for simulation-only, // much, much longer for actual h/w) has elapsed if (detect_edge_done_r) begin if (tap_limit_cpt_r) // Only one edge detected and ran out of taps since only one // bit time worth of taps available for window detection. This // can happen if at tap 0 DQS is in previous window which results // in only left edge being detected. Or at tap 0 DQS is in the // current window resulting in only right edge being detected. // Depending on the frequency this case can also happen if at // tap 0 DQS is in the left noise region resulting in only left // edge being detected. cal1_state_r <= #TCQ CAL1_CALC_IDEL; else if (found_edge_r) begin // Sticky bit - asserted after we encounter an edge, although // the current edge may not be considered the "first edge" this // just means we found at least one edge found_first_edge_r <= #TCQ 1'b1; // Only the right edge of the data valid window is found // Record the inner right edge tap value if (!found_first_edge_r && found_stable_eye_last_r) begin if (tap_cnt_cpt_r == 'd0) right_edge_taps_r <= #TCQ 'd0; else right_edge_taps_r <= #TCQ tap_cnt_cpt_r; end // Both edges of data valid window found: // If we've found a second edge after a region of stability // then we must have just passed the second ("right" edge of // the window. Record this second_edge_taps = current tap-1, // because we're one past the actual second edge tap, where // the edge taps represent the extremes of the data valid // window (i.e. smallest & largest taps where data still valid if (found_first_edge_r && found_stable_eye_last_r) begin found_second_edge_r <= #TCQ 1'b1; second_edge_taps_r <= #TCQ tap_cnt_cpt_r - 1; cal1_state_r <= #TCQ CAL1_CALC_IDEL; end else begin // Otherwise, an edge was found (just not the "second" edge) // Assuming DQS is in the correct window at tap 0 of Phaser IN // fine tap. The first edge found is the right edge of the valid // window and is the beginning of the jitter region hence done! first_edge_taps_r <= #TCQ tap_cnt_cpt_r; cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT; end end else // Otherwise, if we haven't found an edge.... // If we still have taps left to use, then keep incrementing cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT; end end // Increment Phaser_IN delay for DQS CAL1_IDEL_INC_CPT: begin cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT_WAIT; if (~tap_limit_cpt_r) begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b1; end else begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; end end // Wait for Phaser_In to settle, before checking again for an edge CAL1_IDEL_INC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_DETECT_EDGE; end // Calculate final value of Phaser_IN taps. At this point, one or both // edges of data eye have been found, and/or all taps have been // exhausted looking for the edges // NOTE: We're calculating the amount to decrement by, not the // absolute setting for DQS. CAL1_CALC_IDEL: begin // CASE1: If 2 edges found. if (found_second_edge_r) cnt_idel_dec_cpt_r <= #TCQ ((second_edge_taps_r - first_edge_taps_r)>>1) + 1; else if (right_edge_taps_r > 6'd0) // Only right edge detected // right_edge_taps_r is the inner right edge tap value // hence used for calculation cnt_idel_dec_cpt_r <= #TCQ (tap_cnt_cpt_r - (right_edge_taps_r>>1)); else if (found_first_edge_r) // Only left edge detected cnt_idel_dec_cpt_r <= #TCQ ((tap_cnt_cpt_r - first_edge_taps_r)>>1); else cnt_idel_dec_cpt_r <= #TCQ (tap_cnt_cpt_r>>1); // Now use the value we just calculated to decrement CPT taps // to the desired calibration point cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; end // decrement capture clock for final adjustment - center // capture clock in middle of data eye. This adjustment will occur // only when both the edges are found usign CPT taps. Must do this // incrementally to avoid clock glitching (since CPT drives clock // divider within each ISERDES) CAL1_IDEL_DEC_CPT: begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; // once adjustment is complete, we're done with calibration for // this DQS, repeat for next DQS cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; if (cnt_idel_dec_cpt_r == 6'b000001) begin if (mpr_dec_cpt_r) begin if (|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) begin idel_dec_cnt <= #TCQ idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC; end else cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; end else cal1_state_r <= #TCQ CAL1_NEXT_DQS; end else cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT_WAIT; end CAL1_IDEL_DEC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; end // Determine whether we're done, or have more DQS's to calibrate // Also request precharge after every byte, as appropriate CAL1_NEXT_DQS: begin //if (mpr_rdlvl_done_r || (DRAM_TYPE == "DDR2")) cal1_prech_req_r <= #TCQ 1'b1; //else // cal1_prech_req_r <= #TCQ 1'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; // Prepare for another iteration with next DQS group found_first_edge_r <= #TCQ 1'b0; found_second_edge_r <= #TCQ 1'b0; first_edge_taps_r <= #TCQ 'd0; second_edge_taps_r <= #TCQ 'd0; if ((SIM_CAL_OPTION == "FAST_CAL") || (cal1_cnt_cpt_r >= DQS_WIDTH-1)) begin if (mpr_rdlvl_done_r) begin rdlvl_last_byte_done <= #TCQ 1'b1; mpr_last_byte_done <= #TCQ 1'b0; end else begin rdlvl_last_byte_done <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b1; end end // Wait until precharge that occurs in between calibration of // DQS groups is finished if (prech_done) begin // || (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))) begin if (SIM_CAL_OPTION == "FAST_CAL") begin //rdlvl_rank_done_r <= #TCQ 1'b1; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_DONE; //CAL1_REGL_LOAD; end else if (cal1_cnt_cpt_r >= DQS_WIDTH-1) begin if (~mpr_rdlvl_done_r) begin mpr_rank_done_r <= #TCQ 1'b1; // if (rnk_cnt_r == RANKS-1) begin // All DQS groups in all ranks done cal1_state_r <= #TCQ CAL1_DONE; cal1_cnt_cpt_r <= #TCQ 'b0; // end else begin // // Process DQS groups in next rank // rnk_cnt_r <= #TCQ rnk_cnt_r + 1; // new_cnt_cpt_r <= #TCQ 1'b1; // cal1_cnt_cpt_r <= #TCQ 'b0; // cal1_state_r <= #TCQ CAL1_IDLE; // end end else begin // All DQS groups in a rank done rdlvl_rank_done_r <= #TCQ 1'b1; if (rnk_cnt_r == RANKS-1) begin // All DQS groups in all ranks done cal1_state_r <= #TCQ CAL1_REGL_LOAD; end else begin // Process DQS groups in next rank rnk_cnt_r <= #TCQ rnk_cnt_r + 1; new_cnt_cpt_r <= #TCQ 1'b1; cal1_cnt_cpt_r <= #TCQ 'b0; cal1_state_r <= #TCQ CAL1_IDLE; end end end else begin // Process next DQS group new_cnt_cpt_r <= #TCQ 1'b1; cal1_cnt_cpt_r <= #TCQ cal1_cnt_cpt_r + 1; cal1_state_r <= #TCQ CAL1_NEW_DQS_PREWAIT; end end end CAL1_NEW_DQS_PREWAIT: begin if (!cal1_wait_r) begin if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3")) cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT; else cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT; end end // Load rank registers in Phaser_IN CAL1_REGL_LOAD: begin rdlvl_rank_done_r <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; cal1_cnt_cpt_r <= #TCQ 'b0; rnk_cnt_r <= #TCQ 2'b00; if ((regl_rank_cnt == RANKS-1) && ((regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1))) begin cal1_state_r <= #TCQ CAL1_DONE; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; end else cal1_state_r <= #TCQ CAL1_REGL_LOAD; end CAL1_RDLVL_ERR: begin rdlvl_stg1_err <= #TCQ 1'b1; end // Done with this stage of calibration // if used, allow DEBUG_PORT to control taps CAL1_DONE: begin mpr_rdlvl_done_r <= #TCQ 1'b1; cal1_prech_req_r <= #TCQ 1'b0; if (~mpr_rdlvl_done_r && (OCAL_EN=="ON") && (DRAM_TYPE == "DDR3")) begin rdlvl_stg1_done <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_IDLE; end else rdlvl_stg1_done <= #TCQ 1'b1; end endcase end // verilint STARC-2.2.3.3 on endmodule
//***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_rdlvl.v // /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Read leveling Stage1 calibration logic // NOTES: // 1. Window detection with PRBS pattern. //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $ **$Date: 2011/06/24 14:49:00 $ **$Author: mgeorge $ **$Revision: 1.2 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_rdlvl.v,v $ ******************************************************************************/ `timescale 1ps/1ps (* use_dsp48 = "no" *) module mig_7series_v2_3_ddr_phy_rdlvl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter CLK_PERIOD = 3333, // Internal clock period (in ps) parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter RANKS = 1, // # of DRAM ranks parameter PER_BIT_DESKEW = "ON", // Enable per-bit DQ deskew parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps parameter DEBUG_PORT = "OFF", // Enable debug port parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" parameter OCAL_EN = "ON", parameter IDELAY_ADJ = "ON" ) ( input clk, input rst, // Calibration status, control signals input mpr_rdlvl_start, output mpr_rdlvl_done, output reg mpr_last_byte_done, output mpr_rnk_done, input rdlvl_stg1_start, output reg rdlvl_stg1_done /* synthesis syn_maxfan = 30 */, output rdlvl_stg1_rnk_done, output reg rdlvl_stg1_err, output mpr_rdlvl_err, output rdlvl_err, output reg rdlvl_prech_req, output reg rdlvl_last_byte_done, output reg rdlvl_assrt_common, input prech_done, input phy_if_empty, input [4:0] idelaye2_init_val, // Captured data in fabric clock domain input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Decrement initial Phaser_IN Fine tap delay input dqs_po_dec_done, input [5:0] pi_counter_read_val, // Stage 1 calibration outputs output reg pi_fine_dly_dec_done, output reg pi_en_stg2_f, output reg pi_stg2_f_incdec, output reg pi_stg2_load, output reg [5:0] pi_stg2_reg_l, output [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt, // To DQ IDELAY required to find left edge of // valid window output idelay_ce, output idelay_inc, input idelay_ld, input [DQS_CNT_WIDTH:0] wrcal_cnt, // Only output if Per-bit de-skew enabled output reg [5*RANKS*DQ_WIDTH-1:0] dlyval_dq, // Debug Port output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, input dbg_idel_up_all, input dbg_idel_down_all, input dbg_idel_up_cpt, input dbg_idel_down_cpt, input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, input dbg_sel_all_idel_cpt, output [255:0] dbg_phy_rdlvl ); // minimum time (in IDELAY taps) for which capture data must be stable for // algorithm to consider a valid data eye to be found. The read leveling // logic will ignore any window found smaller than this value. Limitations // on how small this number can be is determined by: (1) the algorithmic // limitation of how many taps wide the data eye can be (3 taps), and (2) // how wide regions of "instability" that occur around the edges of the // read valid window can be (i.e. need to be able to filter out "false" // windows that occur for a short # of taps around the edges of the true // data window, although with multi-sampling during read leveling, this is // not as much a concern) - the larger the value, the more protection // against "false" windows localparam MIN_EYE_SIZE = 16; // Length of calibration sequence (in # of words) localparam CAL_PAT_LEN = 8; // Read data shift register length localparam RD_SHIFT_LEN = CAL_PAT_LEN / (2*nCK_PER_CLK); // # of cycles required to perform read data shift register compare // This is defined as from the cycle the new data is loaded until // signal found_edge_r is valid localparam RD_SHIFT_COMP_DELAY = 5; // worst-case # of cycles to wait to ensure that both the SR and // PREV_SR shift registers have valid data, and that the comparison // of the two shift register values is valid. The "+1" at the end of // this equation is a fudge factor, I freely admit that localparam SR_VALID_DELAY = (2 * RD_SHIFT_LEN) + RD_SHIFT_COMP_DELAY + 1; // # of clock cycles to wait after changing tap value or read data MUX // to allow: (1) tap chain to settle, (2) for delayed input to propagate // thru ISERDES, (3) for the read data comparison logic to have time to // output the comparison of two consecutive samples of the settled read data // The minimum delay is 16 cycles, which should be good enough to handle all // three of the above conditions for the simulation-only case with a short // training pattern. For H/W (or for simulation with longer training // pattern), it will take longer to store and compare two consecutive // samples, and the value of this parameter will reflect that localparam PIPE_WAIT_CNT = (SR_VALID_DELAY < 8) ? 16 : (SR_VALID_DELAY + 8); // # of read data samples to examine when detecting whether an edge has // occured during stage 1 calibration. Width of local param must be // changed as appropriate. Note that there are two counters used, each // counter can be changed independently of the other - they are used in // cascade to create a larger counter localparam [11:0] DETECT_EDGE_SAMPLE_CNT0 = 12'h001; //12'hFFF; localparam [11:0] DETECT_EDGE_SAMPLE_CNT1 = 12'h001; // 12'h1FF Must be > 0 localparam [5:0] CAL1_IDLE = 6'h00; localparam [5:0] CAL1_NEW_DQS_WAIT = 6'h01; localparam [5:0] CAL1_STORE_FIRST_WAIT = 6'h02; localparam [5:0] CAL1_PAT_DETECT = 6'h03; localparam [5:0] CAL1_DQ_IDEL_TAP_INC = 6'h04; localparam [5:0] CAL1_DQ_IDEL_TAP_INC_WAIT = 6'h05; localparam [5:0] CAL1_DQ_IDEL_TAP_DEC = 6'h06; localparam [5:0] CAL1_DQ_IDEL_TAP_DEC_WAIT = 6'h07; localparam [5:0] CAL1_DETECT_EDGE = 6'h08; localparam [5:0] CAL1_IDEL_INC_CPT = 6'h09; localparam [5:0] CAL1_IDEL_INC_CPT_WAIT = 6'h0A; localparam [5:0] CAL1_CALC_IDEL = 6'h0B; localparam [5:0] CAL1_IDEL_DEC_CPT = 6'h0C; localparam [5:0] CAL1_IDEL_DEC_CPT_WAIT = 6'h0D; localparam [5:0] CAL1_NEXT_DQS = 6'h0E; localparam [5:0] CAL1_DONE = 6'h0F; localparam [5:0] CAL1_PB_STORE_FIRST_WAIT = 6'h10; localparam [5:0] CAL1_PB_DETECT_EDGE = 6'h11; localparam [5:0] CAL1_PB_INC_CPT = 6'h12; localparam [5:0] CAL1_PB_INC_CPT_WAIT = 6'h13; localparam [5:0] CAL1_PB_DEC_CPT_LEFT = 6'h14; localparam [5:0] CAL1_PB_DEC_CPT_LEFT_WAIT = 6'h15; localparam [5:0] CAL1_PB_DETECT_EDGE_DQ = 6'h16; localparam [5:0] CAL1_PB_INC_DQ = 6'h17; localparam [5:0] CAL1_PB_INC_DQ_WAIT = 6'h18; localparam [5:0] CAL1_PB_DEC_CPT = 6'h19; localparam [5:0] CAL1_PB_DEC_CPT_WAIT = 6'h1A; localparam [5:0] CAL1_REGL_LOAD = 6'h1B; localparam [5:0] CAL1_RDLVL_ERR = 6'h1C; localparam [5:0] CAL1_MPR_NEW_DQS_WAIT = 6'h1D; localparam [5:0] CAL1_VALID_WAIT = 6'h1E; localparam [5:0] CAL1_MPR_PAT_DETECT = 6'h1F; localparam [5:0] CAL1_NEW_DQS_PREWAIT = 6'h20; integer a; integer b; integer d; integer e; integer f; integer h; integer g; integer i; integer j; integer k; integer l; integer m; integer n; integer r; integer p; integer q; integer s; integer t; integer u; integer w; integer ce_i; integer ce_rnk_i; integer aa; integer bb; integer cc; integer dd; genvar x; genvar z; reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_r; wire [DQS_CNT_WIDTH+2:0]cal1_cnt_cpt_timing; reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_timing_r; reg cal1_dq_idel_ce; reg cal1_dq_idel_inc; reg cal1_dlyce_cpt_r; reg cal1_dlyinc_cpt_r; reg cal1_dlyce_dq_r; reg cal1_dlyinc_dq_r; reg cal1_wait_cnt_en_r; reg [4:0] cal1_wait_cnt_r; reg cal1_wait_r; reg [DQ_WIDTH-1:0] dlyce_dq_r; reg dlyinc_dq_r; reg [4:0] dlyval_dq_reg_r [0:RANKS-1][0:DQ_WIDTH-1]; reg cal1_prech_req_r; reg [5:0] cal1_state_r; reg [5:0] cal1_state_r1; reg [5:0] cnt_idel_dec_cpt_r; reg [3:0] cnt_shift_r; reg detect_edge_done_r; reg [5:0] right_edge_taps_r; reg [5:0] first_edge_taps_r; reg found_edge_r; reg found_first_edge_r; reg found_second_edge_r; reg found_stable_eye_r; reg found_stable_eye_last_r; reg found_edge_all_r; reg [5:0] tap_cnt_cpt_r; reg tap_limit_cpt_r; reg [4:0] idel_tap_cnt_dq_pb_r; reg idel_tap_limit_dq_pb_r; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r; reg mux_rd_valid_r; reg new_cnt_cpt_r; reg [RD_SHIFT_LEN-1:0] old_sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise3_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] old_sr_match_fall0_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall1_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise0_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise1_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall2_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall3_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise2_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise3_r; reg [4:0] pb_cnt_eye_size_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] pb_detect_edge_done_r; reg [DRAM_WIDTH-1:0] pb_found_edge_last_r; reg [DRAM_WIDTH-1:0] pb_found_edge_r; reg [DRAM_WIDTH-1:0] pb_found_first_edge_r; reg [DRAM_WIDTH-1:0] pb_found_stable_eye_r; reg [DRAM_WIDTH-1:0] pb_last_tap_jitter_r; reg pi_en_stg2_f_timing; reg pi_stg2_f_incdec_timing; reg pi_stg2_load_timing; reg [5:0] pi_stg2_reg_l_timing; reg [DRAM_WIDTH-1:0] prev_sr_diff_r; reg [RD_SHIFT_LEN-1:0] prev_sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise3_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] prev_sr_match_cyc2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall0_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall1_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise0_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise1_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall3_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise3_r; wire [DQ_WIDTH-1:0] rd_data_rise0; wire [DQ_WIDTH-1:0] rd_data_fall0; wire [DQ_WIDTH-1:0] rd_data_rise1; wire [DQ_WIDTH-1:0] rd_data_fall1; wire [DQ_WIDTH-1:0] rd_data_rise2; wire [DQ_WIDTH-1:0] rd_data_fall2; wire [DQ_WIDTH-1:0] rd_data_rise3; wire [DQ_WIDTH-1:0] rd_data_fall3; reg samp_cnt_done_r; reg samp_edge_cnt0_en_r; reg [11:0] samp_edge_cnt0_r; reg samp_edge_cnt1_en_r; reg [11:0] samp_edge_cnt1_r; reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; reg [5:0] second_edge_taps_r; reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0]; reg store_sr_r; reg store_sr_req_pulsed_r; reg store_sr_req_r; reg sr_valid_r; reg sr_valid_r1; reg sr_valid_r2; reg [DRAM_WIDTH-1:0] old_sr_diff_r; reg [DRAM_WIDTH-1:0] old_sr_match_cyc2_r; reg pat0_data_match_r; reg pat1_data_match_r; wire pat_data_match_r; wire [RD_SHIFT_LEN-1:0] pat0_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall3 [3:0]; reg [DRAM_WIDTH-1:0] pat0_match_fall0_r; reg pat0_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall1_r; reg pat0_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall2_r; reg pat0_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall3_r; reg pat0_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise0_r; reg pat0_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise1_r; reg pat0_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise2_r; reg pat0_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise3_r; reg pat0_match_rise3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall0_r; reg pat1_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall1_r; reg pat1_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall2_r; reg pat1_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall3_r; reg pat1_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise0_r; reg pat1_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise1_r; reg pat1_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise2_r; reg pat1_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise3_r; reg pat1_match_rise3_and_r; reg [4:0] idelay_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1]; reg [5*DQS_WIDTH*RANKS-1:0] idelay_tap_cnt_w; reg [4:0] idelay_tap_cnt_slice_r; reg idelay_tap_limit_r; wire [RD_SHIFT_LEN-1:0] pat0_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall3 [3:0]; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise0_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall0_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise1_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall1_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise2_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall2_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise3_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall3_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise0_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall0_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise1_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall1_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise2_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall2_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise3_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall3_r; reg idel_pat0_match_rise0_and_r; reg idel_pat0_match_fall0_and_r; reg idel_pat0_match_rise1_and_r; reg idel_pat0_match_fall1_and_r; reg idel_pat0_match_rise2_and_r; reg idel_pat0_match_fall2_and_r; reg idel_pat0_match_rise3_and_r; reg idel_pat0_match_fall3_and_r; reg idel_pat1_match_rise0_and_r; reg idel_pat1_match_fall0_and_r; reg idel_pat1_match_rise1_and_r; reg idel_pat1_match_fall1_and_r; reg idel_pat1_match_rise2_and_r; reg idel_pat1_match_fall2_and_r; reg idel_pat1_match_rise3_and_r; reg idel_pat1_match_fall3_and_r; reg idel_pat0_data_match_r; reg idel_pat1_data_match_r; reg idel_pat_data_match; reg idel_pat_data_match_r; reg [4:0] idel_dec_cnt; reg [5:0] rdlvl_dqs_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1]; reg [1:0] rnk_cnt_r; reg rdlvl_rank_done_r; reg [3:0] done_cnt; reg [1:0] regl_rank_cnt; reg [DQS_CNT_WIDTH:0] regl_dqs_cnt; reg [DQS_CNT_WIDTH:0] regl_dqs_cnt_r; wire [DQS_CNT_WIDTH+2:0]regl_dqs_cnt_timing; reg regl_rank_done_r; reg rdlvl_stg1_start_r; reg dqs_po_dec_done_r1; reg dqs_po_dec_done_r2; reg fine_dly_dec_done_r1; reg fine_dly_dec_done_r2; reg [3:0] wait_cnt_r; reg [5:0] pi_rdval_cnt; reg pi_cnt_dec; reg mpr_valid_r; reg mpr_valid_r1; reg mpr_valid_r2; reg mpr_rd_rise0_prev_r; reg mpr_rd_fall0_prev_r; reg mpr_rd_rise1_prev_r; reg mpr_rd_fall1_prev_r; reg mpr_rd_rise2_prev_r; reg mpr_rd_fall2_prev_r; reg mpr_rd_rise3_prev_r; reg mpr_rd_fall3_prev_r; reg mpr_rdlvl_done_r; reg mpr_rdlvl_done_r1; reg mpr_rdlvl_done_r2; reg mpr_rdlvl_start_r; reg mpr_rank_done_r; reg [2:0] stable_idel_cnt; reg inhibit_edge_detect_r; reg idel_pat_detect_valid_r; reg idel_mpr_pat_detect_r; reg mpr_pat_detect_r; reg mpr_dec_cpt_r; reg idel_adj_inc; //IDELAY adjustment wire [1:0] idelay_adj; wire pb_detect_edge_setup; wire pb_detect_edge; // Debug reg [6*DQS_WIDTH-1:0] dbg_cpt_first_edge_taps; reg [6*DQS_WIDTH-1:0] dbg_cpt_second_edge_taps; reg [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt_w; //IDELAY adjustment setting for -1 //2'b10 : IDELAY - 1 //2'b01 : IDELAY + 1 //2'b00 : No IDELAY adjustment assign idelay_adj = (IDELAY_ADJ == "ON") ? 2'b10: 2'b00; //*************************************************************************** // Debug //*************************************************************************** always @(*) begin for (d = 0; d < RANKS; d = d + 1) begin for (e = 0; e < DQS_WIDTH; e = e + 1) begin idelay_tap_cnt_w[(5*e+5*DQS_WIDTH*d)+:5] = idelay_tap_cnt_r[d][e]; dbg_cpt_tap_cnt_w[(6*e+6*DQS_WIDTH*d)+:6] = rdlvl_dqs_tap_cnt_r[d][e]; end end end assign mpr_rdlvl_err = rdlvl_stg1_err & (!mpr_rdlvl_done); assign rdlvl_err = rdlvl_stg1_err & (mpr_rdlvl_done); assign dbg_phy_rdlvl[0] = rdlvl_stg1_start; assign dbg_phy_rdlvl[1] = pat_data_match_r; assign dbg_phy_rdlvl[2] = mux_rd_valid_r; assign dbg_phy_rdlvl[3] = idelay_tap_limit_r; assign dbg_phy_rdlvl[8:4] = 'b0; assign dbg_phy_rdlvl[14:9] = cal1_state_r[5:0]; assign dbg_phy_rdlvl[20:15] = cnt_idel_dec_cpt_r; assign dbg_phy_rdlvl[21] = found_first_edge_r; assign dbg_phy_rdlvl[22] = found_second_edge_r; assign dbg_phy_rdlvl[23] = found_edge_r; assign dbg_phy_rdlvl[24] = store_sr_r; // [40:25] previously used for sr, old_sr shift registers. If connecting // these signals again, don't forget to parameterize based on RD_SHIFT_LEN assign dbg_phy_rdlvl[40:25] = 'b0; assign dbg_phy_rdlvl[41] = sr_valid_r; assign dbg_phy_rdlvl[42] = found_stable_eye_r; assign dbg_phy_rdlvl[48:43] = tap_cnt_cpt_r; assign dbg_phy_rdlvl[54:49] = first_edge_taps_r; assign dbg_phy_rdlvl[60:55] = second_edge_taps_r; assign dbg_phy_rdlvl[64:61] = cal1_cnt_cpt_timing_r; assign dbg_phy_rdlvl[65] = cal1_dlyce_cpt_r; assign dbg_phy_rdlvl[66] = cal1_dlyinc_cpt_r; assign dbg_phy_rdlvl[67] = found_edge_r; assign dbg_phy_rdlvl[68] = found_first_edge_r; assign dbg_phy_rdlvl[73:69] = 'b0; assign dbg_phy_rdlvl[74] = idel_pat_data_match; assign dbg_phy_rdlvl[75] = idel_pat0_data_match_r; assign dbg_phy_rdlvl[76] = idel_pat1_data_match_r; assign dbg_phy_rdlvl[77] = pat0_data_match_r; assign dbg_phy_rdlvl[78] = pat1_data_match_r; assign dbg_phy_rdlvl[79+:5*DQS_WIDTH*RANKS] = idelay_tap_cnt_w; assign dbg_phy_rdlvl[170+:8] = mux_rd_rise0_r; assign dbg_phy_rdlvl[178+:8] = mux_rd_fall0_r; assign dbg_phy_rdlvl[186+:8] = mux_rd_rise1_r; assign dbg_phy_rdlvl[194+:8] = mux_rd_fall1_r; assign dbg_phy_rdlvl[202+:8] = mux_rd_rise2_r; assign dbg_phy_rdlvl[210+:8] = mux_rd_fall2_r; assign dbg_phy_rdlvl[218+:8] = mux_rd_rise3_r; assign dbg_phy_rdlvl[226+:8] = mux_rd_fall3_r; //*************************************************************************** // Debug output //*************************************************************************** // CPT taps assign dbg_cpt_first_edge_cnt = dbg_cpt_first_edge_taps; assign dbg_cpt_second_edge_cnt = dbg_cpt_second_edge_taps; assign dbg_cpt_tap_cnt = dbg_cpt_tap_cnt_w; assign dbg_dq_idelay_tap_cnt = idelay_tap_cnt_w; // Record first and second edges found during CPT calibration generate always @(posedge clk) if (rst) begin dbg_cpt_first_edge_taps <= #TCQ 'b0; dbg_cpt_second_edge_taps <= #TCQ 'b0; end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_CALC_IDEL)) begin //for (ce_rnk_i = 0; ce_rnk_i < RANKS; ce_rnk_i = ce_rnk_i + 1) begin: gen_dbg_cpt_rnk for (ce_i = 0; ce_i < DQS_WIDTH; ce_i = ce_i + 1) begin: gen_dbg_cpt_edge if (found_first_edge_r) dbg_cpt_first_edge_taps[(6*ce_i)+:6] <= #TCQ first_edge_taps_r; if (found_second_edge_r) dbg_cpt_second_edge_taps[(6*ce_i)+:6] <= #TCQ second_edge_taps_r; end //end end else if (cal1_state_r == CAL1_CALC_IDEL) begin // Record tap counts of first and second edge edges during // CPT calibration for each DQS group. If neither edge has // been found, then those taps will remain 0 if (found_first_edge_r) dbg_cpt_first_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6] <= #TCQ first_edge_taps_r; if (found_second_edge_r) dbg_cpt_second_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6] <= #TCQ second_edge_taps_r; end endgenerate assign rdlvl_stg1_rnk_done = rdlvl_rank_done_r;// || regl_rank_done_r; assign mpr_rnk_done = mpr_rank_done_r; assign mpr_rdlvl_done = ((DRAM_TYPE == "DDR3") && (OCAL_EN == "ON")) ? //&& (SIM_CAL_OPTION == "NONE") mpr_rdlvl_done_r : 1'b1; //************************************************************************** // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 // coarse delay //************************************************************************** assign pi_stg2_rdlvl_cnt = (cal1_state_r == CAL1_REGL_LOAD) ? regl_dqs_cnt_r : cal1_cnt_cpt_r; assign idelay_ce = cal1_dq_idel_ce; assign idelay_inc = cal1_dq_idel_inc; //*************************************************************************** // Assert calib_in_common in FAST_CAL mode for IDELAY tap increments to all // DQs simultaneously //*************************************************************************** always @(posedge clk) begin if (rst) rdlvl_assrt_common <= #TCQ 1'b0; else if ((SIM_CAL_OPTION == "FAST_CAL") & rdlvl_stg1_start & !rdlvl_stg1_start_r) rdlvl_assrt_common <= #TCQ 1'b1; else if (!idel_pat_data_match_r & idel_pat_data_match) rdlvl_assrt_common <= #TCQ 1'b0; end //*************************************************************************** // Data mux to route appropriate bit to calibration logic - i.e. calibration // is done sequentially, one bit (or DQS group) at a time //*************************************************************************** generate if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; end else begin: rd_data_div2_logic_clk assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; end endgenerate always @(posedge clk) begin rd_mux_sel_r <= #TCQ cal1_cnt_cpt_r; end // Register outputs for improved timing. // NOTE: Will need to change when per-bit DQ deskew is supported. // Currenly all bits in DQS group are checked in aggregate generate genvar mux_i; for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end endgenerate //*************************************************************************** // MPR Read Leveling //*************************************************************************** // storing the previous read data for checking later. Only bit 0 is used // since MPR contents (01010101) are available generally on DQ[0] per // JEDEC spec. always @(posedge clk)begin if ((cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) || ((cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r)))begin mpr_rd_rise0_prev_r <= #TCQ mux_rd_rise0_r[0]; mpr_rd_fall0_prev_r <= #TCQ mux_rd_fall0_r[0]; mpr_rd_rise1_prev_r <= #TCQ mux_rd_rise1_r[0]; mpr_rd_fall1_prev_r <= #TCQ mux_rd_fall1_r[0]; mpr_rd_rise2_prev_r <= #TCQ mux_rd_rise2_r[0]; mpr_rd_fall2_prev_r <= #TCQ mux_rd_fall2_r[0]; mpr_rd_rise3_prev_r <= #TCQ mux_rd_rise3_r[0]; mpr_rd_fall3_prev_r <= #TCQ mux_rd_fall3_r[0]; end end generate if (nCK_PER_CLK == 4) begin: mpr_4to1 // changed stable count of 2 IDELAY taps at 78 ps resolution always @(posedge clk) begin if (rst | (cal1_state_r == CAL1_NEW_DQS_PREWAIT) | //(cal1_state_r == CAL1_DETECT_EDGE) | (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) | (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) | (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) | (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) | (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) | (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) | (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) | (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0])) stable_idel_cnt <= #TCQ 3'd0; else if ((|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) & ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) begin if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) & (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) & (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) & (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) & (mpr_rd_rise2_prev_r == mux_rd_rise2_r[0]) & (mpr_rd_fall2_prev_r == mux_rd_fall2_r[0]) & (mpr_rd_rise3_prev_r == mux_rd_rise3_r[0]) & (mpr_rd_fall3_prev_r == mux_rd_fall3_r[0]) & (stable_idel_cnt < 3'd2)) stable_idel_cnt <= #TCQ stable_idel_cnt + 1; end end always @(posedge clk) begin if (rst | (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r & mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r & mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r)) inhibit_edge_detect_r <= 1'b1; // Wait for settling time after idelay tap increment before // de-asserting inhibit_edge_detect_r else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) & (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r & ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r & ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r)) inhibit_edge_detect_r <= 1'b0; end //checking for transition from 01010101 to 10101010 always @(posedge clk)begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | inhibit_edge_detect_r) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 10101010 is not the correct pattern else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r & mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r & mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r) || ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r))) //|| (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2)) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 01010101 to 10101010 is the correct transition else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r & ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r & ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r) & (stable_idel_cnt == 3'd2) & ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) || (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) || (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) || (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) || (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) || (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) || (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) || (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0]))) idel_mpr_pat_detect_r <= #TCQ 1'b1; end end else if (nCK_PER_CLK == 2) begin: mpr_2to1 // changed stable count of 2 IDELAY taps at 78 ps resolution always @(posedge clk) begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) | (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) | (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) | (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0])) stable_idel_cnt <= #TCQ 3'd0; else if ((idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd0) & ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) begin if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) & (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) & (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) & (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) & (stable_idel_cnt < 3'd2)) stable_idel_cnt <= #TCQ stable_idel_cnt + 1; end end always @(posedge clk) begin if (rst | (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r)) inhibit_edge_detect_r <= 1'b1; else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) & (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r)) inhibit_edge_detect_r <= 1'b0; end //checking for transition from 01010101 to 10101010 always @(posedge clk)begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | inhibit_edge_detect_r) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 1010 is not the correct pattern else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r) || ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) // ||(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2)) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 0101 to 1010 is the correct transition else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r) & (stable_idel_cnt == 3'd2) & ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) || (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) || (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) || (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]))) idel_mpr_pat_detect_r <= #TCQ 1'b1; end end endgenerate // Registered signal indicates when mux_rd_rise/fall_r is valid always @(posedge clk) mux_rd_valid_r <= #TCQ ~phy_if_empty; //*************************************************************************** // Decrement initial Phaser_IN fine delay value before proceeding with // read calibration //*************************************************************************** always @(posedge clk) begin dqs_po_dec_done_r1 <= #TCQ dqs_po_dec_done; dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1; fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1; pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r2; end always @(posedge clk) begin if (rst || pi_cnt_dec) wait_cnt_r <= #TCQ 'd8; else if (dqs_po_dec_done_r2 && (wait_cnt_r > 'd0)) wait_cnt_r <= #TCQ wait_cnt_r - 1; end always @(posedge clk) begin if (rst) begin pi_rdval_cnt <= #TCQ 'd0; end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin pi_rdval_cnt <= #TCQ pi_counter_read_val; end else if (pi_rdval_cnt > 'd0) begin if (pi_cnt_dec) pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1; else pi_rdval_cnt <= #TCQ pi_rdval_cnt; end else if (pi_rdval_cnt == 'd0) begin pi_rdval_cnt <= #TCQ pi_rdval_cnt; end end always @(posedge clk) begin if (rst || (pi_rdval_cnt == 'd0)) pi_cnt_dec <= #TCQ 1'b0; else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0) && (wait_cnt_r == 'd1)) pi_cnt_dec <= #TCQ 1'b1; else pi_cnt_dec <= #TCQ 1'b0; end always @(posedge clk) begin if (rst) begin fine_dly_dec_done_r1 <= #TCQ 1'b0; end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) || (dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin fine_dly_dec_done_r1 <= #TCQ 1'b1; end end //*************************************************************************** // Demultiplexor to control Phaser_IN delay values //*************************************************************************** // Read DQS always @(posedge clk) begin if (rst) begin pi_en_stg2_f_timing <= #TCQ 'b0; pi_stg2_f_incdec_timing <= #TCQ 'b0; end else if (pi_cnt_dec) begin pi_en_stg2_f_timing <= #TCQ 'b1; pi_stg2_f_incdec_timing <= #TCQ 'b0; end else if (cal1_dlyce_cpt_r) begin if ((SIM_CAL_OPTION == "NONE") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin // Change only specified DQS pi_en_stg2_f_timing <= #TCQ 1'b1; pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r; end else if (SIM_CAL_OPTION == "FAST_CAL") begin // if simulating, and "shortcuts" for calibration enabled, apply // results to all DQSs (i.e. assume same delay on all // DQSs). pi_en_stg2_f_timing <= #TCQ 1'b1; pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r; end end else begin pi_en_stg2_f_timing <= #TCQ 'b0; pi_stg2_f_incdec_timing <= #TCQ 'b0; end end // registered for timing always @(posedge clk) begin pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing; pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing; end // This counter used to implement settling time between // Phaser_IN rank register loads to different DQSs always @(posedge clk) begin if (rst) done_cnt <= #TCQ 'b0; else if (((cal1_state_r == CAL1_REGL_LOAD) && (cal1_state_r1 == CAL1_NEXT_DQS)) || ((done_cnt == 4'd1) && (cal1_state_r != CAL1_DONE))) done_cnt <= #TCQ 4'b1010; else if (done_cnt > 'b0) done_cnt <= #TCQ done_cnt - 1; end // During rank register loading the rank count must be sent to // Phaser_IN via the phy_ctl_wd?? If so phy_init will have to // issue NOPs during rank register loading with the appropriate // rank count always @(posedge clk) begin if (rst || (regl_rank_done_r == 1'b1)) regl_rank_done_r <= #TCQ 1'b0; else if ((regl_dqs_cnt == DQS_WIDTH-1) && (regl_rank_cnt != RANKS-1) && (done_cnt == 4'd1)) regl_rank_done_r <= #TCQ 1'b1; end // Temp wire for timing. // The following in the always block below causes timing issues // due to DSP block inference // 6*regl_dqs_cnt. // replacing this with two left shifts + 1 left shift to avoid // DSP multiplier. assign regl_dqs_cnt_timing = {2'd0, regl_dqs_cnt}; // Load Phaser_OUT rank register with rdlvl delay value // for each DQS per rank. always @(posedge clk) begin if (rst || (done_cnt == 4'd0)) begin pi_stg2_load_timing <= #TCQ 'b0; pi_stg2_reg_l_timing <= #TCQ 'b0; end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt <= DQS_WIDTH-1) && (done_cnt == 4'd1)) begin pi_stg2_load_timing <= #TCQ 'b1; pi_stg2_reg_l_timing <= #TCQ rdlvl_dqs_tap_cnt_r[rnk_cnt_r][regl_dqs_cnt]; end else begin pi_stg2_load_timing <= #TCQ 'b0; pi_stg2_reg_l_timing <= #TCQ 'b0; end end // registered for timing always @(posedge clk) begin pi_stg2_load <= #TCQ pi_stg2_load_timing; pi_stg2_reg_l <= #TCQ pi_stg2_reg_l_timing; end always @(posedge clk) begin if (rst || (done_cnt == 4'd0) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) regl_rank_cnt <= #TCQ 2'b00; else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin if (regl_rank_cnt == RANKS-1) regl_rank_cnt <= #TCQ regl_rank_cnt; else regl_rank_cnt <= #TCQ regl_rank_cnt + 1; end end always @(posedge clk) begin if (rst || (done_cnt == 4'd0) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) regl_dqs_cnt <= #TCQ {DQS_CNT_WIDTH+1{1'b0}}; else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin if (regl_rank_cnt == RANKS-1) regl_dqs_cnt <= #TCQ regl_dqs_cnt; else regl_dqs_cnt <= #TCQ 'b0; end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt != DQS_WIDTH-1) && (done_cnt == 4'd1)) regl_dqs_cnt <= #TCQ regl_dqs_cnt + 1; else regl_dqs_cnt <= #TCQ regl_dqs_cnt; end always @(posedge clk) regl_dqs_cnt_r <= #TCQ regl_dqs_cnt; //***************************************************************** // DQ Stage 1 CALIBRATION INCREMENT/DECREMENT LOGIC: // The actual IDELAY elements for each of the DQ bits is set via the // DLYVAL parallel load port. However, the stage 1 calibration // algorithm (well most of it) only needs to increment or decrement the DQ // IDELAY value by 1 at any one time. //***************************************************************** // Chip-select generation for each of the individual counters tracking // IDELAY tap values for each DQ generate for (z = 0; z < DQS_WIDTH; z = z + 1) begin: gen_dlyce_dq always @(posedge clk) if (rst) dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; else if (SIM_CAL_OPTION == "SKIP_CAL") // If skipping calibration altogether (only for simulation), no // need to set DQ IODELAY values - they are hardcoded dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; else if (SIM_CAL_OPTION == "FAST_CAL") begin // If fast calibration option (simulation only) selected, DQ // IODELAYs across all bytes are updated simultaneously // (although per-bit deskew within DQS[0] is still supported) for (h = 0; h < DRAM_WIDTH; h = h + 1) begin dlyce_dq_r[DRAM_WIDTH*z + h] <= #TCQ cal1_dlyce_dq_r; end end else if ((SIM_CAL_OPTION == "NONE") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin if (cal1_cnt_cpt_r == z) begin for (g = 0; g < DRAM_WIDTH; g = g + 1) begin dlyce_dq_r[DRAM_WIDTH*z + g] <= #TCQ cal1_dlyce_dq_r; end end else dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; end end endgenerate // Also delay increment/decrement control to match delay on DLYCE always @(posedge clk) if (rst) dlyinc_dq_r <= #TCQ 1'b0; else dlyinc_dq_r <= #TCQ cal1_dlyinc_dq_r; // Each DQ has a counter associated with it to record current read-leveling // delay value always @(posedge clk) // Reset or skipping calibration all together if (rst | (SIM_CAL_OPTION == "SKIP_CAL")) begin for (aa = 0; aa < RANKS; aa = aa + 1) begin: rst_dlyval_dq_reg_r for (bb = 0; bb < DQ_WIDTH; bb = bb + 1) dlyval_dq_reg_r[aa][bb] <= #TCQ 'b0; end end else if (SIM_CAL_OPTION == "FAST_CAL") begin for (n = 0; n < RANKS; n = n + 1) begin: gen_dlyval_dq_reg_rnk for (r = 0; r < DQ_WIDTH; r = r + 1) begin: gen_dlyval_dq_reg if (dlyce_dq_r[r]) begin if (dlyinc_dq_r) dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] + 5'h01; else dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] - 5'h01; end end end end else begin if (dlyce_dq_r[cal1_cnt_cpt_r]) begin if (dlyinc_dq_r) dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] + 5'h01; else dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] - 5'h01; end end // Register for timing (help with logic placement) always @(posedge clk) begin for (cc = 0; cc < RANKS; cc = cc + 1) begin: dlyval_dq_assgn for (dd = 0; dd < DQ_WIDTH; dd = dd + 1) dlyval_dq[((5*dd)+(cc*DQ_WIDTH*5))+:5] <= #TCQ dlyval_dq_reg_r[cc][dd]; end end //*************************************************************************** // Generate signal used to delay calibration state machine - used when: // (1) IDELAY value changed // (2) RD_MUX_SEL value changed // Use when a delay is necessary to give the change time to propagate // through the data pipeline (through IDELAY and ISERDES, and fabric // pipeline stages) //*************************************************************************** // List all the stage 1 calibration wait states here. // verilint STARC-2.7.3.3b off always @(posedge clk) if ((cal1_state_r == CAL1_NEW_DQS_WAIT) || (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) || (cal1_state_r == CAL1_NEW_DQS_PREWAIT) || (cal1_state_r == CAL1_VALID_WAIT) || (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_INC_CPT_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT) || (cal1_state_r == CAL1_PB_INC_DQ_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_WAIT) || (cal1_state_r == CAL1_IDEL_INC_CPT_WAIT) || (cal1_state_r == CAL1_IDEL_DEC_CPT_WAIT) || (cal1_state_r == CAL1_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_DQ_IDEL_TAP_INC_WAIT) || (cal1_state_r == CAL1_DQ_IDEL_TAP_DEC_WAIT)) cal1_wait_cnt_en_r <= #TCQ 1'b1; else cal1_wait_cnt_en_r <= #TCQ 1'b0; // verilint STARC-2.7.3.3b on always @(posedge clk) if (!cal1_wait_cnt_en_r) begin cal1_wait_cnt_r <= #TCQ 5'b00000; cal1_wait_r <= #TCQ 1'b1; end else begin if (cal1_wait_cnt_r != PIPE_WAIT_CNT - 1) begin cal1_wait_cnt_r <= #TCQ cal1_wait_cnt_r + 1; cal1_wait_r <= #TCQ 1'b1; end else begin // Need to reset to 0 to handle the case when there are two // different WAIT states back-to-back cal1_wait_cnt_r <= #TCQ 5'b00000; cal1_wait_r <= #TCQ 1'b0; end end //*************************************************************************** // generate request to PHY_INIT logic to issue precharged. Required when // calibration can take a long time (during which there are only constant // reads present on this bus). In this case need to issue perioidic // precharges to avoid tRAS violation. This signal must meet the following // requirements: (1) only transition from 0->1 when prech is first needed, // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted //*************************************************************************** always @(posedge clk) if (rst) rdlvl_prech_req <= #TCQ 1'b0; else rdlvl_prech_req <= #TCQ cal1_prech_req_r; //*************************************************************************** // Serial-to-parallel register to store last RDDATA_SHIFT_LEN cycles of // data from ISERDES. The value of this register is also stored, so that // previous and current values of the ISERDES data can be compared while // varying the IODELAY taps to see if an "edge" of the data valid window // has been encountered since the last IODELAY tap adjustment //*************************************************************************** //*************************************************************************** // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES // NOTE: Written using discrete flops, but SRL can be used if the matching // logic does the comparison sequentially, rather than parallel //*************************************************************************** generate genvar rd_i; if (nCK_PER_CLK == 4) begin: gen_sr_div4 if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i]; sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i]; sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i]; sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i]; end end end end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall1_r[rd_i]}; sr_rise2_r[rd_i] <= #TCQ {sr_rise2_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise2_r[rd_i]}; sr_fall2_r[rd_i] <= #TCQ {sr_fall2_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall2_r[rd_i]}; sr_rise3_r[rd_i] <= #TCQ {sr_rise3_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise3_r[rd_i]}; sr_fall3_r[rd_i] <= #TCQ {sr_fall3_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall3_r[rd_i]}; end end end end end else if (nCK_PER_CLK == 2) begin: gen_sr_div2 if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {mux_rd_fall1_r[rd_i]}; end end end end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall1_r[rd_i]}; end end end end end endgenerate //*************************************************************************** // Conversion to pattern calibration //*************************************************************************** // Pattern for DQ IDELAY calibration //***************************************************************** // Expected data pattern when DQ shifted to the right such that // DQS before the left edge of the DVW: // Based on pattern of ({rise,fall}) = // 0x1, 0xB, 0x4, 0x4, 0xB, 0x9 // Each nibble will look like: // bit3: 0, 1, 0, 0, 1, 1 // bit2: 0, 0, 1, 1, 0, 0 // bit1: 0, 1, 0, 0, 1, 0 // bit0: 1, 1, 0, 0, 1, 1 // Or if the write is early it could look like: // 0x4, 0x4, 0xB, 0x9, 0x6, 0xE // bit3: 0, 0, 1, 1, 0, 1 // bit2: 1, 1, 0, 0, 1, 1 // bit1: 0, 0, 1, 0, 1, 1 // bit0: 0, 0, 1, 1, 0, 0 // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN // and the actual training pattern contents change //***************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_pat_div4 // Pattern for DQ IDELAY increment // Target pattern for "early write" assign {idel_pat0_rise0[3], idel_pat0_rise0[2], idel_pat0_rise0[1], idel_pat0_rise0[0]} = 4'h1; assign {idel_pat0_fall0[3], idel_pat0_fall0[2], idel_pat0_fall0[1], idel_pat0_fall0[0]} = 4'h7; assign {idel_pat0_rise1[3], idel_pat0_rise1[2], idel_pat0_rise1[1], idel_pat0_rise1[0]} = 4'hE; assign {idel_pat0_fall1[3], idel_pat0_fall1[2], idel_pat0_fall1[1], idel_pat0_fall1[0]} = 4'hC; assign {idel_pat0_rise2[3], idel_pat0_rise2[2], idel_pat0_rise2[1], idel_pat0_rise2[0]} = 4'h9; assign {idel_pat0_fall2[3], idel_pat0_fall2[2], idel_pat0_fall2[1], idel_pat0_fall2[0]} = 4'h2; assign {idel_pat0_rise3[3], idel_pat0_rise3[2], idel_pat0_rise3[1], idel_pat0_rise3[0]} = 4'h4; assign {idel_pat0_fall3[3], idel_pat0_fall3[2], idel_pat0_fall3[1], idel_pat0_fall3[0]} = 4'hB; // Target pattern for "on-time write" assign {idel_pat1_rise0[3], idel_pat1_rise0[2], idel_pat1_rise0[1], idel_pat1_rise0[0]} = 4'h4; assign {idel_pat1_fall0[3], idel_pat1_fall0[2], idel_pat1_fall0[1], idel_pat1_fall0[0]} = 4'h9; assign {idel_pat1_rise1[3], idel_pat1_rise1[2], idel_pat1_rise1[1], idel_pat1_rise1[0]} = 4'h3; assign {idel_pat1_fall1[3], idel_pat1_fall1[2], idel_pat1_fall1[1], idel_pat1_fall1[0]} = 4'h7; assign {idel_pat1_rise2[3], idel_pat1_rise2[2], idel_pat1_rise2[1], idel_pat1_rise2[0]} = 4'hE; assign {idel_pat1_fall2[3], idel_pat1_fall2[2], idel_pat1_fall2[1], idel_pat1_fall2[0]} = 4'hC; assign {idel_pat1_rise3[3], idel_pat1_rise3[2], idel_pat1_rise3[1], idel_pat1_rise3[0]} = 4'h9; assign {idel_pat1_fall3[3], idel_pat1_fall3[2], idel_pat1_fall3[1], idel_pat1_fall3[0]} = 4'h2; // Correct data valid window for "early write" assign {pat0_rise0[3], pat0_rise0[2], pat0_rise0[1], pat0_rise0[0]} = 4'h7; assign {pat0_fall0[3], pat0_fall0[2], pat0_fall0[1], pat0_fall0[0]} = 4'hE; assign {pat0_rise1[3], pat0_rise1[2], pat0_rise1[1], pat0_rise1[0]} = 4'hC; assign {pat0_fall1[3], pat0_fall1[2], pat0_fall1[1], pat0_fall1[0]} = 4'h9; assign {pat0_rise2[3], pat0_rise2[2], pat0_rise2[1], pat0_rise2[0]} = 4'h2; assign {pat0_fall2[3], pat0_fall2[2], pat0_fall2[1], pat0_fall2[0]} = 4'h4; assign {pat0_rise3[3], pat0_rise3[2], pat0_rise3[1], pat0_rise3[0]} = 4'hB; assign {pat0_fall3[3], pat0_fall3[2], pat0_fall3[1], pat0_fall3[0]} = 4'h1; // Correct data valid window for "on-time write" assign {pat1_rise0[3], pat1_rise0[2], pat1_rise0[1], pat1_rise0[0]} = 4'h9; assign {pat1_fall0[3], pat1_fall0[2], pat1_fall0[1], pat1_fall0[0]} = 4'h3; assign {pat1_rise1[3], pat1_rise1[2], pat1_rise1[1], pat1_rise1[0]} = 4'h7; assign {pat1_fall1[3], pat1_fall1[2], pat1_fall1[1], pat1_fall1[0]} = 4'hE; assign {pat1_rise2[3], pat1_rise2[2], pat1_rise2[1], pat1_rise2[0]} = 4'hC; assign {pat1_fall2[3], pat1_fall2[2], pat1_fall2[1], pat1_fall2[0]} = 4'h9; assign {pat1_rise3[3], pat1_rise3[2], pat1_rise3[1], pat1_rise3[0]} = 4'h2; assign {pat1_fall3[3], pat1_fall3[2], pat1_fall3[1], pat1_fall3[0]} = 4'h4; end else if (nCK_PER_CLK == 2) begin: gen_pat_div2 // Pattern for DQ IDELAY increment // Target pattern for "early write" assign idel_pat0_rise0[3] = 2'b01; assign idel_pat0_fall0[3] = 2'b00; assign idel_pat0_rise1[3] = 2'b10; assign idel_pat0_fall1[3] = 2'b11; assign idel_pat0_rise0[2] = 2'b00; assign idel_pat0_fall0[2] = 2'b10; assign idel_pat0_rise1[2] = 2'b11; assign idel_pat0_fall1[2] = 2'b10; assign idel_pat0_rise0[1] = 2'b00; assign idel_pat0_fall0[1] = 2'b11; assign idel_pat0_rise1[1] = 2'b10; assign idel_pat0_fall1[1] = 2'b01; assign idel_pat0_rise0[0] = 2'b11; assign idel_pat0_fall0[0] = 2'b10; assign idel_pat0_rise1[0] = 2'b00; assign idel_pat0_fall1[0] = 2'b01; // Target pattern for "on-time write" assign idel_pat1_rise0[3] = 2'b01; assign idel_pat1_fall0[3] = 2'b11; assign idel_pat1_rise1[3] = 2'b01; assign idel_pat1_fall1[3] = 2'b00; assign idel_pat1_rise0[2] = 2'b11; assign idel_pat1_fall0[2] = 2'b01; assign idel_pat1_rise1[2] = 2'b00; assign idel_pat1_fall1[2] = 2'b10; assign idel_pat1_rise0[1] = 2'b01; assign idel_pat1_fall0[1] = 2'b00; assign idel_pat1_rise1[1] = 2'b10; assign idel_pat1_fall1[1] = 2'b11; assign idel_pat1_rise0[0] = 2'b00; assign idel_pat1_fall0[0] = 2'b10; assign idel_pat1_rise1[0] = 2'b11; assign idel_pat1_fall1[0] = 2'b10; // Correct data valid window for "early write" assign pat0_rise0[3] = 2'b00; assign pat0_fall0[3] = 2'b10; assign pat0_rise1[3] = 2'b11; assign pat0_fall1[3] = 2'b10; assign pat0_rise0[2] = 2'b10; assign pat0_fall0[2] = 2'b11; assign pat0_rise1[2] = 2'b10; assign pat0_fall1[2] = 2'b00; assign pat0_rise0[1] = 2'b11; assign pat0_fall0[1] = 2'b10; assign pat0_rise1[1] = 2'b01; assign pat0_fall1[1] = 2'b00; assign pat0_rise0[0] = 2'b10; assign pat0_fall0[0] = 2'b00; assign pat0_rise1[0] = 2'b01; assign pat0_fall1[0] = 2'b11; // Correct data valid window for "on-time write" assign pat1_rise0[3] = 2'b11; assign pat1_fall0[3] = 2'b01; assign pat1_rise1[3] = 2'b00; assign pat1_fall1[3] = 2'b10; assign pat1_rise0[2] = 2'b01; assign pat1_fall0[2] = 2'b00; assign pat1_rise1[2] = 2'b10; assign pat1_fall1[2] = 2'b11; assign pat1_rise0[1] = 2'b00; assign pat1_fall0[1] = 2'b10; assign pat1_rise1[1] = 2'b11; assign pat1_fall1[1] = 2'b10; assign pat1_rise0[0] = 2'b10; assign pat1_fall0[0] = 2'b11; assign pat1_rise1[0] = 2'b10; assign pat1_fall1[0] = 2'b00; end endgenerate // Each bit of each byte is compared to expected pattern. // This was done to prevent (and "drastically decrease") the chance that // invalid data clocked in when the DQ bus is tri-state (along with a // combination of the correct data) will resemble the expected data // pattern. A better fix for this is to change the training pattern and/or // make the pattern longer. generate genvar pt_i; if (nCK_PER_CLK == 4) begin: gen_pat_match_div4 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match // DQ IDELAY pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4]) idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4]) idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4]) idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4]) idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == idel_pat0_rise2[pt_i%4]) idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == idel_pat0_fall2[pt_i%4]) idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == idel_pat0_rise3[pt_i%4]) idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == idel_pat0_fall3[pt_i%4]) idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4]) idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4]) idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4]) idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4]) idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == idel_pat1_rise2[pt_i%4]) idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == idel_pat1_fall2[pt_i%4]) idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == idel_pat1_rise3[pt_i%4]) idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == idel_pat1_fall3[pt_i%4]) idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b0; end // DQS DVW pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4]) pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4]) pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat0_rise2[pt_i%4]) pat0_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat0_fall2[pt_i%4]) pat0_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat0_rise3[pt_i%4]) pat0_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat0_fall3[pt_i%4]) pat0_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat1_rise2[pt_i%4]) pat1_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat1_fall2[pt_i%4]) pat1_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat1_rise3[pt_i%4]) pat1_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat1_fall3[pt_i%4]) pat1_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall3_r[pt_i] <= #TCQ 1'b0; end end // Combine pattern match "subterms" for DQ-IDELAY stage always @(posedge clk) begin idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r; idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r; idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r; idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r; idel_pat0_match_rise2_and_r <= #TCQ &idel_pat0_match_rise2_r; idel_pat0_match_fall2_and_r <= #TCQ &idel_pat0_match_fall2_r; idel_pat0_match_rise3_and_r <= #TCQ &idel_pat0_match_rise3_r; idel_pat0_match_fall3_and_r <= #TCQ &idel_pat0_match_fall3_r; idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r && idel_pat0_match_fall0_and_r && idel_pat0_match_rise1_and_r && idel_pat0_match_fall1_and_r && idel_pat0_match_rise2_and_r && idel_pat0_match_fall2_and_r && idel_pat0_match_rise3_and_r && idel_pat0_match_fall3_and_r); end always @(posedge clk) begin idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r; idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r; idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r; idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r; idel_pat1_match_rise2_and_r <= #TCQ &idel_pat1_match_rise2_r; idel_pat1_match_fall2_and_r <= #TCQ &idel_pat1_match_fall2_r; idel_pat1_match_rise3_and_r <= #TCQ &idel_pat1_match_rise3_r; idel_pat1_match_fall3_and_r <= #TCQ &idel_pat1_match_fall3_r; idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r && idel_pat1_match_fall0_and_r && idel_pat1_match_rise1_and_r && idel_pat1_match_fall1_and_r && idel_pat1_match_rise2_and_r && idel_pat1_match_fall2_and_r && idel_pat1_match_rise3_and_r && idel_pat1_match_fall3_and_r); end always @(*) idel_pat_data_match <= #TCQ idel_pat0_data_match_r | idel_pat1_data_match_r; always @(posedge clk) idel_pat_data_match_r <= #TCQ idel_pat_data_match; // Combine pattern match "subterms" for DQS-PHASER_IN stage always @(posedge clk) begin pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r; pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r; pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r; pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r; pat0_match_rise2_and_r <= #TCQ &pat0_match_rise2_r; pat0_match_fall2_and_r <= #TCQ &pat0_match_fall2_r; pat0_match_rise3_and_r <= #TCQ &pat0_match_rise3_r; pat0_match_fall3_and_r <= #TCQ &pat0_match_fall3_r; pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r && pat0_match_fall0_and_r && pat0_match_rise1_and_r && pat0_match_fall1_and_r && pat0_match_rise2_and_r && pat0_match_fall2_and_r && pat0_match_rise3_and_r && pat0_match_fall3_and_r); end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_match_rise2_and_r <= #TCQ &pat1_match_rise2_r; pat1_match_fall2_and_r <= #TCQ &pat1_match_fall2_r; pat1_match_rise3_and_r <= #TCQ &pat1_match_rise3_r; pat1_match_fall3_and_r <= #TCQ &pat1_match_fall3_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r && pat1_match_rise2_and_r && pat1_match_fall2_and_r && pat1_match_rise3_and_r && pat1_match_fall3_and_r); end assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r; end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match // DQ IDELAY pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4]) idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4]) idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4]) idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4]) idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4]) idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4]) idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4]) idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4]) idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end // DQS DVW pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4]) pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4]) pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end end // Combine pattern match "subterms" for DQ-IDELAY stage always @(posedge clk) begin idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r; idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r; idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r; idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r; idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r && idel_pat0_match_fall0_and_r && idel_pat0_match_rise1_and_r && idel_pat0_match_fall1_and_r); end always @(posedge clk) begin idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r; idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r; idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r; idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r; idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r && idel_pat1_match_fall0_and_r && idel_pat1_match_rise1_and_r && idel_pat1_match_fall1_and_r); end always @(posedge clk) begin if (sr_valid_r2) idel_pat_data_match <= #TCQ idel_pat0_data_match_r | idel_pat1_data_match_r; end //assign idel_pat_data_match = idel_pat0_data_match_r | // idel_pat1_data_match_r; always @(posedge clk) idel_pat_data_match_r <= #TCQ idel_pat_data_match; // Combine pattern match "subterms" for DQS-PHASER_IN stage always @(posedge clk) begin pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r; pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r; pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r; pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r; pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r && pat0_match_fall0_and_r && pat0_match_rise1_and_r && pat0_match_fall1_and_r); end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r); end assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r; end endgenerate always @(posedge clk) begin rdlvl_stg1_start_r <= #TCQ rdlvl_stg1_start; mpr_rdlvl_done_r1 <= #TCQ mpr_rdlvl_done_r; mpr_rdlvl_done_r2 <= #TCQ mpr_rdlvl_done_r1; mpr_rdlvl_start_r <= #TCQ mpr_rdlvl_start; end //*************************************************************************** // First stage calibration: Capture clock //*************************************************************************** //***************************************************************** // Keep track of how many samples have been written to shift registers // Every time RD_SHIFT_LEN samples have been written, then we have a // full read training pattern loaded into the sr_* registers. Then assert // sr_valid_r to indicate that: (1) comparison between the sr_* and // old_sr_* and prev_sr_* registers can take place, (2) transfer of // the contents of sr_* to old_sr_* and prev_sr_* registers can also // take place //***************************************************************** // verilint STARC-2.2.3.3 off always @(posedge clk) if (rst || (mpr_rdlvl_done_r && ~rdlvl_stg1_start)) begin cnt_shift_r <= #TCQ 'b1; sr_valid_r <= #TCQ 1'b0; mpr_valid_r <= #TCQ 1'b0; end else begin if (mux_rd_valid_r && mpr_rdlvl_start && ~mpr_rdlvl_done_r) begin if (cnt_shift_r == 'b0) mpr_valid_r <= #TCQ 1'b1; else begin mpr_valid_r <= #TCQ 1'b0; cnt_shift_r <= #TCQ cnt_shift_r + 1; end end else mpr_valid_r <= #TCQ 1'b0; if (mux_rd_valid_r && rdlvl_stg1_start) begin if (cnt_shift_r == RD_SHIFT_LEN-1) begin sr_valid_r <= #TCQ 1'b1; cnt_shift_r <= #TCQ 'b0; end else begin sr_valid_r <= #TCQ 1'b0; cnt_shift_r <= #TCQ cnt_shift_r + 1; end end else // When the current mux_rd_* contents are not valid, then // retain the current value of cnt_shift_r, and make sure // that sr_valid_r = 0 to prevent any downstream loads or // comparisons sr_valid_r <= #TCQ 1'b0; end // verilint STARC-2.2.3.3 on //***************************************************************** // Logic to determine when either edge of the data eye encountered // Pre- and post-IDELAY update data pattern is compared, if they // differ, than an edge has been encountered. Currently no attempt // made to determine if the data pattern itself is "correct", only // whether it changes after incrementing the IDELAY (possible // future enhancement) //***************************************************************** // One-way control for ensuring that state machine request to store // current read data into OLD SR shift register only occurs on a // valid clock cycle. The FSM provides a one-cycle request pulse. // It is the responsibility of the FSM to wait the worst-case time // before relying on any downstream results of this load. always @(posedge clk) if (rst) store_sr_r <= #TCQ 1'b0; else begin if (store_sr_req_r) store_sr_r <= #TCQ 1'b1; else if ((sr_valid_r || mpr_valid_r) && store_sr_r) store_sr_r <= #TCQ 1'b0; end // Transfer current data to old data, prior to incrementing delay // Also store data from current sampling window - so that we can detect // if the current delay tap yields data that is "jittery" generate if (nCK_PER_CLK == 4) begin: gen_old_sr_div4 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr always @(posedge clk) begin if (sr_valid_r || mpr_valid_r) begin // Load last sample (i.e. from current sampling interval) prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; prev_sr_rise2_r[z] <= #TCQ sr_rise2_r[z]; prev_sr_fall2_r[z] <= #TCQ sr_fall2_r[z]; prev_sr_rise3_r[z] <= #TCQ sr_rise3_r[z]; prev_sr_fall3_r[z] <= #TCQ sr_fall3_r[z]; end if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; old_sr_rise2_r[z] <= #TCQ sr_rise2_r[z]; old_sr_fall2_r[z] <= #TCQ sr_fall2_r[z]; old_sr_rise3_r[z] <= #TCQ sr_rise3_r[z]; old_sr_fall3_r[z] <= #TCQ sr_fall3_r[z]; end end end end else if (nCK_PER_CLK == 2) begin: gen_old_sr_div2 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr always @(posedge clk) begin if (sr_valid_r || mpr_valid_r) begin prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; end if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; end end end end endgenerate //******************************************************* // Match determination occurs over 3 cycles - pipelined for better timing //******************************************************* // Match valid with # of cycles of pipelining in match determination always @(posedge clk) begin sr_valid_r1 <= #TCQ sr_valid_r; sr_valid_r2 <= #TCQ sr_valid_r1; mpr_valid_r1 <= #TCQ mpr_valid_r; mpr_valid_r2 <= #TCQ mpr_valid_r1; end generate if (nCK_PER_CLK == 4) begin: gen_sr_match_div4 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match always @(posedge clk) begin // CYCLE1: Compare all bits in DQS grp, generate separate term for // each bit over four bit times. For example, if there are 8-bits // per DQS group, 32 terms are generated on cycle 1 // NOTE: Structure HDL such that X on data bus will result in a // mismatch. This is required for memory models that can drive the // bus with X's to model uncertainty regions (e.g. Denali) if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z])) old_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z]; else old_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z])) old_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z]; else old_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z])) old_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z]; else old_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z])) old_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z]; else old_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == old_sr_rise2_r[z])) old_sr_match_rise2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise2_r[z] <= #TCQ old_sr_match_rise2_r[z]; else old_sr_match_rise2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == old_sr_fall2_r[z])) old_sr_match_fall2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall2_r[z] <= #TCQ old_sr_match_fall2_r[z]; else old_sr_match_fall2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == old_sr_rise3_r[z])) old_sr_match_rise3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise3_r[z] <= #TCQ old_sr_match_rise3_r[z]; else old_sr_match_rise3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == old_sr_fall3_r[z])) old_sr_match_fall3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall3_r[z] <= #TCQ old_sr_match_fall3_r[z]; else old_sr_match_fall3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z])) prev_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z]; else prev_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z])) prev_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z]; else prev_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z])) prev_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z]; else prev_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z])) prev_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z]; else prev_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == prev_sr_rise2_r[z])) prev_sr_match_rise2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise2_r[z] <= #TCQ prev_sr_match_rise2_r[z]; else prev_sr_match_rise2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == prev_sr_fall2_r[z])) prev_sr_match_fall2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall2_r[z] <= #TCQ prev_sr_match_fall2_r[z]; else prev_sr_match_fall2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == prev_sr_rise3_r[z])) prev_sr_match_rise3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise3_r[z] <= #TCQ prev_sr_match_rise3_r[z]; else prev_sr_match_rise3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == prev_sr_fall3_r[z])) prev_sr_match_fall3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall3_r[z] <= #TCQ prev_sr_match_fall3_r[z]; else prev_sr_match_fall3_r[z] <= #TCQ 1'b0; // CYCLE2: Combine all the comparisons for every 8 words (rise0, // fall0,rise1, fall1) in the calibration sequence. Now we're down // to DRAM_WIDTH terms old_sr_match_cyc2_r[z] <= #TCQ old_sr_match_rise0_r[z] & old_sr_match_fall0_r[z] & old_sr_match_rise1_r[z] & old_sr_match_fall1_r[z] & old_sr_match_rise2_r[z] & old_sr_match_fall2_r[z] & old_sr_match_rise3_r[z] & old_sr_match_fall3_r[z]; prev_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_rise0_r[z] & prev_sr_match_fall0_r[z] & prev_sr_match_rise1_r[z] & prev_sr_match_fall1_r[z] & prev_sr_match_rise2_r[z] & prev_sr_match_fall2_r[z] & prev_sr_match_rise3_r[z] & prev_sr_match_fall3_r[z]; // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen), // and qualify with pipelined valid signal) - probably don't need // a cycle just do do this.... if (sr_valid_r2 || mpr_valid_r2) begin old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z]; prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z]; end else begin old_sr_diff_r[z] <= #TCQ 'b0; prev_sr_diff_r[z] <= #TCQ 'b0; end end end end if (nCK_PER_CLK == 2) begin: gen_sr_match_div2 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match always @(posedge clk) begin if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z])) old_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z]; else old_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z])) old_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z]; else old_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z])) old_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z]; else old_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z])) old_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z]; else old_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z])) prev_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z]; else prev_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z])) prev_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z]; else prev_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z])) prev_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z]; else prev_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z])) prev_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z]; else prev_sr_match_fall1_r[z] <= #TCQ 1'b0; old_sr_match_cyc2_r[z] <= #TCQ old_sr_match_rise0_r[z] & old_sr_match_fall0_r[z] & old_sr_match_rise1_r[z] & old_sr_match_fall1_r[z]; prev_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_rise0_r[z] & prev_sr_match_fall0_r[z] & prev_sr_match_rise1_r[z] & prev_sr_match_fall1_r[z]; // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen), // and qualify with pipelined valid signal) - probably don't need // a cycle just do do this.... if (sr_valid_r2 || mpr_valid_r2) begin old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z]; prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z]; end else begin old_sr_diff_r[z] <= #TCQ 'b0; prev_sr_diff_r[z] <= #TCQ 'b0; end end end end endgenerate //*************************************************************************** // First stage calibration: DQS Capture //*************************************************************************** //******************************************************* // Counters for tracking # of samples compared // For each comparision point (i.e. to determine if an edge has // occurred after each IODELAY increment when read leveling), // multiple samples are compared in order to average out the effects // of jitter. If any one of these samples is different than the "old" // sample corresponding to the previous IODELAY value, then an edge // is declared to be detected. //******************************************************* // Two cascaded counters are used to keep track of # of samples compared, // in order to make it easier to meeting timing on these paths. Once // optimal sampling interval is determined, it may be possible to remove // the second counter always @(posedge clk) samp_edge_cnt0_en_r <= #TCQ (cal1_state_r == CAL1_PAT_DETECT) || (cal1_state_r == CAL1_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ); // First counter counts # of samples compared always @(posedge clk) if (rst) samp_edge_cnt0_r <= #TCQ 'b0; else begin if (!samp_edge_cnt0_en_r) // Reset sample counter when not in any of the "sampling" states samp_edge_cnt0_r <= #TCQ 'b0; else if (sr_valid_r2 || mpr_valid_r2) // Otherwise, count # of samples compared samp_edge_cnt0_r <= #TCQ samp_edge_cnt0_r + 1; end // Counter #2 enable generation always @(posedge clk) if (rst) samp_edge_cnt1_en_r <= #TCQ 1'b0; else begin // Assert pulse when correct number of samples compared if ((samp_edge_cnt0_r == DETECT_EDGE_SAMPLE_CNT0) && (sr_valid_r2 || mpr_valid_r2)) samp_edge_cnt1_en_r <= #TCQ 1'b1; else samp_edge_cnt1_en_r <= #TCQ 1'b0; end // Counter #2 always @(posedge clk) if (rst) samp_edge_cnt1_r <= #TCQ 'b0; else if (!samp_edge_cnt0_en_r) samp_edge_cnt1_r <= #TCQ 'b0; else if (samp_edge_cnt1_en_r) samp_edge_cnt1_r <= #TCQ samp_edge_cnt1_r + 1; always @(posedge clk) if (rst) samp_cnt_done_r <= #TCQ 1'b0; else begin if (!samp_edge_cnt0_en_r) samp_cnt_done_r <= #TCQ 'b0; else if ((SIM_CAL_OPTION == "FAST_CAL") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin if (samp_edge_cnt0_r == SR_VALID_DELAY-1) // For simulation only, stay in edge detection mode a minimum // amount of time - just enough for two data compares to finish samp_cnt_done_r <= #TCQ 1'b1; end else begin if (samp_edge_cnt1_r == DETECT_EDGE_SAMPLE_CNT1) samp_cnt_done_r <= #TCQ 1'b1; end end //***************************************************************** // Logic to keep track of (on per-bit basis): // 1. When a region of stability preceded by a known edge occurs // 2. If for the current tap, the read data jitters // 3. If an edge occured between the current and previous tap // 4. When the current edge detection/sampling interval can end // Essentially, these are a series of status bits - the stage 1 // calibration FSM monitors these to determine when an edge is // found. Additional information is provided to help the FSM // determine if a left or right edge has been found. //**************************************************************** assign pb_detect_edge_setup = (cal1_state_r == CAL1_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT); assign pb_detect_edge = (cal1_state_r == CAL1_PAT_DETECT) || (cal1_state_r == CAL1_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ); generate for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_track_left_edge always @(posedge clk) begin if (pb_detect_edge_setup) begin // Reset eye size, stable eye marker, and jitter marker before // starting new edge detection iteration pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_detect_edge_done_r[z] <= #TCQ 1'b0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_last_tap_jitter_r[z] <= #TCQ 1'b0; pb_found_edge_last_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b0; pb_found_first_edge_r[z] <= #TCQ 1'b0; end else if (pb_detect_edge) begin // Save information on which DQ bits are already out of the // data valid window - those DQ bits will later not have their // IDELAY tap value incremented pb_found_edge_last_r[z] <= #TCQ pb_found_edge_r[z]; if (!pb_detect_edge_done_r[z]) begin if (samp_cnt_done_r) begin // If we've reached end of sampling interval, no jitter on // current tap has been found (although an edge could have // been found between the current and previous taps), and // the sampling interval is complete. Increment the stable // eye counter if no edge found, and always clear the jitter // flag in preparation for the next tap. pb_last_tap_jitter_r[z] <= #TCQ 1'b0; pb_detect_edge_done_r[z] <= #TCQ 1'b1; if (!pb_found_edge_r[z] && !pb_last_tap_jitter_r[z]) begin // If the data was completely stable during this tap and // no edge was found between this and the previous tap // then increment the stable eye counter "as appropriate" if (pb_cnt_eye_size_r[z] != MIN_EYE_SIZE-1) pb_cnt_eye_size_r[z] <= #TCQ pb_cnt_eye_size_r[z] + 1; else //if (pb_found_first_edge_r[z]) // We've reached minimum stable eye width pb_found_stable_eye_r[z] <= #TCQ 1'b1; end else begin // Otherwise, an edge was found, either because of a // difference between this and the previous tap's read // data, and/or because the previous tap's data jittered // (but not the current tap's data), then just set the // edge found flag, and enable the stable eye counter pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b1; pb_detect_edge_done_r[z] <= #TCQ 1'b1; end end else if (prev_sr_diff_r[z]) begin // If we find that the current tap read data jitters, then // set edge and jitter found flags, "enable" the eye size // counter, and stop sampling interval for this bit pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_last_tap_jitter_r[z] <= #TCQ 1'b1; pb_found_edge_r[z] <= #TCQ 1'b1; pb_found_first_edge_r[z] <= #TCQ 1'b1; pb_detect_edge_done_r[z] <= #TCQ 1'b1; end else if (old_sr_diff_r[z] || pb_last_tap_jitter_r[z]) begin // If either an edge was found (i.e. difference between // current tap and previous tap read data), or the previous // tap exhibited jitter (which means by definition that the // current tap cannot match the previous tap because the // previous tap gave unstable data), then set the edge found // flag, and "enable" eye size counter. But do not stop // sampling interval - we still need to check if the current // tap exhibits jitter pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b1; pb_found_first_edge_r[z] <= #TCQ 1'b1; end end end else begin // Before every edge detection interval, reset "intra-tap" flags pb_found_edge_r[z] <= #TCQ 1'b0; pb_detect_edge_done_r[z] <= #TCQ 1'b0; end end end endgenerate // Combine the above per-bit status flags into combined terms when // performing deskew on the aggregate data window always @(posedge clk) begin detect_edge_done_r <= #TCQ &pb_detect_edge_done_r; found_edge_r <= #TCQ |pb_found_edge_r; found_edge_all_r <= #TCQ &pb_found_edge_r; found_stable_eye_r <= #TCQ &pb_found_stable_eye_r; end // last IODELAY "stable eye" indicator is updated only after // detect_edge_done_r is asserted - so that when we do find the "right edge" // of the data valid window, found_edge_r = 1, AND found_stable_eye_r = 1 // when detect_edge_done_r = 1 (otherwise, if found_stable_eye_r updates // immediately, then it never possible to have found_stable_eye_r = 1 // when we detect an edge - and we'll never know whether we've found // a "right edge") always @(posedge clk) if (pb_detect_edge_setup) found_stable_eye_last_r <= #TCQ 1'b0; else if (detect_edge_done_r) found_stable_eye_last_r <= #TCQ found_stable_eye_r; //***************************************************************** // Keep track of DQ IDELAYE2 taps used //***************************************************************** // Added additional register stage to improve timing always @(posedge clk) if (rst) idelay_tap_cnt_slice_r <= 5'h0; else idelay_tap_cnt_slice_r <= idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]; always @(posedge clk) if (rst || (SIM_CAL_OPTION == "SKIP_CAL")) begin //|| new_cnt_cpt_r for (s = 0; s < RANKS; s = s + 1) begin for (t = 0; t < DQS_WIDTH; t = t + 1) begin idelay_tap_cnt_r[s][t] <= #TCQ idelaye2_init_val; end end end else if (SIM_CAL_OPTION == "FAST_CAL") begin for (u = 0; u < RANKS; u = u + 1) begin for (w = 0; w < DQS_WIDTH; w = w + 1) begin if (cal1_dq_idel_ce) begin if (cal1_dq_idel_inc) idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] + 1; else idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] - 1; end end end end else if ((rnk_cnt_r == RANKS-1) && (RANKS == 2) && rdlvl_rank_done_r && (cal1_state_r == CAL1_IDLE)) begin for (f = 0; f < DQS_WIDTH; f = f + 1) begin idelay_tap_cnt_r[rnk_cnt_r][f] <= #TCQ idelay_tap_cnt_r[(rnk_cnt_r-1)][f]; end end else if (cal1_dq_idel_ce) begin if (cal1_dq_idel_inc) idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r + 5'h1; else idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r - 5'h1; end else if (idelay_ld) idelay_tap_cnt_r[0][wrcal_cnt] <= #TCQ 5'b00000; always @(posedge clk) if (rst || new_cnt_cpt_r) idelay_tap_limit_r <= #TCQ 1'b0; else if (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_r] == 'd31) idelay_tap_limit_r <= #TCQ 1'b1; //***************************************************************** // keep track of edge tap counts found, and current capture clock // tap count //***************************************************************** always @(posedge clk) if (rst || new_cnt_cpt_r || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) tap_cnt_cpt_r <= #TCQ 'b0; else if (cal1_dlyce_cpt_r) begin if (cal1_dlyinc_cpt_r) tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r + 1; else if (tap_cnt_cpt_r != 'd0) tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r - 1; end always @(posedge clk) if (rst || new_cnt_cpt_r || (cal1_state_r1 == CAL1_DQ_IDEL_TAP_INC) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) tap_limit_cpt_r <= #TCQ 1'b0; else if (tap_cnt_cpt_r == 6'd63) tap_limit_cpt_r <= #TCQ 1'b1; always @(posedge clk) cal1_cnt_cpt_timing_r <= #TCQ cal1_cnt_cpt_r; assign cal1_cnt_cpt_timing = {2'b00, cal1_cnt_cpt_r}; // Storing DQS tap values at the end of each DQS read leveling always @(posedge clk) begin if (rst) begin for (a = 0; a < RANKS; a = a + 1) begin: rst_rdlvl_dqs_tap_count_loop for (b = 0; b < DQS_WIDTH; b = b + 1) rdlvl_dqs_tap_cnt_r[a][b] <= #TCQ 'b0; end end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_NEXT_DQS)) begin for (p = 0; p < RANKS; p = p +1) begin: rdlvl_dqs_tap_rank_cnt for(q = 0; q < DQS_WIDTH; q = q +1) begin: rdlvl_dqs_tap_cnt rdlvl_dqs_tap_cnt_r[p][q] <= #TCQ tap_cnt_cpt_r; end end end else if (SIM_CAL_OPTION == "SKIP_CAL") begin for (j = 0; j < RANKS; j = j +1) begin: rdlvl_dqs_tap_rnk_cnt for(i = 0; i < DQS_WIDTH; i = i +1) begin: rdlvl_dqs_cnt rdlvl_dqs_tap_cnt_r[j][i] <= #TCQ 6'd31; end end end else if (cal1_state_r1 == CAL1_NEXT_DQS) begin rdlvl_dqs_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing_r] <= #TCQ tap_cnt_cpt_r; end end // Counter to track maximum DQ IODELAY tap usage during the per-bit // deskew portion of stage 1 calibration always @(posedge clk) if (rst) begin idel_tap_cnt_dq_pb_r <= #TCQ 'b0; idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end else if (new_cnt_cpt_r) begin idel_tap_cnt_dq_pb_r <= #TCQ 'b0; idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end else if (|cal1_dlyce_dq_r) begin if (cal1_dlyinc_dq_r) idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r + 1; else idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r - 1; if (idel_tap_cnt_dq_pb_r == 31) idel_tap_limit_dq_pb_r <= #TCQ 1'b1; else idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end //***************************************************************** always @(posedge clk) cal1_state_r1 <= #TCQ cal1_state_r; always @(posedge clk) if (rst) begin cal1_cnt_cpt_r <= #TCQ 'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_IDLE; cnt_idel_dec_cpt_r <= #TCQ 6'bxxxxxx; found_first_edge_r <= #TCQ 1'b0; found_second_edge_r <= #TCQ 1'b0; right_edge_taps_r <= #TCQ 6'bxxxxxx; first_edge_taps_r <= #TCQ 6'bxxxxxx; new_cnt_cpt_r <= #TCQ 1'b0; rdlvl_stg1_done <= #TCQ 1'b0; rdlvl_stg1_err <= #TCQ 1'b0; second_edge_taps_r <= #TCQ 6'bxxxxxx; store_sr_req_pulsed_r <= #TCQ 1'b0; store_sr_req_r <= #TCQ 1'b0; rnk_cnt_r <= #TCQ 2'b00; rdlvl_rank_done_r <= #TCQ 1'b0; idel_dec_cnt <= #TCQ 'd0; rdlvl_last_byte_done <= #TCQ 1'b0; idel_pat_detect_valid_r <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; idel_adj_inc <= #TCQ 1'b0; if (OCAL_EN == "ON") mpr_rdlvl_done_r <= #TCQ 1'b0; else mpr_rdlvl_done_r <= #TCQ 1'b1; mpr_dec_cpt_r <= #TCQ 1'b0; end else begin // default (inactive) states for all "pulse" outputs // verilint STARC-2.2.3.3 off cal1_prech_req_r <= #TCQ 1'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; new_cnt_cpt_r <= #TCQ 1'b0; store_sr_req_pulsed_r <= #TCQ 1'b0; store_sr_req_r <= #TCQ 1'b0; case (cal1_state_r) CAL1_IDLE: begin rdlvl_rank_done_r <= #TCQ 1'b0; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; if (mpr_rdlvl_start && ~mpr_rdlvl_start_r) begin cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT; end else if (rdlvl_stg1_start && ~rdlvl_stg1_start_r) begin if (SIM_CAL_OPTION == "SKIP_CAL") cal1_state_r <= #TCQ CAL1_REGL_LOAD; else if (SIM_CAL_OPTION == "FAST_CAL") cal1_state_r <= #TCQ CAL1_NEXT_DQS; else begin new_cnt_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT; end end end CAL1_MPR_NEW_DQS_WAIT: begin cal1_prech_req_r <= #TCQ 1'b0; if (!cal1_wait_r && mpr_valid_r) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; end // Wait for the new DQS group to change // also gives time for the read data IN_FIFO to // output the updated data for the new DQS group CAL1_NEW_DQS_WAIT: begin rdlvl_rank_done_r <= #TCQ 1'b0; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; if (|pi_counter_read_val) begin //VK_REVIEW mpr_dec_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; cnt_idel_dec_cpt_r <= #TCQ pi_counter_read_val; end else if (!cal1_wait_r) begin //if (!cal1_wait_r) begin // Store "previous tap" read data. Technically there is no // "previous" read data, since we are starting a new DQS // group, so we'll never find an edge at tap 0 unless the // data is fluctuating/jittering store_sr_req_r <= #TCQ 1'b1; // If per-bit deskew is disabled, then skip the first // portion of stage 1 calibration if (PER_BIT_DESKEW == "OFF") cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; else if (PER_BIT_DESKEW == "ON") cal1_state_r <= #TCQ CAL1_PB_STORE_FIRST_WAIT; end end //***************************************************************** // Per-bit deskew states //***************************************************************** // Wait state following storage of initial read data CAL1_PB_STORE_FIRST_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE; // Look for an edge on all DQ bits in current DQS group CAL1_PB_DETECT_EDGE: if (detect_edge_done_r) begin if (found_stable_eye_r) begin // If we've found the left edge for all bits (or more precisely, // we've found the left edge, and then part of the stable // window thereafter), then proceed to positioning the CPT clock // right before the left margin cnt_idel_dec_cpt_r <= #TCQ MIN_EYE_SIZE + 1; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT; end else begin // If we've reached the end of the sampling time, and haven't // yet found the left margin of all the DQ bits, then: if (!tap_limit_cpt_r) begin // If we still have taps left to use, then store current value // of read data, increment the capture clock, and continue to // look for (left) edges store_sr_req_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_CPT; end else begin // If we ran out of taps moving the capture clock, and we // haven't finished edge detection, then reset the capture // clock taps to 0 (gradually, one tap at a time... // then exit the per-bit portion of the algorithm - // i.e. proceed to adjust the capture clock and DQ IODELAYs as cnt_idel_dec_cpt_r <= #TCQ 6'd63; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end end end // Increment delay for DQS CAL1_PB_INC_CPT: begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_CPT_WAIT; end // Wait for IODELAY for both capture and internal nodes within // ISERDES to settle, before checking again for an edge CAL1_PB_INC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE; end // We've found the left edges of the windows for all DQ bits // (actually, we found it MIN_EYE_SIZE taps ago) Decrement capture // clock IDELAY to position just outside left edge of data window CAL1_PB_DEC_CPT_LEFT: if (cnt_idel_dec_cpt_r == 6'b000000) cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT_WAIT; else begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; end CAL1_PB_DEC_CPT_LEFT_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ; // If there is skew between individual DQ bits, then after we've // positioned the CPT clock, we will be "in the window" for some // DQ bits ("early" DQ bits), and "out of the window" for others // ("late" DQ bits). Increase DQ taps until we are out of the // window for all DQ bits CAL1_PB_DETECT_EDGE_DQ: if (detect_edge_done_r) if (found_edge_all_r) begin // We're out of the window for all DQ bits in this DQS group // We're done with per-bit deskew for this group - now decr // capture clock IODELAY tap count back to 0, and proceed // with the rest of stage 1 calibration for this DQS group cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end else if (!idel_tap_limit_dq_pb_r) // If we still have DQ taps available for deskew, keep // incrementing IODELAY tap count for the appropriate DQ bits cal1_state_r <= #TCQ CAL1_PB_INC_DQ; else begin // Otherwise, stop immediately (we've done the best we can) // and proceed with rest of stage 1 calibration cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end CAL1_PB_INC_DQ: begin // Increment only those DQ for which an edge hasn't been found yet cal1_dlyce_dq_r <= #TCQ ~pb_found_edge_last_r; cal1_dlyinc_dq_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_DQ_WAIT; end CAL1_PB_INC_DQ_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ; // Decrement capture clock taps back to initial value CAL1_PB_DEC_CPT: if (cnt_idel_dec_cpt_r == 6'b000000) cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_WAIT; else begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; end // Wait for capture clock to settle, then proceed to rest of // state 1 calibration for this DQS group CAL1_PB_DEC_CPT_WAIT: if (!cal1_wait_r) begin store_sr_req_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; end // When first starting calibration for a DQS group, save the // current value of the read data shift register, and use this // as a reference. Note that for the first iteration of the // edge detection loop, we will in effect be checking for an edge // at IODELAY taps = 0 - normally, we are comparing the read data // for IODELAY taps = N, with the read data for IODELAY taps = N-1 // An edge can only be found at IODELAY taps = 0 if the read data // is changing during this time (possible due to jitter) CAL1_STORE_FIRST_WAIT: begin mpr_dec_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PAT_DETECT; end CAL1_VALID_WAIT: begin if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; end CAL1_MPR_PAT_DETECT: begin // MPR read leveling for centering DQS in valid window before // OCLKDELAYED calibration begins in order to eliminate read issues if (idel_pat_detect_valid_r == 1'b0) begin cal1_state_r <= #TCQ CAL1_VALID_WAIT; idel_pat_detect_valid_r <= #TCQ 1'b1; end else if (idel_pat_detect_valid_r && idel_mpr_pat_detect_r) begin cal1_state_r <= #TCQ CAL1_DETECT_EDGE; idel_dec_cnt <= #TCQ 'd0; end else if (!idelay_tap_limit_r) cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC; else cal1_state_r <= #TCQ CAL1_RDLVL_ERR; end CAL1_PAT_DETECT: begin // All DQ bits associated with a DQS are pushed to the right one IDELAY // tap at a time until first rising DQS is in the tri-state region // before first rising edge window. // The detect_edge_done_r condition included to support averaging // during IDELAY tap increments if (detect_edge_done_r) begin if (idel_pat_data_match) begin case (idelay_adj) 2'b01: begin cal1_state_r <= CAL1_DQ_IDEL_TAP_INC; idel_dec_cnt <= #TCQ 1'b0; idel_adj_inc <= #TCQ 1'b1; end 2'b10: begin //DEC by 1 cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC ; idel_dec_cnt <= #TCQ 1'b1; idel_adj_inc <= #TCQ 1'b0; end default: begin cal1_state_r <= #TCQ CAL1_DETECT_EDGE; idel_dec_cnt <= #TCQ 1'b0; idel_adj_inc <= #TCQ 1'b0; end endcase end else if (!idelay_tap_limit_r) begin cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC; end else begin cal1_state_r <= #TCQ CAL1_RDLVL_ERR; end end end // Increment IDELAY tap by 1 for DQ bits in the byte being calibrated // until left edge of valid window detected CAL1_DQ_IDEL_TAP_INC: begin cal1_dq_idel_ce <= #TCQ 1'b1; cal1_dq_idel_inc <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC_WAIT; idel_pat_detect_valid_r <= #TCQ 1'b0; end CAL1_DQ_IDEL_TAP_INC_WAIT: begin cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; if (!cal1_wait_r) begin idel_adj_inc <= #TCQ 1'b0; if (idel_adj_inc) cal1_state_r <= #TCQ CAL1_DETECT_EDGE; else if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3")) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; else cal1_state_r <= #TCQ CAL1_PAT_DETECT; end end // Decrement by 2 IDELAY taps once idel_pat_data_match detected CAL1_DQ_IDEL_TAP_DEC: begin cal1_dq_idel_inc <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC_WAIT; if (idel_dec_cnt >= 'd0) cal1_dq_idel_ce <= #TCQ 1'b1; else cal1_dq_idel_ce <= #TCQ 1'b0; if (idel_dec_cnt > 'd0) idel_dec_cnt <= #TCQ idel_dec_cnt - 1; else idel_dec_cnt <= #TCQ idel_dec_cnt; end CAL1_DQ_IDEL_TAP_DEC_WAIT: begin cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; if (!cal1_wait_r) begin if ((idel_dec_cnt > 'd0) || (pi_rdval_cnt > 'd0)) cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC; else if (mpr_dec_cpt_r) cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; else cal1_state_r <= #TCQ CAL1_DETECT_EDGE; end end // Check for presence of data eye edge. During this state, we // sample the read data multiple times, and look for changes // in the read data, specifically: // 1. A change in the read data compared with the value of // read data from the previous delay tap. This indicates // that the most recent tap delay increment has moved us // into either a new window, or moved/kept us in the // transition/jitter region between windows. Note that this // condition only needs to be checked for once, and for // logistical purposes, we check this soon after entering // this state (see comment in CAL1_DETECT_EDGE below for // why this is done) // 2. A change in the read data while we are in this state // (i.e. in the absence of a tap delay increment). This // indicates that we're close enough to a window edge that // jitter will cause the read data to change even in the // absence of a tap delay change CAL1_DETECT_EDGE: begin // Essentially wait for the first comparision to finish, then // store current data into "old" data register. This store // happens now, rather than later (e.g. when we've have already // left this state) in order to avoid the situation the data that // is stored as "old" data has not been used in an "active // comparison" - i.e. data is stored after the last comparison // of this state. In this case, we can miss an edge if the // following sequence occurs: // 1. Comparison completes in this state - no edge found // 2. "Momentary jitter" occurs which "pushes" the data out the // equivalent of one delay tap // 3. We store this jittered data as the "old" data // 4. "Jitter" no longer present // 5. We increment the delay tap by one // 6. Now we compare the current with the "old" data - they're // the same, and no edge is detected // NOTE: Given the large # of comparisons done in this state, it's // highly unlikely the above sequence will occur in actual H/W // Wait for the first load of read data into the comparison // shift register to finish, then load the current read data // into the "old" data register. This allows us to do one // initial comparision between the current read data, and // stored data corresponding to the previous delay tap idel_pat_detect_valid_r <= #TCQ 1'b0; if (!store_sr_req_pulsed_r) begin // Pulse store_sr_req_r only once in this state store_sr_req_r <= #TCQ 1'b1; store_sr_req_pulsed_r <= #TCQ 1'b1; end else begin store_sr_req_r <= #TCQ 1'b0; store_sr_req_pulsed_r <= #TCQ 1'b1; end // Continue to sample read data and look for edges until the // appropriate time interval (shorter for simulation-only, // much, much longer for actual h/w) has elapsed if (detect_edge_done_r) begin if (tap_limit_cpt_r) // Only one edge detected and ran out of taps since only one // bit time worth of taps available for window detection. This // can happen if at tap 0 DQS is in previous window which results // in only left edge being detected. Or at tap 0 DQS is in the // current window resulting in only right edge being detected. // Depending on the frequency this case can also happen if at // tap 0 DQS is in the left noise region resulting in only left // edge being detected. cal1_state_r <= #TCQ CAL1_CALC_IDEL; else if (found_edge_r) begin // Sticky bit - asserted after we encounter an edge, although // the current edge may not be considered the "first edge" this // just means we found at least one edge found_first_edge_r <= #TCQ 1'b1; // Only the right edge of the data valid window is found // Record the inner right edge tap value if (!found_first_edge_r && found_stable_eye_last_r) begin if (tap_cnt_cpt_r == 'd0) right_edge_taps_r <= #TCQ 'd0; else right_edge_taps_r <= #TCQ tap_cnt_cpt_r; end // Both edges of data valid window found: // If we've found a second edge after a region of stability // then we must have just passed the second ("right" edge of // the window. Record this second_edge_taps = current tap-1, // because we're one past the actual second edge tap, where // the edge taps represent the extremes of the data valid // window (i.e. smallest & largest taps where data still valid if (found_first_edge_r && found_stable_eye_last_r) begin found_second_edge_r <= #TCQ 1'b1; second_edge_taps_r <= #TCQ tap_cnt_cpt_r - 1; cal1_state_r <= #TCQ CAL1_CALC_IDEL; end else begin // Otherwise, an edge was found (just not the "second" edge) // Assuming DQS is in the correct window at tap 0 of Phaser IN // fine tap. The first edge found is the right edge of the valid // window and is the beginning of the jitter region hence done! first_edge_taps_r <= #TCQ tap_cnt_cpt_r; cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT; end end else // Otherwise, if we haven't found an edge.... // If we still have taps left to use, then keep incrementing cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT; end end // Increment Phaser_IN delay for DQS CAL1_IDEL_INC_CPT: begin cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT_WAIT; if (~tap_limit_cpt_r) begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b1; end else begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; end end // Wait for Phaser_In to settle, before checking again for an edge CAL1_IDEL_INC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_DETECT_EDGE; end // Calculate final value of Phaser_IN taps. At this point, one or both // edges of data eye have been found, and/or all taps have been // exhausted looking for the edges // NOTE: We're calculating the amount to decrement by, not the // absolute setting for DQS. CAL1_CALC_IDEL: begin // CASE1: If 2 edges found. if (found_second_edge_r) cnt_idel_dec_cpt_r <= #TCQ ((second_edge_taps_r - first_edge_taps_r)>>1) + 1; else if (right_edge_taps_r > 6'd0) // Only right edge detected // right_edge_taps_r is the inner right edge tap value // hence used for calculation cnt_idel_dec_cpt_r <= #TCQ (tap_cnt_cpt_r - (right_edge_taps_r>>1)); else if (found_first_edge_r) // Only left edge detected cnt_idel_dec_cpt_r <= #TCQ ((tap_cnt_cpt_r - first_edge_taps_r)>>1); else cnt_idel_dec_cpt_r <= #TCQ (tap_cnt_cpt_r>>1); // Now use the value we just calculated to decrement CPT taps // to the desired calibration point cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; end // decrement capture clock for final adjustment - center // capture clock in middle of data eye. This adjustment will occur // only when both the edges are found usign CPT taps. Must do this // incrementally to avoid clock glitching (since CPT drives clock // divider within each ISERDES) CAL1_IDEL_DEC_CPT: begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; // once adjustment is complete, we're done with calibration for // this DQS, repeat for next DQS cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; if (cnt_idel_dec_cpt_r == 6'b000001) begin if (mpr_dec_cpt_r) begin if (|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) begin idel_dec_cnt <= #TCQ idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC; end else cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; end else cal1_state_r <= #TCQ CAL1_NEXT_DQS; end else cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT_WAIT; end CAL1_IDEL_DEC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; end // Determine whether we're done, or have more DQS's to calibrate // Also request precharge after every byte, as appropriate CAL1_NEXT_DQS: begin //if (mpr_rdlvl_done_r || (DRAM_TYPE == "DDR2")) cal1_prech_req_r <= #TCQ 1'b1; //else // cal1_prech_req_r <= #TCQ 1'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; // Prepare for another iteration with next DQS group found_first_edge_r <= #TCQ 1'b0; found_second_edge_r <= #TCQ 1'b0; first_edge_taps_r <= #TCQ 'd0; second_edge_taps_r <= #TCQ 'd0; if ((SIM_CAL_OPTION == "FAST_CAL") || (cal1_cnt_cpt_r >= DQS_WIDTH-1)) begin if (mpr_rdlvl_done_r) begin rdlvl_last_byte_done <= #TCQ 1'b1; mpr_last_byte_done <= #TCQ 1'b0; end else begin rdlvl_last_byte_done <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b1; end end // Wait until precharge that occurs in between calibration of // DQS groups is finished if (prech_done) begin // || (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))) begin if (SIM_CAL_OPTION == "FAST_CAL") begin //rdlvl_rank_done_r <= #TCQ 1'b1; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_DONE; //CAL1_REGL_LOAD; end else if (cal1_cnt_cpt_r >= DQS_WIDTH-1) begin if (~mpr_rdlvl_done_r) begin mpr_rank_done_r <= #TCQ 1'b1; // if (rnk_cnt_r == RANKS-1) begin // All DQS groups in all ranks done cal1_state_r <= #TCQ CAL1_DONE; cal1_cnt_cpt_r <= #TCQ 'b0; // end else begin // // Process DQS groups in next rank // rnk_cnt_r <= #TCQ rnk_cnt_r + 1; // new_cnt_cpt_r <= #TCQ 1'b1; // cal1_cnt_cpt_r <= #TCQ 'b0; // cal1_state_r <= #TCQ CAL1_IDLE; // end end else begin // All DQS groups in a rank done rdlvl_rank_done_r <= #TCQ 1'b1; if (rnk_cnt_r == RANKS-1) begin // All DQS groups in all ranks done cal1_state_r <= #TCQ CAL1_REGL_LOAD; end else begin // Process DQS groups in next rank rnk_cnt_r <= #TCQ rnk_cnt_r + 1; new_cnt_cpt_r <= #TCQ 1'b1; cal1_cnt_cpt_r <= #TCQ 'b0; cal1_state_r <= #TCQ CAL1_IDLE; end end end else begin // Process next DQS group new_cnt_cpt_r <= #TCQ 1'b1; cal1_cnt_cpt_r <= #TCQ cal1_cnt_cpt_r + 1; cal1_state_r <= #TCQ CAL1_NEW_DQS_PREWAIT; end end end CAL1_NEW_DQS_PREWAIT: begin if (!cal1_wait_r) begin if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3")) cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT; else cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT; end end // Load rank registers in Phaser_IN CAL1_REGL_LOAD: begin rdlvl_rank_done_r <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; cal1_cnt_cpt_r <= #TCQ 'b0; rnk_cnt_r <= #TCQ 2'b00; if ((regl_rank_cnt == RANKS-1) && ((regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1))) begin cal1_state_r <= #TCQ CAL1_DONE; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; end else cal1_state_r <= #TCQ CAL1_REGL_LOAD; end CAL1_RDLVL_ERR: begin rdlvl_stg1_err <= #TCQ 1'b1; end // Done with this stage of calibration // if used, allow DEBUG_PORT to control taps CAL1_DONE: begin mpr_rdlvl_done_r <= #TCQ 1'b1; cal1_prech_req_r <= #TCQ 1'b0; if (~mpr_rdlvl_done_r && (OCAL_EN=="ON") && (DRAM_TYPE == "DDR3")) begin rdlvl_stg1_done <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_IDLE; end else rdlvl_stg1_done <= #TCQ 1'b1; end endcase end // verilint STARC-2.2.3.3 on endmodule
//***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_rdlvl.v // /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Read leveling Stage1 calibration logic // NOTES: // 1. Window detection with PRBS pattern. //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $ **$Date: 2011/06/24 14:49:00 $ **$Author: mgeorge $ **$Revision: 1.2 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_rdlvl.v,v $ ******************************************************************************/ `timescale 1ps/1ps (* use_dsp48 = "no" *) module mig_7series_v2_3_ddr_phy_rdlvl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter CLK_PERIOD = 3333, // Internal clock period (in ps) parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter RANKS = 1, // # of DRAM ranks parameter PER_BIT_DESKEW = "ON", // Enable per-bit DQ deskew parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps parameter DEBUG_PORT = "OFF", // Enable debug port parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" parameter OCAL_EN = "ON", parameter IDELAY_ADJ = "ON" ) ( input clk, input rst, // Calibration status, control signals input mpr_rdlvl_start, output mpr_rdlvl_done, output reg mpr_last_byte_done, output mpr_rnk_done, input rdlvl_stg1_start, output reg rdlvl_stg1_done /* synthesis syn_maxfan = 30 */, output rdlvl_stg1_rnk_done, output reg rdlvl_stg1_err, output mpr_rdlvl_err, output rdlvl_err, output reg rdlvl_prech_req, output reg rdlvl_last_byte_done, output reg rdlvl_assrt_common, input prech_done, input phy_if_empty, input [4:0] idelaye2_init_val, // Captured data in fabric clock domain input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Decrement initial Phaser_IN Fine tap delay input dqs_po_dec_done, input [5:0] pi_counter_read_val, // Stage 1 calibration outputs output reg pi_fine_dly_dec_done, output reg pi_en_stg2_f, output reg pi_stg2_f_incdec, output reg pi_stg2_load, output reg [5:0] pi_stg2_reg_l, output [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt, // To DQ IDELAY required to find left edge of // valid window output idelay_ce, output idelay_inc, input idelay_ld, input [DQS_CNT_WIDTH:0] wrcal_cnt, // Only output if Per-bit de-skew enabled output reg [5*RANKS*DQ_WIDTH-1:0] dlyval_dq, // Debug Port output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, input dbg_idel_up_all, input dbg_idel_down_all, input dbg_idel_up_cpt, input dbg_idel_down_cpt, input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, input dbg_sel_all_idel_cpt, output [255:0] dbg_phy_rdlvl ); // minimum time (in IDELAY taps) for which capture data must be stable for // algorithm to consider a valid data eye to be found. The read leveling // logic will ignore any window found smaller than this value. Limitations // on how small this number can be is determined by: (1) the algorithmic // limitation of how many taps wide the data eye can be (3 taps), and (2) // how wide regions of "instability" that occur around the edges of the // read valid window can be (i.e. need to be able to filter out "false" // windows that occur for a short # of taps around the edges of the true // data window, although with multi-sampling during read leveling, this is // not as much a concern) - the larger the value, the more protection // against "false" windows localparam MIN_EYE_SIZE = 16; // Length of calibration sequence (in # of words) localparam CAL_PAT_LEN = 8; // Read data shift register length localparam RD_SHIFT_LEN = CAL_PAT_LEN / (2*nCK_PER_CLK); // # of cycles required to perform read data shift register compare // This is defined as from the cycle the new data is loaded until // signal found_edge_r is valid localparam RD_SHIFT_COMP_DELAY = 5; // worst-case # of cycles to wait to ensure that both the SR and // PREV_SR shift registers have valid data, and that the comparison // of the two shift register values is valid. The "+1" at the end of // this equation is a fudge factor, I freely admit that localparam SR_VALID_DELAY = (2 * RD_SHIFT_LEN) + RD_SHIFT_COMP_DELAY + 1; // # of clock cycles to wait after changing tap value or read data MUX // to allow: (1) tap chain to settle, (2) for delayed input to propagate // thru ISERDES, (3) for the read data comparison logic to have time to // output the comparison of two consecutive samples of the settled read data // The minimum delay is 16 cycles, which should be good enough to handle all // three of the above conditions for the simulation-only case with a short // training pattern. For H/W (or for simulation with longer training // pattern), it will take longer to store and compare two consecutive // samples, and the value of this parameter will reflect that localparam PIPE_WAIT_CNT = (SR_VALID_DELAY < 8) ? 16 : (SR_VALID_DELAY + 8); // # of read data samples to examine when detecting whether an edge has // occured during stage 1 calibration. Width of local param must be // changed as appropriate. Note that there are two counters used, each // counter can be changed independently of the other - they are used in // cascade to create a larger counter localparam [11:0] DETECT_EDGE_SAMPLE_CNT0 = 12'h001; //12'hFFF; localparam [11:0] DETECT_EDGE_SAMPLE_CNT1 = 12'h001; // 12'h1FF Must be > 0 localparam [5:0] CAL1_IDLE = 6'h00; localparam [5:0] CAL1_NEW_DQS_WAIT = 6'h01; localparam [5:0] CAL1_STORE_FIRST_WAIT = 6'h02; localparam [5:0] CAL1_PAT_DETECT = 6'h03; localparam [5:0] CAL1_DQ_IDEL_TAP_INC = 6'h04; localparam [5:0] CAL1_DQ_IDEL_TAP_INC_WAIT = 6'h05; localparam [5:0] CAL1_DQ_IDEL_TAP_DEC = 6'h06; localparam [5:0] CAL1_DQ_IDEL_TAP_DEC_WAIT = 6'h07; localparam [5:0] CAL1_DETECT_EDGE = 6'h08; localparam [5:0] CAL1_IDEL_INC_CPT = 6'h09; localparam [5:0] CAL1_IDEL_INC_CPT_WAIT = 6'h0A; localparam [5:0] CAL1_CALC_IDEL = 6'h0B; localparam [5:0] CAL1_IDEL_DEC_CPT = 6'h0C; localparam [5:0] CAL1_IDEL_DEC_CPT_WAIT = 6'h0D; localparam [5:0] CAL1_NEXT_DQS = 6'h0E; localparam [5:0] CAL1_DONE = 6'h0F; localparam [5:0] CAL1_PB_STORE_FIRST_WAIT = 6'h10; localparam [5:0] CAL1_PB_DETECT_EDGE = 6'h11; localparam [5:0] CAL1_PB_INC_CPT = 6'h12; localparam [5:0] CAL1_PB_INC_CPT_WAIT = 6'h13; localparam [5:0] CAL1_PB_DEC_CPT_LEFT = 6'h14; localparam [5:0] CAL1_PB_DEC_CPT_LEFT_WAIT = 6'h15; localparam [5:0] CAL1_PB_DETECT_EDGE_DQ = 6'h16; localparam [5:0] CAL1_PB_INC_DQ = 6'h17; localparam [5:0] CAL1_PB_INC_DQ_WAIT = 6'h18; localparam [5:0] CAL1_PB_DEC_CPT = 6'h19; localparam [5:0] CAL1_PB_DEC_CPT_WAIT = 6'h1A; localparam [5:0] CAL1_REGL_LOAD = 6'h1B; localparam [5:0] CAL1_RDLVL_ERR = 6'h1C; localparam [5:0] CAL1_MPR_NEW_DQS_WAIT = 6'h1D; localparam [5:0] CAL1_VALID_WAIT = 6'h1E; localparam [5:0] CAL1_MPR_PAT_DETECT = 6'h1F; localparam [5:0] CAL1_NEW_DQS_PREWAIT = 6'h20; integer a; integer b; integer d; integer e; integer f; integer h; integer g; integer i; integer j; integer k; integer l; integer m; integer n; integer r; integer p; integer q; integer s; integer t; integer u; integer w; integer ce_i; integer ce_rnk_i; integer aa; integer bb; integer cc; integer dd; genvar x; genvar z; reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_r; wire [DQS_CNT_WIDTH+2:0]cal1_cnt_cpt_timing; reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_timing_r; reg cal1_dq_idel_ce; reg cal1_dq_idel_inc; reg cal1_dlyce_cpt_r; reg cal1_dlyinc_cpt_r; reg cal1_dlyce_dq_r; reg cal1_dlyinc_dq_r; reg cal1_wait_cnt_en_r; reg [4:0] cal1_wait_cnt_r; reg cal1_wait_r; reg [DQ_WIDTH-1:0] dlyce_dq_r; reg dlyinc_dq_r; reg [4:0] dlyval_dq_reg_r [0:RANKS-1][0:DQ_WIDTH-1]; reg cal1_prech_req_r; reg [5:0] cal1_state_r; reg [5:0] cal1_state_r1; reg [5:0] cnt_idel_dec_cpt_r; reg [3:0] cnt_shift_r; reg detect_edge_done_r; reg [5:0] right_edge_taps_r; reg [5:0] first_edge_taps_r; reg found_edge_r; reg found_first_edge_r; reg found_second_edge_r; reg found_stable_eye_r; reg found_stable_eye_last_r; reg found_edge_all_r; reg [5:0] tap_cnt_cpt_r; reg tap_limit_cpt_r; reg [4:0] idel_tap_cnt_dq_pb_r; reg idel_tap_limit_dq_pb_r; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r; reg mux_rd_valid_r; reg new_cnt_cpt_r; reg [RD_SHIFT_LEN-1:0] old_sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise3_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] old_sr_match_fall0_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall1_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise0_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise1_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall2_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall3_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise2_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise3_r; reg [4:0] pb_cnt_eye_size_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] pb_detect_edge_done_r; reg [DRAM_WIDTH-1:0] pb_found_edge_last_r; reg [DRAM_WIDTH-1:0] pb_found_edge_r; reg [DRAM_WIDTH-1:0] pb_found_first_edge_r; reg [DRAM_WIDTH-1:0] pb_found_stable_eye_r; reg [DRAM_WIDTH-1:0] pb_last_tap_jitter_r; reg pi_en_stg2_f_timing; reg pi_stg2_f_incdec_timing; reg pi_stg2_load_timing; reg [5:0] pi_stg2_reg_l_timing; reg [DRAM_WIDTH-1:0] prev_sr_diff_r; reg [RD_SHIFT_LEN-1:0] prev_sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise3_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] prev_sr_match_cyc2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall0_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall1_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise0_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise1_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall3_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise3_r; wire [DQ_WIDTH-1:0] rd_data_rise0; wire [DQ_WIDTH-1:0] rd_data_fall0; wire [DQ_WIDTH-1:0] rd_data_rise1; wire [DQ_WIDTH-1:0] rd_data_fall1; wire [DQ_WIDTH-1:0] rd_data_rise2; wire [DQ_WIDTH-1:0] rd_data_fall2; wire [DQ_WIDTH-1:0] rd_data_rise3; wire [DQ_WIDTH-1:0] rd_data_fall3; reg samp_cnt_done_r; reg samp_edge_cnt0_en_r; reg [11:0] samp_edge_cnt0_r; reg samp_edge_cnt1_en_r; reg [11:0] samp_edge_cnt1_r; reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; reg [5:0] second_edge_taps_r; reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0]; reg store_sr_r; reg store_sr_req_pulsed_r; reg store_sr_req_r; reg sr_valid_r; reg sr_valid_r1; reg sr_valid_r2; reg [DRAM_WIDTH-1:0] old_sr_diff_r; reg [DRAM_WIDTH-1:0] old_sr_match_cyc2_r; reg pat0_data_match_r; reg pat1_data_match_r; wire pat_data_match_r; wire [RD_SHIFT_LEN-1:0] pat0_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall3 [3:0]; reg [DRAM_WIDTH-1:0] pat0_match_fall0_r; reg pat0_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall1_r; reg pat0_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall2_r; reg pat0_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall3_r; reg pat0_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise0_r; reg pat0_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise1_r; reg pat0_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise2_r; reg pat0_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise3_r; reg pat0_match_rise3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall0_r; reg pat1_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall1_r; reg pat1_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall2_r; reg pat1_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall3_r; reg pat1_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise0_r; reg pat1_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise1_r; reg pat1_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise2_r; reg pat1_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise3_r; reg pat1_match_rise3_and_r; reg [4:0] idelay_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1]; reg [5*DQS_WIDTH*RANKS-1:0] idelay_tap_cnt_w; reg [4:0] idelay_tap_cnt_slice_r; reg idelay_tap_limit_r; wire [RD_SHIFT_LEN-1:0] pat0_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall3 [3:0]; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise0_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall0_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise1_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall1_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise2_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall2_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise3_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall3_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise0_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall0_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise1_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall1_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise2_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall2_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise3_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall3_r; reg idel_pat0_match_rise0_and_r; reg idel_pat0_match_fall0_and_r; reg idel_pat0_match_rise1_and_r; reg idel_pat0_match_fall1_and_r; reg idel_pat0_match_rise2_and_r; reg idel_pat0_match_fall2_and_r; reg idel_pat0_match_rise3_and_r; reg idel_pat0_match_fall3_and_r; reg idel_pat1_match_rise0_and_r; reg idel_pat1_match_fall0_and_r; reg idel_pat1_match_rise1_and_r; reg idel_pat1_match_fall1_and_r; reg idel_pat1_match_rise2_and_r; reg idel_pat1_match_fall2_and_r; reg idel_pat1_match_rise3_and_r; reg idel_pat1_match_fall3_and_r; reg idel_pat0_data_match_r; reg idel_pat1_data_match_r; reg idel_pat_data_match; reg idel_pat_data_match_r; reg [4:0] idel_dec_cnt; reg [5:0] rdlvl_dqs_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1]; reg [1:0] rnk_cnt_r; reg rdlvl_rank_done_r; reg [3:0] done_cnt; reg [1:0] regl_rank_cnt; reg [DQS_CNT_WIDTH:0] regl_dqs_cnt; reg [DQS_CNT_WIDTH:0] regl_dqs_cnt_r; wire [DQS_CNT_WIDTH+2:0]regl_dqs_cnt_timing; reg regl_rank_done_r; reg rdlvl_stg1_start_r; reg dqs_po_dec_done_r1; reg dqs_po_dec_done_r2; reg fine_dly_dec_done_r1; reg fine_dly_dec_done_r2; reg [3:0] wait_cnt_r; reg [5:0] pi_rdval_cnt; reg pi_cnt_dec; reg mpr_valid_r; reg mpr_valid_r1; reg mpr_valid_r2; reg mpr_rd_rise0_prev_r; reg mpr_rd_fall0_prev_r; reg mpr_rd_rise1_prev_r; reg mpr_rd_fall1_prev_r; reg mpr_rd_rise2_prev_r; reg mpr_rd_fall2_prev_r; reg mpr_rd_rise3_prev_r; reg mpr_rd_fall3_prev_r; reg mpr_rdlvl_done_r; reg mpr_rdlvl_done_r1; reg mpr_rdlvl_done_r2; reg mpr_rdlvl_start_r; reg mpr_rank_done_r; reg [2:0] stable_idel_cnt; reg inhibit_edge_detect_r; reg idel_pat_detect_valid_r; reg idel_mpr_pat_detect_r; reg mpr_pat_detect_r; reg mpr_dec_cpt_r; reg idel_adj_inc; //IDELAY adjustment wire [1:0] idelay_adj; wire pb_detect_edge_setup; wire pb_detect_edge; // Debug reg [6*DQS_WIDTH-1:0] dbg_cpt_first_edge_taps; reg [6*DQS_WIDTH-1:0] dbg_cpt_second_edge_taps; reg [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt_w; //IDELAY adjustment setting for -1 //2'b10 : IDELAY - 1 //2'b01 : IDELAY + 1 //2'b00 : No IDELAY adjustment assign idelay_adj = (IDELAY_ADJ == "ON") ? 2'b10: 2'b00; //*************************************************************************** // Debug //*************************************************************************** always @(*) begin for (d = 0; d < RANKS; d = d + 1) begin for (e = 0; e < DQS_WIDTH; e = e + 1) begin idelay_tap_cnt_w[(5*e+5*DQS_WIDTH*d)+:5] = idelay_tap_cnt_r[d][e]; dbg_cpt_tap_cnt_w[(6*e+6*DQS_WIDTH*d)+:6] = rdlvl_dqs_tap_cnt_r[d][e]; end end end assign mpr_rdlvl_err = rdlvl_stg1_err & (!mpr_rdlvl_done); assign rdlvl_err = rdlvl_stg1_err & (mpr_rdlvl_done); assign dbg_phy_rdlvl[0] = rdlvl_stg1_start; assign dbg_phy_rdlvl[1] = pat_data_match_r; assign dbg_phy_rdlvl[2] = mux_rd_valid_r; assign dbg_phy_rdlvl[3] = idelay_tap_limit_r; assign dbg_phy_rdlvl[8:4] = 'b0; assign dbg_phy_rdlvl[14:9] = cal1_state_r[5:0]; assign dbg_phy_rdlvl[20:15] = cnt_idel_dec_cpt_r; assign dbg_phy_rdlvl[21] = found_first_edge_r; assign dbg_phy_rdlvl[22] = found_second_edge_r; assign dbg_phy_rdlvl[23] = found_edge_r; assign dbg_phy_rdlvl[24] = store_sr_r; // [40:25] previously used for sr, old_sr shift registers. If connecting // these signals again, don't forget to parameterize based on RD_SHIFT_LEN assign dbg_phy_rdlvl[40:25] = 'b0; assign dbg_phy_rdlvl[41] = sr_valid_r; assign dbg_phy_rdlvl[42] = found_stable_eye_r; assign dbg_phy_rdlvl[48:43] = tap_cnt_cpt_r; assign dbg_phy_rdlvl[54:49] = first_edge_taps_r; assign dbg_phy_rdlvl[60:55] = second_edge_taps_r; assign dbg_phy_rdlvl[64:61] = cal1_cnt_cpt_timing_r; assign dbg_phy_rdlvl[65] = cal1_dlyce_cpt_r; assign dbg_phy_rdlvl[66] = cal1_dlyinc_cpt_r; assign dbg_phy_rdlvl[67] = found_edge_r; assign dbg_phy_rdlvl[68] = found_first_edge_r; assign dbg_phy_rdlvl[73:69] = 'b0; assign dbg_phy_rdlvl[74] = idel_pat_data_match; assign dbg_phy_rdlvl[75] = idel_pat0_data_match_r; assign dbg_phy_rdlvl[76] = idel_pat1_data_match_r; assign dbg_phy_rdlvl[77] = pat0_data_match_r; assign dbg_phy_rdlvl[78] = pat1_data_match_r; assign dbg_phy_rdlvl[79+:5*DQS_WIDTH*RANKS] = idelay_tap_cnt_w; assign dbg_phy_rdlvl[170+:8] = mux_rd_rise0_r; assign dbg_phy_rdlvl[178+:8] = mux_rd_fall0_r; assign dbg_phy_rdlvl[186+:8] = mux_rd_rise1_r; assign dbg_phy_rdlvl[194+:8] = mux_rd_fall1_r; assign dbg_phy_rdlvl[202+:8] = mux_rd_rise2_r; assign dbg_phy_rdlvl[210+:8] = mux_rd_fall2_r; assign dbg_phy_rdlvl[218+:8] = mux_rd_rise3_r; assign dbg_phy_rdlvl[226+:8] = mux_rd_fall3_r; //*************************************************************************** // Debug output //*************************************************************************** // CPT taps assign dbg_cpt_first_edge_cnt = dbg_cpt_first_edge_taps; assign dbg_cpt_second_edge_cnt = dbg_cpt_second_edge_taps; assign dbg_cpt_tap_cnt = dbg_cpt_tap_cnt_w; assign dbg_dq_idelay_tap_cnt = idelay_tap_cnt_w; // Record first and second edges found during CPT calibration generate always @(posedge clk) if (rst) begin dbg_cpt_first_edge_taps <= #TCQ 'b0; dbg_cpt_second_edge_taps <= #TCQ 'b0; end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_CALC_IDEL)) begin //for (ce_rnk_i = 0; ce_rnk_i < RANKS; ce_rnk_i = ce_rnk_i + 1) begin: gen_dbg_cpt_rnk for (ce_i = 0; ce_i < DQS_WIDTH; ce_i = ce_i + 1) begin: gen_dbg_cpt_edge if (found_first_edge_r) dbg_cpt_first_edge_taps[(6*ce_i)+:6] <= #TCQ first_edge_taps_r; if (found_second_edge_r) dbg_cpt_second_edge_taps[(6*ce_i)+:6] <= #TCQ second_edge_taps_r; end //end end else if (cal1_state_r == CAL1_CALC_IDEL) begin // Record tap counts of first and second edge edges during // CPT calibration for each DQS group. If neither edge has // been found, then those taps will remain 0 if (found_first_edge_r) dbg_cpt_first_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6] <= #TCQ first_edge_taps_r; if (found_second_edge_r) dbg_cpt_second_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6] <= #TCQ second_edge_taps_r; end endgenerate assign rdlvl_stg1_rnk_done = rdlvl_rank_done_r;// || regl_rank_done_r; assign mpr_rnk_done = mpr_rank_done_r; assign mpr_rdlvl_done = ((DRAM_TYPE == "DDR3") && (OCAL_EN == "ON")) ? //&& (SIM_CAL_OPTION == "NONE") mpr_rdlvl_done_r : 1'b1; //************************************************************************** // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 // coarse delay //************************************************************************** assign pi_stg2_rdlvl_cnt = (cal1_state_r == CAL1_REGL_LOAD) ? regl_dqs_cnt_r : cal1_cnt_cpt_r; assign idelay_ce = cal1_dq_idel_ce; assign idelay_inc = cal1_dq_idel_inc; //*************************************************************************** // Assert calib_in_common in FAST_CAL mode for IDELAY tap increments to all // DQs simultaneously //*************************************************************************** always @(posedge clk) begin if (rst) rdlvl_assrt_common <= #TCQ 1'b0; else if ((SIM_CAL_OPTION == "FAST_CAL") & rdlvl_stg1_start & !rdlvl_stg1_start_r) rdlvl_assrt_common <= #TCQ 1'b1; else if (!idel_pat_data_match_r & idel_pat_data_match) rdlvl_assrt_common <= #TCQ 1'b0; end //*************************************************************************** // Data mux to route appropriate bit to calibration logic - i.e. calibration // is done sequentially, one bit (or DQS group) at a time //*************************************************************************** generate if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; end else begin: rd_data_div2_logic_clk assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; end endgenerate always @(posedge clk) begin rd_mux_sel_r <= #TCQ cal1_cnt_cpt_r; end // Register outputs for improved timing. // NOTE: Will need to change when per-bit DQ deskew is supported. // Currenly all bits in DQS group are checked in aggregate generate genvar mux_i; for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end endgenerate //*************************************************************************** // MPR Read Leveling //*************************************************************************** // storing the previous read data for checking later. Only bit 0 is used // since MPR contents (01010101) are available generally on DQ[0] per // JEDEC spec. always @(posedge clk)begin if ((cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) || ((cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r)))begin mpr_rd_rise0_prev_r <= #TCQ mux_rd_rise0_r[0]; mpr_rd_fall0_prev_r <= #TCQ mux_rd_fall0_r[0]; mpr_rd_rise1_prev_r <= #TCQ mux_rd_rise1_r[0]; mpr_rd_fall1_prev_r <= #TCQ mux_rd_fall1_r[0]; mpr_rd_rise2_prev_r <= #TCQ mux_rd_rise2_r[0]; mpr_rd_fall2_prev_r <= #TCQ mux_rd_fall2_r[0]; mpr_rd_rise3_prev_r <= #TCQ mux_rd_rise3_r[0]; mpr_rd_fall3_prev_r <= #TCQ mux_rd_fall3_r[0]; end end generate if (nCK_PER_CLK == 4) begin: mpr_4to1 // changed stable count of 2 IDELAY taps at 78 ps resolution always @(posedge clk) begin if (rst | (cal1_state_r == CAL1_NEW_DQS_PREWAIT) | //(cal1_state_r == CAL1_DETECT_EDGE) | (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) | (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) | (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) | (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) | (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) | (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) | (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) | (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0])) stable_idel_cnt <= #TCQ 3'd0; else if ((|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) & ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) begin if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) & (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) & (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) & (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) & (mpr_rd_rise2_prev_r == mux_rd_rise2_r[0]) & (mpr_rd_fall2_prev_r == mux_rd_fall2_r[0]) & (mpr_rd_rise3_prev_r == mux_rd_rise3_r[0]) & (mpr_rd_fall3_prev_r == mux_rd_fall3_r[0]) & (stable_idel_cnt < 3'd2)) stable_idel_cnt <= #TCQ stable_idel_cnt + 1; end end always @(posedge clk) begin if (rst | (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r & mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r & mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r)) inhibit_edge_detect_r <= 1'b1; // Wait for settling time after idelay tap increment before // de-asserting inhibit_edge_detect_r else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) & (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r & ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r & ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r)) inhibit_edge_detect_r <= 1'b0; end //checking for transition from 01010101 to 10101010 always @(posedge clk)begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | inhibit_edge_detect_r) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 10101010 is not the correct pattern else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r & mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r & mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r) || ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r))) //|| (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2)) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 01010101 to 10101010 is the correct transition else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r & ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r & ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r) & (stable_idel_cnt == 3'd2) & ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) || (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) || (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) || (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) || (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) || (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) || (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) || (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0]))) idel_mpr_pat_detect_r <= #TCQ 1'b1; end end else if (nCK_PER_CLK == 2) begin: mpr_2to1 // changed stable count of 2 IDELAY taps at 78 ps resolution always @(posedge clk) begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) | (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) | (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) | (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0])) stable_idel_cnt <= #TCQ 3'd0; else if ((idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd0) & ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) begin if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) & (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) & (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) & (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) & (stable_idel_cnt < 3'd2)) stable_idel_cnt <= #TCQ stable_idel_cnt + 1; end end always @(posedge clk) begin if (rst | (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r)) inhibit_edge_detect_r <= 1'b1; else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) & (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r)) inhibit_edge_detect_r <= 1'b0; end //checking for transition from 01010101 to 10101010 always @(posedge clk)begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | inhibit_edge_detect_r) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 1010 is not the correct pattern else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r) || ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) // ||(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2)) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 0101 to 1010 is the correct transition else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r) & (stable_idel_cnt == 3'd2) & ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) || (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) || (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) || (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]))) idel_mpr_pat_detect_r <= #TCQ 1'b1; end end endgenerate // Registered signal indicates when mux_rd_rise/fall_r is valid always @(posedge clk) mux_rd_valid_r <= #TCQ ~phy_if_empty; //*************************************************************************** // Decrement initial Phaser_IN fine delay value before proceeding with // read calibration //*************************************************************************** always @(posedge clk) begin dqs_po_dec_done_r1 <= #TCQ dqs_po_dec_done; dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1; fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1; pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r2; end always @(posedge clk) begin if (rst || pi_cnt_dec) wait_cnt_r <= #TCQ 'd8; else if (dqs_po_dec_done_r2 && (wait_cnt_r > 'd0)) wait_cnt_r <= #TCQ wait_cnt_r - 1; end always @(posedge clk) begin if (rst) begin pi_rdval_cnt <= #TCQ 'd0; end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin pi_rdval_cnt <= #TCQ pi_counter_read_val; end else if (pi_rdval_cnt > 'd0) begin if (pi_cnt_dec) pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1; else pi_rdval_cnt <= #TCQ pi_rdval_cnt; end else if (pi_rdval_cnt == 'd0) begin pi_rdval_cnt <= #TCQ pi_rdval_cnt; end end always @(posedge clk) begin if (rst || (pi_rdval_cnt == 'd0)) pi_cnt_dec <= #TCQ 1'b0; else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0) && (wait_cnt_r == 'd1)) pi_cnt_dec <= #TCQ 1'b1; else pi_cnt_dec <= #TCQ 1'b0; end always @(posedge clk) begin if (rst) begin fine_dly_dec_done_r1 <= #TCQ 1'b0; end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) || (dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin fine_dly_dec_done_r1 <= #TCQ 1'b1; end end //*************************************************************************** // Demultiplexor to control Phaser_IN delay values //*************************************************************************** // Read DQS always @(posedge clk) begin if (rst) begin pi_en_stg2_f_timing <= #TCQ 'b0; pi_stg2_f_incdec_timing <= #TCQ 'b0; end else if (pi_cnt_dec) begin pi_en_stg2_f_timing <= #TCQ 'b1; pi_stg2_f_incdec_timing <= #TCQ 'b0; end else if (cal1_dlyce_cpt_r) begin if ((SIM_CAL_OPTION == "NONE") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin // Change only specified DQS pi_en_stg2_f_timing <= #TCQ 1'b1; pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r; end else if (SIM_CAL_OPTION == "FAST_CAL") begin // if simulating, and "shortcuts" for calibration enabled, apply // results to all DQSs (i.e. assume same delay on all // DQSs). pi_en_stg2_f_timing <= #TCQ 1'b1; pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r; end end else begin pi_en_stg2_f_timing <= #TCQ 'b0; pi_stg2_f_incdec_timing <= #TCQ 'b0; end end // registered for timing always @(posedge clk) begin pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing; pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing; end // This counter used to implement settling time between // Phaser_IN rank register loads to different DQSs always @(posedge clk) begin if (rst) done_cnt <= #TCQ 'b0; else if (((cal1_state_r == CAL1_REGL_LOAD) && (cal1_state_r1 == CAL1_NEXT_DQS)) || ((done_cnt == 4'd1) && (cal1_state_r != CAL1_DONE))) done_cnt <= #TCQ 4'b1010; else if (done_cnt > 'b0) done_cnt <= #TCQ done_cnt - 1; end // During rank register loading the rank count must be sent to // Phaser_IN via the phy_ctl_wd?? If so phy_init will have to // issue NOPs during rank register loading with the appropriate // rank count always @(posedge clk) begin if (rst || (regl_rank_done_r == 1'b1)) regl_rank_done_r <= #TCQ 1'b0; else if ((regl_dqs_cnt == DQS_WIDTH-1) && (regl_rank_cnt != RANKS-1) && (done_cnt == 4'd1)) regl_rank_done_r <= #TCQ 1'b1; end // Temp wire for timing. // The following in the always block below causes timing issues // due to DSP block inference // 6*regl_dqs_cnt. // replacing this with two left shifts + 1 left shift to avoid // DSP multiplier. assign regl_dqs_cnt_timing = {2'd0, regl_dqs_cnt}; // Load Phaser_OUT rank register with rdlvl delay value // for each DQS per rank. always @(posedge clk) begin if (rst || (done_cnt == 4'd0)) begin pi_stg2_load_timing <= #TCQ 'b0; pi_stg2_reg_l_timing <= #TCQ 'b0; end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt <= DQS_WIDTH-1) && (done_cnt == 4'd1)) begin pi_stg2_load_timing <= #TCQ 'b1; pi_stg2_reg_l_timing <= #TCQ rdlvl_dqs_tap_cnt_r[rnk_cnt_r][regl_dqs_cnt]; end else begin pi_stg2_load_timing <= #TCQ 'b0; pi_stg2_reg_l_timing <= #TCQ 'b0; end end // registered for timing always @(posedge clk) begin pi_stg2_load <= #TCQ pi_stg2_load_timing; pi_stg2_reg_l <= #TCQ pi_stg2_reg_l_timing; end always @(posedge clk) begin if (rst || (done_cnt == 4'd0) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) regl_rank_cnt <= #TCQ 2'b00; else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin if (regl_rank_cnt == RANKS-1) regl_rank_cnt <= #TCQ regl_rank_cnt; else regl_rank_cnt <= #TCQ regl_rank_cnt + 1; end end always @(posedge clk) begin if (rst || (done_cnt == 4'd0) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) regl_dqs_cnt <= #TCQ {DQS_CNT_WIDTH+1{1'b0}}; else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin if (regl_rank_cnt == RANKS-1) regl_dqs_cnt <= #TCQ regl_dqs_cnt; else regl_dqs_cnt <= #TCQ 'b0; end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt != DQS_WIDTH-1) && (done_cnt == 4'd1)) regl_dqs_cnt <= #TCQ regl_dqs_cnt + 1; else regl_dqs_cnt <= #TCQ regl_dqs_cnt; end always @(posedge clk) regl_dqs_cnt_r <= #TCQ regl_dqs_cnt; //***************************************************************** // DQ Stage 1 CALIBRATION INCREMENT/DECREMENT LOGIC: // The actual IDELAY elements for each of the DQ bits is set via the // DLYVAL parallel load port. However, the stage 1 calibration // algorithm (well most of it) only needs to increment or decrement the DQ // IDELAY value by 1 at any one time. //***************************************************************** // Chip-select generation for each of the individual counters tracking // IDELAY tap values for each DQ generate for (z = 0; z < DQS_WIDTH; z = z + 1) begin: gen_dlyce_dq always @(posedge clk) if (rst) dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; else if (SIM_CAL_OPTION == "SKIP_CAL") // If skipping calibration altogether (only for simulation), no // need to set DQ IODELAY values - they are hardcoded dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; else if (SIM_CAL_OPTION == "FAST_CAL") begin // If fast calibration option (simulation only) selected, DQ // IODELAYs across all bytes are updated simultaneously // (although per-bit deskew within DQS[0] is still supported) for (h = 0; h < DRAM_WIDTH; h = h + 1) begin dlyce_dq_r[DRAM_WIDTH*z + h] <= #TCQ cal1_dlyce_dq_r; end end else if ((SIM_CAL_OPTION == "NONE") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin if (cal1_cnt_cpt_r == z) begin for (g = 0; g < DRAM_WIDTH; g = g + 1) begin dlyce_dq_r[DRAM_WIDTH*z + g] <= #TCQ cal1_dlyce_dq_r; end end else dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; end end endgenerate // Also delay increment/decrement control to match delay on DLYCE always @(posedge clk) if (rst) dlyinc_dq_r <= #TCQ 1'b0; else dlyinc_dq_r <= #TCQ cal1_dlyinc_dq_r; // Each DQ has a counter associated with it to record current read-leveling // delay value always @(posedge clk) // Reset or skipping calibration all together if (rst | (SIM_CAL_OPTION == "SKIP_CAL")) begin for (aa = 0; aa < RANKS; aa = aa + 1) begin: rst_dlyval_dq_reg_r for (bb = 0; bb < DQ_WIDTH; bb = bb + 1) dlyval_dq_reg_r[aa][bb] <= #TCQ 'b0; end end else if (SIM_CAL_OPTION == "FAST_CAL") begin for (n = 0; n < RANKS; n = n + 1) begin: gen_dlyval_dq_reg_rnk for (r = 0; r < DQ_WIDTH; r = r + 1) begin: gen_dlyval_dq_reg if (dlyce_dq_r[r]) begin if (dlyinc_dq_r) dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] + 5'h01; else dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] - 5'h01; end end end end else begin if (dlyce_dq_r[cal1_cnt_cpt_r]) begin if (dlyinc_dq_r) dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] + 5'h01; else dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] - 5'h01; end end // Register for timing (help with logic placement) always @(posedge clk) begin for (cc = 0; cc < RANKS; cc = cc + 1) begin: dlyval_dq_assgn for (dd = 0; dd < DQ_WIDTH; dd = dd + 1) dlyval_dq[((5*dd)+(cc*DQ_WIDTH*5))+:5] <= #TCQ dlyval_dq_reg_r[cc][dd]; end end //*************************************************************************** // Generate signal used to delay calibration state machine - used when: // (1) IDELAY value changed // (2) RD_MUX_SEL value changed // Use when a delay is necessary to give the change time to propagate // through the data pipeline (through IDELAY and ISERDES, and fabric // pipeline stages) //*************************************************************************** // List all the stage 1 calibration wait states here. // verilint STARC-2.7.3.3b off always @(posedge clk) if ((cal1_state_r == CAL1_NEW_DQS_WAIT) || (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) || (cal1_state_r == CAL1_NEW_DQS_PREWAIT) || (cal1_state_r == CAL1_VALID_WAIT) || (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_INC_CPT_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT) || (cal1_state_r == CAL1_PB_INC_DQ_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_WAIT) || (cal1_state_r == CAL1_IDEL_INC_CPT_WAIT) || (cal1_state_r == CAL1_IDEL_DEC_CPT_WAIT) || (cal1_state_r == CAL1_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_DQ_IDEL_TAP_INC_WAIT) || (cal1_state_r == CAL1_DQ_IDEL_TAP_DEC_WAIT)) cal1_wait_cnt_en_r <= #TCQ 1'b1; else cal1_wait_cnt_en_r <= #TCQ 1'b0; // verilint STARC-2.7.3.3b on always @(posedge clk) if (!cal1_wait_cnt_en_r) begin cal1_wait_cnt_r <= #TCQ 5'b00000; cal1_wait_r <= #TCQ 1'b1; end else begin if (cal1_wait_cnt_r != PIPE_WAIT_CNT - 1) begin cal1_wait_cnt_r <= #TCQ cal1_wait_cnt_r + 1; cal1_wait_r <= #TCQ 1'b1; end else begin // Need to reset to 0 to handle the case when there are two // different WAIT states back-to-back cal1_wait_cnt_r <= #TCQ 5'b00000; cal1_wait_r <= #TCQ 1'b0; end end //*************************************************************************** // generate request to PHY_INIT logic to issue precharged. Required when // calibration can take a long time (during which there are only constant // reads present on this bus). In this case need to issue perioidic // precharges to avoid tRAS violation. This signal must meet the following // requirements: (1) only transition from 0->1 when prech is first needed, // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted //*************************************************************************** always @(posedge clk) if (rst) rdlvl_prech_req <= #TCQ 1'b0; else rdlvl_prech_req <= #TCQ cal1_prech_req_r; //*************************************************************************** // Serial-to-parallel register to store last RDDATA_SHIFT_LEN cycles of // data from ISERDES. The value of this register is also stored, so that // previous and current values of the ISERDES data can be compared while // varying the IODELAY taps to see if an "edge" of the data valid window // has been encountered since the last IODELAY tap adjustment //*************************************************************************** //*************************************************************************** // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES // NOTE: Written using discrete flops, but SRL can be used if the matching // logic does the comparison sequentially, rather than parallel //*************************************************************************** generate genvar rd_i; if (nCK_PER_CLK == 4) begin: gen_sr_div4 if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i]; sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i]; sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i]; sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i]; end end end end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall1_r[rd_i]}; sr_rise2_r[rd_i] <= #TCQ {sr_rise2_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise2_r[rd_i]}; sr_fall2_r[rd_i] <= #TCQ {sr_fall2_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall2_r[rd_i]}; sr_rise3_r[rd_i] <= #TCQ {sr_rise3_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise3_r[rd_i]}; sr_fall3_r[rd_i] <= #TCQ {sr_fall3_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall3_r[rd_i]}; end end end end end else if (nCK_PER_CLK == 2) begin: gen_sr_div2 if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {mux_rd_fall1_r[rd_i]}; end end end end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall1_r[rd_i]}; end end end end end endgenerate //*************************************************************************** // Conversion to pattern calibration //*************************************************************************** // Pattern for DQ IDELAY calibration //***************************************************************** // Expected data pattern when DQ shifted to the right such that // DQS before the left edge of the DVW: // Based on pattern of ({rise,fall}) = // 0x1, 0xB, 0x4, 0x4, 0xB, 0x9 // Each nibble will look like: // bit3: 0, 1, 0, 0, 1, 1 // bit2: 0, 0, 1, 1, 0, 0 // bit1: 0, 1, 0, 0, 1, 0 // bit0: 1, 1, 0, 0, 1, 1 // Or if the write is early it could look like: // 0x4, 0x4, 0xB, 0x9, 0x6, 0xE // bit3: 0, 0, 1, 1, 0, 1 // bit2: 1, 1, 0, 0, 1, 1 // bit1: 0, 0, 1, 0, 1, 1 // bit0: 0, 0, 1, 1, 0, 0 // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN // and the actual training pattern contents change //***************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_pat_div4 // Pattern for DQ IDELAY increment // Target pattern for "early write" assign {idel_pat0_rise0[3], idel_pat0_rise0[2], idel_pat0_rise0[1], idel_pat0_rise0[0]} = 4'h1; assign {idel_pat0_fall0[3], idel_pat0_fall0[2], idel_pat0_fall0[1], idel_pat0_fall0[0]} = 4'h7; assign {idel_pat0_rise1[3], idel_pat0_rise1[2], idel_pat0_rise1[1], idel_pat0_rise1[0]} = 4'hE; assign {idel_pat0_fall1[3], idel_pat0_fall1[2], idel_pat0_fall1[1], idel_pat0_fall1[0]} = 4'hC; assign {idel_pat0_rise2[3], idel_pat0_rise2[2], idel_pat0_rise2[1], idel_pat0_rise2[0]} = 4'h9; assign {idel_pat0_fall2[3], idel_pat0_fall2[2], idel_pat0_fall2[1], idel_pat0_fall2[0]} = 4'h2; assign {idel_pat0_rise3[3], idel_pat0_rise3[2], idel_pat0_rise3[1], idel_pat0_rise3[0]} = 4'h4; assign {idel_pat0_fall3[3], idel_pat0_fall3[2], idel_pat0_fall3[1], idel_pat0_fall3[0]} = 4'hB; // Target pattern for "on-time write" assign {idel_pat1_rise0[3], idel_pat1_rise0[2], idel_pat1_rise0[1], idel_pat1_rise0[0]} = 4'h4; assign {idel_pat1_fall0[3], idel_pat1_fall0[2], idel_pat1_fall0[1], idel_pat1_fall0[0]} = 4'h9; assign {idel_pat1_rise1[3], idel_pat1_rise1[2], idel_pat1_rise1[1], idel_pat1_rise1[0]} = 4'h3; assign {idel_pat1_fall1[3], idel_pat1_fall1[2], idel_pat1_fall1[1], idel_pat1_fall1[0]} = 4'h7; assign {idel_pat1_rise2[3], idel_pat1_rise2[2], idel_pat1_rise2[1], idel_pat1_rise2[0]} = 4'hE; assign {idel_pat1_fall2[3], idel_pat1_fall2[2], idel_pat1_fall2[1], idel_pat1_fall2[0]} = 4'hC; assign {idel_pat1_rise3[3], idel_pat1_rise3[2], idel_pat1_rise3[1], idel_pat1_rise3[0]} = 4'h9; assign {idel_pat1_fall3[3], idel_pat1_fall3[2], idel_pat1_fall3[1], idel_pat1_fall3[0]} = 4'h2; // Correct data valid window for "early write" assign {pat0_rise0[3], pat0_rise0[2], pat0_rise0[1], pat0_rise0[0]} = 4'h7; assign {pat0_fall0[3], pat0_fall0[2], pat0_fall0[1], pat0_fall0[0]} = 4'hE; assign {pat0_rise1[3], pat0_rise1[2], pat0_rise1[1], pat0_rise1[0]} = 4'hC; assign {pat0_fall1[3], pat0_fall1[2], pat0_fall1[1], pat0_fall1[0]} = 4'h9; assign {pat0_rise2[3], pat0_rise2[2], pat0_rise2[1], pat0_rise2[0]} = 4'h2; assign {pat0_fall2[3], pat0_fall2[2], pat0_fall2[1], pat0_fall2[0]} = 4'h4; assign {pat0_rise3[3], pat0_rise3[2], pat0_rise3[1], pat0_rise3[0]} = 4'hB; assign {pat0_fall3[3], pat0_fall3[2], pat0_fall3[1], pat0_fall3[0]} = 4'h1; // Correct data valid window for "on-time write" assign {pat1_rise0[3], pat1_rise0[2], pat1_rise0[1], pat1_rise0[0]} = 4'h9; assign {pat1_fall0[3], pat1_fall0[2], pat1_fall0[1], pat1_fall0[0]} = 4'h3; assign {pat1_rise1[3], pat1_rise1[2], pat1_rise1[1], pat1_rise1[0]} = 4'h7; assign {pat1_fall1[3], pat1_fall1[2], pat1_fall1[1], pat1_fall1[0]} = 4'hE; assign {pat1_rise2[3], pat1_rise2[2], pat1_rise2[1], pat1_rise2[0]} = 4'hC; assign {pat1_fall2[3], pat1_fall2[2], pat1_fall2[1], pat1_fall2[0]} = 4'h9; assign {pat1_rise3[3], pat1_rise3[2], pat1_rise3[1], pat1_rise3[0]} = 4'h2; assign {pat1_fall3[3], pat1_fall3[2], pat1_fall3[1], pat1_fall3[0]} = 4'h4; end else if (nCK_PER_CLK == 2) begin: gen_pat_div2 // Pattern for DQ IDELAY increment // Target pattern for "early write" assign idel_pat0_rise0[3] = 2'b01; assign idel_pat0_fall0[3] = 2'b00; assign idel_pat0_rise1[3] = 2'b10; assign idel_pat0_fall1[3] = 2'b11; assign idel_pat0_rise0[2] = 2'b00; assign idel_pat0_fall0[2] = 2'b10; assign idel_pat0_rise1[2] = 2'b11; assign idel_pat0_fall1[2] = 2'b10; assign idel_pat0_rise0[1] = 2'b00; assign idel_pat0_fall0[1] = 2'b11; assign idel_pat0_rise1[1] = 2'b10; assign idel_pat0_fall1[1] = 2'b01; assign idel_pat0_rise0[0] = 2'b11; assign idel_pat0_fall0[0] = 2'b10; assign idel_pat0_rise1[0] = 2'b00; assign idel_pat0_fall1[0] = 2'b01; // Target pattern for "on-time write" assign idel_pat1_rise0[3] = 2'b01; assign idel_pat1_fall0[3] = 2'b11; assign idel_pat1_rise1[3] = 2'b01; assign idel_pat1_fall1[3] = 2'b00; assign idel_pat1_rise0[2] = 2'b11; assign idel_pat1_fall0[2] = 2'b01; assign idel_pat1_rise1[2] = 2'b00; assign idel_pat1_fall1[2] = 2'b10; assign idel_pat1_rise0[1] = 2'b01; assign idel_pat1_fall0[1] = 2'b00; assign idel_pat1_rise1[1] = 2'b10; assign idel_pat1_fall1[1] = 2'b11; assign idel_pat1_rise0[0] = 2'b00; assign idel_pat1_fall0[0] = 2'b10; assign idel_pat1_rise1[0] = 2'b11; assign idel_pat1_fall1[0] = 2'b10; // Correct data valid window for "early write" assign pat0_rise0[3] = 2'b00; assign pat0_fall0[3] = 2'b10; assign pat0_rise1[3] = 2'b11; assign pat0_fall1[3] = 2'b10; assign pat0_rise0[2] = 2'b10; assign pat0_fall0[2] = 2'b11; assign pat0_rise1[2] = 2'b10; assign pat0_fall1[2] = 2'b00; assign pat0_rise0[1] = 2'b11; assign pat0_fall0[1] = 2'b10; assign pat0_rise1[1] = 2'b01; assign pat0_fall1[1] = 2'b00; assign pat0_rise0[0] = 2'b10; assign pat0_fall0[0] = 2'b00; assign pat0_rise1[0] = 2'b01; assign pat0_fall1[0] = 2'b11; // Correct data valid window for "on-time write" assign pat1_rise0[3] = 2'b11; assign pat1_fall0[3] = 2'b01; assign pat1_rise1[3] = 2'b00; assign pat1_fall1[3] = 2'b10; assign pat1_rise0[2] = 2'b01; assign pat1_fall0[2] = 2'b00; assign pat1_rise1[2] = 2'b10; assign pat1_fall1[2] = 2'b11; assign pat1_rise0[1] = 2'b00; assign pat1_fall0[1] = 2'b10; assign pat1_rise1[1] = 2'b11; assign pat1_fall1[1] = 2'b10; assign pat1_rise0[0] = 2'b10; assign pat1_fall0[0] = 2'b11; assign pat1_rise1[0] = 2'b10; assign pat1_fall1[0] = 2'b00; end endgenerate // Each bit of each byte is compared to expected pattern. // This was done to prevent (and "drastically decrease") the chance that // invalid data clocked in when the DQ bus is tri-state (along with a // combination of the correct data) will resemble the expected data // pattern. A better fix for this is to change the training pattern and/or // make the pattern longer. generate genvar pt_i; if (nCK_PER_CLK == 4) begin: gen_pat_match_div4 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match // DQ IDELAY pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4]) idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4]) idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4]) idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4]) idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == idel_pat0_rise2[pt_i%4]) idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == idel_pat0_fall2[pt_i%4]) idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == idel_pat0_rise3[pt_i%4]) idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == idel_pat0_fall3[pt_i%4]) idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4]) idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4]) idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4]) idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4]) idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == idel_pat1_rise2[pt_i%4]) idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == idel_pat1_fall2[pt_i%4]) idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == idel_pat1_rise3[pt_i%4]) idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == idel_pat1_fall3[pt_i%4]) idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b0; end // DQS DVW pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4]) pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4]) pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat0_rise2[pt_i%4]) pat0_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat0_fall2[pt_i%4]) pat0_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat0_rise3[pt_i%4]) pat0_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat0_fall3[pt_i%4]) pat0_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat1_rise2[pt_i%4]) pat1_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat1_fall2[pt_i%4]) pat1_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat1_rise3[pt_i%4]) pat1_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat1_fall3[pt_i%4]) pat1_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall3_r[pt_i] <= #TCQ 1'b0; end end // Combine pattern match "subterms" for DQ-IDELAY stage always @(posedge clk) begin idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r; idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r; idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r; idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r; idel_pat0_match_rise2_and_r <= #TCQ &idel_pat0_match_rise2_r; idel_pat0_match_fall2_and_r <= #TCQ &idel_pat0_match_fall2_r; idel_pat0_match_rise3_and_r <= #TCQ &idel_pat0_match_rise3_r; idel_pat0_match_fall3_and_r <= #TCQ &idel_pat0_match_fall3_r; idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r && idel_pat0_match_fall0_and_r && idel_pat0_match_rise1_and_r && idel_pat0_match_fall1_and_r && idel_pat0_match_rise2_and_r && idel_pat0_match_fall2_and_r && idel_pat0_match_rise3_and_r && idel_pat0_match_fall3_and_r); end always @(posedge clk) begin idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r; idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r; idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r; idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r; idel_pat1_match_rise2_and_r <= #TCQ &idel_pat1_match_rise2_r; idel_pat1_match_fall2_and_r <= #TCQ &idel_pat1_match_fall2_r; idel_pat1_match_rise3_and_r <= #TCQ &idel_pat1_match_rise3_r; idel_pat1_match_fall3_and_r <= #TCQ &idel_pat1_match_fall3_r; idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r && idel_pat1_match_fall0_and_r && idel_pat1_match_rise1_and_r && idel_pat1_match_fall1_and_r && idel_pat1_match_rise2_and_r && idel_pat1_match_fall2_and_r && idel_pat1_match_rise3_and_r && idel_pat1_match_fall3_and_r); end always @(*) idel_pat_data_match <= #TCQ idel_pat0_data_match_r | idel_pat1_data_match_r; always @(posedge clk) idel_pat_data_match_r <= #TCQ idel_pat_data_match; // Combine pattern match "subterms" for DQS-PHASER_IN stage always @(posedge clk) begin pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r; pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r; pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r; pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r; pat0_match_rise2_and_r <= #TCQ &pat0_match_rise2_r; pat0_match_fall2_and_r <= #TCQ &pat0_match_fall2_r; pat0_match_rise3_and_r <= #TCQ &pat0_match_rise3_r; pat0_match_fall3_and_r <= #TCQ &pat0_match_fall3_r; pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r && pat0_match_fall0_and_r && pat0_match_rise1_and_r && pat0_match_fall1_and_r && pat0_match_rise2_and_r && pat0_match_fall2_and_r && pat0_match_rise3_and_r && pat0_match_fall3_and_r); end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_match_rise2_and_r <= #TCQ &pat1_match_rise2_r; pat1_match_fall2_and_r <= #TCQ &pat1_match_fall2_r; pat1_match_rise3_and_r <= #TCQ &pat1_match_rise3_r; pat1_match_fall3_and_r <= #TCQ &pat1_match_fall3_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r && pat1_match_rise2_and_r && pat1_match_fall2_and_r && pat1_match_rise3_and_r && pat1_match_fall3_and_r); end assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r; end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match // DQ IDELAY pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4]) idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4]) idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4]) idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4]) idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4]) idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4]) idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4]) idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4]) idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end // DQS DVW pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4]) pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4]) pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end end // Combine pattern match "subterms" for DQ-IDELAY stage always @(posedge clk) begin idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r; idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r; idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r; idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r; idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r && idel_pat0_match_fall0_and_r && idel_pat0_match_rise1_and_r && idel_pat0_match_fall1_and_r); end always @(posedge clk) begin idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r; idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r; idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r; idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r; idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r && idel_pat1_match_fall0_and_r && idel_pat1_match_rise1_and_r && idel_pat1_match_fall1_and_r); end always @(posedge clk) begin if (sr_valid_r2) idel_pat_data_match <= #TCQ idel_pat0_data_match_r | idel_pat1_data_match_r; end //assign idel_pat_data_match = idel_pat0_data_match_r | // idel_pat1_data_match_r; always @(posedge clk) idel_pat_data_match_r <= #TCQ idel_pat_data_match; // Combine pattern match "subterms" for DQS-PHASER_IN stage always @(posedge clk) begin pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r; pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r; pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r; pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r; pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r && pat0_match_fall0_and_r && pat0_match_rise1_and_r && pat0_match_fall1_and_r); end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r); end assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r; end endgenerate always @(posedge clk) begin rdlvl_stg1_start_r <= #TCQ rdlvl_stg1_start; mpr_rdlvl_done_r1 <= #TCQ mpr_rdlvl_done_r; mpr_rdlvl_done_r2 <= #TCQ mpr_rdlvl_done_r1; mpr_rdlvl_start_r <= #TCQ mpr_rdlvl_start; end //*************************************************************************** // First stage calibration: Capture clock //*************************************************************************** //***************************************************************** // Keep track of how many samples have been written to shift registers // Every time RD_SHIFT_LEN samples have been written, then we have a // full read training pattern loaded into the sr_* registers. Then assert // sr_valid_r to indicate that: (1) comparison between the sr_* and // old_sr_* and prev_sr_* registers can take place, (2) transfer of // the contents of sr_* to old_sr_* and prev_sr_* registers can also // take place //***************************************************************** // verilint STARC-2.2.3.3 off always @(posedge clk) if (rst || (mpr_rdlvl_done_r && ~rdlvl_stg1_start)) begin cnt_shift_r <= #TCQ 'b1; sr_valid_r <= #TCQ 1'b0; mpr_valid_r <= #TCQ 1'b0; end else begin if (mux_rd_valid_r && mpr_rdlvl_start && ~mpr_rdlvl_done_r) begin if (cnt_shift_r == 'b0) mpr_valid_r <= #TCQ 1'b1; else begin mpr_valid_r <= #TCQ 1'b0; cnt_shift_r <= #TCQ cnt_shift_r + 1; end end else mpr_valid_r <= #TCQ 1'b0; if (mux_rd_valid_r && rdlvl_stg1_start) begin if (cnt_shift_r == RD_SHIFT_LEN-1) begin sr_valid_r <= #TCQ 1'b1; cnt_shift_r <= #TCQ 'b0; end else begin sr_valid_r <= #TCQ 1'b0; cnt_shift_r <= #TCQ cnt_shift_r + 1; end end else // When the current mux_rd_* contents are not valid, then // retain the current value of cnt_shift_r, and make sure // that sr_valid_r = 0 to prevent any downstream loads or // comparisons sr_valid_r <= #TCQ 1'b0; end // verilint STARC-2.2.3.3 on //***************************************************************** // Logic to determine when either edge of the data eye encountered // Pre- and post-IDELAY update data pattern is compared, if they // differ, than an edge has been encountered. Currently no attempt // made to determine if the data pattern itself is "correct", only // whether it changes after incrementing the IDELAY (possible // future enhancement) //***************************************************************** // One-way control for ensuring that state machine request to store // current read data into OLD SR shift register only occurs on a // valid clock cycle. The FSM provides a one-cycle request pulse. // It is the responsibility of the FSM to wait the worst-case time // before relying on any downstream results of this load. always @(posedge clk) if (rst) store_sr_r <= #TCQ 1'b0; else begin if (store_sr_req_r) store_sr_r <= #TCQ 1'b1; else if ((sr_valid_r || mpr_valid_r) && store_sr_r) store_sr_r <= #TCQ 1'b0; end // Transfer current data to old data, prior to incrementing delay // Also store data from current sampling window - so that we can detect // if the current delay tap yields data that is "jittery" generate if (nCK_PER_CLK == 4) begin: gen_old_sr_div4 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr always @(posedge clk) begin if (sr_valid_r || mpr_valid_r) begin // Load last sample (i.e. from current sampling interval) prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; prev_sr_rise2_r[z] <= #TCQ sr_rise2_r[z]; prev_sr_fall2_r[z] <= #TCQ sr_fall2_r[z]; prev_sr_rise3_r[z] <= #TCQ sr_rise3_r[z]; prev_sr_fall3_r[z] <= #TCQ sr_fall3_r[z]; end if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; old_sr_rise2_r[z] <= #TCQ sr_rise2_r[z]; old_sr_fall2_r[z] <= #TCQ sr_fall2_r[z]; old_sr_rise3_r[z] <= #TCQ sr_rise3_r[z]; old_sr_fall3_r[z] <= #TCQ sr_fall3_r[z]; end end end end else if (nCK_PER_CLK == 2) begin: gen_old_sr_div2 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr always @(posedge clk) begin if (sr_valid_r || mpr_valid_r) begin prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; end if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; end end end end endgenerate //******************************************************* // Match determination occurs over 3 cycles - pipelined for better timing //******************************************************* // Match valid with # of cycles of pipelining in match determination always @(posedge clk) begin sr_valid_r1 <= #TCQ sr_valid_r; sr_valid_r2 <= #TCQ sr_valid_r1; mpr_valid_r1 <= #TCQ mpr_valid_r; mpr_valid_r2 <= #TCQ mpr_valid_r1; end generate if (nCK_PER_CLK == 4) begin: gen_sr_match_div4 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match always @(posedge clk) begin // CYCLE1: Compare all bits in DQS grp, generate separate term for // each bit over four bit times. For example, if there are 8-bits // per DQS group, 32 terms are generated on cycle 1 // NOTE: Structure HDL such that X on data bus will result in a // mismatch. This is required for memory models that can drive the // bus with X's to model uncertainty regions (e.g. Denali) if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z])) old_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z]; else old_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z])) old_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z]; else old_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z])) old_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z]; else old_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z])) old_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z]; else old_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == old_sr_rise2_r[z])) old_sr_match_rise2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise2_r[z] <= #TCQ old_sr_match_rise2_r[z]; else old_sr_match_rise2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == old_sr_fall2_r[z])) old_sr_match_fall2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall2_r[z] <= #TCQ old_sr_match_fall2_r[z]; else old_sr_match_fall2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == old_sr_rise3_r[z])) old_sr_match_rise3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise3_r[z] <= #TCQ old_sr_match_rise3_r[z]; else old_sr_match_rise3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == old_sr_fall3_r[z])) old_sr_match_fall3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall3_r[z] <= #TCQ old_sr_match_fall3_r[z]; else old_sr_match_fall3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z])) prev_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z]; else prev_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z])) prev_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z]; else prev_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z])) prev_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z]; else prev_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z])) prev_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z]; else prev_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == prev_sr_rise2_r[z])) prev_sr_match_rise2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise2_r[z] <= #TCQ prev_sr_match_rise2_r[z]; else prev_sr_match_rise2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == prev_sr_fall2_r[z])) prev_sr_match_fall2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall2_r[z] <= #TCQ prev_sr_match_fall2_r[z]; else prev_sr_match_fall2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == prev_sr_rise3_r[z])) prev_sr_match_rise3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise3_r[z] <= #TCQ prev_sr_match_rise3_r[z]; else prev_sr_match_rise3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == prev_sr_fall3_r[z])) prev_sr_match_fall3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall3_r[z] <= #TCQ prev_sr_match_fall3_r[z]; else prev_sr_match_fall3_r[z] <= #TCQ 1'b0; // CYCLE2: Combine all the comparisons for every 8 words (rise0, // fall0,rise1, fall1) in the calibration sequence. Now we're down // to DRAM_WIDTH terms old_sr_match_cyc2_r[z] <= #TCQ old_sr_match_rise0_r[z] & old_sr_match_fall0_r[z] & old_sr_match_rise1_r[z] & old_sr_match_fall1_r[z] & old_sr_match_rise2_r[z] & old_sr_match_fall2_r[z] & old_sr_match_rise3_r[z] & old_sr_match_fall3_r[z]; prev_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_rise0_r[z] & prev_sr_match_fall0_r[z] & prev_sr_match_rise1_r[z] & prev_sr_match_fall1_r[z] & prev_sr_match_rise2_r[z] & prev_sr_match_fall2_r[z] & prev_sr_match_rise3_r[z] & prev_sr_match_fall3_r[z]; // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen), // and qualify with pipelined valid signal) - probably don't need // a cycle just do do this.... if (sr_valid_r2 || mpr_valid_r2) begin old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z]; prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z]; end else begin old_sr_diff_r[z] <= #TCQ 'b0; prev_sr_diff_r[z] <= #TCQ 'b0; end end end end if (nCK_PER_CLK == 2) begin: gen_sr_match_div2 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match always @(posedge clk) begin if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z])) old_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z]; else old_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z])) old_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z]; else old_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z])) old_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z]; else old_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z])) old_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z]; else old_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z])) prev_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z]; else prev_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z])) prev_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z]; else prev_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z])) prev_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z]; else prev_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z])) prev_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z]; else prev_sr_match_fall1_r[z] <= #TCQ 1'b0; old_sr_match_cyc2_r[z] <= #TCQ old_sr_match_rise0_r[z] & old_sr_match_fall0_r[z] & old_sr_match_rise1_r[z] & old_sr_match_fall1_r[z]; prev_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_rise0_r[z] & prev_sr_match_fall0_r[z] & prev_sr_match_rise1_r[z] & prev_sr_match_fall1_r[z]; // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen), // and qualify with pipelined valid signal) - probably don't need // a cycle just do do this.... if (sr_valid_r2 || mpr_valid_r2) begin old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z]; prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z]; end else begin old_sr_diff_r[z] <= #TCQ 'b0; prev_sr_diff_r[z] <= #TCQ 'b0; end end end end endgenerate //*************************************************************************** // First stage calibration: DQS Capture //*************************************************************************** //******************************************************* // Counters for tracking # of samples compared // For each comparision point (i.e. to determine if an edge has // occurred after each IODELAY increment when read leveling), // multiple samples are compared in order to average out the effects // of jitter. If any one of these samples is different than the "old" // sample corresponding to the previous IODELAY value, then an edge // is declared to be detected. //******************************************************* // Two cascaded counters are used to keep track of # of samples compared, // in order to make it easier to meeting timing on these paths. Once // optimal sampling interval is determined, it may be possible to remove // the second counter always @(posedge clk) samp_edge_cnt0_en_r <= #TCQ (cal1_state_r == CAL1_PAT_DETECT) || (cal1_state_r == CAL1_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ); // First counter counts # of samples compared always @(posedge clk) if (rst) samp_edge_cnt0_r <= #TCQ 'b0; else begin if (!samp_edge_cnt0_en_r) // Reset sample counter when not in any of the "sampling" states samp_edge_cnt0_r <= #TCQ 'b0; else if (sr_valid_r2 || mpr_valid_r2) // Otherwise, count # of samples compared samp_edge_cnt0_r <= #TCQ samp_edge_cnt0_r + 1; end // Counter #2 enable generation always @(posedge clk) if (rst) samp_edge_cnt1_en_r <= #TCQ 1'b0; else begin // Assert pulse when correct number of samples compared if ((samp_edge_cnt0_r == DETECT_EDGE_SAMPLE_CNT0) && (sr_valid_r2 || mpr_valid_r2)) samp_edge_cnt1_en_r <= #TCQ 1'b1; else samp_edge_cnt1_en_r <= #TCQ 1'b0; end // Counter #2 always @(posedge clk) if (rst) samp_edge_cnt1_r <= #TCQ 'b0; else if (!samp_edge_cnt0_en_r) samp_edge_cnt1_r <= #TCQ 'b0; else if (samp_edge_cnt1_en_r) samp_edge_cnt1_r <= #TCQ samp_edge_cnt1_r + 1; always @(posedge clk) if (rst) samp_cnt_done_r <= #TCQ 1'b0; else begin if (!samp_edge_cnt0_en_r) samp_cnt_done_r <= #TCQ 'b0; else if ((SIM_CAL_OPTION == "FAST_CAL") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin if (samp_edge_cnt0_r == SR_VALID_DELAY-1) // For simulation only, stay in edge detection mode a minimum // amount of time - just enough for two data compares to finish samp_cnt_done_r <= #TCQ 1'b1; end else begin if (samp_edge_cnt1_r == DETECT_EDGE_SAMPLE_CNT1) samp_cnt_done_r <= #TCQ 1'b1; end end //***************************************************************** // Logic to keep track of (on per-bit basis): // 1. When a region of stability preceded by a known edge occurs // 2. If for the current tap, the read data jitters // 3. If an edge occured between the current and previous tap // 4. When the current edge detection/sampling interval can end // Essentially, these are a series of status bits - the stage 1 // calibration FSM monitors these to determine when an edge is // found. Additional information is provided to help the FSM // determine if a left or right edge has been found. //**************************************************************** assign pb_detect_edge_setup = (cal1_state_r == CAL1_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT); assign pb_detect_edge = (cal1_state_r == CAL1_PAT_DETECT) || (cal1_state_r == CAL1_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ); generate for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_track_left_edge always @(posedge clk) begin if (pb_detect_edge_setup) begin // Reset eye size, stable eye marker, and jitter marker before // starting new edge detection iteration pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_detect_edge_done_r[z] <= #TCQ 1'b0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_last_tap_jitter_r[z] <= #TCQ 1'b0; pb_found_edge_last_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b0; pb_found_first_edge_r[z] <= #TCQ 1'b0; end else if (pb_detect_edge) begin // Save information on which DQ bits are already out of the // data valid window - those DQ bits will later not have their // IDELAY tap value incremented pb_found_edge_last_r[z] <= #TCQ pb_found_edge_r[z]; if (!pb_detect_edge_done_r[z]) begin if (samp_cnt_done_r) begin // If we've reached end of sampling interval, no jitter on // current tap has been found (although an edge could have // been found between the current and previous taps), and // the sampling interval is complete. Increment the stable // eye counter if no edge found, and always clear the jitter // flag in preparation for the next tap. pb_last_tap_jitter_r[z] <= #TCQ 1'b0; pb_detect_edge_done_r[z] <= #TCQ 1'b1; if (!pb_found_edge_r[z] && !pb_last_tap_jitter_r[z]) begin // If the data was completely stable during this tap and // no edge was found between this and the previous tap // then increment the stable eye counter "as appropriate" if (pb_cnt_eye_size_r[z] != MIN_EYE_SIZE-1) pb_cnt_eye_size_r[z] <= #TCQ pb_cnt_eye_size_r[z] + 1; else //if (pb_found_first_edge_r[z]) // We've reached minimum stable eye width pb_found_stable_eye_r[z] <= #TCQ 1'b1; end else begin // Otherwise, an edge was found, either because of a // difference between this and the previous tap's read // data, and/or because the previous tap's data jittered // (but not the current tap's data), then just set the // edge found flag, and enable the stable eye counter pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b1; pb_detect_edge_done_r[z] <= #TCQ 1'b1; end end else if (prev_sr_diff_r[z]) begin // If we find that the current tap read data jitters, then // set edge and jitter found flags, "enable" the eye size // counter, and stop sampling interval for this bit pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_last_tap_jitter_r[z] <= #TCQ 1'b1; pb_found_edge_r[z] <= #TCQ 1'b1; pb_found_first_edge_r[z] <= #TCQ 1'b1; pb_detect_edge_done_r[z] <= #TCQ 1'b1; end else if (old_sr_diff_r[z] || pb_last_tap_jitter_r[z]) begin // If either an edge was found (i.e. difference between // current tap and previous tap read data), or the previous // tap exhibited jitter (which means by definition that the // current tap cannot match the previous tap because the // previous tap gave unstable data), then set the edge found // flag, and "enable" eye size counter. But do not stop // sampling interval - we still need to check if the current // tap exhibits jitter pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b1; pb_found_first_edge_r[z] <= #TCQ 1'b1; end end end else begin // Before every edge detection interval, reset "intra-tap" flags pb_found_edge_r[z] <= #TCQ 1'b0; pb_detect_edge_done_r[z] <= #TCQ 1'b0; end end end endgenerate // Combine the above per-bit status flags into combined terms when // performing deskew on the aggregate data window always @(posedge clk) begin detect_edge_done_r <= #TCQ &pb_detect_edge_done_r; found_edge_r <= #TCQ |pb_found_edge_r; found_edge_all_r <= #TCQ &pb_found_edge_r; found_stable_eye_r <= #TCQ &pb_found_stable_eye_r; end // last IODELAY "stable eye" indicator is updated only after // detect_edge_done_r is asserted - so that when we do find the "right edge" // of the data valid window, found_edge_r = 1, AND found_stable_eye_r = 1 // when detect_edge_done_r = 1 (otherwise, if found_stable_eye_r updates // immediately, then it never possible to have found_stable_eye_r = 1 // when we detect an edge - and we'll never know whether we've found // a "right edge") always @(posedge clk) if (pb_detect_edge_setup) found_stable_eye_last_r <= #TCQ 1'b0; else if (detect_edge_done_r) found_stable_eye_last_r <= #TCQ found_stable_eye_r; //***************************************************************** // Keep track of DQ IDELAYE2 taps used //***************************************************************** // Added additional register stage to improve timing always @(posedge clk) if (rst) idelay_tap_cnt_slice_r <= 5'h0; else idelay_tap_cnt_slice_r <= idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]; always @(posedge clk) if (rst || (SIM_CAL_OPTION == "SKIP_CAL")) begin //|| new_cnt_cpt_r for (s = 0; s < RANKS; s = s + 1) begin for (t = 0; t < DQS_WIDTH; t = t + 1) begin idelay_tap_cnt_r[s][t] <= #TCQ idelaye2_init_val; end end end else if (SIM_CAL_OPTION == "FAST_CAL") begin for (u = 0; u < RANKS; u = u + 1) begin for (w = 0; w < DQS_WIDTH; w = w + 1) begin if (cal1_dq_idel_ce) begin if (cal1_dq_idel_inc) idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] + 1; else idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] - 1; end end end end else if ((rnk_cnt_r == RANKS-1) && (RANKS == 2) && rdlvl_rank_done_r && (cal1_state_r == CAL1_IDLE)) begin for (f = 0; f < DQS_WIDTH; f = f + 1) begin idelay_tap_cnt_r[rnk_cnt_r][f] <= #TCQ idelay_tap_cnt_r[(rnk_cnt_r-1)][f]; end end else if (cal1_dq_idel_ce) begin if (cal1_dq_idel_inc) idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r + 5'h1; else idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r - 5'h1; end else if (idelay_ld) idelay_tap_cnt_r[0][wrcal_cnt] <= #TCQ 5'b00000; always @(posedge clk) if (rst || new_cnt_cpt_r) idelay_tap_limit_r <= #TCQ 1'b0; else if (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_r] == 'd31) idelay_tap_limit_r <= #TCQ 1'b1; //***************************************************************** // keep track of edge tap counts found, and current capture clock // tap count //***************************************************************** always @(posedge clk) if (rst || new_cnt_cpt_r || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) tap_cnt_cpt_r <= #TCQ 'b0; else if (cal1_dlyce_cpt_r) begin if (cal1_dlyinc_cpt_r) tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r + 1; else if (tap_cnt_cpt_r != 'd0) tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r - 1; end always @(posedge clk) if (rst || new_cnt_cpt_r || (cal1_state_r1 == CAL1_DQ_IDEL_TAP_INC) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) tap_limit_cpt_r <= #TCQ 1'b0; else if (tap_cnt_cpt_r == 6'd63) tap_limit_cpt_r <= #TCQ 1'b1; always @(posedge clk) cal1_cnt_cpt_timing_r <= #TCQ cal1_cnt_cpt_r; assign cal1_cnt_cpt_timing = {2'b00, cal1_cnt_cpt_r}; // Storing DQS tap values at the end of each DQS read leveling always @(posedge clk) begin if (rst) begin for (a = 0; a < RANKS; a = a + 1) begin: rst_rdlvl_dqs_tap_count_loop for (b = 0; b < DQS_WIDTH; b = b + 1) rdlvl_dqs_tap_cnt_r[a][b] <= #TCQ 'b0; end end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_NEXT_DQS)) begin for (p = 0; p < RANKS; p = p +1) begin: rdlvl_dqs_tap_rank_cnt for(q = 0; q < DQS_WIDTH; q = q +1) begin: rdlvl_dqs_tap_cnt rdlvl_dqs_tap_cnt_r[p][q] <= #TCQ tap_cnt_cpt_r; end end end else if (SIM_CAL_OPTION == "SKIP_CAL") begin for (j = 0; j < RANKS; j = j +1) begin: rdlvl_dqs_tap_rnk_cnt for(i = 0; i < DQS_WIDTH; i = i +1) begin: rdlvl_dqs_cnt rdlvl_dqs_tap_cnt_r[j][i] <= #TCQ 6'd31; end end end else if (cal1_state_r1 == CAL1_NEXT_DQS) begin rdlvl_dqs_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing_r] <= #TCQ tap_cnt_cpt_r; end end // Counter to track maximum DQ IODELAY tap usage during the per-bit // deskew portion of stage 1 calibration always @(posedge clk) if (rst) begin idel_tap_cnt_dq_pb_r <= #TCQ 'b0; idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end else if (new_cnt_cpt_r) begin idel_tap_cnt_dq_pb_r <= #TCQ 'b0; idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end else if (|cal1_dlyce_dq_r) begin if (cal1_dlyinc_dq_r) idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r + 1; else idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r - 1; if (idel_tap_cnt_dq_pb_r == 31) idel_tap_limit_dq_pb_r <= #TCQ 1'b1; else idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end //***************************************************************** always @(posedge clk) cal1_state_r1 <= #TCQ cal1_state_r; always @(posedge clk) if (rst) begin cal1_cnt_cpt_r <= #TCQ 'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_IDLE; cnt_idel_dec_cpt_r <= #TCQ 6'bxxxxxx; found_first_edge_r <= #TCQ 1'b0; found_second_edge_r <= #TCQ 1'b0; right_edge_taps_r <= #TCQ 6'bxxxxxx; first_edge_taps_r <= #TCQ 6'bxxxxxx; new_cnt_cpt_r <= #TCQ 1'b0; rdlvl_stg1_done <= #TCQ 1'b0; rdlvl_stg1_err <= #TCQ 1'b0; second_edge_taps_r <= #TCQ 6'bxxxxxx; store_sr_req_pulsed_r <= #TCQ 1'b0; store_sr_req_r <= #TCQ 1'b0; rnk_cnt_r <= #TCQ 2'b00; rdlvl_rank_done_r <= #TCQ 1'b0; idel_dec_cnt <= #TCQ 'd0; rdlvl_last_byte_done <= #TCQ 1'b0; idel_pat_detect_valid_r <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; idel_adj_inc <= #TCQ 1'b0; if (OCAL_EN == "ON") mpr_rdlvl_done_r <= #TCQ 1'b0; else mpr_rdlvl_done_r <= #TCQ 1'b1; mpr_dec_cpt_r <= #TCQ 1'b0; end else begin // default (inactive) states for all "pulse" outputs // verilint STARC-2.2.3.3 off cal1_prech_req_r <= #TCQ 1'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; new_cnt_cpt_r <= #TCQ 1'b0; store_sr_req_pulsed_r <= #TCQ 1'b0; store_sr_req_r <= #TCQ 1'b0; case (cal1_state_r) CAL1_IDLE: begin rdlvl_rank_done_r <= #TCQ 1'b0; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; if (mpr_rdlvl_start && ~mpr_rdlvl_start_r) begin cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT; end else if (rdlvl_stg1_start && ~rdlvl_stg1_start_r) begin if (SIM_CAL_OPTION == "SKIP_CAL") cal1_state_r <= #TCQ CAL1_REGL_LOAD; else if (SIM_CAL_OPTION == "FAST_CAL") cal1_state_r <= #TCQ CAL1_NEXT_DQS; else begin new_cnt_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT; end end end CAL1_MPR_NEW_DQS_WAIT: begin cal1_prech_req_r <= #TCQ 1'b0; if (!cal1_wait_r && mpr_valid_r) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; end // Wait for the new DQS group to change // also gives time for the read data IN_FIFO to // output the updated data for the new DQS group CAL1_NEW_DQS_WAIT: begin rdlvl_rank_done_r <= #TCQ 1'b0; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; if (|pi_counter_read_val) begin //VK_REVIEW mpr_dec_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; cnt_idel_dec_cpt_r <= #TCQ pi_counter_read_val; end else if (!cal1_wait_r) begin //if (!cal1_wait_r) begin // Store "previous tap" read data. Technically there is no // "previous" read data, since we are starting a new DQS // group, so we'll never find an edge at tap 0 unless the // data is fluctuating/jittering store_sr_req_r <= #TCQ 1'b1; // If per-bit deskew is disabled, then skip the first // portion of stage 1 calibration if (PER_BIT_DESKEW == "OFF") cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; else if (PER_BIT_DESKEW == "ON") cal1_state_r <= #TCQ CAL1_PB_STORE_FIRST_WAIT; end end //***************************************************************** // Per-bit deskew states //***************************************************************** // Wait state following storage of initial read data CAL1_PB_STORE_FIRST_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE; // Look for an edge on all DQ bits in current DQS group CAL1_PB_DETECT_EDGE: if (detect_edge_done_r) begin if (found_stable_eye_r) begin // If we've found the left edge for all bits (or more precisely, // we've found the left edge, and then part of the stable // window thereafter), then proceed to positioning the CPT clock // right before the left margin cnt_idel_dec_cpt_r <= #TCQ MIN_EYE_SIZE + 1; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT; end else begin // If we've reached the end of the sampling time, and haven't // yet found the left margin of all the DQ bits, then: if (!tap_limit_cpt_r) begin // If we still have taps left to use, then store current value // of read data, increment the capture clock, and continue to // look for (left) edges store_sr_req_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_CPT; end else begin // If we ran out of taps moving the capture clock, and we // haven't finished edge detection, then reset the capture // clock taps to 0 (gradually, one tap at a time... // then exit the per-bit portion of the algorithm - // i.e. proceed to adjust the capture clock and DQ IODELAYs as cnt_idel_dec_cpt_r <= #TCQ 6'd63; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end end end // Increment delay for DQS CAL1_PB_INC_CPT: begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_CPT_WAIT; end // Wait for IODELAY for both capture and internal nodes within // ISERDES to settle, before checking again for an edge CAL1_PB_INC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE; end // We've found the left edges of the windows for all DQ bits // (actually, we found it MIN_EYE_SIZE taps ago) Decrement capture // clock IDELAY to position just outside left edge of data window CAL1_PB_DEC_CPT_LEFT: if (cnt_idel_dec_cpt_r == 6'b000000) cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT_WAIT; else begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; end CAL1_PB_DEC_CPT_LEFT_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ; // If there is skew between individual DQ bits, then after we've // positioned the CPT clock, we will be "in the window" for some // DQ bits ("early" DQ bits), and "out of the window" for others // ("late" DQ bits). Increase DQ taps until we are out of the // window for all DQ bits CAL1_PB_DETECT_EDGE_DQ: if (detect_edge_done_r) if (found_edge_all_r) begin // We're out of the window for all DQ bits in this DQS group // We're done with per-bit deskew for this group - now decr // capture clock IODELAY tap count back to 0, and proceed // with the rest of stage 1 calibration for this DQS group cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end else if (!idel_tap_limit_dq_pb_r) // If we still have DQ taps available for deskew, keep // incrementing IODELAY tap count for the appropriate DQ bits cal1_state_r <= #TCQ CAL1_PB_INC_DQ; else begin // Otherwise, stop immediately (we've done the best we can) // and proceed with rest of stage 1 calibration cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end CAL1_PB_INC_DQ: begin // Increment only those DQ for which an edge hasn't been found yet cal1_dlyce_dq_r <= #TCQ ~pb_found_edge_last_r; cal1_dlyinc_dq_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_DQ_WAIT; end CAL1_PB_INC_DQ_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ; // Decrement capture clock taps back to initial value CAL1_PB_DEC_CPT: if (cnt_idel_dec_cpt_r == 6'b000000) cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_WAIT; else begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; end // Wait for capture clock to settle, then proceed to rest of // state 1 calibration for this DQS group CAL1_PB_DEC_CPT_WAIT: if (!cal1_wait_r) begin store_sr_req_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; end // When first starting calibration for a DQS group, save the // current value of the read data shift register, and use this // as a reference. Note that for the first iteration of the // edge detection loop, we will in effect be checking for an edge // at IODELAY taps = 0 - normally, we are comparing the read data // for IODELAY taps = N, with the read data for IODELAY taps = N-1 // An edge can only be found at IODELAY taps = 0 if the read data // is changing during this time (possible due to jitter) CAL1_STORE_FIRST_WAIT: begin mpr_dec_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PAT_DETECT; end CAL1_VALID_WAIT: begin if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; end CAL1_MPR_PAT_DETECT: begin // MPR read leveling for centering DQS in valid window before // OCLKDELAYED calibration begins in order to eliminate read issues if (idel_pat_detect_valid_r == 1'b0) begin cal1_state_r <= #TCQ CAL1_VALID_WAIT; idel_pat_detect_valid_r <= #TCQ 1'b1; end else if (idel_pat_detect_valid_r && idel_mpr_pat_detect_r) begin cal1_state_r <= #TCQ CAL1_DETECT_EDGE; idel_dec_cnt <= #TCQ 'd0; end else if (!idelay_tap_limit_r) cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC; else cal1_state_r <= #TCQ CAL1_RDLVL_ERR; end CAL1_PAT_DETECT: begin // All DQ bits associated with a DQS are pushed to the right one IDELAY // tap at a time until first rising DQS is in the tri-state region // before first rising edge window. // The detect_edge_done_r condition included to support averaging // during IDELAY tap increments if (detect_edge_done_r) begin if (idel_pat_data_match) begin case (idelay_adj) 2'b01: begin cal1_state_r <= CAL1_DQ_IDEL_TAP_INC; idel_dec_cnt <= #TCQ 1'b0; idel_adj_inc <= #TCQ 1'b1; end 2'b10: begin //DEC by 1 cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC ; idel_dec_cnt <= #TCQ 1'b1; idel_adj_inc <= #TCQ 1'b0; end default: begin cal1_state_r <= #TCQ CAL1_DETECT_EDGE; idel_dec_cnt <= #TCQ 1'b0; idel_adj_inc <= #TCQ 1'b0; end endcase end else if (!idelay_tap_limit_r) begin cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC; end else begin cal1_state_r <= #TCQ CAL1_RDLVL_ERR; end end end // Increment IDELAY tap by 1 for DQ bits in the byte being calibrated // until left edge of valid window detected CAL1_DQ_IDEL_TAP_INC: begin cal1_dq_idel_ce <= #TCQ 1'b1; cal1_dq_idel_inc <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC_WAIT; idel_pat_detect_valid_r <= #TCQ 1'b0; end CAL1_DQ_IDEL_TAP_INC_WAIT: begin cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; if (!cal1_wait_r) begin idel_adj_inc <= #TCQ 1'b0; if (idel_adj_inc) cal1_state_r <= #TCQ CAL1_DETECT_EDGE; else if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3")) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; else cal1_state_r <= #TCQ CAL1_PAT_DETECT; end end // Decrement by 2 IDELAY taps once idel_pat_data_match detected CAL1_DQ_IDEL_TAP_DEC: begin cal1_dq_idel_inc <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC_WAIT; if (idel_dec_cnt >= 'd0) cal1_dq_idel_ce <= #TCQ 1'b1; else cal1_dq_idel_ce <= #TCQ 1'b0; if (idel_dec_cnt > 'd0) idel_dec_cnt <= #TCQ idel_dec_cnt - 1; else idel_dec_cnt <= #TCQ idel_dec_cnt; end CAL1_DQ_IDEL_TAP_DEC_WAIT: begin cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; if (!cal1_wait_r) begin if ((idel_dec_cnt > 'd0) || (pi_rdval_cnt > 'd0)) cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC; else if (mpr_dec_cpt_r) cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; else cal1_state_r <= #TCQ CAL1_DETECT_EDGE; end end // Check for presence of data eye edge. During this state, we // sample the read data multiple times, and look for changes // in the read data, specifically: // 1. A change in the read data compared with the value of // read data from the previous delay tap. This indicates // that the most recent tap delay increment has moved us // into either a new window, or moved/kept us in the // transition/jitter region between windows. Note that this // condition only needs to be checked for once, and for // logistical purposes, we check this soon after entering // this state (see comment in CAL1_DETECT_EDGE below for // why this is done) // 2. A change in the read data while we are in this state // (i.e. in the absence of a tap delay increment). This // indicates that we're close enough to a window edge that // jitter will cause the read data to change even in the // absence of a tap delay change CAL1_DETECT_EDGE: begin // Essentially wait for the first comparision to finish, then // store current data into "old" data register. This store // happens now, rather than later (e.g. when we've have already // left this state) in order to avoid the situation the data that // is stored as "old" data has not been used in an "active // comparison" - i.e. data is stored after the last comparison // of this state. In this case, we can miss an edge if the // following sequence occurs: // 1. Comparison completes in this state - no edge found // 2. "Momentary jitter" occurs which "pushes" the data out the // equivalent of one delay tap // 3. We store this jittered data as the "old" data // 4. "Jitter" no longer present // 5. We increment the delay tap by one // 6. Now we compare the current with the "old" data - they're // the same, and no edge is detected // NOTE: Given the large # of comparisons done in this state, it's // highly unlikely the above sequence will occur in actual H/W // Wait for the first load of read data into the comparison // shift register to finish, then load the current read data // into the "old" data register. This allows us to do one // initial comparision between the current read data, and // stored data corresponding to the previous delay tap idel_pat_detect_valid_r <= #TCQ 1'b0; if (!store_sr_req_pulsed_r) begin // Pulse store_sr_req_r only once in this state store_sr_req_r <= #TCQ 1'b1; store_sr_req_pulsed_r <= #TCQ 1'b1; end else begin store_sr_req_r <= #TCQ 1'b0; store_sr_req_pulsed_r <= #TCQ 1'b1; end // Continue to sample read data and look for edges until the // appropriate time interval (shorter for simulation-only, // much, much longer for actual h/w) has elapsed if (detect_edge_done_r) begin if (tap_limit_cpt_r) // Only one edge detected and ran out of taps since only one // bit time worth of taps available for window detection. This // can happen if at tap 0 DQS is in previous window which results // in only left edge being detected. Or at tap 0 DQS is in the // current window resulting in only right edge being detected. // Depending on the frequency this case can also happen if at // tap 0 DQS is in the left noise region resulting in only left // edge being detected. cal1_state_r <= #TCQ CAL1_CALC_IDEL; else if (found_edge_r) begin // Sticky bit - asserted after we encounter an edge, although // the current edge may not be considered the "first edge" this // just means we found at least one edge found_first_edge_r <= #TCQ 1'b1; // Only the right edge of the data valid window is found // Record the inner right edge tap value if (!found_first_edge_r && found_stable_eye_last_r) begin if (tap_cnt_cpt_r == 'd0) right_edge_taps_r <= #TCQ 'd0; else right_edge_taps_r <= #TCQ tap_cnt_cpt_r; end // Both edges of data valid window found: // If we've found a second edge after a region of stability // then we must have just passed the second ("right" edge of // the window. Record this second_edge_taps = current tap-1, // because we're one past the actual second edge tap, where // the edge taps represent the extremes of the data valid // window (i.e. smallest & largest taps where data still valid if (found_first_edge_r && found_stable_eye_last_r) begin found_second_edge_r <= #TCQ 1'b1; second_edge_taps_r <= #TCQ tap_cnt_cpt_r - 1; cal1_state_r <= #TCQ CAL1_CALC_IDEL; end else begin // Otherwise, an edge was found (just not the "second" edge) // Assuming DQS is in the correct window at tap 0 of Phaser IN // fine tap. The first edge found is the right edge of the valid // window and is the beginning of the jitter region hence done! first_edge_taps_r <= #TCQ tap_cnt_cpt_r; cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT; end end else // Otherwise, if we haven't found an edge.... // If we still have taps left to use, then keep incrementing cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT; end end // Increment Phaser_IN delay for DQS CAL1_IDEL_INC_CPT: begin cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT_WAIT; if (~tap_limit_cpt_r) begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b1; end else begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; end end // Wait for Phaser_In to settle, before checking again for an edge CAL1_IDEL_INC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_DETECT_EDGE; end // Calculate final value of Phaser_IN taps. At this point, one or both // edges of data eye have been found, and/or all taps have been // exhausted looking for the edges // NOTE: We're calculating the amount to decrement by, not the // absolute setting for DQS. CAL1_CALC_IDEL: begin // CASE1: If 2 edges found. if (found_second_edge_r) cnt_idel_dec_cpt_r <= #TCQ ((second_edge_taps_r - first_edge_taps_r)>>1) + 1; else if (right_edge_taps_r > 6'd0) // Only right edge detected // right_edge_taps_r is the inner right edge tap value // hence used for calculation cnt_idel_dec_cpt_r <= #TCQ (tap_cnt_cpt_r - (right_edge_taps_r>>1)); else if (found_first_edge_r) // Only left edge detected cnt_idel_dec_cpt_r <= #TCQ ((tap_cnt_cpt_r - first_edge_taps_r)>>1); else cnt_idel_dec_cpt_r <= #TCQ (tap_cnt_cpt_r>>1); // Now use the value we just calculated to decrement CPT taps // to the desired calibration point cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; end // decrement capture clock for final adjustment - center // capture clock in middle of data eye. This adjustment will occur // only when both the edges are found usign CPT taps. Must do this // incrementally to avoid clock glitching (since CPT drives clock // divider within each ISERDES) CAL1_IDEL_DEC_CPT: begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; // once adjustment is complete, we're done with calibration for // this DQS, repeat for next DQS cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; if (cnt_idel_dec_cpt_r == 6'b000001) begin if (mpr_dec_cpt_r) begin if (|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) begin idel_dec_cnt <= #TCQ idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC; end else cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; end else cal1_state_r <= #TCQ CAL1_NEXT_DQS; end else cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT_WAIT; end CAL1_IDEL_DEC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; end // Determine whether we're done, or have more DQS's to calibrate // Also request precharge after every byte, as appropriate CAL1_NEXT_DQS: begin //if (mpr_rdlvl_done_r || (DRAM_TYPE == "DDR2")) cal1_prech_req_r <= #TCQ 1'b1; //else // cal1_prech_req_r <= #TCQ 1'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; // Prepare for another iteration with next DQS group found_first_edge_r <= #TCQ 1'b0; found_second_edge_r <= #TCQ 1'b0; first_edge_taps_r <= #TCQ 'd0; second_edge_taps_r <= #TCQ 'd0; if ((SIM_CAL_OPTION == "FAST_CAL") || (cal1_cnt_cpt_r >= DQS_WIDTH-1)) begin if (mpr_rdlvl_done_r) begin rdlvl_last_byte_done <= #TCQ 1'b1; mpr_last_byte_done <= #TCQ 1'b0; end else begin rdlvl_last_byte_done <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b1; end end // Wait until precharge that occurs in between calibration of // DQS groups is finished if (prech_done) begin // || (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))) begin if (SIM_CAL_OPTION == "FAST_CAL") begin //rdlvl_rank_done_r <= #TCQ 1'b1; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_DONE; //CAL1_REGL_LOAD; end else if (cal1_cnt_cpt_r >= DQS_WIDTH-1) begin if (~mpr_rdlvl_done_r) begin mpr_rank_done_r <= #TCQ 1'b1; // if (rnk_cnt_r == RANKS-1) begin // All DQS groups in all ranks done cal1_state_r <= #TCQ CAL1_DONE; cal1_cnt_cpt_r <= #TCQ 'b0; // end else begin // // Process DQS groups in next rank // rnk_cnt_r <= #TCQ rnk_cnt_r + 1; // new_cnt_cpt_r <= #TCQ 1'b1; // cal1_cnt_cpt_r <= #TCQ 'b0; // cal1_state_r <= #TCQ CAL1_IDLE; // end end else begin // All DQS groups in a rank done rdlvl_rank_done_r <= #TCQ 1'b1; if (rnk_cnt_r == RANKS-1) begin // All DQS groups in all ranks done cal1_state_r <= #TCQ CAL1_REGL_LOAD; end else begin // Process DQS groups in next rank rnk_cnt_r <= #TCQ rnk_cnt_r + 1; new_cnt_cpt_r <= #TCQ 1'b1; cal1_cnt_cpt_r <= #TCQ 'b0; cal1_state_r <= #TCQ CAL1_IDLE; end end end else begin // Process next DQS group new_cnt_cpt_r <= #TCQ 1'b1; cal1_cnt_cpt_r <= #TCQ cal1_cnt_cpt_r + 1; cal1_state_r <= #TCQ CAL1_NEW_DQS_PREWAIT; end end end CAL1_NEW_DQS_PREWAIT: begin if (!cal1_wait_r) begin if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3")) cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT; else cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT; end end // Load rank registers in Phaser_IN CAL1_REGL_LOAD: begin rdlvl_rank_done_r <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; cal1_cnt_cpt_r <= #TCQ 'b0; rnk_cnt_r <= #TCQ 2'b00; if ((regl_rank_cnt == RANKS-1) && ((regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1))) begin cal1_state_r <= #TCQ CAL1_DONE; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; end else cal1_state_r <= #TCQ CAL1_REGL_LOAD; end CAL1_RDLVL_ERR: begin rdlvl_stg1_err <= #TCQ 1'b1; end // Done with this stage of calibration // if used, allow DEBUG_PORT to control taps CAL1_DONE: begin mpr_rdlvl_done_r <= #TCQ 1'b1; cal1_prech_req_r <= #TCQ 1'b0; if (~mpr_rdlvl_done_r && (OCAL_EN=="ON") && (DRAM_TYPE == "DDR3")) begin rdlvl_stg1_done <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_IDLE; end else rdlvl_stg1_done <= #TCQ 1'b1; end endcase end // verilint STARC-2.2.3.3 on endmodule
//***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_rdlvl.v // /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Read leveling Stage1 calibration logic // NOTES: // 1. Window detection with PRBS pattern. //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $ **$Date: 2011/06/24 14:49:00 $ **$Author: mgeorge $ **$Revision: 1.2 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_rdlvl.v,v $ ******************************************************************************/ `timescale 1ps/1ps (* use_dsp48 = "no" *) module mig_7series_v2_3_ddr_phy_rdlvl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter CLK_PERIOD = 3333, // Internal clock period (in ps) parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter RANKS = 1, // # of DRAM ranks parameter PER_BIT_DESKEW = "ON", // Enable per-bit DQ deskew parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps parameter DEBUG_PORT = "OFF", // Enable debug port parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" parameter OCAL_EN = "ON", parameter IDELAY_ADJ = "ON" ) ( input clk, input rst, // Calibration status, control signals input mpr_rdlvl_start, output mpr_rdlvl_done, output reg mpr_last_byte_done, output mpr_rnk_done, input rdlvl_stg1_start, output reg rdlvl_stg1_done /* synthesis syn_maxfan = 30 */, output rdlvl_stg1_rnk_done, output reg rdlvl_stg1_err, output mpr_rdlvl_err, output rdlvl_err, output reg rdlvl_prech_req, output reg rdlvl_last_byte_done, output reg rdlvl_assrt_common, input prech_done, input phy_if_empty, input [4:0] idelaye2_init_val, // Captured data in fabric clock domain input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Decrement initial Phaser_IN Fine tap delay input dqs_po_dec_done, input [5:0] pi_counter_read_val, // Stage 1 calibration outputs output reg pi_fine_dly_dec_done, output reg pi_en_stg2_f, output reg pi_stg2_f_incdec, output reg pi_stg2_load, output reg [5:0] pi_stg2_reg_l, output [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt, // To DQ IDELAY required to find left edge of // valid window output idelay_ce, output idelay_inc, input idelay_ld, input [DQS_CNT_WIDTH:0] wrcal_cnt, // Only output if Per-bit de-skew enabled output reg [5*RANKS*DQ_WIDTH-1:0] dlyval_dq, // Debug Port output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, input dbg_idel_up_all, input dbg_idel_down_all, input dbg_idel_up_cpt, input dbg_idel_down_cpt, input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, input dbg_sel_all_idel_cpt, output [255:0] dbg_phy_rdlvl ); // minimum time (in IDELAY taps) for which capture data must be stable for // algorithm to consider a valid data eye to be found. The read leveling // logic will ignore any window found smaller than this value. Limitations // on how small this number can be is determined by: (1) the algorithmic // limitation of how many taps wide the data eye can be (3 taps), and (2) // how wide regions of "instability" that occur around the edges of the // read valid window can be (i.e. need to be able to filter out "false" // windows that occur for a short # of taps around the edges of the true // data window, although with multi-sampling during read leveling, this is // not as much a concern) - the larger the value, the more protection // against "false" windows localparam MIN_EYE_SIZE = 16; // Length of calibration sequence (in # of words) localparam CAL_PAT_LEN = 8; // Read data shift register length localparam RD_SHIFT_LEN = CAL_PAT_LEN / (2*nCK_PER_CLK); // # of cycles required to perform read data shift register compare // This is defined as from the cycle the new data is loaded until // signal found_edge_r is valid localparam RD_SHIFT_COMP_DELAY = 5; // worst-case # of cycles to wait to ensure that both the SR and // PREV_SR shift registers have valid data, and that the comparison // of the two shift register values is valid. The "+1" at the end of // this equation is a fudge factor, I freely admit that localparam SR_VALID_DELAY = (2 * RD_SHIFT_LEN) + RD_SHIFT_COMP_DELAY + 1; // # of clock cycles to wait after changing tap value or read data MUX // to allow: (1) tap chain to settle, (2) for delayed input to propagate // thru ISERDES, (3) for the read data comparison logic to have time to // output the comparison of two consecutive samples of the settled read data // The minimum delay is 16 cycles, which should be good enough to handle all // three of the above conditions for the simulation-only case with a short // training pattern. For H/W (or for simulation with longer training // pattern), it will take longer to store and compare two consecutive // samples, and the value of this parameter will reflect that localparam PIPE_WAIT_CNT = (SR_VALID_DELAY < 8) ? 16 : (SR_VALID_DELAY + 8); // # of read data samples to examine when detecting whether an edge has // occured during stage 1 calibration. Width of local param must be // changed as appropriate. Note that there are two counters used, each // counter can be changed independently of the other - they are used in // cascade to create a larger counter localparam [11:0] DETECT_EDGE_SAMPLE_CNT0 = 12'h001; //12'hFFF; localparam [11:0] DETECT_EDGE_SAMPLE_CNT1 = 12'h001; // 12'h1FF Must be > 0 localparam [5:0] CAL1_IDLE = 6'h00; localparam [5:0] CAL1_NEW_DQS_WAIT = 6'h01; localparam [5:0] CAL1_STORE_FIRST_WAIT = 6'h02; localparam [5:0] CAL1_PAT_DETECT = 6'h03; localparam [5:0] CAL1_DQ_IDEL_TAP_INC = 6'h04; localparam [5:0] CAL1_DQ_IDEL_TAP_INC_WAIT = 6'h05; localparam [5:0] CAL1_DQ_IDEL_TAP_DEC = 6'h06; localparam [5:0] CAL1_DQ_IDEL_TAP_DEC_WAIT = 6'h07; localparam [5:0] CAL1_DETECT_EDGE = 6'h08; localparam [5:0] CAL1_IDEL_INC_CPT = 6'h09; localparam [5:0] CAL1_IDEL_INC_CPT_WAIT = 6'h0A; localparam [5:0] CAL1_CALC_IDEL = 6'h0B; localparam [5:0] CAL1_IDEL_DEC_CPT = 6'h0C; localparam [5:0] CAL1_IDEL_DEC_CPT_WAIT = 6'h0D; localparam [5:0] CAL1_NEXT_DQS = 6'h0E; localparam [5:0] CAL1_DONE = 6'h0F; localparam [5:0] CAL1_PB_STORE_FIRST_WAIT = 6'h10; localparam [5:0] CAL1_PB_DETECT_EDGE = 6'h11; localparam [5:0] CAL1_PB_INC_CPT = 6'h12; localparam [5:0] CAL1_PB_INC_CPT_WAIT = 6'h13; localparam [5:0] CAL1_PB_DEC_CPT_LEFT = 6'h14; localparam [5:0] CAL1_PB_DEC_CPT_LEFT_WAIT = 6'h15; localparam [5:0] CAL1_PB_DETECT_EDGE_DQ = 6'h16; localparam [5:0] CAL1_PB_INC_DQ = 6'h17; localparam [5:0] CAL1_PB_INC_DQ_WAIT = 6'h18; localparam [5:0] CAL1_PB_DEC_CPT = 6'h19; localparam [5:0] CAL1_PB_DEC_CPT_WAIT = 6'h1A; localparam [5:0] CAL1_REGL_LOAD = 6'h1B; localparam [5:0] CAL1_RDLVL_ERR = 6'h1C; localparam [5:0] CAL1_MPR_NEW_DQS_WAIT = 6'h1D; localparam [5:0] CAL1_VALID_WAIT = 6'h1E; localparam [5:0] CAL1_MPR_PAT_DETECT = 6'h1F; localparam [5:0] CAL1_NEW_DQS_PREWAIT = 6'h20; integer a; integer b; integer d; integer e; integer f; integer h; integer g; integer i; integer j; integer k; integer l; integer m; integer n; integer r; integer p; integer q; integer s; integer t; integer u; integer w; integer ce_i; integer ce_rnk_i; integer aa; integer bb; integer cc; integer dd; genvar x; genvar z; reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_r; wire [DQS_CNT_WIDTH+2:0]cal1_cnt_cpt_timing; reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_timing_r; reg cal1_dq_idel_ce; reg cal1_dq_idel_inc; reg cal1_dlyce_cpt_r; reg cal1_dlyinc_cpt_r; reg cal1_dlyce_dq_r; reg cal1_dlyinc_dq_r; reg cal1_wait_cnt_en_r; reg [4:0] cal1_wait_cnt_r; reg cal1_wait_r; reg [DQ_WIDTH-1:0] dlyce_dq_r; reg dlyinc_dq_r; reg [4:0] dlyval_dq_reg_r [0:RANKS-1][0:DQ_WIDTH-1]; reg cal1_prech_req_r; reg [5:0] cal1_state_r; reg [5:0] cal1_state_r1; reg [5:0] cnt_idel_dec_cpt_r; reg [3:0] cnt_shift_r; reg detect_edge_done_r; reg [5:0] right_edge_taps_r; reg [5:0] first_edge_taps_r; reg found_edge_r; reg found_first_edge_r; reg found_second_edge_r; reg found_stable_eye_r; reg found_stable_eye_last_r; reg found_edge_all_r; reg [5:0] tap_cnt_cpt_r; reg tap_limit_cpt_r; reg [4:0] idel_tap_cnt_dq_pb_r; reg idel_tap_limit_dq_pb_r; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r; reg mux_rd_valid_r; reg new_cnt_cpt_r; reg [RD_SHIFT_LEN-1:0] old_sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] old_sr_rise3_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] old_sr_match_fall0_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall1_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise0_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise1_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall2_r; reg [DRAM_WIDTH-1:0] old_sr_match_fall3_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise2_r; reg [DRAM_WIDTH-1:0] old_sr_match_rise3_r; reg [4:0] pb_cnt_eye_size_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] pb_detect_edge_done_r; reg [DRAM_WIDTH-1:0] pb_found_edge_last_r; reg [DRAM_WIDTH-1:0] pb_found_edge_r; reg [DRAM_WIDTH-1:0] pb_found_first_edge_r; reg [DRAM_WIDTH-1:0] pb_found_stable_eye_r; reg [DRAM_WIDTH-1:0] pb_last_tap_jitter_r; reg pi_en_stg2_f_timing; reg pi_stg2_f_incdec_timing; reg pi_stg2_load_timing; reg [5:0] pi_stg2_reg_l_timing; reg [DRAM_WIDTH-1:0] prev_sr_diff_r; reg [RD_SHIFT_LEN-1:0] prev_sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] prev_sr_rise3_r [DRAM_WIDTH-1:0]; reg [DRAM_WIDTH-1:0] prev_sr_match_cyc2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall0_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall1_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise0_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise1_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_fall3_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise2_r; reg [DRAM_WIDTH-1:0] prev_sr_match_rise3_r; wire [DQ_WIDTH-1:0] rd_data_rise0; wire [DQ_WIDTH-1:0] rd_data_fall0; wire [DQ_WIDTH-1:0] rd_data_rise1; wire [DQ_WIDTH-1:0] rd_data_fall1; wire [DQ_WIDTH-1:0] rd_data_rise2; wire [DQ_WIDTH-1:0] rd_data_fall2; wire [DQ_WIDTH-1:0] rd_data_rise3; wire [DQ_WIDTH-1:0] rd_data_fall3; reg samp_cnt_done_r; reg samp_edge_cnt0_en_r; reg [11:0] samp_edge_cnt0_r; reg samp_edge_cnt1_en_r; reg [11:0] samp_edge_cnt1_r; reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; reg [5:0] second_edge_taps_r; reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0]; reg store_sr_r; reg store_sr_req_pulsed_r; reg store_sr_req_r; reg sr_valid_r; reg sr_valid_r1; reg sr_valid_r2; reg [DRAM_WIDTH-1:0] old_sr_diff_r; reg [DRAM_WIDTH-1:0] old_sr_match_cyc2_r; reg pat0_data_match_r; reg pat1_data_match_r; wire pat_data_match_r; wire [RD_SHIFT_LEN-1:0] pat0_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall3 [3:0]; reg [DRAM_WIDTH-1:0] pat0_match_fall0_r; reg pat0_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall1_r; reg pat0_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall2_r; reg pat0_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat0_match_fall3_r; reg pat0_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise0_r; reg pat0_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise1_r; reg pat0_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise2_r; reg pat0_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat0_match_rise3_r; reg pat0_match_rise3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall0_r; reg pat1_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall1_r; reg pat1_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall2_r; reg pat1_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat1_match_fall3_r; reg pat1_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise0_r; reg pat1_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise1_r; reg pat1_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise2_r; reg pat1_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise3_r; reg pat1_match_rise3_and_r; reg [4:0] idelay_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1]; reg [5*DQS_WIDTH*RANKS-1:0] idelay_tap_cnt_w; reg [4:0] idelay_tap_cnt_slice_r; reg idelay_tap_limit_r; wire [RD_SHIFT_LEN-1:0] pat0_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat0_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat0_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] idel_pat1_fall3 [3:0]; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise0_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall0_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise1_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall1_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise2_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall2_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_rise3_r; reg [DRAM_WIDTH-1:0] idel_pat0_match_fall3_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise0_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall0_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise1_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall1_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise2_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall2_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_rise3_r; reg [DRAM_WIDTH-1:0] idel_pat1_match_fall3_r; reg idel_pat0_match_rise0_and_r; reg idel_pat0_match_fall0_and_r; reg idel_pat0_match_rise1_and_r; reg idel_pat0_match_fall1_and_r; reg idel_pat0_match_rise2_and_r; reg idel_pat0_match_fall2_and_r; reg idel_pat0_match_rise3_and_r; reg idel_pat0_match_fall3_and_r; reg idel_pat1_match_rise0_and_r; reg idel_pat1_match_fall0_and_r; reg idel_pat1_match_rise1_and_r; reg idel_pat1_match_fall1_and_r; reg idel_pat1_match_rise2_and_r; reg idel_pat1_match_fall2_and_r; reg idel_pat1_match_rise3_and_r; reg idel_pat1_match_fall3_and_r; reg idel_pat0_data_match_r; reg idel_pat1_data_match_r; reg idel_pat_data_match; reg idel_pat_data_match_r; reg [4:0] idel_dec_cnt; reg [5:0] rdlvl_dqs_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1]; reg [1:0] rnk_cnt_r; reg rdlvl_rank_done_r; reg [3:0] done_cnt; reg [1:0] regl_rank_cnt; reg [DQS_CNT_WIDTH:0] regl_dqs_cnt; reg [DQS_CNT_WIDTH:0] regl_dqs_cnt_r; wire [DQS_CNT_WIDTH+2:0]regl_dqs_cnt_timing; reg regl_rank_done_r; reg rdlvl_stg1_start_r; reg dqs_po_dec_done_r1; reg dqs_po_dec_done_r2; reg fine_dly_dec_done_r1; reg fine_dly_dec_done_r2; reg [3:0] wait_cnt_r; reg [5:0] pi_rdval_cnt; reg pi_cnt_dec; reg mpr_valid_r; reg mpr_valid_r1; reg mpr_valid_r2; reg mpr_rd_rise0_prev_r; reg mpr_rd_fall0_prev_r; reg mpr_rd_rise1_prev_r; reg mpr_rd_fall1_prev_r; reg mpr_rd_rise2_prev_r; reg mpr_rd_fall2_prev_r; reg mpr_rd_rise3_prev_r; reg mpr_rd_fall3_prev_r; reg mpr_rdlvl_done_r; reg mpr_rdlvl_done_r1; reg mpr_rdlvl_done_r2; reg mpr_rdlvl_start_r; reg mpr_rank_done_r; reg [2:0] stable_idel_cnt; reg inhibit_edge_detect_r; reg idel_pat_detect_valid_r; reg idel_mpr_pat_detect_r; reg mpr_pat_detect_r; reg mpr_dec_cpt_r; reg idel_adj_inc; //IDELAY adjustment wire [1:0] idelay_adj; wire pb_detect_edge_setup; wire pb_detect_edge; // Debug reg [6*DQS_WIDTH-1:0] dbg_cpt_first_edge_taps; reg [6*DQS_WIDTH-1:0] dbg_cpt_second_edge_taps; reg [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt_w; //IDELAY adjustment setting for -1 //2'b10 : IDELAY - 1 //2'b01 : IDELAY + 1 //2'b00 : No IDELAY adjustment assign idelay_adj = (IDELAY_ADJ == "ON") ? 2'b10: 2'b00; //*************************************************************************** // Debug //*************************************************************************** always @(*) begin for (d = 0; d < RANKS; d = d + 1) begin for (e = 0; e < DQS_WIDTH; e = e + 1) begin idelay_tap_cnt_w[(5*e+5*DQS_WIDTH*d)+:5] = idelay_tap_cnt_r[d][e]; dbg_cpt_tap_cnt_w[(6*e+6*DQS_WIDTH*d)+:6] = rdlvl_dqs_tap_cnt_r[d][e]; end end end assign mpr_rdlvl_err = rdlvl_stg1_err & (!mpr_rdlvl_done); assign rdlvl_err = rdlvl_stg1_err & (mpr_rdlvl_done); assign dbg_phy_rdlvl[0] = rdlvl_stg1_start; assign dbg_phy_rdlvl[1] = pat_data_match_r; assign dbg_phy_rdlvl[2] = mux_rd_valid_r; assign dbg_phy_rdlvl[3] = idelay_tap_limit_r; assign dbg_phy_rdlvl[8:4] = 'b0; assign dbg_phy_rdlvl[14:9] = cal1_state_r[5:0]; assign dbg_phy_rdlvl[20:15] = cnt_idel_dec_cpt_r; assign dbg_phy_rdlvl[21] = found_first_edge_r; assign dbg_phy_rdlvl[22] = found_second_edge_r; assign dbg_phy_rdlvl[23] = found_edge_r; assign dbg_phy_rdlvl[24] = store_sr_r; // [40:25] previously used for sr, old_sr shift registers. If connecting // these signals again, don't forget to parameterize based on RD_SHIFT_LEN assign dbg_phy_rdlvl[40:25] = 'b0; assign dbg_phy_rdlvl[41] = sr_valid_r; assign dbg_phy_rdlvl[42] = found_stable_eye_r; assign dbg_phy_rdlvl[48:43] = tap_cnt_cpt_r; assign dbg_phy_rdlvl[54:49] = first_edge_taps_r; assign dbg_phy_rdlvl[60:55] = second_edge_taps_r; assign dbg_phy_rdlvl[64:61] = cal1_cnt_cpt_timing_r; assign dbg_phy_rdlvl[65] = cal1_dlyce_cpt_r; assign dbg_phy_rdlvl[66] = cal1_dlyinc_cpt_r; assign dbg_phy_rdlvl[67] = found_edge_r; assign dbg_phy_rdlvl[68] = found_first_edge_r; assign dbg_phy_rdlvl[73:69] = 'b0; assign dbg_phy_rdlvl[74] = idel_pat_data_match; assign dbg_phy_rdlvl[75] = idel_pat0_data_match_r; assign dbg_phy_rdlvl[76] = idel_pat1_data_match_r; assign dbg_phy_rdlvl[77] = pat0_data_match_r; assign dbg_phy_rdlvl[78] = pat1_data_match_r; assign dbg_phy_rdlvl[79+:5*DQS_WIDTH*RANKS] = idelay_tap_cnt_w; assign dbg_phy_rdlvl[170+:8] = mux_rd_rise0_r; assign dbg_phy_rdlvl[178+:8] = mux_rd_fall0_r; assign dbg_phy_rdlvl[186+:8] = mux_rd_rise1_r; assign dbg_phy_rdlvl[194+:8] = mux_rd_fall1_r; assign dbg_phy_rdlvl[202+:8] = mux_rd_rise2_r; assign dbg_phy_rdlvl[210+:8] = mux_rd_fall2_r; assign dbg_phy_rdlvl[218+:8] = mux_rd_rise3_r; assign dbg_phy_rdlvl[226+:8] = mux_rd_fall3_r; //*************************************************************************** // Debug output //*************************************************************************** // CPT taps assign dbg_cpt_first_edge_cnt = dbg_cpt_first_edge_taps; assign dbg_cpt_second_edge_cnt = dbg_cpt_second_edge_taps; assign dbg_cpt_tap_cnt = dbg_cpt_tap_cnt_w; assign dbg_dq_idelay_tap_cnt = idelay_tap_cnt_w; // Record first and second edges found during CPT calibration generate always @(posedge clk) if (rst) begin dbg_cpt_first_edge_taps <= #TCQ 'b0; dbg_cpt_second_edge_taps <= #TCQ 'b0; end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_CALC_IDEL)) begin //for (ce_rnk_i = 0; ce_rnk_i < RANKS; ce_rnk_i = ce_rnk_i + 1) begin: gen_dbg_cpt_rnk for (ce_i = 0; ce_i < DQS_WIDTH; ce_i = ce_i + 1) begin: gen_dbg_cpt_edge if (found_first_edge_r) dbg_cpt_first_edge_taps[(6*ce_i)+:6] <= #TCQ first_edge_taps_r; if (found_second_edge_r) dbg_cpt_second_edge_taps[(6*ce_i)+:6] <= #TCQ second_edge_taps_r; end //end end else if (cal1_state_r == CAL1_CALC_IDEL) begin // Record tap counts of first and second edge edges during // CPT calibration for each DQS group. If neither edge has // been found, then those taps will remain 0 if (found_first_edge_r) dbg_cpt_first_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6] <= #TCQ first_edge_taps_r; if (found_second_edge_r) dbg_cpt_second_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6] <= #TCQ second_edge_taps_r; end endgenerate assign rdlvl_stg1_rnk_done = rdlvl_rank_done_r;// || regl_rank_done_r; assign mpr_rnk_done = mpr_rank_done_r; assign mpr_rdlvl_done = ((DRAM_TYPE == "DDR3") && (OCAL_EN == "ON")) ? //&& (SIM_CAL_OPTION == "NONE") mpr_rdlvl_done_r : 1'b1; //************************************************************************** // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 // coarse delay //************************************************************************** assign pi_stg2_rdlvl_cnt = (cal1_state_r == CAL1_REGL_LOAD) ? regl_dqs_cnt_r : cal1_cnt_cpt_r; assign idelay_ce = cal1_dq_idel_ce; assign idelay_inc = cal1_dq_idel_inc; //*************************************************************************** // Assert calib_in_common in FAST_CAL mode for IDELAY tap increments to all // DQs simultaneously //*************************************************************************** always @(posedge clk) begin if (rst) rdlvl_assrt_common <= #TCQ 1'b0; else if ((SIM_CAL_OPTION == "FAST_CAL") & rdlvl_stg1_start & !rdlvl_stg1_start_r) rdlvl_assrt_common <= #TCQ 1'b1; else if (!idel_pat_data_match_r & idel_pat_data_match) rdlvl_assrt_common <= #TCQ 1'b0; end //*************************************************************************** // Data mux to route appropriate bit to calibration logic - i.e. calibration // is done sequentially, one bit (or DQS group) at a time //*************************************************************************** generate if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; end else begin: rd_data_div2_logic_clk assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; end endgenerate always @(posedge clk) begin rd_mux_sel_r <= #TCQ cal1_cnt_cpt_r; end // Register outputs for improved timing. // NOTE: Will need to change when per-bit DQ deskew is supported. // Currenly all bits in DQS group are checked in aggregate generate genvar mux_i; for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end endgenerate //*************************************************************************** // MPR Read Leveling //*************************************************************************** // storing the previous read data for checking later. Only bit 0 is used // since MPR contents (01010101) are available generally on DQ[0] per // JEDEC spec. always @(posedge clk)begin if ((cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) || ((cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r)))begin mpr_rd_rise0_prev_r <= #TCQ mux_rd_rise0_r[0]; mpr_rd_fall0_prev_r <= #TCQ mux_rd_fall0_r[0]; mpr_rd_rise1_prev_r <= #TCQ mux_rd_rise1_r[0]; mpr_rd_fall1_prev_r <= #TCQ mux_rd_fall1_r[0]; mpr_rd_rise2_prev_r <= #TCQ mux_rd_rise2_r[0]; mpr_rd_fall2_prev_r <= #TCQ mux_rd_fall2_r[0]; mpr_rd_rise3_prev_r <= #TCQ mux_rd_rise3_r[0]; mpr_rd_fall3_prev_r <= #TCQ mux_rd_fall3_r[0]; end end generate if (nCK_PER_CLK == 4) begin: mpr_4to1 // changed stable count of 2 IDELAY taps at 78 ps resolution always @(posedge clk) begin if (rst | (cal1_state_r == CAL1_NEW_DQS_PREWAIT) | //(cal1_state_r == CAL1_DETECT_EDGE) | (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) | (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) | (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) | (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) | (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) | (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) | (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) | (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0])) stable_idel_cnt <= #TCQ 3'd0; else if ((|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) & ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) begin if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) & (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) & (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) & (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) & (mpr_rd_rise2_prev_r == mux_rd_rise2_r[0]) & (mpr_rd_fall2_prev_r == mux_rd_fall2_r[0]) & (mpr_rd_rise3_prev_r == mux_rd_rise3_r[0]) & (mpr_rd_fall3_prev_r == mux_rd_fall3_r[0]) & (stable_idel_cnt < 3'd2)) stable_idel_cnt <= #TCQ stable_idel_cnt + 1; end end always @(posedge clk) begin if (rst | (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r & mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r & mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r)) inhibit_edge_detect_r <= 1'b1; // Wait for settling time after idelay tap increment before // de-asserting inhibit_edge_detect_r else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) & (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r & ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r & ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r)) inhibit_edge_detect_r <= 1'b0; end //checking for transition from 01010101 to 10101010 always @(posedge clk)begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | inhibit_edge_detect_r) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 10101010 is not the correct pattern else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r & mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r & mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r) || ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r))) //|| (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2)) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 01010101 to 10101010 is the correct transition else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r & ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r & ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r) & (stable_idel_cnt == 3'd2) & ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) || (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) || (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) || (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) || (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) || (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) || (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) || (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0]))) idel_mpr_pat_detect_r <= #TCQ 1'b1; end end else if (nCK_PER_CLK == 2) begin: mpr_2to1 // changed stable count of 2 IDELAY taps at 78 ps resolution always @(posedge clk) begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) | (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) | (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) | (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0])) stable_idel_cnt <= #TCQ 3'd0; else if ((idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd0) & ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) begin if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) & (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) & (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) & (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) & (stable_idel_cnt < 3'd2)) stable_idel_cnt <= #TCQ stable_idel_cnt + 1; end end always @(posedge clk) begin if (rst | (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r)) inhibit_edge_detect_r <= 1'b1; else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) & (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) & (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r)) inhibit_edge_detect_r <= 1'b0; end //checking for transition from 01010101 to 10101010 always @(posedge clk)begin if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | inhibit_edge_detect_r) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 1010 is not the correct pattern else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r) || ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT) & (idel_pat_detect_valid_r))) // ||(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2)) idel_mpr_pat_detect_r <= #TCQ 1'b0; // 0101 to 1010 is the correct transition else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r) & (stable_idel_cnt == 3'd2) & ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) || (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) || (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) || (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]))) idel_mpr_pat_detect_r <= #TCQ 1'b1; end end endgenerate // Registered signal indicates when mux_rd_rise/fall_r is valid always @(posedge clk) mux_rd_valid_r <= #TCQ ~phy_if_empty; //*************************************************************************** // Decrement initial Phaser_IN fine delay value before proceeding with // read calibration //*************************************************************************** always @(posedge clk) begin dqs_po_dec_done_r1 <= #TCQ dqs_po_dec_done; dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1; fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1; pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r2; end always @(posedge clk) begin if (rst || pi_cnt_dec) wait_cnt_r <= #TCQ 'd8; else if (dqs_po_dec_done_r2 && (wait_cnt_r > 'd0)) wait_cnt_r <= #TCQ wait_cnt_r - 1; end always @(posedge clk) begin if (rst) begin pi_rdval_cnt <= #TCQ 'd0; end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin pi_rdval_cnt <= #TCQ pi_counter_read_val; end else if (pi_rdval_cnt > 'd0) begin if (pi_cnt_dec) pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1; else pi_rdval_cnt <= #TCQ pi_rdval_cnt; end else if (pi_rdval_cnt == 'd0) begin pi_rdval_cnt <= #TCQ pi_rdval_cnt; end end always @(posedge clk) begin if (rst || (pi_rdval_cnt == 'd0)) pi_cnt_dec <= #TCQ 1'b0; else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0) && (wait_cnt_r == 'd1)) pi_cnt_dec <= #TCQ 1'b1; else pi_cnt_dec <= #TCQ 1'b0; end always @(posedge clk) begin if (rst) begin fine_dly_dec_done_r1 <= #TCQ 1'b0; end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) || (dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin fine_dly_dec_done_r1 <= #TCQ 1'b1; end end //*************************************************************************** // Demultiplexor to control Phaser_IN delay values //*************************************************************************** // Read DQS always @(posedge clk) begin if (rst) begin pi_en_stg2_f_timing <= #TCQ 'b0; pi_stg2_f_incdec_timing <= #TCQ 'b0; end else if (pi_cnt_dec) begin pi_en_stg2_f_timing <= #TCQ 'b1; pi_stg2_f_incdec_timing <= #TCQ 'b0; end else if (cal1_dlyce_cpt_r) begin if ((SIM_CAL_OPTION == "NONE") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin // Change only specified DQS pi_en_stg2_f_timing <= #TCQ 1'b1; pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r; end else if (SIM_CAL_OPTION == "FAST_CAL") begin // if simulating, and "shortcuts" for calibration enabled, apply // results to all DQSs (i.e. assume same delay on all // DQSs). pi_en_stg2_f_timing <= #TCQ 1'b1; pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r; end end else begin pi_en_stg2_f_timing <= #TCQ 'b0; pi_stg2_f_incdec_timing <= #TCQ 'b0; end end // registered for timing always @(posedge clk) begin pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing; pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing; end // This counter used to implement settling time between // Phaser_IN rank register loads to different DQSs always @(posedge clk) begin if (rst) done_cnt <= #TCQ 'b0; else if (((cal1_state_r == CAL1_REGL_LOAD) && (cal1_state_r1 == CAL1_NEXT_DQS)) || ((done_cnt == 4'd1) && (cal1_state_r != CAL1_DONE))) done_cnt <= #TCQ 4'b1010; else if (done_cnt > 'b0) done_cnt <= #TCQ done_cnt - 1; end // During rank register loading the rank count must be sent to // Phaser_IN via the phy_ctl_wd?? If so phy_init will have to // issue NOPs during rank register loading with the appropriate // rank count always @(posedge clk) begin if (rst || (regl_rank_done_r == 1'b1)) regl_rank_done_r <= #TCQ 1'b0; else if ((regl_dqs_cnt == DQS_WIDTH-1) && (regl_rank_cnt != RANKS-1) && (done_cnt == 4'd1)) regl_rank_done_r <= #TCQ 1'b1; end // Temp wire for timing. // The following in the always block below causes timing issues // due to DSP block inference // 6*regl_dqs_cnt. // replacing this with two left shifts + 1 left shift to avoid // DSP multiplier. assign regl_dqs_cnt_timing = {2'd0, regl_dqs_cnt}; // Load Phaser_OUT rank register with rdlvl delay value // for each DQS per rank. always @(posedge clk) begin if (rst || (done_cnt == 4'd0)) begin pi_stg2_load_timing <= #TCQ 'b0; pi_stg2_reg_l_timing <= #TCQ 'b0; end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt <= DQS_WIDTH-1) && (done_cnt == 4'd1)) begin pi_stg2_load_timing <= #TCQ 'b1; pi_stg2_reg_l_timing <= #TCQ rdlvl_dqs_tap_cnt_r[rnk_cnt_r][regl_dqs_cnt]; end else begin pi_stg2_load_timing <= #TCQ 'b0; pi_stg2_reg_l_timing <= #TCQ 'b0; end end // registered for timing always @(posedge clk) begin pi_stg2_load <= #TCQ pi_stg2_load_timing; pi_stg2_reg_l <= #TCQ pi_stg2_reg_l_timing; end always @(posedge clk) begin if (rst || (done_cnt == 4'd0) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) regl_rank_cnt <= #TCQ 2'b00; else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin if (regl_rank_cnt == RANKS-1) regl_rank_cnt <= #TCQ regl_rank_cnt; else regl_rank_cnt <= #TCQ regl_rank_cnt + 1; end end always @(posedge clk) begin if (rst || (done_cnt == 4'd0) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) regl_dqs_cnt <= #TCQ {DQS_CNT_WIDTH+1{1'b0}}; else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin if (regl_rank_cnt == RANKS-1) regl_dqs_cnt <= #TCQ regl_dqs_cnt; else regl_dqs_cnt <= #TCQ 'b0; end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt != DQS_WIDTH-1) && (done_cnt == 4'd1)) regl_dqs_cnt <= #TCQ regl_dqs_cnt + 1; else regl_dqs_cnt <= #TCQ regl_dqs_cnt; end always @(posedge clk) regl_dqs_cnt_r <= #TCQ regl_dqs_cnt; //***************************************************************** // DQ Stage 1 CALIBRATION INCREMENT/DECREMENT LOGIC: // The actual IDELAY elements for each of the DQ bits is set via the // DLYVAL parallel load port. However, the stage 1 calibration // algorithm (well most of it) only needs to increment or decrement the DQ // IDELAY value by 1 at any one time. //***************************************************************** // Chip-select generation for each of the individual counters tracking // IDELAY tap values for each DQ generate for (z = 0; z < DQS_WIDTH; z = z + 1) begin: gen_dlyce_dq always @(posedge clk) if (rst) dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; else if (SIM_CAL_OPTION == "SKIP_CAL") // If skipping calibration altogether (only for simulation), no // need to set DQ IODELAY values - they are hardcoded dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; else if (SIM_CAL_OPTION == "FAST_CAL") begin // If fast calibration option (simulation only) selected, DQ // IODELAYs across all bytes are updated simultaneously // (although per-bit deskew within DQS[0] is still supported) for (h = 0; h < DRAM_WIDTH; h = h + 1) begin dlyce_dq_r[DRAM_WIDTH*z + h] <= #TCQ cal1_dlyce_dq_r; end end else if ((SIM_CAL_OPTION == "NONE") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin if (cal1_cnt_cpt_r == z) begin for (g = 0; g < DRAM_WIDTH; g = g + 1) begin dlyce_dq_r[DRAM_WIDTH*z + g] <= #TCQ cal1_dlyce_dq_r; end end else dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; end end endgenerate // Also delay increment/decrement control to match delay on DLYCE always @(posedge clk) if (rst) dlyinc_dq_r <= #TCQ 1'b0; else dlyinc_dq_r <= #TCQ cal1_dlyinc_dq_r; // Each DQ has a counter associated with it to record current read-leveling // delay value always @(posedge clk) // Reset or skipping calibration all together if (rst | (SIM_CAL_OPTION == "SKIP_CAL")) begin for (aa = 0; aa < RANKS; aa = aa + 1) begin: rst_dlyval_dq_reg_r for (bb = 0; bb < DQ_WIDTH; bb = bb + 1) dlyval_dq_reg_r[aa][bb] <= #TCQ 'b0; end end else if (SIM_CAL_OPTION == "FAST_CAL") begin for (n = 0; n < RANKS; n = n + 1) begin: gen_dlyval_dq_reg_rnk for (r = 0; r < DQ_WIDTH; r = r + 1) begin: gen_dlyval_dq_reg if (dlyce_dq_r[r]) begin if (dlyinc_dq_r) dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] + 5'h01; else dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] - 5'h01; end end end end else begin if (dlyce_dq_r[cal1_cnt_cpt_r]) begin if (dlyinc_dq_r) dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] + 5'h01; else dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] - 5'h01; end end // Register for timing (help with logic placement) always @(posedge clk) begin for (cc = 0; cc < RANKS; cc = cc + 1) begin: dlyval_dq_assgn for (dd = 0; dd < DQ_WIDTH; dd = dd + 1) dlyval_dq[((5*dd)+(cc*DQ_WIDTH*5))+:5] <= #TCQ dlyval_dq_reg_r[cc][dd]; end end //*************************************************************************** // Generate signal used to delay calibration state machine - used when: // (1) IDELAY value changed // (2) RD_MUX_SEL value changed // Use when a delay is necessary to give the change time to propagate // through the data pipeline (through IDELAY and ISERDES, and fabric // pipeline stages) //*************************************************************************** // List all the stage 1 calibration wait states here. // verilint STARC-2.7.3.3b off always @(posedge clk) if ((cal1_state_r == CAL1_NEW_DQS_WAIT) || (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) || (cal1_state_r == CAL1_NEW_DQS_PREWAIT) || (cal1_state_r == CAL1_VALID_WAIT) || (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_INC_CPT_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT) || (cal1_state_r == CAL1_PB_INC_DQ_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_WAIT) || (cal1_state_r == CAL1_IDEL_INC_CPT_WAIT) || (cal1_state_r == CAL1_IDEL_DEC_CPT_WAIT) || (cal1_state_r == CAL1_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_DQ_IDEL_TAP_INC_WAIT) || (cal1_state_r == CAL1_DQ_IDEL_TAP_DEC_WAIT)) cal1_wait_cnt_en_r <= #TCQ 1'b1; else cal1_wait_cnt_en_r <= #TCQ 1'b0; // verilint STARC-2.7.3.3b on always @(posedge clk) if (!cal1_wait_cnt_en_r) begin cal1_wait_cnt_r <= #TCQ 5'b00000; cal1_wait_r <= #TCQ 1'b1; end else begin if (cal1_wait_cnt_r != PIPE_WAIT_CNT - 1) begin cal1_wait_cnt_r <= #TCQ cal1_wait_cnt_r + 1; cal1_wait_r <= #TCQ 1'b1; end else begin // Need to reset to 0 to handle the case when there are two // different WAIT states back-to-back cal1_wait_cnt_r <= #TCQ 5'b00000; cal1_wait_r <= #TCQ 1'b0; end end //*************************************************************************** // generate request to PHY_INIT logic to issue precharged. Required when // calibration can take a long time (during which there are only constant // reads present on this bus). In this case need to issue perioidic // precharges to avoid tRAS violation. This signal must meet the following // requirements: (1) only transition from 0->1 when prech is first needed, // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted //*************************************************************************** always @(posedge clk) if (rst) rdlvl_prech_req <= #TCQ 1'b0; else rdlvl_prech_req <= #TCQ cal1_prech_req_r; //*************************************************************************** // Serial-to-parallel register to store last RDDATA_SHIFT_LEN cycles of // data from ISERDES. The value of this register is also stored, so that // previous and current values of the ISERDES data can be compared while // varying the IODELAY taps to see if an "edge" of the data valid window // has been encountered since the last IODELAY tap adjustment //*************************************************************************** //*************************************************************************** // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES // NOTE: Written using discrete flops, but SRL can be used if the matching // logic does the comparison sequentially, rather than parallel //*************************************************************************** generate genvar rd_i; if (nCK_PER_CLK == 4) begin: gen_sr_div4 if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i]; sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i]; sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i]; sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i]; end end end end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall1_r[rd_i]}; sr_rise2_r[rd_i] <= #TCQ {sr_rise2_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise2_r[rd_i]}; sr_fall2_r[rd_i] <= #TCQ {sr_fall2_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall2_r[rd_i]}; sr_rise3_r[rd_i] <= #TCQ {sr_rise3_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise3_r[rd_i]}; sr_fall3_r[rd_i] <= #TCQ {sr_fall3_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall3_r[rd_i]}; end end end end end else if (nCK_PER_CLK == 2) begin: gen_sr_div2 if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {mux_rd_fall1_r[rd_i]}; end end end end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin if (mux_rd_valid_r) begin sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise0_r[rd_i]}; sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall0_r[rd_i]}; sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_rise1_r[rd_i]}; sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0], mux_rd_fall1_r[rd_i]}; end end end end end endgenerate //*************************************************************************** // Conversion to pattern calibration //*************************************************************************** // Pattern for DQ IDELAY calibration //***************************************************************** // Expected data pattern when DQ shifted to the right such that // DQS before the left edge of the DVW: // Based on pattern of ({rise,fall}) = // 0x1, 0xB, 0x4, 0x4, 0xB, 0x9 // Each nibble will look like: // bit3: 0, 1, 0, 0, 1, 1 // bit2: 0, 0, 1, 1, 0, 0 // bit1: 0, 1, 0, 0, 1, 0 // bit0: 1, 1, 0, 0, 1, 1 // Or if the write is early it could look like: // 0x4, 0x4, 0xB, 0x9, 0x6, 0xE // bit3: 0, 0, 1, 1, 0, 1 // bit2: 1, 1, 0, 0, 1, 1 // bit1: 0, 0, 1, 0, 1, 1 // bit0: 0, 0, 1, 1, 0, 0 // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN // and the actual training pattern contents change //***************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_pat_div4 // Pattern for DQ IDELAY increment // Target pattern for "early write" assign {idel_pat0_rise0[3], idel_pat0_rise0[2], idel_pat0_rise0[1], idel_pat0_rise0[0]} = 4'h1; assign {idel_pat0_fall0[3], idel_pat0_fall0[2], idel_pat0_fall0[1], idel_pat0_fall0[0]} = 4'h7; assign {idel_pat0_rise1[3], idel_pat0_rise1[2], idel_pat0_rise1[1], idel_pat0_rise1[0]} = 4'hE; assign {idel_pat0_fall1[3], idel_pat0_fall1[2], idel_pat0_fall1[1], idel_pat0_fall1[0]} = 4'hC; assign {idel_pat0_rise2[3], idel_pat0_rise2[2], idel_pat0_rise2[1], idel_pat0_rise2[0]} = 4'h9; assign {idel_pat0_fall2[3], idel_pat0_fall2[2], idel_pat0_fall2[1], idel_pat0_fall2[0]} = 4'h2; assign {idel_pat0_rise3[3], idel_pat0_rise3[2], idel_pat0_rise3[1], idel_pat0_rise3[0]} = 4'h4; assign {idel_pat0_fall3[3], idel_pat0_fall3[2], idel_pat0_fall3[1], idel_pat0_fall3[0]} = 4'hB; // Target pattern for "on-time write" assign {idel_pat1_rise0[3], idel_pat1_rise0[2], idel_pat1_rise0[1], idel_pat1_rise0[0]} = 4'h4; assign {idel_pat1_fall0[3], idel_pat1_fall0[2], idel_pat1_fall0[1], idel_pat1_fall0[0]} = 4'h9; assign {idel_pat1_rise1[3], idel_pat1_rise1[2], idel_pat1_rise1[1], idel_pat1_rise1[0]} = 4'h3; assign {idel_pat1_fall1[3], idel_pat1_fall1[2], idel_pat1_fall1[1], idel_pat1_fall1[0]} = 4'h7; assign {idel_pat1_rise2[3], idel_pat1_rise2[2], idel_pat1_rise2[1], idel_pat1_rise2[0]} = 4'hE; assign {idel_pat1_fall2[3], idel_pat1_fall2[2], idel_pat1_fall2[1], idel_pat1_fall2[0]} = 4'hC; assign {idel_pat1_rise3[3], idel_pat1_rise3[2], idel_pat1_rise3[1], idel_pat1_rise3[0]} = 4'h9; assign {idel_pat1_fall3[3], idel_pat1_fall3[2], idel_pat1_fall3[1], idel_pat1_fall3[0]} = 4'h2; // Correct data valid window for "early write" assign {pat0_rise0[3], pat0_rise0[2], pat0_rise0[1], pat0_rise0[0]} = 4'h7; assign {pat0_fall0[3], pat0_fall0[2], pat0_fall0[1], pat0_fall0[0]} = 4'hE; assign {pat0_rise1[3], pat0_rise1[2], pat0_rise1[1], pat0_rise1[0]} = 4'hC; assign {pat0_fall1[3], pat0_fall1[2], pat0_fall1[1], pat0_fall1[0]} = 4'h9; assign {pat0_rise2[3], pat0_rise2[2], pat0_rise2[1], pat0_rise2[0]} = 4'h2; assign {pat0_fall2[3], pat0_fall2[2], pat0_fall2[1], pat0_fall2[0]} = 4'h4; assign {pat0_rise3[3], pat0_rise3[2], pat0_rise3[1], pat0_rise3[0]} = 4'hB; assign {pat0_fall3[3], pat0_fall3[2], pat0_fall3[1], pat0_fall3[0]} = 4'h1; // Correct data valid window for "on-time write" assign {pat1_rise0[3], pat1_rise0[2], pat1_rise0[1], pat1_rise0[0]} = 4'h9; assign {pat1_fall0[3], pat1_fall0[2], pat1_fall0[1], pat1_fall0[0]} = 4'h3; assign {pat1_rise1[3], pat1_rise1[2], pat1_rise1[1], pat1_rise1[0]} = 4'h7; assign {pat1_fall1[3], pat1_fall1[2], pat1_fall1[1], pat1_fall1[0]} = 4'hE; assign {pat1_rise2[3], pat1_rise2[2], pat1_rise2[1], pat1_rise2[0]} = 4'hC; assign {pat1_fall2[3], pat1_fall2[2], pat1_fall2[1], pat1_fall2[0]} = 4'h9; assign {pat1_rise3[3], pat1_rise3[2], pat1_rise3[1], pat1_rise3[0]} = 4'h2; assign {pat1_fall3[3], pat1_fall3[2], pat1_fall3[1], pat1_fall3[0]} = 4'h4; end else if (nCK_PER_CLK == 2) begin: gen_pat_div2 // Pattern for DQ IDELAY increment // Target pattern for "early write" assign idel_pat0_rise0[3] = 2'b01; assign idel_pat0_fall0[3] = 2'b00; assign idel_pat0_rise1[3] = 2'b10; assign idel_pat0_fall1[3] = 2'b11; assign idel_pat0_rise0[2] = 2'b00; assign idel_pat0_fall0[2] = 2'b10; assign idel_pat0_rise1[2] = 2'b11; assign idel_pat0_fall1[2] = 2'b10; assign idel_pat0_rise0[1] = 2'b00; assign idel_pat0_fall0[1] = 2'b11; assign idel_pat0_rise1[1] = 2'b10; assign idel_pat0_fall1[1] = 2'b01; assign idel_pat0_rise0[0] = 2'b11; assign idel_pat0_fall0[0] = 2'b10; assign idel_pat0_rise1[0] = 2'b00; assign idel_pat0_fall1[0] = 2'b01; // Target pattern for "on-time write" assign idel_pat1_rise0[3] = 2'b01; assign idel_pat1_fall0[3] = 2'b11; assign idel_pat1_rise1[3] = 2'b01; assign idel_pat1_fall1[3] = 2'b00; assign idel_pat1_rise0[2] = 2'b11; assign idel_pat1_fall0[2] = 2'b01; assign idel_pat1_rise1[2] = 2'b00; assign idel_pat1_fall1[2] = 2'b10; assign idel_pat1_rise0[1] = 2'b01; assign idel_pat1_fall0[1] = 2'b00; assign idel_pat1_rise1[1] = 2'b10; assign idel_pat1_fall1[1] = 2'b11; assign idel_pat1_rise0[0] = 2'b00; assign idel_pat1_fall0[0] = 2'b10; assign idel_pat1_rise1[0] = 2'b11; assign idel_pat1_fall1[0] = 2'b10; // Correct data valid window for "early write" assign pat0_rise0[3] = 2'b00; assign pat0_fall0[3] = 2'b10; assign pat0_rise1[3] = 2'b11; assign pat0_fall1[3] = 2'b10; assign pat0_rise0[2] = 2'b10; assign pat0_fall0[2] = 2'b11; assign pat0_rise1[2] = 2'b10; assign pat0_fall1[2] = 2'b00; assign pat0_rise0[1] = 2'b11; assign pat0_fall0[1] = 2'b10; assign pat0_rise1[1] = 2'b01; assign pat0_fall1[1] = 2'b00; assign pat0_rise0[0] = 2'b10; assign pat0_fall0[0] = 2'b00; assign pat0_rise1[0] = 2'b01; assign pat0_fall1[0] = 2'b11; // Correct data valid window for "on-time write" assign pat1_rise0[3] = 2'b11; assign pat1_fall0[3] = 2'b01; assign pat1_rise1[3] = 2'b00; assign pat1_fall1[3] = 2'b10; assign pat1_rise0[2] = 2'b01; assign pat1_fall0[2] = 2'b00; assign pat1_rise1[2] = 2'b10; assign pat1_fall1[2] = 2'b11; assign pat1_rise0[1] = 2'b00; assign pat1_fall0[1] = 2'b10; assign pat1_rise1[1] = 2'b11; assign pat1_fall1[1] = 2'b10; assign pat1_rise0[0] = 2'b10; assign pat1_fall0[0] = 2'b11; assign pat1_rise1[0] = 2'b10; assign pat1_fall1[0] = 2'b00; end endgenerate // Each bit of each byte is compared to expected pattern. // This was done to prevent (and "drastically decrease") the chance that // invalid data clocked in when the DQ bus is tri-state (along with a // combination of the correct data) will resemble the expected data // pattern. A better fix for this is to change the training pattern and/or // make the pattern longer. generate genvar pt_i; if (nCK_PER_CLK == 4) begin: gen_pat_match_div4 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match // DQ IDELAY pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4]) idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4]) idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4]) idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4]) idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == idel_pat0_rise2[pt_i%4]) idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == idel_pat0_fall2[pt_i%4]) idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == idel_pat0_rise3[pt_i%4]) idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == idel_pat0_fall3[pt_i%4]) idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4]) idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4]) idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4]) idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4]) idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == idel_pat1_rise2[pt_i%4]) idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == idel_pat1_fall2[pt_i%4]) idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == idel_pat1_rise3[pt_i%4]) idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == idel_pat1_fall3[pt_i%4]) idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b0; end // DQS DVW pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4]) pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4]) pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat0_rise2[pt_i%4]) pat0_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat0_fall2[pt_i%4]) pat0_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat0_rise3[pt_i%4]) pat0_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat0_fall3[pt_i%4]) pat0_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat1_rise2[pt_i%4]) pat1_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat1_fall2[pt_i%4]) pat1_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat1_rise3[pt_i%4]) pat1_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat1_fall3[pt_i%4]) pat1_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall3_r[pt_i] <= #TCQ 1'b0; end end // Combine pattern match "subterms" for DQ-IDELAY stage always @(posedge clk) begin idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r; idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r; idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r; idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r; idel_pat0_match_rise2_and_r <= #TCQ &idel_pat0_match_rise2_r; idel_pat0_match_fall2_and_r <= #TCQ &idel_pat0_match_fall2_r; idel_pat0_match_rise3_and_r <= #TCQ &idel_pat0_match_rise3_r; idel_pat0_match_fall3_and_r <= #TCQ &idel_pat0_match_fall3_r; idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r && idel_pat0_match_fall0_and_r && idel_pat0_match_rise1_and_r && idel_pat0_match_fall1_and_r && idel_pat0_match_rise2_and_r && idel_pat0_match_fall2_and_r && idel_pat0_match_rise3_and_r && idel_pat0_match_fall3_and_r); end always @(posedge clk) begin idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r; idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r; idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r; idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r; idel_pat1_match_rise2_and_r <= #TCQ &idel_pat1_match_rise2_r; idel_pat1_match_fall2_and_r <= #TCQ &idel_pat1_match_fall2_r; idel_pat1_match_rise3_and_r <= #TCQ &idel_pat1_match_rise3_r; idel_pat1_match_fall3_and_r <= #TCQ &idel_pat1_match_fall3_r; idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r && idel_pat1_match_fall0_and_r && idel_pat1_match_rise1_and_r && idel_pat1_match_fall1_and_r && idel_pat1_match_rise2_and_r && idel_pat1_match_fall2_and_r && idel_pat1_match_rise3_and_r && idel_pat1_match_fall3_and_r); end always @(*) idel_pat_data_match <= #TCQ idel_pat0_data_match_r | idel_pat1_data_match_r; always @(posedge clk) idel_pat_data_match_r <= #TCQ idel_pat_data_match; // Combine pattern match "subterms" for DQS-PHASER_IN stage always @(posedge clk) begin pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r; pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r; pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r; pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r; pat0_match_rise2_and_r <= #TCQ &pat0_match_rise2_r; pat0_match_fall2_and_r <= #TCQ &pat0_match_fall2_r; pat0_match_rise3_and_r <= #TCQ &pat0_match_rise3_r; pat0_match_fall3_and_r <= #TCQ &pat0_match_fall3_r; pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r && pat0_match_fall0_and_r && pat0_match_rise1_and_r && pat0_match_fall1_and_r && pat0_match_rise2_and_r && pat0_match_fall2_and_r && pat0_match_rise3_and_r && pat0_match_fall3_and_r); end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_match_rise2_and_r <= #TCQ &pat1_match_rise2_r; pat1_match_fall2_and_r <= #TCQ &pat1_match_fall2_r; pat1_match_rise3_and_r <= #TCQ &pat1_match_rise3_r; pat1_match_fall3_and_r <= #TCQ &pat1_match_fall3_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r && pat1_match_rise2_and_r && pat1_match_fall2_and_r && pat1_match_rise3_and_r && pat1_match_fall3_and_r); end assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r; end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match // DQ IDELAY pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4]) idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4]) idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4]) idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4]) idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4]) idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4]) idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4]) idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4]) idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end // DQS DVW pattern detection always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4]) pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4]) pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end end // Combine pattern match "subterms" for DQ-IDELAY stage always @(posedge clk) begin idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r; idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r; idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r; idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r; idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r && idel_pat0_match_fall0_and_r && idel_pat0_match_rise1_and_r && idel_pat0_match_fall1_and_r); end always @(posedge clk) begin idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r; idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r; idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r; idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r; idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r && idel_pat1_match_fall0_and_r && idel_pat1_match_rise1_and_r && idel_pat1_match_fall1_and_r); end always @(posedge clk) begin if (sr_valid_r2) idel_pat_data_match <= #TCQ idel_pat0_data_match_r | idel_pat1_data_match_r; end //assign idel_pat_data_match = idel_pat0_data_match_r | // idel_pat1_data_match_r; always @(posedge clk) idel_pat_data_match_r <= #TCQ idel_pat_data_match; // Combine pattern match "subterms" for DQS-PHASER_IN stage always @(posedge clk) begin pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r; pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r; pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r; pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r; pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r && pat0_match_fall0_and_r && pat0_match_rise1_and_r && pat0_match_fall1_and_r); end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r); end assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r; end endgenerate always @(posedge clk) begin rdlvl_stg1_start_r <= #TCQ rdlvl_stg1_start; mpr_rdlvl_done_r1 <= #TCQ mpr_rdlvl_done_r; mpr_rdlvl_done_r2 <= #TCQ mpr_rdlvl_done_r1; mpr_rdlvl_start_r <= #TCQ mpr_rdlvl_start; end //*************************************************************************** // First stage calibration: Capture clock //*************************************************************************** //***************************************************************** // Keep track of how many samples have been written to shift registers // Every time RD_SHIFT_LEN samples have been written, then we have a // full read training pattern loaded into the sr_* registers. Then assert // sr_valid_r to indicate that: (1) comparison between the sr_* and // old_sr_* and prev_sr_* registers can take place, (2) transfer of // the contents of sr_* to old_sr_* and prev_sr_* registers can also // take place //***************************************************************** // verilint STARC-2.2.3.3 off always @(posedge clk) if (rst || (mpr_rdlvl_done_r && ~rdlvl_stg1_start)) begin cnt_shift_r <= #TCQ 'b1; sr_valid_r <= #TCQ 1'b0; mpr_valid_r <= #TCQ 1'b0; end else begin if (mux_rd_valid_r && mpr_rdlvl_start && ~mpr_rdlvl_done_r) begin if (cnt_shift_r == 'b0) mpr_valid_r <= #TCQ 1'b1; else begin mpr_valid_r <= #TCQ 1'b0; cnt_shift_r <= #TCQ cnt_shift_r + 1; end end else mpr_valid_r <= #TCQ 1'b0; if (mux_rd_valid_r && rdlvl_stg1_start) begin if (cnt_shift_r == RD_SHIFT_LEN-1) begin sr_valid_r <= #TCQ 1'b1; cnt_shift_r <= #TCQ 'b0; end else begin sr_valid_r <= #TCQ 1'b0; cnt_shift_r <= #TCQ cnt_shift_r + 1; end end else // When the current mux_rd_* contents are not valid, then // retain the current value of cnt_shift_r, and make sure // that sr_valid_r = 0 to prevent any downstream loads or // comparisons sr_valid_r <= #TCQ 1'b0; end // verilint STARC-2.2.3.3 on //***************************************************************** // Logic to determine when either edge of the data eye encountered // Pre- and post-IDELAY update data pattern is compared, if they // differ, than an edge has been encountered. Currently no attempt // made to determine if the data pattern itself is "correct", only // whether it changes after incrementing the IDELAY (possible // future enhancement) //***************************************************************** // One-way control for ensuring that state machine request to store // current read data into OLD SR shift register only occurs on a // valid clock cycle. The FSM provides a one-cycle request pulse. // It is the responsibility of the FSM to wait the worst-case time // before relying on any downstream results of this load. always @(posedge clk) if (rst) store_sr_r <= #TCQ 1'b0; else begin if (store_sr_req_r) store_sr_r <= #TCQ 1'b1; else if ((sr_valid_r || mpr_valid_r) && store_sr_r) store_sr_r <= #TCQ 1'b0; end // Transfer current data to old data, prior to incrementing delay // Also store data from current sampling window - so that we can detect // if the current delay tap yields data that is "jittery" generate if (nCK_PER_CLK == 4) begin: gen_old_sr_div4 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr always @(posedge clk) begin if (sr_valid_r || mpr_valid_r) begin // Load last sample (i.e. from current sampling interval) prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; prev_sr_rise2_r[z] <= #TCQ sr_rise2_r[z]; prev_sr_fall2_r[z] <= #TCQ sr_fall2_r[z]; prev_sr_rise3_r[z] <= #TCQ sr_rise3_r[z]; prev_sr_fall3_r[z] <= #TCQ sr_fall3_r[z]; end if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; old_sr_rise2_r[z] <= #TCQ sr_rise2_r[z]; old_sr_fall2_r[z] <= #TCQ sr_fall2_r[z]; old_sr_rise3_r[z] <= #TCQ sr_rise3_r[z]; old_sr_fall3_r[z] <= #TCQ sr_fall3_r[z]; end end end end else if (nCK_PER_CLK == 2) begin: gen_old_sr_div2 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr always @(posedge clk) begin if (sr_valid_r || mpr_valid_r) begin prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; end if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; end end end end endgenerate //******************************************************* // Match determination occurs over 3 cycles - pipelined for better timing //******************************************************* // Match valid with # of cycles of pipelining in match determination always @(posedge clk) begin sr_valid_r1 <= #TCQ sr_valid_r; sr_valid_r2 <= #TCQ sr_valid_r1; mpr_valid_r1 <= #TCQ mpr_valid_r; mpr_valid_r2 <= #TCQ mpr_valid_r1; end generate if (nCK_PER_CLK == 4) begin: gen_sr_match_div4 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match always @(posedge clk) begin // CYCLE1: Compare all bits in DQS grp, generate separate term for // each bit over four bit times. For example, if there are 8-bits // per DQS group, 32 terms are generated on cycle 1 // NOTE: Structure HDL such that X on data bus will result in a // mismatch. This is required for memory models that can drive the // bus with X's to model uncertainty regions (e.g. Denali) if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z])) old_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z]; else old_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z])) old_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z]; else old_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z])) old_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z]; else old_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z])) old_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z]; else old_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == old_sr_rise2_r[z])) old_sr_match_rise2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise2_r[z] <= #TCQ old_sr_match_rise2_r[z]; else old_sr_match_rise2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == old_sr_fall2_r[z])) old_sr_match_fall2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall2_r[z] <= #TCQ old_sr_match_fall2_r[z]; else old_sr_match_fall2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == old_sr_rise3_r[z])) old_sr_match_rise3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise3_r[z] <= #TCQ old_sr_match_rise3_r[z]; else old_sr_match_rise3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == old_sr_fall3_r[z])) old_sr_match_fall3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall3_r[z] <= #TCQ old_sr_match_fall3_r[z]; else old_sr_match_fall3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z])) prev_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z]; else prev_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z])) prev_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z]; else prev_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z])) prev_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z]; else prev_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z])) prev_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z]; else prev_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == prev_sr_rise2_r[z])) prev_sr_match_rise2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise2_r[z] <= #TCQ prev_sr_match_rise2_r[z]; else prev_sr_match_rise2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == prev_sr_fall2_r[z])) prev_sr_match_fall2_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall2_r[z] <= #TCQ prev_sr_match_fall2_r[z]; else prev_sr_match_fall2_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == prev_sr_rise3_r[z])) prev_sr_match_rise3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise3_r[z] <= #TCQ prev_sr_match_rise3_r[z]; else prev_sr_match_rise3_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == prev_sr_fall3_r[z])) prev_sr_match_fall3_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall3_r[z] <= #TCQ prev_sr_match_fall3_r[z]; else prev_sr_match_fall3_r[z] <= #TCQ 1'b0; // CYCLE2: Combine all the comparisons for every 8 words (rise0, // fall0,rise1, fall1) in the calibration sequence. Now we're down // to DRAM_WIDTH terms old_sr_match_cyc2_r[z] <= #TCQ old_sr_match_rise0_r[z] & old_sr_match_fall0_r[z] & old_sr_match_rise1_r[z] & old_sr_match_fall1_r[z] & old_sr_match_rise2_r[z] & old_sr_match_fall2_r[z] & old_sr_match_rise3_r[z] & old_sr_match_fall3_r[z]; prev_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_rise0_r[z] & prev_sr_match_fall0_r[z] & prev_sr_match_rise1_r[z] & prev_sr_match_fall1_r[z] & prev_sr_match_rise2_r[z] & prev_sr_match_fall2_r[z] & prev_sr_match_rise3_r[z] & prev_sr_match_fall3_r[z]; // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen), // and qualify with pipelined valid signal) - probably don't need // a cycle just do do this.... if (sr_valid_r2 || mpr_valid_r2) begin old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z]; prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z]; end else begin old_sr_diff_r[z] <= #TCQ 'b0; prev_sr_diff_r[z] <= #TCQ 'b0; end end end end if (nCK_PER_CLK == 2) begin: gen_sr_match_div2 for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match always @(posedge clk) begin if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z])) old_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z]; else old_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z])) old_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z]; else old_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z])) old_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z]; else old_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z])) old_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z]; else old_sr_match_fall1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z])) prev_sr_match_rise0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z]; else prev_sr_match_rise0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z])) prev_sr_match_fall0_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z]; else prev_sr_match_fall0_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z])) prev_sr_match_rise1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z]; else prev_sr_match_rise1_r[z] <= #TCQ 1'b0; if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z])) prev_sr_match_fall1_r[z] <= #TCQ 1'b1; else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z]; else prev_sr_match_fall1_r[z] <= #TCQ 1'b0; old_sr_match_cyc2_r[z] <= #TCQ old_sr_match_rise0_r[z] & old_sr_match_fall0_r[z] & old_sr_match_rise1_r[z] & old_sr_match_fall1_r[z]; prev_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_rise0_r[z] & prev_sr_match_fall0_r[z] & prev_sr_match_rise1_r[z] & prev_sr_match_fall1_r[z]; // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen), // and qualify with pipelined valid signal) - probably don't need // a cycle just do do this.... if (sr_valid_r2 || mpr_valid_r2) begin old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z]; prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z]; end else begin old_sr_diff_r[z] <= #TCQ 'b0; prev_sr_diff_r[z] <= #TCQ 'b0; end end end end endgenerate //*************************************************************************** // First stage calibration: DQS Capture //*************************************************************************** //******************************************************* // Counters for tracking # of samples compared // For each comparision point (i.e. to determine if an edge has // occurred after each IODELAY increment when read leveling), // multiple samples are compared in order to average out the effects // of jitter. If any one of these samples is different than the "old" // sample corresponding to the previous IODELAY value, then an edge // is declared to be detected. //******************************************************* // Two cascaded counters are used to keep track of # of samples compared, // in order to make it easier to meeting timing on these paths. Once // optimal sampling interval is determined, it may be possible to remove // the second counter always @(posedge clk) samp_edge_cnt0_en_r <= #TCQ (cal1_state_r == CAL1_PAT_DETECT) || (cal1_state_r == CAL1_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ); // First counter counts # of samples compared always @(posedge clk) if (rst) samp_edge_cnt0_r <= #TCQ 'b0; else begin if (!samp_edge_cnt0_en_r) // Reset sample counter when not in any of the "sampling" states samp_edge_cnt0_r <= #TCQ 'b0; else if (sr_valid_r2 || mpr_valid_r2) // Otherwise, count # of samples compared samp_edge_cnt0_r <= #TCQ samp_edge_cnt0_r + 1; end // Counter #2 enable generation always @(posedge clk) if (rst) samp_edge_cnt1_en_r <= #TCQ 1'b0; else begin // Assert pulse when correct number of samples compared if ((samp_edge_cnt0_r == DETECT_EDGE_SAMPLE_CNT0) && (sr_valid_r2 || mpr_valid_r2)) samp_edge_cnt1_en_r <= #TCQ 1'b1; else samp_edge_cnt1_en_r <= #TCQ 1'b0; end // Counter #2 always @(posedge clk) if (rst) samp_edge_cnt1_r <= #TCQ 'b0; else if (!samp_edge_cnt0_en_r) samp_edge_cnt1_r <= #TCQ 'b0; else if (samp_edge_cnt1_en_r) samp_edge_cnt1_r <= #TCQ samp_edge_cnt1_r + 1; always @(posedge clk) if (rst) samp_cnt_done_r <= #TCQ 1'b0; else begin if (!samp_edge_cnt0_en_r) samp_cnt_done_r <= #TCQ 'b0; else if ((SIM_CAL_OPTION == "FAST_CAL") || (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin if (samp_edge_cnt0_r == SR_VALID_DELAY-1) // For simulation only, stay in edge detection mode a minimum // amount of time - just enough for two data compares to finish samp_cnt_done_r <= #TCQ 1'b1; end else begin if (samp_edge_cnt1_r == DETECT_EDGE_SAMPLE_CNT1) samp_cnt_done_r <= #TCQ 1'b1; end end //***************************************************************** // Logic to keep track of (on per-bit basis): // 1. When a region of stability preceded by a known edge occurs // 2. If for the current tap, the read data jitters // 3. If an edge occured between the current and previous tap // 4. When the current edge detection/sampling interval can end // Essentially, these are a series of status bits - the stage 1 // calibration FSM monitors these to determine when an edge is // found. Additional information is provided to help the FSM // determine if a left or right edge has been found. //**************************************************************** assign pb_detect_edge_setup = (cal1_state_r == CAL1_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) || (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT); assign pb_detect_edge = (cal1_state_r == CAL1_PAT_DETECT) || (cal1_state_r == CAL1_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE) || (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ); generate for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_track_left_edge always @(posedge clk) begin if (pb_detect_edge_setup) begin // Reset eye size, stable eye marker, and jitter marker before // starting new edge detection iteration pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_detect_edge_done_r[z] <= #TCQ 1'b0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_last_tap_jitter_r[z] <= #TCQ 1'b0; pb_found_edge_last_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b0; pb_found_first_edge_r[z] <= #TCQ 1'b0; end else if (pb_detect_edge) begin // Save information on which DQ bits are already out of the // data valid window - those DQ bits will later not have their // IDELAY tap value incremented pb_found_edge_last_r[z] <= #TCQ pb_found_edge_r[z]; if (!pb_detect_edge_done_r[z]) begin if (samp_cnt_done_r) begin // If we've reached end of sampling interval, no jitter on // current tap has been found (although an edge could have // been found between the current and previous taps), and // the sampling interval is complete. Increment the stable // eye counter if no edge found, and always clear the jitter // flag in preparation for the next tap. pb_last_tap_jitter_r[z] <= #TCQ 1'b0; pb_detect_edge_done_r[z] <= #TCQ 1'b1; if (!pb_found_edge_r[z] && !pb_last_tap_jitter_r[z]) begin // If the data was completely stable during this tap and // no edge was found between this and the previous tap // then increment the stable eye counter "as appropriate" if (pb_cnt_eye_size_r[z] != MIN_EYE_SIZE-1) pb_cnt_eye_size_r[z] <= #TCQ pb_cnt_eye_size_r[z] + 1; else //if (pb_found_first_edge_r[z]) // We've reached minimum stable eye width pb_found_stable_eye_r[z] <= #TCQ 1'b1; end else begin // Otherwise, an edge was found, either because of a // difference between this and the previous tap's read // data, and/or because the previous tap's data jittered // (but not the current tap's data), then just set the // edge found flag, and enable the stable eye counter pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b1; pb_detect_edge_done_r[z] <= #TCQ 1'b1; end end else if (prev_sr_diff_r[z]) begin // If we find that the current tap read data jitters, then // set edge and jitter found flags, "enable" the eye size // counter, and stop sampling interval for this bit pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_last_tap_jitter_r[z] <= #TCQ 1'b1; pb_found_edge_r[z] <= #TCQ 1'b1; pb_found_first_edge_r[z] <= #TCQ 1'b1; pb_detect_edge_done_r[z] <= #TCQ 1'b1; end else if (old_sr_diff_r[z] || pb_last_tap_jitter_r[z]) begin // If either an edge was found (i.e. difference between // current tap and previous tap read data), or the previous // tap exhibited jitter (which means by definition that the // current tap cannot match the previous tap because the // previous tap gave unstable data), then set the edge found // flag, and "enable" eye size counter. But do not stop // sampling interval - we still need to check if the current // tap exhibits jitter pb_cnt_eye_size_r[z] <= #TCQ 5'd0; pb_found_stable_eye_r[z] <= #TCQ 1'b0; pb_found_edge_r[z] <= #TCQ 1'b1; pb_found_first_edge_r[z] <= #TCQ 1'b1; end end end else begin // Before every edge detection interval, reset "intra-tap" flags pb_found_edge_r[z] <= #TCQ 1'b0; pb_detect_edge_done_r[z] <= #TCQ 1'b0; end end end endgenerate // Combine the above per-bit status flags into combined terms when // performing deskew on the aggregate data window always @(posedge clk) begin detect_edge_done_r <= #TCQ &pb_detect_edge_done_r; found_edge_r <= #TCQ |pb_found_edge_r; found_edge_all_r <= #TCQ &pb_found_edge_r; found_stable_eye_r <= #TCQ &pb_found_stable_eye_r; end // last IODELAY "stable eye" indicator is updated only after // detect_edge_done_r is asserted - so that when we do find the "right edge" // of the data valid window, found_edge_r = 1, AND found_stable_eye_r = 1 // when detect_edge_done_r = 1 (otherwise, if found_stable_eye_r updates // immediately, then it never possible to have found_stable_eye_r = 1 // when we detect an edge - and we'll never know whether we've found // a "right edge") always @(posedge clk) if (pb_detect_edge_setup) found_stable_eye_last_r <= #TCQ 1'b0; else if (detect_edge_done_r) found_stable_eye_last_r <= #TCQ found_stable_eye_r; //***************************************************************** // Keep track of DQ IDELAYE2 taps used //***************************************************************** // Added additional register stage to improve timing always @(posedge clk) if (rst) idelay_tap_cnt_slice_r <= 5'h0; else idelay_tap_cnt_slice_r <= idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]; always @(posedge clk) if (rst || (SIM_CAL_OPTION == "SKIP_CAL")) begin //|| new_cnt_cpt_r for (s = 0; s < RANKS; s = s + 1) begin for (t = 0; t < DQS_WIDTH; t = t + 1) begin idelay_tap_cnt_r[s][t] <= #TCQ idelaye2_init_val; end end end else if (SIM_CAL_OPTION == "FAST_CAL") begin for (u = 0; u < RANKS; u = u + 1) begin for (w = 0; w < DQS_WIDTH; w = w + 1) begin if (cal1_dq_idel_ce) begin if (cal1_dq_idel_inc) idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] + 1; else idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] - 1; end end end end else if ((rnk_cnt_r == RANKS-1) && (RANKS == 2) && rdlvl_rank_done_r && (cal1_state_r == CAL1_IDLE)) begin for (f = 0; f < DQS_WIDTH; f = f + 1) begin idelay_tap_cnt_r[rnk_cnt_r][f] <= #TCQ idelay_tap_cnt_r[(rnk_cnt_r-1)][f]; end end else if (cal1_dq_idel_ce) begin if (cal1_dq_idel_inc) idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r + 5'h1; else idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r - 5'h1; end else if (idelay_ld) idelay_tap_cnt_r[0][wrcal_cnt] <= #TCQ 5'b00000; always @(posedge clk) if (rst || new_cnt_cpt_r) idelay_tap_limit_r <= #TCQ 1'b0; else if (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_r] == 'd31) idelay_tap_limit_r <= #TCQ 1'b1; //***************************************************************** // keep track of edge tap counts found, and current capture clock // tap count //***************************************************************** always @(posedge clk) if (rst || new_cnt_cpt_r || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) tap_cnt_cpt_r <= #TCQ 'b0; else if (cal1_dlyce_cpt_r) begin if (cal1_dlyinc_cpt_r) tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r + 1; else if (tap_cnt_cpt_r != 'd0) tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r - 1; end always @(posedge clk) if (rst || new_cnt_cpt_r || (cal1_state_r1 == CAL1_DQ_IDEL_TAP_INC) || (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) tap_limit_cpt_r <= #TCQ 1'b0; else if (tap_cnt_cpt_r == 6'd63) tap_limit_cpt_r <= #TCQ 1'b1; always @(posedge clk) cal1_cnt_cpt_timing_r <= #TCQ cal1_cnt_cpt_r; assign cal1_cnt_cpt_timing = {2'b00, cal1_cnt_cpt_r}; // Storing DQS tap values at the end of each DQS read leveling always @(posedge clk) begin if (rst) begin for (a = 0; a < RANKS; a = a + 1) begin: rst_rdlvl_dqs_tap_count_loop for (b = 0; b < DQS_WIDTH; b = b + 1) rdlvl_dqs_tap_cnt_r[a][b] <= #TCQ 'b0; end end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_NEXT_DQS)) begin for (p = 0; p < RANKS; p = p +1) begin: rdlvl_dqs_tap_rank_cnt for(q = 0; q < DQS_WIDTH; q = q +1) begin: rdlvl_dqs_tap_cnt rdlvl_dqs_tap_cnt_r[p][q] <= #TCQ tap_cnt_cpt_r; end end end else if (SIM_CAL_OPTION == "SKIP_CAL") begin for (j = 0; j < RANKS; j = j +1) begin: rdlvl_dqs_tap_rnk_cnt for(i = 0; i < DQS_WIDTH; i = i +1) begin: rdlvl_dqs_cnt rdlvl_dqs_tap_cnt_r[j][i] <= #TCQ 6'd31; end end end else if (cal1_state_r1 == CAL1_NEXT_DQS) begin rdlvl_dqs_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing_r] <= #TCQ tap_cnt_cpt_r; end end // Counter to track maximum DQ IODELAY tap usage during the per-bit // deskew portion of stage 1 calibration always @(posedge clk) if (rst) begin idel_tap_cnt_dq_pb_r <= #TCQ 'b0; idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end else if (new_cnt_cpt_r) begin idel_tap_cnt_dq_pb_r <= #TCQ 'b0; idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end else if (|cal1_dlyce_dq_r) begin if (cal1_dlyinc_dq_r) idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r + 1; else idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r - 1; if (idel_tap_cnt_dq_pb_r == 31) idel_tap_limit_dq_pb_r <= #TCQ 1'b1; else idel_tap_limit_dq_pb_r <= #TCQ 1'b0; end //***************************************************************** always @(posedge clk) cal1_state_r1 <= #TCQ cal1_state_r; always @(posedge clk) if (rst) begin cal1_cnt_cpt_r <= #TCQ 'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_IDLE; cnt_idel_dec_cpt_r <= #TCQ 6'bxxxxxx; found_first_edge_r <= #TCQ 1'b0; found_second_edge_r <= #TCQ 1'b0; right_edge_taps_r <= #TCQ 6'bxxxxxx; first_edge_taps_r <= #TCQ 6'bxxxxxx; new_cnt_cpt_r <= #TCQ 1'b0; rdlvl_stg1_done <= #TCQ 1'b0; rdlvl_stg1_err <= #TCQ 1'b0; second_edge_taps_r <= #TCQ 6'bxxxxxx; store_sr_req_pulsed_r <= #TCQ 1'b0; store_sr_req_r <= #TCQ 1'b0; rnk_cnt_r <= #TCQ 2'b00; rdlvl_rank_done_r <= #TCQ 1'b0; idel_dec_cnt <= #TCQ 'd0; rdlvl_last_byte_done <= #TCQ 1'b0; idel_pat_detect_valid_r <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; idel_adj_inc <= #TCQ 1'b0; if (OCAL_EN == "ON") mpr_rdlvl_done_r <= #TCQ 1'b0; else mpr_rdlvl_done_r <= #TCQ 1'b1; mpr_dec_cpt_r <= #TCQ 1'b0; end else begin // default (inactive) states for all "pulse" outputs // verilint STARC-2.2.3.3 off cal1_prech_req_r <= #TCQ 1'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; new_cnt_cpt_r <= #TCQ 1'b0; store_sr_req_pulsed_r <= #TCQ 1'b0; store_sr_req_r <= #TCQ 1'b0; case (cal1_state_r) CAL1_IDLE: begin rdlvl_rank_done_r <= #TCQ 1'b0; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; if (mpr_rdlvl_start && ~mpr_rdlvl_start_r) begin cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT; end else if (rdlvl_stg1_start && ~rdlvl_stg1_start_r) begin if (SIM_CAL_OPTION == "SKIP_CAL") cal1_state_r <= #TCQ CAL1_REGL_LOAD; else if (SIM_CAL_OPTION == "FAST_CAL") cal1_state_r <= #TCQ CAL1_NEXT_DQS; else begin new_cnt_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT; end end end CAL1_MPR_NEW_DQS_WAIT: begin cal1_prech_req_r <= #TCQ 1'b0; if (!cal1_wait_r && mpr_valid_r) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; end // Wait for the new DQS group to change // also gives time for the read data IN_FIFO to // output the updated data for the new DQS group CAL1_NEW_DQS_WAIT: begin rdlvl_rank_done_r <= #TCQ 1'b0; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; if (|pi_counter_read_val) begin //VK_REVIEW mpr_dec_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; cnt_idel_dec_cpt_r <= #TCQ pi_counter_read_val; end else if (!cal1_wait_r) begin //if (!cal1_wait_r) begin // Store "previous tap" read data. Technically there is no // "previous" read data, since we are starting a new DQS // group, so we'll never find an edge at tap 0 unless the // data is fluctuating/jittering store_sr_req_r <= #TCQ 1'b1; // If per-bit deskew is disabled, then skip the first // portion of stage 1 calibration if (PER_BIT_DESKEW == "OFF") cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; else if (PER_BIT_DESKEW == "ON") cal1_state_r <= #TCQ CAL1_PB_STORE_FIRST_WAIT; end end //***************************************************************** // Per-bit deskew states //***************************************************************** // Wait state following storage of initial read data CAL1_PB_STORE_FIRST_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE; // Look for an edge on all DQ bits in current DQS group CAL1_PB_DETECT_EDGE: if (detect_edge_done_r) begin if (found_stable_eye_r) begin // If we've found the left edge for all bits (or more precisely, // we've found the left edge, and then part of the stable // window thereafter), then proceed to positioning the CPT clock // right before the left margin cnt_idel_dec_cpt_r <= #TCQ MIN_EYE_SIZE + 1; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT; end else begin // If we've reached the end of the sampling time, and haven't // yet found the left margin of all the DQ bits, then: if (!tap_limit_cpt_r) begin // If we still have taps left to use, then store current value // of read data, increment the capture clock, and continue to // look for (left) edges store_sr_req_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_CPT; end else begin // If we ran out of taps moving the capture clock, and we // haven't finished edge detection, then reset the capture // clock taps to 0 (gradually, one tap at a time... // then exit the per-bit portion of the algorithm - // i.e. proceed to adjust the capture clock and DQ IODELAYs as cnt_idel_dec_cpt_r <= #TCQ 6'd63; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end end end // Increment delay for DQS CAL1_PB_INC_CPT: begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_CPT_WAIT; end // Wait for IODELAY for both capture and internal nodes within // ISERDES to settle, before checking again for an edge CAL1_PB_INC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE; end // We've found the left edges of the windows for all DQ bits // (actually, we found it MIN_EYE_SIZE taps ago) Decrement capture // clock IDELAY to position just outside left edge of data window CAL1_PB_DEC_CPT_LEFT: if (cnt_idel_dec_cpt_r == 6'b000000) cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT_WAIT; else begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; end CAL1_PB_DEC_CPT_LEFT_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ; // If there is skew between individual DQ bits, then after we've // positioned the CPT clock, we will be "in the window" for some // DQ bits ("early" DQ bits), and "out of the window" for others // ("late" DQ bits). Increase DQ taps until we are out of the // window for all DQ bits CAL1_PB_DETECT_EDGE_DQ: if (detect_edge_done_r) if (found_edge_all_r) begin // We're out of the window for all DQ bits in this DQS group // We're done with per-bit deskew for this group - now decr // capture clock IODELAY tap count back to 0, and proceed // with the rest of stage 1 calibration for this DQS group cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end else if (!idel_tap_limit_dq_pb_r) // If we still have DQ taps available for deskew, keep // incrementing IODELAY tap count for the appropriate DQ bits cal1_state_r <= #TCQ CAL1_PB_INC_DQ; else begin // Otherwise, stop immediately (we've done the best we can) // and proceed with rest of stage 1 calibration cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; end CAL1_PB_INC_DQ: begin // Increment only those DQ for which an edge hasn't been found yet cal1_dlyce_dq_r <= #TCQ ~pb_found_edge_last_r; cal1_dlyinc_dq_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_PB_INC_DQ_WAIT; end CAL1_PB_INC_DQ_WAIT: if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ; // Decrement capture clock taps back to initial value CAL1_PB_DEC_CPT: if (cnt_idel_dec_cpt_r == 6'b000000) cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_WAIT; else begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; end // Wait for capture clock to settle, then proceed to rest of // state 1 calibration for this DQS group CAL1_PB_DEC_CPT_WAIT: if (!cal1_wait_r) begin store_sr_req_r <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; end // When first starting calibration for a DQS group, save the // current value of the read data shift register, and use this // as a reference. Note that for the first iteration of the // edge detection loop, we will in effect be checking for an edge // at IODELAY taps = 0 - normally, we are comparing the read data // for IODELAY taps = N, with the read data for IODELAY taps = N-1 // An edge can only be found at IODELAY taps = 0 if the read data // is changing during this time (possible due to jitter) CAL1_STORE_FIRST_WAIT: begin mpr_dec_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_PAT_DETECT; end CAL1_VALID_WAIT: begin if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; end CAL1_MPR_PAT_DETECT: begin // MPR read leveling for centering DQS in valid window before // OCLKDELAYED calibration begins in order to eliminate read issues if (idel_pat_detect_valid_r == 1'b0) begin cal1_state_r <= #TCQ CAL1_VALID_WAIT; idel_pat_detect_valid_r <= #TCQ 1'b1; end else if (idel_pat_detect_valid_r && idel_mpr_pat_detect_r) begin cal1_state_r <= #TCQ CAL1_DETECT_EDGE; idel_dec_cnt <= #TCQ 'd0; end else if (!idelay_tap_limit_r) cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC; else cal1_state_r <= #TCQ CAL1_RDLVL_ERR; end CAL1_PAT_DETECT: begin // All DQ bits associated with a DQS are pushed to the right one IDELAY // tap at a time until first rising DQS is in the tri-state region // before first rising edge window. // The detect_edge_done_r condition included to support averaging // during IDELAY tap increments if (detect_edge_done_r) begin if (idel_pat_data_match) begin case (idelay_adj) 2'b01: begin cal1_state_r <= CAL1_DQ_IDEL_TAP_INC; idel_dec_cnt <= #TCQ 1'b0; idel_adj_inc <= #TCQ 1'b1; end 2'b10: begin //DEC by 1 cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC ; idel_dec_cnt <= #TCQ 1'b1; idel_adj_inc <= #TCQ 1'b0; end default: begin cal1_state_r <= #TCQ CAL1_DETECT_EDGE; idel_dec_cnt <= #TCQ 1'b0; idel_adj_inc <= #TCQ 1'b0; end endcase end else if (!idelay_tap_limit_r) begin cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC; end else begin cal1_state_r <= #TCQ CAL1_RDLVL_ERR; end end end // Increment IDELAY tap by 1 for DQ bits in the byte being calibrated // until left edge of valid window detected CAL1_DQ_IDEL_TAP_INC: begin cal1_dq_idel_ce <= #TCQ 1'b1; cal1_dq_idel_inc <= #TCQ 1'b1; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC_WAIT; idel_pat_detect_valid_r <= #TCQ 1'b0; end CAL1_DQ_IDEL_TAP_INC_WAIT: begin cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; if (!cal1_wait_r) begin idel_adj_inc <= #TCQ 1'b0; if (idel_adj_inc) cal1_state_r <= #TCQ CAL1_DETECT_EDGE; else if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3")) cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; else cal1_state_r <= #TCQ CAL1_PAT_DETECT; end end // Decrement by 2 IDELAY taps once idel_pat_data_match detected CAL1_DQ_IDEL_TAP_DEC: begin cal1_dq_idel_inc <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC_WAIT; if (idel_dec_cnt >= 'd0) cal1_dq_idel_ce <= #TCQ 1'b1; else cal1_dq_idel_ce <= #TCQ 1'b0; if (idel_dec_cnt > 'd0) idel_dec_cnt <= #TCQ idel_dec_cnt - 1; else idel_dec_cnt <= #TCQ idel_dec_cnt; end CAL1_DQ_IDEL_TAP_DEC_WAIT: begin cal1_dq_idel_ce <= #TCQ 1'b0; cal1_dq_idel_inc <= #TCQ 1'b0; if (!cal1_wait_r) begin if ((idel_dec_cnt > 'd0) || (pi_rdval_cnt > 'd0)) cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC; else if (mpr_dec_cpt_r) cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; else cal1_state_r <= #TCQ CAL1_DETECT_EDGE; end end // Check for presence of data eye edge. During this state, we // sample the read data multiple times, and look for changes // in the read data, specifically: // 1. A change in the read data compared with the value of // read data from the previous delay tap. This indicates // that the most recent tap delay increment has moved us // into either a new window, or moved/kept us in the // transition/jitter region between windows. Note that this // condition only needs to be checked for once, and for // logistical purposes, we check this soon after entering // this state (see comment in CAL1_DETECT_EDGE below for // why this is done) // 2. A change in the read data while we are in this state // (i.e. in the absence of a tap delay increment). This // indicates that we're close enough to a window edge that // jitter will cause the read data to change even in the // absence of a tap delay change CAL1_DETECT_EDGE: begin // Essentially wait for the first comparision to finish, then // store current data into "old" data register. This store // happens now, rather than later (e.g. when we've have already // left this state) in order to avoid the situation the data that // is stored as "old" data has not been used in an "active // comparison" - i.e. data is stored after the last comparison // of this state. In this case, we can miss an edge if the // following sequence occurs: // 1. Comparison completes in this state - no edge found // 2. "Momentary jitter" occurs which "pushes" the data out the // equivalent of one delay tap // 3. We store this jittered data as the "old" data // 4. "Jitter" no longer present // 5. We increment the delay tap by one // 6. Now we compare the current with the "old" data - they're // the same, and no edge is detected // NOTE: Given the large # of comparisons done in this state, it's // highly unlikely the above sequence will occur in actual H/W // Wait for the first load of read data into the comparison // shift register to finish, then load the current read data // into the "old" data register. This allows us to do one // initial comparision between the current read data, and // stored data corresponding to the previous delay tap idel_pat_detect_valid_r <= #TCQ 1'b0; if (!store_sr_req_pulsed_r) begin // Pulse store_sr_req_r only once in this state store_sr_req_r <= #TCQ 1'b1; store_sr_req_pulsed_r <= #TCQ 1'b1; end else begin store_sr_req_r <= #TCQ 1'b0; store_sr_req_pulsed_r <= #TCQ 1'b1; end // Continue to sample read data and look for edges until the // appropriate time interval (shorter for simulation-only, // much, much longer for actual h/w) has elapsed if (detect_edge_done_r) begin if (tap_limit_cpt_r) // Only one edge detected and ran out of taps since only one // bit time worth of taps available for window detection. This // can happen if at tap 0 DQS is in previous window which results // in only left edge being detected. Or at tap 0 DQS is in the // current window resulting in only right edge being detected. // Depending on the frequency this case can also happen if at // tap 0 DQS is in the left noise region resulting in only left // edge being detected. cal1_state_r <= #TCQ CAL1_CALC_IDEL; else if (found_edge_r) begin // Sticky bit - asserted after we encounter an edge, although // the current edge may not be considered the "first edge" this // just means we found at least one edge found_first_edge_r <= #TCQ 1'b1; // Only the right edge of the data valid window is found // Record the inner right edge tap value if (!found_first_edge_r && found_stable_eye_last_r) begin if (tap_cnt_cpt_r == 'd0) right_edge_taps_r <= #TCQ 'd0; else right_edge_taps_r <= #TCQ tap_cnt_cpt_r; end // Both edges of data valid window found: // If we've found a second edge after a region of stability // then we must have just passed the second ("right" edge of // the window. Record this second_edge_taps = current tap-1, // because we're one past the actual second edge tap, where // the edge taps represent the extremes of the data valid // window (i.e. smallest & largest taps where data still valid if (found_first_edge_r && found_stable_eye_last_r) begin found_second_edge_r <= #TCQ 1'b1; second_edge_taps_r <= #TCQ tap_cnt_cpt_r - 1; cal1_state_r <= #TCQ CAL1_CALC_IDEL; end else begin // Otherwise, an edge was found (just not the "second" edge) // Assuming DQS is in the correct window at tap 0 of Phaser IN // fine tap. The first edge found is the right edge of the valid // window and is the beginning of the jitter region hence done! first_edge_taps_r <= #TCQ tap_cnt_cpt_r; cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT; end end else // Otherwise, if we haven't found an edge.... // If we still have taps left to use, then keep incrementing cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT; end end // Increment Phaser_IN delay for DQS CAL1_IDEL_INC_CPT: begin cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT_WAIT; if (~tap_limit_cpt_r) begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b1; end else begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; end end // Wait for Phaser_In to settle, before checking again for an edge CAL1_IDEL_INC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_DETECT_EDGE; end // Calculate final value of Phaser_IN taps. At this point, one or both // edges of data eye have been found, and/or all taps have been // exhausted looking for the edges // NOTE: We're calculating the amount to decrement by, not the // absolute setting for DQS. CAL1_CALC_IDEL: begin // CASE1: If 2 edges found. if (found_second_edge_r) cnt_idel_dec_cpt_r <= #TCQ ((second_edge_taps_r - first_edge_taps_r)>>1) + 1; else if (right_edge_taps_r > 6'd0) // Only right edge detected // right_edge_taps_r is the inner right edge tap value // hence used for calculation cnt_idel_dec_cpt_r <= #TCQ (tap_cnt_cpt_r - (right_edge_taps_r>>1)); else if (found_first_edge_r) // Only left edge detected cnt_idel_dec_cpt_r <= #TCQ ((tap_cnt_cpt_r - first_edge_taps_r)>>1); else cnt_idel_dec_cpt_r <= #TCQ (tap_cnt_cpt_r>>1); // Now use the value we just calculated to decrement CPT taps // to the desired calibration point cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; end // decrement capture clock for final adjustment - center // capture clock in middle of data eye. This adjustment will occur // only when both the edges are found usign CPT taps. Must do this // incrementally to avoid clock glitching (since CPT drives clock // divider within each ISERDES) CAL1_IDEL_DEC_CPT: begin cal1_dlyce_cpt_r <= #TCQ 1'b1; cal1_dlyinc_cpt_r <= #TCQ 1'b0; // once adjustment is complete, we're done with calibration for // this DQS, repeat for next DQS cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; if (cnt_idel_dec_cpt_r == 6'b000001) begin if (mpr_dec_cpt_r) begin if (|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) begin idel_dec_cnt <= #TCQ idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]; cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC; end else cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; end else cal1_state_r <= #TCQ CAL1_NEXT_DQS; end else cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT_WAIT; end CAL1_IDEL_DEC_CPT_WAIT: begin cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; if (!cal1_wait_r) cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; end // Determine whether we're done, or have more DQS's to calibrate // Also request precharge after every byte, as appropriate CAL1_NEXT_DQS: begin //if (mpr_rdlvl_done_r || (DRAM_TYPE == "DDR2")) cal1_prech_req_r <= #TCQ 1'b1; //else // cal1_prech_req_r <= #TCQ 1'b0; cal1_dlyce_cpt_r <= #TCQ 1'b0; cal1_dlyinc_cpt_r <= #TCQ 1'b0; // Prepare for another iteration with next DQS group found_first_edge_r <= #TCQ 1'b0; found_second_edge_r <= #TCQ 1'b0; first_edge_taps_r <= #TCQ 'd0; second_edge_taps_r <= #TCQ 'd0; if ((SIM_CAL_OPTION == "FAST_CAL") || (cal1_cnt_cpt_r >= DQS_WIDTH-1)) begin if (mpr_rdlvl_done_r) begin rdlvl_last_byte_done <= #TCQ 1'b1; mpr_last_byte_done <= #TCQ 1'b0; end else begin rdlvl_last_byte_done <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b1; end end // Wait until precharge that occurs in between calibration of // DQS groups is finished if (prech_done) begin // || (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))) begin if (SIM_CAL_OPTION == "FAST_CAL") begin //rdlvl_rank_done_r <= #TCQ 1'b1; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_DONE; //CAL1_REGL_LOAD; end else if (cal1_cnt_cpt_r >= DQS_WIDTH-1) begin if (~mpr_rdlvl_done_r) begin mpr_rank_done_r <= #TCQ 1'b1; // if (rnk_cnt_r == RANKS-1) begin // All DQS groups in all ranks done cal1_state_r <= #TCQ CAL1_DONE; cal1_cnt_cpt_r <= #TCQ 'b0; // end else begin // // Process DQS groups in next rank // rnk_cnt_r <= #TCQ rnk_cnt_r + 1; // new_cnt_cpt_r <= #TCQ 1'b1; // cal1_cnt_cpt_r <= #TCQ 'b0; // cal1_state_r <= #TCQ CAL1_IDLE; // end end else begin // All DQS groups in a rank done rdlvl_rank_done_r <= #TCQ 1'b1; if (rnk_cnt_r == RANKS-1) begin // All DQS groups in all ranks done cal1_state_r <= #TCQ CAL1_REGL_LOAD; end else begin // Process DQS groups in next rank rnk_cnt_r <= #TCQ rnk_cnt_r + 1; new_cnt_cpt_r <= #TCQ 1'b1; cal1_cnt_cpt_r <= #TCQ 'b0; cal1_state_r <= #TCQ CAL1_IDLE; end end end else begin // Process next DQS group new_cnt_cpt_r <= #TCQ 1'b1; cal1_cnt_cpt_r <= #TCQ cal1_cnt_cpt_r + 1; cal1_state_r <= #TCQ CAL1_NEW_DQS_PREWAIT; end end end CAL1_NEW_DQS_PREWAIT: begin if (!cal1_wait_r) begin if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3")) cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT; else cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT; end end // Load rank registers in Phaser_IN CAL1_REGL_LOAD: begin rdlvl_rank_done_r <= #TCQ 1'b0; mpr_rank_done_r <= #TCQ 1'b0; cal1_prech_req_r <= #TCQ 1'b0; cal1_cnt_cpt_r <= #TCQ 'b0; rnk_cnt_r <= #TCQ 2'b00; if ((regl_rank_cnt == RANKS-1) && ((regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1))) begin cal1_state_r <= #TCQ CAL1_DONE; rdlvl_last_byte_done <= #TCQ 1'b0; mpr_last_byte_done <= #TCQ 1'b0; end else cal1_state_r <= #TCQ CAL1_REGL_LOAD; end CAL1_RDLVL_ERR: begin rdlvl_stg1_err <= #TCQ 1'b1; end // Done with this stage of calibration // if used, allow DEBUG_PORT to control taps CAL1_DONE: begin mpr_rdlvl_done_r <= #TCQ 1'b1; cal1_prech_req_r <= #TCQ 1'b0; if (~mpr_rdlvl_done_r && (OCAL_EN=="ON") && (DRAM_TYPE == "DDR3")) begin rdlvl_stg1_done <= #TCQ 1'b0; cal1_state_r <= #TCQ CAL1_IDLE; end else rdlvl_stg1_done <= #TCQ 1'b1; end endcase end // verilint STARC-2.2.3.3 on endmodule
//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_v2_3_phy_ocd_data.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Data comparison for both "non-complex" and "complex" data. // // Depending on complex_oclkdelay_calib_start, data provided on the phy_rddata // bus is compared against a fixed ones and zeros pattern, or against data // provided on the prob_o bus. // // In the case of complex data, the phy_rddata data is delayed by two // clocks to match up with the prbs_o data. // // For 4:1 mode, in each fabric clock, a complete DRAM burst may be delivered. // A DRAM burst is 8 times the width of the DQ bus. For an 8 byte DQ // bus, 64 bytes are delivered on each clock. // // In 2:1 mode the DRAM burst is delivered on two fabric clocks. For // an 8 byte bus, 32 bytes are delivered with each fabric clock. // // For the most part, this block does not use phy_rddata_en. It delivers // its results and depends on downstream logic to know when its valid. // // phy_rddata_en is used for the PRBS compares when the last line of data // needs to be carried over to a subsequent line. // // Since we work on a byte at a time, the comparison only works on // one byte of the DQ bus at a time. The oclkdelay_calib_cnt field is used to // select the proper 8 bytes out of both the phy_rddata and prob_o streams. // // Comparisons are computed for "zero" or "rise" data, and "oneeighty" or // "fall" data. The "oneeighty" compares assumes the rising edge clock is // landing in the oneeighty data. // // For the simple data, we don't need to worry about first byte or last // byte conditions because the sampled data is taken from the middle // of a 4 burst segment. // // The complex (or PRBS) data starts and stops. And we need to be // careful about ignoring compares that might be using invalid latched // data. The PRBS generator provides prbs_ignore_first_byte and // prbs_ignore_last_bytes. The comparison block is procedural. It // first compares across the entire line, then comes back and overwrites // any byte compare results as indicated by the _ignore_ wires. // // The compares generate an eight bit vector, one for each byte. The // final step is to bitwise AND this eight bit vector. We end up // with two sets of two bits. Zero and oneeighty for the fixed pattern // and the prbs. // // complex_oclkdelay_calib_start is used to // select between the fixed and prbs compares. The final output // is a two bit match bus. // // There is a deprecated feature to mask the compare for any byte. // // //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_ocd_data # (parameter TCQ = 100, parameter nCK_PER_CLK = 4, parameter DQS_CNT_WIDTH = 3, parameter DQ_WIDTH = 64) (/*AUTOARG*/ // Outputs match, // Inputs clk, rst, complex_oclkdelay_calib_start, phy_rddata, prbs_o, oclkdelay_calib_cnt, prbs_ignore_first_byte, prbs_ignore_last_bytes, phy_rddata_en_1 ); localparam [7:0] OCAL_DQ_MASK = 8'b0000_0000; input clk; input rst; input complex_oclkdelay_calib_start; input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata; input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; reg [DQ_WIDTH-1:0] word, word_shifted; reg [63:0] data_bytes_ns, data_bytes_r, data_bytes_r1, data_bytes_r2, prbs_bytes_ns, prbs_bytes_r; always @(posedge clk) data_bytes_r <= #TCQ data_bytes_ns; always @(posedge clk) data_bytes_r1 <= #TCQ data_bytes_r; always @(posedge clk) data_bytes_r2 <= #TCQ data_bytes_r1; always @(posedge clk) prbs_bytes_r <= #TCQ prbs_bytes_ns; input prbs_ignore_first_byte, prbs_ignore_last_bytes; reg prbs_ignore_first_byte_r, prbs_ignore_last_bytes_r; always @(posedge clk) prbs_ignore_first_byte_r <= #TCQ prbs_ignore_first_byte; always @(posedge clk) prbs_ignore_last_bytes_r <= #TCQ prbs_ignore_last_bytes; input phy_rddata_en_1; reg [7:0] last_byte_r; wire [63:0] data_bytes = complex_oclkdelay_calib_start ? data_bytes_r2 : data_bytes_r; wire [7:0] last_byte_ns; generate if (nCK_PER_CLK == 4) begin assign last_byte_ns = phy_rddata_en_1 ? data_bytes[63:56] : last_byte_r; end else begin assign last_byte_ns = phy_rddata_en_1 ? data_bytes[31:24] : last_byte_r; end endgenerate always @(posedge clk) last_byte_r <= #TCQ last_byte_ns; reg second_half_ns, second_half_r; always @(posedge clk) second_half_r <= #TCQ second_half_ns; always @(*) begin second_half_ns = second_half_r; if (rst) second_half_ns = 1'b0; else second_half_ns = phy_rddata_en_1 ^ second_half_r; end reg [7:0] comp0, comp180, prbs0, prbs180; integer ii; always @(*) begin comp0 = 8'hff; comp180 = 8'hff; prbs0 = 8'hff; prbs180 = 8'hff; data_bytes_ns = 64'b0; prbs_bytes_ns = 64'b0; for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1) begin word = phy_rddata[ii*DQ_WIDTH+:DQ_WIDTH]; word_shifted = word >> oclkdelay_calib_cnt*8; data_bytes_ns[ii*8+:8] = word_shifted[7:0]; word = prbs_o[ii*DQ_WIDTH+:DQ_WIDTH]; word_shifted = word >> oclkdelay_calib_cnt*8; prbs_bytes_ns[ii*8+:8] = word_shifted[7:0]; comp0[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'hff : 8'h00); comp180[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'h00 : 8'hff); prbs0[ii] = data_bytes[ii*8+:8] == prbs_bytes_r[ii*8+:8]; end // for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1) prbs180[0] = last_byte_r == prbs_bytes_r[7:0]; for (ii=1; ii<2*nCK_PER_CLK; ii=ii+1) prbs180[ii] = data_bytes[(ii-1)*8+:8] == prbs_bytes_r[ii*8+:8]; if (nCK_PER_CLK == 4) begin if (prbs_ignore_last_bytes_r) begin prbs0[7:6] = 2'b11; prbs180[7] = 1'b1; end if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1; end else begin if (second_half_r) begin if (prbs_ignore_last_bytes_r) begin prbs0[3:2] = 2'b11; prbs180[3] = 1'b1; end end else if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1; end // else: !if(nCK_PER_CLK == 4) end // always @ (*) wire [7:0] comp0_masked = comp0 | OCAL_DQ_MASK; wire [7:0] comp180_masked = comp180 | OCAL_DQ_MASK; wire [7:0] prbs0_masked = prbs0 | OCAL_DQ_MASK; wire [7:0] prbs180_masked = prbs180 | OCAL_DQ_MASK; output [1:0] match; assign match = complex_oclkdelay_calib_start ? {&prbs180_masked, &prbs0_masked} : {&comp180_masked , &comp0_masked}; endmodule // mig_7series_v2_3_ddr_phy_ocd_data
//***************************************************************************** // (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2.3 // \ \ Application : MIG // / / Filename : ddr_phy_top.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Aug 03 2009 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Top level memory interface block. Instantiates a clock // and reset generator, the memory controller, the phy and // the user interface blocks. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_ddr_phy_top # ( parameter TCQ = 100, // Register delay (simulation only) parameter DDR3_VDD_OP_VOLT = 135, // Voltage mode used for DDR3 parameter AL = "0", // Additive Latency option parameter BANK_WIDTH = 3, // # of bank bits parameter BURST_MODE = "8", // Burst length parameter BURST_TYPE = "SEQ", // Burst type parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory parameter CL = 5, parameter COL_WIDTH = 12, // column address width parameter CS_WIDTH = 1, // # of unique CS outputs parameter CKE_WIDTH = 1, // # of cke outputs parameter CWL = 5, parameter DM_WIDTH = 8, // # of DM (data mask) parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_TYPE = "DDR3", parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides parameter LP_DDR_CK_WIDTH = 2, // Hard PHY parameters parameter PHYCTL_CMD_FIFO = "FALSE", // five fields, one per possible I/O bank, 4 bits in each field, // 1 per lane data=1/ctl=0 parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf, // defines the byte lanes in I/O banks being used in the interface // 1- Used, 0- Unused parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, // defines the bit lanes in I/O banks being used in the interface. Each // parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused parameter PHY_0_BITLANES = 48'h0000_0000_0000, parameter PHY_1_BITLANES = 48'h0000_0000_0000, parameter PHY_2_BITLANES = 48'h0000_0000_0000, // control/address/data pin mapping parameters parameter CK_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter ADDR_MAP = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, parameter BANK_MAP = 36'h000_000_000, parameter CAS_MAP = 12'h000, parameter CKE_ODT_BYTE_MAP = 8'h00, parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000, parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000, parameter CKE_ODT_AUX = "FALSE", parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, parameter PARITY_MAP = 12'h000, parameter RAS_MAP = 12'h000, parameter WE_MAP = 12'h000, parameter DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, // This parameter must be set based on memory clock frequency // It must be set to 4 for frequencies above 533 MHz?? (undecided) // and set to 2 for 533 MHz and below parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T" parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option parameter OUTPUT_DRV = "HIGH", // to calib_top parameter REG_CTRL = "OFF", // to calib_top parameter RTT_NOM = "60", // to calib_top parameter RTT_WR = "120", // to calib_top parameter tCK = 2500, // pS parameter tRFC = 110000, // pS parameter tREFI = 7800000, // pS parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter WRLVL = "OFF", // to calib_top parameter DEBUG_PORT = "OFF", // to calib_top parameter RANKS = 4, parameter ODT_WIDTH = 1, parameter ROW_WIDTH = 16, // DRAM address bus width parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000, // calibration Address. The address given below will be used for calibration // read and write operations. parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address parameter CALIB_COL_ADD = 12'h000, // Calibration column address parameter CALIB_BA_ADD = 3'h0, // Calibration bank address // Simulation /debug options parameter SIM_BYPASS_INIT_CAL = "OFF", // Parameter used to force skipping // or abbreviation of initialization // and calibration. Overrides // SIM_INIT_OPTION, SIM_CAL_OPTION, // and disables various other blocks //parameter SIM_INIT_OPTION = "SKIP_PU_DLY", // Skip various init steps //parameter SIM_CAL_OPTION = "NONE", // Skip various calib steps parameter REFCLK_FREQ = 200.0, // IODELAY ref clock freq (MHz) parameter USE_CS_PORT = 1, // Support chip select output parameter USE_DM_PORT = 1, // Support data mask output parameter USE_ODT_PORT = 1, // Support ODT output parameter RD_PATH_REG = 0, // optional registers in the read path // to MC for timing improvement. // =1 enabled, = 0 disabled parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering parameter TAPSPERKCLK = 56, parameter POC_USE_METASTABLE_SAMP = "FALSE" ) ( input clk, // Fabric logic clock // To MC, calib_top, hard PHY input clk_ref, // Idelay_ctrl reference clock // To hard PHY (external source) input freq_refclk, // To hard PHY for Phasers input mem_refclk, // Memory clock to hard PHY input pll_lock, // System PLL lock signal input sync_pulse, // 1/N sync pulse used to synchronize all PHASERS input mmcm_ps_clk, // Phase shift clock for oclk stg3 centering input poc_sample_pd, // Tell POC how to avoid metastability. input error, // Support for TG error detect output rst_tg_mc, // Support for TG error detect input [11:0] device_temp, input tempmon_sample_en, input dbg_sel_pi_incdec, input dbg_sel_po_incdec, input [DQS_CNT_WIDTH:0] dbg_byte_sel, input dbg_pi_f_inc, input dbg_pi_f_dec, input dbg_po_f_inc, input dbg_po_f_stg23_sel, input dbg_po_f_dec, input dbg_idel_down_all, input dbg_idel_down_cpt, input dbg_idel_up_all, input dbg_idel_up_cpt, input dbg_sel_all_idel_cpt, input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, input rst, input iddr_rst, input [7:0] slot_0_present, input [7:0] slot_1_present, // From MC input [nCK_PER_CLK-1:0] mc_ras_n, input [nCK_PER_CLK-1:0] mc_cas_n, input [nCK_PER_CLK-1:0] mc_we_n, input [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, input [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, input mc_reset_n, input [1:0] mc_odt, input [nCK_PER_CLK-1:0] mc_cke, // AUX - For ODT and CKE assertion during reads and writes input [3:0] mc_aux_out0, input [3:0] mc_aux_out1, input mc_cmd_wren, input mc_ctl_wren, input [2:0] mc_cmd, input [1:0] mc_cas_slot, input [5:0] mc_data_offset, input [5:0] mc_data_offset_1, input [5:0] mc_data_offset_2, input [1:0] mc_rank_cnt, // Write input mc_wrdata_en, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata, input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mc_wrdata_mask, input idle, // DDR bus signals output [ROW_WIDTH-1:0] ddr_addr, output [BANK_WIDTH-1:0] ddr_ba, output ddr_cas_n, output [CK_WIDTH-1:0] ddr_ck_n, output [CK_WIDTH-1:0] ddr_ck, output [CKE_WIDTH-1:0] ddr_cke, output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, output [DM_WIDTH-1:0] ddr_dm, output [ODT_WIDTH-1:0] ddr_odt, output ddr_ras_n, output ddr_reset_n, output ddr_parity, output ddr_we_n, inout [DQ_WIDTH-1:0] ddr_dq, inout [DQS_WIDTH-1:0] ddr_dqs_n, inout [DQS_WIDTH-1:0] ddr_dqs, //phase shift clock control output psen, output psincdec, input psdone, // Debug Port Outputs output [255:0] dbg_calib_top, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, output [255:0] dbg_phy_rdlvl, output [99:0] dbg_phy_wrcal, output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect, output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata, output dbg_rddata_valid, output [1:0] dbg_rdlvl_done, output [1:0] dbg_rdlvl_err, output [1:0] dbg_rdlvl_start, output [5:0] dbg_tap_cnt_during_wrlvl, output dbg_wl_edge_detect_valid, output dbg_wrlvl_done, output dbg_wrlvl_err, output dbg_wrlvl_start, output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, output [255:0] dbg_phy_wrlvl, output dbg_pi_phaselock_start, output dbg_pi_phaselocked_done, output dbg_pi_phaselock_err, output [11:0] dbg_pi_phase_locked_phy4lanes, output dbg_pi_dqsfound_start, output dbg_pi_dqsfound_done, output dbg_pi_dqsfound_err, output [11:0] dbg_pi_dqs_found_lanes_phy4lanes, output dbg_wrcal_start, output dbg_wrcal_done, output dbg_wrcal_err, // FIFO status flags output phy_mc_ctl_full, output phy_mc_cmd_full, output phy_mc_data_full, // Calibration status and resultant outputs output init_calib_complete, output init_wrcal_complete, output [6*RANKS-1:0] calib_rd_data_offset_0, output [6*RANKS-1:0] calib_rd_data_offset_1, output [6*RANKS-1:0] calib_rd_data_offset_2, output phy_rddata_valid, output [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data, output ref_dll_lock, input rst_phaser_ref, output [6*RANKS-1:0] dbg_rd_data_offset, output [255:0] dbg_phy_init, output [255:0] dbg_prbs_rdlvl, output [255:0] dbg_dqs_found_cal, output [5:0] dbg_pi_counter_read_val, output [8:0] dbg_po_counter_read_val, output dbg_oclkdelay_calib_start, output dbg_oclkdelay_calib_done, output [255:0] dbg_phy_oclkdelay_cal, output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data, output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps ); // Calculate number of slots in the system localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0); localparam CLK_PERIOD = tCK * nCK_PER_CLK; // Parameter used to force skipping or abbreviation of initialization // and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and // disables various other blocks depending on the option selected // This option should only be used during simulation. In the case of // the "SKIP" option, the testbench used should also not be modeling // propagation delays. // Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"} // "NONE" = options determined by the individual parameter settings // "SIM_FULL" = skip power-up delay. FULL calibration performed without // averaging algorithm turned ON during window detection. // "SKIP" = skip power-up delay. Skip calibration not yet supported. // "FAST" = skip power-up delay, and calibrate (read leveling, write // leveling, and phase detector) only using one DQS group, and // apply the results to all other DQS groups. localparam SIM_INIT_OPTION = ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_INIT" : ((SIM_BYPASS_INIT_CAL == "FAST") || (SIM_BYPASS_INIT_CAL == "SIM_FULL")) ? "SKIP_PU_DLY" : "NONE"); localparam SIM_CAL_OPTION = ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_CAL" : (SIM_BYPASS_INIT_CAL == "FAST") ? "FAST_CAL" : ((SIM_BYPASS_INIT_CAL == "SIM_FULL") || (SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")) ? "FAST_WIN_DETECT" : "NONE"); localparam WRLVL_W = (SIM_BYPASS_INIT_CAL == "SKIP") ? "OFF" : WRLVL; localparam HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))); localparam HIGHEST_LANE_B0 = BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0; localparam HIGHEST_LANE_B1 = BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0; localparam HIGHEST_LANE_B2 = BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0; localparam HIGHEST_LANE_B3 = BYTE_LANES_B3[3] ? 4 : BYTE_LANES_B3[2] ? 3 : BYTE_LANES_B3[1] ? 2 : BYTE_LANES_B3[0] ? 1 : 0; localparam HIGHEST_LANE_B4 = BYTE_LANES_B4[3] ? 4 : BYTE_LANES_B4[2] ? 3 : BYTE_LANES_B4[1] ? 2 : BYTE_LANES_B4[0] ? 1 : 0; localparam HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))); localparam N_CTL_LANES = ((0+(!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) + (0+(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) + (0+(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) + (0+(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) + ((0+(!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) + (0+(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) + (0+(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) + (0+(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) + ((0+(!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) + (0+(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) + (0+(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) + (0+(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) + ((0+(!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) + (0+(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) + (0+(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) + (0+(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) + ((0+(!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) + (0+(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) + (0+(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) + (0+(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3])); // Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank // This should be the case since the PLL should be placed adjacent // to the same IO Bank as Ck/Addr/Cmd and Control localparam [2:0] CTL_BANK = (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) | ((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) | ((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | ((!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) ? 3'b000 : (((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) | ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) | ((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | ((!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) ? 3'b001 : (((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) | ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) | ((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | ((!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) ? 3'b010 : (((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) | ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) | ((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | ((!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) ? 3'b011 : (((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) | ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) | ((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) | ((!DATA_CTL_B4[3]) & BYTE_LANES_B4[3])) ? 3'b100 : 3'b000; localparam [7:0] CTL_BYTE_LANE = (N_CTL_LANES == 4) ? 8'b11_10_01_00 : ((N_CTL_LANES == 3) & (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ? 8'b00_10_01_00 : ((N_CTL_LANES == 3) & (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? 8'b00_11_01_00 : ((N_CTL_LANES == 3) & (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] & (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] & (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] & (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] & (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] & (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? 8'b00_11_10_00 : ((N_CTL_LANES == 3) & (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] & (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] & (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] & (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] & (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] & (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? 8'b00_11_10_01 : ((N_CTL_LANES == 2) & (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) | ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) | ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) | ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) | ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]))) ? 8'b00_00_01_00 : ((N_CTL_LANES == 2) & (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? 8'b00_00_11_00 : ((N_CTL_LANES == 2) & (((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] & (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | ((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] & (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | ((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] & (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | ((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] & (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | ((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] & (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? 8'b00_00_11_10 : ((N_CTL_LANES == 2) & (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ? 8'b00_00_10_01 : ((N_CTL_LANES == 2) & (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? 8'b00_00_11_01 : ((N_CTL_LANES == 2) & (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ? 8'b00_00_10_00 : 8'b11_10_01_00; wire [HIGHEST_LANE*80-1:0] phy_din; wire [HIGHEST_LANE*80-1:0] phy_dout; wire [(HIGHEST_LANE*12)-1:0] ddr_cmd_ctl_data; wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out; wire [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk; wire phy_mc_go; wire phy_ctl_full; wire phy_cmd_full; wire phy_data_full; wire phy_pre_data_a_full; wire if_empty /* synthesis syn_maxfan = 3 */; wire phy_write_calib; wire phy_read_calib; wire [HIGHEST_BANK-1:0] rst_stg1_cal; wire [5:0] calib_sel; wire calib_in_common /* synthesis syn_maxfan = 10 */; wire [HIGHEST_BANK-1:0] calib_zero_inputs; wire [HIGHEST_BANK-1:0] calib_zero_ctrl; wire pi_phase_locked; wire pi_phase_locked_all; wire pi_found_dqs; wire pi_dqs_found_all; wire pi_dqs_out_of_range; wire pi_enstg2_f; wire pi_stg2_fincdec; wire pi_stg2_load; wire [5:0] pi_stg2_reg_l; wire idelay_ce; wire idelay_inc; wire idelay_ld; wire [2:0] po_sel_stg2stg3; wire [2:0] po_stg2_cincdec; wire [2:0] po_enstg2_c; wire [2:0] po_stg2_fincdec; wire [2:0] po_enstg2_f; wire [8:0] po_counter_read_val; wire [5:0] pi_counter_read_val; wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata; reg [nCK_PER_CLK-1:0] parity; wire [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address; wire [nCK_PER_CLK*BANK_WIDTH-1:0] phy_bank; wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n; wire [nCK_PER_CLK-1:0] phy_ras_n; wire [nCK_PER_CLK-1:0] phy_cas_n; wire [nCK_PER_CLK-1:0] phy_we_n; wire phy_reset_n; wire [3:0] calib_aux_out; wire [nCK_PER_CLK-1:0] calib_cke; wire [1:0] calib_odt; wire calib_ctl_wren; wire calib_cmd_wren; wire calib_wrdata_en; wire [2:0] calib_cmd; wire [1:0] calib_seq; wire [5:0] calib_data_offset_0; wire [5:0] calib_data_offset_1; wire [5:0] calib_data_offset_2; wire [1:0] calib_rank_cnt; wire [1:0] calib_cas_slot; wire [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address; wire [3:0] mux_aux_out; wire [3:0] aux_out_map; wire [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank; wire [2:0] mux_cmd; wire mux_cmd_wren; wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n; wire mux_ctl_wren; wire [1:0] mux_cas_slot; wire [5:0] mux_data_offset; wire [5:0] mux_data_offset_1; wire [5:0] mux_data_offset_2; wire [nCK_PER_CLK-1:0] mux_ras_n; wire [nCK_PER_CLK-1:0] mux_cas_n; wire [1:0] mux_rank_cnt; wire mux_reset_n; wire [nCK_PER_CLK-1:0] mux_we_n; wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata; wire [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask; wire mux_wrdata_en; wire [nCK_PER_CLK-1:0] mux_cke ; wire [1:0] mux_odt ; wire phy_if_empty_def; wire phy_if_reset; wire phy_init_data_sel; wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_map; wire phy_rddata_valid_w; reg rddata_valid_reg; reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_reg; wire [4:0] idelaye2_init_val; wire [5:0] oclkdelay_init_val; wire po_counter_load_en; wire [DQS_CNT_WIDTH:0] byte_sel_cnt; wire [DRAM_WIDTH-1:0] fine_delay_incdec_pb; wire fine_delay_sel; wire pd_out; //*************************************************************************** assign dbg_rddata_valid = rddata_valid_reg; assign dbg_rddata = rd_data_reg; assign dbg_rd_data_offset = calib_rd_data_offset_0; assign dbg_pi_phaselocked_done = pi_phase_locked_all; assign dbg_po_counter_read_val = po_counter_read_val; assign dbg_pi_counter_read_val = pi_counter_read_val; //*************************************************************************** genvar i; generate for (i = 0; i < CK_WIDTH; i = i+1) begin: clock_gen assign ddr_ck[i] = ddr_clk[LP_DDR_CK_WIDTH * i]; assign ddr_ck_n[i] = ddr_clk[(LP_DDR_CK_WIDTH * i) + 1]; end endgenerate //*************************************************************************** // During memory initialization and calibration the calibration logic drives // the memory signals. After calibration is complete the memory controller // drives the memory signals. // Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps //*************************************************************************** wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_temp ; genvar v ; generate if((REG_CTRL == "ON") && (DRAM_TYPE == "DDR3") && (RANKS == 1) && (nCS_PER_RANK ==2)) begin : cs_rdimm for(v = 0 ; v < CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK ; v = v+1 ) begin if((v%(CS_WIDTH*nCS_PER_RANK)) == 0) begin assign mc_cs_n_temp[v] = mc_cs_n[v] ; end else begin assign mc_cs_n_temp[v] = 'b1 ; end end end else begin assign mc_cs_n_temp = mc_cs_n ; end endgenerate assign mux_wrdata = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata : phy_wrdata; assign mux_wrdata_mask = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_mask : 'b0; assign mux_address = (phy_init_data_sel | init_wrcal_complete) ? mc_address : phy_address; assign mux_bank = (phy_init_data_sel | init_wrcal_complete) ? mc_bank : phy_bank; assign mux_cs_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cs_n_temp : phy_cs_n; assign mux_ras_n = (phy_init_data_sel | init_wrcal_complete) ? mc_ras_n : phy_ras_n; assign mux_cas_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_n : phy_cas_n; assign mux_we_n = (phy_init_data_sel | init_wrcal_complete) ? mc_we_n : phy_we_n; assign mux_reset_n = (phy_init_data_sel | init_wrcal_complete) ? mc_reset_n : phy_reset_n; assign mux_aux_out = (phy_init_data_sel | init_wrcal_complete) ? mc_aux_out0 : calib_aux_out; assign mux_odt = (phy_init_data_sel | init_wrcal_complete) ? mc_odt : calib_odt ; assign mux_cke = (phy_init_data_sel | init_wrcal_complete) ? mc_cke : calib_cke ; assign mux_cmd_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd_wren : calib_cmd_wren; assign mux_ctl_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_ctl_wren : calib_ctl_wren; assign mux_wrdata_en = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_en : calib_wrdata_en; assign mux_cmd = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd : calib_cmd; assign mux_cas_slot = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_slot : calib_cas_slot; assign mux_data_offset = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset : calib_data_offset_0; assign mux_data_offset_1 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_1 : calib_data_offset_1; assign mux_data_offset_2 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_2 : calib_data_offset_2; // Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601 assign mux_rank_cnt = 2'b00; // Assigning cke & odt for DDR2 & DDR3 // No changes for DDR3 & DDR2 dual rank // DDR2 single rank systems might potentially need 3 odt signals. // Aux_out[2] will have the odt toggled by phy and controller // wiring aux_out[2] to 0 & 3. Depending upon the odt parameter // all of the three odt bits or some of them might be used. // mapping done in mc_phy_wrapper module generate if(CKE_ODT_AUX == "TRUE") begin assign aux_out_map = ((DRAM_TYPE == "DDR2") && (RANKS == 1)) ? {mux_aux_out[1],mux_aux_out[1],mux_aux_out[1],mux_aux_out[0]} : mux_aux_out; end else begin assign aux_out_map = 4'b0000 ; end endgenerate assign init_calib_complete = phy_init_data_sel; assign phy_mc_ctl_full = phy_ctl_full; assign phy_mc_cmd_full = phy_cmd_full; assign phy_mc_data_full = phy_pre_data_a_full; //*************************************************************************** // Generate parity for DDR3 RDIMM. //*************************************************************************** generate if ((DRAM_TYPE == "DDR3") && (REG_CTRL == "ON")) begin: gen_ddr3_parity if (nCK_PER_CLK == 4) begin always @(posedge clk) begin parity[0] <= #TCQ (^{mux_address[(ROW_WIDTH*4)-1:ROW_WIDTH*3], mux_bank[(BANK_WIDTH*4)-1:BANK_WIDTH*3], mux_cas_n[3], mux_ras_n[3], mux_we_n[3]}); end always @(*) begin parity[1] = (^{mux_address[ROW_WIDTH-1:0], mux_bank[BANK_WIDTH-1:0], mux_cas_n[0],mux_ras_n[0], mux_we_n[0]}); parity[2] = (^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH], mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH], mux_cas_n[1], mux_ras_n[1], mux_we_n[1]}); parity[3] = (^{mux_address[(ROW_WIDTH*3)-1:ROW_WIDTH*2], mux_bank[(BANK_WIDTH*3)-1:BANK_WIDTH*2], mux_cas_n[2],mux_ras_n[2], mux_we_n[2]}); end end else begin always @(posedge clk) begin parity[0] <= #TCQ(^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH], mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH], mux_cas_n[1], mux_ras_n[1], mux_we_n[1]}); end always @(*) begin parity[1] = (^{mux_address[ROW_WIDTH-1:0], mux_bank[BANK_WIDTH-1:0], mux_cas_n[0], mux_ras_n[0], mux_we_n[0]}); end end end else begin: gen_ddr3_noparity if (nCK_PER_CLK == 4) begin always @(posedge clk) begin parity[0] <= #TCQ 1'b0; parity[1] <= #TCQ 1'b0; parity[2] <= #TCQ 1'b0; parity[3] <= #TCQ 1'b0; end end else begin always @(posedge clk) begin parity[0] <= #TCQ 1'b0; parity[1] <= #TCQ 1'b0; end end end endgenerate //*************************************************************************** // Code for optional register stage in read path to MC for timing //*************************************************************************** generate if(RD_PATH_REG == 1)begin:RD_REG_TIMING always @(posedge clk)begin rddata_valid_reg <= #TCQ phy_rddata_valid_w; rd_data_reg <= #TCQ rd_data_map; end // always @ (posedge clk) end else begin : RD_REG_NO_TIMING // block: RD_REG_TIMING always @(phy_rddata_valid_w or rd_data_map)begin rddata_valid_reg = phy_rddata_valid_w; rd_data_reg = rd_data_map; end end endgenerate assign phy_rddata_valid = rddata_valid_reg; assign phy_rd_data = rd_data_reg; //*************************************************************************** // Hard PHY and accompanying bit mapping logic //*************************************************************************** mig_7series_v2_3_ddr_mc_phy_wrapper # ( .TCQ (TCQ), .tCK (tCK), .BANK_TYPE (BANK_TYPE), .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE), .DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .nCK_PER_CLK (nCK_PER_CLK), .nCS_PER_RANK (nCS_PER_RANK), .BANK_WIDTH (BANK_WIDTH), .CKE_WIDTH (CKE_WIDTH), .CS_WIDTH (CS_WIDTH), .CK_WIDTH (CK_WIDTH), .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH), .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE), .CWL (CWL), .DM_WIDTH (DM_WIDTH), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_TYPE (DRAM_TYPE), .RANKS (RANKS), .ODT_WIDTH (ODT_WIDTH), .REG_CTRL (REG_CTRL), .ROW_WIDTH (ROW_WIDTH), .USE_CS_PORT (USE_CS_PORT), .USE_DM_PORT (USE_DM_PORT), .USE_ODT_PORT (USE_ODT_PORT), .IBUF_LPWR_MODE (IBUF_LPWR_MODE), .PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .PHY_0_BITLANES (PHY_0_BITLANES), .PHY_1_BITLANES (PHY_1_BITLANES), .PHY_2_BITLANES (PHY_2_BITLANES), .HIGHEST_BANK (HIGHEST_BANK), .HIGHEST_LANE (HIGHEST_LANE), .CK_BYTE_MAP (CK_BYTE_MAP), .ADDR_MAP (ADDR_MAP), .BANK_MAP (BANK_MAP), .CAS_MAP (CAS_MAP), .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP), .CKE_MAP (CKE_MAP), .ODT_MAP (ODT_MAP), .CKE_ODT_AUX (CKE_ODT_AUX), .CS_MAP (CS_MAP), .PARITY_MAP (PARITY_MAP), .RAS_MAP (RAS_MAP), .WE_MAP (WE_MAP), .DQS_BYTE_MAP (DQS_BYTE_MAP), .DATA0_MAP (DATA0_MAP), .DATA1_MAP (DATA1_MAP), .DATA2_MAP (DATA2_MAP), .DATA3_MAP (DATA3_MAP), .DATA4_MAP (DATA4_MAP), .DATA5_MAP (DATA5_MAP), .DATA6_MAP (DATA6_MAP), .DATA7_MAP (DATA7_MAP), .DATA8_MAP (DATA8_MAP), .DATA9_MAP (DATA9_MAP), .DATA10_MAP (DATA10_MAP), .DATA11_MAP (DATA11_MAP), .DATA12_MAP (DATA12_MAP), .DATA13_MAP (DATA13_MAP), .DATA14_MAP (DATA14_MAP), .DATA15_MAP (DATA15_MAP), .DATA16_MAP (DATA16_MAP), .DATA17_MAP (DATA17_MAP), .MASK0_MAP (MASK0_MAP), .MASK1_MAP (MASK1_MAP), .SIM_CAL_OPTION (SIM_CAL_OPTION), .MASTER_PHY_CTL (MASTER_PHY_CTL), .DRAM_WIDTH (DRAM_WIDTH), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) ) u_ddr_mc_phy_wrapper ( .rst (rst), .iddr_rst (iddr_rst), .clk (clk), // For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk // For memory frequencies below 400 MHz mem_refclk = mem_refclk and // freq_refclk = 2x or 4x mem_refclk such that it remains in the // 400~1066 MHz range .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .mmcm_ps_clk (mmcm_ps_clk), .pll_lock (pll_lock), .sync_pulse (sync_pulse), .idelayctrl_refclk (clk_ref), .phy_cmd_wr_en (mux_cmd_wren), .phy_data_wr_en (mux_wrdata_en), // phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23], // DataOffset[22:17],HiIndex[16:15],LowIndex[14:12], // AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]} // The fields ACTPRE, and BankCount are only used // when the hard PHY counters are used by the MC. .phy_ctl_wd ({5'd0, mux_cas_slot, calib_seq, mux_data_offset, mux_rank_cnt, 3'd0, aux_out_map, 5'd0, mux_cmd}), .phy_ctl_wr (mux_ctl_wren), .phy_if_empty_def (phy_if_empty_def), .phy_if_reset (phy_if_reset), .data_offset_1 (mux_data_offset_1), .data_offset_2 (mux_data_offset_2), .aux_in_1 (aux_out_map), .aux_in_2 (aux_out_map), .idelaye2_init_val (idelaye2_init_val), .oclkdelay_init_val (oclkdelay_init_val), .if_empty (if_empty), .phy_ctl_full (phy_ctl_full), .phy_cmd_full (phy_cmd_full), .phy_data_full (phy_data_full), .phy_pre_data_a_full (phy_pre_data_a_full), .ddr_clk (ddr_clk), .phy_mc_go (phy_mc_go), .phy_write_calib (phy_write_calib), .phy_read_calib (phy_read_calib), .po_fine_enable (po_enstg2_f), .po_coarse_enable (po_enstg2_c), .po_fine_inc (po_stg2_fincdec), .po_coarse_inc (po_stg2_cincdec), .po_counter_load_en (po_counter_load_en), .po_counter_read_en (1'b1), .po_sel_fine_oclk_delay (po_sel_stg2stg3), .po_counter_load_val (), .po_counter_read_val (po_counter_read_val), .pi_rst_dqs_find (rst_stg1_cal), .pi_fine_enable (pi_enstg2_f), .pi_fine_inc (pi_stg2_fincdec), .pi_counter_load_en (pi_stg2_load), .pi_counter_load_val (pi_stg2_reg_l), .pi_counter_read_val (pi_counter_read_val), .idelay_ce (idelay_ce), .idelay_inc (idelay_inc), .idelay_ld (idelay_ld), .pi_phase_locked (pi_phase_locked), .pi_phase_locked_all (pi_phase_locked_all), .pi_dqs_found (pi_found_dqs), .pi_dqs_found_all (pi_dqs_found_all), // Currently not being used. May be used in future if periodic reads // become a requirement. This output could also be used to signal a // catastrophic failure in read capture and the need for re-cal .pi_dqs_out_of_range (pi_dqs_out_of_range), .phy_init_data_sel (phy_init_data_sel), .calib_sel (calib_sel), .calib_in_common (calib_in_common), .calib_zero_inputs (calib_zero_inputs), .calib_zero_ctrl (calib_zero_ctrl), .mux_address (mux_address), .mux_bank (mux_bank), .mux_cs_n (mux_cs_n), .mux_ras_n (mux_ras_n), .mux_cas_n (mux_cas_n), .mux_we_n (mux_we_n), .mux_reset_n (mux_reset_n), .parity_in (parity), .mux_wrdata (mux_wrdata), .mux_wrdata_mask (mux_wrdata_mask), .mux_odt (mux_odt), .mux_cke (mux_cke), .idle (idle), .rd_data (rd_data_map), .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_cas_n (ddr_cas_n), .ddr_cke (ddr_cke), .ddr_cs_n (ddr_cs_n), .ddr_dm (ddr_dm), .ddr_odt (ddr_odt), .ddr_parity (ddr_parity), .ddr_ras_n (ddr_ras_n), .ddr_we_n (ddr_we_n), .ddr_dq (ddr_dq), .ddr_dqs (ddr_dqs), .ddr_dqs_n (ddr_dqs_n), .ddr_reset_n (ddr_reset_n), .dbg_pi_counter_read_en (1'b1), .ref_dll_lock (ref_dll_lock), .rst_phaser_ref (rst_phaser_ref), .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes), .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes), .byte_sel_cnt (byte_sel_cnt), .pd_out (pd_out), .fine_delay_incdec_pb (fine_delay_incdec_pb), .fine_delay_sel (fine_delay_sel) ); //*************************************************************************** // Soft memory initialization and calibration logic //*************************************************************************** mig_7series_v2_3_ddr_calib_top # ( .TCQ (TCQ), .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT), .nCK_PER_CLK (nCK_PER_CLK), .PRE_REV3ES (PRE_REV3ES), .tCK (tCK), .CLK_PERIOD (CLK_PERIOD), .N_CTL_LANES (N_CTL_LANES), .CTL_BYTE_LANE (CTL_BYTE_LANE), .CTL_BANK (CTL_BANK), .DRAM_TYPE (DRAM_TYPE), .PRBS_WIDTH (8), .DQS_BYTE_MAP (DQS_BYTE_MAP), .HIGHEST_BANK (HIGHEST_BANK), .BANK_TYPE (BANK_TYPE), .HIGHEST_LANE (HIGHEST_LANE), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .SLOT_1_CONFIG (SLOT_1_CONFIG), .BANK_WIDTH (BANK_WIDTH), .CA_MIRROR (CA_MIRROR), .COL_WIDTH (COL_WIDTH), .CKE_ODT_AUX (CKE_ODT_AUX), .nCS_PER_RANK (nCS_PER_RANK), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .ROW_WIDTH (ROW_WIDTH), .RANKS (RANKS), .CS_WIDTH (CS_WIDTH), .CKE_WIDTH (CKE_WIDTH), .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE), .PER_BIT_DESKEW ("OFF"), .CALIB_ROW_ADD (CALIB_ROW_ADD), .CALIB_COL_ADD (CALIB_COL_ADD), .CALIB_BA_ADD (CALIB_BA_ADD), .AL (AL), .BURST_MODE (BURST_MODE), .BURST_TYPE (BURST_TYPE), .nCL (CL), .nCWL (CWL), .tRFC (tRFC), .tREFI (tREFI), .OUTPUT_DRV (OUTPUT_DRV), .REG_CTRL (REG_CTRL), .ADDR_CMD_MODE (ADDR_CMD_MODE), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .WRLVL (WRLVL_W), .USE_ODT_PORT (USE_ODT_PORT), .SIM_INIT_OPTION (SIM_INIT_OPTION), .SIM_CAL_OPTION (SIM_CAL_OPTION), .DEBUG_PORT (DEBUG_PORT), .IDELAY_ADJ (IDELAY_ADJ), .FINE_PER_BIT (FINE_PER_BIT), .CENTER_COMP_MODE (CENTER_COMP_MODE), .PI_VAL_ADJ (PI_VAL_ADJ), .TAPSPERKCLK (TAPSPERKCLK), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) ) u_ddr_calib_top ( .clk (clk), .rst (rst), .tg_err (error), .rst_tg_mc (rst_tg_mc), .slot_0_present (slot_0_present), .slot_1_present (slot_1_present), // PHY Control Block and IN_FIFO status .phy_ctl_ready (phy_mc_go), .phy_ctl_full (1'b0), .phy_cmd_full (1'b0), .phy_data_full (1'b0), .phy_if_empty (if_empty), .idelaye2_init_val (idelaye2_init_val), .oclkdelay_init_val (oclkdelay_init_val), // From calib logic To data IN_FIFO // DQ IDELAY tap value from Calib logic // port to be added to mc_phy by Gary .dlyval_dq (), // hard PHY calibration modes .write_calib (phy_write_calib), .read_calib (phy_read_calib), // DQS count and ck/addr/cmd to be mapped to calib_sel // based on parameter that defines placement of ctl lanes // and DQS byte groups in each bank. When phy_write_calib // is de-asserted calib_sel should select CK/addr/cmd/ctl. .calib_sel (calib_sel), .calib_in_common (calib_in_common), .calib_zero_inputs (calib_zero_inputs), .calib_zero_ctrl (calib_zero_ctrl), .phy_if_empty_def (phy_if_empty_def), .phy_if_reset (phy_if_reset), // Signals from calib logic to be MUXED with MC // signals before sending to hard PHY .calib_ctl_wren (calib_ctl_wren), .calib_cmd_wren (calib_cmd_wren), .calib_seq (calib_seq), .calib_aux_out (calib_aux_out), .calib_odt (calib_odt), .calib_cke (calib_cke), .calib_cmd (calib_cmd), .calib_wrdata_en (calib_wrdata_en), .calib_rank_cnt (calib_rank_cnt), .calib_cas_slot (calib_cas_slot), .calib_data_offset_0 (calib_data_offset_0), .calib_data_offset_1 (calib_data_offset_1), .calib_data_offset_2 (calib_data_offset_2), .phy_reset_n (phy_reset_n), .phy_address (phy_address), .phy_bank (phy_bank), .phy_cs_n (phy_cs_n), .phy_ras_n (phy_ras_n), .phy_cas_n (phy_cas_n), .phy_we_n (phy_we_n), .phy_wrdata (phy_wrdata), // DQS Phaser_IN calibration/status signals .pi_phaselocked (pi_phase_locked), .pi_phase_locked_all (pi_phase_locked_all), .pi_found_dqs (pi_found_dqs), .pi_dqs_found_all (pi_dqs_found_all), .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes), .pi_rst_stg1_cal (rst_stg1_cal), .pi_en_stg2_f (pi_enstg2_f), .pi_stg2_f_incdec (pi_stg2_fincdec), .pi_stg2_load (pi_stg2_load), .pi_stg2_reg_l (pi_stg2_reg_l), .pi_counter_read_val (pi_counter_read_val), .device_temp (device_temp), .tempmon_sample_en (tempmon_sample_en), // IDELAY tap enable and inc signals .idelay_ce (idelay_ce), .idelay_inc (idelay_inc), .idelay_ld (idelay_ld), // DQS Phaser_OUT calibration/status signals .po_sel_stg2stg3 (po_sel_stg2stg3), .po_stg2_c_incdec (po_stg2_cincdec), .po_en_stg2_c (po_enstg2_c), .po_stg2_f_incdec (po_stg2_fincdec), .po_en_stg2_f (po_enstg2_f), .po_counter_load_en (po_counter_load_en), .po_counter_read_val (po_counter_read_val), // From data IN_FIFO To Calib logic and MC/UI .phy_rddata (rd_data_map), // From calib logic To MC .phy_rddata_valid (phy_rddata_valid_w), .calib_rd_data_offset_0 (calib_rd_data_offset_0), .calib_rd_data_offset_1 (calib_rd_data_offset_1), .calib_rd_data_offset_2 (calib_rd_data_offset_2), .calib_writes (), // Mem Init and Calibration status To MC .init_calib_complete (phy_init_data_sel), .init_wrcal_complete (init_wrcal_complete), // Debug Error signals .pi_phase_locked_err (dbg_pi_phaselock_err), .pi_dqsfound_err (dbg_pi_dqsfound_err), .wrcal_err (dbg_wrcal_err), //used for oclk stg3 centering .pd_out (pd_out), .psen (psen), .psincdec (psincdec), .psdone (psdone), .poc_sample_pd (poc_sample_pd), // Debug Signals .dbg_pi_phaselock_start (dbg_pi_phaselock_start), .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start), .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done), .dbg_wrlvl_start (dbg_wrlvl_start), .dbg_wrlvl_done (dbg_wrlvl_done), .dbg_wrlvl_err (dbg_wrlvl_err), .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), .dbg_phy_wrlvl (dbg_phy_wrlvl), .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl), .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), .dbg_wrcal_start (dbg_wrcal_start), .dbg_wrcal_done (dbg_wrcal_done), .dbg_phy_wrcal (dbg_phy_wrcal), .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt), .dbg_rdlvl_start (dbg_rdlvl_start), .dbg_rdlvl_done (dbg_rdlvl_done), .dbg_rdlvl_err (dbg_rdlvl_err), .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), .dbg_sel_pi_incdec (dbg_sel_pi_incdec), .dbg_sel_po_incdec (dbg_sel_po_incdec), .dbg_byte_sel (dbg_byte_sel), .dbg_pi_f_inc (dbg_pi_f_inc), .dbg_pi_f_dec (dbg_pi_f_dec), .dbg_po_f_inc (dbg_po_f_inc), .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel), .dbg_po_f_dec (dbg_po_f_dec), .dbg_idel_up_all (dbg_idel_up_all), .dbg_idel_down_all (dbg_idel_down_all), .dbg_idel_up_cpt (dbg_idel_up_cpt), .dbg_idel_down_cpt (dbg_idel_down_cpt), .dbg_sel_idel_cpt (dbg_sel_idel_cpt), .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), .dbg_phy_rdlvl (dbg_phy_rdlvl), .dbg_calib_top (dbg_calib_top), .dbg_phy_init (dbg_phy_init), .dbg_prbs_rdlvl (dbg_prbs_rdlvl), .dbg_dqs_found_cal (dbg_dqs_found_cal), .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal), .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data), .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start), .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done), .prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r), .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps), .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps), .byte_sel_cnt (byte_sel_cnt), .fine_delay_incdec_pb (fine_delay_incdec_pb), .fine_delay_sel (fine_delay_sel) ); endmodule
/********************************************************** -- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). A Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. // // THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. // // // Owner: Gary Martin // Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $ // $Author: gary $ // $DateTime: 2010/05/11 18:05:17 $ // $Change: 490882 $ // Description: // This verilog file is the parameterizable 4-byte lane phy primitive top // This module may be ganged to create an N-lane phy. // // History: // Date Engineer Description // 04/01/2010 G. Martin Initial Checkin. // /////////////////////////////////////////////////////////// **********************************************************/ `timescale 1ps/1ps `define PC_DATA_OFFSET_RANGE 22:17 module mig_7series_v2_3_ddr_phy_4lanes #( parameter GENERATE_IDELAYCTRL = "TRUE", parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010, parameter NUM_DDR_CK = 1, // next three parameter fields correspond to byte lanes for lane order DCBA parameter BYTE_LANES = 4'b1111, // lane existence, one per lane parameter DATA_CTL_N = 4'b1111, // data or control, per lane parameter BITLANES = 48'hffff_ffff_ffff, parameter BITLANES_OUTONLY = 48'h0000_0000_0000, parameter LANE_REMAP = 16'h3210,// 4-bit index // used to rewire to one of four // input/output buss lanes // example: 0321 remaps lanes as: // D->A // C->D // B->C // A->B parameter LAST_BANK = "FALSE", parameter USE_PRE_POST_FIFO = "FALSE", parameter RCLK_SELECT_LANE = "B", parameter real TCK = 0.00, parameter SYNTHESIS = "FALSE", parameter PO_CTL_COARSE_BYPASS = "FALSE", parameter PO_FINE_DELAY = 0, parameter PI_SEL_CLK_OFFSET = 0, // phy_control paramter used in other paramsters parameter PC_CLK_RATIO = 4, //phaser_in parameters parameter A_PI_FREQ_REF_DIV = "NONE", parameter A_PI_CLKOUT_DIV = 2, parameter A_PI_BURST_MODE = "TRUE", parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF", parameter A_PI_FINE_DELAY = 60, parameter A_PI_SYNC_IN_DIV_RST = "TRUE", parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter B_PI_BURST_MODE = A_PI_BURST_MODE, parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY, parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter C_PI_BURST_MODE = A_PI_BURST_MODE, parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter C_PI_FINE_DELAY = 0, parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter D_PI_BURST_MODE = A_PI_BURST_MODE, parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter D_PI_FINE_DELAY = 0, parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, //phaser_out parameters parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2, parameter A_PO_FINE_DELAY = PO_FINE_DELAY, parameter A_PO_COARSE_DELAY = 0, parameter A_PO_OCLK_DELAY = 0, parameter A_PO_OCLKDELAY_INV = "FALSE", parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF", parameter A_PO_SYNC_IN_DIV_RST = "TRUE", //parameter A_PO_SYNC_IN_DIV_RST = "FALSE", parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2, parameter B_PO_FINE_DELAY = PO_FINE_DELAY, parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2, parameter C_PO_FINE_DELAY = PO_FINE_DELAY, parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2, parameter D_PO_FINE_DELAY = PO_FINE_DELAY, parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE", parameter A_IDELAYE2_IDELAY_VALUE = 00, parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, // phy_control parameters parameter PC_BURST_MODE = "TRUE", parameter PC_DATA_CTL_N = DATA_CTL_N, parameter PC_CMD_OFFSET = 0, parameter PC_RD_CMD_OFFSET_0 = 0, parameter PC_RD_CMD_OFFSET_1 = 0, parameter PC_RD_CMD_OFFSET_2 = 0, parameter PC_RD_CMD_OFFSET_3 = 0, parameter PC_CO_DURATION = 1, parameter PC_DI_DURATION = 1, parameter PC_DO_DURATION = 1, parameter PC_RD_DURATION_0 = 0, parameter PC_RD_DURATION_1 = 0, parameter PC_RD_DURATION_2 = 0, parameter PC_RD_DURATION_3 = 0, parameter PC_WR_CMD_OFFSET_0 = 5, parameter PC_WR_CMD_OFFSET_1 = 5, parameter PC_WR_CMD_OFFSET_2 = 5, parameter PC_WR_CMD_OFFSET_3 = 5, parameter PC_WR_DURATION_0 = 6, parameter PC_WR_DURATION_1 = 6, parameter PC_WR_DURATION_2 = 6, parameter PC_WR_DURATION_3 = 6, parameter PC_AO_WRLVL_EN = 0, parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE) parameter PC_FOUR_WINDOW_CLOCKS = 63, parameter PC_EVENTS_DELAY = 18, parameter PC_PHY_COUNT_EN = "TRUE", parameter PC_SYNC_MODE = "TRUE", parameter PC_DISABLE_SEQ_MATCH = "TRUE", parameter PC_MULTI_REGION = "FALSE", // io fifo parameters parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter OF_ALMOST_EMPTY_VALUE = 1, parameter OF_ALMOST_FULL_VALUE = 1, parameter OF_OUTPUT_DISABLE = "TRUE", parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE, parameter A_OS_DATA_RATE = "DDR", parameter A_OS_DATA_WIDTH = 4, parameter B_OS_DATA_RATE = A_OS_DATA_RATE, parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter C_OS_DATA_RATE = A_OS_DATA_RATE, parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter D_OS_DATA_RATE = A_OS_DATA_RATE, parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8", parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter IF_ALMOST_EMPTY_VALUE = 1, parameter IF_ALMOST_FULL_VALUE = 1, parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE, // this is used locally, not for external pushdown // NOTE: the 0+ is needed in each to coerce to integer for addition. // otherwise 4x 1'b values are added producing a 1'b value. parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1), parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])), parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]), parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES, // assume odt per rank + any declared cke's parameter AUXOUT_WIDTH = 4, parameter LP_DDR_CK_WIDTH = 2 ,parameter CKE_ODT_AUX = "FALSE" ) ( //`include "phy.vh" input rst, input phy_clk, input phy_ctl_clk, input freq_refclk, input mem_refclk, input mem_refclk_div4, input pll_lock, input sync_pulse, input idelayctrl_refclk, input [HIGHEST_LANE*80-1:0] phy_dout, input phy_cmd_wr_en, input phy_data_wr_en, input phy_rd_en, input phy_ctl_mstr_empty, input [31:0] phy_ctl_wd, input [`PC_DATA_OFFSET_RANGE] data_offset, input phy_ctl_wr, input if_empty_def, input phyGo, input input_sink, output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory output rclk, output if_a_empty, output if_empty, output byte_rd_en, output if_empty_or, output if_empty_and, output of_ctl_a_full, output of_data_a_full, output of_ctl_full, output of_data_full, output pre_data_a_full, output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus output phy_ctl_empty, output phy_ctl_a_full, output phy_ctl_full, output [HIGHEST_LANE*12-1:0]mem_dq_out, output [HIGHEST_LANE*12-1:0]mem_dq_ts, input [HIGHEST_LANE*10-1:0]mem_dq_in, output [HIGHEST_LANE-1:0] mem_dqs_out, output [HIGHEST_LANE-1:0] mem_dqs_ts, input [HIGHEST_LANE-1:0] mem_dqs_in, input [1:0] byte_rd_en_oth_banks, output [AUXOUT_WIDTH-1:0] aux_out, output reg rst_out = 0, output reg mcGo=0, output phy_ctl_ready, output ref_dll_lock, input if_rst, input phy_read_calib, input phy_write_calib, input idelay_inc, input idelay_ce, input idelay_ld, input [2:0] calib_sel, input calib_zero_ctrl, input [HIGHEST_LANE-1:0] calib_zero_lanes, input calib_in_common, input po_fine_enable, input po_coarse_enable, input po_fine_inc, input po_coarse_inc, input po_counter_load_en, input po_counter_read_en, input [8:0] po_counter_load_val, input po_sel_fine_oclk_delay, output reg po_coarse_overflow, output reg po_fine_overflow, output reg [8:0] po_counter_read_val, input pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input pi_counter_read_en, input [5:0] pi_counter_load_val, output reg pi_fine_overflow, output reg [5:0] pi_counter_read_val, output reg pi_dqs_found, output pi_dqs_found_all, output pi_dqs_found_any, output [HIGHEST_LANE-1:0] pi_phase_locked_lanes, output [HIGHEST_LANE-1:0] pi_dqs_found_lanes, output reg pi_dqs_out_of_range, output reg pi_phase_locked, output pi_phase_locked_all, input [29:0] fine_delay, input fine_delay_sel ); localparam DATA_CTL_A = (~DATA_CTL_N[0]); localparam DATA_CTL_B = (~DATA_CTL_N[1]); localparam DATA_CTL_C = (~DATA_CTL_N[2]); localparam DATA_CTL_D = (~DATA_CTL_N[3]); localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0]; localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1]; localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2]; localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3]; localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0]; localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1]; localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2]; localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3]; localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE"; localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam IO_A_START = 41; localparam IO_A_END = 40; localparam IO_B_START = 43; localparam IO_B_END = 42; localparam IO_C_START = 45; localparam IO_C_END = 44; localparam IO_D_START = 47; localparam IO_D_END = 46; localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1; localparam IO_A_X_END = (IO_A_X_START-1); localparam IO_B_X_START = (IO_A_X_START + 2); localparam IO_B_X_END = (IO_B_X_START -1); localparam IO_C_X_START = (IO_B_X_START + 2); localparam IO_C_X_END = (IO_C_X_START -1); localparam IO_D_X_START = (IO_C_X_START + 2); localparam IO_D_X_END = (IO_D_X_START -1); localparam MSB_BURST_PEND_PO = 3; localparam MSB_BURST_PEND_PI = 7; localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8; localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1; wire [1:0] oserdes_dqs; wire [1:0] oserdes_dqs_ts; wire [1:0] oserdes_dq_ts; wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus; wire [7:0] in_rank; wire [11:0] IO_A; wire [11:0] IO_B; wire [11:0] IO_C; wire [11:0] IO_D; wire [319:0] phy_din_remap; reg A_po_counter_read_en; wire [8:0] A_po_counter_read_val; reg A_pi_counter_read_en; wire [5:0] A_pi_counter_read_val; wire A_pi_fine_overflow; wire A_po_coarse_overflow; wire A_po_fine_overflow; wire A_pi_dqs_found; wire A_pi_dqs_out_of_range; wire A_pi_phase_locked; wire A_pi_iserdes_rst; reg A_pi_fine_enable; reg A_pi_fine_inc; reg A_pi_counter_load_en; reg [5:0] A_pi_counter_load_val; reg A_pi_rst_dqs_find; reg A_po_fine_enable; reg A_po_coarse_enable; reg A_po_fine_inc /* synthesis syn_maxfan = 3 */; reg A_po_sel_fine_oclk_delay; reg A_po_coarse_inc; reg A_po_counter_load_en; reg [8:0] A_po_counter_load_val; wire A_rclk; reg A_idelay_ce; reg A_idelay_ld; reg [29:0] A_fine_delay; reg A_fine_delay_sel; reg B_po_counter_read_en; wire [8:0] B_po_counter_read_val; reg B_pi_counter_read_en; wire [5:0] B_pi_counter_read_val; wire B_pi_fine_overflow; wire B_po_coarse_overflow; wire B_po_fine_overflow; wire B_pi_phase_locked; wire B_pi_iserdes_rst; wire B_pi_dqs_found; wire B_pi_dqs_out_of_range; reg B_pi_fine_enable; reg B_pi_fine_inc; reg B_pi_counter_load_en; reg [5:0] B_pi_counter_load_val; reg B_pi_rst_dqs_find; reg B_po_fine_enable; reg B_po_coarse_enable; reg B_po_fine_inc /* synthesis syn_maxfan = 3 */; reg B_po_coarse_inc; reg B_po_sel_fine_oclk_delay; reg B_po_counter_load_en; reg [8:0] B_po_counter_load_val; wire B_rclk; reg B_idelay_ce; reg B_idelay_ld; reg [29:0] B_fine_delay; reg B_fine_delay_sel; reg C_pi_fine_inc; reg D_pi_fine_inc; reg C_pi_fine_enable; reg D_pi_fine_enable; reg C_po_counter_load_en; reg D_po_counter_load_en; reg C_po_coarse_inc; reg D_po_coarse_inc; reg C_po_fine_inc /* synthesis syn_maxfan = 3 */; reg D_po_fine_inc /* synthesis syn_maxfan = 3 */; reg C_po_sel_fine_oclk_delay; reg D_po_sel_fine_oclk_delay; reg [5:0] C_pi_counter_load_val; reg [5:0] D_pi_counter_load_val; reg [8:0] C_po_counter_load_val; reg [8:0] D_po_counter_load_val; reg C_po_coarse_enable; reg D_po_coarse_enable; reg C_po_fine_enable; reg D_po_fine_enable; wire C_po_coarse_overflow; wire D_po_coarse_overflow; wire C_po_fine_overflow; wire D_po_fine_overflow; wire [8:0] C_po_counter_read_val; wire [8:0] D_po_counter_read_val; reg C_po_counter_read_en; reg D_po_counter_read_en; wire C_pi_dqs_found; wire D_pi_dqs_found; wire C_pi_fine_overflow; wire D_pi_fine_overflow; reg C_pi_counter_read_en; reg D_pi_counter_read_en; reg C_pi_counter_load_en; reg D_pi_counter_load_en; wire C_pi_phase_locked; wire C_pi_iserdes_rst; wire D_pi_phase_locked; wire D_pi_iserdes_rst; wire C_pi_dqs_out_of_range; wire D_pi_dqs_out_of_range; wire [5:0] C_pi_counter_read_val; wire [5:0] D_pi_counter_read_val; wire C_rclk; wire D_rclk; reg C_idelay_ce; reg D_idelay_ce; reg C_idelay_ld; reg D_idelay_ld; reg C_pi_rst_dqs_find; reg D_pi_rst_dqs_find; reg [29:0] C_fine_delay; reg [29:0] D_fine_delay; reg C_fine_delay_sel; reg D_fine_delay_sel; wire pi_iserdes_rst; wire A_if_empty; wire B_if_empty; wire C_if_empty; wire D_if_empty; wire A_byte_rd_en; wire B_byte_rd_en; wire C_byte_rd_en; wire D_byte_rd_en; wire A_if_a_empty; wire B_if_a_empty; wire C_if_a_empty; wire D_if_a_empty; //wire A_if_full; //wire B_if_full; //wire C_if_full; //wire D_if_full; //wire A_of_empty; //wire B_of_empty; //wire C_of_empty; //wire D_of_empty; wire A_of_full; wire B_of_full; wire C_of_full; wire D_of_full; wire A_of_ctl_full; wire B_of_ctl_full; wire C_of_ctl_full; wire D_of_ctl_full; wire A_of_data_full; wire B_of_data_full; wire C_of_data_full; wire D_of_data_full; wire A_of_a_full; wire B_of_a_full; wire C_of_a_full; wire D_of_a_full; wire A_pre_fifo_a_full; wire B_pre_fifo_a_full; wire C_pre_fifo_a_full; wire D_pre_fifo_a_full; wire A_of_ctl_a_full; wire B_of_ctl_a_full; wire C_of_ctl_a_full; wire D_of_ctl_a_full; wire A_of_data_a_full; wire B_of_data_a_full; wire C_of_data_a_full; wire D_of_data_a_full; wire A_pre_data_a_full; wire B_pre_data_a_full; wire C_pre_data_a_full; wire D_pre_data_a_full; wire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation wire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; // wire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; // wire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; // wire [3:0] dummy_data; wire [31:0] _phy_ctl_wd; wire [1:0] phy_encalib; assign pi_dqs_found_all = (! PRESENT_DATA_A | A_pi_dqs_found) & (! PRESENT_DATA_B | B_pi_dqs_found) & (! PRESENT_DATA_C | C_pi_dqs_found) & (! PRESENT_DATA_D | D_pi_dqs_found) ; assign pi_dqs_found_any = ( PRESENT_DATA_A & A_pi_dqs_found) | ( PRESENT_DATA_B & B_pi_dqs_found) | ( PRESENT_DATA_C & C_pi_dqs_found) | ( PRESENT_DATA_D & D_pi_dqs_found) ; assign pi_phase_locked_all = (! PRESENT_DATA_A | A_pi_phase_locked) & (! PRESENT_DATA_B | B_pi_phase_locked) & (! PRESENT_DATA_C | C_pi_phase_locked) & (! PRESENT_DATA_D | D_pi_phase_locked); wire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal // which is combined into another signals such that // the other signal isn't changed. The purpose // is to fake the tools into ignoring dangling inputs. // Because it is anded with 1'b0, the contributing signals // are folded as constants or trimmed. assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty); assign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) : (A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en); assign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty); assign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty); assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty; //assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ; //assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty; assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ; assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ; assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ; assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ; assign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full; function [79:0] part_select_80; input [319:0] vector; input [1:0] select; begin case (select) 2'b00 : part_select_80[79:0] = vector[1*80-1:0*80]; 2'b01 : part_select_80[79:0] = vector[2*80-1:1*80]; 2'b10 : part_select_80[79:0] = vector[3*80-1:2*80]; 2'b11 : part_select_80[79:0] = vector[4*80-1:3*80]; endcase end endfunction wire [319:0] phy_dout_remap; reg rst_out_trig = 1'b0; reg [31:0] rclk_delay; reg rst_edge1 = 1'b0; reg rst_edge2 = 1'b0; reg rst_edge3 = 1'b0; reg rst_edge_detect = 1'b0; wire rclk_; reg rst_out_start = 1'b0 ; reg rst_primitives=0; reg A_rst_primitives=0; reg B_rst_primitives=0; reg C_rst_primitives=0; reg D_rst_primitives=0; `ifdef USE_PHY_CONTROL_TEST wire [15:0] test_output; wire [15:0] test_input; wire [2:0] test_select=0; wire scan_enable = 0; `endif generate genvar i; if (RCLK_SELECT_LANE == "A") begin assign rclk_ = A_rclk; assign pi_iserdes_rst = A_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "B") begin assign rclk_ = B_rclk; assign pi_iserdes_rst = B_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "C") begin assign rclk_ = C_rclk; assign pi_iserdes_rst = C_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "D") begin assign rclk_ = D_rclk; assign pi_iserdes_rst = D_pi_iserdes_rst; end else begin assign rclk_ = B_rclk; // default end endgenerate assign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk; assign pi_phase_locked_lanes = {(! PRESENT_DATA_A[0] | A_pi_phase_locked), (! PRESENT_DATA_B[0] | B_pi_phase_locked) , (! PRESENT_DATA_C[0] | C_pi_phase_locked) , (! PRESENT_DATA_D[0] | D_pi_phase_locked)}; assign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found}; // this block scrubs X from rclk_delay[11] reg rclk_delay_11; always @(rclk_delay[11]) begin : rclk_delay_11_blk if ( rclk_delay[11]) rclk_delay_11 = 1; else rclk_delay_11 = 0; end always @(posedge phy_clk or posedge rst ) begin // scrub 4-state values from rclk_delay[11] if ( rst) begin rst_out <= #1 0; end else begin if ( rclk_delay_11) rst_out <= #1 1; end end always @(posedge phy_clk ) begin // phy_ctl_ready drives reset of the system rst_primitives <= !phy_ctl_ready ; A_rst_primitives <= rst_primitives ; B_rst_primitives <= rst_primitives ; C_rst_primitives <= rst_primitives ; D_rst_primitives <= rst_primitives ; rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo); mcGo <= #1 rst_out ; end generate if (BYTE_LANES[0]) begin assign dummy_data[0] = 0; end else begin assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80]; end if (BYTE_LANES[1]) begin assign dummy_data[1] = 0; end else begin assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80]; end if (BYTE_LANES[2]) begin assign dummy_data[2] = 0; end else begin assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80]; end if (BYTE_LANES[3]) begin assign dummy_data[3] = 0; end else begin assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80]; end if (PRESENT_DATA_A) begin assign A_of_data_full = A_of_full; assign A_of_ctl_full = 0; assign A_of_data_a_full = A_of_a_full; assign A_of_ctl_a_full = 0; assign A_pre_data_a_full = A_pre_fifo_a_full; end else begin assign A_of_ctl_full = A_of_full; assign A_of_data_full = 0; assign A_of_ctl_a_full = A_of_a_full; assign A_of_data_a_full = 0; assign A_pre_data_a_full = 0; end if (PRESENT_DATA_B) begin assign B_of_data_full = B_of_full; assign B_of_ctl_full = 0; assign B_of_data_a_full = B_of_a_full; assign B_of_ctl_a_full = 0; assign B_pre_data_a_full = B_pre_fifo_a_full; end else begin assign B_of_ctl_full = B_of_full; assign B_of_data_full = 0; assign B_of_ctl_a_full = B_of_a_full; assign B_of_data_a_full = 0; assign B_pre_data_a_full = 0; end if (PRESENT_DATA_C) begin assign C_of_data_full = C_of_full; assign C_of_ctl_full = 0; assign C_of_data_a_full = C_of_a_full; assign C_of_ctl_a_full = 0; assign C_pre_data_a_full = C_pre_fifo_a_full; end else begin assign C_of_ctl_full = C_of_full; assign C_of_data_full = 0; assign C_of_ctl_a_full = C_of_a_full; assign C_of_data_a_full = 0; assign C_pre_data_a_full = 0; end if (PRESENT_DATA_D) begin assign D_of_data_full = D_of_full; assign D_of_ctl_full = 0; assign D_of_data_a_full = D_of_a_full; assign D_of_ctl_a_full = 0; assign D_pre_data_a_full = D_pre_fifo_a_full; end else begin assign D_of_ctl_full = D_of_full; assign D_of_data_full = 0; assign D_of_ctl_a_full = D_of_a_full; assign D_of_data_a_full = 0; assign D_pre_data_a_full = 0; end // byte lane must exist and be data lane. if (PRESENT_DATA_A ) case ( LANE_REMAP[1:0] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0]; endcase else case ( LANE_REMAP[1:0] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_B ) case ( LANE_REMAP[5:4] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80]; endcase else if (HIGHEST_LANE > 1) case ( LANE_REMAP[5:4] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_C) case ( LANE_REMAP[9:8] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160]; endcase else if (HIGHEST_LANE > 2) case ( LANE_REMAP[9:8] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_D ) case ( LANE_REMAP[13:12] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240]; endcase else if (HIGHEST_LANE > 3) case ( LANE_REMAP[13:12] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (HIGHEST_LANE > 1) assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]}; if (HIGHEST_LANE == 1) assign _phy_ctl_wd = phy_ctl_wd; //BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst)); BUFIO rclk_buf(.I(rclk_), .O(rclk) ); if ( BYTE_LANES[0] ) begin : ddr_byte_lane_A assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("A"), .PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[11:0]), .BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (A_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (A_PI_BURST_MODE), .PI_CLKOUT_DIV (A_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV), .PI_FINE_DELAY (A_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (A_PO_CLKOUT_DIV), .PO_FINE_DELAY (A_PO_FINE_DELAY), .PO_COARSE_BYPASS (A_PO_COARSE_BYPASS), .PO_COARSE_DELAY (A_PO_COARSE_DELAY), .PO_OCLK_DELAY (A_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (A_OS_DATA_RATE), .OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_A( .mem_dq_out (mem_dq_out[11:0]), .mem_dq_ts (mem_dq_ts[11:0]), .mem_dq_in (mem_dq_in[9:0]), .mem_dqs_out (mem_dqs_out[0]), .mem_dqs_ts (mem_dqs_ts[0]), .mem_dqs_in (mem_dqs_in[0]), .rst (A_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (A_ddr_clk), .rclk (A_rclk), .pi_dqs_found (A_pi_dqs_found), .dqs_out_of_range (A_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (A_if_a_empty), .if_empty (A_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*A_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*A_of_empty*/), .of_a_full (A_of_a_full), .of_full (A_of_full), .pre_fifo_a_full (A_pre_fifo_a_full), .phy_din (phy_din_remap[79:0]), .phy_dout (phy_dout_remap[79:0]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (A_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (A_idelay_ce), .idelay_ld (A_idelay_ld), .pi_rst_dqs_find (A_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (A_po_fine_enable), .po_coarse_enable (A_po_coarse_enable), .po_fine_inc (A_po_fine_inc), .po_coarse_inc (A_po_coarse_inc), .po_counter_load_en (A_po_counter_load_en), .po_counter_read_en (A_po_counter_read_en), .po_counter_load_val (A_po_counter_load_val), .po_coarse_overflow (A_po_coarse_overflow), .po_fine_overflow (A_po_fine_overflow), .po_counter_read_val (A_po_counter_read_val), .po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (A_pi_fine_enable), .pi_fine_inc (A_pi_fine_inc), .pi_counter_load_en (A_pi_counter_load_en), .pi_counter_read_en (A_pi_counter_read_en), .pi_counter_load_val (A_pi_counter_load_val), .pi_fine_overflow (A_pi_fine_overflow), .pi_counter_read_val (A_pi_counter_read_val), .pi_iserdes_rst (A_pi_iserdes_rst), .pi_phase_locked (A_pi_phase_locked), .fine_delay (A_fine_delay), .fine_delay_sel (A_fine_delay_sel) ); end else begin : no_ddr_byte_lane_A assign A_of_a_full = 1'b0; assign A_of_full = 1'b0; assign A_pre_fifo_a_full = 1'b0; assign A_if_empty = 1'b0; assign A_byte_rd_en = 1'b1; assign A_if_a_empty = 1'b0; assign A_pi_phase_locked = 1; assign A_pi_dqs_found = 1; assign A_rclk = 0; assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign A_pi_counter_read_val = 0; assign A_po_counter_read_val = 0; assign A_pi_fine_overflow = 0; assign A_po_coarse_overflow = 0; assign A_po_fine_overflow = 0; end if ( BYTE_LANES[1] ) begin : ddr_byte_lane_B assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("B"), .PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[23:12]), .BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (B_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (B_PI_BURST_MODE), .PI_CLKOUT_DIV (B_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV), .PI_FINE_DELAY (B_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (B_PO_CLKOUT_DIV), .PO_FINE_DELAY (B_PO_FINE_DELAY), .PO_COARSE_BYPASS (B_PO_COARSE_BYPASS), .PO_COARSE_DELAY (B_PO_COARSE_DELAY), .PO_OCLK_DELAY (B_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (B_OS_DATA_RATE), .OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_B( .mem_dq_out (mem_dq_out[23:12]), .mem_dq_ts (mem_dq_ts[23:12]), .mem_dq_in (mem_dq_in[19:10]), .mem_dqs_out (mem_dqs_out[1]), .mem_dqs_ts (mem_dqs_ts[1]), .mem_dqs_in (mem_dqs_in[1]), .rst (B_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (B_ddr_clk), .rclk (B_rclk), .pi_dqs_found (B_pi_dqs_found), .dqs_out_of_range (B_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (B_if_a_empty), .if_empty (B_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*B_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*B_of_empty*/), .of_a_full (B_of_a_full), .of_full (B_of_full), .pre_fifo_a_full (B_pre_fifo_a_full), .phy_din (phy_din_remap[159:80]), .phy_dout (phy_dout_remap[159:80]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (B_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (B_idelay_ce), .idelay_ld (B_idelay_ld), .pi_rst_dqs_find (B_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (B_po_fine_enable), .po_coarse_enable (B_po_coarse_enable), .po_fine_inc (B_po_fine_inc), .po_coarse_inc (B_po_coarse_inc), .po_counter_load_en (B_po_counter_load_en), .po_counter_read_en (B_po_counter_read_en), .po_counter_load_val (B_po_counter_load_val), .po_coarse_overflow (B_po_coarse_overflow), .po_fine_overflow (B_po_fine_overflow), .po_counter_read_val (B_po_counter_read_val), .po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (B_pi_fine_enable), .pi_fine_inc (B_pi_fine_inc), .pi_counter_load_en (B_pi_counter_load_en), .pi_counter_read_en (B_pi_counter_read_en), .pi_counter_load_val (B_pi_counter_load_val), .pi_fine_overflow (B_pi_fine_overflow), .pi_counter_read_val (B_pi_counter_read_val), .pi_iserdes_rst (B_pi_iserdes_rst), .pi_phase_locked (B_pi_phase_locked), .fine_delay (B_fine_delay), .fine_delay_sel (B_fine_delay_sel) ); end else begin : no_ddr_byte_lane_B assign B_of_a_full = 1'b0; assign B_of_full = 1'b0; assign B_pre_fifo_a_full = 1'b0; assign B_if_empty = 1'b0; assign B_if_a_empty = 1'b0; assign B_byte_rd_en = 1'b1; assign B_pi_phase_locked = 1; assign B_pi_dqs_found = 1; assign B_rclk = 0; assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign B_pi_counter_read_val = 0; assign B_po_counter_read_val = 0; assign B_pi_fine_overflow = 0; assign B_po_coarse_overflow = 0; assign B_po_fine_overflow = 0; end if ( BYTE_LANES[2] ) begin : ddr_byte_lane_C assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("C"), .PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[35:24]), .BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (C_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (C_PI_BURST_MODE), .PI_CLKOUT_DIV (C_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV), .PI_FINE_DELAY (C_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (C_PO_CLKOUT_DIV), .PO_FINE_DELAY (C_PO_FINE_DELAY), .PO_COARSE_BYPASS (C_PO_COARSE_BYPASS), .PO_COARSE_DELAY (C_PO_COARSE_DELAY), .PO_OCLK_DELAY (C_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (C_OS_DATA_RATE), .OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_C( .mem_dq_out (mem_dq_out[35:24]), .mem_dq_ts (mem_dq_ts[35:24]), .mem_dq_in (mem_dq_in[29:20]), .mem_dqs_out (mem_dqs_out[2]), .mem_dqs_ts (mem_dqs_ts[2]), .mem_dqs_in (mem_dqs_in[2]), .rst (C_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (C_ddr_clk), .rclk (C_rclk), .pi_dqs_found (C_pi_dqs_found), .dqs_out_of_range (C_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (C_if_a_empty), .if_empty (C_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*C_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*C_of_empty*/), .of_a_full (C_of_a_full), .of_full (C_of_full), .pre_fifo_a_full (C_pre_fifo_a_full), .phy_din (phy_din_remap[239:160]), .phy_dout (phy_dout_remap[239:160]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (C_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (C_idelay_ce), .idelay_ld (C_idelay_ld), .pi_rst_dqs_find (C_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (C_po_fine_enable), .po_coarse_enable (C_po_coarse_enable), .po_fine_inc (C_po_fine_inc), .po_coarse_inc (C_po_coarse_inc), .po_counter_load_en (C_po_counter_load_en), .po_counter_read_en (C_po_counter_read_en), .po_counter_load_val (C_po_counter_load_val), .po_coarse_overflow (C_po_coarse_overflow), .po_fine_overflow (C_po_fine_overflow), .po_counter_read_val (C_po_counter_read_val), .po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (C_pi_fine_enable), .pi_fine_inc (C_pi_fine_inc), .pi_counter_load_en (C_pi_counter_load_en), .pi_counter_read_en (C_pi_counter_read_en), .pi_counter_load_val (C_pi_counter_load_val), .pi_fine_overflow (C_pi_fine_overflow), .pi_counter_read_val (C_pi_counter_read_val), .pi_iserdes_rst (C_pi_iserdes_rst), .pi_phase_locked (C_pi_phase_locked), .fine_delay (C_fine_delay), .fine_delay_sel (C_fine_delay_sel) ); end else begin : no_ddr_byte_lane_C assign C_of_a_full = 1'b0; assign C_of_full = 1'b0; assign C_pre_fifo_a_full = 1'b0; assign C_if_empty = 1'b0; assign C_byte_rd_en = 1'b1; assign C_if_a_empty = 1'b0; assign C_pi_phase_locked = 1; assign C_pi_dqs_found = 1; assign C_rclk = 0; assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign C_pi_counter_read_val = 0; assign C_po_counter_read_val = 0; assign C_pi_fine_overflow = 0; assign C_po_coarse_overflow = 0; assign C_po_fine_overflow = 0; end if ( BYTE_LANES[3] ) begin : ddr_byte_lane_D assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("D"), .PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[47:36]), .BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (D_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (D_PI_BURST_MODE), .PI_CLKOUT_DIV (D_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV), .PI_FINE_DELAY (D_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (D_PO_CLKOUT_DIV), .PO_FINE_DELAY (D_PO_FINE_DELAY), .PO_COARSE_BYPASS (D_PO_COARSE_BYPASS), .PO_COARSE_DELAY (D_PO_COARSE_DELAY), .PO_OCLK_DELAY (D_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (D_OS_DATA_RATE), .OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_D( .mem_dq_out (mem_dq_out[47:36]), .mem_dq_ts (mem_dq_ts[47:36]), .mem_dq_in (mem_dq_in[39:30]), .mem_dqs_out (mem_dqs_out[3]), .mem_dqs_ts (mem_dqs_ts[3]), .mem_dqs_in (mem_dqs_in[3]), .rst (D_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (D_ddr_clk), .rclk (D_rclk), .pi_dqs_found (D_pi_dqs_found), .dqs_out_of_range (D_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (D_if_a_empty), .if_empty (D_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*D_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*D_of_empty*/), .of_a_full (D_of_a_full), .of_full (D_of_full), .pre_fifo_a_full (D_pre_fifo_a_full), .phy_din (phy_din_remap[319:240]), .phy_dout (phy_dout_remap[319:240]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .idelay_inc (idelay_inc), .idelay_ce (D_idelay_ce), .idelay_ld (D_idelay_ld), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (D_byte_rd_en), // calibration signals .pi_rst_dqs_find (D_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (D_po_fine_enable), .po_coarse_enable (D_po_coarse_enable), .po_fine_inc (D_po_fine_inc), .po_coarse_inc (D_po_coarse_inc), .po_counter_load_en (D_po_counter_load_en), .po_counter_read_en (D_po_counter_read_en), .po_counter_load_val (D_po_counter_load_val), .po_coarse_overflow (D_po_coarse_overflow), .po_fine_overflow (D_po_fine_overflow), .po_counter_read_val (D_po_counter_read_val), .po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (D_pi_fine_enable), .pi_fine_inc (D_pi_fine_inc), .pi_counter_load_en (D_pi_counter_load_en), .pi_counter_read_en (D_pi_counter_read_en), .pi_counter_load_val (D_pi_counter_load_val), .pi_fine_overflow (D_pi_fine_overflow), .pi_counter_read_val (D_pi_counter_read_val), .pi_iserdes_rst (D_pi_iserdes_rst), .pi_phase_locked (D_pi_phase_locked), .fine_delay (D_fine_delay), .fine_delay_sel (D_fine_delay_sel) ); end else begin : no_ddr_byte_lane_D assign D_of_a_full = 1'b0; assign D_of_full = 1'b0; assign D_pre_fifo_a_full = 1'b0; assign D_if_empty = 1'b0; assign D_byte_rd_en = 1'b1; assign D_if_a_empty = 1'b0; assign D_rclk = 0; assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign D_pi_dqs_found = 1; assign D_pi_phase_locked = 1; assign D_pi_counter_read_val = 0; assign D_po_counter_read_val = 0; assign D_pi_fine_overflow = 0; assign D_po_coarse_overflow = 0; assign D_po_fine_overflow = 0; end endgenerate assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank; PHY_CONTROL #( .AO_WRLVL_EN ( PC_AO_WRLVL_EN), .AO_TOGGLE ( PC_AO_TOGGLE), .BURST_MODE ( PC_BURST_MODE), .CO_DURATION ( PC_CO_DURATION ), .CLK_RATIO ( PC_CLK_RATIO), .DATA_CTL_A_N ( PC_DATA_CTL_A), .DATA_CTL_B_N ( PC_DATA_CTL_B), .DATA_CTL_C_N ( PC_DATA_CTL_C), .DATA_CTL_D_N ( PC_DATA_CTL_D), .DI_DURATION ( PC_DI_DURATION ), .DO_DURATION ( PC_DO_DURATION ), .EVENTS_DELAY ( PC_EVENTS_DELAY), .FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS), .MULTI_REGION ( PC_MULTI_REGION ), .PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN), .DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH), .SYNC_MODE ( PC_SYNC_MODE), .CMD_OFFSET ( PC_CMD_OFFSET), .RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0), .RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1), .RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2), .RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3), .RD_DURATION_0 ( PC_RD_DURATION_0), .RD_DURATION_1 ( PC_RD_DURATION_1), .RD_DURATION_2 ( PC_RD_DURATION_2), .RD_DURATION_3 ( PC_RD_DURATION_3), .WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0), .WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1), .WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2), .WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3), .WR_DURATION_0 ( PC_WR_DURATION_0), .WR_DURATION_1 ( PC_WR_DURATION_1), .WR_DURATION_2 ( PC_WR_DURATION_2), .WR_DURATION_3 ( PC_WR_DURATION_3) ) phy_control_i ( .AUXOUTPUT (aux_out), .INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]), .INRANKA (in_rank[1:0]), .INRANKB (in_rank[3:2]), .INRANKC (in_rank[5:4]), .INRANKD (in_rank[7:6]), .OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]), .PCENABLECALIB (phy_encalib), .PHYCTLALMOSTFULL (phy_ctl_a_full), .PHYCTLEMPTY (phy_ctl_empty), .PHYCTLFULL (phy_ctl_full), .PHYCTLREADY (phy_ctl_ready), .MEMREFCLK (mem_refclk), .PHYCLK (phy_ctl_clk), .PHYCTLMSTREMPTY (phy_ctl_mstr_empty), .PHYCTLWD (_phy_ctl_wd), .PHYCTLWRENABLE (phy_ctl_wr), .PLLLOCK (pll_lock), .REFDLLLOCK (ref_dll_lock), // is reset while !locked .RESET (rst), .SYNCIN (sync_pulse), .READCALIBENABLE (phy_read_calib), .WRITECALIBENABLE (phy_write_calib) `ifdef USE_PHY_CONTROL_TEST , .TESTINPUT (16'b0), .TESTOUTPUT (test_output), .TESTSELECT (test_select), .SCANENABLEN (scan_enable) `endif ); // register outputs to give extra slack in timing always @(posedge phy_clk ) begin case (calib_sel[1:0]) 2'h0: begin po_coarse_overflow <= #1 A_po_coarse_overflow; po_fine_overflow <= #1 A_po_fine_overflow; po_counter_read_val <= #1 A_po_counter_read_val; pi_fine_overflow <= #1 A_pi_fine_overflow; pi_counter_read_val<= #1 A_pi_counter_read_val; pi_phase_locked <= #1 A_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 A_pi_dqs_found; pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range; end 2'h1: begin po_coarse_overflow <= #1 B_po_coarse_overflow; po_fine_overflow <= #1 B_po_fine_overflow; po_counter_read_val <= #1 B_po_counter_read_val; pi_fine_overflow <= #1 B_pi_fine_overflow; pi_counter_read_val <= #1 B_pi_counter_read_val; pi_phase_locked <= #1 B_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 B_pi_dqs_found; pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range; end 2'h2: begin po_coarse_overflow <= #1 C_po_coarse_overflow; po_fine_overflow <= #1 C_po_fine_overflow; po_counter_read_val <= #1 C_po_counter_read_val; pi_fine_overflow <= #1 C_pi_fine_overflow; pi_counter_read_val <= #1 C_pi_counter_read_val; pi_phase_locked <= #1 C_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 C_pi_dqs_found; pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range; end 2'h3: begin po_coarse_overflow <= #1 D_po_coarse_overflow; po_fine_overflow <= #1 D_po_fine_overflow; po_counter_read_val <= #1 D_po_counter_read_val; pi_fine_overflow <= #1 D_pi_fine_overflow; pi_counter_read_val <= #1 D_pi_counter_read_val; pi_phase_locked <= #1 D_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 D_pi_dqs_found; pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range; end default: begin po_coarse_overflow <= po_coarse_overflow; end endcase end wire B_mux_ctrl; wire C_mux_ctrl; wire D_mux_ctrl; generate if (HIGHEST_LANE > 1) assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1])); else assign B_mux_ctrl = 0; if (HIGHEST_LANE > 2) assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2])); else assign C_mux_ctrl = 0; if (HIGHEST_LANE > 3) assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3])); else assign D_mux_ctrl = 0; endgenerate always @(*) begin A_pi_fine_enable = 0; A_pi_fine_inc = 0; A_pi_counter_load_en = 0; A_pi_counter_read_en = 0; A_pi_counter_load_val = 0; A_pi_rst_dqs_find = 0; A_po_fine_enable = 0; A_po_coarse_enable = 0; A_po_fine_inc = 0; A_po_coarse_inc = 0; A_po_counter_load_en = 0; A_po_counter_read_en = 0; A_po_counter_load_val = 0; A_po_sel_fine_oclk_delay = 0; A_idelay_ce = 0; A_idelay_ld = 0; A_fine_delay = 0; A_fine_delay_sel = 0; B_pi_fine_enable = 0; B_pi_fine_inc = 0; B_pi_counter_load_en = 0; B_pi_counter_read_en = 0; B_pi_counter_load_val = 0; B_pi_rst_dqs_find = 0; B_po_fine_enable = 0; B_po_coarse_enable = 0; B_po_fine_inc = 0; B_po_coarse_inc = 0; B_po_counter_load_en = 0; B_po_counter_read_en = 0; B_po_counter_load_val = 0; B_po_sel_fine_oclk_delay = 0; B_idelay_ce = 0; B_idelay_ld = 0; B_fine_delay = 0; B_fine_delay_sel = 0; C_pi_fine_enable = 0; C_pi_fine_inc = 0; C_pi_counter_load_en = 0; C_pi_counter_read_en = 0; C_pi_counter_load_val = 0; C_pi_rst_dqs_find = 0; C_po_fine_enable = 0; C_po_coarse_enable = 0; C_po_fine_inc = 0; C_po_coarse_inc = 0; C_po_counter_load_en = 0; C_po_counter_read_en = 0; C_po_counter_load_val = 0; C_po_sel_fine_oclk_delay = 0; C_idelay_ce = 0; C_idelay_ld = 0; C_fine_delay = 0; C_fine_delay_sel = 0; D_pi_fine_enable = 0; D_pi_fine_inc = 0; D_pi_counter_load_en = 0; D_pi_counter_read_en = 0; D_pi_counter_load_val = 0; D_pi_rst_dqs_find = 0; D_po_fine_enable = 0; D_po_coarse_enable = 0; D_po_fine_inc = 0; D_po_coarse_inc = 0; D_po_counter_load_en = 0; D_po_counter_read_en = 0; D_po_counter_load_val = 0; D_po_sel_fine_oclk_delay = 0; D_idelay_ce = 0; D_idelay_ld = 0; D_fine_delay = 0; D_fine_delay_sel = 0; if ( calib_sel[2]) begin // if this is asserted, all calib signals are deasserted A_pi_fine_enable = 0; A_pi_fine_inc = 0; A_pi_counter_load_en = 0; A_pi_counter_read_en = 0; A_pi_counter_load_val = 0; A_pi_rst_dqs_find = 0; A_po_fine_enable = 0; A_po_coarse_enable = 0; A_po_fine_inc = 0; A_po_coarse_inc = 0; A_po_counter_load_en = 0; A_po_counter_read_en = 0; A_po_counter_load_val = 0; A_po_sel_fine_oclk_delay = 0; A_idelay_ce = 0; A_idelay_ld = 0; A_fine_delay = 0; A_fine_delay_sel = 0; B_pi_fine_enable = 0; B_pi_fine_inc = 0; B_pi_counter_load_en = 0; B_pi_counter_read_en = 0; B_pi_counter_load_val = 0; B_pi_rst_dqs_find = 0; B_po_fine_enable = 0; B_po_coarse_enable = 0; B_po_fine_inc = 0; B_po_coarse_inc = 0; B_po_counter_load_en = 0; B_po_counter_read_en = 0; B_po_counter_load_val = 0; B_po_sel_fine_oclk_delay = 0; B_idelay_ce = 0; B_idelay_ld = 0; B_fine_delay = 0; B_fine_delay_sel = 0; C_pi_fine_enable = 0; C_pi_fine_inc = 0; C_pi_counter_load_en = 0; C_pi_counter_read_en = 0; C_pi_counter_load_val = 0; C_pi_rst_dqs_find = 0; C_po_fine_enable = 0; C_po_coarse_enable = 0; C_po_fine_inc = 0; C_po_coarse_inc = 0; C_po_counter_load_en = 0; C_po_counter_read_en = 0; C_po_counter_load_val = 0; C_po_sel_fine_oclk_delay = 0; C_idelay_ce = 0; C_idelay_ld = 0; C_fine_delay = 0; C_fine_delay_sel = 0; D_pi_fine_enable = 0; D_pi_fine_inc = 0; D_pi_counter_load_en = 0; D_pi_counter_read_en = 0; D_pi_counter_load_val = 0; D_pi_rst_dqs_find = 0; D_po_fine_enable = 0; D_po_coarse_enable = 0; D_po_fine_inc = 0; D_po_coarse_inc = 0; D_po_counter_load_en = 0; D_po_counter_read_en = 0; D_po_counter_load_val = 0; D_po_sel_fine_oclk_delay = 0; D_idelay_ce = 0; D_idelay_ld = 0; D_fine_delay = 0; D_fine_delay_sel = 0; end else if (calib_in_common) begin // if this is asserted, each signal is broadcast to all phasers // in common if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin A_pi_fine_enable = pi_fine_enable; A_pi_fine_inc = pi_fine_inc; A_pi_counter_load_en = pi_counter_load_en; A_pi_counter_read_en = pi_counter_read_en; A_pi_counter_load_val = pi_counter_load_val; A_pi_rst_dqs_find = pi_rst_dqs_find; A_po_fine_enable = po_fine_enable; A_po_coarse_enable = po_coarse_enable; A_po_fine_inc = po_fine_inc; A_po_coarse_inc = po_coarse_inc; A_po_counter_load_en = po_counter_load_en; A_po_counter_read_en = po_counter_read_en; A_po_counter_load_val = po_counter_load_val; A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; A_idelay_ce = idelay_ce; A_idelay_ld = idelay_ld; A_fine_delay = fine_delay ; A_fine_delay_sel = fine_delay_sel; end if ( B_mux_ctrl) begin B_pi_fine_enable = pi_fine_enable; B_pi_fine_inc = pi_fine_inc; B_pi_counter_load_en = pi_counter_load_en; B_pi_counter_read_en = pi_counter_read_en; B_pi_counter_load_val = pi_counter_load_val; B_pi_rst_dqs_find = pi_rst_dqs_find; B_po_fine_enable = po_fine_enable; B_po_coarse_enable = po_coarse_enable; B_po_fine_inc = po_fine_inc; B_po_coarse_inc = po_coarse_inc; B_po_counter_load_en = po_counter_load_en; B_po_counter_read_en = po_counter_read_en; B_po_counter_load_val = po_counter_load_val; B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; B_idelay_ce = idelay_ce; B_idelay_ld = idelay_ld; B_fine_delay = fine_delay ; B_fine_delay_sel = fine_delay_sel; end if ( C_mux_ctrl) begin C_pi_fine_enable = pi_fine_enable; C_pi_fine_inc = pi_fine_inc; C_pi_counter_load_en = pi_counter_load_en; C_pi_counter_read_en = pi_counter_read_en; C_pi_counter_load_val = pi_counter_load_val; C_pi_rst_dqs_find = pi_rst_dqs_find; C_po_fine_enable = po_fine_enable; C_po_coarse_enable = po_coarse_enable; C_po_fine_inc = po_fine_inc; C_po_coarse_inc = po_coarse_inc; C_po_counter_load_en = po_counter_load_en; C_po_counter_read_en = po_counter_read_en; C_po_counter_load_val = po_counter_load_val; C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; C_idelay_ce = idelay_ce; C_idelay_ld = idelay_ld; C_fine_delay = fine_delay ; C_fine_delay_sel = fine_delay_sel; end if ( D_mux_ctrl) begin D_pi_fine_enable = pi_fine_enable; D_pi_fine_inc = pi_fine_inc; D_pi_counter_load_en = pi_counter_load_en; D_pi_counter_read_en = pi_counter_read_en; D_pi_counter_load_val = pi_counter_load_val; D_pi_rst_dqs_find = pi_rst_dqs_find; D_po_fine_enable = po_fine_enable; D_po_coarse_enable = po_coarse_enable; D_po_fine_inc = po_fine_inc; D_po_coarse_inc = po_coarse_inc; D_po_counter_load_en = po_counter_load_en; D_po_counter_read_en = po_counter_read_en; D_po_counter_load_val = po_counter_load_val; D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; D_idelay_ce = idelay_ce; D_idelay_ld = idelay_ld; D_fine_delay = fine_delay ; D_fine_delay_sel = fine_delay_sel; end end else begin // otherwise, only a single phaser is selected case (calib_sel[1:0]) 0: begin A_pi_fine_enable = pi_fine_enable; A_pi_fine_inc = pi_fine_inc; A_pi_counter_load_en = pi_counter_load_en; A_pi_counter_read_en = pi_counter_read_en; A_pi_counter_load_val = pi_counter_load_val; A_pi_rst_dqs_find = pi_rst_dqs_find; A_po_fine_enable = po_fine_enable; A_po_coarse_enable = po_coarse_enable; A_po_fine_inc = po_fine_inc; A_po_coarse_inc = po_coarse_inc; A_po_counter_load_en = po_counter_load_en; A_po_counter_read_en = po_counter_read_en; A_po_counter_load_val = po_counter_load_val; A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; A_idelay_ce = idelay_ce; A_idelay_ld = idelay_ld; A_fine_delay = fine_delay ; A_fine_delay_sel = fine_delay_sel; end 1: begin B_pi_fine_enable = pi_fine_enable; B_pi_fine_inc = pi_fine_inc; B_pi_counter_load_en = pi_counter_load_en; B_pi_counter_read_en = pi_counter_read_en; B_pi_counter_load_val = pi_counter_load_val; B_pi_rst_dqs_find = pi_rst_dqs_find; B_po_fine_enable = po_fine_enable; B_po_coarse_enable = po_coarse_enable; B_po_fine_inc = po_fine_inc; B_po_coarse_inc = po_coarse_inc; B_po_counter_load_en = po_counter_load_en; B_po_counter_read_en = po_counter_read_en; B_po_counter_load_val = po_counter_load_val; B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; B_idelay_ce = idelay_ce; B_idelay_ld = idelay_ld; B_fine_delay = fine_delay ; B_fine_delay_sel = fine_delay_sel; end 2: begin C_pi_fine_enable = pi_fine_enable; C_pi_fine_inc = pi_fine_inc; C_pi_counter_load_en = pi_counter_load_en; C_pi_counter_read_en = pi_counter_read_en; C_pi_counter_load_val = pi_counter_load_val; C_pi_rst_dqs_find = pi_rst_dqs_find; C_po_fine_enable = po_fine_enable; C_po_coarse_enable = po_coarse_enable; C_po_fine_inc = po_fine_inc; C_po_coarse_inc = po_coarse_inc; C_po_counter_load_en = po_counter_load_en; C_po_counter_read_en = po_counter_read_en; C_po_counter_load_val = po_counter_load_val; C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; C_idelay_ce = idelay_ce; C_idelay_ld = idelay_ld; C_fine_delay = fine_delay ; C_fine_delay_sel = fine_delay_sel; end 3: begin D_pi_fine_enable = pi_fine_enable; D_pi_fine_inc = pi_fine_inc; D_pi_counter_load_en = pi_counter_load_en; D_pi_counter_read_en = pi_counter_read_en; D_pi_counter_load_val = pi_counter_load_val; D_pi_rst_dqs_find = pi_rst_dqs_find; D_po_fine_enable = po_fine_enable; D_po_coarse_enable = po_coarse_enable; D_po_fine_inc = po_fine_inc; D_po_coarse_inc = po_coarse_inc; D_po_counter_load_en = po_counter_load_en; D_po_counter_load_val = po_counter_load_val; D_po_counter_read_en = po_counter_read_en; D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; D_idelay_ce = idelay_ce; D_idelay_ld = idelay_ld; D_fine_delay = fine_delay ; D_fine_delay_sel = fine_delay_sel; end endcase end end //obligatory phaser-ref PHASER_REF phaser_ref_i( .LOCKED (ref_dll_lock), .CLKIN (freq_refclk), .PWRDWN (1'b0), .RST ( ! pll_lock) ); // optional idelay_ctrl generate if ( GENERATE_IDELAYCTRL == "TRUE") IDELAYCTRL idelayctrl ( .RDY (/*idelayctrl_rdy*/), .REFCLK (idelayctrl_refclk), .RST (rst) ); endgenerate endmodule
/********************************************************** -- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). A Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. // // THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. // // // Owner: Gary Martin // Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $ // $Author: gary $ // $DateTime: 2010/05/11 18:05:17 $ // $Change: 490882 $ // Description: // This verilog file is the parameterizable 4-byte lane phy primitive top // This module may be ganged to create an N-lane phy. // // History: // Date Engineer Description // 04/01/2010 G. Martin Initial Checkin. // /////////////////////////////////////////////////////////// **********************************************************/ `timescale 1ps/1ps `define PC_DATA_OFFSET_RANGE 22:17 module mig_7series_v2_3_ddr_phy_4lanes #( parameter GENERATE_IDELAYCTRL = "TRUE", parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010, parameter NUM_DDR_CK = 1, // next three parameter fields correspond to byte lanes for lane order DCBA parameter BYTE_LANES = 4'b1111, // lane existence, one per lane parameter DATA_CTL_N = 4'b1111, // data or control, per lane parameter BITLANES = 48'hffff_ffff_ffff, parameter BITLANES_OUTONLY = 48'h0000_0000_0000, parameter LANE_REMAP = 16'h3210,// 4-bit index // used to rewire to one of four // input/output buss lanes // example: 0321 remaps lanes as: // D->A // C->D // B->C // A->B parameter LAST_BANK = "FALSE", parameter USE_PRE_POST_FIFO = "FALSE", parameter RCLK_SELECT_LANE = "B", parameter real TCK = 0.00, parameter SYNTHESIS = "FALSE", parameter PO_CTL_COARSE_BYPASS = "FALSE", parameter PO_FINE_DELAY = 0, parameter PI_SEL_CLK_OFFSET = 0, // phy_control paramter used in other paramsters parameter PC_CLK_RATIO = 4, //phaser_in parameters parameter A_PI_FREQ_REF_DIV = "NONE", parameter A_PI_CLKOUT_DIV = 2, parameter A_PI_BURST_MODE = "TRUE", parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF", parameter A_PI_FINE_DELAY = 60, parameter A_PI_SYNC_IN_DIV_RST = "TRUE", parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter B_PI_BURST_MODE = A_PI_BURST_MODE, parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY, parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter C_PI_BURST_MODE = A_PI_BURST_MODE, parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter C_PI_FINE_DELAY = 0, parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter D_PI_BURST_MODE = A_PI_BURST_MODE, parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter D_PI_FINE_DELAY = 0, parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, //phaser_out parameters parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2, parameter A_PO_FINE_DELAY = PO_FINE_DELAY, parameter A_PO_COARSE_DELAY = 0, parameter A_PO_OCLK_DELAY = 0, parameter A_PO_OCLKDELAY_INV = "FALSE", parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF", parameter A_PO_SYNC_IN_DIV_RST = "TRUE", //parameter A_PO_SYNC_IN_DIV_RST = "FALSE", parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2, parameter B_PO_FINE_DELAY = PO_FINE_DELAY, parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2, parameter C_PO_FINE_DELAY = PO_FINE_DELAY, parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2, parameter D_PO_FINE_DELAY = PO_FINE_DELAY, parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE", parameter A_IDELAYE2_IDELAY_VALUE = 00, parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, // phy_control parameters parameter PC_BURST_MODE = "TRUE", parameter PC_DATA_CTL_N = DATA_CTL_N, parameter PC_CMD_OFFSET = 0, parameter PC_RD_CMD_OFFSET_0 = 0, parameter PC_RD_CMD_OFFSET_1 = 0, parameter PC_RD_CMD_OFFSET_2 = 0, parameter PC_RD_CMD_OFFSET_3 = 0, parameter PC_CO_DURATION = 1, parameter PC_DI_DURATION = 1, parameter PC_DO_DURATION = 1, parameter PC_RD_DURATION_0 = 0, parameter PC_RD_DURATION_1 = 0, parameter PC_RD_DURATION_2 = 0, parameter PC_RD_DURATION_3 = 0, parameter PC_WR_CMD_OFFSET_0 = 5, parameter PC_WR_CMD_OFFSET_1 = 5, parameter PC_WR_CMD_OFFSET_2 = 5, parameter PC_WR_CMD_OFFSET_3 = 5, parameter PC_WR_DURATION_0 = 6, parameter PC_WR_DURATION_1 = 6, parameter PC_WR_DURATION_2 = 6, parameter PC_WR_DURATION_3 = 6, parameter PC_AO_WRLVL_EN = 0, parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE) parameter PC_FOUR_WINDOW_CLOCKS = 63, parameter PC_EVENTS_DELAY = 18, parameter PC_PHY_COUNT_EN = "TRUE", parameter PC_SYNC_MODE = "TRUE", parameter PC_DISABLE_SEQ_MATCH = "TRUE", parameter PC_MULTI_REGION = "FALSE", // io fifo parameters parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter OF_ALMOST_EMPTY_VALUE = 1, parameter OF_ALMOST_FULL_VALUE = 1, parameter OF_OUTPUT_DISABLE = "TRUE", parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE, parameter A_OS_DATA_RATE = "DDR", parameter A_OS_DATA_WIDTH = 4, parameter B_OS_DATA_RATE = A_OS_DATA_RATE, parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter C_OS_DATA_RATE = A_OS_DATA_RATE, parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter D_OS_DATA_RATE = A_OS_DATA_RATE, parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8", parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter IF_ALMOST_EMPTY_VALUE = 1, parameter IF_ALMOST_FULL_VALUE = 1, parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE, // this is used locally, not for external pushdown // NOTE: the 0+ is needed in each to coerce to integer for addition. // otherwise 4x 1'b values are added producing a 1'b value. parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1), parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])), parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]), parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES, // assume odt per rank + any declared cke's parameter AUXOUT_WIDTH = 4, parameter LP_DDR_CK_WIDTH = 2 ,parameter CKE_ODT_AUX = "FALSE" ) ( //`include "phy.vh" input rst, input phy_clk, input phy_ctl_clk, input freq_refclk, input mem_refclk, input mem_refclk_div4, input pll_lock, input sync_pulse, input idelayctrl_refclk, input [HIGHEST_LANE*80-1:0] phy_dout, input phy_cmd_wr_en, input phy_data_wr_en, input phy_rd_en, input phy_ctl_mstr_empty, input [31:0] phy_ctl_wd, input [`PC_DATA_OFFSET_RANGE] data_offset, input phy_ctl_wr, input if_empty_def, input phyGo, input input_sink, output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory output rclk, output if_a_empty, output if_empty, output byte_rd_en, output if_empty_or, output if_empty_and, output of_ctl_a_full, output of_data_a_full, output of_ctl_full, output of_data_full, output pre_data_a_full, output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus output phy_ctl_empty, output phy_ctl_a_full, output phy_ctl_full, output [HIGHEST_LANE*12-1:0]mem_dq_out, output [HIGHEST_LANE*12-1:0]mem_dq_ts, input [HIGHEST_LANE*10-1:0]mem_dq_in, output [HIGHEST_LANE-1:0] mem_dqs_out, output [HIGHEST_LANE-1:0] mem_dqs_ts, input [HIGHEST_LANE-1:0] mem_dqs_in, input [1:0] byte_rd_en_oth_banks, output [AUXOUT_WIDTH-1:0] aux_out, output reg rst_out = 0, output reg mcGo=0, output phy_ctl_ready, output ref_dll_lock, input if_rst, input phy_read_calib, input phy_write_calib, input idelay_inc, input idelay_ce, input idelay_ld, input [2:0] calib_sel, input calib_zero_ctrl, input [HIGHEST_LANE-1:0] calib_zero_lanes, input calib_in_common, input po_fine_enable, input po_coarse_enable, input po_fine_inc, input po_coarse_inc, input po_counter_load_en, input po_counter_read_en, input [8:0] po_counter_load_val, input po_sel_fine_oclk_delay, output reg po_coarse_overflow, output reg po_fine_overflow, output reg [8:0] po_counter_read_val, input pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input pi_counter_read_en, input [5:0] pi_counter_load_val, output reg pi_fine_overflow, output reg [5:0] pi_counter_read_val, output reg pi_dqs_found, output pi_dqs_found_all, output pi_dqs_found_any, output [HIGHEST_LANE-1:0] pi_phase_locked_lanes, output [HIGHEST_LANE-1:0] pi_dqs_found_lanes, output reg pi_dqs_out_of_range, output reg pi_phase_locked, output pi_phase_locked_all, input [29:0] fine_delay, input fine_delay_sel ); localparam DATA_CTL_A = (~DATA_CTL_N[0]); localparam DATA_CTL_B = (~DATA_CTL_N[1]); localparam DATA_CTL_C = (~DATA_CTL_N[2]); localparam DATA_CTL_D = (~DATA_CTL_N[3]); localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0]; localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1]; localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2]; localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3]; localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0]; localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1]; localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2]; localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3]; localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE"; localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam IO_A_START = 41; localparam IO_A_END = 40; localparam IO_B_START = 43; localparam IO_B_END = 42; localparam IO_C_START = 45; localparam IO_C_END = 44; localparam IO_D_START = 47; localparam IO_D_END = 46; localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1; localparam IO_A_X_END = (IO_A_X_START-1); localparam IO_B_X_START = (IO_A_X_START + 2); localparam IO_B_X_END = (IO_B_X_START -1); localparam IO_C_X_START = (IO_B_X_START + 2); localparam IO_C_X_END = (IO_C_X_START -1); localparam IO_D_X_START = (IO_C_X_START + 2); localparam IO_D_X_END = (IO_D_X_START -1); localparam MSB_BURST_PEND_PO = 3; localparam MSB_BURST_PEND_PI = 7; localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8; localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1; wire [1:0] oserdes_dqs; wire [1:0] oserdes_dqs_ts; wire [1:0] oserdes_dq_ts; wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus; wire [7:0] in_rank; wire [11:0] IO_A; wire [11:0] IO_B; wire [11:0] IO_C; wire [11:0] IO_D; wire [319:0] phy_din_remap; reg A_po_counter_read_en; wire [8:0] A_po_counter_read_val; reg A_pi_counter_read_en; wire [5:0] A_pi_counter_read_val; wire A_pi_fine_overflow; wire A_po_coarse_overflow; wire A_po_fine_overflow; wire A_pi_dqs_found; wire A_pi_dqs_out_of_range; wire A_pi_phase_locked; wire A_pi_iserdes_rst; reg A_pi_fine_enable; reg A_pi_fine_inc; reg A_pi_counter_load_en; reg [5:0] A_pi_counter_load_val; reg A_pi_rst_dqs_find; reg A_po_fine_enable; reg A_po_coarse_enable; reg A_po_fine_inc /* synthesis syn_maxfan = 3 */; reg A_po_sel_fine_oclk_delay; reg A_po_coarse_inc; reg A_po_counter_load_en; reg [8:0] A_po_counter_load_val; wire A_rclk; reg A_idelay_ce; reg A_idelay_ld; reg [29:0] A_fine_delay; reg A_fine_delay_sel; reg B_po_counter_read_en; wire [8:0] B_po_counter_read_val; reg B_pi_counter_read_en; wire [5:0] B_pi_counter_read_val; wire B_pi_fine_overflow; wire B_po_coarse_overflow; wire B_po_fine_overflow; wire B_pi_phase_locked; wire B_pi_iserdes_rst; wire B_pi_dqs_found; wire B_pi_dqs_out_of_range; reg B_pi_fine_enable; reg B_pi_fine_inc; reg B_pi_counter_load_en; reg [5:0] B_pi_counter_load_val; reg B_pi_rst_dqs_find; reg B_po_fine_enable; reg B_po_coarse_enable; reg B_po_fine_inc /* synthesis syn_maxfan = 3 */; reg B_po_coarse_inc; reg B_po_sel_fine_oclk_delay; reg B_po_counter_load_en; reg [8:0] B_po_counter_load_val; wire B_rclk; reg B_idelay_ce; reg B_idelay_ld; reg [29:0] B_fine_delay; reg B_fine_delay_sel; reg C_pi_fine_inc; reg D_pi_fine_inc; reg C_pi_fine_enable; reg D_pi_fine_enable; reg C_po_counter_load_en; reg D_po_counter_load_en; reg C_po_coarse_inc; reg D_po_coarse_inc; reg C_po_fine_inc /* synthesis syn_maxfan = 3 */; reg D_po_fine_inc /* synthesis syn_maxfan = 3 */; reg C_po_sel_fine_oclk_delay; reg D_po_sel_fine_oclk_delay; reg [5:0] C_pi_counter_load_val; reg [5:0] D_pi_counter_load_val; reg [8:0] C_po_counter_load_val; reg [8:0] D_po_counter_load_val; reg C_po_coarse_enable; reg D_po_coarse_enable; reg C_po_fine_enable; reg D_po_fine_enable; wire C_po_coarse_overflow; wire D_po_coarse_overflow; wire C_po_fine_overflow; wire D_po_fine_overflow; wire [8:0] C_po_counter_read_val; wire [8:0] D_po_counter_read_val; reg C_po_counter_read_en; reg D_po_counter_read_en; wire C_pi_dqs_found; wire D_pi_dqs_found; wire C_pi_fine_overflow; wire D_pi_fine_overflow; reg C_pi_counter_read_en; reg D_pi_counter_read_en; reg C_pi_counter_load_en; reg D_pi_counter_load_en; wire C_pi_phase_locked; wire C_pi_iserdes_rst; wire D_pi_phase_locked; wire D_pi_iserdes_rst; wire C_pi_dqs_out_of_range; wire D_pi_dqs_out_of_range; wire [5:0] C_pi_counter_read_val; wire [5:0] D_pi_counter_read_val; wire C_rclk; wire D_rclk; reg C_idelay_ce; reg D_idelay_ce; reg C_idelay_ld; reg D_idelay_ld; reg C_pi_rst_dqs_find; reg D_pi_rst_dqs_find; reg [29:0] C_fine_delay; reg [29:0] D_fine_delay; reg C_fine_delay_sel; reg D_fine_delay_sel; wire pi_iserdes_rst; wire A_if_empty; wire B_if_empty; wire C_if_empty; wire D_if_empty; wire A_byte_rd_en; wire B_byte_rd_en; wire C_byte_rd_en; wire D_byte_rd_en; wire A_if_a_empty; wire B_if_a_empty; wire C_if_a_empty; wire D_if_a_empty; //wire A_if_full; //wire B_if_full; //wire C_if_full; //wire D_if_full; //wire A_of_empty; //wire B_of_empty; //wire C_of_empty; //wire D_of_empty; wire A_of_full; wire B_of_full; wire C_of_full; wire D_of_full; wire A_of_ctl_full; wire B_of_ctl_full; wire C_of_ctl_full; wire D_of_ctl_full; wire A_of_data_full; wire B_of_data_full; wire C_of_data_full; wire D_of_data_full; wire A_of_a_full; wire B_of_a_full; wire C_of_a_full; wire D_of_a_full; wire A_pre_fifo_a_full; wire B_pre_fifo_a_full; wire C_pre_fifo_a_full; wire D_pre_fifo_a_full; wire A_of_ctl_a_full; wire B_of_ctl_a_full; wire C_of_ctl_a_full; wire D_of_ctl_a_full; wire A_of_data_a_full; wire B_of_data_a_full; wire C_of_data_a_full; wire D_of_data_a_full; wire A_pre_data_a_full; wire B_pre_data_a_full; wire C_pre_data_a_full; wire D_pre_data_a_full; wire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation wire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; // wire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; // wire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; // wire [3:0] dummy_data; wire [31:0] _phy_ctl_wd; wire [1:0] phy_encalib; assign pi_dqs_found_all = (! PRESENT_DATA_A | A_pi_dqs_found) & (! PRESENT_DATA_B | B_pi_dqs_found) & (! PRESENT_DATA_C | C_pi_dqs_found) & (! PRESENT_DATA_D | D_pi_dqs_found) ; assign pi_dqs_found_any = ( PRESENT_DATA_A & A_pi_dqs_found) | ( PRESENT_DATA_B & B_pi_dqs_found) | ( PRESENT_DATA_C & C_pi_dqs_found) | ( PRESENT_DATA_D & D_pi_dqs_found) ; assign pi_phase_locked_all = (! PRESENT_DATA_A | A_pi_phase_locked) & (! PRESENT_DATA_B | B_pi_phase_locked) & (! PRESENT_DATA_C | C_pi_phase_locked) & (! PRESENT_DATA_D | D_pi_phase_locked); wire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal // which is combined into another signals such that // the other signal isn't changed. The purpose // is to fake the tools into ignoring dangling inputs. // Because it is anded with 1'b0, the contributing signals // are folded as constants or trimmed. assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty); assign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) : (A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en); assign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty); assign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty); assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty; //assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ; //assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty; assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ; assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ; assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ; assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ; assign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full; function [79:0] part_select_80; input [319:0] vector; input [1:0] select; begin case (select) 2'b00 : part_select_80[79:0] = vector[1*80-1:0*80]; 2'b01 : part_select_80[79:0] = vector[2*80-1:1*80]; 2'b10 : part_select_80[79:0] = vector[3*80-1:2*80]; 2'b11 : part_select_80[79:0] = vector[4*80-1:3*80]; endcase end endfunction wire [319:0] phy_dout_remap; reg rst_out_trig = 1'b0; reg [31:0] rclk_delay; reg rst_edge1 = 1'b0; reg rst_edge2 = 1'b0; reg rst_edge3 = 1'b0; reg rst_edge_detect = 1'b0; wire rclk_; reg rst_out_start = 1'b0 ; reg rst_primitives=0; reg A_rst_primitives=0; reg B_rst_primitives=0; reg C_rst_primitives=0; reg D_rst_primitives=0; `ifdef USE_PHY_CONTROL_TEST wire [15:0] test_output; wire [15:0] test_input; wire [2:0] test_select=0; wire scan_enable = 0; `endif generate genvar i; if (RCLK_SELECT_LANE == "A") begin assign rclk_ = A_rclk; assign pi_iserdes_rst = A_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "B") begin assign rclk_ = B_rclk; assign pi_iserdes_rst = B_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "C") begin assign rclk_ = C_rclk; assign pi_iserdes_rst = C_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "D") begin assign rclk_ = D_rclk; assign pi_iserdes_rst = D_pi_iserdes_rst; end else begin assign rclk_ = B_rclk; // default end endgenerate assign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk; assign pi_phase_locked_lanes = {(! PRESENT_DATA_A[0] | A_pi_phase_locked), (! PRESENT_DATA_B[0] | B_pi_phase_locked) , (! PRESENT_DATA_C[0] | C_pi_phase_locked) , (! PRESENT_DATA_D[0] | D_pi_phase_locked)}; assign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found}; // this block scrubs X from rclk_delay[11] reg rclk_delay_11; always @(rclk_delay[11]) begin : rclk_delay_11_blk if ( rclk_delay[11]) rclk_delay_11 = 1; else rclk_delay_11 = 0; end always @(posedge phy_clk or posedge rst ) begin // scrub 4-state values from rclk_delay[11] if ( rst) begin rst_out <= #1 0; end else begin if ( rclk_delay_11) rst_out <= #1 1; end end always @(posedge phy_clk ) begin // phy_ctl_ready drives reset of the system rst_primitives <= !phy_ctl_ready ; A_rst_primitives <= rst_primitives ; B_rst_primitives <= rst_primitives ; C_rst_primitives <= rst_primitives ; D_rst_primitives <= rst_primitives ; rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo); mcGo <= #1 rst_out ; end generate if (BYTE_LANES[0]) begin assign dummy_data[0] = 0; end else begin assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80]; end if (BYTE_LANES[1]) begin assign dummy_data[1] = 0; end else begin assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80]; end if (BYTE_LANES[2]) begin assign dummy_data[2] = 0; end else begin assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80]; end if (BYTE_LANES[3]) begin assign dummy_data[3] = 0; end else begin assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80]; end if (PRESENT_DATA_A) begin assign A_of_data_full = A_of_full; assign A_of_ctl_full = 0; assign A_of_data_a_full = A_of_a_full; assign A_of_ctl_a_full = 0; assign A_pre_data_a_full = A_pre_fifo_a_full; end else begin assign A_of_ctl_full = A_of_full; assign A_of_data_full = 0; assign A_of_ctl_a_full = A_of_a_full; assign A_of_data_a_full = 0; assign A_pre_data_a_full = 0; end if (PRESENT_DATA_B) begin assign B_of_data_full = B_of_full; assign B_of_ctl_full = 0; assign B_of_data_a_full = B_of_a_full; assign B_of_ctl_a_full = 0; assign B_pre_data_a_full = B_pre_fifo_a_full; end else begin assign B_of_ctl_full = B_of_full; assign B_of_data_full = 0; assign B_of_ctl_a_full = B_of_a_full; assign B_of_data_a_full = 0; assign B_pre_data_a_full = 0; end if (PRESENT_DATA_C) begin assign C_of_data_full = C_of_full; assign C_of_ctl_full = 0; assign C_of_data_a_full = C_of_a_full; assign C_of_ctl_a_full = 0; assign C_pre_data_a_full = C_pre_fifo_a_full; end else begin assign C_of_ctl_full = C_of_full; assign C_of_data_full = 0; assign C_of_ctl_a_full = C_of_a_full; assign C_of_data_a_full = 0; assign C_pre_data_a_full = 0; end if (PRESENT_DATA_D) begin assign D_of_data_full = D_of_full; assign D_of_ctl_full = 0; assign D_of_data_a_full = D_of_a_full; assign D_of_ctl_a_full = 0; assign D_pre_data_a_full = D_pre_fifo_a_full; end else begin assign D_of_ctl_full = D_of_full; assign D_of_data_full = 0; assign D_of_ctl_a_full = D_of_a_full; assign D_of_data_a_full = 0; assign D_pre_data_a_full = 0; end // byte lane must exist and be data lane. if (PRESENT_DATA_A ) case ( LANE_REMAP[1:0] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0]; endcase else case ( LANE_REMAP[1:0] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_B ) case ( LANE_REMAP[5:4] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80]; endcase else if (HIGHEST_LANE > 1) case ( LANE_REMAP[5:4] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_C) case ( LANE_REMAP[9:8] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160]; endcase else if (HIGHEST_LANE > 2) case ( LANE_REMAP[9:8] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_D ) case ( LANE_REMAP[13:12] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240]; endcase else if (HIGHEST_LANE > 3) case ( LANE_REMAP[13:12] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (HIGHEST_LANE > 1) assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]}; if (HIGHEST_LANE == 1) assign _phy_ctl_wd = phy_ctl_wd; //BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst)); BUFIO rclk_buf(.I(rclk_), .O(rclk) ); if ( BYTE_LANES[0] ) begin : ddr_byte_lane_A assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("A"), .PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[11:0]), .BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (A_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (A_PI_BURST_MODE), .PI_CLKOUT_DIV (A_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV), .PI_FINE_DELAY (A_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (A_PO_CLKOUT_DIV), .PO_FINE_DELAY (A_PO_FINE_DELAY), .PO_COARSE_BYPASS (A_PO_COARSE_BYPASS), .PO_COARSE_DELAY (A_PO_COARSE_DELAY), .PO_OCLK_DELAY (A_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (A_OS_DATA_RATE), .OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_A( .mem_dq_out (mem_dq_out[11:0]), .mem_dq_ts (mem_dq_ts[11:0]), .mem_dq_in (mem_dq_in[9:0]), .mem_dqs_out (mem_dqs_out[0]), .mem_dqs_ts (mem_dqs_ts[0]), .mem_dqs_in (mem_dqs_in[0]), .rst (A_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (A_ddr_clk), .rclk (A_rclk), .pi_dqs_found (A_pi_dqs_found), .dqs_out_of_range (A_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (A_if_a_empty), .if_empty (A_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*A_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*A_of_empty*/), .of_a_full (A_of_a_full), .of_full (A_of_full), .pre_fifo_a_full (A_pre_fifo_a_full), .phy_din (phy_din_remap[79:0]), .phy_dout (phy_dout_remap[79:0]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (A_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (A_idelay_ce), .idelay_ld (A_idelay_ld), .pi_rst_dqs_find (A_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (A_po_fine_enable), .po_coarse_enable (A_po_coarse_enable), .po_fine_inc (A_po_fine_inc), .po_coarse_inc (A_po_coarse_inc), .po_counter_load_en (A_po_counter_load_en), .po_counter_read_en (A_po_counter_read_en), .po_counter_load_val (A_po_counter_load_val), .po_coarse_overflow (A_po_coarse_overflow), .po_fine_overflow (A_po_fine_overflow), .po_counter_read_val (A_po_counter_read_val), .po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (A_pi_fine_enable), .pi_fine_inc (A_pi_fine_inc), .pi_counter_load_en (A_pi_counter_load_en), .pi_counter_read_en (A_pi_counter_read_en), .pi_counter_load_val (A_pi_counter_load_val), .pi_fine_overflow (A_pi_fine_overflow), .pi_counter_read_val (A_pi_counter_read_val), .pi_iserdes_rst (A_pi_iserdes_rst), .pi_phase_locked (A_pi_phase_locked), .fine_delay (A_fine_delay), .fine_delay_sel (A_fine_delay_sel) ); end else begin : no_ddr_byte_lane_A assign A_of_a_full = 1'b0; assign A_of_full = 1'b0; assign A_pre_fifo_a_full = 1'b0; assign A_if_empty = 1'b0; assign A_byte_rd_en = 1'b1; assign A_if_a_empty = 1'b0; assign A_pi_phase_locked = 1; assign A_pi_dqs_found = 1; assign A_rclk = 0; assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign A_pi_counter_read_val = 0; assign A_po_counter_read_val = 0; assign A_pi_fine_overflow = 0; assign A_po_coarse_overflow = 0; assign A_po_fine_overflow = 0; end if ( BYTE_LANES[1] ) begin : ddr_byte_lane_B assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("B"), .PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[23:12]), .BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (B_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (B_PI_BURST_MODE), .PI_CLKOUT_DIV (B_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV), .PI_FINE_DELAY (B_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (B_PO_CLKOUT_DIV), .PO_FINE_DELAY (B_PO_FINE_DELAY), .PO_COARSE_BYPASS (B_PO_COARSE_BYPASS), .PO_COARSE_DELAY (B_PO_COARSE_DELAY), .PO_OCLK_DELAY (B_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (B_OS_DATA_RATE), .OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_B( .mem_dq_out (mem_dq_out[23:12]), .mem_dq_ts (mem_dq_ts[23:12]), .mem_dq_in (mem_dq_in[19:10]), .mem_dqs_out (mem_dqs_out[1]), .mem_dqs_ts (mem_dqs_ts[1]), .mem_dqs_in (mem_dqs_in[1]), .rst (B_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (B_ddr_clk), .rclk (B_rclk), .pi_dqs_found (B_pi_dqs_found), .dqs_out_of_range (B_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (B_if_a_empty), .if_empty (B_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*B_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*B_of_empty*/), .of_a_full (B_of_a_full), .of_full (B_of_full), .pre_fifo_a_full (B_pre_fifo_a_full), .phy_din (phy_din_remap[159:80]), .phy_dout (phy_dout_remap[159:80]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (B_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (B_idelay_ce), .idelay_ld (B_idelay_ld), .pi_rst_dqs_find (B_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (B_po_fine_enable), .po_coarse_enable (B_po_coarse_enable), .po_fine_inc (B_po_fine_inc), .po_coarse_inc (B_po_coarse_inc), .po_counter_load_en (B_po_counter_load_en), .po_counter_read_en (B_po_counter_read_en), .po_counter_load_val (B_po_counter_load_val), .po_coarse_overflow (B_po_coarse_overflow), .po_fine_overflow (B_po_fine_overflow), .po_counter_read_val (B_po_counter_read_val), .po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (B_pi_fine_enable), .pi_fine_inc (B_pi_fine_inc), .pi_counter_load_en (B_pi_counter_load_en), .pi_counter_read_en (B_pi_counter_read_en), .pi_counter_load_val (B_pi_counter_load_val), .pi_fine_overflow (B_pi_fine_overflow), .pi_counter_read_val (B_pi_counter_read_val), .pi_iserdes_rst (B_pi_iserdes_rst), .pi_phase_locked (B_pi_phase_locked), .fine_delay (B_fine_delay), .fine_delay_sel (B_fine_delay_sel) ); end else begin : no_ddr_byte_lane_B assign B_of_a_full = 1'b0; assign B_of_full = 1'b0; assign B_pre_fifo_a_full = 1'b0; assign B_if_empty = 1'b0; assign B_if_a_empty = 1'b0; assign B_byte_rd_en = 1'b1; assign B_pi_phase_locked = 1; assign B_pi_dqs_found = 1; assign B_rclk = 0; assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign B_pi_counter_read_val = 0; assign B_po_counter_read_val = 0; assign B_pi_fine_overflow = 0; assign B_po_coarse_overflow = 0; assign B_po_fine_overflow = 0; end if ( BYTE_LANES[2] ) begin : ddr_byte_lane_C assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("C"), .PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[35:24]), .BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (C_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (C_PI_BURST_MODE), .PI_CLKOUT_DIV (C_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV), .PI_FINE_DELAY (C_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (C_PO_CLKOUT_DIV), .PO_FINE_DELAY (C_PO_FINE_DELAY), .PO_COARSE_BYPASS (C_PO_COARSE_BYPASS), .PO_COARSE_DELAY (C_PO_COARSE_DELAY), .PO_OCLK_DELAY (C_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (C_OS_DATA_RATE), .OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_C( .mem_dq_out (mem_dq_out[35:24]), .mem_dq_ts (mem_dq_ts[35:24]), .mem_dq_in (mem_dq_in[29:20]), .mem_dqs_out (mem_dqs_out[2]), .mem_dqs_ts (mem_dqs_ts[2]), .mem_dqs_in (mem_dqs_in[2]), .rst (C_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (C_ddr_clk), .rclk (C_rclk), .pi_dqs_found (C_pi_dqs_found), .dqs_out_of_range (C_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (C_if_a_empty), .if_empty (C_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*C_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*C_of_empty*/), .of_a_full (C_of_a_full), .of_full (C_of_full), .pre_fifo_a_full (C_pre_fifo_a_full), .phy_din (phy_din_remap[239:160]), .phy_dout (phy_dout_remap[239:160]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (C_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (C_idelay_ce), .idelay_ld (C_idelay_ld), .pi_rst_dqs_find (C_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (C_po_fine_enable), .po_coarse_enable (C_po_coarse_enable), .po_fine_inc (C_po_fine_inc), .po_coarse_inc (C_po_coarse_inc), .po_counter_load_en (C_po_counter_load_en), .po_counter_read_en (C_po_counter_read_en), .po_counter_load_val (C_po_counter_load_val), .po_coarse_overflow (C_po_coarse_overflow), .po_fine_overflow (C_po_fine_overflow), .po_counter_read_val (C_po_counter_read_val), .po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (C_pi_fine_enable), .pi_fine_inc (C_pi_fine_inc), .pi_counter_load_en (C_pi_counter_load_en), .pi_counter_read_en (C_pi_counter_read_en), .pi_counter_load_val (C_pi_counter_load_val), .pi_fine_overflow (C_pi_fine_overflow), .pi_counter_read_val (C_pi_counter_read_val), .pi_iserdes_rst (C_pi_iserdes_rst), .pi_phase_locked (C_pi_phase_locked), .fine_delay (C_fine_delay), .fine_delay_sel (C_fine_delay_sel) ); end else begin : no_ddr_byte_lane_C assign C_of_a_full = 1'b0; assign C_of_full = 1'b0; assign C_pre_fifo_a_full = 1'b0; assign C_if_empty = 1'b0; assign C_byte_rd_en = 1'b1; assign C_if_a_empty = 1'b0; assign C_pi_phase_locked = 1; assign C_pi_dqs_found = 1; assign C_rclk = 0; assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign C_pi_counter_read_val = 0; assign C_po_counter_read_val = 0; assign C_pi_fine_overflow = 0; assign C_po_coarse_overflow = 0; assign C_po_fine_overflow = 0; end if ( BYTE_LANES[3] ) begin : ddr_byte_lane_D assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("D"), .PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[47:36]), .BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (D_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (D_PI_BURST_MODE), .PI_CLKOUT_DIV (D_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV), .PI_FINE_DELAY (D_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (D_PO_CLKOUT_DIV), .PO_FINE_DELAY (D_PO_FINE_DELAY), .PO_COARSE_BYPASS (D_PO_COARSE_BYPASS), .PO_COARSE_DELAY (D_PO_COARSE_DELAY), .PO_OCLK_DELAY (D_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (D_OS_DATA_RATE), .OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_D( .mem_dq_out (mem_dq_out[47:36]), .mem_dq_ts (mem_dq_ts[47:36]), .mem_dq_in (mem_dq_in[39:30]), .mem_dqs_out (mem_dqs_out[3]), .mem_dqs_ts (mem_dqs_ts[3]), .mem_dqs_in (mem_dqs_in[3]), .rst (D_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (D_ddr_clk), .rclk (D_rclk), .pi_dqs_found (D_pi_dqs_found), .dqs_out_of_range (D_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (D_if_a_empty), .if_empty (D_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*D_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*D_of_empty*/), .of_a_full (D_of_a_full), .of_full (D_of_full), .pre_fifo_a_full (D_pre_fifo_a_full), .phy_din (phy_din_remap[319:240]), .phy_dout (phy_dout_remap[319:240]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .idelay_inc (idelay_inc), .idelay_ce (D_idelay_ce), .idelay_ld (D_idelay_ld), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (D_byte_rd_en), // calibration signals .pi_rst_dqs_find (D_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (D_po_fine_enable), .po_coarse_enable (D_po_coarse_enable), .po_fine_inc (D_po_fine_inc), .po_coarse_inc (D_po_coarse_inc), .po_counter_load_en (D_po_counter_load_en), .po_counter_read_en (D_po_counter_read_en), .po_counter_load_val (D_po_counter_load_val), .po_coarse_overflow (D_po_coarse_overflow), .po_fine_overflow (D_po_fine_overflow), .po_counter_read_val (D_po_counter_read_val), .po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (D_pi_fine_enable), .pi_fine_inc (D_pi_fine_inc), .pi_counter_load_en (D_pi_counter_load_en), .pi_counter_read_en (D_pi_counter_read_en), .pi_counter_load_val (D_pi_counter_load_val), .pi_fine_overflow (D_pi_fine_overflow), .pi_counter_read_val (D_pi_counter_read_val), .pi_iserdes_rst (D_pi_iserdes_rst), .pi_phase_locked (D_pi_phase_locked), .fine_delay (D_fine_delay), .fine_delay_sel (D_fine_delay_sel) ); end else begin : no_ddr_byte_lane_D assign D_of_a_full = 1'b0; assign D_of_full = 1'b0; assign D_pre_fifo_a_full = 1'b0; assign D_if_empty = 1'b0; assign D_byte_rd_en = 1'b1; assign D_if_a_empty = 1'b0; assign D_rclk = 0; assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign D_pi_dqs_found = 1; assign D_pi_phase_locked = 1; assign D_pi_counter_read_val = 0; assign D_po_counter_read_val = 0; assign D_pi_fine_overflow = 0; assign D_po_coarse_overflow = 0; assign D_po_fine_overflow = 0; end endgenerate assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank; PHY_CONTROL #( .AO_WRLVL_EN ( PC_AO_WRLVL_EN), .AO_TOGGLE ( PC_AO_TOGGLE), .BURST_MODE ( PC_BURST_MODE), .CO_DURATION ( PC_CO_DURATION ), .CLK_RATIO ( PC_CLK_RATIO), .DATA_CTL_A_N ( PC_DATA_CTL_A), .DATA_CTL_B_N ( PC_DATA_CTL_B), .DATA_CTL_C_N ( PC_DATA_CTL_C), .DATA_CTL_D_N ( PC_DATA_CTL_D), .DI_DURATION ( PC_DI_DURATION ), .DO_DURATION ( PC_DO_DURATION ), .EVENTS_DELAY ( PC_EVENTS_DELAY), .FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS), .MULTI_REGION ( PC_MULTI_REGION ), .PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN), .DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH), .SYNC_MODE ( PC_SYNC_MODE), .CMD_OFFSET ( PC_CMD_OFFSET), .RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0), .RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1), .RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2), .RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3), .RD_DURATION_0 ( PC_RD_DURATION_0), .RD_DURATION_1 ( PC_RD_DURATION_1), .RD_DURATION_2 ( PC_RD_DURATION_2), .RD_DURATION_3 ( PC_RD_DURATION_3), .WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0), .WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1), .WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2), .WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3), .WR_DURATION_0 ( PC_WR_DURATION_0), .WR_DURATION_1 ( PC_WR_DURATION_1), .WR_DURATION_2 ( PC_WR_DURATION_2), .WR_DURATION_3 ( PC_WR_DURATION_3) ) phy_control_i ( .AUXOUTPUT (aux_out), .INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]), .INRANKA (in_rank[1:0]), .INRANKB (in_rank[3:2]), .INRANKC (in_rank[5:4]), .INRANKD (in_rank[7:6]), .OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]), .PCENABLECALIB (phy_encalib), .PHYCTLALMOSTFULL (phy_ctl_a_full), .PHYCTLEMPTY (phy_ctl_empty), .PHYCTLFULL (phy_ctl_full), .PHYCTLREADY (phy_ctl_ready), .MEMREFCLK (mem_refclk), .PHYCLK (phy_ctl_clk), .PHYCTLMSTREMPTY (phy_ctl_mstr_empty), .PHYCTLWD (_phy_ctl_wd), .PHYCTLWRENABLE (phy_ctl_wr), .PLLLOCK (pll_lock), .REFDLLLOCK (ref_dll_lock), // is reset while !locked .RESET (rst), .SYNCIN (sync_pulse), .READCALIBENABLE (phy_read_calib), .WRITECALIBENABLE (phy_write_calib) `ifdef USE_PHY_CONTROL_TEST , .TESTINPUT (16'b0), .TESTOUTPUT (test_output), .TESTSELECT (test_select), .SCANENABLEN (scan_enable) `endif ); // register outputs to give extra slack in timing always @(posedge phy_clk ) begin case (calib_sel[1:0]) 2'h0: begin po_coarse_overflow <= #1 A_po_coarse_overflow; po_fine_overflow <= #1 A_po_fine_overflow; po_counter_read_val <= #1 A_po_counter_read_val; pi_fine_overflow <= #1 A_pi_fine_overflow; pi_counter_read_val<= #1 A_pi_counter_read_val; pi_phase_locked <= #1 A_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 A_pi_dqs_found; pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range; end 2'h1: begin po_coarse_overflow <= #1 B_po_coarse_overflow; po_fine_overflow <= #1 B_po_fine_overflow; po_counter_read_val <= #1 B_po_counter_read_val; pi_fine_overflow <= #1 B_pi_fine_overflow; pi_counter_read_val <= #1 B_pi_counter_read_val; pi_phase_locked <= #1 B_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 B_pi_dqs_found; pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range; end 2'h2: begin po_coarse_overflow <= #1 C_po_coarse_overflow; po_fine_overflow <= #1 C_po_fine_overflow; po_counter_read_val <= #1 C_po_counter_read_val; pi_fine_overflow <= #1 C_pi_fine_overflow; pi_counter_read_val <= #1 C_pi_counter_read_val; pi_phase_locked <= #1 C_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 C_pi_dqs_found; pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range; end 2'h3: begin po_coarse_overflow <= #1 D_po_coarse_overflow; po_fine_overflow <= #1 D_po_fine_overflow; po_counter_read_val <= #1 D_po_counter_read_val; pi_fine_overflow <= #1 D_pi_fine_overflow; pi_counter_read_val <= #1 D_pi_counter_read_val; pi_phase_locked <= #1 D_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 D_pi_dqs_found; pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range; end default: begin po_coarse_overflow <= po_coarse_overflow; end endcase end wire B_mux_ctrl; wire C_mux_ctrl; wire D_mux_ctrl; generate if (HIGHEST_LANE > 1) assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1])); else assign B_mux_ctrl = 0; if (HIGHEST_LANE > 2) assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2])); else assign C_mux_ctrl = 0; if (HIGHEST_LANE > 3) assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3])); else assign D_mux_ctrl = 0; endgenerate always @(*) begin A_pi_fine_enable = 0; A_pi_fine_inc = 0; A_pi_counter_load_en = 0; A_pi_counter_read_en = 0; A_pi_counter_load_val = 0; A_pi_rst_dqs_find = 0; A_po_fine_enable = 0; A_po_coarse_enable = 0; A_po_fine_inc = 0; A_po_coarse_inc = 0; A_po_counter_load_en = 0; A_po_counter_read_en = 0; A_po_counter_load_val = 0; A_po_sel_fine_oclk_delay = 0; A_idelay_ce = 0; A_idelay_ld = 0; A_fine_delay = 0; A_fine_delay_sel = 0; B_pi_fine_enable = 0; B_pi_fine_inc = 0; B_pi_counter_load_en = 0; B_pi_counter_read_en = 0; B_pi_counter_load_val = 0; B_pi_rst_dqs_find = 0; B_po_fine_enable = 0; B_po_coarse_enable = 0; B_po_fine_inc = 0; B_po_coarse_inc = 0; B_po_counter_load_en = 0; B_po_counter_read_en = 0; B_po_counter_load_val = 0; B_po_sel_fine_oclk_delay = 0; B_idelay_ce = 0; B_idelay_ld = 0; B_fine_delay = 0; B_fine_delay_sel = 0; C_pi_fine_enable = 0; C_pi_fine_inc = 0; C_pi_counter_load_en = 0; C_pi_counter_read_en = 0; C_pi_counter_load_val = 0; C_pi_rst_dqs_find = 0; C_po_fine_enable = 0; C_po_coarse_enable = 0; C_po_fine_inc = 0; C_po_coarse_inc = 0; C_po_counter_load_en = 0; C_po_counter_read_en = 0; C_po_counter_load_val = 0; C_po_sel_fine_oclk_delay = 0; C_idelay_ce = 0; C_idelay_ld = 0; C_fine_delay = 0; C_fine_delay_sel = 0; D_pi_fine_enable = 0; D_pi_fine_inc = 0; D_pi_counter_load_en = 0; D_pi_counter_read_en = 0; D_pi_counter_load_val = 0; D_pi_rst_dqs_find = 0; D_po_fine_enable = 0; D_po_coarse_enable = 0; D_po_fine_inc = 0; D_po_coarse_inc = 0; D_po_counter_load_en = 0; D_po_counter_read_en = 0; D_po_counter_load_val = 0; D_po_sel_fine_oclk_delay = 0; D_idelay_ce = 0; D_idelay_ld = 0; D_fine_delay = 0; D_fine_delay_sel = 0; if ( calib_sel[2]) begin // if this is asserted, all calib signals are deasserted A_pi_fine_enable = 0; A_pi_fine_inc = 0; A_pi_counter_load_en = 0; A_pi_counter_read_en = 0; A_pi_counter_load_val = 0; A_pi_rst_dqs_find = 0; A_po_fine_enable = 0; A_po_coarse_enable = 0; A_po_fine_inc = 0; A_po_coarse_inc = 0; A_po_counter_load_en = 0; A_po_counter_read_en = 0; A_po_counter_load_val = 0; A_po_sel_fine_oclk_delay = 0; A_idelay_ce = 0; A_idelay_ld = 0; A_fine_delay = 0; A_fine_delay_sel = 0; B_pi_fine_enable = 0; B_pi_fine_inc = 0; B_pi_counter_load_en = 0; B_pi_counter_read_en = 0; B_pi_counter_load_val = 0; B_pi_rst_dqs_find = 0; B_po_fine_enable = 0; B_po_coarse_enable = 0; B_po_fine_inc = 0; B_po_coarse_inc = 0; B_po_counter_load_en = 0; B_po_counter_read_en = 0; B_po_counter_load_val = 0; B_po_sel_fine_oclk_delay = 0; B_idelay_ce = 0; B_idelay_ld = 0; B_fine_delay = 0; B_fine_delay_sel = 0; C_pi_fine_enable = 0; C_pi_fine_inc = 0; C_pi_counter_load_en = 0; C_pi_counter_read_en = 0; C_pi_counter_load_val = 0; C_pi_rst_dqs_find = 0; C_po_fine_enable = 0; C_po_coarse_enable = 0; C_po_fine_inc = 0; C_po_coarse_inc = 0; C_po_counter_load_en = 0; C_po_counter_read_en = 0; C_po_counter_load_val = 0; C_po_sel_fine_oclk_delay = 0; C_idelay_ce = 0; C_idelay_ld = 0; C_fine_delay = 0; C_fine_delay_sel = 0; D_pi_fine_enable = 0; D_pi_fine_inc = 0; D_pi_counter_load_en = 0; D_pi_counter_read_en = 0; D_pi_counter_load_val = 0; D_pi_rst_dqs_find = 0; D_po_fine_enable = 0; D_po_coarse_enable = 0; D_po_fine_inc = 0; D_po_coarse_inc = 0; D_po_counter_load_en = 0; D_po_counter_read_en = 0; D_po_counter_load_val = 0; D_po_sel_fine_oclk_delay = 0; D_idelay_ce = 0; D_idelay_ld = 0; D_fine_delay = 0; D_fine_delay_sel = 0; end else if (calib_in_common) begin // if this is asserted, each signal is broadcast to all phasers // in common if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin A_pi_fine_enable = pi_fine_enable; A_pi_fine_inc = pi_fine_inc; A_pi_counter_load_en = pi_counter_load_en; A_pi_counter_read_en = pi_counter_read_en; A_pi_counter_load_val = pi_counter_load_val; A_pi_rst_dqs_find = pi_rst_dqs_find; A_po_fine_enable = po_fine_enable; A_po_coarse_enable = po_coarse_enable; A_po_fine_inc = po_fine_inc; A_po_coarse_inc = po_coarse_inc; A_po_counter_load_en = po_counter_load_en; A_po_counter_read_en = po_counter_read_en; A_po_counter_load_val = po_counter_load_val; A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; A_idelay_ce = idelay_ce; A_idelay_ld = idelay_ld; A_fine_delay = fine_delay ; A_fine_delay_sel = fine_delay_sel; end if ( B_mux_ctrl) begin B_pi_fine_enable = pi_fine_enable; B_pi_fine_inc = pi_fine_inc; B_pi_counter_load_en = pi_counter_load_en; B_pi_counter_read_en = pi_counter_read_en; B_pi_counter_load_val = pi_counter_load_val; B_pi_rst_dqs_find = pi_rst_dqs_find; B_po_fine_enable = po_fine_enable; B_po_coarse_enable = po_coarse_enable; B_po_fine_inc = po_fine_inc; B_po_coarse_inc = po_coarse_inc; B_po_counter_load_en = po_counter_load_en; B_po_counter_read_en = po_counter_read_en; B_po_counter_load_val = po_counter_load_val; B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; B_idelay_ce = idelay_ce; B_idelay_ld = idelay_ld; B_fine_delay = fine_delay ; B_fine_delay_sel = fine_delay_sel; end if ( C_mux_ctrl) begin C_pi_fine_enable = pi_fine_enable; C_pi_fine_inc = pi_fine_inc; C_pi_counter_load_en = pi_counter_load_en; C_pi_counter_read_en = pi_counter_read_en; C_pi_counter_load_val = pi_counter_load_val; C_pi_rst_dqs_find = pi_rst_dqs_find; C_po_fine_enable = po_fine_enable; C_po_coarse_enable = po_coarse_enable; C_po_fine_inc = po_fine_inc; C_po_coarse_inc = po_coarse_inc; C_po_counter_load_en = po_counter_load_en; C_po_counter_read_en = po_counter_read_en; C_po_counter_load_val = po_counter_load_val; C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; C_idelay_ce = idelay_ce; C_idelay_ld = idelay_ld; C_fine_delay = fine_delay ; C_fine_delay_sel = fine_delay_sel; end if ( D_mux_ctrl) begin D_pi_fine_enable = pi_fine_enable; D_pi_fine_inc = pi_fine_inc; D_pi_counter_load_en = pi_counter_load_en; D_pi_counter_read_en = pi_counter_read_en; D_pi_counter_load_val = pi_counter_load_val; D_pi_rst_dqs_find = pi_rst_dqs_find; D_po_fine_enable = po_fine_enable; D_po_coarse_enable = po_coarse_enable; D_po_fine_inc = po_fine_inc; D_po_coarse_inc = po_coarse_inc; D_po_counter_load_en = po_counter_load_en; D_po_counter_read_en = po_counter_read_en; D_po_counter_load_val = po_counter_load_val; D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; D_idelay_ce = idelay_ce; D_idelay_ld = idelay_ld; D_fine_delay = fine_delay ; D_fine_delay_sel = fine_delay_sel; end end else begin // otherwise, only a single phaser is selected case (calib_sel[1:0]) 0: begin A_pi_fine_enable = pi_fine_enable; A_pi_fine_inc = pi_fine_inc; A_pi_counter_load_en = pi_counter_load_en; A_pi_counter_read_en = pi_counter_read_en; A_pi_counter_load_val = pi_counter_load_val; A_pi_rst_dqs_find = pi_rst_dqs_find; A_po_fine_enable = po_fine_enable; A_po_coarse_enable = po_coarse_enable; A_po_fine_inc = po_fine_inc; A_po_coarse_inc = po_coarse_inc; A_po_counter_load_en = po_counter_load_en; A_po_counter_read_en = po_counter_read_en; A_po_counter_load_val = po_counter_load_val; A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; A_idelay_ce = idelay_ce; A_idelay_ld = idelay_ld; A_fine_delay = fine_delay ; A_fine_delay_sel = fine_delay_sel; end 1: begin B_pi_fine_enable = pi_fine_enable; B_pi_fine_inc = pi_fine_inc; B_pi_counter_load_en = pi_counter_load_en; B_pi_counter_read_en = pi_counter_read_en; B_pi_counter_load_val = pi_counter_load_val; B_pi_rst_dqs_find = pi_rst_dqs_find; B_po_fine_enable = po_fine_enable; B_po_coarse_enable = po_coarse_enable; B_po_fine_inc = po_fine_inc; B_po_coarse_inc = po_coarse_inc; B_po_counter_load_en = po_counter_load_en; B_po_counter_read_en = po_counter_read_en; B_po_counter_load_val = po_counter_load_val; B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; B_idelay_ce = idelay_ce; B_idelay_ld = idelay_ld; B_fine_delay = fine_delay ; B_fine_delay_sel = fine_delay_sel; end 2: begin C_pi_fine_enable = pi_fine_enable; C_pi_fine_inc = pi_fine_inc; C_pi_counter_load_en = pi_counter_load_en; C_pi_counter_read_en = pi_counter_read_en; C_pi_counter_load_val = pi_counter_load_val; C_pi_rst_dqs_find = pi_rst_dqs_find; C_po_fine_enable = po_fine_enable; C_po_coarse_enable = po_coarse_enable; C_po_fine_inc = po_fine_inc; C_po_coarse_inc = po_coarse_inc; C_po_counter_load_en = po_counter_load_en; C_po_counter_read_en = po_counter_read_en; C_po_counter_load_val = po_counter_load_val; C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; C_idelay_ce = idelay_ce; C_idelay_ld = idelay_ld; C_fine_delay = fine_delay ; C_fine_delay_sel = fine_delay_sel; end 3: begin D_pi_fine_enable = pi_fine_enable; D_pi_fine_inc = pi_fine_inc; D_pi_counter_load_en = pi_counter_load_en; D_pi_counter_read_en = pi_counter_read_en; D_pi_counter_load_val = pi_counter_load_val; D_pi_rst_dqs_find = pi_rst_dqs_find; D_po_fine_enable = po_fine_enable; D_po_coarse_enable = po_coarse_enable; D_po_fine_inc = po_fine_inc; D_po_coarse_inc = po_coarse_inc; D_po_counter_load_en = po_counter_load_en; D_po_counter_load_val = po_counter_load_val; D_po_counter_read_en = po_counter_read_en; D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; D_idelay_ce = idelay_ce; D_idelay_ld = idelay_ld; D_fine_delay = fine_delay ; D_fine_delay_sel = fine_delay_sel; end endcase end end //obligatory phaser-ref PHASER_REF phaser_ref_i( .LOCKED (ref_dll_lock), .CLKIN (freq_refclk), .PWRDWN (1'b0), .RST ( ! pll_lock) ); // optional idelay_ctrl generate if ( GENERATE_IDELAYCTRL == "TRUE") IDELAYCTRL idelayctrl ( .RDY (/*idelayctrl_rdy*/), .REFCLK (idelayctrl_refclk), .RST (rst) ); endgenerate endmodule
/********************************************************** -- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). A Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. // // THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. // // // Owner: Gary Martin // Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $ // $Author: gary $ // $DateTime: 2010/05/11 18:05:17 $ // $Change: 490882 $ // Description: // This verilog file is the parameterizable 4-byte lane phy primitive top // This module may be ganged to create an N-lane phy. // // History: // Date Engineer Description // 04/01/2010 G. Martin Initial Checkin. // /////////////////////////////////////////////////////////// **********************************************************/ `timescale 1ps/1ps `define PC_DATA_OFFSET_RANGE 22:17 module mig_7series_v2_3_ddr_phy_4lanes #( parameter GENERATE_IDELAYCTRL = "TRUE", parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010, parameter NUM_DDR_CK = 1, // next three parameter fields correspond to byte lanes for lane order DCBA parameter BYTE_LANES = 4'b1111, // lane existence, one per lane parameter DATA_CTL_N = 4'b1111, // data or control, per lane parameter BITLANES = 48'hffff_ffff_ffff, parameter BITLANES_OUTONLY = 48'h0000_0000_0000, parameter LANE_REMAP = 16'h3210,// 4-bit index // used to rewire to one of four // input/output buss lanes // example: 0321 remaps lanes as: // D->A // C->D // B->C // A->B parameter LAST_BANK = "FALSE", parameter USE_PRE_POST_FIFO = "FALSE", parameter RCLK_SELECT_LANE = "B", parameter real TCK = 0.00, parameter SYNTHESIS = "FALSE", parameter PO_CTL_COARSE_BYPASS = "FALSE", parameter PO_FINE_DELAY = 0, parameter PI_SEL_CLK_OFFSET = 0, // phy_control paramter used in other paramsters parameter PC_CLK_RATIO = 4, //phaser_in parameters parameter A_PI_FREQ_REF_DIV = "NONE", parameter A_PI_CLKOUT_DIV = 2, parameter A_PI_BURST_MODE = "TRUE", parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF", parameter A_PI_FINE_DELAY = 60, parameter A_PI_SYNC_IN_DIV_RST = "TRUE", parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter B_PI_BURST_MODE = A_PI_BURST_MODE, parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY, parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter C_PI_BURST_MODE = A_PI_BURST_MODE, parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter C_PI_FINE_DELAY = 0, parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter D_PI_BURST_MODE = A_PI_BURST_MODE, parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter D_PI_FINE_DELAY = 0, parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, //phaser_out parameters parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2, parameter A_PO_FINE_DELAY = PO_FINE_DELAY, parameter A_PO_COARSE_DELAY = 0, parameter A_PO_OCLK_DELAY = 0, parameter A_PO_OCLKDELAY_INV = "FALSE", parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF", parameter A_PO_SYNC_IN_DIV_RST = "TRUE", //parameter A_PO_SYNC_IN_DIV_RST = "FALSE", parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2, parameter B_PO_FINE_DELAY = PO_FINE_DELAY, parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2, parameter C_PO_FINE_DELAY = PO_FINE_DELAY, parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2, parameter D_PO_FINE_DELAY = PO_FINE_DELAY, parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE", parameter A_IDELAYE2_IDELAY_VALUE = 00, parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, // phy_control parameters parameter PC_BURST_MODE = "TRUE", parameter PC_DATA_CTL_N = DATA_CTL_N, parameter PC_CMD_OFFSET = 0, parameter PC_RD_CMD_OFFSET_0 = 0, parameter PC_RD_CMD_OFFSET_1 = 0, parameter PC_RD_CMD_OFFSET_2 = 0, parameter PC_RD_CMD_OFFSET_3 = 0, parameter PC_CO_DURATION = 1, parameter PC_DI_DURATION = 1, parameter PC_DO_DURATION = 1, parameter PC_RD_DURATION_0 = 0, parameter PC_RD_DURATION_1 = 0, parameter PC_RD_DURATION_2 = 0, parameter PC_RD_DURATION_3 = 0, parameter PC_WR_CMD_OFFSET_0 = 5, parameter PC_WR_CMD_OFFSET_1 = 5, parameter PC_WR_CMD_OFFSET_2 = 5, parameter PC_WR_CMD_OFFSET_3 = 5, parameter PC_WR_DURATION_0 = 6, parameter PC_WR_DURATION_1 = 6, parameter PC_WR_DURATION_2 = 6, parameter PC_WR_DURATION_3 = 6, parameter PC_AO_WRLVL_EN = 0, parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE) parameter PC_FOUR_WINDOW_CLOCKS = 63, parameter PC_EVENTS_DELAY = 18, parameter PC_PHY_COUNT_EN = "TRUE", parameter PC_SYNC_MODE = "TRUE", parameter PC_DISABLE_SEQ_MATCH = "TRUE", parameter PC_MULTI_REGION = "FALSE", // io fifo parameters parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter OF_ALMOST_EMPTY_VALUE = 1, parameter OF_ALMOST_FULL_VALUE = 1, parameter OF_OUTPUT_DISABLE = "TRUE", parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE, parameter A_OS_DATA_RATE = "DDR", parameter A_OS_DATA_WIDTH = 4, parameter B_OS_DATA_RATE = A_OS_DATA_RATE, parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter C_OS_DATA_RATE = A_OS_DATA_RATE, parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter D_OS_DATA_RATE = A_OS_DATA_RATE, parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8", parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter IF_ALMOST_EMPTY_VALUE = 1, parameter IF_ALMOST_FULL_VALUE = 1, parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE, // this is used locally, not for external pushdown // NOTE: the 0+ is needed in each to coerce to integer for addition. // otherwise 4x 1'b values are added producing a 1'b value. parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1), parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])), parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]), parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES, // assume odt per rank + any declared cke's parameter AUXOUT_WIDTH = 4, parameter LP_DDR_CK_WIDTH = 2 ,parameter CKE_ODT_AUX = "FALSE" ) ( //`include "phy.vh" input rst, input phy_clk, input phy_ctl_clk, input freq_refclk, input mem_refclk, input mem_refclk_div4, input pll_lock, input sync_pulse, input idelayctrl_refclk, input [HIGHEST_LANE*80-1:0] phy_dout, input phy_cmd_wr_en, input phy_data_wr_en, input phy_rd_en, input phy_ctl_mstr_empty, input [31:0] phy_ctl_wd, input [`PC_DATA_OFFSET_RANGE] data_offset, input phy_ctl_wr, input if_empty_def, input phyGo, input input_sink, output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory output rclk, output if_a_empty, output if_empty, output byte_rd_en, output if_empty_or, output if_empty_and, output of_ctl_a_full, output of_data_a_full, output of_ctl_full, output of_data_full, output pre_data_a_full, output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus output phy_ctl_empty, output phy_ctl_a_full, output phy_ctl_full, output [HIGHEST_LANE*12-1:0]mem_dq_out, output [HIGHEST_LANE*12-1:0]mem_dq_ts, input [HIGHEST_LANE*10-1:0]mem_dq_in, output [HIGHEST_LANE-1:0] mem_dqs_out, output [HIGHEST_LANE-1:0] mem_dqs_ts, input [HIGHEST_LANE-1:0] mem_dqs_in, input [1:0] byte_rd_en_oth_banks, output [AUXOUT_WIDTH-1:0] aux_out, output reg rst_out = 0, output reg mcGo=0, output phy_ctl_ready, output ref_dll_lock, input if_rst, input phy_read_calib, input phy_write_calib, input idelay_inc, input idelay_ce, input idelay_ld, input [2:0] calib_sel, input calib_zero_ctrl, input [HIGHEST_LANE-1:0] calib_zero_lanes, input calib_in_common, input po_fine_enable, input po_coarse_enable, input po_fine_inc, input po_coarse_inc, input po_counter_load_en, input po_counter_read_en, input [8:0] po_counter_load_val, input po_sel_fine_oclk_delay, output reg po_coarse_overflow, output reg po_fine_overflow, output reg [8:0] po_counter_read_val, input pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input pi_counter_read_en, input [5:0] pi_counter_load_val, output reg pi_fine_overflow, output reg [5:0] pi_counter_read_val, output reg pi_dqs_found, output pi_dqs_found_all, output pi_dqs_found_any, output [HIGHEST_LANE-1:0] pi_phase_locked_lanes, output [HIGHEST_LANE-1:0] pi_dqs_found_lanes, output reg pi_dqs_out_of_range, output reg pi_phase_locked, output pi_phase_locked_all, input [29:0] fine_delay, input fine_delay_sel ); localparam DATA_CTL_A = (~DATA_CTL_N[0]); localparam DATA_CTL_B = (~DATA_CTL_N[1]); localparam DATA_CTL_C = (~DATA_CTL_N[2]); localparam DATA_CTL_D = (~DATA_CTL_N[3]); localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0]; localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1]; localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2]; localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3]; localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0]; localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1]; localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2]; localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3]; localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE"; localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam IO_A_START = 41; localparam IO_A_END = 40; localparam IO_B_START = 43; localparam IO_B_END = 42; localparam IO_C_START = 45; localparam IO_C_END = 44; localparam IO_D_START = 47; localparam IO_D_END = 46; localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1; localparam IO_A_X_END = (IO_A_X_START-1); localparam IO_B_X_START = (IO_A_X_START + 2); localparam IO_B_X_END = (IO_B_X_START -1); localparam IO_C_X_START = (IO_B_X_START + 2); localparam IO_C_X_END = (IO_C_X_START -1); localparam IO_D_X_START = (IO_C_X_START + 2); localparam IO_D_X_END = (IO_D_X_START -1); localparam MSB_BURST_PEND_PO = 3; localparam MSB_BURST_PEND_PI = 7; localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8; localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1; wire [1:0] oserdes_dqs; wire [1:0] oserdes_dqs_ts; wire [1:0] oserdes_dq_ts; wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus; wire [7:0] in_rank; wire [11:0] IO_A; wire [11:0] IO_B; wire [11:0] IO_C; wire [11:0] IO_D; wire [319:0] phy_din_remap; reg A_po_counter_read_en; wire [8:0] A_po_counter_read_val; reg A_pi_counter_read_en; wire [5:0] A_pi_counter_read_val; wire A_pi_fine_overflow; wire A_po_coarse_overflow; wire A_po_fine_overflow; wire A_pi_dqs_found; wire A_pi_dqs_out_of_range; wire A_pi_phase_locked; wire A_pi_iserdes_rst; reg A_pi_fine_enable; reg A_pi_fine_inc; reg A_pi_counter_load_en; reg [5:0] A_pi_counter_load_val; reg A_pi_rst_dqs_find; reg A_po_fine_enable; reg A_po_coarse_enable; reg A_po_fine_inc /* synthesis syn_maxfan = 3 */; reg A_po_sel_fine_oclk_delay; reg A_po_coarse_inc; reg A_po_counter_load_en; reg [8:0] A_po_counter_load_val; wire A_rclk; reg A_idelay_ce; reg A_idelay_ld; reg [29:0] A_fine_delay; reg A_fine_delay_sel; reg B_po_counter_read_en; wire [8:0] B_po_counter_read_val; reg B_pi_counter_read_en; wire [5:0] B_pi_counter_read_val; wire B_pi_fine_overflow; wire B_po_coarse_overflow; wire B_po_fine_overflow; wire B_pi_phase_locked; wire B_pi_iserdes_rst; wire B_pi_dqs_found; wire B_pi_dqs_out_of_range; reg B_pi_fine_enable; reg B_pi_fine_inc; reg B_pi_counter_load_en; reg [5:0] B_pi_counter_load_val; reg B_pi_rst_dqs_find; reg B_po_fine_enable; reg B_po_coarse_enable; reg B_po_fine_inc /* synthesis syn_maxfan = 3 */; reg B_po_coarse_inc; reg B_po_sel_fine_oclk_delay; reg B_po_counter_load_en; reg [8:0] B_po_counter_load_val; wire B_rclk; reg B_idelay_ce; reg B_idelay_ld; reg [29:0] B_fine_delay; reg B_fine_delay_sel; reg C_pi_fine_inc; reg D_pi_fine_inc; reg C_pi_fine_enable; reg D_pi_fine_enable; reg C_po_counter_load_en; reg D_po_counter_load_en; reg C_po_coarse_inc; reg D_po_coarse_inc; reg C_po_fine_inc /* synthesis syn_maxfan = 3 */; reg D_po_fine_inc /* synthesis syn_maxfan = 3 */; reg C_po_sel_fine_oclk_delay; reg D_po_sel_fine_oclk_delay; reg [5:0] C_pi_counter_load_val; reg [5:0] D_pi_counter_load_val; reg [8:0] C_po_counter_load_val; reg [8:0] D_po_counter_load_val; reg C_po_coarse_enable; reg D_po_coarse_enable; reg C_po_fine_enable; reg D_po_fine_enable; wire C_po_coarse_overflow; wire D_po_coarse_overflow; wire C_po_fine_overflow; wire D_po_fine_overflow; wire [8:0] C_po_counter_read_val; wire [8:0] D_po_counter_read_val; reg C_po_counter_read_en; reg D_po_counter_read_en; wire C_pi_dqs_found; wire D_pi_dqs_found; wire C_pi_fine_overflow; wire D_pi_fine_overflow; reg C_pi_counter_read_en; reg D_pi_counter_read_en; reg C_pi_counter_load_en; reg D_pi_counter_load_en; wire C_pi_phase_locked; wire C_pi_iserdes_rst; wire D_pi_phase_locked; wire D_pi_iserdes_rst; wire C_pi_dqs_out_of_range; wire D_pi_dqs_out_of_range; wire [5:0] C_pi_counter_read_val; wire [5:0] D_pi_counter_read_val; wire C_rclk; wire D_rclk; reg C_idelay_ce; reg D_idelay_ce; reg C_idelay_ld; reg D_idelay_ld; reg C_pi_rst_dqs_find; reg D_pi_rst_dqs_find; reg [29:0] C_fine_delay; reg [29:0] D_fine_delay; reg C_fine_delay_sel; reg D_fine_delay_sel; wire pi_iserdes_rst; wire A_if_empty; wire B_if_empty; wire C_if_empty; wire D_if_empty; wire A_byte_rd_en; wire B_byte_rd_en; wire C_byte_rd_en; wire D_byte_rd_en; wire A_if_a_empty; wire B_if_a_empty; wire C_if_a_empty; wire D_if_a_empty; //wire A_if_full; //wire B_if_full; //wire C_if_full; //wire D_if_full; //wire A_of_empty; //wire B_of_empty; //wire C_of_empty; //wire D_of_empty; wire A_of_full; wire B_of_full; wire C_of_full; wire D_of_full; wire A_of_ctl_full; wire B_of_ctl_full; wire C_of_ctl_full; wire D_of_ctl_full; wire A_of_data_full; wire B_of_data_full; wire C_of_data_full; wire D_of_data_full; wire A_of_a_full; wire B_of_a_full; wire C_of_a_full; wire D_of_a_full; wire A_pre_fifo_a_full; wire B_pre_fifo_a_full; wire C_pre_fifo_a_full; wire D_pre_fifo_a_full; wire A_of_ctl_a_full; wire B_of_ctl_a_full; wire C_of_ctl_a_full; wire D_of_ctl_a_full; wire A_of_data_a_full; wire B_of_data_a_full; wire C_of_data_a_full; wire D_of_data_a_full; wire A_pre_data_a_full; wire B_pre_data_a_full; wire C_pre_data_a_full; wire D_pre_data_a_full; wire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation wire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; // wire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; // wire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; // wire [3:0] dummy_data; wire [31:0] _phy_ctl_wd; wire [1:0] phy_encalib; assign pi_dqs_found_all = (! PRESENT_DATA_A | A_pi_dqs_found) & (! PRESENT_DATA_B | B_pi_dqs_found) & (! PRESENT_DATA_C | C_pi_dqs_found) & (! PRESENT_DATA_D | D_pi_dqs_found) ; assign pi_dqs_found_any = ( PRESENT_DATA_A & A_pi_dqs_found) | ( PRESENT_DATA_B & B_pi_dqs_found) | ( PRESENT_DATA_C & C_pi_dqs_found) | ( PRESENT_DATA_D & D_pi_dqs_found) ; assign pi_phase_locked_all = (! PRESENT_DATA_A | A_pi_phase_locked) & (! PRESENT_DATA_B | B_pi_phase_locked) & (! PRESENT_DATA_C | C_pi_phase_locked) & (! PRESENT_DATA_D | D_pi_phase_locked); wire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal // which is combined into another signals such that // the other signal isn't changed. The purpose // is to fake the tools into ignoring dangling inputs. // Because it is anded with 1'b0, the contributing signals // are folded as constants or trimmed. assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty); assign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) : (A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en); assign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty); assign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty); assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty; //assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ; //assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty; assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ; assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ; assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ; assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ; assign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full; function [79:0] part_select_80; input [319:0] vector; input [1:0] select; begin case (select) 2'b00 : part_select_80[79:0] = vector[1*80-1:0*80]; 2'b01 : part_select_80[79:0] = vector[2*80-1:1*80]; 2'b10 : part_select_80[79:0] = vector[3*80-1:2*80]; 2'b11 : part_select_80[79:0] = vector[4*80-1:3*80]; endcase end endfunction wire [319:0] phy_dout_remap; reg rst_out_trig = 1'b0; reg [31:0] rclk_delay; reg rst_edge1 = 1'b0; reg rst_edge2 = 1'b0; reg rst_edge3 = 1'b0; reg rst_edge_detect = 1'b0; wire rclk_; reg rst_out_start = 1'b0 ; reg rst_primitives=0; reg A_rst_primitives=0; reg B_rst_primitives=0; reg C_rst_primitives=0; reg D_rst_primitives=0; `ifdef USE_PHY_CONTROL_TEST wire [15:0] test_output; wire [15:0] test_input; wire [2:0] test_select=0; wire scan_enable = 0; `endif generate genvar i; if (RCLK_SELECT_LANE == "A") begin assign rclk_ = A_rclk; assign pi_iserdes_rst = A_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "B") begin assign rclk_ = B_rclk; assign pi_iserdes_rst = B_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "C") begin assign rclk_ = C_rclk; assign pi_iserdes_rst = C_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "D") begin assign rclk_ = D_rclk; assign pi_iserdes_rst = D_pi_iserdes_rst; end else begin assign rclk_ = B_rclk; // default end endgenerate assign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk; assign pi_phase_locked_lanes = {(! PRESENT_DATA_A[0] | A_pi_phase_locked), (! PRESENT_DATA_B[0] | B_pi_phase_locked) , (! PRESENT_DATA_C[0] | C_pi_phase_locked) , (! PRESENT_DATA_D[0] | D_pi_phase_locked)}; assign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found}; // this block scrubs X from rclk_delay[11] reg rclk_delay_11; always @(rclk_delay[11]) begin : rclk_delay_11_blk if ( rclk_delay[11]) rclk_delay_11 = 1; else rclk_delay_11 = 0; end always @(posedge phy_clk or posedge rst ) begin // scrub 4-state values from rclk_delay[11] if ( rst) begin rst_out <= #1 0; end else begin if ( rclk_delay_11) rst_out <= #1 1; end end always @(posedge phy_clk ) begin // phy_ctl_ready drives reset of the system rst_primitives <= !phy_ctl_ready ; A_rst_primitives <= rst_primitives ; B_rst_primitives <= rst_primitives ; C_rst_primitives <= rst_primitives ; D_rst_primitives <= rst_primitives ; rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo); mcGo <= #1 rst_out ; end generate if (BYTE_LANES[0]) begin assign dummy_data[0] = 0; end else begin assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80]; end if (BYTE_LANES[1]) begin assign dummy_data[1] = 0; end else begin assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80]; end if (BYTE_LANES[2]) begin assign dummy_data[2] = 0; end else begin assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80]; end if (BYTE_LANES[3]) begin assign dummy_data[3] = 0; end else begin assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80]; end if (PRESENT_DATA_A) begin assign A_of_data_full = A_of_full; assign A_of_ctl_full = 0; assign A_of_data_a_full = A_of_a_full; assign A_of_ctl_a_full = 0; assign A_pre_data_a_full = A_pre_fifo_a_full; end else begin assign A_of_ctl_full = A_of_full; assign A_of_data_full = 0; assign A_of_ctl_a_full = A_of_a_full; assign A_of_data_a_full = 0; assign A_pre_data_a_full = 0; end if (PRESENT_DATA_B) begin assign B_of_data_full = B_of_full; assign B_of_ctl_full = 0; assign B_of_data_a_full = B_of_a_full; assign B_of_ctl_a_full = 0; assign B_pre_data_a_full = B_pre_fifo_a_full; end else begin assign B_of_ctl_full = B_of_full; assign B_of_data_full = 0; assign B_of_ctl_a_full = B_of_a_full; assign B_of_data_a_full = 0; assign B_pre_data_a_full = 0; end if (PRESENT_DATA_C) begin assign C_of_data_full = C_of_full; assign C_of_ctl_full = 0; assign C_of_data_a_full = C_of_a_full; assign C_of_ctl_a_full = 0; assign C_pre_data_a_full = C_pre_fifo_a_full; end else begin assign C_of_ctl_full = C_of_full; assign C_of_data_full = 0; assign C_of_ctl_a_full = C_of_a_full; assign C_of_data_a_full = 0; assign C_pre_data_a_full = 0; end if (PRESENT_DATA_D) begin assign D_of_data_full = D_of_full; assign D_of_ctl_full = 0; assign D_of_data_a_full = D_of_a_full; assign D_of_ctl_a_full = 0; assign D_pre_data_a_full = D_pre_fifo_a_full; end else begin assign D_of_ctl_full = D_of_full; assign D_of_data_full = 0; assign D_of_ctl_a_full = D_of_a_full; assign D_of_data_a_full = 0; assign D_pre_data_a_full = 0; end // byte lane must exist and be data lane. if (PRESENT_DATA_A ) case ( LANE_REMAP[1:0] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0]; endcase else case ( LANE_REMAP[1:0] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_B ) case ( LANE_REMAP[5:4] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80]; endcase else if (HIGHEST_LANE > 1) case ( LANE_REMAP[5:4] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_C) case ( LANE_REMAP[9:8] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160]; endcase else if (HIGHEST_LANE > 2) case ( LANE_REMAP[9:8] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_D ) case ( LANE_REMAP[13:12] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240]; endcase else if (HIGHEST_LANE > 3) case ( LANE_REMAP[13:12] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (HIGHEST_LANE > 1) assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]}; if (HIGHEST_LANE == 1) assign _phy_ctl_wd = phy_ctl_wd; //BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst)); BUFIO rclk_buf(.I(rclk_), .O(rclk) ); if ( BYTE_LANES[0] ) begin : ddr_byte_lane_A assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("A"), .PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[11:0]), .BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (A_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (A_PI_BURST_MODE), .PI_CLKOUT_DIV (A_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV), .PI_FINE_DELAY (A_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (A_PO_CLKOUT_DIV), .PO_FINE_DELAY (A_PO_FINE_DELAY), .PO_COARSE_BYPASS (A_PO_COARSE_BYPASS), .PO_COARSE_DELAY (A_PO_COARSE_DELAY), .PO_OCLK_DELAY (A_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (A_OS_DATA_RATE), .OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_A( .mem_dq_out (mem_dq_out[11:0]), .mem_dq_ts (mem_dq_ts[11:0]), .mem_dq_in (mem_dq_in[9:0]), .mem_dqs_out (mem_dqs_out[0]), .mem_dqs_ts (mem_dqs_ts[0]), .mem_dqs_in (mem_dqs_in[0]), .rst (A_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (A_ddr_clk), .rclk (A_rclk), .pi_dqs_found (A_pi_dqs_found), .dqs_out_of_range (A_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (A_if_a_empty), .if_empty (A_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*A_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*A_of_empty*/), .of_a_full (A_of_a_full), .of_full (A_of_full), .pre_fifo_a_full (A_pre_fifo_a_full), .phy_din (phy_din_remap[79:0]), .phy_dout (phy_dout_remap[79:0]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (A_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (A_idelay_ce), .idelay_ld (A_idelay_ld), .pi_rst_dqs_find (A_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (A_po_fine_enable), .po_coarse_enable (A_po_coarse_enable), .po_fine_inc (A_po_fine_inc), .po_coarse_inc (A_po_coarse_inc), .po_counter_load_en (A_po_counter_load_en), .po_counter_read_en (A_po_counter_read_en), .po_counter_load_val (A_po_counter_load_val), .po_coarse_overflow (A_po_coarse_overflow), .po_fine_overflow (A_po_fine_overflow), .po_counter_read_val (A_po_counter_read_val), .po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (A_pi_fine_enable), .pi_fine_inc (A_pi_fine_inc), .pi_counter_load_en (A_pi_counter_load_en), .pi_counter_read_en (A_pi_counter_read_en), .pi_counter_load_val (A_pi_counter_load_val), .pi_fine_overflow (A_pi_fine_overflow), .pi_counter_read_val (A_pi_counter_read_val), .pi_iserdes_rst (A_pi_iserdes_rst), .pi_phase_locked (A_pi_phase_locked), .fine_delay (A_fine_delay), .fine_delay_sel (A_fine_delay_sel) ); end else begin : no_ddr_byte_lane_A assign A_of_a_full = 1'b0; assign A_of_full = 1'b0; assign A_pre_fifo_a_full = 1'b0; assign A_if_empty = 1'b0; assign A_byte_rd_en = 1'b1; assign A_if_a_empty = 1'b0; assign A_pi_phase_locked = 1; assign A_pi_dqs_found = 1; assign A_rclk = 0; assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign A_pi_counter_read_val = 0; assign A_po_counter_read_val = 0; assign A_pi_fine_overflow = 0; assign A_po_coarse_overflow = 0; assign A_po_fine_overflow = 0; end if ( BYTE_LANES[1] ) begin : ddr_byte_lane_B assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("B"), .PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[23:12]), .BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (B_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (B_PI_BURST_MODE), .PI_CLKOUT_DIV (B_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV), .PI_FINE_DELAY (B_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (B_PO_CLKOUT_DIV), .PO_FINE_DELAY (B_PO_FINE_DELAY), .PO_COARSE_BYPASS (B_PO_COARSE_BYPASS), .PO_COARSE_DELAY (B_PO_COARSE_DELAY), .PO_OCLK_DELAY (B_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (B_OS_DATA_RATE), .OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_B( .mem_dq_out (mem_dq_out[23:12]), .mem_dq_ts (mem_dq_ts[23:12]), .mem_dq_in (mem_dq_in[19:10]), .mem_dqs_out (mem_dqs_out[1]), .mem_dqs_ts (mem_dqs_ts[1]), .mem_dqs_in (mem_dqs_in[1]), .rst (B_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (B_ddr_clk), .rclk (B_rclk), .pi_dqs_found (B_pi_dqs_found), .dqs_out_of_range (B_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (B_if_a_empty), .if_empty (B_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*B_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*B_of_empty*/), .of_a_full (B_of_a_full), .of_full (B_of_full), .pre_fifo_a_full (B_pre_fifo_a_full), .phy_din (phy_din_remap[159:80]), .phy_dout (phy_dout_remap[159:80]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (B_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (B_idelay_ce), .idelay_ld (B_idelay_ld), .pi_rst_dqs_find (B_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (B_po_fine_enable), .po_coarse_enable (B_po_coarse_enable), .po_fine_inc (B_po_fine_inc), .po_coarse_inc (B_po_coarse_inc), .po_counter_load_en (B_po_counter_load_en), .po_counter_read_en (B_po_counter_read_en), .po_counter_load_val (B_po_counter_load_val), .po_coarse_overflow (B_po_coarse_overflow), .po_fine_overflow (B_po_fine_overflow), .po_counter_read_val (B_po_counter_read_val), .po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (B_pi_fine_enable), .pi_fine_inc (B_pi_fine_inc), .pi_counter_load_en (B_pi_counter_load_en), .pi_counter_read_en (B_pi_counter_read_en), .pi_counter_load_val (B_pi_counter_load_val), .pi_fine_overflow (B_pi_fine_overflow), .pi_counter_read_val (B_pi_counter_read_val), .pi_iserdes_rst (B_pi_iserdes_rst), .pi_phase_locked (B_pi_phase_locked), .fine_delay (B_fine_delay), .fine_delay_sel (B_fine_delay_sel) ); end else begin : no_ddr_byte_lane_B assign B_of_a_full = 1'b0; assign B_of_full = 1'b0; assign B_pre_fifo_a_full = 1'b0; assign B_if_empty = 1'b0; assign B_if_a_empty = 1'b0; assign B_byte_rd_en = 1'b1; assign B_pi_phase_locked = 1; assign B_pi_dqs_found = 1; assign B_rclk = 0; assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign B_pi_counter_read_val = 0; assign B_po_counter_read_val = 0; assign B_pi_fine_overflow = 0; assign B_po_coarse_overflow = 0; assign B_po_fine_overflow = 0; end if ( BYTE_LANES[2] ) begin : ddr_byte_lane_C assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("C"), .PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[35:24]), .BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (C_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (C_PI_BURST_MODE), .PI_CLKOUT_DIV (C_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV), .PI_FINE_DELAY (C_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (C_PO_CLKOUT_DIV), .PO_FINE_DELAY (C_PO_FINE_DELAY), .PO_COARSE_BYPASS (C_PO_COARSE_BYPASS), .PO_COARSE_DELAY (C_PO_COARSE_DELAY), .PO_OCLK_DELAY (C_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (C_OS_DATA_RATE), .OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_C( .mem_dq_out (mem_dq_out[35:24]), .mem_dq_ts (mem_dq_ts[35:24]), .mem_dq_in (mem_dq_in[29:20]), .mem_dqs_out (mem_dqs_out[2]), .mem_dqs_ts (mem_dqs_ts[2]), .mem_dqs_in (mem_dqs_in[2]), .rst (C_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (C_ddr_clk), .rclk (C_rclk), .pi_dqs_found (C_pi_dqs_found), .dqs_out_of_range (C_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (C_if_a_empty), .if_empty (C_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*C_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*C_of_empty*/), .of_a_full (C_of_a_full), .of_full (C_of_full), .pre_fifo_a_full (C_pre_fifo_a_full), .phy_din (phy_din_remap[239:160]), .phy_dout (phy_dout_remap[239:160]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (C_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (C_idelay_ce), .idelay_ld (C_idelay_ld), .pi_rst_dqs_find (C_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (C_po_fine_enable), .po_coarse_enable (C_po_coarse_enable), .po_fine_inc (C_po_fine_inc), .po_coarse_inc (C_po_coarse_inc), .po_counter_load_en (C_po_counter_load_en), .po_counter_read_en (C_po_counter_read_en), .po_counter_load_val (C_po_counter_load_val), .po_coarse_overflow (C_po_coarse_overflow), .po_fine_overflow (C_po_fine_overflow), .po_counter_read_val (C_po_counter_read_val), .po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (C_pi_fine_enable), .pi_fine_inc (C_pi_fine_inc), .pi_counter_load_en (C_pi_counter_load_en), .pi_counter_read_en (C_pi_counter_read_en), .pi_counter_load_val (C_pi_counter_load_val), .pi_fine_overflow (C_pi_fine_overflow), .pi_counter_read_val (C_pi_counter_read_val), .pi_iserdes_rst (C_pi_iserdes_rst), .pi_phase_locked (C_pi_phase_locked), .fine_delay (C_fine_delay), .fine_delay_sel (C_fine_delay_sel) ); end else begin : no_ddr_byte_lane_C assign C_of_a_full = 1'b0; assign C_of_full = 1'b0; assign C_pre_fifo_a_full = 1'b0; assign C_if_empty = 1'b0; assign C_byte_rd_en = 1'b1; assign C_if_a_empty = 1'b0; assign C_pi_phase_locked = 1; assign C_pi_dqs_found = 1; assign C_rclk = 0; assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign C_pi_counter_read_val = 0; assign C_po_counter_read_val = 0; assign C_pi_fine_overflow = 0; assign C_po_coarse_overflow = 0; assign C_po_fine_overflow = 0; end if ( BYTE_LANES[3] ) begin : ddr_byte_lane_D assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("D"), .PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[47:36]), .BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (D_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (D_PI_BURST_MODE), .PI_CLKOUT_DIV (D_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV), .PI_FINE_DELAY (D_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (D_PO_CLKOUT_DIV), .PO_FINE_DELAY (D_PO_FINE_DELAY), .PO_COARSE_BYPASS (D_PO_COARSE_BYPASS), .PO_COARSE_DELAY (D_PO_COARSE_DELAY), .PO_OCLK_DELAY (D_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (D_OS_DATA_RATE), .OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_D( .mem_dq_out (mem_dq_out[47:36]), .mem_dq_ts (mem_dq_ts[47:36]), .mem_dq_in (mem_dq_in[39:30]), .mem_dqs_out (mem_dqs_out[3]), .mem_dqs_ts (mem_dqs_ts[3]), .mem_dqs_in (mem_dqs_in[3]), .rst (D_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (D_ddr_clk), .rclk (D_rclk), .pi_dqs_found (D_pi_dqs_found), .dqs_out_of_range (D_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (D_if_a_empty), .if_empty (D_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*D_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*D_of_empty*/), .of_a_full (D_of_a_full), .of_full (D_of_full), .pre_fifo_a_full (D_pre_fifo_a_full), .phy_din (phy_din_remap[319:240]), .phy_dout (phy_dout_remap[319:240]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .idelay_inc (idelay_inc), .idelay_ce (D_idelay_ce), .idelay_ld (D_idelay_ld), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (D_byte_rd_en), // calibration signals .pi_rst_dqs_find (D_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (D_po_fine_enable), .po_coarse_enable (D_po_coarse_enable), .po_fine_inc (D_po_fine_inc), .po_coarse_inc (D_po_coarse_inc), .po_counter_load_en (D_po_counter_load_en), .po_counter_read_en (D_po_counter_read_en), .po_counter_load_val (D_po_counter_load_val), .po_coarse_overflow (D_po_coarse_overflow), .po_fine_overflow (D_po_fine_overflow), .po_counter_read_val (D_po_counter_read_val), .po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (D_pi_fine_enable), .pi_fine_inc (D_pi_fine_inc), .pi_counter_load_en (D_pi_counter_load_en), .pi_counter_read_en (D_pi_counter_read_en), .pi_counter_load_val (D_pi_counter_load_val), .pi_fine_overflow (D_pi_fine_overflow), .pi_counter_read_val (D_pi_counter_read_val), .pi_iserdes_rst (D_pi_iserdes_rst), .pi_phase_locked (D_pi_phase_locked), .fine_delay (D_fine_delay), .fine_delay_sel (D_fine_delay_sel) ); end else begin : no_ddr_byte_lane_D assign D_of_a_full = 1'b0; assign D_of_full = 1'b0; assign D_pre_fifo_a_full = 1'b0; assign D_if_empty = 1'b0; assign D_byte_rd_en = 1'b1; assign D_if_a_empty = 1'b0; assign D_rclk = 0; assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign D_pi_dqs_found = 1; assign D_pi_phase_locked = 1; assign D_pi_counter_read_val = 0; assign D_po_counter_read_val = 0; assign D_pi_fine_overflow = 0; assign D_po_coarse_overflow = 0; assign D_po_fine_overflow = 0; end endgenerate assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank; PHY_CONTROL #( .AO_WRLVL_EN ( PC_AO_WRLVL_EN), .AO_TOGGLE ( PC_AO_TOGGLE), .BURST_MODE ( PC_BURST_MODE), .CO_DURATION ( PC_CO_DURATION ), .CLK_RATIO ( PC_CLK_RATIO), .DATA_CTL_A_N ( PC_DATA_CTL_A), .DATA_CTL_B_N ( PC_DATA_CTL_B), .DATA_CTL_C_N ( PC_DATA_CTL_C), .DATA_CTL_D_N ( PC_DATA_CTL_D), .DI_DURATION ( PC_DI_DURATION ), .DO_DURATION ( PC_DO_DURATION ), .EVENTS_DELAY ( PC_EVENTS_DELAY), .FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS), .MULTI_REGION ( PC_MULTI_REGION ), .PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN), .DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH), .SYNC_MODE ( PC_SYNC_MODE), .CMD_OFFSET ( PC_CMD_OFFSET), .RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0), .RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1), .RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2), .RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3), .RD_DURATION_0 ( PC_RD_DURATION_0), .RD_DURATION_1 ( PC_RD_DURATION_1), .RD_DURATION_2 ( PC_RD_DURATION_2), .RD_DURATION_3 ( PC_RD_DURATION_3), .WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0), .WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1), .WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2), .WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3), .WR_DURATION_0 ( PC_WR_DURATION_0), .WR_DURATION_1 ( PC_WR_DURATION_1), .WR_DURATION_2 ( PC_WR_DURATION_2), .WR_DURATION_3 ( PC_WR_DURATION_3) ) phy_control_i ( .AUXOUTPUT (aux_out), .INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]), .INRANKA (in_rank[1:0]), .INRANKB (in_rank[3:2]), .INRANKC (in_rank[5:4]), .INRANKD (in_rank[7:6]), .OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]), .PCENABLECALIB (phy_encalib), .PHYCTLALMOSTFULL (phy_ctl_a_full), .PHYCTLEMPTY (phy_ctl_empty), .PHYCTLFULL (phy_ctl_full), .PHYCTLREADY (phy_ctl_ready), .MEMREFCLK (mem_refclk), .PHYCLK (phy_ctl_clk), .PHYCTLMSTREMPTY (phy_ctl_mstr_empty), .PHYCTLWD (_phy_ctl_wd), .PHYCTLWRENABLE (phy_ctl_wr), .PLLLOCK (pll_lock), .REFDLLLOCK (ref_dll_lock), // is reset while !locked .RESET (rst), .SYNCIN (sync_pulse), .READCALIBENABLE (phy_read_calib), .WRITECALIBENABLE (phy_write_calib) `ifdef USE_PHY_CONTROL_TEST , .TESTINPUT (16'b0), .TESTOUTPUT (test_output), .TESTSELECT (test_select), .SCANENABLEN (scan_enable) `endif ); // register outputs to give extra slack in timing always @(posedge phy_clk ) begin case (calib_sel[1:0]) 2'h0: begin po_coarse_overflow <= #1 A_po_coarse_overflow; po_fine_overflow <= #1 A_po_fine_overflow; po_counter_read_val <= #1 A_po_counter_read_val; pi_fine_overflow <= #1 A_pi_fine_overflow; pi_counter_read_val<= #1 A_pi_counter_read_val; pi_phase_locked <= #1 A_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 A_pi_dqs_found; pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range; end 2'h1: begin po_coarse_overflow <= #1 B_po_coarse_overflow; po_fine_overflow <= #1 B_po_fine_overflow; po_counter_read_val <= #1 B_po_counter_read_val; pi_fine_overflow <= #1 B_pi_fine_overflow; pi_counter_read_val <= #1 B_pi_counter_read_val; pi_phase_locked <= #1 B_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 B_pi_dqs_found; pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range; end 2'h2: begin po_coarse_overflow <= #1 C_po_coarse_overflow; po_fine_overflow <= #1 C_po_fine_overflow; po_counter_read_val <= #1 C_po_counter_read_val; pi_fine_overflow <= #1 C_pi_fine_overflow; pi_counter_read_val <= #1 C_pi_counter_read_val; pi_phase_locked <= #1 C_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 C_pi_dqs_found; pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range; end 2'h3: begin po_coarse_overflow <= #1 D_po_coarse_overflow; po_fine_overflow <= #1 D_po_fine_overflow; po_counter_read_val <= #1 D_po_counter_read_val; pi_fine_overflow <= #1 D_pi_fine_overflow; pi_counter_read_val <= #1 D_pi_counter_read_val; pi_phase_locked <= #1 D_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 D_pi_dqs_found; pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range; end default: begin po_coarse_overflow <= po_coarse_overflow; end endcase end wire B_mux_ctrl; wire C_mux_ctrl; wire D_mux_ctrl; generate if (HIGHEST_LANE > 1) assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1])); else assign B_mux_ctrl = 0; if (HIGHEST_LANE > 2) assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2])); else assign C_mux_ctrl = 0; if (HIGHEST_LANE > 3) assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3])); else assign D_mux_ctrl = 0; endgenerate always @(*) begin A_pi_fine_enable = 0; A_pi_fine_inc = 0; A_pi_counter_load_en = 0; A_pi_counter_read_en = 0; A_pi_counter_load_val = 0; A_pi_rst_dqs_find = 0; A_po_fine_enable = 0; A_po_coarse_enable = 0; A_po_fine_inc = 0; A_po_coarse_inc = 0; A_po_counter_load_en = 0; A_po_counter_read_en = 0; A_po_counter_load_val = 0; A_po_sel_fine_oclk_delay = 0; A_idelay_ce = 0; A_idelay_ld = 0; A_fine_delay = 0; A_fine_delay_sel = 0; B_pi_fine_enable = 0; B_pi_fine_inc = 0; B_pi_counter_load_en = 0; B_pi_counter_read_en = 0; B_pi_counter_load_val = 0; B_pi_rst_dqs_find = 0; B_po_fine_enable = 0; B_po_coarse_enable = 0; B_po_fine_inc = 0; B_po_coarse_inc = 0; B_po_counter_load_en = 0; B_po_counter_read_en = 0; B_po_counter_load_val = 0; B_po_sel_fine_oclk_delay = 0; B_idelay_ce = 0; B_idelay_ld = 0; B_fine_delay = 0; B_fine_delay_sel = 0; C_pi_fine_enable = 0; C_pi_fine_inc = 0; C_pi_counter_load_en = 0; C_pi_counter_read_en = 0; C_pi_counter_load_val = 0; C_pi_rst_dqs_find = 0; C_po_fine_enable = 0; C_po_coarse_enable = 0; C_po_fine_inc = 0; C_po_coarse_inc = 0; C_po_counter_load_en = 0; C_po_counter_read_en = 0; C_po_counter_load_val = 0; C_po_sel_fine_oclk_delay = 0; C_idelay_ce = 0; C_idelay_ld = 0; C_fine_delay = 0; C_fine_delay_sel = 0; D_pi_fine_enable = 0; D_pi_fine_inc = 0; D_pi_counter_load_en = 0; D_pi_counter_read_en = 0; D_pi_counter_load_val = 0; D_pi_rst_dqs_find = 0; D_po_fine_enable = 0; D_po_coarse_enable = 0; D_po_fine_inc = 0; D_po_coarse_inc = 0; D_po_counter_load_en = 0; D_po_counter_read_en = 0; D_po_counter_load_val = 0; D_po_sel_fine_oclk_delay = 0; D_idelay_ce = 0; D_idelay_ld = 0; D_fine_delay = 0; D_fine_delay_sel = 0; if ( calib_sel[2]) begin // if this is asserted, all calib signals are deasserted A_pi_fine_enable = 0; A_pi_fine_inc = 0; A_pi_counter_load_en = 0; A_pi_counter_read_en = 0; A_pi_counter_load_val = 0; A_pi_rst_dqs_find = 0; A_po_fine_enable = 0; A_po_coarse_enable = 0; A_po_fine_inc = 0; A_po_coarse_inc = 0; A_po_counter_load_en = 0; A_po_counter_read_en = 0; A_po_counter_load_val = 0; A_po_sel_fine_oclk_delay = 0; A_idelay_ce = 0; A_idelay_ld = 0; A_fine_delay = 0; A_fine_delay_sel = 0; B_pi_fine_enable = 0; B_pi_fine_inc = 0; B_pi_counter_load_en = 0; B_pi_counter_read_en = 0; B_pi_counter_load_val = 0; B_pi_rst_dqs_find = 0; B_po_fine_enable = 0; B_po_coarse_enable = 0; B_po_fine_inc = 0; B_po_coarse_inc = 0; B_po_counter_load_en = 0; B_po_counter_read_en = 0; B_po_counter_load_val = 0; B_po_sel_fine_oclk_delay = 0; B_idelay_ce = 0; B_idelay_ld = 0; B_fine_delay = 0; B_fine_delay_sel = 0; C_pi_fine_enable = 0; C_pi_fine_inc = 0; C_pi_counter_load_en = 0; C_pi_counter_read_en = 0; C_pi_counter_load_val = 0; C_pi_rst_dqs_find = 0; C_po_fine_enable = 0; C_po_coarse_enable = 0; C_po_fine_inc = 0; C_po_coarse_inc = 0; C_po_counter_load_en = 0; C_po_counter_read_en = 0; C_po_counter_load_val = 0; C_po_sel_fine_oclk_delay = 0; C_idelay_ce = 0; C_idelay_ld = 0; C_fine_delay = 0; C_fine_delay_sel = 0; D_pi_fine_enable = 0; D_pi_fine_inc = 0; D_pi_counter_load_en = 0; D_pi_counter_read_en = 0; D_pi_counter_load_val = 0; D_pi_rst_dqs_find = 0; D_po_fine_enable = 0; D_po_coarse_enable = 0; D_po_fine_inc = 0; D_po_coarse_inc = 0; D_po_counter_load_en = 0; D_po_counter_read_en = 0; D_po_counter_load_val = 0; D_po_sel_fine_oclk_delay = 0; D_idelay_ce = 0; D_idelay_ld = 0; D_fine_delay = 0; D_fine_delay_sel = 0; end else if (calib_in_common) begin // if this is asserted, each signal is broadcast to all phasers // in common if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin A_pi_fine_enable = pi_fine_enable; A_pi_fine_inc = pi_fine_inc; A_pi_counter_load_en = pi_counter_load_en; A_pi_counter_read_en = pi_counter_read_en; A_pi_counter_load_val = pi_counter_load_val; A_pi_rst_dqs_find = pi_rst_dqs_find; A_po_fine_enable = po_fine_enable; A_po_coarse_enable = po_coarse_enable; A_po_fine_inc = po_fine_inc; A_po_coarse_inc = po_coarse_inc; A_po_counter_load_en = po_counter_load_en; A_po_counter_read_en = po_counter_read_en; A_po_counter_load_val = po_counter_load_val; A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; A_idelay_ce = idelay_ce; A_idelay_ld = idelay_ld; A_fine_delay = fine_delay ; A_fine_delay_sel = fine_delay_sel; end if ( B_mux_ctrl) begin B_pi_fine_enable = pi_fine_enable; B_pi_fine_inc = pi_fine_inc; B_pi_counter_load_en = pi_counter_load_en; B_pi_counter_read_en = pi_counter_read_en; B_pi_counter_load_val = pi_counter_load_val; B_pi_rst_dqs_find = pi_rst_dqs_find; B_po_fine_enable = po_fine_enable; B_po_coarse_enable = po_coarse_enable; B_po_fine_inc = po_fine_inc; B_po_coarse_inc = po_coarse_inc; B_po_counter_load_en = po_counter_load_en; B_po_counter_read_en = po_counter_read_en; B_po_counter_load_val = po_counter_load_val; B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; B_idelay_ce = idelay_ce; B_idelay_ld = idelay_ld; B_fine_delay = fine_delay ; B_fine_delay_sel = fine_delay_sel; end if ( C_mux_ctrl) begin C_pi_fine_enable = pi_fine_enable; C_pi_fine_inc = pi_fine_inc; C_pi_counter_load_en = pi_counter_load_en; C_pi_counter_read_en = pi_counter_read_en; C_pi_counter_load_val = pi_counter_load_val; C_pi_rst_dqs_find = pi_rst_dqs_find; C_po_fine_enable = po_fine_enable; C_po_coarse_enable = po_coarse_enable; C_po_fine_inc = po_fine_inc; C_po_coarse_inc = po_coarse_inc; C_po_counter_load_en = po_counter_load_en; C_po_counter_read_en = po_counter_read_en; C_po_counter_load_val = po_counter_load_val; C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; C_idelay_ce = idelay_ce; C_idelay_ld = idelay_ld; C_fine_delay = fine_delay ; C_fine_delay_sel = fine_delay_sel; end if ( D_mux_ctrl) begin D_pi_fine_enable = pi_fine_enable; D_pi_fine_inc = pi_fine_inc; D_pi_counter_load_en = pi_counter_load_en; D_pi_counter_read_en = pi_counter_read_en; D_pi_counter_load_val = pi_counter_load_val; D_pi_rst_dqs_find = pi_rst_dqs_find; D_po_fine_enable = po_fine_enable; D_po_coarse_enable = po_coarse_enable; D_po_fine_inc = po_fine_inc; D_po_coarse_inc = po_coarse_inc; D_po_counter_load_en = po_counter_load_en; D_po_counter_read_en = po_counter_read_en; D_po_counter_load_val = po_counter_load_val; D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; D_idelay_ce = idelay_ce; D_idelay_ld = idelay_ld; D_fine_delay = fine_delay ; D_fine_delay_sel = fine_delay_sel; end end else begin // otherwise, only a single phaser is selected case (calib_sel[1:0]) 0: begin A_pi_fine_enable = pi_fine_enable; A_pi_fine_inc = pi_fine_inc; A_pi_counter_load_en = pi_counter_load_en; A_pi_counter_read_en = pi_counter_read_en; A_pi_counter_load_val = pi_counter_load_val; A_pi_rst_dqs_find = pi_rst_dqs_find; A_po_fine_enable = po_fine_enable; A_po_coarse_enable = po_coarse_enable; A_po_fine_inc = po_fine_inc; A_po_coarse_inc = po_coarse_inc; A_po_counter_load_en = po_counter_load_en; A_po_counter_read_en = po_counter_read_en; A_po_counter_load_val = po_counter_load_val; A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; A_idelay_ce = idelay_ce; A_idelay_ld = idelay_ld; A_fine_delay = fine_delay ; A_fine_delay_sel = fine_delay_sel; end 1: begin B_pi_fine_enable = pi_fine_enable; B_pi_fine_inc = pi_fine_inc; B_pi_counter_load_en = pi_counter_load_en; B_pi_counter_read_en = pi_counter_read_en; B_pi_counter_load_val = pi_counter_load_val; B_pi_rst_dqs_find = pi_rst_dqs_find; B_po_fine_enable = po_fine_enable; B_po_coarse_enable = po_coarse_enable; B_po_fine_inc = po_fine_inc; B_po_coarse_inc = po_coarse_inc; B_po_counter_load_en = po_counter_load_en; B_po_counter_read_en = po_counter_read_en; B_po_counter_load_val = po_counter_load_val; B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; B_idelay_ce = idelay_ce; B_idelay_ld = idelay_ld; B_fine_delay = fine_delay ; B_fine_delay_sel = fine_delay_sel; end 2: begin C_pi_fine_enable = pi_fine_enable; C_pi_fine_inc = pi_fine_inc; C_pi_counter_load_en = pi_counter_load_en; C_pi_counter_read_en = pi_counter_read_en; C_pi_counter_load_val = pi_counter_load_val; C_pi_rst_dqs_find = pi_rst_dqs_find; C_po_fine_enable = po_fine_enable; C_po_coarse_enable = po_coarse_enable; C_po_fine_inc = po_fine_inc; C_po_coarse_inc = po_coarse_inc; C_po_counter_load_en = po_counter_load_en; C_po_counter_read_en = po_counter_read_en; C_po_counter_load_val = po_counter_load_val; C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; C_idelay_ce = idelay_ce; C_idelay_ld = idelay_ld; C_fine_delay = fine_delay ; C_fine_delay_sel = fine_delay_sel; end 3: begin D_pi_fine_enable = pi_fine_enable; D_pi_fine_inc = pi_fine_inc; D_pi_counter_load_en = pi_counter_load_en; D_pi_counter_read_en = pi_counter_read_en; D_pi_counter_load_val = pi_counter_load_val; D_pi_rst_dqs_find = pi_rst_dqs_find; D_po_fine_enable = po_fine_enable; D_po_coarse_enable = po_coarse_enable; D_po_fine_inc = po_fine_inc; D_po_coarse_inc = po_coarse_inc; D_po_counter_load_en = po_counter_load_en; D_po_counter_load_val = po_counter_load_val; D_po_counter_read_en = po_counter_read_en; D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; D_idelay_ce = idelay_ce; D_idelay_ld = idelay_ld; D_fine_delay = fine_delay ; D_fine_delay_sel = fine_delay_sel; end endcase end end //obligatory phaser-ref PHASER_REF phaser_ref_i( .LOCKED (ref_dll_lock), .CLKIN (freq_refclk), .PWRDWN (1'b0), .RST ( ! pll_lock) ); // optional idelay_ctrl generate if ( GENERATE_IDELAYCTRL == "TRUE") IDELAYCTRL idelayctrl ( .RDY (/*idelayctrl_rdy*/), .REFCLK (idelayctrl_refclk), .RST (rst) ); endgenerate endmodule
/********************************************************** -- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). A Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. // // THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. // // // Owner: Gary Martin // Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $ // $Author: gary $ // $DateTime: 2010/05/11 18:05:17 $ // $Change: 490882 $ // Description: // This verilog file is the parameterizable 4-byte lane phy primitive top // This module may be ganged to create an N-lane phy. // // History: // Date Engineer Description // 04/01/2010 G. Martin Initial Checkin. // /////////////////////////////////////////////////////////// **********************************************************/ `timescale 1ps/1ps `define PC_DATA_OFFSET_RANGE 22:17 module mig_7series_v2_3_ddr_phy_4lanes #( parameter GENERATE_IDELAYCTRL = "TRUE", parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010, parameter NUM_DDR_CK = 1, // next three parameter fields correspond to byte lanes for lane order DCBA parameter BYTE_LANES = 4'b1111, // lane existence, one per lane parameter DATA_CTL_N = 4'b1111, // data or control, per lane parameter BITLANES = 48'hffff_ffff_ffff, parameter BITLANES_OUTONLY = 48'h0000_0000_0000, parameter LANE_REMAP = 16'h3210,// 4-bit index // used to rewire to one of four // input/output buss lanes // example: 0321 remaps lanes as: // D->A // C->D // B->C // A->B parameter LAST_BANK = "FALSE", parameter USE_PRE_POST_FIFO = "FALSE", parameter RCLK_SELECT_LANE = "B", parameter real TCK = 0.00, parameter SYNTHESIS = "FALSE", parameter PO_CTL_COARSE_BYPASS = "FALSE", parameter PO_FINE_DELAY = 0, parameter PI_SEL_CLK_OFFSET = 0, // phy_control paramter used in other paramsters parameter PC_CLK_RATIO = 4, //phaser_in parameters parameter A_PI_FREQ_REF_DIV = "NONE", parameter A_PI_CLKOUT_DIV = 2, parameter A_PI_BURST_MODE = "TRUE", parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF", parameter A_PI_FINE_DELAY = 60, parameter A_PI_SYNC_IN_DIV_RST = "TRUE", parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter B_PI_BURST_MODE = A_PI_BURST_MODE, parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY, parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter C_PI_BURST_MODE = A_PI_BURST_MODE, parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter C_PI_FINE_DELAY = 0, parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter D_PI_BURST_MODE = A_PI_BURST_MODE, parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter D_PI_FINE_DELAY = 0, parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, //phaser_out parameters parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2, parameter A_PO_FINE_DELAY = PO_FINE_DELAY, parameter A_PO_COARSE_DELAY = 0, parameter A_PO_OCLK_DELAY = 0, parameter A_PO_OCLKDELAY_INV = "FALSE", parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF", parameter A_PO_SYNC_IN_DIV_RST = "TRUE", //parameter A_PO_SYNC_IN_DIV_RST = "FALSE", parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2, parameter B_PO_FINE_DELAY = PO_FINE_DELAY, parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2, parameter C_PO_FINE_DELAY = PO_FINE_DELAY, parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2, parameter D_PO_FINE_DELAY = PO_FINE_DELAY, parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE", parameter A_IDELAYE2_IDELAY_VALUE = 00, parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, // phy_control parameters parameter PC_BURST_MODE = "TRUE", parameter PC_DATA_CTL_N = DATA_CTL_N, parameter PC_CMD_OFFSET = 0, parameter PC_RD_CMD_OFFSET_0 = 0, parameter PC_RD_CMD_OFFSET_1 = 0, parameter PC_RD_CMD_OFFSET_2 = 0, parameter PC_RD_CMD_OFFSET_3 = 0, parameter PC_CO_DURATION = 1, parameter PC_DI_DURATION = 1, parameter PC_DO_DURATION = 1, parameter PC_RD_DURATION_0 = 0, parameter PC_RD_DURATION_1 = 0, parameter PC_RD_DURATION_2 = 0, parameter PC_RD_DURATION_3 = 0, parameter PC_WR_CMD_OFFSET_0 = 5, parameter PC_WR_CMD_OFFSET_1 = 5, parameter PC_WR_CMD_OFFSET_2 = 5, parameter PC_WR_CMD_OFFSET_3 = 5, parameter PC_WR_DURATION_0 = 6, parameter PC_WR_DURATION_1 = 6, parameter PC_WR_DURATION_2 = 6, parameter PC_WR_DURATION_3 = 6, parameter PC_AO_WRLVL_EN = 0, parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE) parameter PC_FOUR_WINDOW_CLOCKS = 63, parameter PC_EVENTS_DELAY = 18, parameter PC_PHY_COUNT_EN = "TRUE", parameter PC_SYNC_MODE = "TRUE", parameter PC_DISABLE_SEQ_MATCH = "TRUE", parameter PC_MULTI_REGION = "FALSE", // io fifo parameters parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter OF_ALMOST_EMPTY_VALUE = 1, parameter OF_ALMOST_FULL_VALUE = 1, parameter OF_OUTPUT_DISABLE = "TRUE", parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE, parameter A_OS_DATA_RATE = "DDR", parameter A_OS_DATA_WIDTH = 4, parameter B_OS_DATA_RATE = A_OS_DATA_RATE, parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter C_OS_DATA_RATE = A_OS_DATA_RATE, parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter D_OS_DATA_RATE = A_OS_DATA_RATE, parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8", parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter IF_ALMOST_EMPTY_VALUE = 1, parameter IF_ALMOST_FULL_VALUE = 1, parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE, // this is used locally, not for external pushdown // NOTE: the 0+ is needed in each to coerce to integer for addition. // otherwise 4x 1'b values are added producing a 1'b value. parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1), parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])), parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]), parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES, // assume odt per rank + any declared cke's parameter AUXOUT_WIDTH = 4, parameter LP_DDR_CK_WIDTH = 2 ,parameter CKE_ODT_AUX = "FALSE" ) ( //`include "phy.vh" input rst, input phy_clk, input phy_ctl_clk, input freq_refclk, input mem_refclk, input mem_refclk_div4, input pll_lock, input sync_pulse, input idelayctrl_refclk, input [HIGHEST_LANE*80-1:0] phy_dout, input phy_cmd_wr_en, input phy_data_wr_en, input phy_rd_en, input phy_ctl_mstr_empty, input [31:0] phy_ctl_wd, input [`PC_DATA_OFFSET_RANGE] data_offset, input phy_ctl_wr, input if_empty_def, input phyGo, input input_sink, output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory output rclk, output if_a_empty, output if_empty, output byte_rd_en, output if_empty_or, output if_empty_and, output of_ctl_a_full, output of_data_a_full, output of_ctl_full, output of_data_full, output pre_data_a_full, output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus output phy_ctl_empty, output phy_ctl_a_full, output phy_ctl_full, output [HIGHEST_LANE*12-1:0]mem_dq_out, output [HIGHEST_LANE*12-1:0]mem_dq_ts, input [HIGHEST_LANE*10-1:0]mem_dq_in, output [HIGHEST_LANE-1:0] mem_dqs_out, output [HIGHEST_LANE-1:0] mem_dqs_ts, input [HIGHEST_LANE-1:0] mem_dqs_in, input [1:0] byte_rd_en_oth_banks, output [AUXOUT_WIDTH-1:0] aux_out, output reg rst_out = 0, output reg mcGo=0, output phy_ctl_ready, output ref_dll_lock, input if_rst, input phy_read_calib, input phy_write_calib, input idelay_inc, input idelay_ce, input idelay_ld, input [2:0] calib_sel, input calib_zero_ctrl, input [HIGHEST_LANE-1:0] calib_zero_lanes, input calib_in_common, input po_fine_enable, input po_coarse_enable, input po_fine_inc, input po_coarse_inc, input po_counter_load_en, input po_counter_read_en, input [8:0] po_counter_load_val, input po_sel_fine_oclk_delay, output reg po_coarse_overflow, output reg po_fine_overflow, output reg [8:0] po_counter_read_val, input pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input pi_counter_read_en, input [5:0] pi_counter_load_val, output reg pi_fine_overflow, output reg [5:0] pi_counter_read_val, output reg pi_dqs_found, output pi_dqs_found_all, output pi_dqs_found_any, output [HIGHEST_LANE-1:0] pi_phase_locked_lanes, output [HIGHEST_LANE-1:0] pi_dqs_found_lanes, output reg pi_dqs_out_of_range, output reg pi_phase_locked, output pi_phase_locked_all, input [29:0] fine_delay, input fine_delay_sel ); localparam DATA_CTL_A = (~DATA_CTL_N[0]); localparam DATA_CTL_B = (~DATA_CTL_N[1]); localparam DATA_CTL_C = (~DATA_CTL_N[2]); localparam DATA_CTL_D = (~DATA_CTL_N[3]); localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0]; localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1]; localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2]; localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3]; localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0]; localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1]; localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2]; localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3]; localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE"; localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam IO_A_START = 41; localparam IO_A_END = 40; localparam IO_B_START = 43; localparam IO_B_END = 42; localparam IO_C_START = 45; localparam IO_C_END = 44; localparam IO_D_START = 47; localparam IO_D_END = 46; localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1; localparam IO_A_X_END = (IO_A_X_START-1); localparam IO_B_X_START = (IO_A_X_START + 2); localparam IO_B_X_END = (IO_B_X_START -1); localparam IO_C_X_START = (IO_B_X_START + 2); localparam IO_C_X_END = (IO_C_X_START -1); localparam IO_D_X_START = (IO_C_X_START + 2); localparam IO_D_X_END = (IO_D_X_START -1); localparam MSB_BURST_PEND_PO = 3; localparam MSB_BURST_PEND_PI = 7; localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8; localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1; wire [1:0] oserdes_dqs; wire [1:0] oserdes_dqs_ts; wire [1:0] oserdes_dq_ts; wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus; wire [7:0] in_rank; wire [11:0] IO_A; wire [11:0] IO_B; wire [11:0] IO_C; wire [11:0] IO_D; wire [319:0] phy_din_remap; reg A_po_counter_read_en; wire [8:0] A_po_counter_read_val; reg A_pi_counter_read_en; wire [5:0] A_pi_counter_read_val; wire A_pi_fine_overflow; wire A_po_coarse_overflow; wire A_po_fine_overflow; wire A_pi_dqs_found; wire A_pi_dqs_out_of_range; wire A_pi_phase_locked; wire A_pi_iserdes_rst; reg A_pi_fine_enable; reg A_pi_fine_inc; reg A_pi_counter_load_en; reg [5:0] A_pi_counter_load_val; reg A_pi_rst_dqs_find; reg A_po_fine_enable; reg A_po_coarse_enable; reg A_po_fine_inc /* synthesis syn_maxfan = 3 */; reg A_po_sel_fine_oclk_delay; reg A_po_coarse_inc; reg A_po_counter_load_en; reg [8:0] A_po_counter_load_val; wire A_rclk; reg A_idelay_ce; reg A_idelay_ld; reg [29:0] A_fine_delay; reg A_fine_delay_sel; reg B_po_counter_read_en; wire [8:0] B_po_counter_read_val; reg B_pi_counter_read_en; wire [5:0] B_pi_counter_read_val; wire B_pi_fine_overflow; wire B_po_coarse_overflow; wire B_po_fine_overflow; wire B_pi_phase_locked; wire B_pi_iserdes_rst; wire B_pi_dqs_found; wire B_pi_dqs_out_of_range; reg B_pi_fine_enable; reg B_pi_fine_inc; reg B_pi_counter_load_en; reg [5:0] B_pi_counter_load_val; reg B_pi_rst_dqs_find; reg B_po_fine_enable; reg B_po_coarse_enable; reg B_po_fine_inc /* synthesis syn_maxfan = 3 */; reg B_po_coarse_inc; reg B_po_sel_fine_oclk_delay; reg B_po_counter_load_en; reg [8:0] B_po_counter_load_val; wire B_rclk; reg B_idelay_ce; reg B_idelay_ld; reg [29:0] B_fine_delay; reg B_fine_delay_sel; reg C_pi_fine_inc; reg D_pi_fine_inc; reg C_pi_fine_enable; reg D_pi_fine_enable; reg C_po_counter_load_en; reg D_po_counter_load_en; reg C_po_coarse_inc; reg D_po_coarse_inc; reg C_po_fine_inc /* synthesis syn_maxfan = 3 */; reg D_po_fine_inc /* synthesis syn_maxfan = 3 */; reg C_po_sel_fine_oclk_delay; reg D_po_sel_fine_oclk_delay; reg [5:0] C_pi_counter_load_val; reg [5:0] D_pi_counter_load_val; reg [8:0] C_po_counter_load_val; reg [8:0] D_po_counter_load_val; reg C_po_coarse_enable; reg D_po_coarse_enable; reg C_po_fine_enable; reg D_po_fine_enable; wire C_po_coarse_overflow; wire D_po_coarse_overflow; wire C_po_fine_overflow; wire D_po_fine_overflow; wire [8:0] C_po_counter_read_val; wire [8:0] D_po_counter_read_val; reg C_po_counter_read_en; reg D_po_counter_read_en; wire C_pi_dqs_found; wire D_pi_dqs_found; wire C_pi_fine_overflow; wire D_pi_fine_overflow; reg C_pi_counter_read_en; reg D_pi_counter_read_en; reg C_pi_counter_load_en; reg D_pi_counter_load_en; wire C_pi_phase_locked; wire C_pi_iserdes_rst; wire D_pi_phase_locked; wire D_pi_iserdes_rst; wire C_pi_dqs_out_of_range; wire D_pi_dqs_out_of_range; wire [5:0] C_pi_counter_read_val; wire [5:0] D_pi_counter_read_val; wire C_rclk; wire D_rclk; reg C_idelay_ce; reg D_idelay_ce; reg C_idelay_ld; reg D_idelay_ld; reg C_pi_rst_dqs_find; reg D_pi_rst_dqs_find; reg [29:0] C_fine_delay; reg [29:0] D_fine_delay; reg C_fine_delay_sel; reg D_fine_delay_sel; wire pi_iserdes_rst; wire A_if_empty; wire B_if_empty; wire C_if_empty; wire D_if_empty; wire A_byte_rd_en; wire B_byte_rd_en; wire C_byte_rd_en; wire D_byte_rd_en; wire A_if_a_empty; wire B_if_a_empty; wire C_if_a_empty; wire D_if_a_empty; //wire A_if_full; //wire B_if_full; //wire C_if_full; //wire D_if_full; //wire A_of_empty; //wire B_of_empty; //wire C_of_empty; //wire D_of_empty; wire A_of_full; wire B_of_full; wire C_of_full; wire D_of_full; wire A_of_ctl_full; wire B_of_ctl_full; wire C_of_ctl_full; wire D_of_ctl_full; wire A_of_data_full; wire B_of_data_full; wire C_of_data_full; wire D_of_data_full; wire A_of_a_full; wire B_of_a_full; wire C_of_a_full; wire D_of_a_full; wire A_pre_fifo_a_full; wire B_pre_fifo_a_full; wire C_pre_fifo_a_full; wire D_pre_fifo_a_full; wire A_of_ctl_a_full; wire B_of_ctl_a_full; wire C_of_ctl_a_full; wire D_of_ctl_a_full; wire A_of_data_a_full; wire B_of_data_a_full; wire C_of_data_a_full; wire D_of_data_a_full; wire A_pre_data_a_full; wire B_pre_data_a_full; wire C_pre_data_a_full; wire D_pre_data_a_full; wire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation wire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; // wire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; // wire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; // wire [3:0] dummy_data; wire [31:0] _phy_ctl_wd; wire [1:0] phy_encalib; assign pi_dqs_found_all = (! PRESENT_DATA_A | A_pi_dqs_found) & (! PRESENT_DATA_B | B_pi_dqs_found) & (! PRESENT_DATA_C | C_pi_dqs_found) & (! PRESENT_DATA_D | D_pi_dqs_found) ; assign pi_dqs_found_any = ( PRESENT_DATA_A & A_pi_dqs_found) | ( PRESENT_DATA_B & B_pi_dqs_found) | ( PRESENT_DATA_C & C_pi_dqs_found) | ( PRESENT_DATA_D & D_pi_dqs_found) ; assign pi_phase_locked_all = (! PRESENT_DATA_A | A_pi_phase_locked) & (! PRESENT_DATA_B | B_pi_phase_locked) & (! PRESENT_DATA_C | C_pi_phase_locked) & (! PRESENT_DATA_D | D_pi_phase_locked); wire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal // which is combined into another signals such that // the other signal isn't changed. The purpose // is to fake the tools into ignoring dangling inputs. // Because it is anded with 1'b0, the contributing signals // are folded as constants or trimmed. assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty); assign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) : (A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en); assign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty); assign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty); assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty; //assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ; //assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty; assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ; assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ; assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ; assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ; assign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full; function [79:0] part_select_80; input [319:0] vector; input [1:0] select; begin case (select) 2'b00 : part_select_80[79:0] = vector[1*80-1:0*80]; 2'b01 : part_select_80[79:0] = vector[2*80-1:1*80]; 2'b10 : part_select_80[79:0] = vector[3*80-1:2*80]; 2'b11 : part_select_80[79:0] = vector[4*80-1:3*80]; endcase end endfunction wire [319:0] phy_dout_remap; reg rst_out_trig = 1'b0; reg [31:0] rclk_delay; reg rst_edge1 = 1'b0; reg rst_edge2 = 1'b0; reg rst_edge3 = 1'b0; reg rst_edge_detect = 1'b0; wire rclk_; reg rst_out_start = 1'b0 ; reg rst_primitives=0; reg A_rst_primitives=0; reg B_rst_primitives=0; reg C_rst_primitives=0; reg D_rst_primitives=0; `ifdef USE_PHY_CONTROL_TEST wire [15:0] test_output; wire [15:0] test_input; wire [2:0] test_select=0; wire scan_enable = 0; `endif generate genvar i; if (RCLK_SELECT_LANE == "A") begin assign rclk_ = A_rclk; assign pi_iserdes_rst = A_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "B") begin assign rclk_ = B_rclk; assign pi_iserdes_rst = B_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "C") begin assign rclk_ = C_rclk; assign pi_iserdes_rst = C_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "D") begin assign rclk_ = D_rclk; assign pi_iserdes_rst = D_pi_iserdes_rst; end else begin assign rclk_ = B_rclk; // default end endgenerate assign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk; assign pi_phase_locked_lanes = {(! PRESENT_DATA_A[0] | A_pi_phase_locked), (! PRESENT_DATA_B[0] | B_pi_phase_locked) , (! PRESENT_DATA_C[0] | C_pi_phase_locked) , (! PRESENT_DATA_D[0] | D_pi_phase_locked)}; assign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found}; // this block scrubs X from rclk_delay[11] reg rclk_delay_11; always @(rclk_delay[11]) begin : rclk_delay_11_blk if ( rclk_delay[11]) rclk_delay_11 = 1; else rclk_delay_11 = 0; end always @(posedge phy_clk or posedge rst ) begin // scrub 4-state values from rclk_delay[11] if ( rst) begin rst_out <= #1 0; end else begin if ( rclk_delay_11) rst_out <= #1 1; end end always @(posedge phy_clk ) begin // phy_ctl_ready drives reset of the system rst_primitives <= !phy_ctl_ready ; A_rst_primitives <= rst_primitives ; B_rst_primitives <= rst_primitives ; C_rst_primitives <= rst_primitives ; D_rst_primitives <= rst_primitives ; rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo); mcGo <= #1 rst_out ; end generate if (BYTE_LANES[0]) begin assign dummy_data[0] = 0; end else begin assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80]; end if (BYTE_LANES[1]) begin assign dummy_data[1] = 0; end else begin assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80]; end if (BYTE_LANES[2]) begin assign dummy_data[2] = 0; end else begin assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80]; end if (BYTE_LANES[3]) begin assign dummy_data[3] = 0; end else begin assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80]; end if (PRESENT_DATA_A) begin assign A_of_data_full = A_of_full; assign A_of_ctl_full = 0; assign A_of_data_a_full = A_of_a_full; assign A_of_ctl_a_full = 0; assign A_pre_data_a_full = A_pre_fifo_a_full; end else begin assign A_of_ctl_full = A_of_full; assign A_of_data_full = 0; assign A_of_ctl_a_full = A_of_a_full; assign A_of_data_a_full = 0; assign A_pre_data_a_full = 0; end if (PRESENT_DATA_B) begin assign B_of_data_full = B_of_full; assign B_of_ctl_full = 0; assign B_of_data_a_full = B_of_a_full; assign B_of_ctl_a_full = 0; assign B_pre_data_a_full = B_pre_fifo_a_full; end else begin assign B_of_ctl_full = B_of_full; assign B_of_data_full = 0; assign B_of_ctl_a_full = B_of_a_full; assign B_of_data_a_full = 0; assign B_pre_data_a_full = 0; end if (PRESENT_DATA_C) begin assign C_of_data_full = C_of_full; assign C_of_ctl_full = 0; assign C_of_data_a_full = C_of_a_full; assign C_of_ctl_a_full = 0; assign C_pre_data_a_full = C_pre_fifo_a_full; end else begin assign C_of_ctl_full = C_of_full; assign C_of_data_full = 0; assign C_of_ctl_a_full = C_of_a_full; assign C_of_data_a_full = 0; assign C_pre_data_a_full = 0; end if (PRESENT_DATA_D) begin assign D_of_data_full = D_of_full; assign D_of_ctl_full = 0; assign D_of_data_a_full = D_of_a_full; assign D_of_ctl_a_full = 0; assign D_pre_data_a_full = D_pre_fifo_a_full; end else begin assign D_of_ctl_full = D_of_full; assign D_of_data_full = 0; assign D_of_ctl_a_full = D_of_a_full; assign D_of_data_a_full = 0; assign D_pre_data_a_full = 0; end // byte lane must exist and be data lane. if (PRESENT_DATA_A ) case ( LANE_REMAP[1:0] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0]; endcase else case ( LANE_REMAP[1:0] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_B ) case ( LANE_REMAP[5:4] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80]; endcase else if (HIGHEST_LANE > 1) case ( LANE_REMAP[5:4] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_C) case ( LANE_REMAP[9:8] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160]; endcase else if (HIGHEST_LANE > 2) case ( LANE_REMAP[9:8] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_D ) case ( LANE_REMAP[13:12] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240]; endcase else if (HIGHEST_LANE > 3) case ( LANE_REMAP[13:12] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (HIGHEST_LANE > 1) assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]}; if (HIGHEST_LANE == 1) assign _phy_ctl_wd = phy_ctl_wd; //BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst)); BUFIO rclk_buf(.I(rclk_), .O(rclk) ); if ( BYTE_LANES[0] ) begin : ddr_byte_lane_A assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("A"), .PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[11:0]), .BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (A_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (A_PI_BURST_MODE), .PI_CLKOUT_DIV (A_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV), .PI_FINE_DELAY (A_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (A_PO_CLKOUT_DIV), .PO_FINE_DELAY (A_PO_FINE_DELAY), .PO_COARSE_BYPASS (A_PO_COARSE_BYPASS), .PO_COARSE_DELAY (A_PO_COARSE_DELAY), .PO_OCLK_DELAY (A_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (A_OS_DATA_RATE), .OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_A( .mem_dq_out (mem_dq_out[11:0]), .mem_dq_ts (mem_dq_ts[11:0]), .mem_dq_in (mem_dq_in[9:0]), .mem_dqs_out (mem_dqs_out[0]), .mem_dqs_ts (mem_dqs_ts[0]), .mem_dqs_in (mem_dqs_in[0]), .rst (A_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (A_ddr_clk), .rclk (A_rclk), .pi_dqs_found (A_pi_dqs_found), .dqs_out_of_range (A_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (A_if_a_empty), .if_empty (A_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*A_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*A_of_empty*/), .of_a_full (A_of_a_full), .of_full (A_of_full), .pre_fifo_a_full (A_pre_fifo_a_full), .phy_din (phy_din_remap[79:0]), .phy_dout (phy_dout_remap[79:0]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (A_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (A_idelay_ce), .idelay_ld (A_idelay_ld), .pi_rst_dqs_find (A_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (A_po_fine_enable), .po_coarse_enable (A_po_coarse_enable), .po_fine_inc (A_po_fine_inc), .po_coarse_inc (A_po_coarse_inc), .po_counter_load_en (A_po_counter_load_en), .po_counter_read_en (A_po_counter_read_en), .po_counter_load_val (A_po_counter_load_val), .po_coarse_overflow (A_po_coarse_overflow), .po_fine_overflow (A_po_fine_overflow), .po_counter_read_val (A_po_counter_read_val), .po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (A_pi_fine_enable), .pi_fine_inc (A_pi_fine_inc), .pi_counter_load_en (A_pi_counter_load_en), .pi_counter_read_en (A_pi_counter_read_en), .pi_counter_load_val (A_pi_counter_load_val), .pi_fine_overflow (A_pi_fine_overflow), .pi_counter_read_val (A_pi_counter_read_val), .pi_iserdes_rst (A_pi_iserdes_rst), .pi_phase_locked (A_pi_phase_locked), .fine_delay (A_fine_delay), .fine_delay_sel (A_fine_delay_sel) ); end else begin : no_ddr_byte_lane_A assign A_of_a_full = 1'b0; assign A_of_full = 1'b0; assign A_pre_fifo_a_full = 1'b0; assign A_if_empty = 1'b0; assign A_byte_rd_en = 1'b1; assign A_if_a_empty = 1'b0; assign A_pi_phase_locked = 1; assign A_pi_dqs_found = 1; assign A_rclk = 0; assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign A_pi_counter_read_val = 0; assign A_po_counter_read_val = 0; assign A_pi_fine_overflow = 0; assign A_po_coarse_overflow = 0; assign A_po_fine_overflow = 0; end if ( BYTE_LANES[1] ) begin : ddr_byte_lane_B assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("B"), .PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[23:12]), .BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (B_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (B_PI_BURST_MODE), .PI_CLKOUT_DIV (B_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV), .PI_FINE_DELAY (B_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (B_PO_CLKOUT_DIV), .PO_FINE_DELAY (B_PO_FINE_DELAY), .PO_COARSE_BYPASS (B_PO_COARSE_BYPASS), .PO_COARSE_DELAY (B_PO_COARSE_DELAY), .PO_OCLK_DELAY (B_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (B_OS_DATA_RATE), .OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_B( .mem_dq_out (mem_dq_out[23:12]), .mem_dq_ts (mem_dq_ts[23:12]), .mem_dq_in (mem_dq_in[19:10]), .mem_dqs_out (mem_dqs_out[1]), .mem_dqs_ts (mem_dqs_ts[1]), .mem_dqs_in (mem_dqs_in[1]), .rst (B_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (B_ddr_clk), .rclk (B_rclk), .pi_dqs_found (B_pi_dqs_found), .dqs_out_of_range (B_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (B_if_a_empty), .if_empty (B_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*B_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*B_of_empty*/), .of_a_full (B_of_a_full), .of_full (B_of_full), .pre_fifo_a_full (B_pre_fifo_a_full), .phy_din (phy_din_remap[159:80]), .phy_dout (phy_dout_remap[159:80]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (B_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (B_idelay_ce), .idelay_ld (B_idelay_ld), .pi_rst_dqs_find (B_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (B_po_fine_enable), .po_coarse_enable (B_po_coarse_enable), .po_fine_inc (B_po_fine_inc), .po_coarse_inc (B_po_coarse_inc), .po_counter_load_en (B_po_counter_load_en), .po_counter_read_en (B_po_counter_read_en), .po_counter_load_val (B_po_counter_load_val), .po_coarse_overflow (B_po_coarse_overflow), .po_fine_overflow (B_po_fine_overflow), .po_counter_read_val (B_po_counter_read_val), .po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (B_pi_fine_enable), .pi_fine_inc (B_pi_fine_inc), .pi_counter_load_en (B_pi_counter_load_en), .pi_counter_read_en (B_pi_counter_read_en), .pi_counter_load_val (B_pi_counter_load_val), .pi_fine_overflow (B_pi_fine_overflow), .pi_counter_read_val (B_pi_counter_read_val), .pi_iserdes_rst (B_pi_iserdes_rst), .pi_phase_locked (B_pi_phase_locked), .fine_delay (B_fine_delay), .fine_delay_sel (B_fine_delay_sel) ); end else begin : no_ddr_byte_lane_B assign B_of_a_full = 1'b0; assign B_of_full = 1'b0; assign B_pre_fifo_a_full = 1'b0; assign B_if_empty = 1'b0; assign B_if_a_empty = 1'b0; assign B_byte_rd_en = 1'b1; assign B_pi_phase_locked = 1; assign B_pi_dqs_found = 1; assign B_rclk = 0; assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign B_pi_counter_read_val = 0; assign B_po_counter_read_val = 0; assign B_pi_fine_overflow = 0; assign B_po_coarse_overflow = 0; assign B_po_fine_overflow = 0; end if ( BYTE_LANES[2] ) begin : ddr_byte_lane_C assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("C"), .PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[35:24]), .BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (C_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (C_PI_BURST_MODE), .PI_CLKOUT_DIV (C_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV), .PI_FINE_DELAY (C_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (C_PO_CLKOUT_DIV), .PO_FINE_DELAY (C_PO_FINE_DELAY), .PO_COARSE_BYPASS (C_PO_COARSE_BYPASS), .PO_COARSE_DELAY (C_PO_COARSE_DELAY), .PO_OCLK_DELAY (C_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (C_OS_DATA_RATE), .OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_C( .mem_dq_out (mem_dq_out[35:24]), .mem_dq_ts (mem_dq_ts[35:24]), .mem_dq_in (mem_dq_in[29:20]), .mem_dqs_out (mem_dqs_out[2]), .mem_dqs_ts (mem_dqs_ts[2]), .mem_dqs_in (mem_dqs_in[2]), .rst (C_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (C_ddr_clk), .rclk (C_rclk), .pi_dqs_found (C_pi_dqs_found), .dqs_out_of_range (C_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (C_if_a_empty), .if_empty (C_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*C_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*C_of_empty*/), .of_a_full (C_of_a_full), .of_full (C_of_full), .pre_fifo_a_full (C_pre_fifo_a_full), .phy_din (phy_din_remap[239:160]), .phy_dout (phy_dout_remap[239:160]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (C_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (C_idelay_ce), .idelay_ld (C_idelay_ld), .pi_rst_dqs_find (C_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (C_po_fine_enable), .po_coarse_enable (C_po_coarse_enable), .po_fine_inc (C_po_fine_inc), .po_coarse_inc (C_po_coarse_inc), .po_counter_load_en (C_po_counter_load_en), .po_counter_read_en (C_po_counter_read_en), .po_counter_load_val (C_po_counter_load_val), .po_coarse_overflow (C_po_coarse_overflow), .po_fine_overflow (C_po_fine_overflow), .po_counter_read_val (C_po_counter_read_val), .po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (C_pi_fine_enable), .pi_fine_inc (C_pi_fine_inc), .pi_counter_load_en (C_pi_counter_load_en), .pi_counter_read_en (C_pi_counter_read_en), .pi_counter_load_val (C_pi_counter_load_val), .pi_fine_overflow (C_pi_fine_overflow), .pi_counter_read_val (C_pi_counter_read_val), .pi_iserdes_rst (C_pi_iserdes_rst), .pi_phase_locked (C_pi_phase_locked), .fine_delay (C_fine_delay), .fine_delay_sel (C_fine_delay_sel) ); end else begin : no_ddr_byte_lane_C assign C_of_a_full = 1'b0; assign C_of_full = 1'b0; assign C_pre_fifo_a_full = 1'b0; assign C_if_empty = 1'b0; assign C_byte_rd_en = 1'b1; assign C_if_a_empty = 1'b0; assign C_pi_phase_locked = 1; assign C_pi_dqs_found = 1; assign C_rclk = 0; assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign C_pi_counter_read_val = 0; assign C_po_counter_read_val = 0; assign C_pi_fine_overflow = 0; assign C_po_coarse_overflow = 0; assign C_po_fine_overflow = 0; end if ( BYTE_LANES[3] ) begin : ddr_byte_lane_D assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("D"), .PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[47:36]), .BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (D_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (D_PI_BURST_MODE), .PI_CLKOUT_DIV (D_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV), .PI_FINE_DELAY (D_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (D_PO_CLKOUT_DIV), .PO_FINE_DELAY (D_PO_FINE_DELAY), .PO_COARSE_BYPASS (D_PO_COARSE_BYPASS), .PO_COARSE_DELAY (D_PO_COARSE_DELAY), .PO_OCLK_DELAY (D_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (D_OS_DATA_RATE), .OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_D( .mem_dq_out (mem_dq_out[47:36]), .mem_dq_ts (mem_dq_ts[47:36]), .mem_dq_in (mem_dq_in[39:30]), .mem_dqs_out (mem_dqs_out[3]), .mem_dqs_ts (mem_dqs_ts[3]), .mem_dqs_in (mem_dqs_in[3]), .rst (D_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (D_ddr_clk), .rclk (D_rclk), .pi_dqs_found (D_pi_dqs_found), .dqs_out_of_range (D_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (D_if_a_empty), .if_empty (D_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*D_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*D_of_empty*/), .of_a_full (D_of_a_full), .of_full (D_of_full), .pre_fifo_a_full (D_pre_fifo_a_full), .phy_din (phy_din_remap[319:240]), .phy_dout (phy_dout_remap[319:240]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .idelay_inc (idelay_inc), .idelay_ce (D_idelay_ce), .idelay_ld (D_idelay_ld), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (D_byte_rd_en), // calibration signals .pi_rst_dqs_find (D_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (D_po_fine_enable), .po_coarse_enable (D_po_coarse_enable), .po_fine_inc (D_po_fine_inc), .po_coarse_inc (D_po_coarse_inc), .po_counter_load_en (D_po_counter_load_en), .po_counter_read_en (D_po_counter_read_en), .po_counter_load_val (D_po_counter_load_val), .po_coarse_overflow (D_po_coarse_overflow), .po_fine_overflow (D_po_fine_overflow), .po_counter_read_val (D_po_counter_read_val), .po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (D_pi_fine_enable), .pi_fine_inc (D_pi_fine_inc), .pi_counter_load_en (D_pi_counter_load_en), .pi_counter_read_en (D_pi_counter_read_en), .pi_counter_load_val (D_pi_counter_load_val), .pi_fine_overflow (D_pi_fine_overflow), .pi_counter_read_val (D_pi_counter_read_val), .pi_iserdes_rst (D_pi_iserdes_rst), .pi_phase_locked (D_pi_phase_locked), .fine_delay (D_fine_delay), .fine_delay_sel (D_fine_delay_sel) ); end else begin : no_ddr_byte_lane_D assign D_of_a_full = 1'b0; assign D_of_full = 1'b0; assign D_pre_fifo_a_full = 1'b0; assign D_if_empty = 1'b0; assign D_byte_rd_en = 1'b1; assign D_if_a_empty = 1'b0; assign D_rclk = 0; assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign D_pi_dqs_found = 1; assign D_pi_phase_locked = 1; assign D_pi_counter_read_val = 0; assign D_po_counter_read_val = 0; assign D_pi_fine_overflow = 0; assign D_po_coarse_overflow = 0; assign D_po_fine_overflow = 0; end endgenerate assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank; PHY_CONTROL #( .AO_WRLVL_EN ( PC_AO_WRLVL_EN), .AO_TOGGLE ( PC_AO_TOGGLE), .BURST_MODE ( PC_BURST_MODE), .CO_DURATION ( PC_CO_DURATION ), .CLK_RATIO ( PC_CLK_RATIO), .DATA_CTL_A_N ( PC_DATA_CTL_A), .DATA_CTL_B_N ( PC_DATA_CTL_B), .DATA_CTL_C_N ( PC_DATA_CTL_C), .DATA_CTL_D_N ( PC_DATA_CTL_D), .DI_DURATION ( PC_DI_DURATION ), .DO_DURATION ( PC_DO_DURATION ), .EVENTS_DELAY ( PC_EVENTS_DELAY), .FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS), .MULTI_REGION ( PC_MULTI_REGION ), .PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN), .DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH), .SYNC_MODE ( PC_SYNC_MODE), .CMD_OFFSET ( PC_CMD_OFFSET), .RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0), .RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1), .RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2), .RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3), .RD_DURATION_0 ( PC_RD_DURATION_0), .RD_DURATION_1 ( PC_RD_DURATION_1), .RD_DURATION_2 ( PC_RD_DURATION_2), .RD_DURATION_3 ( PC_RD_DURATION_3), .WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0), .WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1), .WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2), .WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3), .WR_DURATION_0 ( PC_WR_DURATION_0), .WR_DURATION_1 ( PC_WR_DURATION_1), .WR_DURATION_2 ( PC_WR_DURATION_2), .WR_DURATION_3 ( PC_WR_DURATION_3) ) phy_control_i ( .AUXOUTPUT (aux_out), .INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]), .INRANKA (in_rank[1:0]), .INRANKB (in_rank[3:2]), .INRANKC (in_rank[5:4]), .INRANKD (in_rank[7:6]), .OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]), .PCENABLECALIB (phy_encalib), .PHYCTLALMOSTFULL (phy_ctl_a_full), .PHYCTLEMPTY (phy_ctl_empty), .PHYCTLFULL (phy_ctl_full), .PHYCTLREADY (phy_ctl_ready), .MEMREFCLK (mem_refclk), .PHYCLK (phy_ctl_clk), .PHYCTLMSTREMPTY (phy_ctl_mstr_empty), .PHYCTLWD (_phy_ctl_wd), .PHYCTLWRENABLE (phy_ctl_wr), .PLLLOCK (pll_lock), .REFDLLLOCK (ref_dll_lock), // is reset while !locked .RESET (rst), .SYNCIN (sync_pulse), .READCALIBENABLE (phy_read_calib), .WRITECALIBENABLE (phy_write_calib) `ifdef USE_PHY_CONTROL_TEST , .TESTINPUT (16'b0), .TESTOUTPUT (test_output), .TESTSELECT (test_select), .SCANENABLEN (scan_enable) `endif ); // register outputs to give extra slack in timing always @(posedge phy_clk ) begin case (calib_sel[1:0]) 2'h0: begin po_coarse_overflow <= #1 A_po_coarse_overflow; po_fine_overflow <= #1 A_po_fine_overflow; po_counter_read_val <= #1 A_po_counter_read_val; pi_fine_overflow <= #1 A_pi_fine_overflow; pi_counter_read_val<= #1 A_pi_counter_read_val; pi_phase_locked <= #1 A_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 A_pi_dqs_found; pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range; end 2'h1: begin po_coarse_overflow <= #1 B_po_coarse_overflow; po_fine_overflow <= #1 B_po_fine_overflow; po_counter_read_val <= #1 B_po_counter_read_val; pi_fine_overflow <= #1 B_pi_fine_overflow; pi_counter_read_val <= #1 B_pi_counter_read_val; pi_phase_locked <= #1 B_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 B_pi_dqs_found; pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range; end 2'h2: begin po_coarse_overflow <= #1 C_po_coarse_overflow; po_fine_overflow <= #1 C_po_fine_overflow; po_counter_read_val <= #1 C_po_counter_read_val; pi_fine_overflow <= #1 C_pi_fine_overflow; pi_counter_read_val <= #1 C_pi_counter_read_val; pi_phase_locked <= #1 C_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 C_pi_dqs_found; pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range; end 2'h3: begin po_coarse_overflow <= #1 D_po_coarse_overflow; po_fine_overflow <= #1 D_po_fine_overflow; po_counter_read_val <= #1 D_po_counter_read_val; pi_fine_overflow <= #1 D_pi_fine_overflow; pi_counter_read_val <= #1 D_pi_counter_read_val; pi_phase_locked <= #1 D_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 D_pi_dqs_found; pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range; end default: begin po_coarse_overflow <= po_coarse_overflow; end endcase end wire B_mux_ctrl; wire C_mux_ctrl; wire D_mux_ctrl; generate if (HIGHEST_LANE > 1) assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1])); else assign B_mux_ctrl = 0; if (HIGHEST_LANE > 2) assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2])); else assign C_mux_ctrl = 0; if (HIGHEST_LANE > 3) assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3])); else assign D_mux_ctrl = 0; endgenerate always @(*) begin A_pi_fine_enable = 0; A_pi_fine_inc = 0; A_pi_counter_load_en = 0; A_pi_counter_read_en = 0; A_pi_counter_load_val = 0; A_pi_rst_dqs_find = 0; A_po_fine_enable = 0; A_po_coarse_enable = 0; A_po_fine_inc = 0; A_po_coarse_inc = 0; A_po_counter_load_en = 0; A_po_counter_read_en = 0; A_po_counter_load_val = 0; A_po_sel_fine_oclk_delay = 0; A_idelay_ce = 0; A_idelay_ld = 0; A_fine_delay = 0; A_fine_delay_sel = 0; B_pi_fine_enable = 0; B_pi_fine_inc = 0; B_pi_counter_load_en = 0; B_pi_counter_read_en = 0; B_pi_counter_load_val = 0; B_pi_rst_dqs_find = 0; B_po_fine_enable = 0; B_po_coarse_enable = 0; B_po_fine_inc = 0; B_po_coarse_inc = 0; B_po_counter_load_en = 0; B_po_counter_read_en = 0; B_po_counter_load_val = 0; B_po_sel_fine_oclk_delay = 0; B_idelay_ce = 0; B_idelay_ld = 0; B_fine_delay = 0; B_fine_delay_sel = 0; C_pi_fine_enable = 0; C_pi_fine_inc = 0; C_pi_counter_load_en = 0; C_pi_counter_read_en = 0; C_pi_counter_load_val = 0; C_pi_rst_dqs_find = 0; C_po_fine_enable = 0; C_po_coarse_enable = 0; C_po_fine_inc = 0; C_po_coarse_inc = 0; C_po_counter_load_en = 0; C_po_counter_read_en = 0; C_po_counter_load_val = 0; C_po_sel_fine_oclk_delay = 0; C_idelay_ce = 0; C_idelay_ld = 0; C_fine_delay = 0; C_fine_delay_sel = 0; D_pi_fine_enable = 0; D_pi_fine_inc = 0; D_pi_counter_load_en = 0; D_pi_counter_read_en = 0; D_pi_counter_load_val = 0; D_pi_rst_dqs_find = 0; D_po_fine_enable = 0; D_po_coarse_enable = 0; D_po_fine_inc = 0; D_po_coarse_inc = 0; D_po_counter_load_en = 0; D_po_counter_read_en = 0; D_po_counter_load_val = 0; D_po_sel_fine_oclk_delay = 0; D_idelay_ce = 0; D_idelay_ld = 0; D_fine_delay = 0; D_fine_delay_sel = 0; if ( calib_sel[2]) begin // if this is asserted, all calib signals are deasserted A_pi_fine_enable = 0; A_pi_fine_inc = 0; A_pi_counter_load_en = 0; A_pi_counter_read_en = 0; A_pi_counter_load_val = 0; A_pi_rst_dqs_find = 0; A_po_fine_enable = 0; A_po_coarse_enable = 0; A_po_fine_inc = 0; A_po_coarse_inc = 0; A_po_counter_load_en = 0; A_po_counter_read_en = 0; A_po_counter_load_val = 0; A_po_sel_fine_oclk_delay = 0; A_idelay_ce = 0; A_idelay_ld = 0; A_fine_delay = 0; A_fine_delay_sel = 0; B_pi_fine_enable = 0; B_pi_fine_inc = 0; B_pi_counter_load_en = 0; B_pi_counter_read_en = 0; B_pi_counter_load_val = 0; B_pi_rst_dqs_find = 0; B_po_fine_enable = 0; B_po_coarse_enable = 0; B_po_fine_inc = 0; B_po_coarse_inc = 0; B_po_counter_load_en = 0; B_po_counter_read_en = 0; B_po_counter_load_val = 0; B_po_sel_fine_oclk_delay = 0; B_idelay_ce = 0; B_idelay_ld = 0; B_fine_delay = 0; B_fine_delay_sel = 0; C_pi_fine_enable = 0; C_pi_fine_inc = 0; C_pi_counter_load_en = 0; C_pi_counter_read_en = 0; C_pi_counter_load_val = 0; C_pi_rst_dqs_find = 0; C_po_fine_enable = 0; C_po_coarse_enable = 0; C_po_fine_inc = 0; C_po_coarse_inc = 0; C_po_counter_load_en = 0; C_po_counter_read_en = 0; C_po_counter_load_val = 0; C_po_sel_fine_oclk_delay = 0; C_idelay_ce = 0; C_idelay_ld = 0; C_fine_delay = 0; C_fine_delay_sel = 0; D_pi_fine_enable = 0; D_pi_fine_inc = 0; D_pi_counter_load_en = 0; D_pi_counter_read_en = 0; D_pi_counter_load_val = 0; D_pi_rst_dqs_find = 0; D_po_fine_enable = 0; D_po_coarse_enable = 0; D_po_fine_inc = 0; D_po_coarse_inc = 0; D_po_counter_load_en = 0; D_po_counter_read_en = 0; D_po_counter_load_val = 0; D_po_sel_fine_oclk_delay = 0; D_idelay_ce = 0; D_idelay_ld = 0; D_fine_delay = 0; D_fine_delay_sel = 0; end else if (calib_in_common) begin // if this is asserted, each signal is broadcast to all phasers // in common if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin A_pi_fine_enable = pi_fine_enable; A_pi_fine_inc = pi_fine_inc; A_pi_counter_load_en = pi_counter_load_en; A_pi_counter_read_en = pi_counter_read_en; A_pi_counter_load_val = pi_counter_load_val; A_pi_rst_dqs_find = pi_rst_dqs_find; A_po_fine_enable = po_fine_enable; A_po_coarse_enable = po_coarse_enable; A_po_fine_inc = po_fine_inc; A_po_coarse_inc = po_coarse_inc; A_po_counter_load_en = po_counter_load_en; A_po_counter_read_en = po_counter_read_en; A_po_counter_load_val = po_counter_load_val; A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; A_idelay_ce = idelay_ce; A_idelay_ld = idelay_ld; A_fine_delay = fine_delay ; A_fine_delay_sel = fine_delay_sel; end if ( B_mux_ctrl) begin B_pi_fine_enable = pi_fine_enable; B_pi_fine_inc = pi_fine_inc; B_pi_counter_load_en = pi_counter_load_en; B_pi_counter_read_en = pi_counter_read_en; B_pi_counter_load_val = pi_counter_load_val; B_pi_rst_dqs_find = pi_rst_dqs_find; B_po_fine_enable = po_fine_enable; B_po_coarse_enable = po_coarse_enable; B_po_fine_inc = po_fine_inc; B_po_coarse_inc = po_coarse_inc; B_po_counter_load_en = po_counter_load_en; B_po_counter_read_en = po_counter_read_en; B_po_counter_load_val = po_counter_load_val; B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; B_idelay_ce = idelay_ce; B_idelay_ld = idelay_ld; B_fine_delay = fine_delay ; B_fine_delay_sel = fine_delay_sel; end if ( C_mux_ctrl) begin C_pi_fine_enable = pi_fine_enable; C_pi_fine_inc = pi_fine_inc; C_pi_counter_load_en = pi_counter_load_en; C_pi_counter_read_en = pi_counter_read_en; C_pi_counter_load_val = pi_counter_load_val; C_pi_rst_dqs_find = pi_rst_dqs_find; C_po_fine_enable = po_fine_enable; C_po_coarse_enable = po_coarse_enable; C_po_fine_inc = po_fine_inc; C_po_coarse_inc = po_coarse_inc; C_po_counter_load_en = po_counter_load_en; C_po_counter_read_en = po_counter_read_en; C_po_counter_load_val = po_counter_load_val; C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; C_idelay_ce = idelay_ce; C_idelay_ld = idelay_ld; C_fine_delay = fine_delay ; C_fine_delay_sel = fine_delay_sel; end if ( D_mux_ctrl) begin D_pi_fine_enable = pi_fine_enable; D_pi_fine_inc = pi_fine_inc; D_pi_counter_load_en = pi_counter_load_en; D_pi_counter_read_en = pi_counter_read_en; D_pi_counter_load_val = pi_counter_load_val; D_pi_rst_dqs_find = pi_rst_dqs_find; D_po_fine_enable = po_fine_enable; D_po_coarse_enable = po_coarse_enable; D_po_fine_inc = po_fine_inc; D_po_coarse_inc = po_coarse_inc; D_po_counter_load_en = po_counter_load_en; D_po_counter_read_en = po_counter_read_en; D_po_counter_load_val = po_counter_load_val; D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; D_idelay_ce = idelay_ce; D_idelay_ld = idelay_ld; D_fine_delay = fine_delay ; D_fine_delay_sel = fine_delay_sel; end end else begin // otherwise, only a single phaser is selected case (calib_sel[1:0]) 0: begin A_pi_fine_enable = pi_fine_enable; A_pi_fine_inc = pi_fine_inc; A_pi_counter_load_en = pi_counter_load_en; A_pi_counter_read_en = pi_counter_read_en; A_pi_counter_load_val = pi_counter_load_val; A_pi_rst_dqs_find = pi_rst_dqs_find; A_po_fine_enable = po_fine_enable; A_po_coarse_enable = po_coarse_enable; A_po_fine_inc = po_fine_inc; A_po_coarse_inc = po_coarse_inc; A_po_counter_load_en = po_counter_load_en; A_po_counter_read_en = po_counter_read_en; A_po_counter_load_val = po_counter_load_val; A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; A_idelay_ce = idelay_ce; A_idelay_ld = idelay_ld; A_fine_delay = fine_delay ; A_fine_delay_sel = fine_delay_sel; end 1: begin B_pi_fine_enable = pi_fine_enable; B_pi_fine_inc = pi_fine_inc; B_pi_counter_load_en = pi_counter_load_en; B_pi_counter_read_en = pi_counter_read_en; B_pi_counter_load_val = pi_counter_load_val; B_pi_rst_dqs_find = pi_rst_dqs_find; B_po_fine_enable = po_fine_enable; B_po_coarse_enable = po_coarse_enable; B_po_fine_inc = po_fine_inc; B_po_coarse_inc = po_coarse_inc; B_po_counter_load_en = po_counter_load_en; B_po_counter_read_en = po_counter_read_en; B_po_counter_load_val = po_counter_load_val; B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; B_idelay_ce = idelay_ce; B_idelay_ld = idelay_ld; B_fine_delay = fine_delay ; B_fine_delay_sel = fine_delay_sel; end 2: begin C_pi_fine_enable = pi_fine_enable; C_pi_fine_inc = pi_fine_inc; C_pi_counter_load_en = pi_counter_load_en; C_pi_counter_read_en = pi_counter_read_en; C_pi_counter_load_val = pi_counter_load_val; C_pi_rst_dqs_find = pi_rst_dqs_find; C_po_fine_enable = po_fine_enable; C_po_coarse_enable = po_coarse_enable; C_po_fine_inc = po_fine_inc; C_po_coarse_inc = po_coarse_inc; C_po_counter_load_en = po_counter_load_en; C_po_counter_read_en = po_counter_read_en; C_po_counter_load_val = po_counter_load_val; C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; C_idelay_ce = idelay_ce; C_idelay_ld = idelay_ld; C_fine_delay = fine_delay ; C_fine_delay_sel = fine_delay_sel; end 3: begin D_pi_fine_enable = pi_fine_enable; D_pi_fine_inc = pi_fine_inc; D_pi_counter_load_en = pi_counter_load_en; D_pi_counter_read_en = pi_counter_read_en; D_pi_counter_load_val = pi_counter_load_val; D_pi_rst_dqs_find = pi_rst_dqs_find; D_po_fine_enable = po_fine_enable; D_po_coarse_enable = po_coarse_enable; D_po_fine_inc = po_fine_inc; D_po_coarse_inc = po_coarse_inc; D_po_counter_load_en = po_counter_load_en; D_po_counter_load_val = po_counter_load_val; D_po_counter_read_en = po_counter_read_en; D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; D_idelay_ce = idelay_ce; D_idelay_ld = idelay_ld; D_fine_delay = fine_delay ; D_fine_delay_sel = fine_delay_sel; end endcase end end //obligatory phaser-ref PHASER_REF phaser_ref_i( .LOCKED (ref_dll_lock), .CLKIN (freq_refclk), .PWRDWN (1'b0), .RST ( ! pll_lock) ); // optional idelay_ctrl generate if ( GENERATE_IDELAYCTRL == "TRUE") IDELAYCTRL idelayctrl ( .RDY (/*idelayctrl_rdy*/), .REFCLK (idelayctrl_refclk), .RST (rst) ); endgenerate endmodule
/********************************************************** -- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). A Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. // // THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. // // // Owner: Gary Martin // Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $ // $Author: gary $ // $DateTime: 2010/05/11 18:05:17 $ // $Change: 490882 $ // Description: // This verilog file is the parameterizable 4-byte lane phy primitive top // This module may be ganged to create an N-lane phy. // // History: // Date Engineer Description // 04/01/2010 G. Martin Initial Checkin. // /////////////////////////////////////////////////////////// **********************************************************/ `timescale 1ps/1ps `define PC_DATA_OFFSET_RANGE 22:17 module mig_7series_v2_3_ddr_phy_4lanes #( parameter GENERATE_IDELAYCTRL = "TRUE", parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010, parameter NUM_DDR_CK = 1, // next three parameter fields correspond to byte lanes for lane order DCBA parameter BYTE_LANES = 4'b1111, // lane existence, one per lane parameter DATA_CTL_N = 4'b1111, // data or control, per lane parameter BITLANES = 48'hffff_ffff_ffff, parameter BITLANES_OUTONLY = 48'h0000_0000_0000, parameter LANE_REMAP = 16'h3210,// 4-bit index // used to rewire to one of four // input/output buss lanes // example: 0321 remaps lanes as: // D->A // C->D // B->C // A->B parameter LAST_BANK = "FALSE", parameter USE_PRE_POST_FIFO = "FALSE", parameter RCLK_SELECT_LANE = "B", parameter real TCK = 0.00, parameter SYNTHESIS = "FALSE", parameter PO_CTL_COARSE_BYPASS = "FALSE", parameter PO_FINE_DELAY = 0, parameter PI_SEL_CLK_OFFSET = 0, // phy_control paramter used in other paramsters parameter PC_CLK_RATIO = 4, //phaser_in parameters parameter A_PI_FREQ_REF_DIV = "NONE", parameter A_PI_CLKOUT_DIV = 2, parameter A_PI_BURST_MODE = "TRUE", parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF", parameter A_PI_FINE_DELAY = 60, parameter A_PI_SYNC_IN_DIV_RST = "TRUE", parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter B_PI_BURST_MODE = A_PI_BURST_MODE, parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY, parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter C_PI_BURST_MODE = A_PI_BURST_MODE, parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter C_PI_FINE_DELAY = 0, parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, parameter D_PI_BURST_MODE = A_PI_BURST_MODE, parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, parameter D_PI_FINE_DELAY = 0, parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, //phaser_out parameters parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2, parameter A_PO_FINE_DELAY = PO_FINE_DELAY, parameter A_PO_COARSE_DELAY = 0, parameter A_PO_OCLK_DELAY = 0, parameter A_PO_OCLKDELAY_INV = "FALSE", parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF", parameter A_PO_SYNC_IN_DIV_RST = "TRUE", //parameter A_PO_SYNC_IN_DIV_RST = "FALSE", parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2, parameter B_PO_FINE_DELAY = PO_FINE_DELAY, parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2, parameter C_PO_FINE_DELAY = PO_FINE_DELAY, parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2, parameter D_PO_FINE_DELAY = PO_FINE_DELAY, parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY, parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY, parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE", parameter A_IDELAYE2_IDELAY_VALUE = 00, parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, // phy_control parameters parameter PC_BURST_MODE = "TRUE", parameter PC_DATA_CTL_N = DATA_CTL_N, parameter PC_CMD_OFFSET = 0, parameter PC_RD_CMD_OFFSET_0 = 0, parameter PC_RD_CMD_OFFSET_1 = 0, parameter PC_RD_CMD_OFFSET_2 = 0, parameter PC_RD_CMD_OFFSET_3 = 0, parameter PC_CO_DURATION = 1, parameter PC_DI_DURATION = 1, parameter PC_DO_DURATION = 1, parameter PC_RD_DURATION_0 = 0, parameter PC_RD_DURATION_1 = 0, parameter PC_RD_DURATION_2 = 0, parameter PC_RD_DURATION_3 = 0, parameter PC_WR_CMD_OFFSET_0 = 5, parameter PC_WR_CMD_OFFSET_1 = 5, parameter PC_WR_CMD_OFFSET_2 = 5, parameter PC_WR_CMD_OFFSET_3 = 5, parameter PC_WR_DURATION_0 = 6, parameter PC_WR_DURATION_1 = 6, parameter PC_WR_DURATION_2 = 6, parameter PC_WR_DURATION_3 = 6, parameter PC_AO_WRLVL_EN = 0, parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE) parameter PC_FOUR_WINDOW_CLOCKS = 63, parameter PC_EVENTS_DELAY = 18, parameter PC_PHY_COUNT_EN = "TRUE", parameter PC_SYNC_MODE = "TRUE", parameter PC_DISABLE_SEQ_MATCH = "TRUE", parameter PC_MULTI_REGION = "FALSE", // io fifo parameters parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", parameter OF_ALMOST_EMPTY_VALUE = 1, parameter OF_ALMOST_FULL_VALUE = 1, parameter OF_OUTPUT_DISABLE = "TRUE", parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE, parameter A_OS_DATA_RATE = "DDR", parameter A_OS_DATA_WIDTH = 4, parameter B_OS_DATA_RATE = A_OS_DATA_RATE, parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter C_OS_DATA_RATE = A_OS_DATA_RATE, parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter D_OS_DATA_RATE = A_OS_DATA_RATE, parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH, parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8", parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE, parameter IF_ALMOST_EMPTY_VALUE = 1, parameter IF_ALMOST_FULL_VALUE = 1, parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE, // this is used locally, not for external pushdown // NOTE: the 0+ is needed in each to coerce to integer for addition. // otherwise 4x 1'b values are added producing a 1'b value. parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1), parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])), parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]), parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES, // assume odt per rank + any declared cke's parameter AUXOUT_WIDTH = 4, parameter LP_DDR_CK_WIDTH = 2 ,parameter CKE_ODT_AUX = "FALSE" ) ( //`include "phy.vh" input rst, input phy_clk, input phy_ctl_clk, input freq_refclk, input mem_refclk, input mem_refclk_div4, input pll_lock, input sync_pulse, input idelayctrl_refclk, input [HIGHEST_LANE*80-1:0] phy_dout, input phy_cmd_wr_en, input phy_data_wr_en, input phy_rd_en, input phy_ctl_mstr_empty, input [31:0] phy_ctl_wd, input [`PC_DATA_OFFSET_RANGE] data_offset, input phy_ctl_wr, input if_empty_def, input phyGo, input input_sink, output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory output rclk, output if_a_empty, output if_empty, output byte_rd_en, output if_empty_or, output if_empty_and, output of_ctl_a_full, output of_data_a_full, output of_ctl_full, output of_data_full, output pre_data_a_full, output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus output phy_ctl_empty, output phy_ctl_a_full, output phy_ctl_full, output [HIGHEST_LANE*12-1:0]mem_dq_out, output [HIGHEST_LANE*12-1:0]mem_dq_ts, input [HIGHEST_LANE*10-1:0]mem_dq_in, output [HIGHEST_LANE-1:0] mem_dqs_out, output [HIGHEST_LANE-1:0] mem_dqs_ts, input [HIGHEST_LANE-1:0] mem_dqs_in, input [1:0] byte_rd_en_oth_banks, output [AUXOUT_WIDTH-1:0] aux_out, output reg rst_out = 0, output reg mcGo=0, output phy_ctl_ready, output ref_dll_lock, input if_rst, input phy_read_calib, input phy_write_calib, input idelay_inc, input idelay_ce, input idelay_ld, input [2:0] calib_sel, input calib_zero_ctrl, input [HIGHEST_LANE-1:0] calib_zero_lanes, input calib_in_common, input po_fine_enable, input po_coarse_enable, input po_fine_inc, input po_coarse_inc, input po_counter_load_en, input po_counter_read_en, input [8:0] po_counter_load_val, input po_sel_fine_oclk_delay, output reg po_coarse_overflow, output reg po_fine_overflow, output reg [8:0] po_counter_read_val, input pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input pi_counter_read_en, input [5:0] pi_counter_load_val, output reg pi_fine_overflow, output reg [5:0] pi_counter_read_val, output reg pi_dqs_found, output pi_dqs_found_all, output pi_dqs_found_any, output [HIGHEST_LANE-1:0] pi_phase_locked_lanes, output [HIGHEST_LANE-1:0] pi_dqs_found_lanes, output reg pi_dqs_out_of_range, output reg pi_phase_locked, output pi_phase_locked_all, input [29:0] fine_delay, input fine_delay_sel ); localparam DATA_CTL_A = (~DATA_CTL_N[0]); localparam DATA_CTL_B = (~DATA_CTL_N[1]); localparam DATA_CTL_C = (~DATA_CTL_N[2]); localparam DATA_CTL_D = (~DATA_CTL_N[3]); localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0]; localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1]; localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2]; localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3]; localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0]; localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1]; localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2]; localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3]; localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE"; localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE"; localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE"; localparam IO_A_START = 41; localparam IO_A_END = 40; localparam IO_B_START = 43; localparam IO_B_END = 42; localparam IO_C_START = 45; localparam IO_C_END = 44; localparam IO_D_START = 47; localparam IO_D_END = 46; localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1; localparam IO_A_X_END = (IO_A_X_START-1); localparam IO_B_X_START = (IO_A_X_START + 2); localparam IO_B_X_END = (IO_B_X_START -1); localparam IO_C_X_START = (IO_B_X_START + 2); localparam IO_C_X_END = (IO_C_X_START -1); localparam IO_D_X_START = (IO_C_X_START + 2); localparam IO_D_X_END = (IO_D_X_START -1); localparam MSB_BURST_PEND_PO = 3; localparam MSB_BURST_PEND_PI = 7; localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8; localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1; wire [1:0] oserdes_dqs; wire [1:0] oserdes_dqs_ts; wire [1:0] oserdes_dq_ts; wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus; wire [7:0] in_rank; wire [11:0] IO_A; wire [11:0] IO_B; wire [11:0] IO_C; wire [11:0] IO_D; wire [319:0] phy_din_remap; reg A_po_counter_read_en; wire [8:0] A_po_counter_read_val; reg A_pi_counter_read_en; wire [5:0] A_pi_counter_read_val; wire A_pi_fine_overflow; wire A_po_coarse_overflow; wire A_po_fine_overflow; wire A_pi_dqs_found; wire A_pi_dqs_out_of_range; wire A_pi_phase_locked; wire A_pi_iserdes_rst; reg A_pi_fine_enable; reg A_pi_fine_inc; reg A_pi_counter_load_en; reg [5:0] A_pi_counter_load_val; reg A_pi_rst_dqs_find; reg A_po_fine_enable; reg A_po_coarse_enable; reg A_po_fine_inc /* synthesis syn_maxfan = 3 */; reg A_po_sel_fine_oclk_delay; reg A_po_coarse_inc; reg A_po_counter_load_en; reg [8:0] A_po_counter_load_val; wire A_rclk; reg A_idelay_ce; reg A_idelay_ld; reg [29:0] A_fine_delay; reg A_fine_delay_sel; reg B_po_counter_read_en; wire [8:0] B_po_counter_read_val; reg B_pi_counter_read_en; wire [5:0] B_pi_counter_read_val; wire B_pi_fine_overflow; wire B_po_coarse_overflow; wire B_po_fine_overflow; wire B_pi_phase_locked; wire B_pi_iserdes_rst; wire B_pi_dqs_found; wire B_pi_dqs_out_of_range; reg B_pi_fine_enable; reg B_pi_fine_inc; reg B_pi_counter_load_en; reg [5:0] B_pi_counter_load_val; reg B_pi_rst_dqs_find; reg B_po_fine_enable; reg B_po_coarse_enable; reg B_po_fine_inc /* synthesis syn_maxfan = 3 */; reg B_po_coarse_inc; reg B_po_sel_fine_oclk_delay; reg B_po_counter_load_en; reg [8:0] B_po_counter_load_val; wire B_rclk; reg B_idelay_ce; reg B_idelay_ld; reg [29:0] B_fine_delay; reg B_fine_delay_sel; reg C_pi_fine_inc; reg D_pi_fine_inc; reg C_pi_fine_enable; reg D_pi_fine_enable; reg C_po_counter_load_en; reg D_po_counter_load_en; reg C_po_coarse_inc; reg D_po_coarse_inc; reg C_po_fine_inc /* synthesis syn_maxfan = 3 */; reg D_po_fine_inc /* synthesis syn_maxfan = 3 */; reg C_po_sel_fine_oclk_delay; reg D_po_sel_fine_oclk_delay; reg [5:0] C_pi_counter_load_val; reg [5:0] D_pi_counter_load_val; reg [8:0] C_po_counter_load_val; reg [8:0] D_po_counter_load_val; reg C_po_coarse_enable; reg D_po_coarse_enable; reg C_po_fine_enable; reg D_po_fine_enable; wire C_po_coarse_overflow; wire D_po_coarse_overflow; wire C_po_fine_overflow; wire D_po_fine_overflow; wire [8:0] C_po_counter_read_val; wire [8:0] D_po_counter_read_val; reg C_po_counter_read_en; reg D_po_counter_read_en; wire C_pi_dqs_found; wire D_pi_dqs_found; wire C_pi_fine_overflow; wire D_pi_fine_overflow; reg C_pi_counter_read_en; reg D_pi_counter_read_en; reg C_pi_counter_load_en; reg D_pi_counter_load_en; wire C_pi_phase_locked; wire C_pi_iserdes_rst; wire D_pi_phase_locked; wire D_pi_iserdes_rst; wire C_pi_dqs_out_of_range; wire D_pi_dqs_out_of_range; wire [5:0] C_pi_counter_read_val; wire [5:0] D_pi_counter_read_val; wire C_rclk; wire D_rclk; reg C_idelay_ce; reg D_idelay_ce; reg C_idelay_ld; reg D_idelay_ld; reg C_pi_rst_dqs_find; reg D_pi_rst_dqs_find; reg [29:0] C_fine_delay; reg [29:0] D_fine_delay; reg C_fine_delay_sel; reg D_fine_delay_sel; wire pi_iserdes_rst; wire A_if_empty; wire B_if_empty; wire C_if_empty; wire D_if_empty; wire A_byte_rd_en; wire B_byte_rd_en; wire C_byte_rd_en; wire D_byte_rd_en; wire A_if_a_empty; wire B_if_a_empty; wire C_if_a_empty; wire D_if_a_empty; //wire A_if_full; //wire B_if_full; //wire C_if_full; //wire D_if_full; //wire A_of_empty; //wire B_of_empty; //wire C_of_empty; //wire D_of_empty; wire A_of_full; wire B_of_full; wire C_of_full; wire D_of_full; wire A_of_ctl_full; wire B_of_ctl_full; wire C_of_ctl_full; wire D_of_ctl_full; wire A_of_data_full; wire B_of_data_full; wire C_of_data_full; wire D_of_data_full; wire A_of_a_full; wire B_of_a_full; wire C_of_a_full; wire D_of_a_full; wire A_pre_fifo_a_full; wire B_pre_fifo_a_full; wire C_pre_fifo_a_full; wire D_pre_fifo_a_full; wire A_of_ctl_a_full; wire B_of_ctl_a_full; wire C_of_ctl_a_full; wire D_of_ctl_a_full; wire A_of_data_a_full; wire B_of_data_a_full; wire C_of_data_a_full; wire D_of_data_a_full; wire A_pre_data_a_full; wire B_pre_data_a_full; wire C_pre_data_a_full; wire D_pre_data_a_full; wire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation wire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; // wire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; // wire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; // wire [3:0] dummy_data; wire [31:0] _phy_ctl_wd; wire [1:0] phy_encalib; assign pi_dqs_found_all = (! PRESENT_DATA_A | A_pi_dqs_found) & (! PRESENT_DATA_B | B_pi_dqs_found) & (! PRESENT_DATA_C | C_pi_dqs_found) & (! PRESENT_DATA_D | D_pi_dqs_found) ; assign pi_dqs_found_any = ( PRESENT_DATA_A & A_pi_dqs_found) | ( PRESENT_DATA_B & B_pi_dqs_found) | ( PRESENT_DATA_C & C_pi_dqs_found) | ( PRESENT_DATA_D & D_pi_dqs_found) ; assign pi_phase_locked_all = (! PRESENT_DATA_A | A_pi_phase_locked) & (! PRESENT_DATA_B | B_pi_phase_locked) & (! PRESENT_DATA_C | C_pi_phase_locked) & (! PRESENT_DATA_D | D_pi_phase_locked); wire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal // which is combined into another signals such that // the other signal isn't changed. The purpose // is to fake the tools into ignoring dangling inputs. // Because it is anded with 1'b0, the contributing signals // are folded as constants or trimmed. assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty); assign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) : (A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en); assign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty); assign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty); assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty; //assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ; //assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty; assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ; assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ; assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ; assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ; assign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full; function [79:0] part_select_80; input [319:0] vector; input [1:0] select; begin case (select) 2'b00 : part_select_80[79:0] = vector[1*80-1:0*80]; 2'b01 : part_select_80[79:0] = vector[2*80-1:1*80]; 2'b10 : part_select_80[79:0] = vector[3*80-1:2*80]; 2'b11 : part_select_80[79:0] = vector[4*80-1:3*80]; endcase end endfunction wire [319:0] phy_dout_remap; reg rst_out_trig = 1'b0; reg [31:0] rclk_delay; reg rst_edge1 = 1'b0; reg rst_edge2 = 1'b0; reg rst_edge3 = 1'b0; reg rst_edge_detect = 1'b0; wire rclk_; reg rst_out_start = 1'b0 ; reg rst_primitives=0; reg A_rst_primitives=0; reg B_rst_primitives=0; reg C_rst_primitives=0; reg D_rst_primitives=0; `ifdef USE_PHY_CONTROL_TEST wire [15:0] test_output; wire [15:0] test_input; wire [2:0] test_select=0; wire scan_enable = 0; `endif generate genvar i; if (RCLK_SELECT_LANE == "A") begin assign rclk_ = A_rclk; assign pi_iserdes_rst = A_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "B") begin assign rclk_ = B_rclk; assign pi_iserdes_rst = B_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "C") begin assign rclk_ = C_rclk; assign pi_iserdes_rst = C_pi_iserdes_rst; end else if (RCLK_SELECT_LANE == "D") begin assign rclk_ = D_rclk; assign pi_iserdes_rst = D_pi_iserdes_rst; end else begin assign rclk_ = B_rclk; // default end endgenerate assign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk; assign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk; assign pi_phase_locked_lanes = {(! PRESENT_DATA_A[0] | A_pi_phase_locked), (! PRESENT_DATA_B[0] | B_pi_phase_locked) , (! PRESENT_DATA_C[0] | C_pi_phase_locked) , (! PRESENT_DATA_D[0] | D_pi_phase_locked)}; assign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found}; // this block scrubs X from rclk_delay[11] reg rclk_delay_11; always @(rclk_delay[11]) begin : rclk_delay_11_blk if ( rclk_delay[11]) rclk_delay_11 = 1; else rclk_delay_11 = 0; end always @(posedge phy_clk or posedge rst ) begin // scrub 4-state values from rclk_delay[11] if ( rst) begin rst_out <= #1 0; end else begin if ( rclk_delay_11) rst_out <= #1 1; end end always @(posedge phy_clk ) begin // phy_ctl_ready drives reset of the system rst_primitives <= !phy_ctl_ready ; A_rst_primitives <= rst_primitives ; B_rst_primitives <= rst_primitives ; C_rst_primitives <= rst_primitives ; D_rst_primitives <= rst_primitives ; rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo); mcGo <= #1 rst_out ; end generate if (BYTE_LANES[0]) begin assign dummy_data[0] = 0; end else begin assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80]; end if (BYTE_LANES[1]) begin assign dummy_data[1] = 0; end else begin assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80]; end if (BYTE_LANES[2]) begin assign dummy_data[2] = 0; end else begin assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80]; end if (BYTE_LANES[3]) begin assign dummy_data[3] = 0; end else begin assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80]; end if (PRESENT_DATA_A) begin assign A_of_data_full = A_of_full; assign A_of_ctl_full = 0; assign A_of_data_a_full = A_of_a_full; assign A_of_ctl_a_full = 0; assign A_pre_data_a_full = A_pre_fifo_a_full; end else begin assign A_of_ctl_full = A_of_full; assign A_of_data_full = 0; assign A_of_ctl_a_full = A_of_a_full; assign A_of_data_a_full = 0; assign A_pre_data_a_full = 0; end if (PRESENT_DATA_B) begin assign B_of_data_full = B_of_full; assign B_of_ctl_full = 0; assign B_of_data_a_full = B_of_a_full; assign B_of_ctl_a_full = 0; assign B_pre_data_a_full = B_pre_fifo_a_full; end else begin assign B_of_ctl_full = B_of_full; assign B_of_data_full = 0; assign B_of_ctl_a_full = B_of_a_full; assign B_of_data_a_full = 0; assign B_pre_data_a_full = 0; end if (PRESENT_DATA_C) begin assign C_of_data_full = C_of_full; assign C_of_ctl_full = 0; assign C_of_data_a_full = C_of_a_full; assign C_of_ctl_a_full = 0; assign C_pre_data_a_full = C_pre_fifo_a_full; end else begin assign C_of_ctl_full = C_of_full; assign C_of_data_full = 0; assign C_of_ctl_a_full = C_of_a_full; assign C_of_data_a_full = 0; assign C_pre_data_a_full = 0; end if (PRESENT_DATA_D) begin assign D_of_data_full = D_of_full; assign D_of_ctl_full = 0; assign D_of_data_a_full = D_of_a_full; assign D_of_ctl_a_full = 0; assign D_pre_data_a_full = D_pre_fifo_a_full; end else begin assign D_of_ctl_full = D_of_full; assign D_of_data_full = 0; assign D_of_ctl_a_full = D_of_a_full; assign D_of_data_a_full = 0; assign D_pre_data_a_full = 0; end // byte lane must exist and be data lane. if (PRESENT_DATA_A ) case ( LANE_REMAP[1:0] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0]; endcase else case ( LANE_REMAP[1:0] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_B ) case ( LANE_REMAP[5:4] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80]; endcase else if (HIGHEST_LANE > 1) case ( LANE_REMAP[5:4] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_C) case ( LANE_REMAP[9:8] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160]; endcase else if (HIGHEST_LANE > 2) case ( LANE_REMAP[9:8] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (PRESENT_DATA_D ) case ( LANE_REMAP[13:12] ) 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240]; 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240]; 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240]; 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240]; endcase else if (HIGHEST_LANE > 3) case ( LANE_REMAP[13:12] ) 2'b00 : assign phy_din[1*80-1:0] = 80'h0; 2'b01 : assign phy_din[2*80-1:80] = 80'h0; 2'b10 : assign phy_din[3*80-1:160] = 80'h0; 2'b11 : assign phy_din[4*80-1:240] = 80'h0; endcase if (HIGHEST_LANE > 1) assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]}; if (HIGHEST_LANE == 1) assign _phy_ctl_wd = phy_ctl_wd; //BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst)); BUFIO rclk_buf(.I(rclk_), .O(rclk) ); if ( BYTE_LANES[0] ) begin : ddr_byte_lane_A assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("A"), .PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[11:0]), .BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (A_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (A_PI_BURST_MODE), .PI_CLKOUT_DIV (A_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV), .PI_FINE_DELAY (A_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (A_PO_CLKOUT_DIV), .PO_FINE_DELAY (A_PO_FINE_DELAY), .PO_COARSE_BYPASS (A_PO_COARSE_BYPASS), .PO_COARSE_DELAY (A_PO_COARSE_DELAY), .PO_OCLK_DELAY (A_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (A_OS_DATA_RATE), .OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_A( .mem_dq_out (mem_dq_out[11:0]), .mem_dq_ts (mem_dq_ts[11:0]), .mem_dq_in (mem_dq_in[9:0]), .mem_dqs_out (mem_dqs_out[0]), .mem_dqs_ts (mem_dqs_ts[0]), .mem_dqs_in (mem_dqs_in[0]), .rst (A_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (A_ddr_clk), .rclk (A_rclk), .pi_dqs_found (A_pi_dqs_found), .dqs_out_of_range (A_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (A_if_a_empty), .if_empty (A_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*A_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*A_of_empty*/), .of_a_full (A_of_a_full), .of_full (A_of_full), .pre_fifo_a_full (A_pre_fifo_a_full), .phy_din (phy_din_remap[79:0]), .phy_dout (phy_dout_remap[79:0]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (A_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (A_idelay_ce), .idelay_ld (A_idelay_ld), .pi_rst_dqs_find (A_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (A_po_fine_enable), .po_coarse_enable (A_po_coarse_enable), .po_fine_inc (A_po_fine_inc), .po_coarse_inc (A_po_coarse_inc), .po_counter_load_en (A_po_counter_load_en), .po_counter_read_en (A_po_counter_read_en), .po_counter_load_val (A_po_counter_load_val), .po_coarse_overflow (A_po_coarse_overflow), .po_fine_overflow (A_po_fine_overflow), .po_counter_read_val (A_po_counter_read_val), .po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (A_pi_fine_enable), .pi_fine_inc (A_pi_fine_inc), .pi_counter_load_en (A_pi_counter_load_en), .pi_counter_read_en (A_pi_counter_read_en), .pi_counter_load_val (A_pi_counter_load_val), .pi_fine_overflow (A_pi_fine_overflow), .pi_counter_read_val (A_pi_counter_read_val), .pi_iserdes_rst (A_pi_iserdes_rst), .pi_phase_locked (A_pi_phase_locked), .fine_delay (A_fine_delay), .fine_delay_sel (A_fine_delay_sel) ); end else begin : no_ddr_byte_lane_A assign A_of_a_full = 1'b0; assign A_of_full = 1'b0; assign A_pre_fifo_a_full = 1'b0; assign A_if_empty = 1'b0; assign A_byte_rd_en = 1'b1; assign A_if_a_empty = 1'b0; assign A_pi_phase_locked = 1; assign A_pi_dqs_found = 1; assign A_rclk = 0; assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign A_pi_counter_read_val = 0; assign A_po_counter_read_val = 0; assign A_pi_fine_overflow = 0; assign A_po_coarse_overflow = 0; assign A_po_fine_overflow = 0; end if ( BYTE_LANES[1] ) begin : ddr_byte_lane_B assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("B"), .PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[23:12]), .BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (B_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (B_PI_BURST_MODE), .PI_CLKOUT_DIV (B_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV), .PI_FINE_DELAY (B_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (B_PO_CLKOUT_DIV), .PO_FINE_DELAY (B_PO_FINE_DELAY), .PO_COARSE_BYPASS (B_PO_COARSE_BYPASS), .PO_COARSE_DELAY (B_PO_COARSE_DELAY), .PO_OCLK_DELAY (B_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (B_OS_DATA_RATE), .OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_B( .mem_dq_out (mem_dq_out[23:12]), .mem_dq_ts (mem_dq_ts[23:12]), .mem_dq_in (mem_dq_in[19:10]), .mem_dqs_out (mem_dqs_out[1]), .mem_dqs_ts (mem_dqs_ts[1]), .mem_dqs_in (mem_dqs_in[1]), .rst (B_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (B_ddr_clk), .rclk (B_rclk), .pi_dqs_found (B_pi_dqs_found), .dqs_out_of_range (B_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (B_if_a_empty), .if_empty (B_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*B_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*B_of_empty*/), .of_a_full (B_of_a_full), .of_full (B_of_full), .pre_fifo_a_full (B_pre_fifo_a_full), .phy_din (phy_din_remap[159:80]), .phy_dout (phy_dout_remap[159:80]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (B_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (B_idelay_ce), .idelay_ld (B_idelay_ld), .pi_rst_dqs_find (B_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (B_po_fine_enable), .po_coarse_enable (B_po_coarse_enable), .po_fine_inc (B_po_fine_inc), .po_coarse_inc (B_po_coarse_inc), .po_counter_load_en (B_po_counter_load_en), .po_counter_read_en (B_po_counter_read_en), .po_counter_load_val (B_po_counter_load_val), .po_coarse_overflow (B_po_coarse_overflow), .po_fine_overflow (B_po_fine_overflow), .po_counter_read_val (B_po_counter_read_val), .po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (B_pi_fine_enable), .pi_fine_inc (B_pi_fine_inc), .pi_counter_load_en (B_pi_counter_load_en), .pi_counter_read_en (B_pi_counter_read_en), .pi_counter_load_val (B_pi_counter_load_val), .pi_fine_overflow (B_pi_fine_overflow), .pi_counter_read_val (B_pi_counter_read_val), .pi_iserdes_rst (B_pi_iserdes_rst), .pi_phase_locked (B_pi_phase_locked), .fine_delay (B_fine_delay), .fine_delay_sel (B_fine_delay_sel) ); end else begin : no_ddr_byte_lane_B assign B_of_a_full = 1'b0; assign B_of_full = 1'b0; assign B_pre_fifo_a_full = 1'b0; assign B_if_empty = 1'b0; assign B_if_a_empty = 1'b0; assign B_byte_rd_en = 1'b1; assign B_pi_phase_locked = 1; assign B_pi_dqs_found = 1; assign B_rclk = 0; assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign B_pi_counter_read_val = 0; assign B_po_counter_read_val = 0; assign B_pi_fine_overflow = 0; assign B_po_coarse_overflow = 0; assign B_po_fine_overflow = 0; end if ( BYTE_LANES[2] ) begin : ddr_byte_lane_C assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("C"), .PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[35:24]), .BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (C_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (C_PI_BURST_MODE), .PI_CLKOUT_DIV (C_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV), .PI_FINE_DELAY (C_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (C_PO_CLKOUT_DIV), .PO_FINE_DELAY (C_PO_FINE_DELAY), .PO_COARSE_BYPASS (C_PO_COARSE_BYPASS), .PO_COARSE_DELAY (C_PO_COARSE_DELAY), .PO_OCLK_DELAY (C_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (C_OS_DATA_RATE), .OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_C( .mem_dq_out (mem_dq_out[35:24]), .mem_dq_ts (mem_dq_ts[35:24]), .mem_dq_in (mem_dq_in[29:20]), .mem_dqs_out (mem_dqs_out[2]), .mem_dqs_ts (mem_dqs_ts[2]), .mem_dqs_in (mem_dqs_in[2]), .rst (C_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (C_ddr_clk), .rclk (C_rclk), .pi_dqs_found (C_pi_dqs_found), .dqs_out_of_range (C_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (C_if_a_empty), .if_empty (C_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*C_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*C_of_empty*/), .of_a_full (C_of_a_full), .of_full (C_of_full), .pre_fifo_a_full (C_pre_fifo_a_full), .phy_din (phy_din_remap[239:160]), .phy_dout (phy_dout_remap[239:160]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (C_byte_rd_en), // calibration signals .idelay_inc (idelay_inc), .idelay_ce (C_idelay_ce), .idelay_ld (C_idelay_ld), .pi_rst_dqs_find (C_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (C_po_fine_enable), .po_coarse_enable (C_po_coarse_enable), .po_fine_inc (C_po_fine_inc), .po_coarse_inc (C_po_coarse_inc), .po_counter_load_en (C_po_counter_load_en), .po_counter_read_en (C_po_counter_read_en), .po_counter_load_val (C_po_counter_load_val), .po_coarse_overflow (C_po_coarse_overflow), .po_fine_overflow (C_po_fine_overflow), .po_counter_read_val (C_po_counter_read_val), .po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (C_pi_fine_enable), .pi_fine_inc (C_pi_fine_inc), .pi_counter_load_en (C_pi_counter_load_en), .pi_counter_read_en (C_pi_counter_read_en), .pi_counter_load_val (C_pi_counter_load_val), .pi_fine_overflow (C_pi_fine_overflow), .pi_counter_read_val (C_pi_counter_read_val), .pi_iserdes_rst (C_pi_iserdes_rst), .pi_phase_locked (C_pi_phase_locked), .fine_delay (C_fine_delay), .fine_delay_sel (C_fine_delay_sel) ); end else begin : no_ddr_byte_lane_C assign C_of_a_full = 1'b0; assign C_of_full = 1'b0; assign C_pre_fifo_a_full = 1'b0; assign C_if_empty = 1'b0; assign C_byte_rd_en = 1'b1; assign C_if_a_empty = 1'b0; assign C_pi_phase_locked = 1; assign C_pi_dqs_found = 1; assign C_rclk = 0; assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign C_pi_counter_read_val = 0; assign C_po_counter_read_val = 0; assign C_pi_fine_overflow = 0; assign C_po_coarse_overflow = 0; assign C_po_fine_overflow = 0; end if ( BYTE_LANES[3] ) begin : ddr_byte_lane_D assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12])); mig_7series_v2_3_ddr_byte_lane # ( .ABCD ("D"), .PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"), .BITLANES (BITLANES[47:36]), .BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]), .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), //.OF_ARRAY_MODE (D_OF_ARRAY_MODE), //.IF_ARRAY_MODE (IF_ARRAY_MODE), .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .BYTELANES_DDR_CK (BYTELANES_DDR_CK), .RCLK_SELECT_LANE (RCLK_SELECT_LANE), .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), .SYNTHESIS (SYNTHESIS), .TCK (TCK), .PC_CLK_RATIO (PC_CLK_RATIO), .PI_BURST_MODE (D_PI_BURST_MODE), .PI_CLKOUT_DIV (D_PI_CLKOUT_DIV), .PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV), .PI_FINE_DELAY (D_PI_FINE_DELAY), .PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC), .PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST), .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), .PO_CLKOUT_DIV (D_PO_CLKOUT_DIV), .PO_FINE_DELAY (D_PO_FINE_DELAY), .PO_COARSE_BYPASS (D_PO_COARSE_BYPASS), .PO_COARSE_DELAY (D_PO_COARSE_DELAY), .PO_OCLK_DELAY (D_PO_OCLK_DELAY), .PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV), .PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC), .PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST), .OSERDES_DATA_RATE (D_OS_DATA_RATE), .OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH), .IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE), .IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE) ,.CKE_ODT_AUX (CKE_ODT_AUX) ) ddr_byte_lane_D( .mem_dq_out (mem_dq_out[47:36]), .mem_dq_ts (mem_dq_ts[47:36]), .mem_dq_in (mem_dq_in[39:30]), .mem_dqs_out (mem_dqs_out[3]), .mem_dqs_ts (mem_dqs_ts[3]), .mem_dqs_in (mem_dqs_in[3]), .rst (D_rst_primitives), .phy_clk (phy_clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), .idelayctrl_refclk (idelayctrl_refclk), .sync_pulse (sync_pulse), .ddr_ck_out (D_ddr_clk), .rclk (D_rclk), .pi_dqs_found (D_pi_dqs_found), .dqs_out_of_range (D_pi_dqs_out_of_range), .if_empty_def (if_empty_def), .if_a_empty (D_if_a_empty), .if_empty (D_if_empty), .if_a_full (/*if_a_full*/), .if_full (/*D_if_full*/), .of_a_empty (/*of_a_empty*/), .of_empty (/*D_of_empty*/), .of_a_full (D_of_a_full), .of_full (D_of_full), .pre_fifo_a_full (D_pre_fifo_a_full), .phy_din (phy_din_remap[319:240]), .phy_dout (phy_dout_remap[319:240]), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phaser_ctl_bus (phaser_ctl_bus), .idelay_inc (idelay_inc), .idelay_ce (D_idelay_ce), .idelay_ld (D_idelay_ld), .if_rst (if_rst), .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}), .byte_rd_en_oth_banks (byte_rd_en_oth_banks), .byte_rd_en (D_byte_rd_en), // calibration signals .pi_rst_dqs_find (D_pi_rst_dqs_find), .po_en_calib (phy_encalib), .po_fine_enable (D_po_fine_enable), .po_coarse_enable (D_po_coarse_enable), .po_fine_inc (D_po_fine_inc), .po_coarse_inc (D_po_coarse_inc), .po_counter_load_en (D_po_counter_load_en), .po_counter_read_en (D_po_counter_read_en), .po_counter_load_val (D_po_counter_load_val), .po_coarse_overflow (D_po_coarse_overflow), .po_fine_overflow (D_po_fine_overflow), .po_counter_read_val (D_po_counter_read_val), .po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay), .pi_en_calib (phy_encalib), .pi_fine_enable (D_pi_fine_enable), .pi_fine_inc (D_pi_fine_inc), .pi_counter_load_en (D_pi_counter_load_en), .pi_counter_read_en (D_pi_counter_read_en), .pi_counter_load_val (D_pi_counter_load_val), .pi_fine_overflow (D_pi_fine_overflow), .pi_counter_read_val (D_pi_counter_read_val), .pi_iserdes_rst (D_pi_iserdes_rst), .pi_phase_locked (D_pi_phase_locked), .fine_delay (D_fine_delay), .fine_delay_sel (D_fine_delay_sel) ); end else begin : no_ddr_byte_lane_D assign D_of_a_full = 1'b0; assign D_of_full = 1'b0; assign D_pre_fifo_a_full = 1'b0; assign D_if_empty = 1'b0; assign D_byte_rd_en = 1'b1; assign D_if_a_empty = 1'b0; assign D_rclk = 0; assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; assign D_pi_dqs_found = 1; assign D_pi_phase_locked = 1; assign D_pi_counter_read_val = 0; assign D_po_counter_read_val = 0; assign D_pi_fine_overflow = 0; assign D_po_coarse_overflow = 0; assign D_po_fine_overflow = 0; end endgenerate assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank; PHY_CONTROL #( .AO_WRLVL_EN ( PC_AO_WRLVL_EN), .AO_TOGGLE ( PC_AO_TOGGLE), .BURST_MODE ( PC_BURST_MODE), .CO_DURATION ( PC_CO_DURATION ), .CLK_RATIO ( PC_CLK_RATIO), .DATA_CTL_A_N ( PC_DATA_CTL_A), .DATA_CTL_B_N ( PC_DATA_CTL_B), .DATA_CTL_C_N ( PC_DATA_CTL_C), .DATA_CTL_D_N ( PC_DATA_CTL_D), .DI_DURATION ( PC_DI_DURATION ), .DO_DURATION ( PC_DO_DURATION ), .EVENTS_DELAY ( PC_EVENTS_DELAY), .FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS), .MULTI_REGION ( PC_MULTI_REGION ), .PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN), .DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH), .SYNC_MODE ( PC_SYNC_MODE), .CMD_OFFSET ( PC_CMD_OFFSET), .RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0), .RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1), .RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2), .RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3), .RD_DURATION_0 ( PC_RD_DURATION_0), .RD_DURATION_1 ( PC_RD_DURATION_1), .RD_DURATION_2 ( PC_RD_DURATION_2), .RD_DURATION_3 ( PC_RD_DURATION_3), .WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0), .WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1), .WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2), .WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3), .WR_DURATION_0 ( PC_WR_DURATION_0), .WR_DURATION_1 ( PC_WR_DURATION_1), .WR_DURATION_2 ( PC_WR_DURATION_2), .WR_DURATION_3 ( PC_WR_DURATION_3) ) phy_control_i ( .AUXOUTPUT (aux_out), .INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]), .INRANKA (in_rank[1:0]), .INRANKB (in_rank[3:2]), .INRANKC (in_rank[5:4]), .INRANKD (in_rank[7:6]), .OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]), .PCENABLECALIB (phy_encalib), .PHYCTLALMOSTFULL (phy_ctl_a_full), .PHYCTLEMPTY (phy_ctl_empty), .PHYCTLFULL (phy_ctl_full), .PHYCTLREADY (phy_ctl_ready), .MEMREFCLK (mem_refclk), .PHYCLK (phy_ctl_clk), .PHYCTLMSTREMPTY (phy_ctl_mstr_empty), .PHYCTLWD (_phy_ctl_wd), .PHYCTLWRENABLE (phy_ctl_wr), .PLLLOCK (pll_lock), .REFDLLLOCK (ref_dll_lock), // is reset while !locked .RESET (rst), .SYNCIN (sync_pulse), .READCALIBENABLE (phy_read_calib), .WRITECALIBENABLE (phy_write_calib) `ifdef USE_PHY_CONTROL_TEST , .TESTINPUT (16'b0), .TESTOUTPUT (test_output), .TESTSELECT (test_select), .SCANENABLEN (scan_enable) `endif ); // register outputs to give extra slack in timing always @(posedge phy_clk ) begin case (calib_sel[1:0]) 2'h0: begin po_coarse_overflow <= #1 A_po_coarse_overflow; po_fine_overflow <= #1 A_po_fine_overflow; po_counter_read_val <= #1 A_po_counter_read_val; pi_fine_overflow <= #1 A_pi_fine_overflow; pi_counter_read_val<= #1 A_pi_counter_read_val; pi_phase_locked <= #1 A_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 A_pi_dqs_found; pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range; end 2'h1: begin po_coarse_overflow <= #1 B_po_coarse_overflow; po_fine_overflow <= #1 B_po_fine_overflow; po_counter_read_val <= #1 B_po_counter_read_val; pi_fine_overflow <= #1 B_pi_fine_overflow; pi_counter_read_val <= #1 B_pi_counter_read_val; pi_phase_locked <= #1 B_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 B_pi_dqs_found; pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range; end 2'h2: begin po_coarse_overflow <= #1 C_po_coarse_overflow; po_fine_overflow <= #1 C_po_fine_overflow; po_counter_read_val <= #1 C_po_counter_read_val; pi_fine_overflow <= #1 C_pi_fine_overflow; pi_counter_read_val <= #1 C_pi_counter_read_val; pi_phase_locked <= #1 C_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 C_pi_dqs_found; pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range; end 2'h3: begin po_coarse_overflow <= #1 D_po_coarse_overflow; po_fine_overflow <= #1 D_po_fine_overflow; po_counter_read_val <= #1 D_po_counter_read_val; pi_fine_overflow <= #1 D_pi_fine_overflow; pi_counter_read_val <= #1 D_pi_counter_read_val; pi_phase_locked <= #1 D_pi_phase_locked; if ( calib_in_common) pi_dqs_found <= #1 pi_dqs_found_any; else pi_dqs_found <= #1 D_pi_dqs_found; pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range; end default: begin po_coarse_overflow <= po_coarse_overflow; end endcase end wire B_mux_ctrl; wire C_mux_ctrl; wire D_mux_ctrl; generate if (HIGHEST_LANE > 1) assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1])); else assign B_mux_ctrl = 0; if (HIGHEST_LANE > 2) assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2])); else assign C_mux_ctrl = 0; if (HIGHEST_LANE > 3) assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3])); else assign D_mux_ctrl = 0; endgenerate always @(*) begin A_pi_fine_enable = 0; A_pi_fine_inc = 0; A_pi_counter_load_en = 0; A_pi_counter_read_en = 0; A_pi_counter_load_val = 0; A_pi_rst_dqs_find = 0; A_po_fine_enable = 0; A_po_coarse_enable = 0; A_po_fine_inc = 0; A_po_coarse_inc = 0; A_po_counter_load_en = 0; A_po_counter_read_en = 0; A_po_counter_load_val = 0; A_po_sel_fine_oclk_delay = 0; A_idelay_ce = 0; A_idelay_ld = 0; A_fine_delay = 0; A_fine_delay_sel = 0; B_pi_fine_enable = 0; B_pi_fine_inc = 0; B_pi_counter_load_en = 0; B_pi_counter_read_en = 0; B_pi_counter_load_val = 0; B_pi_rst_dqs_find = 0; B_po_fine_enable = 0; B_po_coarse_enable = 0; B_po_fine_inc = 0; B_po_coarse_inc = 0; B_po_counter_load_en = 0; B_po_counter_read_en = 0; B_po_counter_load_val = 0; B_po_sel_fine_oclk_delay = 0; B_idelay_ce = 0; B_idelay_ld = 0; B_fine_delay = 0; B_fine_delay_sel = 0; C_pi_fine_enable = 0; C_pi_fine_inc = 0; C_pi_counter_load_en = 0; C_pi_counter_read_en = 0; C_pi_counter_load_val = 0; C_pi_rst_dqs_find = 0; C_po_fine_enable = 0; C_po_coarse_enable = 0; C_po_fine_inc = 0; C_po_coarse_inc = 0; C_po_counter_load_en = 0; C_po_counter_read_en = 0; C_po_counter_load_val = 0; C_po_sel_fine_oclk_delay = 0; C_idelay_ce = 0; C_idelay_ld = 0; C_fine_delay = 0; C_fine_delay_sel = 0; D_pi_fine_enable = 0; D_pi_fine_inc = 0; D_pi_counter_load_en = 0; D_pi_counter_read_en = 0; D_pi_counter_load_val = 0; D_pi_rst_dqs_find = 0; D_po_fine_enable = 0; D_po_coarse_enable = 0; D_po_fine_inc = 0; D_po_coarse_inc = 0; D_po_counter_load_en = 0; D_po_counter_read_en = 0; D_po_counter_load_val = 0; D_po_sel_fine_oclk_delay = 0; D_idelay_ce = 0; D_idelay_ld = 0; D_fine_delay = 0; D_fine_delay_sel = 0; if ( calib_sel[2]) begin // if this is asserted, all calib signals are deasserted A_pi_fine_enable = 0; A_pi_fine_inc = 0; A_pi_counter_load_en = 0; A_pi_counter_read_en = 0; A_pi_counter_load_val = 0; A_pi_rst_dqs_find = 0; A_po_fine_enable = 0; A_po_coarse_enable = 0; A_po_fine_inc = 0; A_po_coarse_inc = 0; A_po_counter_load_en = 0; A_po_counter_read_en = 0; A_po_counter_load_val = 0; A_po_sel_fine_oclk_delay = 0; A_idelay_ce = 0; A_idelay_ld = 0; A_fine_delay = 0; A_fine_delay_sel = 0; B_pi_fine_enable = 0; B_pi_fine_inc = 0; B_pi_counter_load_en = 0; B_pi_counter_read_en = 0; B_pi_counter_load_val = 0; B_pi_rst_dqs_find = 0; B_po_fine_enable = 0; B_po_coarse_enable = 0; B_po_fine_inc = 0; B_po_coarse_inc = 0; B_po_counter_load_en = 0; B_po_counter_read_en = 0; B_po_counter_load_val = 0; B_po_sel_fine_oclk_delay = 0; B_idelay_ce = 0; B_idelay_ld = 0; B_fine_delay = 0; B_fine_delay_sel = 0; C_pi_fine_enable = 0; C_pi_fine_inc = 0; C_pi_counter_load_en = 0; C_pi_counter_read_en = 0; C_pi_counter_load_val = 0; C_pi_rst_dqs_find = 0; C_po_fine_enable = 0; C_po_coarse_enable = 0; C_po_fine_inc = 0; C_po_coarse_inc = 0; C_po_counter_load_en = 0; C_po_counter_read_en = 0; C_po_counter_load_val = 0; C_po_sel_fine_oclk_delay = 0; C_idelay_ce = 0; C_idelay_ld = 0; C_fine_delay = 0; C_fine_delay_sel = 0; D_pi_fine_enable = 0; D_pi_fine_inc = 0; D_pi_counter_load_en = 0; D_pi_counter_read_en = 0; D_pi_counter_load_val = 0; D_pi_rst_dqs_find = 0; D_po_fine_enable = 0; D_po_coarse_enable = 0; D_po_fine_inc = 0; D_po_coarse_inc = 0; D_po_counter_load_en = 0; D_po_counter_read_en = 0; D_po_counter_load_val = 0; D_po_sel_fine_oclk_delay = 0; D_idelay_ce = 0; D_idelay_ld = 0; D_fine_delay = 0; D_fine_delay_sel = 0; end else if (calib_in_common) begin // if this is asserted, each signal is broadcast to all phasers // in common if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin A_pi_fine_enable = pi_fine_enable; A_pi_fine_inc = pi_fine_inc; A_pi_counter_load_en = pi_counter_load_en; A_pi_counter_read_en = pi_counter_read_en; A_pi_counter_load_val = pi_counter_load_val; A_pi_rst_dqs_find = pi_rst_dqs_find; A_po_fine_enable = po_fine_enable; A_po_coarse_enable = po_coarse_enable; A_po_fine_inc = po_fine_inc; A_po_coarse_inc = po_coarse_inc; A_po_counter_load_en = po_counter_load_en; A_po_counter_read_en = po_counter_read_en; A_po_counter_load_val = po_counter_load_val; A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; A_idelay_ce = idelay_ce; A_idelay_ld = idelay_ld; A_fine_delay = fine_delay ; A_fine_delay_sel = fine_delay_sel; end if ( B_mux_ctrl) begin B_pi_fine_enable = pi_fine_enable; B_pi_fine_inc = pi_fine_inc; B_pi_counter_load_en = pi_counter_load_en; B_pi_counter_read_en = pi_counter_read_en; B_pi_counter_load_val = pi_counter_load_val; B_pi_rst_dqs_find = pi_rst_dqs_find; B_po_fine_enable = po_fine_enable; B_po_coarse_enable = po_coarse_enable; B_po_fine_inc = po_fine_inc; B_po_coarse_inc = po_coarse_inc; B_po_counter_load_en = po_counter_load_en; B_po_counter_read_en = po_counter_read_en; B_po_counter_load_val = po_counter_load_val; B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; B_idelay_ce = idelay_ce; B_idelay_ld = idelay_ld; B_fine_delay = fine_delay ; B_fine_delay_sel = fine_delay_sel; end if ( C_mux_ctrl) begin C_pi_fine_enable = pi_fine_enable; C_pi_fine_inc = pi_fine_inc; C_pi_counter_load_en = pi_counter_load_en; C_pi_counter_read_en = pi_counter_read_en; C_pi_counter_load_val = pi_counter_load_val; C_pi_rst_dqs_find = pi_rst_dqs_find; C_po_fine_enable = po_fine_enable; C_po_coarse_enable = po_coarse_enable; C_po_fine_inc = po_fine_inc; C_po_coarse_inc = po_coarse_inc; C_po_counter_load_en = po_counter_load_en; C_po_counter_read_en = po_counter_read_en; C_po_counter_load_val = po_counter_load_val; C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; C_idelay_ce = idelay_ce; C_idelay_ld = idelay_ld; C_fine_delay = fine_delay ; C_fine_delay_sel = fine_delay_sel; end if ( D_mux_ctrl) begin D_pi_fine_enable = pi_fine_enable; D_pi_fine_inc = pi_fine_inc; D_pi_counter_load_en = pi_counter_load_en; D_pi_counter_read_en = pi_counter_read_en; D_pi_counter_load_val = pi_counter_load_val; D_pi_rst_dqs_find = pi_rst_dqs_find; D_po_fine_enable = po_fine_enable; D_po_coarse_enable = po_coarse_enable; D_po_fine_inc = po_fine_inc; D_po_coarse_inc = po_coarse_inc; D_po_counter_load_en = po_counter_load_en; D_po_counter_read_en = po_counter_read_en; D_po_counter_load_val = po_counter_load_val; D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; D_idelay_ce = idelay_ce; D_idelay_ld = idelay_ld; D_fine_delay = fine_delay ; D_fine_delay_sel = fine_delay_sel; end end else begin // otherwise, only a single phaser is selected case (calib_sel[1:0]) 0: begin A_pi_fine_enable = pi_fine_enable; A_pi_fine_inc = pi_fine_inc; A_pi_counter_load_en = pi_counter_load_en; A_pi_counter_read_en = pi_counter_read_en; A_pi_counter_load_val = pi_counter_load_val; A_pi_rst_dqs_find = pi_rst_dqs_find; A_po_fine_enable = po_fine_enable; A_po_coarse_enable = po_coarse_enable; A_po_fine_inc = po_fine_inc; A_po_coarse_inc = po_coarse_inc; A_po_counter_load_en = po_counter_load_en; A_po_counter_read_en = po_counter_read_en; A_po_counter_load_val = po_counter_load_val; A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; A_idelay_ce = idelay_ce; A_idelay_ld = idelay_ld; A_fine_delay = fine_delay ; A_fine_delay_sel = fine_delay_sel; end 1: begin B_pi_fine_enable = pi_fine_enable; B_pi_fine_inc = pi_fine_inc; B_pi_counter_load_en = pi_counter_load_en; B_pi_counter_read_en = pi_counter_read_en; B_pi_counter_load_val = pi_counter_load_val; B_pi_rst_dqs_find = pi_rst_dqs_find; B_po_fine_enable = po_fine_enable; B_po_coarse_enable = po_coarse_enable; B_po_fine_inc = po_fine_inc; B_po_coarse_inc = po_coarse_inc; B_po_counter_load_en = po_counter_load_en; B_po_counter_read_en = po_counter_read_en; B_po_counter_load_val = po_counter_load_val; B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; B_idelay_ce = idelay_ce; B_idelay_ld = idelay_ld; B_fine_delay = fine_delay ; B_fine_delay_sel = fine_delay_sel; end 2: begin C_pi_fine_enable = pi_fine_enable; C_pi_fine_inc = pi_fine_inc; C_pi_counter_load_en = pi_counter_load_en; C_pi_counter_read_en = pi_counter_read_en; C_pi_counter_load_val = pi_counter_load_val; C_pi_rst_dqs_find = pi_rst_dqs_find; C_po_fine_enable = po_fine_enable; C_po_coarse_enable = po_coarse_enable; C_po_fine_inc = po_fine_inc; C_po_coarse_inc = po_coarse_inc; C_po_counter_load_en = po_counter_load_en; C_po_counter_read_en = po_counter_read_en; C_po_counter_load_val = po_counter_load_val; C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; C_idelay_ce = idelay_ce; C_idelay_ld = idelay_ld; C_fine_delay = fine_delay ; C_fine_delay_sel = fine_delay_sel; end 3: begin D_pi_fine_enable = pi_fine_enable; D_pi_fine_inc = pi_fine_inc; D_pi_counter_load_en = pi_counter_load_en; D_pi_counter_read_en = pi_counter_read_en; D_pi_counter_load_val = pi_counter_load_val; D_pi_rst_dqs_find = pi_rst_dqs_find; D_po_fine_enable = po_fine_enable; D_po_coarse_enable = po_coarse_enable; D_po_fine_inc = po_fine_inc; D_po_coarse_inc = po_coarse_inc; D_po_counter_load_en = po_counter_load_en; D_po_counter_load_val = po_counter_load_val; D_po_counter_read_en = po_counter_read_en; D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; D_idelay_ce = idelay_ce; D_idelay_ld = idelay_ld; D_fine_delay = fine_delay ; D_fine_delay_sel = fine_delay_sel; end endcase end end //obligatory phaser-ref PHASER_REF phaser_ref_i( .LOCKED (ref_dll_lock), .CLKIN (freq_refclk), .PWRDWN (1'b0), .RST ( ! pll_lock) ); // optional idelay_ctrl generate if ( GENERATE_IDELAYCTRL == "TRUE") IDELAYCTRL idelayctrl ( .RDY (/*idelayctrl_rdy*/), .REFCLK (idelayctrl_refclk), .RST (rst) ); endgenerate endmodule
//***************************************************************************** // (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ddr_mc_phy_wrapper.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Oct 10 2010 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Wrapper file that encompasses the MC_PHY module // instantiation and handles the vector remapping between // the MC_PHY ports and the user's DDR3 ports. Vector // remapping affects DDR3 control, address, and DQ/DQS/DM. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_ddr_mc_phy_wrapper # ( parameter TCQ = 100, // Register delay (simulation only) parameter tCK = 2500, // ps parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank parameter BANK_WIDTH = 3, // # of bank address parameter CKE_WIDTH = 1, // # of clock enable outputs parameter CS_WIDTH = 1, // # of chip select parameter CK_WIDTH = 1, // # of CK parameter CWL = 5, // CAS Write latency parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter DM_WIDTH = 8, // # of data mask parameter DQ_WIDTH = 16, // # of data bits parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of strobe pairs parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3) parameter RANKS = 4, // # of ranks parameter ODT_WIDTH = 1, // # of ODT outputs parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter REG_CTRL = "OFF", // "ON" for registered DIMM parameter ROW_WIDTH = 16, // # of row/column address parameter USE_CS_PORT = 1, // Support chip select output parameter USE_DM_PORT = 1, // Support data mask output parameter USE_ODT_PORT = 1, // Support ODT output parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option parameter LP_DDR_CK_WIDTH = 2, // Hard PHY parameters parameter PHYCTL_CMD_FIFO = "FALSE", parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf, parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter PHY_0_BITLANES = 48'h0000_0000_0000, parameter PHY_1_BITLANES = 48'h0000_0000_0000, parameter PHY_2_BITLANES = 48'h0000_0000_0000, // Parameters calculated outside of this block parameter HIGHEST_BANK = 3, // Highest I/O bank index parameter HIGHEST_LANE = 12, // Highest byte lane index // ** Pin mapping parameters // Parameters for mapping between hard PHY and physical DDR3 signals // There are 2 classes of parameters: // - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of // 8-bit elements. Each element indicates the bank and byte lane // location of that particular signal. The bit lane in this case // doesn't need to be specified, either because there's only one // pin pair in each byte lane that the DQS or CK pair can be // located at, or in the case of CKE_ODT_BYTE_MAP, only the byte // lane needs to be specified in order to determine which byte // lane generates the RCLK (Note that CKE, and ODT must be located // in the same bank, thus only one element in CKE_ODT_BYTE_MAP) // [7:4] = bank # (0-4) // [3:0] = byte lane # (0-3) // - All other MAP parameters: These consist of 12-bit elements. Each // element indicates the bank, byte lane, and bit lane location of // that particular signal: // [11:8] = bank # (0-4) // [7:4] = byte lane # (0-3) // [3:0] = bit lane # (0-11) // Note that not all elements in all parameters will be used - it // depends on the actual widths of the DDR3 buses. The parameters are // structured to support a maximum of: // - DQS groups: 18 // - data mask bits: 18 // In addition, the default parameter size of some of the parameters will // support a certain number of bits, however, this can be expanded at // compile time by expanding the width of the vector passed into this // parameter // - chip selects: 10 // - bank bits: 3 // - address bits: 16 parameter CK_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter ADDR_MAP = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, parameter BANK_MAP = 36'h000_000_000, parameter CAS_MAP = 12'h000, parameter CKE_ODT_BYTE_MAP = 8'h00, parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000, parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000, parameter CKE_ODT_AUX = "FALSE", parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, parameter PARITY_MAP = 12'h000, parameter RAS_MAP = 12'h000, parameter WE_MAP = 12'h000, parameter DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, // DATAx_MAP parameter is used for byte lane X in the design parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, // MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9] parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, // Simulation options parameter SIM_CAL_OPTION = "NONE", // The PHY_CONTROL primitive in the bank where PLL exists is declared // as the Master PHY_CONTROL. parameter MASTER_PHY_CTL = 1, parameter DRAM_WIDTH = 8 ) ( input rst, input iddr_rst, input clk, input freq_refclk, input mem_refclk, input pll_lock, input sync_pulse, input mmcm_ps_clk, input idelayctrl_refclk, input phy_cmd_wr_en, input phy_data_wr_en, input [31:0] phy_ctl_wd, input phy_ctl_wr, input phy_if_empty_def, input phy_if_reset, input [5:0] data_offset_1, input [5:0] data_offset_2, input [3:0] aux_in_1, input [3:0] aux_in_2, output [4:0] idelaye2_init_val, output [5:0] oclkdelay_init_val, output if_empty, output phy_ctl_full, output phy_cmd_full, output phy_data_full, output phy_pre_data_a_full, output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk, output phy_mc_go, input phy_write_calib, input phy_read_calib, input calib_in_common, input [5:0] calib_sel, input [DQS_CNT_WIDTH:0] byte_sel_cnt, input [DRAM_WIDTH-1:0] fine_delay_incdec_pb, input fine_delay_sel, input [HIGHEST_BANK-1:0] calib_zero_inputs, input [HIGHEST_BANK-1:0] calib_zero_ctrl, input [2:0] po_fine_enable, input [2:0] po_coarse_enable, input [2:0] po_fine_inc, input [2:0] po_coarse_inc, input po_counter_load_en, input po_counter_read_en, input [2:0] po_sel_fine_oclk_delay, input [8:0] po_counter_load_val, output [8:0] po_counter_read_val, output [5:0] pi_counter_read_val, input [HIGHEST_BANK-1:0] pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input [5:0] pi_counter_load_val, input idelay_ce, input idelay_inc, input idelay_ld, input idle, output pi_phase_locked, output pi_phase_locked_all, output pi_dqs_found, output pi_dqs_found_all, output pi_dqs_out_of_range, // From/to calibration logic/soft PHY input phy_init_data_sel, input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address, input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank, input [nCK_PER_CLK-1:0] mux_cas_n, input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n, input [nCK_PER_CLK-1:0] mux_ras_n, input [1:0] mux_odt, input [nCK_PER_CLK-1:0] mux_cke, input [nCK_PER_CLK-1:0] mux_we_n, input [nCK_PER_CLK-1:0] parity_in, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata, input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask, input mux_reset_n, output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Memory I/F output [ROW_WIDTH-1:0] ddr_addr, output [BANK_WIDTH-1:0] ddr_ba, output ddr_cas_n, output [CKE_WIDTH-1:0] ddr_cke, output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, output [DM_WIDTH-1:0] ddr_dm, output [ODT_WIDTH-1:0] ddr_odt, output ddr_parity, output ddr_ras_n, output ddr_we_n, output ddr_reset_n, inout [DQ_WIDTH-1:0] ddr_dq, inout [DQS_WIDTH-1:0] ddr_dqs, inout [DQS_WIDTH-1:0] ddr_dqs_n, //output iodelay_ctrl_rdy, output pd_out ,input dbg_pi_counter_read_en ,output ref_dll_lock ,input rst_phaser_ref ,output [11:0] dbg_pi_phase_locked_phy4lanes ,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes ); function [71:0] generate_bytelanes_ddr_ck; input [143:0] ck_byte_map; integer v ; begin generate_bytelanes_ddr_ck = 'b0 ; for (v = 0; v < CK_WIDTH; v = v + 1) begin if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2) generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1) generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; else generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; end end endfunction function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map; input [143:0] ck_byte_map; integer g; begin generate_ddr_ck_map = 'b0 ; for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" : (ck_byte_map[(g*8)+:4] == 4'd1) ? "B" : (ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ; generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" : (ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location end end endfunction // Enable low power mode for input buffer localparam IBUF_LOW_PWR = (IBUF_LPWR_MODE == "OFF") ? "FALSE" : ((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL"); // Ratio of data to strobe localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH; // number of data phases per internal clock localparam PHASE_PER_CLK = 2*nCK_PER_CLK; // used to determine routing to OUT_FIFO for control/address for 2:1 // vs. 4:1 memory:internal clock ratio modes localparam PHASE_DIV = 4 / nCK_PER_CLK; localparam CLK_PERIOD = tCK * nCK_PER_CLK; // Create an aggregate parameters for data mapping to reduce # of generate // statements required in remapping code. Need to account for the case // when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP // parameter will have fewer than 8 elements used localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0], DATA16_MAP[12*DQ_PER_DQS-1:0], DATA15_MAP[12*DQ_PER_DQS-1:0], DATA14_MAP[12*DQ_PER_DQS-1:0], DATA13_MAP[12*DQ_PER_DQS-1:0], DATA12_MAP[12*DQ_PER_DQS-1:0], DATA11_MAP[12*DQ_PER_DQS-1:0], DATA10_MAP[12*DQ_PER_DQS-1:0], DATA9_MAP[12*DQ_PER_DQS-1:0], DATA8_MAP[12*DQ_PER_DQS-1:0], DATA7_MAP[12*DQ_PER_DQS-1:0], DATA6_MAP[12*DQ_PER_DQS-1:0], DATA5_MAP[12*DQ_PER_DQS-1:0], DATA4_MAP[12*DQ_PER_DQS-1:0], DATA3_MAP[12*DQ_PER_DQS-1:0], DATA2_MAP[12*DQ_PER_DQS-1:0], DATA1_MAP[12*DQ_PER_DQS-1:0], DATA0_MAP[12*DQ_PER_DQS-1:0]}; // Same deal, but for data mask mapping localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP}; localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ; localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ; // Temporary parameters to determine which bank is outputting the CK/CK# // Eventually there will be support for multiple CK/CK# output //localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]); //// Temporary method to force MC_PHY to generate ODDR associated with //// CK/CK# output only for a single byte lane in the design. All banks //// that won't be generating the CK/CK# will have "UNUSED" as their //// PHY_GENERATE_DDR_CK parameter //localparam TMP_PHY_0_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); //localparam TMP_PHY_1_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); //localparam TMP_PHY_2_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); // Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx // which indicates which bit lanes in data byte lanes are // output-only bitlanes (e.g. used specifically for data mask outputs) function [143:0] calc_phy_bitlanes_outonly; input [215:0] data_mask_in; integer z; begin calc_phy_bitlanes_outonly = 'b0; // Only enable BITLANES parameters for data masks if, well, if // the data masks are actually enabled if (USE_DM_PORT == 1) for (z = 0; z < DM_WIDTH; z = z + 1) calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] + 12*data_mask_in[(12*z+4)+:2] + data_mask_in[12*z+:4]] = 1'b1; end endfunction localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP); localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0]; localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48]; localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96]; // Determine which bank and byte lane generates the RCLK used to clock // out the auxilliary (ODT, CKE) outputs localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON = (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1)))); localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON = (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL"))); localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF = (CKE_MAP[11:8] == 4'h0) ? 0 : ((CKE_MAP[11:8] == 4'h1) ? 1 : ((CKE_MAP[11:8] == 4'h2) ? 2 : ((CKE_MAP[11:8] == 4'h3) ? 3 : ((CKE_MAP[11:8] == 4'h4) ? 4 : -1)))); localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF = (CKE_MAP[7:4] == 4'h0) ? "A" : ((CKE_MAP[7:4] == 4'h1) ? "B" : ((CKE_MAP[7:4] == 4'h2) ? "C" : ((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL"))); localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ; localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ; //*************************************************************************** // OCLKDELAYED tap setting calculation: // Parameters for calculating amount of phase shifting output clock to // achieve 90 degree offset between DQS and DQ on writes //*************************************************************************** //90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz // and 1.25 for Mem_RefClk > 300 MHz localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE"; //DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400, //DIV4: MemRefClk < 200 MHz localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" : tCK > 2500 ? "DIV2": "NONE"; localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 : PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1); // Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK; // Whether OCLK_DELAY output comes inverted or not localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0); // Phaser-Out Stage3 Tap delay for 90 deg shift. // Maximum tap delay is FreqRefClk period distributed over 64 taps // localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV; localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) - (INT_DELAY + HALF_CYCLE_DELAY)) * 63 * FREQ_REF_DIV; //localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY; localparam integer PHY_0_A_PO_OCLK_DELAY_HW = (tCK > 2273) ? 34 : (tCK > 2000) ? 33 : (tCK > 1724) ? 32 : (tCK > 1515) ? 31 : (tCK > 1315) ? 30 : (tCK > 1136) ? 29 : (tCK > 1021) ? 28 : 27; // Note that simulation requires a different value than in H/W because of the // difference in the way delays are modeled localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ? ((tCK > 2500) ? 8 : (DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) : MC_OCLK_DELAY; // Initial DQ IDELAY value localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 : (tCK < 1000) ? 0 : (tCK < 1330) ? 0 : (tCK < 2300) ? 0 : (tCK < 2500) ? 2 : 0; //localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0; // Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3? localparam PHY_0_RD_CMD_OFFSET_0 = 10; localparam PHY_0_RD_CMD_OFFSET_1 = 10; localparam PHY_0_RD_CMD_OFFSET_2 = 10; localparam PHY_0_RD_CMD_OFFSET_3 = 10; // 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4; // 4:1 and 2:1 have different values localparam PHY_0_WR_DURATION_0 = 7; localparam PHY_0_WR_DURATION_1 = 7; localparam PHY_0_WR_DURATION_2 = 7; localparam PHY_0_WR_DURATION_3 = 7; // Aux_out parameters for toggle mode (CKE) localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 : (CWL < 7) ? 4 + ((CWL_M % 2) ? 0 : 1) : 5 + ((CWL_M % 2) ? 0 : 1); // temporary parameter to enable/disable PHY PC counters. In both 4:1 and // 2:1 cases, this should be disabled. For now, enable for 4:1 mode to // avoid making too many changes at once. localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE"; wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out; wire [HIGHEST_LANE-1:0] mem_dqs_in; wire [HIGHEST_LANE-1:0] mem_dqs_out; wire [HIGHEST_LANE-1:0] mem_dqs_ts; wire [HIGHEST_LANE*10-1:0] mem_dq_in; wire [HIGHEST_LANE*12-1:0] mem_dq_out; wire [HIGHEST_LANE*12-1:0] mem_dq_ts; wire [DQ_WIDTH-1:0] in_dq; wire [DQS_WIDTH-1:0] in_dqs; wire [ROW_WIDTH-1:0] out_addr; wire [BANK_WIDTH-1:0] out_ba; wire out_cas_n; wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n; wire [DM_WIDTH-1:0] out_dm; wire [ODT_WIDTH -1:0] out_odt; wire [CKE_WIDTH -1 :0] out_cke ; wire [DQ_WIDTH-1:0] out_dq; wire [DQS_WIDTH-1:0] out_dqs; wire out_parity; wire out_ras_n; wire out_we_n; wire [HIGHEST_LANE*80-1:0] phy_din; wire [HIGHEST_LANE*80-1:0] phy_dout; wire phy_rd_en; wire [DM_WIDTH-1:0] ts_dm; wire [DQ_WIDTH-1:0] ts_dq; wire [DQS_WIDTH-1:0] ts_dqs; wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr; wire [DQS_WIDTH-1:0] pd_out_pre; //wire metaQ; reg [31:0] phy_ctl_wd_i1; reg [31:0] phy_ctl_wd_i2; reg phy_ctl_wr_i1; reg phy_ctl_wr_i2; reg [5:0] data_offset_1_i1; reg [5:0] data_offset_1_i2; reg [5:0] data_offset_2_i1; reg [5:0] data_offset_2_i2; wire [31:0] phy_ctl_wd_temp; wire phy_ctl_wr_temp; wire [5:0] data_offset_1_temp; wire [5:0] data_offset_2_temp; wire [5:0] data_offset_1_of; wire [5:0] data_offset_2_of; wire [31:0] phy_ctl_wd_of; wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */; wire [3:0] phy_ctl_full_temp; wire data_io_idle_pwrdwn; reg [29:0] fine_delay_mod; //3 bit per DQ reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb (* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1; // Always read from input data FIFOs when not empty assign phy_rd_en = !if_empty; // IDELAYE2 initial value assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE; assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY; // Idle powerdown when there are no pending reads in the MC assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0; //*************************************************************************** // Auxiliary output steering //*************************************************************************** // For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be // mapped to ddr_odt and the aux_out[7:4] from one of the data banks // will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the // addr/ctl bank would bank would map to both ddr_odt and ddr_cke. generate if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins if (CKE_WIDTH == 1) begin : gen_cke // Explicitly instantiate OBUF to ensure that these are present // in the netlist. Typically this is not required since NGDBUILD // at the top-level knows to infer an I/O/IOBUF and therefore a // top-level LOC constraint can be attached to that pin. This does // not work when a hierarchical flow is used and the LOC is applied // at the individual core-level UCF OBUF u_cke_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), .O (ddr_cke) ); end else begin: gen_2rank_cke OBUF u_cke0_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), .O (ddr_cke[0]) ); OBUF u_cke1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_cke[1]) ); end end endgenerate generate if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins if (USE_ODT_PORT == 1) begin : gen_use_odt // Explicitly instantiate OBUF to ensure that these are present // in the netlist. Typically this is not required since NGDBUILD // at the top-level knows to infer an I/O/IOBUF and therefore a // top-level LOC constraint can be attached to that pin. This does // not work when a hierarchical flow is used and the LOC is applied // at the individual core-level UCF OBUF u_odt_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]), .O (ddr_odt[0]) ); if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_odt[1]) ); end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), .O (ddr_odt[1]) ); end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_odt[1]) ); OBUF u_odt2_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), .O (ddr_odt[2]) ); end end else begin assign ddr_odt = 'b0; end end endgenerate //*************************************************************************** // Read data bit steering //*************************************************************************** // Transpose elements of rd_data_map to form final read data output: // phy_din elements are grouped according to "physical bit" - e.g. // for nCK_PER_CLK = 4, there are 8 data phases transfered per physical // bit per clock cycle: // = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2, // dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0} // whereas rd_data is are grouped according to "phase" - e.g. // = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0, // dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0} // therefore rd_data is formed by transposing phy_din - e.g. // for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY // bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then // the assignments for bits of rd_data corresponding to DQ[1:0] // would be: // {rd_data[112], rd_data[96], rd_data[80], rd_data[64], // rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0] // {rd_data[113], rd_data[97], rd_data[81], rd_data[65], // rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8] generate genvar i, j; for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1 for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2 assign rd_data[DQ_WIDTH*j + i] = phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+ 80*FULL_DATA_MAP[(12*i+4)+:2] + 8*FULL_DATA_MAP[12*i+:4]) + j]; end end endgenerate //generage idelay_inc per bits reg [11:0] cal_tmp; reg [95:0] byte_sel_data_map; assign byte_sel_cnt_w1 = byte_sel_cnt; always @ (posedge clk) begin byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96]; end always @ (posedge clk) begin fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00}; fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00}; fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00}; fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00}; fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00}; fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00}; fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00}; fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00}; fine_delay_sel_r <= #TCQ fine_delay_sel; end //*************************************************************************** // Control/address //*************************************************************************** assign out_cas_n = mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]]; generate // if signal placed on bit lanes [0-9] if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10 // Determine routing based on clock ratio mode. If running in 4:1 // mode, then all four bits from logic are used. If 2:1 mode, only // 2-bits are provided by logic, and each bit is repeated 2x to form // 4-bit input to IN_FIFO, e.g. // 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]} // 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]} assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + 8*CAS_MAP[3:0])+:4] = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; end else begin: gen_cas_ge10 // If signal is placed in bit lane [10] or [11], route to upper // nibble of phy_dout lane [5] or [6] respectively (in this case // phy_dout lane [5, 6] are multiplexed to take input for two // different SDR signals - this is how bits[10,11] need to be // provided to the OUT_FIFO assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + 8*(CAS_MAP[3:0]-5) + 4)+:4] = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; end endgenerate assign out_ras_n = mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]]; generate if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10 assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + 8*RAS_MAP[3:0])+:4] = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; end else begin: gen_ras_ge10 assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + 8*(RAS_MAP[3:0]-5) + 4)+:4] = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; end endgenerate assign out_we_n = mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]]; generate if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10 assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + 8*WE_MAP[3:0])+:4] = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], mux_we_n[1/PHASE_DIV], mux_we_n[0]}; end else begin: gen_we_ge10 assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + 8*(WE_MAP[3:0]-5) + 4)+:4] = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], mux_we_n[1/PHASE_DIV], mux_we_n[0]}; end endgenerate generate if (REG_CTRL == "ON") begin: gen_parity_out // Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs assign out_parity = mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] + PARITY_MAP[3:0]]; if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10 assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + 8*PARITY_MAP[3:0])+:4] = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], parity_in[1/PHASE_DIV], parity_in[0]}; end else begin: gen_ge10 assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + 8*(PARITY_MAP[3:0]-5) + 4)+:4] = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], parity_in[1/PHASE_DIV], parity_in[0]}; end end endgenerate //***************************************************************** generate genvar m, n,x; //***************************************************************** // Control/address (multi-bit) buses //***************************************************************** // Row/Column address for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out assign out_addr[m] = mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] + 12*ADDR_MAP[(12*m+4)+:2] + ADDR_MAP[12*m+:4]]; if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10 // For multi-bit buses, we also have to deal with transposition // when going from the logic-side control bus to phy_dout for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + 80*ADDR_MAP[(12*m+4)+:2] + 8*ADDR_MAP[12*m+:4] + n] = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + 80*ADDR_MAP[(12*m+4)+:2] + 8*(ADDR_MAP[12*m+:4]-5) + 4 + n] = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; end end end // Bank address for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out assign out_ba[m] = mem_dq_out[48*BANK_MAP[(12*m+8)+:3] + 12*BANK_MAP[(12*m+4)+:2] + BANK_MAP[12*m+:4]]; if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + 80*BANK_MAP[(12*m+4)+:2] + 8*BANK_MAP[12*m+:4] + n] = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + 80*BANK_MAP[(12*m+4)+:2] + 8*(BANK_MAP[12*m+:4]-5) + 4 + n] = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; end end end // Chip select if (USE_CS_PORT == 1) begin: gen_cs_n_out for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out assign out_cs_n[m] = mem_dq_out[48*CS_MAP[(12*m+8)+:3] + 12*CS_MAP[(12*m+4)+:2] + CS_MAP[12*m+:4]]; if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CS_MAP[(12*m+8)+:3] + 80*CS_MAP[(12*m+4)+:2] + 8*CS_MAP[12*m+:4] + n] = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CS_MAP[(12*m+8)+:3] + 80*CS_MAP[(12*m+4)+:2] + 8*(CS_MAP[12*m+:4]-5) + 4 + n] = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; end end end end if(CKE_ODT_AUX == "FALSE") begin // ODT_ports wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ; if(RANKS == 1) begin for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ; end end else begin for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ; assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ; end end if (USE_ODT_PORT == 1) begin: gen_odt_out for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1 assign out_odt[m] = mem_dq_out[48*ODT_MAP[(12*m+8)+:3] + 12*ODT_MAP[(12*m+4)+:2] + ODT_MAP[12*m+:4]]; if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + 80*ODT_MAP[(12*m+4)+:2] + 8*ODT_MAP[12*m+:4] + n] = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + 80*ODT_MAP[(12*m+4)+:2] + 8*(ODT_MAP[12*m+:4]-5) + 4 + n] = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; end end end end wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ; for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ; end for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out assign out_cke[m] = mem_dq_out[48*CKE_MAP[(12*m+8)+:3] + 12*CKE_MAP[(12*m+4)+:2] + CKE_MAP[12*m+:4]]; if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + 80*CKE_MAP[(12*m+4)+:2] + 8*CKE_MAP[12*m+:4] + n] = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + 80*CKE_MAP[(12*m+4)+:2] + 8*(CKE_MAP[12*m+:4]-5) + 4 + n] = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; end end end end //***************************************************************** // Data mask //***************************************************************** if (USE_DM_PORT == 1) begin: gen_dm_out for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out assign out_dm[m] = mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] + 12*FULL_MASK_MAP[(12*m+4)+:2] + FULL_MASK_MAP[12*m+:4]]; assign ts_dm[m] = mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] + 12*FULL_MASK_MAP[(12*m+4)+:2] + FULL_MASK_MAP[12*m+:4]]; for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] + 80*FULL_MASK_MAP[(12*m+4)+:2] + 8*FULL_MASK_MAP[12*m+:4] + n] = mux_wrdata_mask[DM_WIDTH*n + m]; end end end //***************************************************************** // Input and output DQ //***************************************************************** for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout // to MC_PHY assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] + 10*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]] = in_dq[m]; // to I/O buffers assign out_dq[m] = mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] + 12*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]]; assign ts_dq[m] = mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] + 12*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]]; for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] + 80*FULL_DATA_MAP[(12*m+4)+:2] + 8*FULL_DATA_MAP[12*m+:4] + n] = mux_wrdata[DQ_WIDTH*n + m]; end end //***************************************************************** // Input and output DQS //***************************************************************** for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout // to MC_PHY assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]] = in_dqs[m]; // to I/O buffers assign out_dqs[m] = mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; assign ts_dqs[m] = mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; end endgenerate assign pd_out = pd_out_pre[byte_sel_cnt_w1]; //*************************************************************************** // Memory I/F output and I/O buffer instantiation //*************************************************************************** // Note on instantiation - generally at the minimum, it's not required to // instantiate the output buffers - they can be inferred by the synthesis // tool, and there aren't any attributes that need to be associated with // them. Consider as a future option to take out the OBUF instantiations OBUF u_cas_n_obuf ( .I (out_cas_n), .O (ddr_cas_n) ); OBUF u_ras_n_obuf ( .I (out_ras_n), .O (ddr_ras_n) ); OBUF u_we_n_obuf ( .I (out_we_n), .O (ddr_we_n) ); generate genvar p; for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf OBUF u_addr_obuf ( .I (out_addr[p]), .O (ddr_addr[p]) ); end for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf OBUF u_bank_obuf ( .I (out_ba[p]), .O (ddr_ba[p]) ); end if (USE_CS_PORT == 1) begin: gen_cs_n_obuf for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf OBUF u_cs_n_obuf ( .I (out_cs_n[p]), .O (ddr_cs_n[p]) ); end end if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo if (USE_ODT_PORT== 1) begin: gen_odt_obuf for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf OBUF u_cs_n_obuf ( .I (out_odt[p]), .O (ddr_odt[p]) ); end end for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf OBUF u_cs_n_obuf ( .I (out_cke[p]), .O (ddr_cke[p]) ); end end if (REG_CTRL == "ON") begin: gen_parity_obuf // Generate addr/ctrl parity output only for DDR3 registered DIMMs OBUF u_parity_obuf ( .I (out_parity), .O (ddr_parity) ); end else begin: gen_parity_tieoff assign ddr_parity = 1'b0; end if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf // Generate reset output only for DDR3 and DDR2 RDIMMs OBUF u_reset_obuf ( .I (mux_reset_n), .O (ddr_reset_n) ); end else begin: gen_reset_tieoff assign ddr_reset_n = 1'b1; end if (USE_DM_PORT == 1) begin: gen_dm_obuf for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm OBUFT u_dm_obuf ( .I (out_dm[p]), .T (ts_dm[p]), .O (ddr_dm[p]) ); end end else begin: gen_dm_tieoff assign ddr_dm = 'b0; end if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end else begin: gen_dq_iobuf_default for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end //if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else if ((DRAM_TYPE == "DDR2") || (tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff IOBUFDS_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS_DIFF_OUT_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE"), .SIM_DEVICE ("7SERIES"), .USE_IBUFDISABLE ("FALSE") ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .TM (ts_dqs[p]), .TS (ts_dqs[p]), .OB (in_dqs_lpbk_to_iddr[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); mig_7series_v2_3_poc_pd # ( .TCQ (TCQ), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) ) u_iddr_edge_det ( .clk (clk), .iddr_rst (iddr_rst), .kclk (in_dqs_lpbk_to_iddr[p]), .mmcm_ps_clk (mmcm_ps_clk), .pd_out (pd_out_pre[p]) ); end end //end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else if ((DRAM_TYPE == "DDR2") || (tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff IOBUFDS_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS_DIFF_OUT_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE"), .SIM_DEVICE ("7SERIES"), .USE_IBUFDISABLE ("FALSE") ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), //.IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .TM (ts_dqs[p]), .TS (ts_dqs[p]), .OB (in_dqs_lpbk_to_iddr[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); mig_7series_v2_3_poc_pd # ( .TCQ (TCQ), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) ) u_iddr_edge_det ( .clk (clk), .iddr_rst (iddr_rst), .kclk (in_dqs_lpbk_to_iddr[p]), .mmcm_ps_clk (mmcm_ps_clk), .pd_out (pd_out_pre[p]) ); end end end else begin: gen_dqs_iobuf_default for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end end end endgenerate always @(posedge clk) begin phy_ctl_wd_i1 <= #TCQ phy_ctl_wd; phy_ctl_wr_i1 <= #TCQ phy_ctl_wr; phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1; phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1; data_offset_1_i1 <= #TCQ data_offset_1; data_offset_1_i2 <= #TCQ data_offset_1_i1; data_offset_2_i1 <= #TCQ data_offset_2; data_offset_2_i2 <= #TCQ data_offset_2_i1; end // 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it. // 2:1 mode the command goes through pre fifo assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of; assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of; assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of; assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of; generate begin mig_7series_v2_3_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (32) ) phy_ctl_pre_fifo_0 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[1]), .wr_en_in (phy_ctl_wr), .d_in (phy_ctl_wd), .wr_en_out (phy_ctl_wr_of), .d_out (phy_ctl_wd_of) ); mig_7series_v2_3_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (6) ) phy_ctl_pre_fifo_1 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[2]), .wr_en_in (phy_ctl_wr), .d_in (data_offset_1), .wr_en_out (), .d_out (data_offset_1_of) ); mig_7series_v2_3_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (6) ) phy_ctl_pre_fifo_2 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[3]), .wr_en_in (phy_ctl_wr), .d_in (data_offset_2), .wr_en_out (), .d_out (data_offset_2_of) ); end endgenerate //*************************************************************************** // Hard PHY instantiation //*************************************************************************** assign phy_ctl_full = phy_ctl_full_temp[0]; mig_7series_v2_3_ddr_mc_phy # ( .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .PHY_0_BITLANES (PHY_0_BITLANES), .PHY_1_BITLANES (PHY_1_BITLANES), .PHY_2_BITLANES (PHY_2_BITLANES), .PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY), .PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY), .PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY), .RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK), .RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE), //.CKE_ODT_AUX (CKE_ODT_AUX), .GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP), .BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK), .NUM_DDR_CK (CK_WIDTH), .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH), .PO_CTL_COARSE_BYPASS ("FALSE"), .PHYCTL_CMD_FIFO ("FALSE"), .PHY_CLK_RATIO (nCK_PER_CLK), .MASTER_PHY_CTL (MASTER_PHY_CTL), .PHY_FOUR_WINDOW_CLOCKS (63), .PHY_EVENTS_DELAY (18), .PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN .PHY_SYNC_MODE ("FALSE"), .SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"), .PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE" .PHY_0_GENERATE_IDELAYCTRL ("FALSE"), .PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV), .PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE .PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0), .PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1), .PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2), .PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3), .PHY_0_RD_DURATION_0 (6), .PHY_0_RD_DURATION_1 (6), .PHY_0_RD_DURATION_2 (6), .PHY_0_RD_DURATION_3 (6), .PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0), .PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1), .PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2), .PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3), .PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0), .PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1), .PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2), .PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3), .PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5), .PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV), .PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_GENERATE_IDELAYCTRL ("FALSE"), //.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK), //.PHY_1_NUM_DDR_CK (1), .PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_GENERATE_IDELAYCTRL ("FALSE"), //.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK), //.PHY_2_NUM_DDR_CK (1), .PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .TCK (tCK), .PHY_0_IODELAY_GRP (IODELAY_GRP), .PHY_1_IODELAY_GRP (IODELAY_GRP), .PHY_2_IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .CKE_ODT_AUX (CKE_ODT_AUX) ) u_ddr_mc_phy ( .rst (rst), // Don't use MC_PHY to generate DDR_RESET_N output. Instead // generate this output outside of MC_PHY (and synchronous to CLK) .ddr_rst_in_n (1'b1), .phy_clk (clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), // Remove later - always same connection as phy_clk port .mem_refclk_div4 (clk), .pll_lock (pll_lock), .auxout_clk (), .sync_pulse (sync_pulse), // IDELAYCTRL instantiated outside of mc_phy module .idelayctrl_refclk (), .phy_dout (phy_dout), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phy_ctl_wd (phy_ctl_wd_temp), .phy_ctl_wr (phy_ctl_wr_temp), .if_empty_def (phy_if_empty_def), .if_rst (phy_if_reset), .phyGo ('b1), .aux_in_1 (aux_in_1), .aux_in_2 (aux_in_2), // No support yet for different data offsets for different I/O banks // (possible use in supporting wider range of skew among bytes) .data_offset_1 (data_offset_1_temp), .data_offset_2 (data_offset_2_temp), .cke_in (), .if_a_empty (), .if_empty (if_empty), .if_empty_or (), .if_empty_and (), .of_ctl_a_full (), // .of_data_a_full (phy_data_full), .of_ctl_full (phy_cmd_full), .of_data_full (), .pre_data_a_full (phy_pre_data_a_full), .idelay_ld (idelay_ld), .idelay_ce (idelay_ce), .idelay_inc (idelay_inc), .input_sink (), .phy_din (phy_din), .phy_ctl_a_full (), .phy_ctl_full (phy_ctl_full_temp), .mem_dq_out (mem_dq_out), .mem_dq_ts (mem_dq_ts), .mem_dq_in (mem_dq_in), .mem_dqs_out (mem_dqs_out), .mem_dqs_ts (mem_dqs_ts), .mem_dqs_in (mem_dqs_in), .aux_out (aux_out), .phy_ctl_ready (), .rst_out (), .ddr_clk (ddr_clk), //.rclk (), .mcGo (phy_mc_go), .phy_write_calib (phy_write_calib), .phy_read_calib (phy_read_calib), .calib_sel (calib_sel), .calib_in_common (calib_in_common), .calib_zero_inputs (calib_zero_inputs), .calib_zero_ctrl (calib_zero_ctrl), .calib_zero_lanes ('b0), .po_fine_enable (po_fine_enable), .po_coarse_enable (po_coarse_enable), .po_fine_inc (po_fine_inc), .po_coarse_inc (po_coarse_inc), .po_counter_load_en (po_counter_load_en), .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay), .po_counter_load_val (po_counter_load_val), .po_counter_read_en (po_counter_read_en), .po_coarse_overflow (), .po_fine_overflow (), .po_counter_read_val (po_counter_read_val), .pi_rst_dqs_find (pi_rst_dqs_find), .pi_fine_enable (pi_fine_enable), .pi_fine_inc (pi_fine_inc), .pi_counter_load_en (pi_counter_load_en), .pi_counter_read_en (dbg_pi_counter_read_en), .pi_counter_load_val (pi_counter_load_val), .pi_fine_overflow (), .pi_counter_read_val (pi_counter_read_val), .pi_phase_locked (pi_phase_locked), .pi_phase_locked_all (pi_phase_locked_all), .pi_dqs_found (), .pi_dqs_found_any (pi_dqs_found), .pi_dqs_found_all (pi_dqs_found_all), .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes), // Currently not being used. May be used in future if periodic // reads become a requirement. This output could be used to signal // a catastrophic failure in read capture and the need for // re-calibration. .pi_dqs_out_of_range (pi_dqs_out_of_range) ,.ref_dll_lock (ref_dll_lock) ,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes) ,.fine_delay (fine_delay_mod) ,.fine_delay_sel (fine_delay_sel_r) // ,.rst_phaser_ref (rst_phaser_ref) ); endmodule
//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_wrcal.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Write calibration logic to align DQS to correct CK edge //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ **$Date: 2011/06/02 08:35:09 $ **$Author: **$Revision: **$Source: ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_wrcal # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter CLK_PERIOD = 2500, parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly parameter SIM_CAL_OPTION = "NONE" // Skip various calibration steps ) ( input clk, input rst, // Calibration status, control signals input wrcal_start, input wrcal_rd_wait, input wrcal_sanity_chk, input dqsfound_retry_done, input phy_rddata_en, output dqsfound_retry, output wrcal_read_req, output reg wrcal_act_req, output reg wrcal_done, output reg wrcal_pat_err, output reg wrcal_prech_req, output reg temp_wrcal_done, output reg wrcal_sanity_chk_done, input prech_done, // Captured data in resync clock domain input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Write level values of Phaser_Out coarse and fine // delay taps required to load Phaser_Out register input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt, input [6*DQS_WIDTH-1:0] wl_po_fine_cnt, input wrlvl_byte_done, output reg wrlvl_byte_redo, output reg early1_data, output reg early2_data, // DQ IDELAY output reg idelay_ld, output reg wrcal_pat_resume, // to phy_init for write output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt, output phy_if_reset, // Debug Port output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, output [99:0] dbg_phy_wrcal ); // Length of calibration sequence (in # of words) //localparam CAL_PAT_LEN = 8; // Read data shift register length localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2; // # of reads for reliable read capture localparam NUM_READS = 2; // # of cycles to wait after changing RDEN count value localparam RDEN_WAIT_CNT = 12; localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6; localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44; localparam CAL2_IDLE = 4'h0; localparam CAL2_READ_WAIT = 4'h1; localparam CAL2_NEXT_DQS = 4'h2; localparam CAL2_WRLVL_WAIT = 4'h3; localparam CAL2_IFIFO_RESET = 4'h4; localparam CAL2_DQ_IDEL_DEC = 4'h5; localparam CAL2_DONE = 4'h6; localparam CAL2_SANITY_WAIT = 4'h7; localparam CAL2_ERR = 4'h8; integer i,j,k,l,m,p,q,d; reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1]; reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w; reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1]; reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w; reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */; reg [4:0] not_empty_wait_cnt; reg [3:0] tap_inc_wait_cnt; reg cal2_done_r; reg cal2_done_r1; reg cal2_prech_req_r; reg [3:0] cal2_state_r; reg [3:0] cal2_state_r1; reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1]; reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1]; reg cal2_if_reset; reg wrcal_pat_resume_r; reg wrcal_pat_resume_r1; reg wrcal_pat_resume_r2; reg wrcal_pat_resume_r3; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r; reg pat_data_match_r; reg pat1_data_match_r; reg pat1_data_match_r1; reg pat2_data_match_r; reg pat_data_match_valid_r; wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0]; reg [DRAM_WIDTH-1:0] pat_match_fall0_r; reg pat_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall1_r; reg pat_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall2_r; reg pat_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall3_r; reg pat_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise0_r; reg pat_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise1_r; reg pat_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise2_r; reg pat_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise3_r; reg pat_match_rise3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise0_r; reg [DRAM_WIDTH-1:0] pat1_match_rise1_r; reg [DRAM_WIDTH-1:0] pat1_match_fall0_r; reg [DRAM_WIDTH-1:0] pat1_match_fall1_r; reg [DRAM_WIDTH-1:0] pat2_match_rise0_r; reg [DRAM_WIDTH-1:0] pat2_match_rise1_r; reg [DRAM_WIDTH-1:0] pat2_match_fall0_r; reg [DRAM_WIDTH-1:0] pat2_match_fall1_r; reg pat1_match_rise0_and_r; reg pat1_match_rise1_and_r; reg pat1_match_fall0_and_r; reg pat1_match_fall1_and_r; reg pat2_match_rise0_and_r; reg pat2_match_rise1_and_r; reg pat2_match_fall0_and_r; reg pat2_match_fall1_and_r; reg early1_data_match_r; reg early1_data_match_r1; reg [DRAM_WIDTH-1:0] early1_match_fall0_r; reg early1_match_fall0_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall1_r; reg early1_match_fall1_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall2_r; reg early1_match_fall2_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall3_r; reg early1_match_fall3_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise0_r; reg early1_match_rise0_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise1_r; reg early1_match_rise1_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise2_r; reg early1_match_rise2_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise3_r; reg early1_match_rise3_and_r; reg early2_data_match_r; reg [DRAM_WIDTH-1:0] early2_match_fall0_r; reg early2_match_fall0_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall1_r; reg early2_match_fall1_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall2_r; reg early2_match_fall2_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall3_r; reg early2_match_fall3_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise0_r; reg early2_match_rise0_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise1_r; reg early2_match_rise1_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise2_r; reg early2_match_rise2_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise3_r; reg early2_match_rise3_and_r; wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0]; wire [DQ_WIDTH-1:0] rd_data_rise0; wire [DQ_WIDTH-1:0] rd_data_fall0; wire [DQ_WIDTH-1:0] rd_data_rise1; wire [DQ_WIDTH-1:0] rd_data_fall1; wire [DQ_WIDTH-1:0] rd_data_rise2; wire [DQ_WIDTH-1:0] rd_data_fall2; wire [DQ_WIDTH-1:0] rd_data_rise3; wire [DQ_WIDTH-1:0] rd_data_fall3; reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; reg rd_active_posedge_r; reg rd_active_r; reg rd_active_r1; reg rd_active_r2; reg rd_active_r3; reg rd_active_r4; reg rd_active_r5; reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0]; reg wrlvl_byte_done_r; reg idelay_ld_done; reg pat1_detect; reg early1_detect; reg wrcal_sanity_chk_r; reg wrcal_sanity_chk_err; //*************************************************************************** // Debug //*************************************************************************** always @(*) begin for (d = 0; d < DQS_WIDTH; d = d + 1) begin po_fine_tap_cnt_w[(6*d)+:6] = po_fine_tap_cnt[d]; po_coarse_tap_cnt_w[(3*d)+:3] = po_coarse_tap_cnt[d]; end end assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w; assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w; assign dbg_phy_wrcal[0] = pat_data_match_r; assign dbg_phy_wrcal[4:1] = cal2_state_r1[3:0]; assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err; assign dbg_phy_wrcal[6] = wrcal_start; assign dbg_phy_wrcal[7] = wrcal_done; assign dbg_phy_wrcal[8] = pat_data_match_valid_r; assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r; assign dbg_phy_wrcal[17+:5] = not_empty_wait_cnt; assign dbg_phy_wrcal[22] = early1_data; assign dbg_phy_wrcal[23] = early2_data; assign dbg_phy_wrcal[24+:8] = mux_rd_rise0_r; assign dbg_phy_wrcal[32+:8] = mux_rd_fall0_r; assign dbg_phy_wrcal[40+:8] = mux_rd_rise1_r; assign dbg_phy_wrcal[48+:8] = mux_rd_fall1_r; assign dbg_phy_wrcal[56+:8] = mux_rd_rise2_r; assign dbg_phy_wrcal[64+:8] = mux_rd_fall2_r; assign dbg_phy_wrcal[72+:8] = mux_rd_rise3_r; assign dbg_phy_wrcal[80+:8] = mux_rd_fall3_r; assign dbg_phy_wrcal[88] = early1_data_match_r; assign dbg_phy_wrcal[89] = early2_data_match_r; assign dbg_phy_wrcal[90] = wrcal_sanity_chk_r & pat_data_match_valid_r; assign dbg_phy_wrcal[91] = wrcal_sanity_chk_r; assign dbg_phy_wrcal[92] = wrcal_sanity_chk_done; assign dqsfound_retry = 1'b0; assign wrcal_read_req = 1'b0; assign phy_if_reset = cal2_if_reset; //************************************************************************** // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 // coarse delay //************************************************************************** always @(posedge clk) begin po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r; wrlvl_byte_done_r <= #TCQ wrlvl_byte_done; wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk; end //*************************************************************************** // Data mux to route appropriate byte to calibration logic - i.e. calibration // is done sequentially, one byte (or DQS group) at a time //*************************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_rd_data_div4 assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2 assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; end endgenerate //************************************************************************** // Final Phaser OUT coarse and fine delay taps after write calibration // Sum of taps used during write leveling taps and write calibration //************************************************************************** always @(*) begin for (m = 0; m < DQS_WIDTH; m = m + 1) begin wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3]; wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6]; end end always @(posedge clk) begin if (rst) begin for (p = 0; p < DQS_WIDTH; p = p + 1) begin po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}}; po_fine_tap_cnt[p] <= #TCQ {6{1'b0}}; end end else if (cal2_done_r && ~cal2_done_r1) begin for (q = 0; q < DQS_WIDTH; q = q + 1) begin po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i]; po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i]; end end end always @(posedge clk) begin rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r; end // Register outputs for improved timing. // NOTE: Will need to change when per-bit DQ deskew is supported. // Currenly all bits in DQS group are checked in aggregate generate genvar mux_i; if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4 for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2 for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end end endgenerate //*************************************************************************** // generate request to PHY_INIT logic to issue precharged. Required when // calibration can take a long time (during which there are only constant // reads present on this bus). In this case need to issue perioidic // precharges to avoid tRAS violation. This signal must meet the following // requirements: (1) only transition from 0->1 when prech is first needed, // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted //*************************************************************************** always @(posedge clk) if (rst) wrcal_prech_req <= #TCQ 1'b0; else // Combine requests from all stages here wrcal_prech_req <= #TCQ cal2_prech_req_r; //*************************************************************************** // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES // NOTE: Written using discrete flops, but SRL can be used if the matching // logic does the comparison sequentially, rather than parallel //*************************************************************************** generate genvar rd_i; if (nCK_PER_CLK == 4) begin: gen_sr_div4 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i]; sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i]; sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i]; sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i]; end end end else if (nCK_PER_CLK == 2) begin: gen_sr_div2 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; end end end endgenerate //*************************************************************************** // Write calibration: // During write leveling DQS is aligned to the nearest CK edge that may not // be the correct CK edge. Write calibration is required to align the DQS to // the correct CK edge that clocks the write command. // The Phaser_Out coarse delay line is adjusted if required to add a memory // clock cycle of delay in order to read back the expected pattern. //*************************************************************************** always @(posedge clk) begin rd_active_r <= #TCQ phy_rddata_en; rd_active_r1 <= #TCQ rd_active_r; rd_active_r2 <= #TCQ rd_active_r1; rd_active_r3 <= #TCQ rd_active_r2; rd_active_r4 <= #TCQ rd_active_r3; rd_active_r5 <= #TCQ rd_active_r4; end //***************************************************************** // Expected data pattern when properly received by read capture // logic: // Based on pattern of ({rise,fall}) = // 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 // Each nibble will look like: // bit3: 1, 0, 1, 0, 0, 1, 1, 0 // bit2: 1, 0, 0, 1, 1, 0, 0, 1 // bit1: 1, 0, 1, 0, 0, 1, 0, 1 // bit0: 1, 0, 0, 1, 1, 0, 1, 0 // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN // and the actual training pattern contents change //***************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_pat_div4 // FF00AA5555AA9966 assign pat_rise0[3] = 1'b1; assign pat_fall0[3] = 1'b0; assign pat_rise1[3] = 1'b1; assign pat_fall1[3] = 1'b0; assign pat_rise2[3] = 1'b0; assign pat_fall2[3] = 1'b1; assign pat_rise3[3] = 1'b1; assign pat_fall3[3] = 1'b0; assign pat_rise0[2] = 1'b1; assign pat_fall0[2] = 1'b0; assign pat_rise1[2] = 1'b0; assign pat_fall1[2] = 1'b1; assign pat_rise2[2] = 1'b1; assign pat_fall2[2] = 1'b0; assign pat_rise3[2] = 1'b0; assign pat_fall3[2] = 1'b1; assign pat_rise0[1] = 1'b1; assign pat_fall0[1] = 1'b0; assign pat_rise1[1] = 1'b1; assign pat_fall1[1] = 1'b0; assign pat_rise2[1] = 1'b0; assign pat_fall2[1] = 1'b1; assign pat_rise3[1] = 1'b0; assign pat_fall3[1] = 1'b1; assign pat_rise0[0] = 1'b1; assign pat_fall0[0] = 1'b0; assign pat_rise1[0] = 1'b0; assign pat_fall1[0] = 1'b1; assign pat_rise2[0] = 1'b1; assign pat_fall2[0] = 1'b0; assign pat_rise3[0] = 1'b1; assign pat_fall3[0] = 1'b0; // Pattern to distinguish between early write and incorrect read // BB11EE4444EEDD88 assign early_rise0[3] = 1'b1; assign early_fall0[3] = 1'b0; assign early_rise1[3] = 1'b1; assign early_fall1[3] = 1'b0; assign early_rise2[3] = 1'b0; assign early_fall2[3] = 1'b1; assign early_rise3[3] = 1'b1; assign early_fall3[3] = 1'b1; assign early_rise0[2] = 1'b0; assign early_fall0[2] = 1'b0; assign early_rise1[2] = 1'b1; assign early_fall1[2] = 1'b1; assign early_rise2[2] = 1'b1; assign early_fall2[2] = 1'b1; assign early_rise3[2] = 1'b1; assign early_fall3[2] = 1'b0; assign early_rise0[1] = 1'b1; assign early_fall0[1] = 1'b0; assign early_rise1[1] = 1'b1; assign early_fall1[1] = 1'b0; assign early_rise2[1] = 1'b0; assign early_fall2[1] = 1'b1; assign early_rise3[1] = 1'b0; assign early_fall3[1] = 1'b0; assign early_rise0[0] = 1'b1; assign early_fall0[0] = 1'b1; assign early_rise1[0] = 1'b0; assign early_fall1[0] = 1'b0; assign early_rise2[0] = 1'b0; assign early_fall2[0] = 1'b0; assign early_rise3[0] = 1'b1; assign early_fall3[0] = 1'b0; end else if (nCK_PER_CLK == 2) begin: gen_pat_div2 // First cycle pattern FF00AA55 assign pat1_rise0[3] = 1'b1; assign pat1_fall0[3] = 1'b0; assign pat1_rise1[3] = 1'b1; assign pat1_fall1[3] = 1'b0; assign pat1_rise0[2] = 1'b1; assign pat1_fall0[2] = 1'b0; assign pat1_rise1[2] = 1'b0; assign pat1_fall1[2] = 1'b1; assign pat1_rise0[1] = 1'b1; assign pat1_fall0[1] = 1'b0; assign pat1_rise1[1] = 1'b1; assign pat1_fall1[1] = 1'b0; assign pat1_rise0[0] = 1'b1; assign pat1_fall0[0] = 1'b0; assign pat1_rise1[0] = 1'b0; assign pat1_fall1[0] = 1'b1; // Second cycle pattern 55AA9966 assign pat2_rise0[3] = 1'b0; assign pat2_fall0[3] = 1'b1; assign pat2_rise1[3] = 1'b1; assign pat2_fall1[3] = 1'b0; assign pat2_rise0[2] = 1'b1; assign pat2_fall0[2] = 1'b0; assign pat2_rise1[2] = 1'b0; assign pat2_fall1[2] = 1'b1; assign pat2_rise0[1] = 1'b0; assign pat2_fall0[1] = 1'b1; assign pat2_rise1[1] = 1'b0; assign pat2_fall1[1] = 1'b1; assign pat2_rise0[0] = 1'b1; assign pat2_fall0[0] = 1'b0; assign pat2_rise1[0] = 1'b1; assign pat2_fall1[0] = 1'b0; //Pattern to distinguish between early write and incorrect read // First cycle pattern AA5555AA assign early1_rise0[3] = 2'b1; assign early1_fall0[3] = 2'b0; assign early1_rise1[3] = 2'b0; assign early1_fall1[3] = 2'b1; assign early1_rise0[2] = 2'b0; assign early1_fall0[2] = 2'b1; assign early1_rise1[2] = 2'b1; assign early1_fall1[2] = 2'b0; assign early1_rise0[1] = 2'b1; assign early1_fall0[1] = 2'b0; assign early1_rise1[1] = 2'b0; assign early1_fall1[1] = 2'b1; assign early1_rise0[0] = 2'b0; assign early1_fall0[0] = 2'b1; assign early1_rise1[0] = 2'b1; assign early1_fall1[0] = 2'b0; // Second cycle pattern 9966BB11 assign early2_rise0[3] = 2'b1; assign early2_fall0[3] = 2'b0; assign early2_rise1[3] = 2'b1; assign early2_fall1[3] = 2'b0; assign early2_rise0[2] = 2'b0; assign early2_fall0[2] = 2'b1; assign early2_rise1[2] = 2'b0; assign early2_fall1[2] = 2'b0; assign early2_rise0[1] = 2'b0; assign early2_fall0[1] = 2'b1; assign early2_rise1[1] = 2'b1; assign early2_fall1[1] = 2'b0; assign early2_rise0[0] = 2'b1; assign early2_fall0[0] = 2'b0; assign early2_rise1[0] = 2'b1; assign early2_fall1[0] = 2'b1; end endgenerate // Each bit of each byte is compared to expected pattern. // This was done to prevent (and "drastically decrease") the chance that // invalid data clocked in when the DQ bus is tri-state (along with a // combination of the correct data) will resemble the expected data // pattern. A better fix for this is to change the training pattern and/or // make the pattern longer. generate genvar pt_i; if (nCK_PER_CLK == 4) begin: gen_pat_match_div4 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4]) pat_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4]) pat_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4]) pat_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4]) pat_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4]) pat_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4]) pat_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4]) pat_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4]) pat_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4]) early1_match_rise0_r[pt_i] <= #TCQ 1'b1; else early1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4]) early1_match_fall0_r[pt_i] <= #TCQ 1'b1; else early1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4]) early1_match_rise1_r[pt_i] <= #TCQ 1'b1; else early1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4]) early1_match_fall1_r[pt_i] <= #TCQ 1'b1; else early1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4]) early1_match_rise2_r[pt_i] <= #TCQ 1'b1; else early1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4]) early1_match_fall2_r[pt_i] <= #TCQ 1'b1; else early1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == early_rise0[pt_i%4]) early1_match_rise3_r[pt_i] <= #TCQ 1'b1; else early1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == early_fall0[pt_i%4]) early1_match_fall3_r[pt_i] <= #TCQ 1'b1; else early1_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4]) early2_match_rise0_r[pt_i] <= #TCQ 1'b1; else early2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4]) early2_match_fall0_r[pt_i] <= #TCQ 1'b1; else early2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4]) early2_match_rise1_r[pt_i] <= #TCQ 1'b1; else early2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4]) early2_match_fall1_r[pt_i] <= #TCQ 1'b1; else early2_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == early_rise0[pt_i%4]) early2_match_rise2_r[pt_i] <= #TCQ 1'b1; else early2_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == early_fall0[pt_i%4]) early2_match_fall2_r[pt_i] <= #TCQ 1'b1; else early2_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == early_rise1[pt_i%4]) early2_match_rise3_r[pt_i] <= #TCQ 1'b1; else early2_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == early_fall1[pt_i%4]) early2_match_fall3_r[pt_i] <= #TCQ 1'b1; else early2_match_fall3_r[pt_i] <= #TCQ 1'b0; end end always @(posedge clk) begin pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r; pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r; pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r; pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r; pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r; pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r; pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r; pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r; pat_data_match_r <= #TCQ (pat_match_rise0_and_r && pat_match_fall0_and_r && pat_match_rise1_and_r && pat_match_fall1_and_r && pat_match_rise2_and_r && pat_match_fall2_and_r && pat_match_rise3_and_r && pat_match_fall3_and_r); pat_data_match_valid_r <= #TCQ rd_active_r3; end always @(posedge clk) begin early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r; early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r; early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r; early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r; early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r; early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r; early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r; early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r; early1_data_match_r <= #TCQ (early1_match_rise0_and_r && early1_match_fall0_and_r && early1_match_rise1_and_r && early1_match_fall1_and_r && early1_match_rise2_and_r && early1_match_fall2_and_r && early1_match_rise3_and_r && early1_match_fall3_and_r); end always @(posedge clk) begin early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r; early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r; early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r; early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r; early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r; early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r; early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r; early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r; early2_data_match_r <= #TCQ (early2_match_rise0_and_r && early2_match_fall0_and_r && early2_match_rise1_and_r && early2_match_fall1_and_r && early2_match_rise2_and_r && early2_match_fall2_and_r && early2_match_rise3_and_r && early2_match_fall3_and_r); end end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4]) pat2_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4]) pat2_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4]) pat2_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4]) pat2_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat2_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4]) early1_match_rise0_r[pt_i] <= #TCQ 1'b1; else early1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4]) early1_match_fall0_r[pt_i] <= #TCQ 1'b1; else early1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4]) early1_match_rise1_r[pt_i] <= #TCQ 1'b1; else early1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4]) early1_match_fall1_r[pt_i] <= #TCQ 1'b1; else early1_match_fall1_r[pt_i] <= #TCQ 1'b0; end // early2 in this case does not mean 2 cycles early but // the second cycle of read data in 2:1 mode always @(posedge clk) begin if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4]) early2_match_rise0_r[pt_i] <= #TCQ 1'b1; else early2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4]) early2_match_fall0_r[pt_i] <= #TCQ 1'b1; else early2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4]) early2_match_rise1_r[pt_i] <= #TCQ 1'b1; else early2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4]) early2_match_fall1_r[pt_i] <= #TCQ 1'b1; else early2_match_fall1_r[pt_i] <= #TCQ 1'b0; end end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r); pat1_data_match_r1 <= #TCQ pat1_data_match_r; pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3; pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3; pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3; pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3; pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r && pat2_match_fall0_and_r && pat2_match_rise1_and_r && pat2_match_fall1_and_r); // For 2:1 mode, read valid is asserted for 2 clock cycles - // here we generate a "match valid" pulse that is only 1 clock // cycle wide that is simulatenous when the match calculation // is complete pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5; end always @(posedge clk) begin early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r; early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r; early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r; early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r; early1_data_match_r <= #TCQ (early1_match_rise0_and_r && early1_match_fall0_and_r && early1_match_rise1_and_r && early1_match_fall1_and_r); early1_data_match_r1 <= #TCQ early1_data_match_r; early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3; early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3; early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3; early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3; early2_data_match_r <= #TCQ (early2_match_rise0_and_r && early2_match_fall0_and_r && early2_match_rise1_and_r && early2_match_fall1_and_r); end end endgenerate // Need to delay it by 3 cycles in order to wait for Phaser_Out // coarse delay to take effect before issuing a write command always @(posedge clk) begin wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r; wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1; wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2; end always @(posedge clk) begin if (rst) tap_inc_wait_cnt <= #TCQ 'd0; else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) || (cal2_state_r == CAL2_IFIFO_RESET) || (cal2_state_r == CAL2_SANITY_WAIT)) tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1; else tap_inc_wait_cnt <= #TCQ 'd0; end always @(posedge clk) begin if (rst) not_empty_wait_cnt <= #TCQ 'd0; else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait) not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1; else not_empty_wait_cnt <= #TCQ 'd0; end always @(posedge clk) cal2_state_r1 <= #TCQ cal2_state_r; //***************************************************************** // Write Calibration state machine //***************************************************************** // when calibrating, check to see if the expected pattern is received. // Otherwise delay DQS to align to correct CK edge. // NOTES: // 1. An error condition can occur due to two reasons: // a. If the matching logic does not receive the expected data // pattern. However, the error may be "recoverable" because // the write calibration is still in progress. If an error is // found the write calibration logic delays DQS by an additional // clock cycle and restarts the pattern detection process. // By design, if the write path timing is incorrect, the correct // data pattern will never be detected. // b. Valid data not found even after incrementing Phaser_Out // coarse delay line. always @(posedge clk) begin if (rst) begin wrcal_dqs_cnt_r <= #TCQ 'b0; cal2_done_r <= #TCQ 1'b0; cal2_prech_req_r <= #TCQ 1'b0; cal2_state_r <= #TCQ CAL2_IDLE; wrcal_pat_err <= #TCQ 1'b0; wrcal_pat_resume_r <= #TCQ 1'b0; wrcal_act_req <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; temp_wrcal_done <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b0; early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b0; idelay_ld <= #TCQ 1'b0; idelay_ld_done <= #TCQ 1'b0; pat1_detect <= #TCQ 1'b0; early1_detect <= #TCQ 1'b0; wrcal_sanity_chk_done <= #TCQ 1'b0; wrcal_sanity_chk_err <= #TCQ 1'b0; end else begin cal2_prech_req_r <= #TCQ 1'b0; case (cal2_state_r) CAL2_IDLE: begin wrcal_pat_err <= #TCQ 1'b0; if (wrcal_start) begin cal2_if_reset <= #TCQ 1'b0; if (SIM_CAL_OPTION == "SKIP_CAL") // If skip write calibration, then proceed to end. cal2_state_r <= #TCQ CAL2_DONE; else cal2_state_r <= #TCQ CAL2_READ_WAIT; end end // General wait state to wait for read data to be output by the // IN_FIFO CAL2_READ_WAIT: begin wrcal_pat_resume_r <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; // Wait until read data is received, and pattern matching // calculation is complete. NOTE: Need to add a timeout here // in case for some reason data is never received (or rather // the PHASER_IN and IN_FIFO think they never receives data) if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin if (pat_data_match_r) // If found data match, then move on to next DQS group cal2_state_r <= #TCQ CAL2_NEXT_DQS; else begin if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_ERR; // If writes are one or two cycles early then redo // write leveling for the byte else if (early1_data_match_r) begin early1_data <= #TCQ 1'b1; early2_data <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; end else if (early2_data_match_r) begin early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b1; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; // Read late due to incorrect MPR idelay value // Decrement Idelay to '0'for the current byte end else if (~idelay_ld_done) begin cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC; idelay_ld <= #TCQ 1'b1; end else cal2_state_r <= #TCQ CAL2_ERR; end end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin if ((pat1_data_match_r1 && pat2_data_match_r) || (pat1_detect && pat2_data_match_r)) // If found data match, then move on to next DQS group cal2_state_r <= #TCQ CAL2_NEXT_DQS; else if (pat1_data_match_r1 && ~pat2_data_match_r) begin cal2_state_r <= #TCQ CAL2_READ_WAIT; pat1_detect <= #TCQ 1'b1; end else begin // If writes are one or two cycles early then redo // write leveling for the byte if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_ERR; else if ((early1_data_match_r1 && early2_data_match_r) || (early1_detect && early2_data_match_r)) begin early1_data <= #TCQ 1'b1; early2_data <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; end else if (early1_data_match_r1 && ~early2_data_match_r) begin early1_detect <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_READ_WAIT; // Read late due to incorrect MPR idelay value // Decrement Idelay to '0'for the current byte end else if (~idelay_ld_done) begin cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC; idelay_ld <= #TCQ 1'b1; end else cal2_state_r <= #TCQ CAL2_ERR; end end else if (not_empty_wait_cnt == 'd31) cal2_state_r <= #TCQ CAL2_ERR; end CAL2_WRLVL_WAIT: begin early1_detect <= #TCQ 1'b0; if (wrlvl_byte_done && ~wrlvl_byte_done_r) wrlvl_byte_redo <= #TCQ 1'b0; if (wrlvl_byte_done) begin if (rd_active_r1 && ~rd_active_r) begin cal2_state_r <= #TCQ CAL2_IFIFO_RESET; cal2_if_reset <= #TCQ 1'b1; early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b0; end end end CAL2_DQ_IDEL_DEC: begin if (tap_inc_wait_cnt == 'd4) begin idelay_ld <= #TCQ 1'b0; cal2_state_r <= #TCQ CAL2_IFIFO_RESET; cal2_if_reset <= #TCQ 1'b1; idelay_ld_done <= #TCQ 1'b1; end end CAL2_IFIFO_RESET: begin if (tap_inc_wait_cnt == 'd15) begin cal2_if_reset <= #TCQ 1'b0; if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_DONE; else if (idelay_ld_done) begin wrcal_pat_resume_r <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_READ_WAIT; end else cal2_state_r <= #TCQ CAL2_IDLE; end end // Final processing for current DQS group. Move on to next group CAL2_NEXT_DQS: begin // At this point, we've just found the correct pattern for the // current DQS group. // Request bank/row precharge, and wait for its completion. Always // precharge after each DQS group to avoid tRAS(max) violation //verilint STARC-2.2.3.3 off if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin cal2_prech_req_r <= #TCQ 1'b0; wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1; cal2_state_r <= #TCQ CAL2_SANITY_WAIT; end else cal2_prech_req_r <= #TCQ 1'b1; idelay_ld_done <= #TCQ 1'b0; pat1_detect <= #TCQ 1'b0; if (prech_done) if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) || (wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin // If either FAST_CAL is enabled and first DQS group is // finished, or if the last DQS group was just finished, // then end of write calibration if (wrcal_sanity_chk_r) begin cal2_if_reset <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_IFIFO_RESET; end else cal2_state_r <= #TCQ CAL2_DONE; end else begin // Continue to next DQS group wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1; cal2_state_r <= #TCQ CAL2_READ_WAIT; end end //verilint STARC-2.2.3.3 on CAL2_SANITY_WAIT: begin if (tap_inc_wait_cnt == 'd15) begin cal2_state_r <= #TCQ CAL2_READ_WAIT; wrcal_pat_resume_r <= #TCQ 1'b1; end end // Finished with read enable calibration CAL2_DONE: begin if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin cal2_done_r <= #TCQ 1'b0; wrcal_dqs_cnt_r <= #TCQ 'd0; cal2_state_r <= #TCQ CAL2_IDLE; end else cal2_done_r <= #TCQ 1'b1; cal2_prech_req_r <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; if (wrcal_sanity_chk_r) wrcal_sanity_chk_done <= #TCQ 1'b1; end // Assert error signal indicating that writes timing is incorrect CAL2_ERR: begin wrcal_pat_resume_r <= #TCQ 1'b0; if (wrcal_sanity_chk_r) wrcal_sanity_chk_err <= #TCQ 1'b1; else wrcal_pat_err <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_ERR; end endcase end end // Delay assertion of wrcal_done for write calibration by a few cycles after // we've reached CAL2_DONE always @(posedge clk) if (rst) cal2_done_r1 <= #TCQ 1'b0; else cal2_done_r1 <= #TCQ cal2_done_r; always @(posedge clk) if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r)) wrcal_done <= #TCQ 1'b0; else if (cal2_done_r) wrcal_done <= #TCQ 1'b1; endmodule
//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_wrcal.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Write calibration logic to align DQS to correct CK edge //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ **$Date: 2011/06/02 08:35:09 $ **$Author: **$Revision: **$Source: ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_wrcal # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter CLK_PERIOD = 2500, parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly parameter SIM_CAL_OPTION = "NONE" // Skip various calibration steps ) ( input clk, input rst, // Calibration status, control signals input wrcal_start, input wrcal_rd_wait, input wrcal_sanity_chk, input dqsfound_retry_done, input phy_rddata_en, output dqsfound_retry, output wrcal_read_req, output reg wrcal_act_req, output reg wrcal_done, output reg wrcal_pat_err, output reg wrcal_prech_req, output reg temp_wrcal_done, output reg wrcal_sanity_chk_done, input prech_done, // Captured data in resync clock domain input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Write level values of Phaser_Out coarse and fine // delay taps required to load Phaser_Out register input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt, input [6*DQS_WIDTH-1:0] wl_po_fine_cnt, input wrlvl_byte_done, output reg wrlvl_byte_redo, output reg early1_data, output reg early2_data, // DQ IDELAY output reg idelay_ld, output reg wrcal_pat_resume, // to phy_init for write output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt, output phy_if_reset, // Debug Port output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, output [99:0] dbg_phy_wrcal ); // Length of calibration sequence (in # of words) //localparam CAL_PAT_LEN = 8; // Read data shift register length localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2; // # of reads for reliable read capture localparam NUM_READS = 2; // # of cycles to wait after changing RDEN count value localparam RDEN_WAIT_CNT = 12; localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6; localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44; localparam CAL2_IDLE = 4'h0; localparam CAL2_READ_WAIT = 4'h1; localparam CAL2_NEXT_DQS = 4'h2; localparam CAL2_WRLVL_WAIT = 4'h3; localparam CAL2_IFIFO_RESET = 4'h4; localparam CAL2_DQ_IDEL_DEC = 4'h5; localparam CAL2_DONE = 4'h6; localparam CAL2_SANITY_WAIT = 4'h7; localparam CAL2_ERR = 4'h8; integer i,j,k,l,m,p,q,d; reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1]; reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w; reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1]; reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w; reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */; reg [4:0] not_empty_wait_cnt; reg [3:0] tap_inc_wait_cnt; reg cal2_done_r; reg cal2_done_r1; reg cal2_prech_req_r; reg [3:0] cal2_state_r; reg [3:0] cal2_state_r1; reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1]; reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1]; reg cal2_if_reset; reg wrcal_pat_resume_r; reg wrcal_pat_resume_r1; reg wrcal_pat_resume_r2; reg wrcal_pat_resume_r3; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r; reg pat_data_match_r; reg pat1_data_match_r; reg pat1_data_match_r1; reg pat2_data_match_r; reg pat_data_match_valid_r; wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0]; reg [DRAM_WIDTH-1:0] pat_match_fall0_r; reg pat_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall1_r; reg pat_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall2_r; reg pat_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall3_r; reg pat_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise0_r; reg pat_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise1_r; reg pat_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise2_r; reg pat_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise3_r; reg pat_match_rise3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise0_r; reg [DRAM_WIDTH-1:0] pat1_match_rise1_r; reg [DRAM_WIDTH-1:0] pat1_match_fall0_r; reg [DRAM_WIDTH-1:0] pat1_match_fall1_r; reg [DRAM_WIDTH-1:0] pat2_match_rise0_r; reg [DRAM_WIDTH-1:0] pat2_match_rise1_r; reg [DRAM_WIDTH-1:0] pat2_match_fall0_r; reg [DRAM_WIDTH-1:0] pat2_match_fall1_r; reg pat1_match_rise0_and_r; reg pat1_match_rise1_and_r; reg pat1_match_fall0_and_r; reg pat1_match_fall1_and_r; reg pat2_match_rise0_and_r; reg pat2_match_rise1_and_r; reg pat2_match_fall0_and_r; reg pat2_match_fall1_and_r; reg early1_data_match_r; reg early1_data_match_r1; reg [DRAM_WIDTH-1:0] early1_match_fall0_r; reg early1_match_fall0_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall1_r; reg early1_match_fall1_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall2_r; reg early1_match_fall2_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall3_r; reg early1_match_fall3_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise0_r; reg early1_match_rise0_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise1_r; reg early1_match_rise1_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise2_r; reg early1_match_rise2_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise3_r; reg early1_match_rise3_and_r; reg early2_data_match_r; reg [DRAM_WIDTH-1:0] early2_match_fall0_r; reg early2_match_fall0_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall1_r; reg early2_match_fall1_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall2_r; reg early2_match_fall2_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall3_r; reg early2_match_fall3_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise0_r; reg early2_match_rise0_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise1_r; reg early2_match_rise1_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise2_r; reg early2_match_rise2_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise3_r; reg early2_match_rise3_and_r; wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0]; wire [DQ_WIDTH-1:0] rd_data_rise0; wire [DQ_WIDTH-1:0] rd_data_fall0; wire [DQ_WIDTH-1:0] rd_data_rise1; wire [DQ_WIDTH-1:0] rd_data_fall1; wire [DQ_WIDTH-1:0] rd_data_rise2; wire [DQ_WIDTH-1:0] rd_data_fall2; wire [DQ_WIDTH-1:0] rd_data_rise3; wire [DQ_WIDTH-1:0] rd_data_fall3; reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; reg rd_active_posedge_r; reg rd_active_r; reg rd_active_r1; reg rd_active_r2; reg rd_active_r3; reg rd_active_r4; reg rd_active_r5; reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0]; reg wrlvl_byte_done_r; reg idelay_ld_done; reg pat1_detect; reg early1_detect; reg wrcal_sanity_chk_r; reg wrcal_sanity_chk_err; //*************************************************************************** // Debug //*************************************************************************** always @(*) begin for (d = 0; d < DQS_WIDTH; d = d + 1) begin po_fine_tap_cnt_w[(6*d)+:6] = po_fine_tap_cnt[d]; po_coarse_tap_cnt_w[(3*d)+:3] = po_coarse_tap_cnt[d]; end end assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w; assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w; assign dbg_phy_wrcal[0] = pat_data_match_r; assign dbg_phy_wrcal[4:1] = cal2_state_r1[3:0]; assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err; assign dbg_phy_wrcal[6] = wrcal_start; assign dbg_phy_wrcal[7] = wrcal_done; assign dbg_phy_wrcal[8] = pat_data_match_valid_r; assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r; assign dbg_phy_wrcal[17+:5] = not_empty_wait_cnt; assign dbg_phy_wrcal[22] = early1_data; assign dbg_phy_wrcal[23] = early2_data; assign dbg_phy_wrcal[24+:8] = mux_rd_rise0_r; assign dbg_phy_wrcal[32+:8] = mux_rd_fall0_r; assign dbg_phy_wrcal[40+:8] = mux_rd_rise1_r; assign dbg_phy_wrcal[48+:8] = mux_rd_fall1_r; assign dbg_phy_wrcal[56+:8] = mux_rd_rise2_r; assign dbg_phy_wrcal[64+:8] = mux_rd_fall2_r; assign dbg_phy_wrcal[72+:8] = mux_rd_rise3_r; assign dbg_phy_wrcal[80+:8] = mux_rd_fall3_r; assign dbg_phy_wrcal[88] = early1_data_match_r; assign dbg_phy_wrcal[89] = early2_data_match_r; assign dbg_phy_wrcal[90] = wrcal_sanity_chk_r & pat_data_match_valid_r; assign dbg_phy_wrcal[91] = wrcal_sanity_chk_r; assign dbg_phy_wrcal[92] = wrcal_sanity_chk_done; assign dqsfound_retry = 1'b0; assign wrcal_read_req = 1'b0; assign phy_if_reset = cal2_if_reset; //************************************************************************** // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 // coarse delay //************************************************************************** always @(posedge clk) begin po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r; wrlvl_byte_done_r <= #TCQ wrlvl_byte_done; wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk; end //*************************************************************************** // Data mux to route appropriate byte to calibration logic - i.e. calibration // is done sequentially, one byte (or DQS group) at a time //*************************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_rd_data_div4 assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2 assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; end endgenerate //************************************************************************** // Final Phaser OUT coarse and fine delay taps after write calibration // Sum of taps used during write leveling taps and write calibration //************************************************************************** always @(*) begin for (m = 0; m < DQS_WIDTH; m = m + 1) begin wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3]; wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6]; end end always @(posedge clk) begin if (rst) begin for (p = 0; p < DQS_WIDTH; p = p + 1) begin po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}}; po_fine_tap_cnt[p] <= #TCQ {6{1'b0}}; end end else if (cal2_done_r && ~cal2_done_r1) begin for (q = 0; q < DQS_WIDTH; q = q + 1) begin po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i]; po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i]; end end end always @(posedge clk) begin rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r; end // Register outputs for improved timing. // NOTE: Will need to change when per-bit DQ deskew is supported. // Currenly all bits in DQS group are checked in aggregate generate genvar mux_i; if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4 for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2 for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end end endgenerate //*************************************************************************** // generate request to PHY_INIT logic to issue precharged. Required when // calibration can take a long time (during which there are only constant // reads present on this bus). In this case need to issue perioidic // precharges to avoid tRAS violation. This signal must meet the following // requirements: (1) only transition from 0->1 when prech is first needed, // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted //*************************************************************************** always @(posedge clk) if (rst) wrcal_prech_req <= #TCQ 1'b0; else // Combine requests from all stages here wrcal_prech_req <= #TCQ cal2_prech_req_r; //*************************************************************************** // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES // NOTE: Written using discrete flops, but SRL can be used if the matching // logic does the comparison sequentially, rather than parallel //*************************************************************************** generate genvar rd_i; if (nCK_PER_CLK == 4) begin: gen_sr_div4 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i]; sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i]; sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i]; sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i]; end end end else if (nCK_PER_CLK == 2) begin: gen_sr_div2 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; end end end endgenerate //*************************************************************************** // Write calibration: // During write leveling DQS is aligned to the nearest CK edge that may not // be the correct CK edge. Write calibration is required to align the DQS to // the correct CK edge that clocks the write command. // The Phaser_Out coarse delay line is adjusted if required to add a memory // clock cycle of delay in order to read back the expected pattern. //*************************************************************************** always @(posedge clk) begin rd_active_r <= #TCQ phy_rddata_en; rd_active_r1 <= #TCQ rd_active_r; rd_active_r2 <= #TCQ rd_active_r1; rd_active_r3 <= #TCQ rd_active_r2; rd_active_r4 <= #TCQ rd_active_r3; rd_active_r5 <= #TCQ rd_active_r4; end //***************************************************************** // Expected data pattern when properly received by read capture // logic: // Based on pattern of ({rise,fall}) = // 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 // Each nibble will look like: // bit3: 1, 0, 1, 0, 0, 1, 1, 0 // bit2: 1, 0, 0, 1, 1, 0, 0, 1 // bit1: 1, 0, 1, 0, 0, 1, 0, 1 // bit0: 1, 0, 0, 1, 1, 0, 1, 0 // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN // and the actual training pattern contents change //***************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_pat_div4 // FF00AA5555AA9966 assign pat_rise0[3] = 1'b1; assign pat_fall0[3] = 1'b0; assign pat_rise1[3] = 1'b1; assign pat_fall1[3] = 1'b0; assign pat_rise2[3] = 1'b0; assign pat_fall2[3] = 1'b1; assign pat_rise3[3] = 1'b1; assign pat_fall3[3] = 1'b0; assign pat_rise0[2] = 1'b1; assign pat_fall0[2] = 1'b0; assign pat_rise1[2] = 1'b0; assign pat_fall1[2] = 1'b1; assign pat_rise2[2] = 1'b1; assign pat_fall2[2] = 1'b0; assign pat_rise3[2] = 1'b0; assign pat_fall3[2] = 1'b1; assign pat_rise0[1] = 1'b1; assign pat_fall0[1] = 1'b0; assign pat_rise1[1] = 1'b1; assign pat_fall1[1] = 1'b0; assign pat_rise2[1] = 1'b0; assign pat_fall2[1] = 1'b1; assign pat_rise3[1] = 1'b0; assign pat_fall3[1] = 1'b1; assign pat_rise0[0] = 1'b1; assign pat_fall0[0] = 1'b0; assign pat_rise1[0] = 1'b0; assign pat_fall1[0] = 1'b1; assign pat_rise2[0] = 1'b1; assign pat_fall2[0] = 1'b0; assign pat_rise3[0] = 1'b1; assign pat_fall3[0] = 1'b0; // Pattern to distinguish between early write and incorrect read // BB11EE4444EEDD88 assign early_rise0[3] = 1'b1; assign early_fall0[3] = 1'b0; assign early_rise1[3] = 1'b1; assign early_fall1[3] = 1'b0; assign early_rise2[3] = 1'b0; assign early_fall2[3] = 1'b1; assign early_rise3[3] = 1'b1; assign early_fall3[3] = 1'b1; assign early_rise0[2] = 1'b0; assign early_fall0[2] = 1'b0; assign early_rise1[2] = 1'b1; assign early_fall1[2] = 1'b1; assign early_rise2[2] = 1'b1; assign early_fall2[2] = 1'b1; assign early_rise3[2] = 1'b1; assign early_fall3[2] = 1'b0; assign early_rise0[1] = 1'b1; assign early_fall0[1] = 1'b0; assign early_rise1[1] = 1'b1; assign early_fall1[1] = 1'b0; assign early_rise2[1] = 1'b0; assign early_fall2[1] = 1'b1; assign early_rise3[1] = 1'b0; assign early_fall3[1] = 1'b0; assign early_rise0[0] = 1'b1; assign early_fall0[0] = 1'b1; assign early_rise1[0] = 1'b0; assign early_fall1[0] = 1'b0; assign early_rise2[0] = 1'b0; assign early_fall2[0] = 1'b0; assign early_rise3[0] = 1'b1; assign early_fall3[0] = 1'b0; end else if (nCK_PER_CLK == 2) begin: gen_pat_div2 // First cycle pattern FF00AA55 assign pat1_rise0[3] = 1'b1; assign pat1_fall0[3] = 1'b0; assign pat1_rise1[3] = 1'b1; assign pat1_fall1[3] = 1'b0; assign pat1_rise0[2] = 1'b1; assign pat1_fall0[2] = 1'b0; assign pat1_rise1[2] = 1'b0; assign pat1_fall1[2] = 1'b1; assign pat1_rise0[1] = 1'b1; assign pat1_fall0[1] = 1'b0; assign pat1_rise1[1] = 1'b1; assign pat1_fall1[1] = 1'b0; assign pat1_rise0[0] = 1'b1; assign pat1_fall0[0] = 1'b0; assign pat1_rise1[0] = 1'b0; assign pat1_fall1[0] = 1'b1; // Second cycle pattern 55AA9966 assign pat2_rise0[3] = 1'b0; assign pat2_fall0[3] = 1'b1; assign pat2_rise1[3] = 1'b1; assign pat2_fall1[3] = 1'b0; assign pat2_rise0[2] = 1'b1; assign pat2_fall0[2] = 1'b0; assign pat2_rise1[2] = 1'b0; assign pat2_fall1[2] = 1'b1; assign pat2_rise0[1] = 1'b0; assign pat2_fall0[1] = 1'b1; assign pat2_rise1[1] = 1'b0; assign pat2_fall1[1] = 1'b1; assign pat2_rise0[0] = 1'b1; assign pat2_fall0[0] = 1'b0; assign pat2_rise1[0] = 1'b1; assign pat2_fall1[0] = 1'b0; //Pattern to distinguish between early write and incorrect read // First cycle pattern AA5555AA assign early1_rise0[3] = 2'b1; assign early1_fall0[3] = 2'b0; assign early1_rise1[3] = 2'b0; assign early1_fall1[3] = 2'b1; assign early1_rise0[2] = 2'b0; assign early1_fall0[2] = 2'b1; assign early1_rise1[2] = 2'b1; assign early1_fall1[2] = 2'b0; assign early1_rise0[1] = 2'b1; assign early1_fall0[1] = 2'b0; assign early1_rise1[1] = 2'b0; assign early1_fall1[1] = 2'b1; assign early1_rise0[0] = 2'b0; assign early1_fall0[0] = 2'b1; assign early1_rise1[0] = 2'b1; assign early1_fall1[0] = 2'b0; // Second cycle pattern 9966BB11 assign early2_rise0[3] = 2'b1; assign early2_fall0[3] = 2'b0; assign early2_rise1[3] = 2'b1; assign early2_fall1[3] = 2'b0; assign early2_rise0[2] = 2'b0; assign early2_fall0[2] = 2'b1; assign early2_rise1[2] = 2'b0; assign early2_fall1[2] = 2'b0; assign early2_rise0[1] = 2'b0; assign early2_fall0[1] = 2'b1; assign early2_rise1[1] = 2'b1; assign early2_fall1[1] = 2'b0; assign early2_rise0[0] = 2'b1; assign early2_fall0[0] = 2'b0; assign early2_rise1[0] = 2'b1; assign early2_fall1[0] = 2'b1; end endgenerate // Each bit of each byte is compared to expected pattern. // This was done to prevent (and "drastically decrease") the chance that // invalid data clocked in when the DQ bus is tri-state (along with a // combination of the correct data) will resemble the expected data // pattern. A better fix for this is to change the training pattern and/or // make the pattern longer. generate genvar pt_i; if (nCK_PER_CLK == 4) begin: gen_pat_match_div4 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4]) pat_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4]) pat_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4]) pat_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4]) pat_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4]) pat_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4]) pat_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4]) pat_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4]) pat_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4]) early1_match_rise0_r[pt_i] <= #TCQ 1'b1; else early1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4]) early1_match_fall0_r[pt_i] <= #TCQ 1'b1; else early1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4]) early1_match_rise1_r[pt_i] <= #TCQ 1'b1; else early1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4]) early1_match_fall1_r[pt_i] <= #TCQ 1'b1; else early1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4]) early1_match_rise2_r[pt_i] <= #TCQ 1'b1; else early1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4]) early1_match_fall2_r[pt_i] <= #TCQ 1'b1; else early1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == early_rise0[pt_i%4]) early1_match_rise3_r[pt_i] <= #TCQ 1'b1; else early1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == early_fall0[pt_i%4]) early1_match_fall3_r[pt_i] <= #TCQ 1'b1; else early1_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4]) early2_match_rise0_r[pt_i] <= #TCQ 1'b1; else early2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4]) early2_match_fall0_r[pt_i] <= #TCQ 1'b1; else early2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4]) early2_match_rise1_r[pt_i] <= #TCQ 1'b1; else early2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4]) early2_match_fall1_r[pt_i] <= #TCQ 1'b1; else early2_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == early_rise0[pt_i%4]) early2_match_rise2_r[pt_i] <= #TCQ 1'b1; else early2_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == early_fall0[pt_i%4]) early2_match_fall2_r[pt_i] <= #TCQ 1'b1; else early2_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == early_rise1[pt_i%4]) early2_match_rise3_r[pt_i] <= #TCQ 1'b1; else early2_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == early_fall1[pt_i%4]) early2_match_fall3_r[pt_i] <= #TCQ 1'b1; else early2_match_fall3_r[pt_i] <= #TCQ 1'b0; end end always @(posedge clk) begin pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r; pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r; pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r; pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r; pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r; pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r; pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r; pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r; pat_data_match_r <= #TCQ (pat_match_rise0_and_r && pat_match_fall0_and_r && pat_match_rise1_and_r && pat_match_fall1_and_r && pat_match_rise2_and_r && pat_match_fall2_and_r && pat_match_rise3_and_r && pat_match_fall3_and_r); pat_data_match_valid_r <= #TCQ rd_active_r3; end always @(posedge clk) begin early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r; early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r; early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r; early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r; early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r; early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r; early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r; early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r; early1_data_match_r <= #TCQ (early1_match_rise0_and_r && early1_match_fall0_and_r && early1_match_rise1_and_r && early1_match_fall1_and_r && early1_match_rise2_and_r && early1_match_fall2_and_r && early1_match_rise3_and_r && early1_match_fall3_and_r); end always @(posedge clk) begin early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r; early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r; early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r; early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r; early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r; early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r; early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r; early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r; early2_data_match_r <= #TCQ (early2_match_rise0_and_r && early2_match_fall0_and_r && early2_match_rise1_and_r && early2_match_fall1_and_r && early2_match_rise2_and_r && early2_match_fall2_and_r && early2_match_rise3_and_r && early2_match_fall3_and_r); end end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4]) pat2_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4]) pat2_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4]) pat2_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4]) pat2_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat2_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4]) early1_match_rise0_r[pt_i] <= #TCQ 1'b1; else early1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4]) early1_match_fall0_r[pt_i] <= #TCQ 1'b1; else early1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4]) early1_match_rise1_r[pt_i] <= #TCQ 1'b1; else early1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4]) early1_match_fall1_r[pt_i] <= #TCQ 1'b1; else early1_match_fall1_r[pt_i] <= #TCQ 1'b0; end // early2 in this case does not mean 2 cycles early but // the second cycle of read data in 2:1 mode always @(posedge clk) begin if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4]) early2_match_rise0_r[pt_i] <= #TCQ 1'b1; else early2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4]) early2_match_fall0_r[pt_i] <= #TCQ 1'b1; else early2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4]) early2_match_rise1_r[pt_i] <= #TCQ 1'b1; else early2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4]) early2_match_fall1_r[pt_i] <= #TCQ 1'b1; else early2_match_fall1_r[pt_i] <= #TCQ 1'b0; end end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r); pat1_data_match_r1 <= #TCQ pat1_data_match_r; pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3; pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3; pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3; pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3; pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r && pat2_match_fall0_and_r && pat2_match_rise1_and_r && pat2_match_fall1_and_r); // For 2:1 mode, read valid is asserted for 2 clock cycles - // here we generate a "match valid" pulse that is only 1 clock // cycle wide that is simulatenous when the match calculation // is complete pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5; end always @(posedge clk) begin early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r; early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r; early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r; early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r; early1_data_match_r <= #TCQ (early1_match_rise0_and_r && early1_match_fall0_and_r && early1_match_rise1_and_r && early1_match_fall1_and_r); early1_data_match_r1 <= #TCQ early1_data_match_r; early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3; early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3; early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3; early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3; early2_data_match_r <= #TCQ (early2_match_rise0_and_r && early2_match_fall0_and_r && early2_match_rise1_and_r && early2_match_fall1_and_r); end end endgenerate // Need to delay it by 3 cycles in order to wait for Phaser_Out // coarse delay to take effect before issuing a write command always @(posedge clk) begin wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r; wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1; wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2; end always @(posedge clk) begin if (rst) tap_inc_wait_cnt <= #TCQ 'd0; else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) || (cal2_state_r == CAL2_IFIFO_RESET) || (cal2_state_r == CAL2_SANITY_WAIT)) tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1; else tap_inc_wait_cnt <= #TCQ 'd0; end always @(posedge clk) begin if (rst) not_empty_wait_cnt <= #TCQ 'd0; else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait) not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1; else not_empty_wait_cnt <= #TCQ 'd0; end always @(posedge clk) cal2_state_r1 <= #TCQ cal2_state_r; //***************************************************************** // Write Calibration state machine //***************************************************************** // when calibrating, check to see if the expected pattern is received. // Otherwise delay DQS to align to correct CK edge. // NOTES: // 1. An error condition can occur due to two reasons: // a. If the matching logic does not receive the expected data // pattern. However, the error may be "recoverable" because // the write calibration is still in progress. If an error is // found the write calibration logic delays DQS by an additional // clock cycle and restarts the pattern detection process. // By design, if the write path timing is incorrect, the correct // data pattern will never be detected. // b. Valid data not found even after incrementing Phaser_Out // coarse delay line. always @(posedge clk) begin if (rst) begin wrcal_dqs_cnt_r <= #TCQ 'b0; cal2_done_r <= #TCQ 1'b0; cal2_prech_req_r <= #TCQ 1'b0; cal2_state_r <= #TCQ CAL2_IDLE; wrcal_pat_err <= #TCQ 1'b0; wrcal_pat_resume_r <= #TCQ 1'b0; wrcal_act_req <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; temp_wrcal_done <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b0; early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b0; idelay_ld <= #TCQ 1'b0; idelay_ld_done <= #TCQ 1'b0; pat1_detect <= #TCQ 1'b0; early1_detect <= #TCQ 1'b0; wrcal_sanity_chk_done <= #TCQ 1'b0; wrcal_sanity_chk_err <= #TCQ 1'b0; end else begin cal2_prech_req_r <= #TCQ 1'b0; case (cal2_state_r) CAL2_IDLE: begin wrcal_pat_err <= #TCQ 1'b0; if (wrcal_start) begin cal2_if_reset <= #TCQ 1'b0; if (SIM_CAL_OPTION == "SKIP_CAL") // If skip write calibration, then proceed to end. cal2_state_r <= #TCQ CAL2_DONE; else cal2_state_r <= #TCQ CAL2_READ_WAIT; end end // General wait state to wait for read data to be output by the // IN_FIFO CAL2_READ_WAIT: begin wrcal_pat_resume_r <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; // Wait until read data is received, and pattern matching // calculation is complete. NOTE: Need to add a timeout here // in case for some reason data is never received (or rather // the PHASER_IN and IN_FIFO think they never receives data) if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin if (pat_data_match_r) // If found data match, then move on to next DQS group cal2_state_r <= #TCQ CAL2_NEXT_DQS; else begin if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_ERR; // If writes are one or two cycles early then redo // write leveling for the byte else if (early1_data_match_r) begin early1_data <= #TCQ 1'b1; early2_data <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; end else if (early2_data_match_r) begin early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b1; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; // Read late due to incorrect MPR idelay value // Decrement Idelay to '0'for the current byte end else if (~idelay_ld_done) begin cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC; idelay_ld <= #TCQ 1'b1; end else cal2_state_r <= #TCQ CAL2_ERR; end end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin if ((pat1_data_match_r1 && pat2_data_match_r) || (pat1_detect && pat2_data_match_r)) // If found data match, then move on to next DQS group cal2_state_r <= #TCQ CAL2_NEXT_DQS; else if (pat1_data_match_r1 && ~pat2_data_match_r) begin cal2_state_r <= #TCQ CAL2_READ_WAIT; pat1_detect <= #TCQ 1'b1; end else begin // If writes are one or two cycles early then redo // write leveling for the byte if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_ERR; else if ((early1_data_match_r1 && early2_data_match_r) || (early1_detect && early2_data_match_r)) begin early1_data <= #TCQ 1'b1; early2_data <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; end else if (early1_data_match_r1 && ~early2_data_match_r) begin early1_detect <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_READ_WAIT; // Read late due to incorrect MPR idelay value // Decrement Idelay to '0'for the current byte end else if (~idelay_ld_done) begin cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC; idelay_ld <= #TCQ 1'b1; end else cal2_state_r <= #TCQ CAL2_ERR; end end else if (not_empty_wait_cnt == 'd31) cal2_state_r <= #TCQ CAL2_ERR; end CAL2_WRLVL_WAIT: begin early1_detect <= #TCQ 1'b0; if (wrlvl_byte_done && ~wrlvl_byte_done_r) wrlvl_byte_redo <= #TCQ 1'b0; if (wrlvl_byte_done) begin if (rd_active_r1 && ~rd_active_r) begin cal2_state_r <= #TCQ CAL2_IFIFO_RESET; cal2_if_reset <= #TCQ 1'b1; early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b0; end end end CAL2_DQ_IDEL_DEC: begin if (tap_inc_wait_cnt == 'd4) begin idelay_ld <= #TCQ 1'b0; cal2_state_r <= #TCQ CAL2_IFIFO_RESET; cal2_if_reset <= #TCQ 1'b1; idelay_ld_done <= #TCQ 1'b1; end end CAL2_IFIFO_RESET: begin if (tap_inc_wait_cnt == 'd15) begin cal2_if_reset <= #TCQ 1'b0; if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_DONE; else if (idelay_ld_done) begin wrcal_pat_resume_r <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_READ_WAIT; end else cal2_state_r <= #TCQ CAL2_IDLE; end end // Final processing for current DQS group. Move on to next group CAL2_NEXT_DQS: begin // At this point, we've just found the correct pattern for the // current DQS group. // Request bank/row precharge, and wait for its completion. Always // precharge after each DQS group to avoid tRAS(max) violation //verilint STARC-2.2.3.3 off if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin cal2_prech_req_r <= #TCQ 1'b0; wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1; cal2_state_r <= #TCQ CAL2_SANITY_WAIT; end else cal2_prech_req_r <= #TCQ 1'b1; idelay_ld_done <= #TCQ 1'b0; pat1_detect <= #TCQ 1'b0; if (prech_done) if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) || (wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin // If either FAST_CAL is enabled and first DQS group is // finished, or if the last DQS group was just finished, // then end of write calibration if (wrcal_sanity_chk_r) begin cal2_if_reset <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_IFIFO_RESET; end else cal2_state_r <= #TCQ CAL2_DONE; end else begin // Continue to next DQS group wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1; cal2_state_r <= #TCQ CAL2_READ_WAIT; end end //verilint STARC-2.2.3.3 on CAL2_SANITY_WAIT: begin if (tap_inc_wait_cnt == 'd15) begin cal2_state_r <= #TCQ CAL2_READ_WAIT; wrcal_pat_resume_r <= #TCQ 1'b1; end end // Finished with read enable calibration CAL2_DONE: begin if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin cal2_done_r <= #TCQ 1'b0; wrcal_dqs_cnt_r <= #TCQ 'd0; cal2_state_r <= #TCQ CAL2_IDLE; end else cal2_done_r <= #TCQ 1'b1; cal2_prech_req_r <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; if (wrcal_sanity_chk_r) wrcal_sanity_chk_done <= #TCQ 1'b1; end // Assert error signal indicating that writes timing is incorrect CAL2_ERR: begin wrcal_pat_resume_r <= #TCQ 1'b0; if (wrcal_sanity_chk_r) wrcal_sanity_chk_err <= #TCQ 1'b1; else wrcal_pat_err <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_ERR; end endcase end end // Delay assertion of wrcal_done for write calibration by a few cycles after // we've reached CAL2_DONE always @(posedge clk) if (rst) cal2_done_r1 <= #TCQ 1'b0; else cal2_done_r1 <= #TCQ cal2_done_r; always @(posedge clk) if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r)) wrcal_done <= #TCQ 1'b0; else if (cal2_done_r) wrcal_done <= #TCQ 1'b1; endmodule
//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_wrcal.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Write calibration logic to align DQS to correct CK edge //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ **$Date: 2011/06/02 08:35:09 $ **$Author: **$Revision: **$Source: ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_wrcal # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter CLK_PERIOD = 2500, parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly parameter SIM_CAL_OPTION = "NONE" // Skip various calibration steps ) ( input clk, input rst, // Calibration status, control signals input wrcal_start, input wrcal_rd_wait, input wrcal_sanity_chk, input dqsfound_retry_done, input phy_rddata_en, output dqsfound_retry, output wrcal_read_req, output reg wrcal_act_req, output reg wrcal_done, output reg wrcal_pat_err, output reg wrcal_prech_req, output reg temp_wrcal_done, output reg wrcal_sanity_chk_done, input prech_done, // Captured data in resync clock domain input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Write level values of Phaser_Out coarse and fine // delay taps required to load Phaser_Out register input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt, input [6*DQS_WIDTH-1:0] wl_po_fine_cnt, input wrlvl_byte_done, output reg wrlvl_byte_redo, output reg early1_data, output reg early2_data, // DQ IDELAY output reg idelay_ld, output reg wrcal_pat_resume, // to phy_init for write output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt, output phy_if_reset, // Debug Port output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, output [99:0] dbg_phy_wrcal ); // Length of calibration sequence (in # of words) //localparam CAL_PAT_LEN = 8; // Read data shift register length localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2; // # of reads for reliable read capture localparam NUM_READS = 2; // # of cycles to wait after changing RDEN count value localparam RDEN_WAIT_CNT = 12; localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6; localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44; localparam CAL2_IDLE = 4'h0; localparam CAL2_READ_WAIT = 4'h1; localparam CAL2_NEXT_DQS = 4'h2; localparam CAL2_WRLVL_WAIT = 4'h3; localparam CAL2_IFIFO_RESET = 4'h4; localparam CAL2_DQ_IDEL_DEC = 4'h5; localparam CAL2_DONE = 4'h6; localparam CAL2_SANITY_WAIT = 4'h7; localparam CAL2_ERR = 4'h8; integer i,j,k,l,m,p,q,d; reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1]; reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w; reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1]; reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w; reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */; reg [4:0] not_empty_wait_cnt; reg [3:0] tap_inc_wait_cnt; reg cal2_done_r; reg cal2_done_r1; reg cal2_prech_req_r; reg [3:0] cal2_state_r; reg [3:0] cal2_state_r1; reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1]; reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1]; reg cal2_if_reset; reg wrcal_pat_resume_r; reg wrcal_pat_resume_r1; reg wrcal_pat_resume_r2; reg wrcal_pat_resume_r3; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r; reg pat_data_match_r; reg pat1_data_match_r; reg pat1_data_match_r1; reg pat2_data_match_r; reg pat_data_match_valid_r; wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0]; reg [DRAM_WIDTH-1:0] pat_match_fall0_r; reg pat_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall1_r; reg pat_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall2_r; reg pat_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall3_r; reg pat_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise0_r; reg pat_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise1_r; reg pat_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise2_r; reg pat_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise3_r; reg pat_match_rise3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise0_r; reg [DRAM_WIDTH-1:0] pat1_match_rise1_r; reg [DRAM_WIDTH-1:0] pat1_match_fall0_r; reg [DRAM_WIDTH-1:0] pat1_match_fall1_r; reg [DRAM_WIDTH-1:0] pat2_match_rise0_r; reg [DRAM_WIDTH-1:0] pat2_match_rise1_r; reg [DRAM_WIDTH-1:0] pat2_match_fall0_r; reg [DRAM_WIDTH-1:0] pat2_match_fall1_r; reg pat1_match_rise0_and_r; reg pat1_match_rise1_and_r; reg pat1_match_fall0_and_r; reg pat1_match_fall1_and_r; reg pat2_match_rise0_and_r; reg pat2_match_rise1_and_r; reg pat2_match_fall0_and_r; reg pat2_match_fall1_and_r; reg early1_data_match_r; reg early1_data_match_r1; reg [DRAM_WIDTH-1:0] early1_match_fall0_r; reg early1_match_fall0_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall1_r; reg early1_match_fall1_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall2_r; reg early1_match_fall2_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall3_r; reg early1_match_fall3_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise0_r; reg early1_match_rise0_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise1_r; reg early1_match_rise1_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise2_r; reg early1_match_rise2_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise3_r; reg early1_match_rise3_and_r; reg early2_data_match_r; reg [DRAM_WIDTH-1:0] early2_match_fall0_r; reg early2_match_fall0_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall1_r; reg early2_match_fall1_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall2_r; reg early2_match_fall2_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall3_r; reg early2_match_fall3_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise0_r; reg early2_match_rise0_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise1_r; reg early2_match_rise1_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise2_r; reg early2_match_rise2_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise3_r; reg early2_match_rise3_and_r; wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0]; wire [DQ_WIDTH-1:0] rd_data_rise0; wire [DQ_WIDTH-1:0] rd_data_fall0; wire [DQ_WIDTH-1:0] rd_data_rise1; wire [DQ_WIDTH-1:0] rd_data_fall1; wire [DQ_WIDTH-1:0] rd_data_rise2; wire [DQ_WIDTH-1:0] rd_data_fall2; wire [DQ_WIDTH-1:0] rd_data_rise3; wire [DQ_WIDTH-1:0] rd_data_fall3; reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; reg rd_active_posedge_r; reg rd_active_r; reg rd_active_r1; reg rd_active_r2; reg rd_active_r3; reg rd_active_r4; reg rd_active_r5; reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0]; reg wrlvl_byte_done_r; reg idelay_ld_done; reg pat1_detect; reg early1_detect; reg wrcal_sanity_chk_r; reg wrcal_sanity_chk_err; //*************************************************************************** // Debug //*************************************************************************** always @(*) begin for (d = 0; d < DQS_WIDTH; d = d + 1) begin po_fine_tap_cnt_w[(6*d)+:6] = po_fine_tap_cnt[d]; po_coarse_tap_cnt_w[(3*d)+:3] = po_coarse_tap_cnt[d]; end end assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w; assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w; assign dbg_phy_wrcal[0] = pat_data_match_r; assign dbg_phy_wrcal[4:1] = cal2_state_r1[3:0]; assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err; assign dbg_phy_wrcal[6] = wrcal_start; assign dbg_phy_wrcal[7] = wrcal_done; assign dbg_phy_wrcal[8] = pat_data_match_valid_r; assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r; assign dbg_phy_wrcal[17+:5] = not_empty_wait_cnt; assign dbg_phy_wrcal[22] = early1_data; assign dbg_phy_wrcal[23] = early2_data; assign dbg_phy_wrcal[24+:8] = mux_rd_rise0_r; assign dbg_phy_wrcal[32+:8] = mux_rd_fall0_r; assign dbg_phy_wrcal[40+:8] = mux_rd_rise1_r; assign dbg_phy_wrcal[48+:8] = mux_rd_fall1_r; assign dbg_phy_wrcal[56+:8] = mux_rd_rise2_r; assign dbg_phy_wrcal[64+:8] = mux_rd_fall2_r; assign dbg_phy_wrcal[72+:8] = mux_rd_rise3_r; assign dbg_phy_wrcal[80+:8] = mux_rd_fall3_r; assign dbg_phy_wrcal[88] = early1_data_match_r; assign dbg_phy_wrcal[89] = early2_data_match_r; assign dbg_phy_wrcal[90] = wrcal_sanity_chk_r & pat_data_match_valid_r; assign dbg_phy_wrcal[91] = wrcal_sanity_chk_r; assign dbg_phy_wrcal[92] = wrcal_sanity_chk_done; assign dqsfound_retry = 1'b0; assign wrcal_read_req = 1'b0; assign phy_if_reset = cal2_if_reset; //************************************************************************** // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 // coarse delay //************************************************************************** always @(posedge clk) begin po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r; wrlvl_byte_done_r <= #TCQ wrlvl_byte_done; wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk; end //*************************************************************************** // Data mux to route appropriate byte to calibration logic - i.e. calibration // is done sequentially, one byte (or DQS group) at a time //*************************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_rd_data_div4 assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2 assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; end endgenerate //************************************************************************** // Final Phaser OUT coarse and fine delay taps after write calibration // Sum of taps used during write leveling taps and write calibration //************************************************************************** always @(*) begin for (m = 0; m < DQS_WIDTH; m = m + 1) begin wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3]; wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6]; end end always @(posedge clk) begin if (rst) begin for (p = 0; p < DQS_WIDTH; p = p + 1) begin po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}}; po_fine_tap_cnt[p] <= #TCQ {6{1'b0}}; end end else if (cal2_done_r && ~cal2_done_r1) begin for (q = 0; q < DQS_WIDTH; q = q + 1) begin po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i]; po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i]; end end end always @(posedge clk) begin rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r; end // Register outputs for improved timing. // NOTE: Will need to change when per-bit DQ deskew is supported. // Currenly all bits in DQS group are checked in aggregate generate genvar mux_i; if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4 for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2 for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end end endgenerate //*************************************************************************** // generate request to PHY_INIT logic to issue precharged. Required when // calibration can take a long time (during which there are only constant // reads present on this bus). In this case need to issue perioidic // precharges to avoid tRAS violation. This signal must meet the following // requirements: (1) only transition from 0->1 when prech is first needed, // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted //*************************************************************************** always @(posedge clk) if (rst) wrcal_prech_req <= #TCQ 1'b0; else // Combine requests from all stages here wrcal_prech_req <= #TCQ cal2_prech_req_r; //*************************************************************************** // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES // NOTE: Written using discrete flops, but SRL can be used if the matching // logic does the comparison sequentially, rather than parallel //*************************************************************************** generate genvar rd_i; if (nCK_PER_CLK == 4) begin: gen_sr_div4 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i]; sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i]; sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i]; sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i]; end end end else if (nCK_PER_CLK == 2) begin: gen_sr_div2 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; end end end endgenerate //*************************************************************************** // Write calibration: // During write leveling DQS is aligned to the nearest CK edge that may not // be the correct CK edge. Write calibration is required to align the DQS to // the correct CK edge that clocks the write command. // The Phaser_Out coarse delay line is adjusted if required to add a memory // clock cycle of delay in order to read back the expected pattern. //*************************************************************************** always @(posedge clk) begin rd_active_r <= #TCQ phy_rddata_en; rd_active_r1 <= #TCQ rd_active_r; rd_active_r2 <= #TCQ rd_active_r1; rd_active_r3 <= #TCQ rd_active_r2; rd_active_r4 <= #TCQ rd_active_r3; rd_active_r5 <= #TCQ rd_active_r4; end //***************************************************************** // Expected data pattern when properly received by read capture // logic: // Based on pattern of ({rise,fall}) = // 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 // Each nibble will look like: // bit3: 1, 0, 1, 0, 0, 1, 1, 0 // bit2: 1, 0, 0, 1, 1, 0, 0, 1 // bit1: 1, 0, 1, 0, 0, 1, 0, 1 // bit0: 1, 0, 0, 1, 1, 0, 1, 0 // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN // and the actual training pattern contents change //***************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_pat_div4 // FF00AA5555AA9966 assign pat_rise0[3] = 1'b1; assign pat_fall0[3] = 1'b0; assign pat_rise1[3] = 1'b1; assign pat_fall1[3] = 1'b0; assign pat_rise2[3] = 1'b0; assign pat_fall2[3] = 1'b1; assign pat_rise3[3] = 1'b1; assign pat_fall3[3] = 1'b0; assign pat_rise0[2] = 1'b1; assign pat_fall0[2] = 1'b0; assign pat_rise1[2] = 1'b0; assign pat_fall1[2] = 1'b1; assign pat_rise2[2] = 1'b1; assign pat_fall2[2] = 1'b0; assign pat_rise3[2] = 1'b0; assign pat_fall3[2] = 1'b1; assign pat_rise0[1] = 1'b1; assign pat_fall0[1] = 1'b0; assign pat_rise1[1] = 1'b1; assign pat_fall1[1] = 1'b0; assign pat_rise2[1] = 1'b0; assign pat_fall2[1] = 1'b1; assign pat_rise3[1] = 1'b0; assign pat_fall3[1] = 1'b1; assign pat_rise0[0] = 1'b1; assign pat_fall0[0] = 1'b0; assign pat_rise1[0] = 1'b0; assign pat_fall1[0] = 1'b1; assign pat_rise2[0] = 1'b1; assign pat_fall2[0] = 1'b0; assign pat_rise3[0] = 1'b1; assign pat_fall3[0] = 1'b0; // Pattern to distinguish between early write and incorrect read // BB11EE4444EEDD88 assign early_rise0[3] = 1'b1; assign early_fall0[3] = 1'b0; assign early_rise1[3] = 1'b1; assign early_fall1[3] = 1'b0; assign early_rise2[3] = 1'b0; assign early_fall2[3] = 1'b1; assign early_rise3[3] = 1'b1; assign early_fall3[3] = 1'b1; assign early_rise0[2] = 1'b0; assign early_fall0[2] = 1'b0; assign early_rise1[2] = 1'b1; assign early_fall1[2] = 1'b1; assign early_rise2[2] = 1'b1; assign early_fall2[2] = 1'b1; assign early_rise3[2] = 1'b1; assign early_fall3[2] = 1'b0; assign early_rise0[1] = 1'b1; assign early_fall0[1] = 1'b0; assign early_rise1[1] = 1'b1; assign early_fall1[1] = 1'b0; assign early_rise2[1] = 1'b0; assign early_fall2[1] = 1'b1; assign early_rise3[1] = 1'b0; assign early_fall3[1] = 1'b0; assign early_rise0[0] = 1'b1; assign early_fall0[0] = 1'b1; assign early_rise1[0] = 1'b0; assign early_fall1[0] = 1'b0; assign early_rise2[0] = 1'b0; assign early_fall2[0] = 1'b0; assign early_rise3[0] = 1'b1; assign early_fall3[0] = 1'b0; end else if (nCK_PER_CLK == 2) begin: gen_pat_div2 // First cycle pattern FF00AA55 assign pat1_rise0[3] = 1'b1; assign pat1_fall0[3] = 1'b0; assign pat1_rise1[3] = 1'b1; assign pat1_fall1[3] = 1'b0; assign pat1_rise0[2] = 1'b1; assign pat1_fall0[2] = 1'b0; assign pat1_rise1[2] = 1'b0; assign pat1_fall1[2] = 1'b1; assign pat1_rise0[1] = 1'b1; assign pat1_fall0[1] = 1'b0; assign pat1_rise1[1] = 1'b1; assign pat1_fall1[1] = 1'b0; assign pat1_rise0[0] = 1'b1; assign pat1_fall0[0] = 1'b0; assign pat1_rise1[0] = 1'b0; assign pat1_fall1[0] = 1'b1; // Second cycle pattern 55AA9966 assign pat2_rise0[3] = 1'b0; assign pat2_fall0[3] = 1'b1; assign pat2_rise1[3] = 1'b1; assign pat2_fall1[3] = 1'b0; assign pat2_rise0[2] = 1'b1; assign pat2_fall0[2] = 1'b0; assign pat2_rise1[2] = 1'b0; assign pat2_fall1[2] = 1'b1; assign pat2_rise0[1] = 1'b0; assign pat2_fall0[1] = 1'b1; assign pat2_rise1[1] = 1'b0; assign pat2_fall1[1] = 1'b1; assign pat2_rise0[0] = 1'b1; assign pat2_fall0[0] = 1'b0; assign pat2_rise1[0] = 1'b1; assign pat2_fall1[0] = 1'b0; //Pattern to distinguish between early write and incorrect read // First cycle pattern AA5555AA assign early1_rise0[3] = 2'b1; assign early1_fall0[3] = 2'b0; assign early1_rise1[3] = 2'b0; assign early1_fall1[3] = 2'b1; assign early1_rise0[2] = 2'b0; assign early1_fall0[2] = 2'b1; assign early1_rise1[2] = 2'b1; assign early1_fall1[2] = 2'b0; assign early1_rise0[1] = 2'b1; assign early1_fall0[1] = 2'b0; assign early1_rise1[1] = 2'b0; assign early1_fall1[1] = 2'b1; assign early1_rise0[0] = 2'b0; assign early1_fall0[0] = 2'b1; assign early1_rise1[0] = 2'b1; assign early1_fall1[0] = 2'b0; // Second cycle pattern 9966BB11 assign early2_rise0[3] = 2'b1; assign early2_fall0[3] = 2'b0; assign early2_rise1[3] = 2'b1; assign early2_fall1[3] = 2'b0; assign early2_rise0[2] = 2'b0; assign early2_fall0[2] = 2'b1; assign early2_rise1[2] = 2'b0; assign early2_fall1[2] = 2'b0; assign early2_rise0[1] = 2'b0; assign early2_fall0[1] = 2'b1; assign early2_rise1[1] = 2'b1; assign early2_fall1[1] = 2'b0; assign early2_rise0[0] = 2'b1; assign early2_fall0[0] = 2'b0; assign early2_rise1[0] = 2'b1; assign early2_fall1[0] = 2'b1; end endgenerate // Each bit of each byte is compared to expected pattern. // This was done to prevent (and "drastically decrease") the chance that // invalid data clocked in when the DQ bus is tri-state (along with a // combination of the correct data) will resemble the expected data // pattern. A better fix for this is to change the training pattern and/or // make the pattern longer. generate genvar pt_i; if (nCK_PER_CLK == 4) begin: gen_pat_match_div4 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4]) pat_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4]) pat_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4]) pat_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4]) pat_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4]) pat_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4]) pat_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4]) pat_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4]) pat_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4]) early1_match_rise0_r[pt_i] <= #TCQ 1'b1; else early1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4]) early1_match_fall0_r[pt_i] <= #TCQ 1'b1; else early1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4]) early1_match_rise1_r[pt_i] <= #TCQ 1'b1; else early1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4]) early1_match_fall1_r[pt_i] <= #TCQ 1'b1; else early1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4]) early1_match_rise2_r[pt_i] <= #TCQ 1'b1; else early1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4]) early1_match_fall2_r[pt_i] <= #TCQ 1'b1; else early1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == early_rise0[pt_i%4]) early1_match_rise3_r[pt_i] <= #TCQ 1'b1; else early1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == early_fall0[pt_i%4]) early1_match_fall3_r[pt_i] <= #TCQ 1'b1; else early1_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4]) early2_match_rise0_r[pt_i] <= #TCQ 1'b1; else early2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4]) early2_match_fall0_r[pt_i] <= #TCQ 1'b1; else early2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4]) early2_match_rise1_r[pt_i] <= #TCQ 1'b1; else early2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4]) early2_match_fall1_r[pt_i] <= #TCQ 1'b1; else early2_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == early_rise0[pt_i%4]) early2_match_rise2_r[pt_i] <= #TCQ 1'b1; else early2_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == early_fall0[pt_i%4]) early2_match_fall2_r[pt_i] <= #TCQ 1'b1; else early2_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == early_rise1[pt_i%4]) early2_match_rise3_r[pt_i] <= #TCQ 1'b1; else early2_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == early_fall1[pt_i%4]) early2_match_fall3_r[pt_i] <= #TCQ 1'b1; else early2_match_fall3_r[pt_i] <= #TCQ 1'b0; end end always @(posedge clk) begin pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r; pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r; pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r; pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r; pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r; pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r; pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r; pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r; pat_data_match_r <= #TCQ (pat_match_rise0_and_r && pat_match_fall0_and_r && pat_match_rise1_and_r && pat_match_fall1_and_r && pat_match_rise2_and_r && pat_match_fall2_and_r && pat_match_rise3_and_r && pat_match_fall3_and_r); pat_data_match_valid_r <= #TCQ rd_active_r3; end always @(posedge clk) begin early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r; early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r; early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r; early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r; early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r; early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r; early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r; early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r; early1_data_match_r <= #TCQ (early1_match_rise0_and_r && early1_match_fall0_and_r && early1_match_rise1_and_r && early1_match_fall1_and_r && early1_match_rise2_and_r && early1_match_fall2_and_r && early1_match_rise3_and_r && early1_match_fall3_and_r); end always @(posedge clk) begin early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r; early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r; early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r; early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r; early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r; early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r; early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r; early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r; early2_data_match_r <= #TCQ (early2_match_rise0_and_r && early2_match_fall0_and_r && early2_match_rise1_and_r && early2_match_fall1_and_r && early2_match_rise2_and_r && early2_match_fall2_and_r && early2_match_rise3_and_r && early2_match_fall3_and_r); end end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4]) pat2_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4]) pat2_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4]) pat2_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4]) pat2_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat2_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4]) early1_match_rise0_r[pt_i] <= #TCQ 1'b1; else early1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4]) early1_match_fall0_r[pt_i] <= #TCQ 1'b1; else early1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4]) early1_match_rise1_r[pt_i] <= #TCQ 1'b1; else early1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4]) early1_match_fall1_r[pt_i] <= #TCQ 1'b1; else early1_match_fall1_r[pt_i] <= #TCQ 1'b0; end // early2 in this case does not mean 2 cycles early but // the second cycle of read data in 2:1 mode always @(posedge clk) begin if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4]) early2_match_rise0_r[pt_i] <= #TCQ 1'b1; else early2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4]) early2_match_fall0_r[pt_i] <= #TCQ 1'b1; else early2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4]) early2_match_rise1_r[pt_i] <= #TCQ 1'b1; else early2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4]) early2_match_fall1_r[pt_i] <= #TCQ 1'b1; else early2_match_fall1_r[pt_i] <= #TCQ 1'b0; end end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r); pat1_data_match_r1 <= #TCQ pat1_data_match_r; pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3; pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3; pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3; pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3; pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r && pat2_match_fall0_and_r && pat2_match_rise1_and_r && pat2_match_fall1_and_r); // For 2:1 mode, read valid is asserted for 2 clock cycles - // here we generate a "match valid" pulse that is only 1 clock // cycle wide that is simulatenous when the match calculation // is complete pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5; end always @(posedge clk) begin early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r; early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r; early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r; early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r; early1_data_match_r <= #TCQ (early1_match_rise0_and_r && early1_match_fall0_and_r && early1_match_rise1_and_r && early1_match_fall1_and_r); early1_data_match_r1 <= #TCQ early1_data_match_r; early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3; early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3; early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3; early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3; early2_data_match_r <= #TCQ (early2_match_rise0_and_r && early2_match_fall0_and_r && early2_match_rise1_and_r && early2_match_fall1_and_r); end end endgenerate // Need to delay it by 3 cycles in order to wait for Phaser_Out // coarse delay to take effect before issuing a write command always @(posedge clk) begin wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r; wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1; wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2; end always @(posedge clk) begin if (rst) tap_inc_wait_cnt <= #TCQ 'd0; else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) || (cal2_state_r == CAL2_IFIFO_RESET) || (cal2_state_r == CAL2_SANITY_WAIT)) tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1; else tap_inc_wait_cnt <= #TCQ 'd0; end always @(posedge clk) begin if (rst) not_empty_wait_cnt <= #TCQ 'd0; else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait) not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1; else not_empty_wait_cnt <= #TCQ 'd0; end always @(posedge clk) cal2_state_r1 <= #TCQ cal2_state_r; //***************************************************************** // Write Calibration state machine //***************************************************************** // when calibrating, check to see if the expected pattern is received. // Otherwise delay DQS to align to correct CK edge. // NOTES: // 1. An error condition can occur due to two reasons: // a. If the matching logic does not receive the expected data // pattern. However, the error may be "recoverable" because // the write calibration is still in progress. If an error is // found the write calibration logic delays DQS by an additional // clock cycle and restarts the pattern detection process. // By design, if the write path timing is incorrect, the correct // data pattern will never be detected. // b. Valid data not found even after incrementing Phaser_Out // coarse delay line. always @(posedge clk) begin if (rst) begin wrcal_dqs_cnt_r <= #TCQ 'b0; cal2_done_r <= #TCQ 1'b0; cal2_prech_req_r <= #TCQ 1'b0; cal2_state_r <= #TCQ CAL2_IDLE; wrcal_pat_err <= #TCQ 1'b0; wrcal_pat_resume_r <= #TCQ 1'b0; wrcal_act_req <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; temp_wrcal_done <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b0; early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b0; idelay_ld <= #TCQ 1'b0; idelay_ld_done <= #TCQ 1'b0; pat1_detect <= #TCQ 1'b0; early1_detect <= #TCQ 1'b0; wrcal_sanity_chk_done <= #TCQ 1'b0; wrcal_sanity_chk_err <= #TCQ 1'b0; end else begin cal2_prech_req_r <= #TCQ 1'b0; case (cal2_state_r) CAL2_IDLE: begin wrcal_pat_err <= #TCQ 1'b0; if (wrcal_start) begin cal2_if_reset <= #TCQ 1'b0; if (SIM_CAL_OPTION == "SKIP_CAL") // If skip write calibration, then proceed to end. cal2_state_r <= #TCQ CAL2_DONE; else cal2_state_r <= #TCQ CAL2_READ_WAIT; end end // General wait state to wait for read data to be output by the // IN_FIFO CAL2_READ_WAIT: begin wrcal_pat_resume_r <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; // Wait until read data is received, and pattern matching // calculation is complete. NOTE: Need to add a timeout here // in case for some reason data is never received (or rather // the PHASER_IN and IN_FIFO think they never receives data) if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin if (pat_data_match_r) // If found data match, then move on to next DQS group cal2_state_r <= #TCQ CAL2_NEXT_DQS; else begin if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_ERR; // If writes are one or two cycles early then redo // write leveling for the byte else if (early1_data_match_r) begin early1_data <= #TCQ 1'b1; early2_data <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; end else if (early2_data_match_r) begin early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b1; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; // Read late due to incorrect MPR idelay value // Decrement Idelay to '0'for the current byte end else if (~idelay_ld_done) begin cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC; idelay_ld <= #TCQ 1'b1; end else cal2_state_r <= #TCQ CAL2_ERR; end end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin if ((pat1_data_match_r1 && pat2_data_match_r) || (pat1_detect && pat2_data_match_r)) // If found data match, then move on to next DQS group cal2_state_r <= #TCQ CAL2_NEXT_DQS; else if (pat1_data_match_r1 && ~pat2_data_match_r) begin cal2_state_r <= #TCQ CAL2_READ_WAIT; pat1_detect <= #TCQ 1'b1; end else begin // If writes are one or two cycles early then redo // write leveling for the byte if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_ERR; else if ((early1_data_match_r1 && early2_data_match_r) || (early1_detect && early2_data_match_r)) begin early1_data <= #TCQ 1'b1; early2_data <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; end else if (early1_data_match_r1 && ~early2_data_match_r) begin early1_detect <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_READ_WAIT; // Read late due to incorrect MPR idelay value // Decrement Idelay to '0'for the current byte end else if (~idelay_ld_done) begin cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC; idelay_ld <= #TCQ 1'b1; end else cal2_state_r <= #TCQ CAL2_ERR; end end else if (not_empty_wait_cnt == 'd31) cal2_state_r <= #TCQ CAL2_ERR; end CAL2_WRLVL_WAIT: begin early1_detect <= #TCQ 1'b0; if (wrlvl_byte_done && ~wrlvl_byte_done_r) wrlvl_byte_redo <= #TCQ 1'b0; if (wrlvl_byte_done) begin if (rd_active_r1 && ~rd_active_r) begin cal2_state_r <= #TCQ CAL2_IFIFO_RESET; cal2_if_reset <= #TCQ 1'b1; early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b0; end end end CAL2_DQ_IDEL_DEC: begin if (tap_inc_wait_cnt == 'd4) begin idelay_ld <= #TCQ 1'b0; cal2_state_r <= #TCQ CAL2_IFIFO_RESET; cal2_if_reset <= #TCQ 1'b1; idelay_ld_done <= #TCQ 1'b1; end end CAL2_IFIFO_RESET: begin if (tap_inc_wait_cnt == 'd15) begin cal2_if_reset <= #TCQ 1'b0; if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_DONE; else if (idelay_ld_done) begin wrcal_pat_resume_r <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_READ_WAIT; end else cal2_state_r <= #TCQ CAL2_IDLE; end end // Final processing for current DQS group. Move on to next group CAL2_NEXT_DQS: begin // At this point, we've just found the correct pattern for the // current DQS group. // Request bank/row precharge, and wait for its completion. Always // precharge after each DQS group to avoid tRAS(max) violation //verilint STARC-2.2.3.3 off if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin cal2_prech_req_r <= #TCQ 1'b0; wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1; cal2_state_r <= #TCQ CAL2_SANITY_WAIT; end else cal2_prech_req_r <= #TCQ 1'b1; idelay_ld_done <= #TCQ 1'b0; pat1_detect <= #TCQ 1'b0; if (prech_done) if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) || (wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin // If either FAST_CAL is enabled and first DQS group is // finished, or if the last DQS group was just finished, // then end of write calibration if (wrcal_sanity_chk_r) begin cal2_if_reset <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_IFIFO_RESET; end else cal2_state_r <= #TCQ CAL2_DONE; end else begin // Continue to next DQS group wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1; cal2_state_r <= #TCQ CAL2_READ_WAIT; end end //verilint STARC-2.2.3.3 on CAL2_SANITY_WAIT: begin if (tap_inc_wait_cnt == 'd15) begin cal2_state_r <= #TCQ CAL2_READ_WAIT; wrcal_pat_resume_r <= #TCQ 1'b1; end end // Finished with read enable calibration CAL2_DONE: begin if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin cal2_done_r <= #TCQ 1'b0; wrcal_dqs_cnt_r <= #TCQ 'd0; cal2_state_r <= #TCQ CAL2_IDLE; end else cal2_done_r <= #TCQ 1'b1; cal2_prech_req_r <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; if (wrcal_sanity_chk_r) wrcal_sanity_chk_done <= #TCQ 1'b1; end // Assert error signal indicating that writes timing is incorrect CAL2_ERR: begin wrcal_pat_resume_r <= #TCQ 1'b0; if (wrcal_sanity_chk_r) wrcal_sanity_chk_err <= #TCQ 1'b1; else wrcal_pat_err <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_ERR; end endcase end end // Delay assertion of wrcal_done for write calibration by a few cycles after // we've reached CAL2_DONE always @(posedge clk) if (rst) cal2_done_r1 <= #TCQ 1'b0; else cal2_done_r1 <= #TCQ cal2_done_r; always @(posedge clk) if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r)) wrcal_done <= #TCQ 1'b0; else if (cal2_done_r) wrcal_done <= #TCQ 1'b1; endmodule
//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_wrlvl.v // /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ // \ \ / \ Date Created: Mon Jun 23 2008 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Memory initialization and overall master state control during // initialization and calibration. Specifically, the following functions // are performed: // 1. Memory initialization (initial AR, mode register programming, etc.) // 2. Initiating write leveling // 3. Generate training pattern writes for read leveling. Generate // memory readback for read leveling. // This module has a DFI interface for providing control/address and write // data to the rest of the PHY datapath during initialization/calibration. // Once initialization is complete, control is passed to the MC. // NOTES: // 1. Multiple CS (multi-rank) not supported // 2. DDR2 not supported // 3. ODT not supported //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_wrlvl.v,v 1.3 2011/06/24 14:49:00 mgeorge Exp $ **$Date: 2011/06/24 14:49:00 $ **$Author: mgeorge $ **$Revision: 1.3 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_wrlvl.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_wrlvl # ( parameter TCQ = 100, parameter DQS_CNT_WIDTH = 3, parameter DQ_WIDTH = 64, parameter DQS_WIDTH = 2, parameter DRAM_WIDTH = 8, parameter RANKS = 1, parameter nCK_PER_CLK = 4, parameter CLK_PERIOD = 4, parameter SIM_CAL_OPTION = "NONE" ) ( input clk, input rst, input phy_ctl_ready, input wr_level_start, input wl_sm_start, input wrlvl_final, input wrlvl_byte_redo, input [DQS_CNT_WIDTH:0] wrcal_cnt, input early1_data, input early2_data, input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt, input oclkdelay_calib_done, input [(DQ_WIDTH)-1:0] rd_data_rise0, output reg wrlvl_byte_done, output reg dqs_po_dec_done /* synthesis syn_maxfan = 2 */, output phy_ctl_rdy_dly, output reg wr_level_done /* synthesis syn_maxfan = 2 */, // to phy_init for cs logic output wrlvl_rank_done, output done_dqs_tap_inc, output [DQS_CNT_WIDTH:0] po_stg2_wl_cnt, // Fine delay line used only during write leveling // Inc/dec Phaser_Out fine delay line output reg dqs_po_stg2_f_incdec, // Enable Phaser_Out fine delay inc/dec output reg dqs_po_en_stg2_f, // Coarse delay line used during write leveling // only if 64 taps of fine delay line were not // sufficient to detect a 0->1 transition // Inc Phaser_Out coarse delay line output reg dqs_wl_po_stg2_c_incdec, // Enable Phaser_Out coarse delay inc/dec output reg dqs_wl_po_en_stg2_c, // Read Phaser_Out delay value input [8:0] po_counter_read_val, // output reg dqs_wl_po_stg2_load, // output reg [8:0] dqs_wl_po_stg2_reg_l, // CK edge undetected output reg wrlvl_err, output reg [3*DQS_WIDTH-1:0] wl_po_coarse_cnt, output reg [6*DQS_WIDTH-1:0] wl_po_fine_cnt, // Debug ports output [5:0] dbg_wl_tap_cnt, output dbg_wl_edge_detect_valid, output [(DQS_WIDTH)-1:0] dbg_rd_data_edge_detect, output [DQS_CNT_WIDTH:0] dbg_dqs_count, output [4:0] dbg_wl_state, output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, output [255:0] dbg_phy_wrlvl ); localparam WL_IDLE = 5'h0; localparam WL_INIT = 5'h1; localparam WL_INIT_FINE_INC = 5'h2; localparam WL_INIT_FINE_INC_WAIT1= 5'h3; localparam WL_INIT_FINE_INC_WAIT = 5'h4; localparam WL_INIT_FINE_DEC = 5'h5; localparam WL_INIT_FINE_DEC_WAIT = 5'h6; localparam WL_FINE_INC = 5'h7; localparam WL_WAIT = 5'h8; localparam WL_EDGE_CHECK = 5'h9; localparam WL_DQS_CHECK = 5'hA; localparam WL_DQS_CNT = 5'hB; localparam WL_2RANK_TAP_DEC = 5'hC; localparam WL_2RANK_DQS_CNT = 5'hD; localparam WL_FINE_DEC = 5'hE; localparam WL_FINE_DEC_WAIT = 5'hF; localparam WL_CORSE_INC = 5'h10; localparam WL_CORSE_INC_WAIT = 5'h11; localparam WL_CORSE_INC_WAIT1 = 5'h12; localparam WL_CORSE_INC_WAIT2 = 5'h13; localparam WL_CORSE_DEC = 5'h14; localparam WL_CORSE_DEC_WAIT = 5'h15; localparam WL_CORSE_DEC_WAIT1 = 5'h16; localparam WL_FINE_INC_WAIT = 5'h17; localparam WL_2RANK_FINAL_TAP = 5'h18; localparam WL_INIT_FINE_DEC_WAIT1= 5'h19; localparam WL_FINE_DEC_WAIT1 = 5'h1A; localparam WL_CORSE_INC_WAIT_TMP = 5'h1B; localparam COARSE_TAPS = 7; localparam FAST_CAL_FINE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 45 : 48; localparam FAST_CAL_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 1 : 2; localparam REDO_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 2 : 5; integer i, j, k, l, p, q, r, s, t, m, n, u, v, w, x,y; reg phy_ctl_ready_r1; reg phy_ctl_ready_r2; reg phy_ctl_ready_r3; reg phy_ctl_ready_r4; reg phy_ctl_ready_r5; reg phy_ctl_ready_r6; (* max_fanout = 50 *) reg [DQS_CNT_WIDTH:0] dqs_count_r; reg [1:0] rank_cnt_r; reg [DQS_WIDTH-1:0] rd_data_rise_wl_r; reg [DQS_WIDTH-1:0] rd_data_previous_r; reg [DQS_WIDTH-1:0] rd_data_edge_detect_r; reg wr_level_done_r; reg wrlvl_rank_done_r; reg wr_level_start_r; reg [4:0] wl_state_r, wl_state_r1; reg inhibit_edge_detect_r; reg wl_edge_detect_valid_r; reg [5:0] wl_tap_count_r; reg [5:0] fine_dec_cnt; reg [5:0] fine_inc[0:DQS_WIDTH-1]; // DQS_WIDTH number of counters 6-bit each reg [2:0] corse_dec[0:DQS_WIDTH-1]; reg [2:0] corse_inc[0:DQS_WIDTH-1]; reg dq_cnt_inc; reg [3:0] stable_cnt; reg flag_ck_negedge; //reg past_negedge; reg flag_init; reg [2:0] corse_cnt[0:DQS_WIDTH-1]; reg [3*DQS_WIDTH-1:0] corse_cnt_dbg; reg [2:0] wl_corse_cnt[0:RANKS-1][0:DQS_WIDTH-1]; //reg [3*DQS_WIDTH-1:0] coarse_tap_inc; reg [2:0] final_coarse_tap[0:DQS_WIDTH-1]; reg [5:0] add_smallest[0:DQS_WIDTH-1]; reg [5:0] add_largest[0:DQS_WIDTH-1]; //reg [6*DQS_WIDTH-1:0] fine_tap_inc; //reg [6*DQS_WIDTH-1:0] fine_tap_dec; reg wr_level_done_r1; reg wr_level_done_r2; reg wr_level_done_r3; reg wr_level_done_r4; reg wr_level_done_r5; reg [5:0] wl_dqs_tap_count_r[0:RANKS-1][0:DQS_WIDTH-1]; reg [5:0] smallest[0:DQS_WIDTH-1]; reg [5:0] largest[0:DQS_WIDTH-1]; reg [5:0] final_val[0:DQS_WIDTH-1]; reg [5:0] po_dec_cnt[0:DQS_WIDTH-1]; reg done_dqs_dec; reg [8:0] po_rdval_cnt; reg po_cnt_dec; reg po_dec_done; reg dual_rnk_dec; wire [DQS_CNT_WIDTH+2:0] dqs_count_w; reg [5:0] fast_cal_fine_cnt; reg [2:0] fast_cal_coarse_cnt; reg wrlvl_byte_redo_r; reg [2:0] wrlvl_redo_corse_inc; reg wrlvl_final_r; reg final_corse_dec; wire [DQS_CNT_WIDTH+2:0] oclk_count_w; reg wrlvl_tap_done_r ; reg [3:0] wait_cnt; reg [3:0] incdec_wait_cnt; // Debug ports assign dbg_wl_edge_detect_valid = wl_edge_detect_valid_r; assign dbg_rd_data_edge_detect = rd_data_edge_detect_r; assign dbg_wl_tap_cnt = wl_tap_count_r; assign dbg_dqs_count = dqs_count_r; assign dbg_wl_state = wl_state_r; assign dbg_wrlvl_fine_tap_cnt = wl_po_fine_cnt; assign dbg_wrlvl_coarse_tap_cnt = wl_po_coarse_cnt; always @(*) begin for (v = 0; v < DQS_WIDTH; v = v + 1) corse_cnt_dbg[3*v+:3] = corse_cnt[v]; end assign dbg_phy_wrlvl[0+:27] = corse_cnt_dbg; assign dbg_phy_wrlvl[27+:5] = wl_state_r; assign dbg_phy_wrlvl[32+:4] = dqs_count_r; assign dbg_phy_wrlvl[36+:9] = rd_data_rise_wl_r; assign dbg_phy_wrlvl[45+:9] = rd_data_previous_r; assign dbg_phy_wrlvl[54+:4] = stable_cnt; assign dbg_phy_wrlvl[58] = 'd0; assign dbg_phy_wrlvl[59] = flag_ck_negedge; assign dbg_phy_wrlvl [60] = wl_edge_detect_valid_r; assign dbg_phy_wrlvl [61+:6] = wl_tap_count_r; assign dbg_phy_wrlvl [67+:9] = rd_data_edge_detect_r; assign dbg_phy_wrlvl [76+:54] = wl_po_fine_cnt; assign dbg_phy_wrlvl [130+:27] = wl_po_coarse_cnt; //************************************************************************** // DQS count to hard PHY during write leveling using Phaser_OUT Stage2 delay //************************************************************************** assign po_stg2_wl_cnt = dqs_count_r; assign wrlvl_rank_done = wrlvl_rank_done_r; assign done_dqs_tap_inc = done_dqs_dec; assign phy_ctl_rdy_dly = phy_ctl_ready_r6; always @(posedge clk) begin phy_ctl_ready_r1 <= #TCQ phy_ctl_ready; phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1; phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2; phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3; phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4; phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5; wrlvl_byte_redo_r <= #TCQ wrlvl_byte_redo; wrlvl_final_r <= #TCQ wrlvl_final; if ((wrlvl_byte_redo && ~wrlvl_byte_redo_r) || (wrlvl_final && ~wrlvl_final_r)) wr_level_done <= #TCQ 1'b0; else wr_level_done <= #TCQ done_dqs_dec; end // Status signal that will be asserted once the first // pass of write leveling is done. always @(posedge clk) begin if(rst) begin wrlvl_tap_done_r <= #TCQ 1'b0 ; end else begin if(wrlvl_tap_done_r == 1'b0) begin if(oclkdelay_calib_done) begin wrlvl_tap_done_r <= #TCQ 1'b1 ; end end end end always @(posedge clk) begin if (rst || po_cnt_dec) wait_cnt <= #TCQ 'd8; else if (phy_ctl_ready_r6 && (wait_cnt > 'd0)) wait_cnt <= #TCQ wait_cnt - 1; end always @(posedge clk) begin if (rst) begin po_rdval_cnt <= #TCQ 'd0; end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin po_rdval_cnt <= #TCQ po_counter_read_val; end else if (po_rdval_cnt > 'd0) begin if (po_cnt_dec) po_rdval_cnt <= #TCQ po_rdval_cnt - 1; else po_rdval_cnt <= #TCQ po_rdval_cnt; end else if (po_rdval_cnt == 'd0) begin po_rdval_cnt <= #TCQ po_rdval_cnt; end end always @(posedge clk) begin if (rst || (po_rdval_cnt == 'd0)) po_cnt_dec <= #TCQ 1'b0; else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (wait_cnt == 'd1)) po_cnt_dec <= #TCQ 1'b1; else po_cnt_dec <= #TCQ 1'b0; end always @(posedge clk) begin if (rst) po_dec_done <= #TCQ 1'b0; else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) || (phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin po_dec_done <= #TCQ 1'b1; end end always @(posedge clk) begin dqs_po_dec_done <= #TCQ po_dec_done; wr_level_done_r1 <= #TCQ wr_level_done_r; wr_level_done_r2 <= #TCQ wr_level_done_r1; wr_level_done_r3 <= #TCQ wr_level_done_r2; wr_level_done_r4 <= #TCQ wr_level_done_r3; wr_level_done_r5 <= #TCQ wr_level_done_r4; for (l = 0; l < DQS_WIDTH; l = l + 1) begin wl_po_coarse_cnt[3*l+:3] <= #TCQ final_coarse_tap[l]; if ((RANKS == 1) || ~oclkdelay_calib_done) wl_po_fine_cnt[6*l+:6] <= #TCQ smallest[l]; else wl_po_fine_cnt[6*l+:6] <= #TCQ final_val[l]; end end generate if (RANKS == 2) begin: dual_rank always @(posedge clk) begin if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) || (wrlvl_final && ~wrlvl_final_r)) done_dqs_dec <= #TCQ 1'b0; else if ((SIM_CAL_OPTION == "FAST_CAL") || ~oclkdelay_calib_done) done_dqs_dec <= #TCQ wr_level_done_r; else if (wr_level_done_r5 && (wl_state_r == WL_IDLE)) done_dqs_dec <= #TCQ 1'b1; end end else begin: single_rank always @(posedge clk) begin if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) || (wrlvl_final && ~wrlvl_final_r)) done_dqs_dec <= #TCQ 1'b0; else if (~oclkdelay_calib_done) done_dqs_dec <= #TCQ wr_level_done_r; else if (wr_level_done_r3 && ~wr_level_done_r4) done_dqs_dec <= #TCQ 1'b1; end end endgenerate always @(posedge clk) if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r)) wrlvl_byte_done <= #TCQ 1'b0; else if (wrlvl_byte_redo && wr_level_done_r3 && ~wr_level_done_r4) wrlvl_byte_done <= #TCQ 1'b1; // Storing DQS tap values at the end of each DQS write leveling always @(posedge clk) begin if (rst) begin for (k = 0; k < RANKS; k = k + 1) begin: rst_wl_dqs_tap_count_loop for (n = 0; n < DQS_WIDTH; n = n + 1) begin wl_corse_cnt[k][n] <= #TCQ 'b0; wl_dqs_tap_count_r[k][n] <= #TCQ 'b0; end end end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1) | (wl_state_r == WL_2RANK_TAP_DEC)) begin wl_dqs_tap_count_r[rank_cnt_r][dqs_count_r] <= #TCQ wl_tap_count_r; wl_corse_cnt[rank_cnt_r][dqs_count_r] <= #TCQ corse_cnt[dqs_count_r]; end else if ((SIM_CAL_OPTION == "FAST_CAL") & (wl_state_r == WL_DQS_CHECK)) begin for (p = 0; p < RANKS; p = p +1) begin: dqs_tap_rank_cnt for(q = 0; q < DQS_WIDTH; q = q +1) begin: dqs_tap_dqs_cnt wl_dqs_tap_count_r[p][q] <= #TCQ wl_tap_count_r; wl_corse_cnt[p][q] <= #TCQ corse_cnt[0]; end end end end // Convert coarse delay to fine taps in case of unequal number of coarse // taps between ranks. Assuming a difference of 1 coarse tap counts // between ranks. A common fine and coarse tap value must be used for both ranks // because Phaser_Out has only one rank register. // Coarse tap1 = period(ps)*93/360 = 34 fine taps // Other coarse taps = period(ps)*103/360 = 38 fine taps generate genvar cnt; if (RANKS == 2) begin // Dual rank for(cnt = 0; cnt < DQS_WIDTH; cnt = cnt +1) begin: coarse_dqs_cnt always @(posedge clk) begin if (rst) begin //coarse_tap_inc[3*cnt+:3] <= #TCQ 'b0; add_smallest[cnt] <= #TCQ 'd0; add_largest[cnt] <= #TCQ 'd0; final_coarse_tap[cnt] <= #TCQ 'd0; end else if (wr_level_done_r1 & ~wr_level_done_r2) begin if (~oclkdelay_calib_done) begin for(y = 0 ; y < DQS_WIDTH; y = y+1) begin final_coarse_tap[y] <= #TCQ wl_corse_cnt[0][y]; add_smallest[y] <= #TCQ 'd0; add_largest[y] <= #TCQ 'd0; end end else if (wl_corse_cnt[0][cnt] == wl_corse_cnt[1][cnt]) begin // Both ranks have use the same number of coarse delay taps. // No conversion of coarse tap to fine taps required. //coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3]; final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt]; add_smallest[cnt] <= #TCQ 'd0; add_largest[cnt] <= #TCQ 'd0; end else if (wl_corse_cnt[0][cnt] < wl_corse_cnt[1][cnt]) begin // Rank 0 uses fewer coarse delay taps than rank1. // conversion of coarse tap to fine taps required for rank1. // The final coarse count will the smaller value. //coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3] - 1; final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt] - 1; if (|wl_corse_cnt[0][cnt]) // Coarse tap 2 or higher being converted to fine taps // This will be added to 'largest' value in final_val // computation add_largest[cnt] <= #TCQ 'd38; else // Coarse tap 1 being converted to fine taps // This will be added to 'largest' value in final_val // computation add_largest[cnt] <= #TCQ 'd34; end else if (wl_corse_cnt[0][cnt] > wl_corse_cnt[1][cnt]) begin // This may be an unlikely scenario in a real system. // Rank 0 uses more coarse delay taps than rank1. // conversion of coarse tap to fine taps required. //coarse_tap_inc[3*cnt+:3] <= #TCQ 'd0; final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt]; if (|wl_corse_cnt[1][cnt]) // Coarse tap 2 or higher being converted to fine taps // This will be added to 'smallest' value in final_val // computation add_smallest[cnt] <= #TCQ 'd38; else // Coarse tap 1 being converted to fine taps // This will be added to 'smallest' value in // final_val computation add_smallest[cnt] <= #TCQ 'd34; end end end end end else begin // Single rank always @(posedge clk) begin //coarse_tap_inc <= #TCQ 'd0; for(w = 0; w < DQS_WIDTH; w = w + 1) begin final_coarse_tap[w] <= #TCQ wl_corse_cnt[0][w]; add_smallest[w] <= #TCQ 'd0; add_largest[w] <= #TCQ 'd0; end end end endgenerate // Determine delay value for DQS in multirank system // Assuming delay value is the smallest for rank 0 DQS // and largest delay value for rank 4 DQS // Set to smallest + ((largest-smallest)/2) always @(posedge clk) begin if (rst) begin for(x = 0; x < DQS_WIDTH; x = x +1) begin smallest[x] <= #TCQ 'b0; largest[x] <= #TCQ 'b0; end end else if ((wl_state_r == WL_DQS_CNT) & wrlvl_byte_redo) begin smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_2RANK_TAP_DEC)) begin smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[RANKS-1][dqs_count_r]; end else if (((SIM_CAL_OPTION == "FAST_CAL") | (~oclkdelay_calib_done & ~wrlvl_byte_redo)) & wr_level_done_r1 & ~wr_level_done_r2) begin for(i = 0; i < DQS_WIDTH; i = i +1) begin: smallest_dqs smallest[i] <= #TCQ wl_dqs_tap_count_r[0][i]; largest[i] <= #TCQ wl_dqs_tap_count_r[0][i]; end end end // final_val to be used for all DQSs in all ranks genvar wr_i; generate for (wr_i = 0; wr_i < DQS_WIDTH; wr_i = wr_i +1) begin: gen_final_tap always @(posedge clk) begin if (rst) final_val[wr_i] <= #TCQ 'b0; else if (wr_level_done_r2 && ~wr_level_done_r3) begin if (~oclkdelay_calib_done) final_val[wr_i] <= #TCQ (smallest[wr_i] + add_smallest[wr_i]); else if ((smallest[wr_i] + add_smallest[wr_i]) < (largest[wr_i] + add_largest[wr_i])) final_val[wr_i] <= #TCQ ((smallest[wr_i] + add_smallest[wr_i]) + (((largest[wr_i] + add_largest[wr_i]) - (smallest[wr_i] + add_smallest[wr_i]))/2)); else if ((smallest[wr_i] + add_smallest[wr_i]) > (largest[wr_i] + add_largest[wr_i])) final_val[wr_i] <= #TCQ ((largest[wr_i] + add_largest[wr_i]) + (((smallest[wr_i] + add_smallest[wr_i]) - (largest[wr_i] + add_largest[wr_i]))/2)); else if ((smallest[wr_i] + add_smallest[wr_i]) == (largest[wr_i] + add_largest[wr_i])) final_val[wr_i] <= #TCQ (largest[wr_i] + add_largest[wr_i]); end end end endgenerate // // fine tap inc/dec value for all DQSs in all ranks // genvar dqs_i; // generate // for (dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i +1) begin: gen_fine_tap // always @(posedge clk) begin // if (rst) // fine_tap_inc[6*dqs_i+:6] <= #TCQ 'd0; // //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0; // else if (wr_level_done_r3 && ~wr_level_done_r4) begin // fine_tap_inc[6*dqs_i+:6] <= #TCQ final_val[6*dqs_i+:6]; // //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0; // end // end // endgenerate // Inc/Dec Phaser_Out stage 2 fine delay line always @(posedge clk) begin if (rst) begin // Fine delay line used only during write leveling dqs_po_stg2_f_incdec <= #TCQ 1'b0; dqs_po_en_stg2_f <= #TCQ 1'b0; // Dec Phaser_Out fine delay (1)before write leveling, // (2)if no 0 to 1 transition detected with 63 fine delay taps, or // (3)dual rank case where fine taps for the first rank need to be 0 end else if (po_cnt_dec || (wl_state_r == WL_INIT_FINE_DEC) || (wl_state_r == WL_FINE_DEC)) begin dqs_po_stg2_f_incdec <= #TCQ 1'b0; dqs_po_en_stg2_f <= #TCQ 1'b1; // Inc Phaser_Out fine delay during write leveling end else if ((wl_state_r == WL_INIT_FINE_INC) || (wl_state_r == WL_FINE_INC)) begin dqs_po_stg2_f_incdec <= #TCQ 1'b1; dqs_po_en_stg2_f <= #TCQ 1'b1; end else begin dqs_po_stg2_f_incdec <= #TCQ 1'b0; dqs_po_en_stg2_f <= #TCQ 1'b0; end end // Inc Phaser_Out stage 2 Coarse delay line always @(posedge clk) begin if (rst) begin // Coarse delay line used during write leveling // only if no 0->1 transition undetected with 64 // fine delay line taps dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0; dqs_wl_po_en_stg2_c <= #TCQ 1'b0; end else if (wl_state_r == WL_CORSE_INC) begin // Inc Phaser_Out coarse delay during write leveling dqs_wl_po_stg2_c_incdec <= #TCQ 1'b1; dqs_wl_po_en_stg2_c <= #TCQ 1'b1; end else begin dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0; dqs_wl_po_en_stg2_c <= #TCQ 1'b0; end end // only storing the rise data for checking. The data comming back during // write leveling will be a static value. Just checking for rise data is // enough. genvar rd_i; generate for(rd_i = 0; rd_i < DQS_WIDTH; rd_i = rd_i +1)begin: gen_rd always @(posedge clk) rd_data_rise_wl_r[rd_i] <= #TCQ |rd_data_rise0[(rd_i*DRAM_WIDTH)+DRAM_WIDTH-1:rd_i*DRAM_WIDTH]; end endgenerate // storing the previous data for checking later. always @(posedge clk)begin if ((wl_state_r == WL_INIT) || //(wl_state_r == WL_INIT_FINE_INC_WAIT) || //(wl_state_r == WL_INIT_FINE_INC_WAIT1) || ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)) || (wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_FINE_DEC_WAIT) || (wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) || (wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2) || ((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r))) rd_data_previous_r <= #TCQ rd_data_rise_wl_r; end // changed stable count from 3 to 7 because of fine tap resolution always @(posedge clk)begin if (rst | (wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_2RANK_TAP_DEC) | (wl_state_r == WL_FINE_DEC) | (rd_data_previous_r[dqs_count_r] != rd_data_rise_wl_r[dqs_count_r]) | (wl_state_r1 == WL_INIT_FINE_DEC)) stable_cnt <= #TCQ 'd0; else if ((wl_tap_count_r > 6'd0) & (((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)) | ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)))) begin if ((rd_data_previous_r[dqs_count_r] == rd_data_rise_wl_r[dqs_count_r]) & (stable_cnt < 'd14)) stable_cnt <= #TCQ stable_cnt + 1; end end // Signal to ensure that flag_ck_negedge does not incorrectly assert // when DQS is very close to CK rising edge //always @(posedge clk) begin // if (rst | (wl_state_r == WL_DQS_CNT) | // (wl_state_r == WL_DQS_CHECK) | wr_level_done_r) // past_negedge <= #TCQ 1'b0; // else if (~flag_ck_negedge && ~rd_data_previous_r[dqs_count_r] && // (stable_cnt == 'd0) && ((wl_state_r == WL_CORSE_INC_WAIT1) | // (wl_state_r == WL_CORSE_INC_WAIT2))) // past_negedge <= #TCQ 1'b1; //end // Flag to indicate negedge of CK detected and ignore 0->1 transitions // in this region always @(posedge clk)begin if (rst | (wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_DQS_CHECK) | wr_level_done_r | (wl_state_r1 == WL_INIT_FINE_DEC)) flag_ck_negedge <= #TCQ 1'd0; else if ((rd_data_previous_r[dqs_count_r] && ((stable_cnt > 'd0) | (wl_state_r == WL_FINE_DEC) | (wl_state_r == WL_FINE_DEC_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1))) | (wl_state_r == WL_CORSE_INC)) flag_ck_negedge <= #TCQ 1'd1; else if (~rd_data_previous_r[dqs_count_r] && (stable_cnt == 'd14)) //&& flag_ck_negedge) flag_ck_negedge <= #TCQ 1'd0; end // Flag to inhibit rd_data_edge_detect_r before stable DQ always @(posedge clk) begin if (rst) flag_init <= #TCQ 1'b1; else if ((wl_state_r == WL_WAIT) && ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) || (wl_state_r1 == WL_INIT_FINE_DEC_WAIT))) flag_init <= #TCQ 1'b0; end //checking for transition from 0 to 1 always @(posedge clk)begin if (rst | flag_ck_negedge | flag_init | (wl_tap_count_r < 'd1) | inhibit_edge_detect_r) rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; else if (rd_data_edge_detect_r[dqs_count_r] == 1'b1) begin if ((wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT) || (wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) || (wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2)) rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; else rd_data_edge_detect_r <= #TCQ rd_data_edge_detect_r; end else if (rd_data_previous_r[dqs_count_r] && (stable_cnt < 'd14)) rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; else rd_data_edge_detect_r <= #TCQ (~rd_data_previous_r & rd_data_rise_wl_r); end // registring the write level start signal always@(posedge clk) begin wr_level_start_r <= #TCQ wr_level_start; end // Assign dqs_count_r to dqs_count_w to perform the shift operation // instead of multiply operation assign dqs_count_w = {2'b00, dqs_count_r}; assign oclk_count_w = {2'b00, oclkdelay_calib_cnt}; always @(posedge clk) begin if (rst) incdec_wait_cnt <= #TCQ 'd0; else if ((wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_INIT_FINE_DEC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT_TMP)) incdec_wait_cnt <= #TCQ incdec_wait_cnt + 1; else incdec_wait_cnt <= #TCQ 'd0; end // state machine to initiate the write leveling sequence // The state machine operates on one byte at a time. // It will increment the delays to the DQS OSERDES // and sample the DQ from the memory. When it detects // a transition from 1 to 0 then the write leveling is considered // done. always @(posedge clk) begin if(rst)begin wrlvl_err <= #TCQ 1'b0; wr_level_done_r <= #TCQ 1'b0; wrlvl_rank_done_r <= #TCQ 1'b0; dqs_count_r <= #TCQ {DQS_CNT_WIDTH+1{1'b0}}; dq_cnt_inc <= #TCQ 1'b1; rank_cnt_r <= #TCQ 2'b00; wl_state_r <= #TCQ WL_IDLE; wl_state_r1 <= #TCQ WL_IDLE; inhibit_edge_detect_r <= #TCQ 1'b1; wl_edge_detect_valid_r <= #TCQ 1'b0; wl_tap_count_r <= #TCQ 6'd0; fine_dec_cnt <= #TCQ 6'd0; for (r = 0; r < DQS_WIDTH; r = r + 1) begin fine_inc[r] <= #TCQ 6'b0; corse_dec[r] <= #TCQ 3'b0; corse_inc[r] <= #TCQ 3'b0; corse_cnt[r] <= #TCQ 3'b0; end dual_rnk_dec <= #TCQ 1'b0; fast_cal_fine_cnt <= #TCQ FAST_CAL_FINE; fast_cal_coarse_cnt <= #TCQ FAST_CAL_COARSE; final_corse_dec <= #TCQ 1'b0; //zero_tran_r <= #TCQ 1'b0; wrlvl_redo_corse_inc <= #TCQ 'd0; end else begin wl_state_r1 <= #TCQ wl_state_r; case (wl_state_r) WL_IDLE: begin wrlvl_rank_done_r <= #TCQ 1'd0; inhibit_edge_detect_r <= #TCQ 1'b1; if (wrlvl_byte_redo && ~wrlvl_byte_redo_r) begin wr_level_done_r <= #TCQ 1'b0; dqs_count_r <= #TCQ wrcal_cnt; corse_cnt[wrcal_cnt] <= #TCQ final_coarse_tap[wrcal_cnt]; wl_tap_count_r <= #TCQ smallest[wrcal_cnt]; if (early1_data && (((final_coarse_tap[wrcal_cnt] < 'd6) && (CLK_PERIOD/nCK_PER_CLK <= 2500)) || ((final_coarse_tap[wrcal_cnt] < 'd3) && (CLK_PERIOD/nCK_PER_CLK > 2500)))) wrlvl_redo_corse_inc <= #TCQ REDO_COARSE; else if (early2_data && (final_coarse_tap[wrcal_cnt] < 'd2)) wrlvl_redo_corse_inc <= #TCQ 3'd6; else begin wl_state_r <= #TCQ WL_IDLE; wrlvl_err <= #TCQ 1'b1; end end else if (wrlvl_final && ~wrlvl_final_r) begin wr_level_done_r <= #TCQ 1'b0; dqs_count_r <= #TCQ 'd0; end // verilint STARC-2.2.3.3 off if(!wr_level_done_r & wr_level_start_r & wl_sm_start) begin if (SIM_CAL_OPTION == "FAST_CAL") wl_state_r <= #TCQ WL_FINE_INC; else wl_state_r <= #TCQ WL_INIT; end end // verilint STARC-2.2.3.3 on WL_INIT: begin wl_edge_detect_valid_r <= #TCQ 1'b0; inhibit_edge_detect_r <= #TCQ 1'b1; wrlvl_rank_done_r <= #TCQ 1'd0; //zero_tran_r <= #TCQ 1'b0; if (wrlvl_final) corse_cnt[dqs_count_w ] <= #TCQ final_coarse_tap[dqs_count_w ]; if (wrlvl_byte_redo) begin if (|wl_tap_count_r) begin wl_state_r <= #TCQ WL_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; end else if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7) wl_state_r <= #TCQ WL_CORSE_INC; else begin wl_state_r <= #TCQ WL_IDLE; wrlvl_err <= #TCQ 1'b1; end end else if(wl_sm_start) wl_state_r <= #TCQ WL_INIT_FINE_INC; end // Initially Phaser_Out fine delay taps incremented // until stable_cnt=14. A stable_cnt of 14 indicates // that rd_data_rise_wl_r=rd_data_previous_r for 14 fine // tap increments. This is done to inhibit false 0->1 // edge detection when DQS is initially aligned to the // negedge of CK WL_INIT_FINE_INC: begin wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT1; wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1; final_corse_dec <= #TCQ 1'b0; end WL_INIT_FINE_INC_WAIT1: begin if (wl_sm_start) wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT; end // Case1: stable value of rd_data_previous_r=0 then // proceed to 0->1 edge detection. // Case2: stable value of rd_data_previous_r=1 then // decrement fine taps to '0' and proceed to 0->1 // edge detection. Need to decrement in this case to // make sure a valid 0->1 transition was not left // undetected. WL_INIT_FINE_INC_WAIT: begin if (wl_sm_start) begin if (stable_cnt < 'd14) wl_state_r <= #TCQ WL_INIT_FINE_INC; else if (~rd_data_previous_r[dqs_count_r]) begin wl_state_r <= #TCQ WL_WAIT; inhibit_edge_detect_r <= #TCQ 1'b0; end else begin wl_state_r <= #TCQ WL_INIT_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; end end end // Case2: stable value of rd_data_previous_r=1 then // decrement fine taps to '0' and proceed to 0->1 // edge detection. Need to decrement in this case to // make sure a valid 0->1 transition was not left // undetected. WL_INIT_FINE_DEC: begin wl_tap_count_r <= #TCQ 'd0; wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT1; if (fine_dec_cnt > 6'd0) fine_dec_cnt <= #TCQ fine_dec_cnt - 1; else fine_dec_cnt <= #TCQ fine_dec_cnt; end WL_INIT_FINE_DEC_WAIT1: begin if (incdec_wait_cnt == 'd8) wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT; end WL_INIT_FINE_DEC_WAIT: begin if (fine_dec_cnt > 6'd0) begin wl_state_r <= #TCQ WL_INIT_FINE_DEC; inhibit_edge_detect_r <= #TCQ 1'b1; end else begin wl_state_r <= #TCQ WL_WAIT; inhibit_edge_detect_r <= #TCQ 1'b0; end end // Inc DQS Phaser_Out Stage2 Fine Delay line WL_FINE_INC: begin wl_edge_detect_valid_r <= #TCQ 1'b0; if (SIM_CAL_OPTION == "FAST_CAL") begin wl_state_r <= #TCQ WL_FINE_INC_WAIT; if (fast_cal_fine_cnt > 'd0) fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt - 1; else fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt; end else if (wr_level_done_r5) begin wl_tap_count_r <= #TCQ 'd0; wl_state_r <= #TCQ WL_FINE_INC_WAIT; if (|fine_inc[dqs_count_w]) fine_inc[dqs_count_w] <= #TCQ fine_inc[dqs_count_w] - 1; end else begin wl_state_r <= #TCQ WL_WAIT; wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1; end end WL_FINE_INC_WAIT: begin if (SIM_CAL_OPTION == "FAST_CAL") begin if (fast_cal_fine_cnt > 'd0) wl_state_r <= #TCQ WL_FINE_INC; else if (fast_cal_coarse_cnt > 'd0) wl_state_r <= #TCQ WL_CORSE_INC; else wl_state_r <= #TCQ WL_DQS_CNT; end else if (|fine_inc[dqs_count_w]) wl_state_r <= #TCQ WL_FINE_INC; else if (dqs_count_r == (DQS_WIDTH-1)) wl_state_r <= #TCQ WL_IDLE; else begin wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; dqs_count_r <= #TCQ dqs_count_r + 1; end end WL_FINE_DEC: begin wl_edge_detect_valid_r <= #TCQ 1'b0; wl_tap_count_r <= #TCQ 'd0; wl_state_r <= #TCQ WL_FINE_DEC_WAIT1; if (fine_dec_cnt > 6'd0) fine_dec_cnt <= #TCQ fine_dec_cnt - 1; else fine_dec_cnt <= #TCQ fine_dec_cnt; end WL_FINE_DEC_WAIT1: begin if (incdec_wait_cnt == 'd8) wl_state_r <= #TCQ WL_FINE_DEC_WAIT; end WL_FINE_DEC_WAIT: begin if (fine_dec_cnt > 6'd0) wl_state_r <= #TCQ WL_FINE_DEC; //else if (zero_tran_r) // wl_state_r <= #TCQ WL_DQS_CNT; else if (dual_rnk_dec) begin if (|corse_dec[dqs_count_r]) wl_state_r <= #TCQ WL_CORSE_DEC; else wl_state_r <= #TCQ WL_2RANK_DQS_CNT; end else if (wrlvl_byte_redo) begin if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7) wl_state_r <= #TCQ WL_CORSE_INC; else begin wl_state_r <= #TCQ WL_IDLE; wrlvl_err <= #TCQ 1'b1; end end else wl_state_r <= #TCQ WL_CORSE_INC; end WL_CORSE_DEC: begin wl_state_r <= #TCQ WL_CORSE_DEC_WAIT; dual_rnk_dec <= #TCQ 1'b0; if (|corse_dec[dqs_count_r]) corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r] - 1; else corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r]; end WL_CORSE_DEC_WAIT: begin if (wl_sm_start) begin //if (|corse_dec[dqs_count_r]) // wl_state_r <= #TCQ WL_CORSE_DEC; if (|corse_dec[dqs_count_r]) wl_state_r <= #TCQ WL_CORSE_DEC_WAIT1; else wl_state_r <= #TCQ WL_2RANK_DQS_CNT; end end WL_CORSE_DEC_WAIT1: begin if (wl_sm_start) wl_state_r <= #TCQ WL_CORSE_DEC; end WL_CORSE_INC: begin wl_state_r <= #TCQ WL_CORSE_INC_WAIT_TMP; if (SIM_CAL_OPTION == "FAST_CAL") begin if (fast_cal_coarse_cnt > 'd0) fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt - 1; else fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt; end else if (wrlvl_byte_redo) begin corse_cnt[dqs_count_w] <= #TCQ corse_cnt[dqs_count_w] + 1; if (|wrlvl_redo_corse_inc) wrlvl_redo_corse_inc <= #TCQ wrlvl_redo_corse_inc - 1; end else if (~wr_level_done_r5) corse_cnt[dqs_count_r] <= #TCQ corse_cnt[dqs_count_r] + 1; else if (|corse_inc[dqs_count_w]) corse_inc[dqs_count_w] <= #TCQ corse_inc[dqs_count_w] - 1; end WL_CORSE_INC_WAIT_TMP: begin if (incdec_wait_cnt == 'd8) wl_state_r <= #TCQ WL_CORSE_INC_WAIT; end WL_CORSE_INC_WAIT: begin if (SIM_CAL_OPTION == "FAST_CAL") begin if (fast_cal_coarse_cnt > 'd0) wl_state_r <= #TCQ WL_CORSE_INC; else wl_state_r <= #TCQ WL_DQS_CNT; end else if (wrlvl_byte_redo) begin if (|wrlvl_redo_corse_inc) wl_state_r <= #TCQ WL_CORSE_INC; else begin wl_state_r <= #TCQ WL_INIT_FINE_INC; inhibit_edge_detect_r <= #TCQ 1'b1; end end else if (~wr_level_done_r5 && wl_sm_start) wl_state_r <= #TCQ WL_CORSE_INC_WAIT1; else if (wr_level_done_r5) begin if (|corse_inc[dqs_count_r]) wl_state_r <= #TCQ WL_CORSE_INC; else if (|fine_inc[dqs_count_w]) wl_state_r <= #TCQ WL_FINE_INC; else if (dqs_count_r == (DQS_WIDTH-1)) wl_state_r <= #TCQ WL_IDLE; else begin wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; dqs_count_r <= #TCQ dqs_count_r + 1; end end end WL_CORSE_INC_WAIT1: begin if (wl_sm_start) wl_state_r <= #TCQ WL_CORSE_INC_WAIT2; end WL_CORSE_INC_WAIT2: begin if (wl_sm_start) wl_state_r <= #TCQ WL_WAIT; end WL_WAIT: begin if (wl_sm_start) wl_state_r <= #TCQ WL_EDGE_CHECK; end WL_EDGE_CHECK: begin // Look for the edge if (wl_edge_detect_valid_r == 1'b0) begin wl_state_r <= #TCQ WL_WAIT; wl_edge_detect_valid_r <= #TCQ 1'b1; end // 0->1 transition detected with DQS else if(rd_data_edge_detect_r[dqs_count_r] && wl_edge_detect_valid_r) begin wl_tap_count_r <= #TCQ wl_tap_count_r; if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) || ~oclkdelay_calib_done) wl_state_r <= #TCQ WL_DQS_CNT; else wl_state_r <= #TCQ WL_2RANK_TAP_DEC; end // For initial writes check only upto 56 taps. Reserving the // remaining taps for OCLK calibration. else if((~wrlvl_tap_done_r) && (wl_tap_count_r > 6'd55)) begin if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin wl_state_r <= #TCQ WL_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; end else begin wrlvl_err <= #TCQ 1'b1; wl_state_r <= #TCQ WL_IDLE; end end else begin if (wl_tap_count_r < 6'd56) //for reuse wrlvl for complex ocal wl_state_r <= #TCQ WL_FINE_INC; else if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin wl_state_r <= #TCQ WL_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; end else begin wrlvl_err <= #TCQ 1'b1; wl_state_r <= #TCQ WL_IDLE; end end end WL_2RANK_TAP_DEC: begin wl_state_r <= #TCQ WL_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; for (m = 0; m < DQS_WIDTH; m = m + 1) corse_dec[m] <= #TCQ corse_cnt[m]; wl_edge_detect_valid_r <= #TCQ 1'b0; dual_rnk_dec <= #TCQ 1'b1; end WL_DQS_CNT: begin if ((SIM_CAL_OPTION == "FAST_CAL") || (dqs_count_r == (DQS_WIDTH-1)) || wrlvl_byte_redo) begin dqs_count_r <= #TCQ dqs_count_r; dq_cnt_inc <= #TCQ 1'b0; end else begin dqs_count_r <= #TCQ dqs_count_r + 1'b1; dq_cnt_inc <= #TCQ 1'b1; end wl_state_r <= #TCQ WL_DQS_CHECK; wl_edge_detect_valid_r <= #TCQ 1'b0; end WL_2RANK_DQS_CNT: begin if ((SIM_CAL_OPTION == "FAST_CAL") || (dqs_count_r == (DQS_WIDTH-1))) begin dqs_count_r <= #TCQ dqs_count_r; dq_cnt_inc <= #TCQ 1'b0; end else begin dqs_count_r <= #TCQ dqs_count_r + 1'b1; dq_cnt_inc <= #TCQ 1'b1; end wl_state_r <= #TCQ WL_DQS_CHECK; wl_edge_detect_valid_r <= #TCQ 1'b0; dual_rnk_dec <= #TCQ 1'b0; end WL_DQS_CHECK: begin // check if all DQS have been calibrated wl_tap_count_r <= #TCQ 'd0; if (dq_cnt_inc == 1'b0)begin wrlvl_rank_done_r <= #TCQ 1'd1; for (t = 0; t < DQS_WIDTH; t = t + 1) corse_cnt[t] <= #TCQ 3'b0; if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) || ~oclkdelay_calib_done) begin wl_state_r <= #TCQ WL_IDLE; if (wrlvl_byte_redo) dqs_count_r <= #TCQ dqs_count_r; else dqs_count_r <= #TCQ 'd0; end else if (rank_cnt_r == RANKS-1) begin dqs_count_r <= #TCQ dqs_count_r; if (RANKS > 1) wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; else wl_state_r <= #TCQ WL_IDLE; end else begin wl_state_r <= #TCQ WL_INIT; dqs_count_r <= #TCQ 'd0; end if ((SIM_CAL_OPTION == "FAST_CAL") || (rank_cnt_r == RANKS-1)) begin wr_level_done_r <= #TCQ 1'd1; rank_cnt_r <= #TCQ 2'b00; end else begin wr_level_done_r <= #TCQ 1'd0; rank_cnt_r <= #TCQ rank_cnt_r + 1'b1; end end else wl_state_r <= #TCQ WL_INIT; end WL_2RANK_FINAL_TAP: begin if (wr_level_done_r4 && ~wr_level_done_r5) begin for(u = 0; u < DQS_WIDTH; u = u + 1) begin corse_inc[u] <= #TCQ final_coarse_tap[u]; fine_inc[u] <= #TCQ final_val[u]; end dqs_count_r <= #TCQ 'd0; end else if (wr_level_done_r5) begin if (|corse_inc[dqs_count_r]) wl_state_r <= #TCQ WL_CORSE_INC; else if (|fine_inc[dqs_count_w]) wl_state_r <= #TCQ WL_FINE_INC; end end endcase end end // always @ (posedge clk) endmodule
//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_wrlvl.v // /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ // \ \ / \ Date Created: Mon Jun 23 2008 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Memory initialization and overall master state control during // initialization and calibration. Specifically, the following functions // are performed: // 1. Memory initialization (initial AR, mode register programming, etc.) // 2. Initiating write leveling // 3. Generate training pattern writes for read leveling. Generate // memory readback for read leveling. // This module has a DFI interface for providing control/address and write // data to the rest of the PHY datapath during initialization/calibration. // Once initialization is complete, control is passed to the MC. // NOTES: // 1. Multiple CS (multi-rank) not supported // 2. DDR2 not supported // 3. ODT not supported //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_wrlvl.v,v 1.3 2011/06/24 14:49:00 mgeorge Exp $ **$Date: 2011/06/24 14:49:00 $ **$Author: mgeorge $ **$Revision: 1.3 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_wrlvl.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_wrlvl # ( parameter TCQ = 100, parameter DQS_CNT_WIDTH = 3, parameter DQ_WIDTH = 64, parameter DQS_WIDTH = 2, parameter DRAM_WIDTH = 8, parameter RANKS = 1, parameter nCK_PER_CLK = 4, parameter CLK_PERIOD = 4, parameter SIM_CAL_OPTION = "NONE" ) ( input clk, input rst, input phy_ctl_ready, input wr_level_start, input wl_sm_start, input wrlvl_final, input wrlvl_byte_redo, input [DQS_CNT_WIDTH:0] wrcal_cnt, input early1_data, input early2_data, input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt, input oclkdelay_calib_done, input [(DQ_WIDTH)-1:0] rd_data_rise0, output reg wrlvl_byte_done, output reg dqs_po_dec_done /* synthesis syn_maxfan = 2 */, output phy_ctl_rdy_dly, output reg wr_level_done /* synthesis syn_maxfan = 2 */, // to phy_init for cs logic output wrlvl_rank_done, output done_dqs_tap_inc, output [DQS_CNT_WIDTH:0] po_stg2_wl_cnt, // Fine delay line used only during write leveling // Inc/dec Phaser_Out fine delay line output reg dqs_po_stg2_f_incdec, // Enable Phaser_Out fine delay inc/dec output reg dqs_po_en_stg2_f, // Coarse delay line used during write leveling // only if 64 taps of fine delay line were not // sufficient to detect a 0->1 transition // Inc Phaser_Out coarse delay line output reg dqs_wl_po_stg2_c_incdec, // Enable Phaser_Out coarse delay inc/dec output reg dqs_wl_po_en_stg2_c, // Read Phaser_Out delay value input [8:0] po_counter_read_val, // output reg dqs_wl_po_stg2_load, // output reg [8:0] dqs_wl_po_stg2_reg_l, // CK edge undetected output reg wrlvl_err, output reg [3*DQS_WIDTH-1:0] wl_po_coarse_cnt, output reg [6*DQS_WIDTH-1:0] wl_po_fine_cnt, // Debug ports output [5:0] dbg_wl_tap_cnt, output dbg_wl_edge_detect_valid, output [(DQS_WIDTH)-1:0] dbg_rd_data_edge_detect, output [DQS_CNT_WIDTH:0] dbg_dqs_count, output [4:0] dbg_wl_state, output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, output [255:0] dbg_phy_wrlvl ); localparam WL_IDLE = 5'h0; localparam WL_INIT = 5'h1; localparam WL_INIT_FINE_INC = 5'h2; localparam WL_INIT_FINE_INC_WAIT1= 5'h3; localparam WL_INIT_FINE_INC_WAIT = 5'h4; localparam WL_INIT_FINE_DEC = 5'h5; localparam WL_INIT_FINE_DEC_WAIT = 5'h6; localparam WL_FINE_INC = 5'h7; localparam WL_WAIT = 5'h8; localparam WL_EDGE_CHECK = 5'h9; localparam WL_DQS_CHECK = 5'hA; localparam WL_DQS_CNT = 5'hB; localparam WL_2RANK_TAP_DEC = 5'hC; localparam WL_2RANK_DQS_CNT = 5'hD; localparam WL_FINE_DEC = 5'hE; localparam WL_FINE_DEC_WAIT = 5'hF; localparam WL_CORSE_INC = 5'h10; localparam WL_CORSE_INC_WAIT = 5'h11; localparam WL_CORSE_INC_WAIT1 = 5'h12; localparam WL_CORSE_INC_WAIT2 = 5'h13; localparam WL_CORSE_DEC = 5'h14; localparam WL_CORSE_DEC_WAIT = 5'h15; localparam WL_CORSE_DEC_WAIT1 = 5'h16; localparam WL_FINE_INC_WAIT = 5'h17; localparam WL_2RANK_FINAL_TAP = 5'h18; localparam WL_INIT_FINE_DEC_WAIT1= 5'h19; localparam WL_FINE_DEC_WAIT1 = 5'h1A; localparam WL_CORSE_INC_WAIT_TMP = 5'h1B; localparam COARSE_TAPS = 7; localparam FAST_CAL_FINE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 45 : 48; localparam FAST_CAL_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 1 : 2; localparam REDO_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 2 : 5; integer i, j, k, l, p, q, r, s, t, m, n, u, v, w, x,y; reg phy_ctl_ready_r1; reg phy_ctl_ready_r2; reg phy_ctl_ready_r3; reg phy_ctl_ready_r4; reg phy_ctl_ready_r5; reg phy_ctl_ready_r6; (* max_fanout = 50 *) reg [DQS_CNT_WIDTH:0] dqs_count_r; reg [1:0] rank_cnt_r; reg [DQS_WIDTH-1:0] rd_data_rise_wl_r; reg [DQS_WIDTH-1:0] rd_data_previous_r; reg [DQS_WIDTH-1:0] rd_data_edge_detect_r; reg wr_level_done_r; reg wrlvl_rank_done_r; reg wr_level_start_r; reg [4:0] wl_state_r, wl_state_r1; reg inhibit_edge_detect_r; reg wl_edge_detect_valid_r; reg [5:0] wl_tap_count_r; reg [5:0] fine_dec_cnt; reg [5:0] fine_inc[0:DQS_WIDTH-1]; // DQS_WIDTH number of counters 6-bit each reg [2:0] corse_dec[0:DQS_WIDTH-1]; reg [2:0] corse_inc[0:DQS_WIDTH-1]; reg dq_cnt_inc; reg [3:0] stable_cnt; reg flag_ck_negedge; //reg past_negedge; reg flag_init; reg [2:0] corse_cnt[0:DQS_WIDTH-1]; reg [3*DQS_WIDTH-1:0] corse_cnt_dbg; reg [2:0] wl_corse_cnt[0:RANKS-1][0:DQS_WIDTH-1]; //reg [3*DQS_WIDTH-1:0] coarse_tap_inc; reg [2:0] final_coarse_tap[0:DQS_WIDTH-1]; reg [5:0] add_smallest[0:DQS_WIDTH-1]; reg [5:0] add_largest[0:DQS_WIDTH-1]; //reg [6*DQS_WIDTH-1:0] fine_tap_inc; //reg [6*DQS_WIDTH-1:0] fine_tap_dec; reg wr_level_done_r1; reg wr_level_done_r2; reg wr_level_done_r3; reg wr_level_done_r4; reg wr_level_done_r5; reg [5:0] wl_dqs_tap_count_r[0:RANKS-1][0:DQS_WIDTH-1]; reg [5:0] smallest[0:DQS_WIDTH-1]; reg [5:0] largest[0:DQS_WIDTH-1]; reg [5:0] final_val[0:DQS_WIDTH-1]; reg [5:0] po_dec_cnt[0:DQS_WIDTH-1]; reg done_dqs_dec; reg [8:0] po_rdval_cnt; reg po_cnt_dec; reg po_dec_done; reg dual_rnk_dec; wire [DQS_CNT_WIDTH+2:0] dqs_count_w; reg [5:0] fast_cal_fine_cnt; reg [2:0] fast_cal_coarse_cnt; reg wrlvl_byte_redo_r; reg [2:0] wrlvl_redo_corse_inc; reg wrlvl_final_r; reg final_corse_dec; wire [DQS_CNT_WIDTH+2:0] oclk_count_w; reg wrlvl_tap_done_r ; reg [3:0] wait_cnt; reg [3:0] incdec_wait_cnt; // Debug ports assign dbg_wl_edge_detect_valid = wl_edge_detect_valid_r; assign dbg_rd_data_edge_detect = rd_data_edge_detect_r; assign dbg_wl_tap_cnt = wl_tap_count_r; assign dbg_dqs_count = dqs_count_r; assign dbg_wl_state = wl_state_r; assign dbg_wrlvl_fine_tap_cnt = wl_po_fine_cnt; assign dbg_wrlvl_coarse_tap_cnt = wl_po_coarse_cnt; always @(*) begin for (v = 0; v < DQS_WIDTH; v = v + 1) corse_cnt_dbg[3*v+:3] = corse_cnt[v]; end assign dbg_phy_wrlvl[0+:27] = corse_cnt_dbg; assign dbg_phy_wrlvl[27+:5] = wl_state_r; assign dbg_phy_wrlvl[32+:4] = dqs_count_r; assign dbg_phy_wrlvl[36+:9] = rd_data_rise_wl_r; assign dbg_phy_wrlvl[45+:9] = rd_data_previous_r; assign dbg_phy_wrlvl[54+:4] = stable_cnt; assign dbg_phy_wrlvl[58] = 'd0; assign dbg_phy_wrlvl[59] = flag_ck_negedge; assign dbg_phy_wrlvl [60] = wl_edge_detect_valid_r; assign dbg_phy_wrlvl [61+:6] = wl_tap_count_r; assign dbg_phy_wrlvl [67+:9] = rd_data_edge_detect_r; assign dbg_phy_wrlvl [76+:54] = wl_po_fine_cnt; assign dbg_phy_wrlvl [130+:27] = wl_po_coarse_cnt; //************************************************************************** // DQS count to hard PHY during write leveling using Phaser_OUT Stage2 delay //************************************************************************** assign po_stg2_wl_cnt = dqs_count_r; assign wrlvl_rank_done = wrlvl_rank_done_r; assign done_dqs_tap_inc = done_dqs_dec; assign phy_ctl_rdy_dly = phy_ctl_ready_r6; always @(posedge clk) begin phy_ctl_ready_r1 <= #TCQ phy_ctl_ready; phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1; phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2; phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3; phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4; phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5; wrlvl_byte_redo_r <= #TCQ wrlvl_byte_redo; wrlvl_final_r <= #TCQ wrlvl_final; if ((wrlvl_byte_redo && ~wrlvl_byte_redo_r) || (wrlvl_final && ~wrlvl_final_r)) wr_level_done <= #TCQ 1'b0; else wr_level_done <= #TCQ done_dqs_dec; end // Status signal that will be asserted once the first // pass of write leveling is done. always @(posedge clk) begin if(rst) begin wrlvl_tap_done_r <= #TCQ 1'b0 ; end else begin if(wrlvl_tap_done_r == 1'b0) begin if(oclkdelay_calib_done) begin wrlvl_tap_done_r <= #TCQ 1'b1 ; end end end end always @(posedge clk) begin if (rst || po_cnt_dec) wait_cnt <= #TCQ 'd8; else if (phy_ctl_ready_r6 && (wait_cnt > 'd0)) wait_cnt <= #TCQ wait_cnt - 1; end always @(posedge clk) begin if (rst) begin po_rdval_cnt <= #TCQ 'd0; end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin po_rdval_cnt <= #TCQ po_counter_read_val; end else if (po_rdval_cnt > 'd0) begin if (po_cnt_dec) po_rdval_cnt <= #TCQ po_rdval_cnt - 1; else po_rdval_cnt <= #TCQ po_rdval_cnt; end else if (po_rdval_cnt == 'd0) begin po_rdval_cnt <= #TCQ po_rdval_cnt; end end always @(posedge clk) begin if (rst || (po_rdval_cnt == 'd0)) po_cnt_dec <= #TCQ 1'b0; else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (wait_cnt == 'd1)) po_cnt_dec <= #TCQ 1'b1; else po_cnt_dec <= #TCQ 1'b0; end always @(posedge clk) begin if (rst) po_dec_done <= #TCQ 1'b0; else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) || (phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin po_dec_done <= #TCQ 1'b1; end end always @(posedge clk) begin dqs_po_dec_done <= #TCQ po_dec_done; wr_level_done_r1 <= #TCQ wr_level_done_r; wr_level_done_r2 <= #TCQ wr_level_done_r1; wr_level_done_r3 <= #TCQ wr_level_done_r2; wr_level_done_r4 <= #TCQ wr_level_done_r3; wr_level_done_r5 <= #TCQ wr_level_done_r4; for (l = 0; l < DQS_WIDTH; l = l + 1) begin wl_po_coarse_cnt[3*l+:3] <= #TCQ final_coarse_tap[l]; if ((RANKS == 1) || ~oclkdelay_calib_done) wl_po_fine_cnt[6*l+:6] <= #TCQ smallest[l]; else wl_po_fine_cnt[6*l+:6] <= #TCQ final_val[l]; end end generate if (RANKS == 2) begin: dual_rank always @(posedge clk) begin if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) || (wrlvl_final && ~wrlvl_final_r)) done_dqs_dec <= #TCQ 1'b0; else if ((SIM_CAL_OPTION == "FAST_CAL") || ~oclkdelay_calib_done) done_dqs_dec <= #TCQ wr_level_done_r; else if (wr_level_done_r5 && (wl_state_r == WL_IDLE)) done_dqs_dec <= #TCQ 1'b1; end end else begin: single_rank always @(posedge clk) begin if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) || (wrlvl_final && ~wrlvl_final_r)) done_dqs_dec <= #TCQ 1'b0; else if (~oclkdelay_calib_done) done_dqs_dec <= #TCQ wr_level_done_r; else if (wr_level_done_r3 && ~wr_level_done_r4) done_dqs_dec <= #TCQ 1'b1; end end endgenerate always @(posedge clk) if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r)) wrlvl_byte_done <= #TCQ 1'b0; else if (wrlvl_byte_redo && wr_level_done_r3 && ~wr_level_done_r4) wrlvl_byte_done <= #TCQ 1'b1; // Storing DQS tap values at the end of each DQS write leveling always @(posedge clk) begin if (rst) begin for (k = 0; k < RANKS; k = k + 1) begin: rst_wl_dqs_tap_count_loop for (n = 0; n < DQS_WIDTH; n = n + 1) begin wl_corse_cnt[k][n] <= #TCQ 'b0; wl_dqs_tap_count_r[k][n] <= #TCQ 'b0; end end end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1) | (wl_state_r == WL_2RANK_TAP_DEC)) begin wl_dqs_tap_count_r[rank_cnt_r][dqs_count_r] <= #TCQ wl_tap_count_r; wl_corse_cnt[rank_cnt_r][dqs_count_r] <= #TCQ corse_cnt[dqs_count_r]; end else if ((SIM_CAL_OPTION == "FAST_CAL") & (wl_state_r == WL_DQS_CHECK)) begin for (p = 0; p < RANKS; p = p +1) begin: dqs_tap_rank_cnt for(q = 0; q < DQS_WIDTH; q = q +1) begin: dqs_tap_dqs_cnt wl_dqs_tap_count_r[p][q] <= #TCQ wl_tap_count_r; wl_corse_cnt[p][q] <= #TCQ corse_cnt[0]; end end end end // Convert coarse delay to fine taps in case of unequal number of coarse // taps between ranks. Assuming a difference of 1 coarse tap counts // between ranks. A common fine and coarse tap value must be used for both ranks // because Phaser_Out has only one rank register. // Coarse tap1 = period(ps)*93/360 = 34 fine taps // Other coarse taps = period(ps)*103/360 = 38 fine taps generate genvar cnt; if (RANKS == 2) begin // Dual rank for(cnt = 0; cnt < DQS_WIDTH; cnt = cnt +1) begin: coarse_dqs_cnt always @(posedge clk) begin if (rst) begin //coarse_tap_inc[3*cnt+:3] <= #TCQ 'b0; add_smallest[cnt] <= #TCQ 'd0; add_largest[cnt] <= #TCQ 'd0; final_coarse_tap[cnt] <= #TCQ 'd0; end else if (wr_level_done_r1 & ~wr_level_done_r2) begin if (~oclkdelay_calib_done) begin for(y = 0 ; y < DQS_WIDTH; y = y+1) begin final_coarse_tap[y] <= #TCQ wl_corse_cnt[0][y]; add_smallest[y] <= #TCQ 'd0; add_largest[y] <= #TCQ 'd0; end end else if (wl_corse_cnt[0][cnt] == wl_corse_cnt[1][cnt]) begin // Both ranks have use the same number of coarse delay taps. // No conversion of coarse tap to fine taps required. //coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3]; final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt]; add_smallest[cnt] <= #TCQ 'd0; add_largest[cnt] <= #TCQ 'd0; end else if (wl_corse_cnt[0][cnt] < wl_corse_cnt[1][cnt]) begin // Rank 0 uses fewer coarse delay taps than rank1. // conversion of coarse tap to fine taps required for rank1. // The final coarse count will the smaller value. //coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3] - 1; final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt] - 1; if (|wl_corse_cnt[0][cnt]) // Coarse tap 2 or higher being converted to fine taps // This will be added to 'largest' value in final_val // computation add_largest[cnt] <= #TCQ 'd38; else // Coarse tap 1 being converted to fine taps // This will be added to 'largest' value in final_val // computation add_largest[cnt] <= #TCQ 'd34; end else if (wl_corse_cnt[0][cnt] > wl_corse_cnt[1][cnt]) begin // This may be an unlikely scenario in a real system. // Rank 0 uses more coarse delay taps than rank1. // conversion of coarse tap to fine taps required. //coarse_tap_inc[3*cnt+:3] <= #TCQ 'd0; final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt]; if (|wl_corse_cnt[1][cnt]) // Coarse tap 2 or higher being converted to fine taps // This will be added to 'smallest' value in final_val // computation add_smallest[cnt] <= #TCQ 'd38; else // Coarse tap 1 being converted to fine taps // This will be added to 'smallest' value in // final_val computation add_smallest[cnt] <= #TCQ 'd34; end end end end end else begin // Single rank always @(posedge clk) begin //coarse_tap_inc <= #TCQ 'd0; for(w = 0; w < DQS_WIDTH; w = w + 1) begin final_coarse_tap[w] <= #TCQ wl_corse_cnt[0][w]; add_smallest[w] <= #TCQ 'd0; add_largest[w] <= #TCQ 'd0; end end end endgenerate // Determine delay value for DQS in multirank system // Assuming delay value is the smallest for rank 0 DQS // and largest delay value for rank 4 DQS // Set to smallest + ((largest-smallest)/2) always @(posedge clk) begin if (rst) begin for(x = 0; x < DQS_WIDTH; x = x +1) begin smallest[x] <= #TCQ 'b0; largest[x] <= #TCQ 'b0; end end else if ((wl_state_r == WL_DQS_CNT) & wrlvl_byte_redo) begin smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_2RANK_TAP_DEC)) begin smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[RANKS-1][dqs_count_r]; end else if (((SIM_CAL_OPTION == "FAST_CAL") | (~oclkdelay_calib_done & ~wrlvl_byte_redo)) & wr_level_done_r1 & ~wr_level_done_r2) begin for(i = 0; i < DQS_WIDTH; i = i +1) begin: smallest_dqs smallest[i] <= #TCQ wl_dqs_tap_count_r[0][i]; largest[i] <= #TCQ wl_dqs_tap_count_r[0][i]; end end end // final_val to be used for all DQSs in all ranks genvar wr_i; generate for (wr_i = 0; wr_i < DQS_WIDTH; wr_i = wr_i +1) begin: gen_final_tap always @(posedge clk) begin if (rst) final_val[wr_i] <= #TCQ 'b0; else if (wr_level_done_r2 && ~wr_level_done_r3) begin if (~oclkdelay_calib_done) final_val[wr_i] <= #TCQ (smallest[wr_i] + add_smallest[wr_i]); else if ((smallest[wr_i] + add_smallest[wr_i]) < (largest[wr_i] + add_largest[wr_i])) final_val[wr_i] <= #TCQ ((smallest[wr_i] + add_smallest[wr_i]) + (((largest[wr_i] + add_largest[wr_i]) - (smallest[wr_i] + add_smallest[wr_i]))/2)); else if ((smallest[wr_i] + add_smallest[wr_i]) > (largest[wr_i] + add_largest[wr_i])) final_val[wr_i] <= #TCQ ((largest[wr_i] + add_largest[wr_i]) + (((smallest[wr_i] + add_smallest[wr_i]) - (largest[wr_i] + add_largest[wr_i]))/2)); else if ((smallest[wr_i] + add_smallest[wr_i]) == (largest[wr_i] + add_largest[wr_i])) final_val[wr_i] <= #TCQ (largest[wr_i] + add_largest[wr_i]); end end end endgenerate // // fine tap inc/dec value for all DQSs in all ranks // genvar dqs_i; // generate // for (dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i +1) begin: gen_fine_tap // always @(posedge clk) begin // if (rst) // fine_tap_inc[6*dqs_i+:6] <= #TCQ 'd0; // //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0; // else if (wr_level_done_r3 && ~wr_level_done_r4) begin // fine_tap_inc[6*dqs_i+:6] <= #TCQ final_val[6*dqs_i+:6]; // //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0; // end // end // endgenerate // Inc/Dec Phaser_Out stage 2 fine delay line always @(posedge clk) begin if (rst) begin // Fine delay line used only during write leveling dqs_po_stg2_f_incdec <= #TCQ 1'b0; dqs_po_en_stg2_f <= #TCQ 1'b0; // Dec Phaser_Out fine delay (1)before write leveling, // (2)if no 0 to 1 transition detected with 63 fine delay taps, or // (3)dual rank case where fine taps for the first rank need to be 0 end else if (po_cnt_dec || (wl_state_r == WL_INIT_FINE_DEC) || (wl_state_r == WL_FINE_DEC)) begin dqs_po_stg2_f_incdec <= #TCQ 1'b0; dqs_po_en_stg2_f <= #TCQ 1'b1; // Inc Phaser_Out fine delay during write leveling end else if ((wl_state_r == WL_INIT_FINE_INC) || (wl_state_r == WL_FINE_INC)) begin dqs_po_stg2_f_incdec <= #TCQ 1'b1; dqs_po_en_stg2_f <= #TCQ 1'b1; end else begin dqs_po_stg2_f_incdec <= #TCQ 1'b0; dqs_po_en_stg2_f <= #TCQ 1'b0; end end // Inc Phaser_Out stage 2 Coarse delay line always @(posedge clk) begin if (rst) begin // Coarse delay line used during write leveling // only if no 0->1 transition undetected with 64 // fine delay line taps dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0; dqs_wl_po_en_stg2_c <= #TCQ 1'b0; end else if (wl_state_r == WL_CORSE_INC) begin // Inc Phaser_Out coarse delay during write leveling dqs_wl_po_stg2_c_incdec <= #TCQ 1'b1; dqs_wl_po_en_stg2_c <= #TCQ 1'b1; end else begin dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0; dqs_wl_po_en_stg2_c <= #TCQ 1'b0; end end // only storing the rise data for checking. The data comming back during // write leveling will be a static value. Just checking for rise data is // enough. genvar rd_i; generate for(rd_i = 0; rd_i < DQS_WIDTH; rd_i = rd_i +1)begin: gen_rd always @(posedge clk) rd_data_rise_wl_r[rd_i] <= #TCQ |rd_data_rise0[(rd_i*DRAM_WIDTH)+DRAM_WIDTH-1:rd_i*DRAM_WIDTH]; end endgenerate // storing the previous data for checking later. always @(posedge clk)begin if ((wl_state_r == WL_INIT) || //(wl_state_r == WL_INIT_FINE_INC_WAIT) || //(wl_state_r == WL_INIT_FINE_INC_WAIT1) || ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)) || (wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_FINE_DEC_WAIT) || (wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) || (wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2) || ((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r))) rd_data_previous_r <= #TCQ rd_data_rise_wl_r; end // changed stable count from 3 to 7 because of fine tap resolution always @(posedge clk)begin if (rst | (wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_2RANK_TAP_DEC) | (wl_state_r == WL_FINE_DEC) | (rd_data_previous_r[dqs_count_r] != rd_data_rise_wl_r[dqs_count_r]) | (wl_state_r1 == WL_INIT_FINE_DEC)) stable_cnt <= #TCQ 'd0; else if ((wl_tap_count_r > 6'd0) & (((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)) | ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)))) begin if ((rd_data_previous_r[dqs_count_r] == rd_data_rise_wl_r[dqs_count_r]) & (stable_cnt < 'd14)) stable_cnt <= #TCQ stable_cnt + 1; end end // Signal to ensure that flag_ck_negedge does not incorrectly assert // when DQS is very close to CK rising edge //always @(posedge clk) begin // if (rst | (wl_state_r == WL_DQS_CNT) | // (wl_state_r == WL_DQS_CHECK) | wr_level_done_r) // past_negedge <= #TCQ 1'b0; // else if (~flag_ck_negedge && ~rd_data_previous_r[dqs_count_r] && // (stable_cnt == 'd0) && ((wl_state_r == WL_CORSE_INC_WAIT1) | // (wl_state_r == WL_CORSE_INC_WAIT2))) // past_negedge <= #TCQ 1'b1; //end // Flag to indicate negedge of CK detected and ignore 0->1 transitions // in this region always @(posedge clk)begin if (rst | (wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_DQS_CHECK) | wr_level_done_r | (wl_state_r1 == WL_INIT_FINE_DEC)) flag_ck_negedge <= #TCQ 1'd0; else if ((rd_data_previous_r[dqs_count_r] && ((stable_cnt > 'd0) | (wl_state_r == WL_FINE_DEC) | (wl_state_r == WL_FINE_DEC_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1))) | (wl_state_r == WL_CORSE_INC)) flag_ck_negedge <= #TCQ 1'd1; else if (~rd_data_previous_r[dqs_count_r] && (stable_cnt == 'd14)) //&& flag_ck_negedge) flag_ck_negedge <= #TCQ 1'd0; end // Flag to inhibit rd_data_edge_detect_r before stable DQ always @(posedge clk) begin if (rst) flag_init <= #TCQ 1'b1; else if ((wl_state_r == WL_WAIT) && ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) || (wl_state_r1 == WL_INIT_FINE_DEC_WAIT))) flag_init <= #TCQ 1'b0; end //checking for transition from 0 to 1 always @(posedge clk)begin if (rst | flag_ck_negedge | flag_init | (wl_tap_count_r < 'd1) | inhibit_edge_detect_r) rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; else if (rd_data_edge_detect_r[dqs_count_r] == 1'b1) begin if ((wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT) || (wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) || (wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2)) rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; else rd_data_edge_detect_r <= #TCQ rd_data_edge_detect_r; end else if (rd_data_previous_r[dqs_count_r] && (stable_cnt < 'd14)) rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; else rd_data_edge_detect_r <= #TCQ (~rd_data_previous_r & rd_data_rise_wl_r); end // registring the write level start signal always@(posedge clk) begin wr_level_start_r <= #TCQ wr_level_start; end // Assign dqs_count_r to dqs_count_w to perform the shift operation // instead of multiply operation assign dqs_count_w = {2'b00, dqs_count_r}; assign oclk_count_w = {2'b00, oclkdelay_calib_cnt}; always @(posedge clk) begin if (rst) incdec_wait_cnt <= #TCQ 'd0; else if ((wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_INIT_FINE_DEC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT_TMP)) incdec_wait_cnt <= #TCQ incdec_wait_cnt + 1; else incdec_wait_cnt <= #TCQ 'd0; end // state machine to initiate the write leveling sequence // The state machine operates on one byte at a time. // It will increment the delays to the DQS OSERDES // and sample the DQ from the memory. When it detects // a transition from 1 to 0 then the write leveling is considered // done. always @(posedge clk) begin if(rst)begin wrlvl_err <= #TCQ 1'b0; wr_level_done_r <= #TCQ 1'b0; wrlvl_rank_done_r <= #TCQ 1'b0; dqs_count_r <= #TCQ {DQS_CNT_WIDTH+1{1'b0}}; dq_cnt_inc <= #TCQ 1'b1; rank_cnt_r <= #TCQ 2'b00; wl_state_r <= #TCQ WL_IDLE; wl_state_r1 <= #TCQ WL_IDLE; inhibit_edge_detect_r <= #TCQ 1'b1; wl_edge_detect_valid_r <= #TCQ 1'b0; wl_tap_count_r <= #TCQ 6'd0; fine_dec_cnt <= #TCQ 6'd0; for (r = 0; r < DQS_WIDTH; r = r + 1) begin fine_inc[r] <= #TCQ 6'b0; corse_dec[r] <= #TCQ 3'b0; corse_inc[r] <= #TCQ 3'b0; corse_cnt[r] <= #TCQ 3'b0; end dual_rnk_dec <= #TCQ 1'b0; fast_cal_fine_cnt <= #TCQ FAST_CAL_FINE; fast_cal_coarse_cnt <= #TCQ FAST_CAL_COARSE; final_corse_dec <= #TCQ 1'b0; //zero_tran_r <= #TCQ 1'b0; wrlvl_redo_corse_inc <= #TCQ 'd0; end else begin wl_state_r1 <= #TCQ wl_state_r; case (wl_state_r) WL_IDLE: begin wrlvl_rank_done_r <= #TCQ 1'd0; inhibit_edge_detect_r <= #TCQ 1'b1; if (wrlvl_byte_redo && ~wrlvl_byte_redo_r) begin wr_level_done_r <= #TCQ 1'b0; dqs_count_r <= #TCQ wrcal_cnt; corse_cnt[wrcal_cnt] <= #TCQ final_coarse_tap[wrcal_cnt]; wl_tap_count_r <= #TCQ smallest[wrcal_cnt]; if (early1_data && (((final_coarse_tap[wrcal_cnt] < 'd6) && (CLK_PERIOD/nCK_PER_CLK <= 2500)) || ((final_coarse_tap[wrcal_cnt] < 'd3) && (CLK_PERIOD/nCK_PER_CLK > 2500)))) wrlvl_redo_corse_inc <= #TCQ REDO_COARSE; else if (early2_data && (final_coarse_tap[wrcal_cnt] < 'd2)) wrlvl_redo_corse_inc <= #TCQ 3'd6; else begin wl_state_r <= #TCQ WL_IDLE; wrlvl_err <= #TCQ 1'b1; end end else if (wrlvl_final && ~wrlvl_final_r) begin wr_level_done_r <= #TCQ 1'b0; dqs_count_r <= #TCQ 'd0; end // verilint STARC-2.2.3.3 off if(!wr_level_done_r & wr_level_start_r & wl_sm_start) begin if (SIM_CAL_OPTION == "FAST_CAL") wl_state_r <= #TCQ WL_FINE_INC; else wl_state_r <= #TCQ WL_INIT; end end // verilint STARC-2.2.3.3 on WL_INIT: begin wl_edge_detect_valid_r <= #TCQ 1'b0; inhibit_edge_detect_r <= #TCQ 1'b1; wrlvl_rank_done_r <= #TCQ 1'd0; //zero_tran_r <= #TCQ 1'b0; if (wrlvl_final) corse_cnt[dqs_count_w ] <= #TCQ final_coarse_tap[dqs_count_w ]; if (wrlvl_byte_redo) begin if (|wl_tap_count_r) begin wl_state_r <= #TCQ WL_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; end else if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7) wl_state_r <= #TCQ WL_CORSE_INC; else begin wl_state_r <= #TCQ WL_IDLE; wrlvl_err <= #TCQ 1'b1; end end else if(wl_sm_start) wl_state_r <= #TCQ WL_INIT_FINE_INC; end // Initially Phaser_Out fine delay taps incremented // until stable_cnt=14. A stable_cnt of 14 indicates // that rd_data_rise_wl_r=rd_data_previous_r for 14 fine // tap increments. This is done to inhibit false 0->1 // edge detection when DQS is initially aligned to the // negedge of CK WL_INIT_FINE_INC: begin wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT1; wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1; final_corse_dec <= #TCQ 1'b0; end WL_INIT_FINE_INC_WAIT1: begin if (wl_sm_start) wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT; end // Case1: stable value of rd_data_previous_r=0 then // proceed to 0->1 edge detection. // Case2: stable value of rd_data_previous_r=1 then // decrement fine taps to '0' and proceed to 0->1 // edge detection. Need to decrement in this case to // make sure a valid 0->1 transition was not left // undetected. WL_INIT_FINE_INC_WAIT: begin if (wl_sm_start) begin if (stable_cnt < 'd14) wl_state_r <= #TCQ WL_INIT_FINE_INC; else if (~rd_data_previous_r[dqs_count_r]) begin wl_state_r <= #TCQ WL_WAIT; inhibit_edge_detect_r <= #TCQ 1'b0; end else begin wl_state_r <= #TCQ WL_INIT_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; end end end // Case2: stable value of rd_data_previous_r=1 then // decrement fine taps to '0' and proceed to 0->1 // edge detection. Need to decrement in this case to // make sure a valid 0->1 transition was not left // undetected. WL_INIT_FINE_DEC: begin wl_tap_count_r <= #TCQ 'd0; wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT1; if (fine_dec_cnt > 6'd0) fine_dec_cnt <= #TCQ fine_dec_cnt - 1; else fine_dec_cnt <= #TCQ fine_dec_cnt; end WL_INIT_FINE_DEC_WAIT1: begin if (incdec_wait_cnt == 'd8) wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT; end WL_INIT_FINE_DEC_WAIT: begin if (fine_dec_cnt > 6'd0) begin wl_state_r <= #TCQ WL_INIT_FINE_DEC; inhibit_edge_detect_r <= #TCQ 1'b1; end else begin wl_state_r <= #TCQ WL_WAIT; inhibit_edge_detect_r <= #TCQ 1'b0; end end // Inc DQS Phaser_Out Stage2 Fine Delay line WL_FINE_INC: begin wl_edge_detect_valid_r <= #TCQ 1'b0; if (SIM_CAL_OPTION == "FAST_CAL") begin wl_state_r <= #TCQ WL_FINE_INC_WAIT; if (fast_cal_fine_cnt > 'd0) fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt - 1; else fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt; end else if (wr_level_done_r5) begin wl_tap_count_r <= #TCQ 'd0; wl_state_r <= #TCQ WL_FINE_INC_WAIT; if (|fine_inc[dqs_count_w]) fine_inc[dqs_count_w] <= #TCQ fine_inc[dqs_count_w] - 1; end else begin wl_state_r <= #TCQ WL_WAIT; wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1; end end WL_FINE_INC_WAIT: begin if (SIM_CAL_OPTION == "FAST_CAL") begin if (fast_cal_fine_cnt > 'd0) wl_state_r <= #TCQ WL_FINE_INC; else if (fast_cal_coarse_cnt > 'd0) wl_state_r <= #TCQ WL_CORSE_INC; else wl_state_r <= #TCQ WL_DQS_CNT; end else if (|fine_inc[dqs_count_w]) wl_state_r <= #TCQ WL_FINE_INC; else if (dqs_count_r == (DQS_WIDTH-1)) wl_state_r <= #TCQ WL_IDLE; else begin wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; dqs_count_r <= #TCQ dqs_count_r + 1; end end WL_FINE_DEC: begin wl_edge_detect_valid_r <= #TCQ 1'b0; wl_tap_count_r <= #TCQ 'd0; wl_state_r <= #TCQ WL_FINE_DEC_WAIT1; if (fine_dec_cnt > 6'd0) fine_dec_cnt <= #TCQ fine_dec_cnt - 1; else fine_dec_cnt <= #TCQ fine_dec_cnt; end WL_FINE_DEC_WAIT1: begin if (incdec_wait_cnt == 'd8) wl_state_r <= #TCQ WL_FINE_DEC_WAIT; end WL_FINE_DEC_WAIT: begin if (fine_dec_cnt > 6'd0) wl_state_r <= #TCQ WL_FINE_DEC; //else if (zero_tran_r) // wl_state_r <= #TCQ WL_DQS_CNT; else if (dual_rnk_dec) begin if (|corse_dec[dqs_count_r]) wl_state_r <= #TCQ WL_CORSE_DEC; else wl_state_r <= #TCQ WL_2RANK_DQS_CNT; end else if (wrlvl_byte_redo) begin if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7) wl_state_r <= #TCQ WL_CORSE_INC; else begin wl_state_r <= #TCQ WL_IDLE; wrlvl_err <= #TCQ 1'b1; end end else wl_state_r <= #TCQ WL_CORSE_INC; end WL_CORSE_DEC: begin wl_state_r <= #TCQ WL_CORSE_DEC_WAIT; dual_rnk_dec <= #TCQ 1'b0; if (|corse_dec[dqs_count_r]) corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r] - 1; else corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r]; end WL_CORSE_DEC_WAIT: begin if (wl_sm_start) begin //if (|corse_dec[dqs_count_r]) // wl_state_r <= #TCQ WL_CORSE_DEC; if (|corse_dec[dqs_count_r]) wl_state_r <= #TCQ WL_CORSE_DEC_WAIT1; else wl_state_r <= #TCQ WL_2RANK_DQS_CNT; end end WL_CORSE_DEC_WAIT1: begin if (wl_sm_start) wl_state_r <= #TCQ WL_CORSE_DEC; end WL_CORSE_INC: begin wl_state_r <= #TCQ WL_CORSE_INC_WAIT_TMP; if (SIM_CAL_OPTION == "FAST_CAL") begin if (fast_cal_coarse_cnt > 'd0) fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt - 1; else fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt; end else if (wrlvl_byte_redo) begin corse_cnt[dqs_count_w] <= #TCQ corse_cnt[dqs_count_w] + 1; if (|wrlvl_redo_corse_inc) wrlvl_redo_corse_inc <= #TCQ wrlvl_redo_corse_inc - 1; end else if (~wr_level_done_r5) corse_cnt[dqs_count_r] <= #TCQ corse_cnt[dqs_count_r] + 1; else if (|corse_inc[dqs_count_w]) corse_inc[dqs_count_w] <= #TCQ corse_inc[dqs_count_w] - 1; end WL_CORSE_INC_WAIT_TMP: begin if (incdec_wait_cnt == 'd8) wl_state_r <= #TCQ WL_CORSE_INC_WAIT; end WL_CORSE_INC_WAIT: begin if (SIM_CAL_OPTION == "FAST_CAL") begin if (fast_cal_coarse_cnt > 'd0) wl_state_r <= #TCQ WL_CORSE_INC; else wl_state_r <= #TCQ WL_DQS_CNT; end else if (wrlvl_byte_redo) begin if (|wrlvl_redo_corse_inc) wl_state_r <= #TCQ WL_CORSE_INC; else begin wl_state_r <= #TCQ WL_INIT_FINE_INC; inhibit_edge_detect_r <= #TCQ 1'b1; end end else if (~wr_level_done_r5 && wl_sm_start) wl_state_r <= #TCQ WL_CORSE_INC_WAIT1; else if (wr_level_done_r5) begin if (|corse_inc[dqs_count_r]) wl_state_r <= #TCQ WL_CORSE_INC; else if (|fine_inc[dqs_count_w]) wl_state_r <= #TCQ WL_FINE_INC; else if (dqs_count_r == (DQS_WIDTH-1)) wl_state_r <= #TCQ WL_IDLE; else begin wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; dqs_count_r <= #TCQ dqs_count_r + 1; end end end WL_CORSE_INC_WAIT1: begin if (wl_sm_start) wl_state_r <= #TCQ WL_CORSE_INC_WAIT2; end WL_CORSE_INC_WAIT2: begin if (wl_sm_start) wl_state_r <= #TCQ WL_WAIT; end WL_WAIT: begin if (wl_sm_start) wl_state_r <= #TCQ WL_EDGE_CHECK; end WL_EDGE_CHECK: begin // Look for the edge if (wl_edge_detect_valid_r == 1'b0) begin wl_state_r <= #TCQ WL_WAIT; wl_edge_detect_valid_r <= #TCQ 1'b1; end // 0->1 transition detected with DQS else if(rd_data_edge_detect_r[dqs_count_r] && wl_edge_detect_valid_r) begin wl_tap_count_r <= #TCQ wl_tap_count_r; if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) || ~oclkdelay_calib_done) wl_state_r <= #TCQ WL_DQS_CNT; else wl_state_r <= #TCQ WL_2RANK_TAP_DEC; end // For initial writes check only upto 56 taps. Reserving the // remaining taps for OCLK calibration. else if((~wrlvl_tap_done_r) && (wl_tap_count_r > 6'd55)) begin if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin wl_state_r <= #TCQ WL_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; end else begin wrlvl_err <= #TCQ 1'b1; wl_state_r <= #TCQ WL_IDLE; end end else begin if (wl_tap_count_r < 6'd56) //for reuse wrlvl for complex ocal wl_state_r <= #TCQ WL_FINE_INC; else if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin wl_state_r <= #TCQ WL_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; end else begin wrlvl_err <= #TCQ 1'b1; wl_state_r <= #TCQ WL_IDLE; end end end WL_2RANK_TAP_DEC: begin wl_state_r <= #TCQ WL_FINE_DEC; fine_dec_cnt <= #TCQ wl_tap_count_r; for (m = 0; m < DQS_WIDTH; m = m + 1) corse_dec[m] <= #TCQ corse_cnt[m]; wl_edge_detect_valid_r <= #TCQ 1'b0; dual_rnk_dec <= #TCQ 1'b1; end WL_DQS_CNT: begin if ((SIM_CAL_OPTION == "FAST_CAL") || (dqs_count_r == (DQS_WIDTH-1)) || wrlvl_byte_redo) begin dqs_count_r <= #TCQ dqs_count_r; dq_cnt_inc <= #TCQ 1'b0; end else begin dqs_count_r <= #TCQ dqs_count_r + 1'b1; dq_cnt_inc <= #TCQ 1'b1; end wl_state_r <= #TCQ WL_DQS_CHECK; wl_edge_detect_valid_r <= #TCQ 1'b0; end WL_2RANK_DQS_CNT: begin if ((SIM_CAL_OPTION == "FAST_CAL") || (dqs_count_r == (DQS_WIDTH-1))) begin dqs_count_r <= #TCQ dqs_count_r; dq_cnt_inc <= #TCQ 1'b0; end else begin dqs_count_r <= #TCQ dqs_count_r + 1'b1; dq_cnt_inc <= #TCQ 1'b1; end wl_state_r <= #TCQ WL_DQS_CHECK; wl_edge_detect_valid_r <= #TCQ 1'b0; dual_rnk_dec <= #TCQ 1'b0; end WL_DQS_CHECK: begin // check if all DQS have been calibrated wl_tap_count_r <= #TCQ 'd0; if (dq_cnt_inc == 1'b0)begin wrlvl_rank_done_r <= #TCQ 1'd1; for (t = 0; t < DQS_WIDTH; t = t + 1) corse_cnt[t] <= #TCQ 3'b0; if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) || ~oclkdelay_calib_done) begin wl_state_r <= #TCQ WL_IDLE; if (wrlvl_byte_redo) dqs_count_r <= #TCQ dqs_count_r; else dqs_count_r <= #TCQ 'd0; end else if (rank_cnt_r == RANKS-1) begin dqs_count_r <= #TCQ dqs_count_r; if (RANKS > 1) wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; else wl_state_r <= #TCQ WL_IDLE; end else begin wl_state_r <= #TCQ WL_INIT; dqs_count_r <= #TCQ 'd0; end if ((SIM_CAL_OPTION == "FAST_CAL") || (rank_cnt_r == RANKS-1)) begin wr_level_done_r <= #TCQ 1'd1; rank_cnt_r <= #TCQ 2'b00; end else begin wr_level_done_r <= #TCQ 1'd0; rank_cnt_r <= #TCQ rank_cnt_r + 1'b1; end end else wl_state_r <= #TCQ WL_INIT; end WL_2RANK_FINAL_TAP: begin if (wr_level_done_r4 && ~wr_level_done_r5) begin for(u = 0; u < DQS_WIDTH; u = u + 1) begin corse_inc[u] <= #TCQ final_coarse_tap[u]; fine_inc[u] <= #TCQ final_val[u]; end dqs_count_r <= #TCQ 'd0; end else if (wr_level_done_r5) begin if (|corse_inc[dqs_count_r]) wl_state_r <= #TCQ WL_CORSE_INC; else if (|fine_inc[dqs_count_w]) wl_state_r <= #TCQ WL_FINE_INC; end end endcase end end // always @ (posedge clk) endmodule
//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_v2_3_phy_ocd_po_cntlr.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Manipulates phaser out stg2f and stg3 on behalf of // scan and DQS centering. // // Maintains a shadow of the phaser out stg2f and stg3 tap settings. // The stg3 shadow is 6 bits, just like the phaser out. stg2f is // 8 bits. This allows the po_cntlr to track how far past the stg2f // saturation points we have gone when stepping to the limits of stg3. // This way we're can stay in sync when we step back from the saturation // limits. // // Looks at the edge values and determines which case has been // detected by the scan. Uses the results to drive the centering. // // Main state machine waits until it sees reset_scan go to zero. While // waiting it is writing the initialzation values to the stg2 and stg3 // shadows. When reset_scan goes low, taps_set is pulsed. This // tells the sampling block to begin sampling. When the sampling // block has finished sampling this setting of the phaser out taps, // is signals by setting samp_done. When the main state machine // sees samp_done it sets the next value in the phaser out and // waits for the phaser out to be ready before beginning the next // sample. // // Turns out phy_init is sensitive to the length of the ocal_num_samples_done // pulse. Something like a precharge and activate time. Added feature // to resume_wait to wait at least 32 cycles between assertion and // subsequent deassertion of ocal_num_samples_done. // // Also turns out phy_init needs help to get into consistent // starting state for complex cal. This can be done by preseting // ocal_num_samples_done to one. Then waiting for 32 fabric clocks, // turn off _done and then assert _resume. // // Scanning algorithm. // // Phaser manipulation algoritm. // //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_ocd_po_cntlr # (parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 8, parameter nCK_PER_CLK = 4, parameter TCQ = 100) (/*AUTOARG*/ // Outputs scan_done, ocal_num_samples_done_r, oclkdelay_center_calib_start, oclkdelay_center_calib_done, oclk_center_write_resume, ocd2stg2_inc, ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, stg3, simp_stg3_final, cmplx_stg3_final, simp_stg3_final_sel, ninety_offsets, scanning_right, ocd_ktap_left, ocd_ktap_right, ocd_edge_detect_rdy, taps_set, use_noise_window, ocal_scan_win_not_found, // Inputs clk, rst, reset_scan, oclkdelay_init_val, lim2ocal_stg3_right_lim, lim2ocal_stg3_left_lim, complex_oclkdelay_calib_start, po_counter_read_val, oclkdelay_calib_cnt, mmcm_edge_detect_done, mmcm_lbclk_edge_aligned, poc_backup, phy_rddata_en_3, zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty, z2f, f2z, o2f, f2o, scan_right, samp_done, wl_po_fine_cnt_sel, po_rdy ); input clk; input rst; input reset_scan; reg scan_done_r; output scan_done; assign scan_done = scan_done_r; output [5:0] simp_stg3_final_sel; reg cmplx_samples_done_ns, cmplx_samples_done_r; always @(posedge clk) cmplx_samples_done_r <= #TCQ cmplx_samples_done_ns; output ocal_num_samples_done_r; assign ocal_num_samples_done_r = cmplx_samples_done_r; // Write Level signals during OCLKDELAY calibration input [5:0] oclkdelay_init_val; input [5:0] lim2ocal_stg3_right_lim; input [5:0] lim2ocal_stg3_left_lim; input complex_oclkdelay_calib_start; reg oclkdelay_center_calib_start_ns, oclkdelay_center_calib_start_r; always @(posedge clk) oclkdelay_center_calib_start_r <= #TCQ oclkdelay_center_calib_start_ns; output oclkdelay_center_calib_start; assign oclkdelay_center_calib_start = oclkdelay_center_calib_start_r; reg oclkdelay_center_calib_done_ns, oclkdelay_center_calib_done_r; always @(posedge clk) oclkdelay_center_calib_done_r <= #TCQ oclkdelay_center_calib_done_ns; output oclkdelay_center_calib_done; assign oclkdelay_center_calib_done = oclkdelay_center_calib_done_r; reg oclk_center_write_resume_ns, oclk_center_write_resume_r; always @(posedge clk) oclk_center_write_resume_r <= #TCQ oclk_center_write_resume_ns; output oclk_center_write_resume; assign oclk_center_write_resume = oclk_center_write_resume_r; reg ocd2stg2_inc_r, ocd2stg2_dec_r, ocd2stg3_inc_r, ocd2stg3_dec_r; output ocd2stg2_inc, ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec; assign ocd2stg2_inc = ocd2stg2_inc_r; assign ocd2stg2_dec = ocd2stg2_dec_r; assign ocd2stg3_inc = ocd2stg3_inc_r; assign ocd2stg3_dec = ocd2stg3_dec_r; // Remember, two stage 2 steps for every stg 3 step. And we need a sign bit. reg [8:0] stg2_ns, stg2_r; always @(posedge clk) stg2_r <= #TCQ stg2_ns; reg [5:0] stg3_ns, stg3_r; always @(posedge clk) stg3_r <= #TCQ stg3_ns; output [5:0] stg3; assign stg3 = stg3_r; input [5:0] wl_po_fine_cnt_sel; input [8:0] po_counter_read_val; reg [5:0] po_counter_read_val_r; always @(posedge clk) po_counter_read_val_r <= #TCQ po_counter_read_val[5:0]; reg [DQS_WIDTH*6-1:0] simp_stg3_final_ns, simp_stg3_final_r, cmplx_stg3_final_ns, cmplx_stg3_final_r; always @(posedge clk) simp_stg3_final_r <= #TCQ simp_stg3_final_ns; always @(posedge clk) cmplx_stg3_final_r <= #TCQ cmplx_stg3_final_ns; output [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final; assign simp_stg3_final = simp_stg3_final_r; assign cmplx_stg3_final = cmplx_stg3_final_r; input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; wire [DQS_WIDTH*6-1:0] simp_stg3_final_shft = simp_stg3_final_r >> oclkdelay_calib_cnt * 6; assign simp_stg3_final_sel = simp_stg3_final_shft[5:0]; wire [5:0] stg3_init = complex_oclkdelay_calib_start ? simp_stg3_final_sel : oclkdelay_init_val; wire signed [8:0] stg2_steps = stg3_r > stg3_init ? -9'sd2 * $signed({3'b0, (stg3_r - stg3_init)}) : 9'sd2 * $signed({3'b0, (stg3_init - stg3_r)}); wire signed [8:0] stg2_target_ns = $signed({3'b0, wl_po_fine_cnt_sel}) + stg2_steps; reg signed [8:0] stg2_target_r; always @ (posedge clk) stg2_target_r <= #TCQ stg2_target_ns; reg [5:0] stg2_final_ns, stg2_final_r; always @(posedge clk) stg2_final_r <= #TCQ stg2_final_ns; always @(*) stg2_final_ns = stg2_target_r[8] == 1'b1 ? 6'd0 : stg2_target_r > 9'd63 ? 6'd63 : stg2_target_r[5:0]; wire final_stg2_inc = stg2_final_r > po_counter_read_val_r; wire final_stg2_dec = stg2_final_r < po_counter_read_val_r; wire left_lim = stg3_r == lim2ocal_stg3_left_lim; wire right_lim = stg3_r == lim2ocal_stg3_right_lim; reg [1:0] ninety_offsets_ns, ninety_offsets_r; always @(posedge clk) ninety_offsets_r <= #TCQ ninety_offsets_ns; output [1:0] ninety_offsets; assign ninety_offsets = ninety_offsets_r; reg scanning_right_ns, scanning_right_r; always @(posedge clk) scanning_right_r <= #TCQ scanning_right_ns; output scanning_right; assign scanning_right = scanning_right_r; reg ocd_ktap_left_ns, ocd_ktap_left_r, ocd_ktap_right_ns, ocd_ktap_right_r; always @(posedge clk) ocd_ktap_left_r <= #TCQ ocd_ktap_left_ns; always @(posedge clk) ocd_ktap_right_r <= #TCQ ocd_ktap_right_ns; output ocd_ktap_left, ocd_ktap_right; assign ocd_ktap_left = ocd_ktap_left_r; assign ocd_ktap_right = ocd_ktap_right_r; reg ocd_edge_detect_rdy_ns, ocd_edge_detect_rdy_r; always @(posedge clk) ocd_edge_detect_rdy_r <= #TCQ ocd_edge_detect_rdy_ns; output ocd_edge_detect_rdy; assign ocd_edge_detect_rdy = ocd_edge_detect_rdy_r; input mmcm_edge_detect_done; input mmcm_lbclk_edge_aligned; input poc_backup; reg poc_backup_ns, poc_backup_r; always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns; reg taps_set_r; output taps_set; assign taps_set = taps_set_r; input phy_rddata_en_3; input [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty; input z2f, f2z, o2f, f2o; wire zero = f2z && z2f; wire noise = z2f && f2o; wire oneeighty = f2o && o2f; reg win_not_found; reg [1:0] ninety_offsets_final; reg [5:0] left, right, current_edge; always @(*) begin left = lim2ocal_stg3_left_lim; right = lim2ocal_stg3_right_lim; ninety_offsets_final = 2'd0; win_not_found = 1'b0; if (zero) begin left = fuzz2zero; right = zero2fuzz; end else if (noise) begin left = zero2fuzz; right = fuzz2oneeighty; ninety_offsets_final = 2'd1; end else if (oneeighty) begin left = fuzz2oneeighty; right = oneeighty2fuzz; ninety_offsets_final = 2'd2; end else if (z2f) begin right = zero2fuzz; end else if (f2o) begin left = fuzz2oneeighty; ninety_offsets_final = 2'd2; end else if (f2z) begin left = fuzz2zero; end else win_not_found = 1'b1; current_edge = ocd_ktap_left_r ? left : right; end // always @ begin output use_noise_window; assign use_noise_window = ninety_offsets == 2'd1; reg ocal_scan_win_not_found_ns, ocal_scan_win_not_found_r; always @(posedge clk) ocal_scan_win_not_found_r <= #TCQ ocal_scan_win_not_found_ns; output ocal_scan_win_not_found; assign ocal_scan_win_not_found = ocal_scan_win_not_found_r; wire inc_po_ns = current_edge > stg3_r; wire dec_po_ns = current_edge < stg3_r; reg inc_po_r, dec_po_r; always @(posedge clk) inc_po_r <= #TCQ inc_po_ns; always @(posedge clk) dec_po_r <= #TCQ dec_po_ns; input scan_right; wire left_stop = left_lim || scan_right; wire right_stop = right_lim || o2f; reg [4:0] resume_wait_ns, resume_wait_r; always @(posedge clk) resume_wait_r <= #TCQ resume_wait_ns; wire resume_wait = |resume_wait_r; reg po_done_ns, po_done_r; always @(posedge clk) po_done_r <= #TCQ po_done_ns; input samp_done; input po_rdy; reg up_ns, up_r; always @(posedge clk) up_r <= #TCQ up_ns; reg [1:0] two_ns, two_r; always @(posedge clk) two_r <= #TCQ two_ns; /* wire stg2_zero = ~|stg2_r; wire [8:0] stg2_2_zero = stg2_r[8] ? 9'd0 : stg2_r > 9'd63 ? 9'd63 : stg2_r; */ reg [3:0] sm_ns, sm_r; always @(posedge clk) sm_r <= #TCQ sm_ns; (* dont_touch = "true" *) reg phy_rddata_en_3_second_ns, phy_rddata_en_3_second_r; always @(posedge clk) phy_rddata_en_3_second_r <= #TCQ phy_rddata_en_3_second_ns; always @(*) phy_rddata_en_3_second_ns = ~reset_scan && (phy_rddata_en_3 ? ~phy_rddata_en_3_second_r : phy_rddata_en_3_second_r); (* dont_touch = "true" *) wire use_samp_done = nCK_PER_CLK == 2 ? phy_rddata_en_3 && phy_rddata_en_3_second_r : phy_rddata_en_3; reg po_center_wait; reg po_slew; reg po_finish_scan; always @(*) begin // Default next state assignments. cmplx_samples_done_ns = cmplx_samples_done_r; cmplx_stg3_final_ns = cmplx_stg3_final_r; scanning_right_ns = scanning_right_r; ninety_offsets_ns = ninety_offsets_r; ocal_scan_win_not_found_ns = ocal_scan_win_not_found_r; ocd_edge_detect_rdy_ns = ocd_edge_detect_rdy_r; ocd_ktap_left_ns = ocd_ktap_left_r; ocd_ktap_right_ns = ocd_ktap_right_r; ocd2stg2_inc_r = 1'b0; ocd2stg2_dec_r = 1'b0; ocd2stg3_inc_r = 1'b0; ocd2stg3_dec_r = 1'b0; oclkdelay_center_calib_start_ns = oclkdelay_center_calib_start_r; oclkdelay_center_calib_done_ns = 1'b0; oclk_center_write_resume_ns = oclk_center_write_resume_r; po_center_wait = 1'b0; po_done_ns = po_done_r; po_finish_scan = 1'b0; po_slew = 1'b0; poc_backup_ns = poc_backup_r; scan_done_r = 1'b0; simp_stg3_final_ns = simp_stg3_final_r; sm_ns = sm_r; taps_set_r = 1'b0; up_ns = up_r; stg2_ns = stg2_r; stg3_ns = stg3_r; two_ns = two_r; resume_wait_ns = resume_wait_r; if (rst == 1'b1) begin // RESET next states cmplx_samples_done_ns = 1'b0; ocal_scan_win_not_found_ns = 1'b0; ocd_ktap_left_ns = 1'b0; ocd_ktap_right_ns = 1'b0; ocd_edge_detect_rdy_ns = 1'b0; oclk_center_write_resume_ns = 1'b0; oclkdelay_center_calib_start_ns = 1'b0; po_done_ns = 1'b1; resume_wait_ns = 5'd0; sm_ns = /*AK("READY")*/4'd0; end else // State based actions and next states. case (sm_r) /*AL("READY")*/4'd0:begin poc_backup_ns = 1'b0; stg2_ns = {3'b0, wl_po_fine_cnt_sel}; stg3_ns = stg3_init; scanning_right_ns = 1'b0; if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1; if (!reset_scan && ~resume_wait) begin cmplx_samples_done_ns = 1'b0; ocal_scan_win_not_found_ns = 1'b0; taps_set_r = 1'b1; sm_ns = /*AK("SAMPLING")*/4'd1; end end /*AL("SAMPLING")*/4'd1:begin if (samp_done && use_samp_done) begin if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1; scanning_right_ns = scanning_right_r || left_stop; if (right_stop && scanning_right_r) begin oclkdelay_center_calib_start_ns = 1'b1; ocd_ktap_left_ns = 1'b1; ocal_scan_win_not_found_ns = win_not_found; sm_ns = /*AK("SLEW_PO")*/4'd3; end else begin if (scanning_right_ns) ocd2stg3_inc_r = 1'b1; else ocd2stg3_dec_r = 1'b1; sm_ns = /*AK("PO_WAIT")*/4'd2; end end end /*AL("PO_WAIT")*/4'd2:begin if (po_done_r && ~resume_wait) begin taps_set_r = 1'b1; sm_ns = /*AK("SAMPLING")*/4'd1; cmplx_samples_done_ns = 1'b0; end end /*AL("SLEW_PO")*/4'd3:begin po_slew = 1'b1; ninety_offsets_ns = |ninety_offsets_final ? 2'b01 : 2'b00; if (~resume_wait) begin if (po_done_r) begin if (inc_po_r) ocd2stg3_inc_r = 1'b1; else if (dec_po_r) ocd2stg3_dec_r = 1'b1; else if (~resume_wait) begin cmplx_samples_done_ns = 1'b0; sm_ns = /*AK("ALIGN_EDGES")*/4'd4; oclk_center_write_resume_ns = 1'b1; end end // if (po_done) end end // case: 3'd3 /*AL("ALIGN_EDGES")*/4'd4: if (~resume_wait) begin if (mmcm_edge_detect_done) begin ocd_edge_detect_rdy_ns = 1'b0; if (ocd_ktap_left_r) begin ocd_ktap_left_ns = 1'b0; ocd_ktap_right_ns = 1'b1; oclk_center_write_resume_ns = 1'b0; sm_ns = /*AK("SLEW_PO")*/4'd3; end else if (ocd_ktap_right_r) begin ocd_ktap_right_ns = 1'b0; sm_ns = /*AK("WAIT_ONE")*/4'd5; end else if (~mmcm_lbclk_edge_aligned) begin sm_ns = /*AK("DQS_STOP_WAIT")*/4'd6; oclk_center_write_resume_ns = 1'b0; end else begin if (ninety_offsets_r != ninety_offsets_final && ocd_edge_detect_rdy_r) begin ninety_offsets_ns = ninety_offsets_r + 2'b01; sm_ns = /*AK("WAIT_ONE")*/4'd5; end else begin oclk_center_write_resume_ns = 1'b0; poc_backup_ns = poc_backup; // stg2_ns = stg2_2_zero; sm_ns = /*AK("FINISH_SCAN")*/4'd8; end end // else: !if(~mmcm_lbclk_edge_aligned) end else ocd_edge_detect_rdy_ns = 1'b1; end // if (~resume_wait) /*AL("WAIT_ONE")*/4'd5: sm_ns = /*AK("ALIGN_EDGES")*/4'd4; /*AL("DQS_STOP_WAIT")*/4'd6: if (~resume_wait) begin ocd2stg3_dec_r = 1'b1; sm_ns = /*AK("CENTER_PO_WAIT")*/4'd7; end /*AL("CENTER_PO_WAIT")*/4'd7: begin po_center_wait = 1'b1; // Kludge to get around limitation of the AUTOs symbols. if (po_done_r) begin sm_ns = /*AK("ALIGN_EDGES")*/4'd4; oclk_center_write_resume_ns = 1'b1; end end /*AL("FINISH_SCAN")*/4'd8: begin po_finish_scan = 1'b1; if (resume_wait_r == 5'd1) begin if (~poc_backup_r) begin oclkdelay_center_calib_done_ns = 1'b1; oclkdelay_center_calib_start_ns = 1'b0; end end if (~resume_wait) begin if (po_rdy) if (poc_backup_r) begin ocd2stg3_inc_r = 1'b1; poc_backup_ns = 1'b0; end else if (~final_stg2_inc && ~final_stg2_dec) begin if (complex_oclkdelay_calib_start) cmplx_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r; else simp_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r; sm_ns = /*AK("READY")*/4'd0; scan_done_r = 1'b1; end else begin ocd2stg2_inc_r = final_stg2_inc; ocd2stg2_dec_r = final_stg2_dec; end end // if (~resume_wait) end // case: 4'd8 endcase // case (sm_r) if (ocd2stg3_inc_r) begin stg3_ns = stg3_r + 6'h1; up_ns = 1'b0; end if (ocd2stg3_dec_r) begin stg3_ns = stg3_r - 6'h1; up_ns = 1'b1; end if (ocd2stg3_inc_r || ocd2stg3_dec_r) begin po_done_ns = 1'b0; two_ns = 2'b00; end if (~po_done_r) if (po_rdy) if (two_r == 2'b10 || po_center_wait || po_slew || po_finish_scan) po_done_ns = 1'b1; else begin two_ns = two_r + 2'b1; if (up_r) begin stg2_ns = stg2_r + 9'b1; if (stg2_r >= 9'd0 && stg2_r < 9'd63) ocd2stg2_inc_r = 1'b1; end else begin stg2_ns = stg2_r - 9'b1; if (stg2_r > 9'd0 && stg2_r <= 9'd63) ocd2stg2_dec_r = 1'b1; end end // else: !if(two_r == 2'b10) if (ocd_ktap_left_ns && ~ocd_ktap_left_r) resume_wait_ns = 5'b1; else if (oclk_center_write_resume_ns ^ oclk_center_write_resume_r) resume_wait_ns = 5'd15; else if (cmplx_samples_done_ns & ~cmplx_samples_done_r || complex_oclkdelay_calib_start & reset_scan || poc_backup_r & ocd2stg3_inc_r) resume_wait_ns = 5'd31; else if (|resume_wait_r) resume_wait_ns = resume_wait_r - 5'd1; end // always @ begin endmodule // mig_7series_v2_3_ddr_phy_ocd_po_cntlr // Local Variables: // verilog-autolabel-prefix: "4'd" // End:
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: crossbar.v // // Description: // This module is a M-master to N-slave AXI axi_crossbar_v2_1_crossbar switch. // The interface of this module consists of a vectored slave and master interface // in which all slots are sized and synchronized to the native width and clock // of the interconnect. // The SAMD axi_crossbar_v2_1_crossbar supports only AXI4 and AXI3 protocols. // All width, clock and protocol conversions are done outside this block, as are // any pipeline registers or data FIFOs. // This module contains all arbitration, decoders and channel multiplexing logic. // It also contains the diagnostic registers and control interface. // //----------------------------------------------------------------------------- // // Structure: // crossbar // si_transactor // addr_decoder // comparator_static // mux_enc // axic_srl_fifo // arbiter_resp // splitter // wdata_router // axic_reg_srl_fifo // wdata_mux // axic_reg_srl_fifo // mux_enc // addr_decoder // comparator_static // axic_srl_fifo // axi_register_slice // addr_arbiter // mux_enc // decerr_slave // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_crossbar # ( parameter C_FAMILY = "none", parameter integer C_NUM_SLAVE_SLOTS = 1, parameter integer C_NUM_MASTER_SLOTS = 1, parameter integer C_NUM_ADDR_RANGES = 1, parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_PROTOCOL = 0, parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}}, parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}}, parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}}, parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}}, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE = {C_NUM_SLAVE_SLOTS{1'b1}}, parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ = {C_NUM_SLAVE_SLOTS{1'b1}}, parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE = {C_NUM_MASTER_SLOTS{1'b1}}, parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ = {C_NUM_MASTER_SLOTS{1'b1}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = {C_NUM_SLAVE_SLOTS{32'h00000000}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = {C_NUM_SLAVE_SLOTS{32'h00000001}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = {C_NUM_SLAVE_SLOTS{32'h00000001}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = {C_NUM_MASTER_SLOTS{32'h00000001}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = {C_NUM_MASTER_SLOTS{32'h00000001}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = {C_NUM_SLAVE_SLOTS{32'h00000000}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = {C_NUM_MASTER_SLOTS{32'h00000000}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}}, parameter integer C_RANGE_CHECK = 0, parameter integer C_ADDR_DECODE = 0, parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_W_ISSUE_WIDTH = {C_NUM_MASTER_SLOTS+1{32'h00000000}}, parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_R_ISSUE_WIDTH = {C_NUM_MASTER_SLOTS+1{32'h00000000}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_W_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_R_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}}, parameter integer C_DEBUG = 1 ) ( // Global Signals input wire ACLK, input wire ARESETN, // Slave Interface Write Address Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_AWLEN, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWSIZE, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWBURST, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWLOCK, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWCACHE, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWPROT, // input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWREGION, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWQOS, input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWREADY, // Slave Interface Write Data Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_WID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WLAST, input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WREADY, // Slave Interface Write Response Ports output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_BID, output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_BRESP, output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BVALID, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BREADY, // Slave Interface Read Address Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_ARID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_ARLEN, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARSIZE, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARBURST, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARLOCK, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARCACHE, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARPROT, // input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARREGION, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARQOS, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARREADY, // Slave Interface Read Data Ports output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_RID, output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_RRESP, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RLAST, output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RVALID, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RREADY, // Master Interface Write Address Port output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_AWLEN, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWSIZE, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWBURST, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWLOCK, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWCACHE, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWPROT, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWREGION, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWQOS, output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWREADY, // Master Interface Write Data Ports output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_WID, output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WLAST, output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WREADY, // Master Interface Write Response Ports input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_BID, input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_BRESP, input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BVALID, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BREADY, // Master Interface Read Address Port output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_ARID, output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_ARLEN, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARSIZE, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARBURST, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARLOCK, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARCACHE, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARPROT, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARREGION, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARQOS, output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARREADY, // Master Interface Read Data Ports input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_RID, input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_RRESP, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RLAST, input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RVALID, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RREADY ); localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; localparam integer P_WRITE = 0; localparam integer P_READ = 1; localparam integer P_NUM_MASTER_SLOTS_LOG = f_ceil_log2(C_NUM_MASTER_SLOTS); localparam integer P_NUM_SLAVE_SLOTS_LOG = f_ceil_log2((C_NUM_SLAVE_SLOTS>1) ? C_NUM_SLAVE_SLOTS : 2); localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1; localparam integer P_ST_AWMESG_WIDTH = 2+4+4 + C_AXI_AWUSER_WIDTH; localparam integer P_AA_AWMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_AWMESG_WIDTH; localparam integer P_ST_ARMESG_WIDTH = 2+4+4 + C_AXI_ARUSER_WIDTH; localparam integer P_AA_ARMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_ARMESG_WIDTH; localparam integer P_ST_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH; localparam integer P_ST_RMESG_WIDTH = 2 + C_AXI_RUSER_WIDTH + C_AXI_DATA_WIDTH; localparam integer P_WR_WMESG_WIDTH = C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH; localparam [31:0] P_BYPASS = 32'h00000000; localparam [31:0] P_FWD_REV = 32'h00000001; localparam [31:0] P_SIMPLE = 32'h00000007; localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_READ = {1'b1, C_M_AXI_SUPPORTS_READ[0+:C_NUM_MASTER_SLOTS]}; localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_WRITE = {1'b1, C_M_AXI_SUPPORTS_WRITE[0+:C_NUM_MASTER_SLOTS]}; localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_WRITE_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]}; localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_READ_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]}; localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_WRITE_CONNECTIVITY = f_si_write_connectivity(0); localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_READ_CONNECTIVITY = f_si_read_connectivity(0); localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_ISSUING = {32'h00000001, C_M_AXI_READ_ISSUING[0+:C_NUM_MASTER_SLOTS*32]}; localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_ISSUING = {32'h00000001, C_M_AXI_WRITE_ISSUING[0+:C_NUM_MASTER_SLOTS*32]}; localparam P_DECERR = 2'b11; //--------------------------------------------------------------------------- // Functions //--------------------------------------------------------------------------- // Ceiling of log2(x) function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2**acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value // only for end-point SI-slots function [C_AXI_ID_WIDTH-1:0] f_extend_ID ( input [C_AXI_ID_WIDTH-1:0] s_id, input integer slot ); begin f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH])); end endfunction // Write connectivity array transposed function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_write_connectivity ( input integer null_arg ); integer si_slot; integer mi_slot; reg [C_NUM_SLAVE_SLOTS*32-1:0] result; begin result = {C_NUM_SLAVE_SLOTS*32{1'b1}}; for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin result[si_slot*32+mi_slot] = C_M_AXI_WRITE_CONNECTIVITY[mi_slot*32+si_slot]; end end f_si_write_connectivity = result; end endfunction // Read connectivity array transposed function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_read_connectivity ( input integer null_arg ); integer si_slot; integer mi_slot; reg [C_NUM_SLAVE_SLOTS*32-1:0] result; begin result = {C_NUM_SLAVE_SLOTS*32{1'b1}}; for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin result[si_slot*32+mi_slot] = C_M_AXI_READ_CONNECTIVITY[mi_slot*32+si_slot]; end end f_si_read_connectivity = result; end endfunction genvar gen_si_slot; genvar gen_mi_slot; wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0] si_st_awmesg ; wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0] st_tmp_awmesg ; wire [C_NUM_SLAVE_SLOTS*P_AA_AWMESG_WIDTH-1:0] tmp_aa_awmesg ; wire [P_AA_AWMESG_WIDTH-1:0] aa_mi_awmesg ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] st_aa_awid ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] st_aa_awaddr ; wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_awlen ; wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_awsize ; wire [C_NUM_SLAVE_SLOTS*2-1:0] st_aa_awlock ; wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_awprot ; wire [C_NUM_SLAVE_SLOTS*4-1:0] st_aa_awregion ; wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_awerror ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_aa_awtarget_hot ; wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0] st_aa_awtarget_enc ; wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0] aa_wm_awgrant_enc ; wire [(C_NUM_MASTER_SLOTS+1)-1:0] aa_mi_awtarget_hot ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_awvalid_qual ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_ss_awvalid ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_ss_awready ; wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_wr_awvalid ; wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_wr_awready ; wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_aa_awvalid ; wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_aa_awready ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] sa_wm_awvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] sa_wm_awready ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awready ; wire aa_sa_awvalid ; wire aa_sa_awready ; wire aa_mi_arready ; wire mi_awvalid_en ; wire sa_wm_awvalid_en ; wire sa_wm_awready_mux ; wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0] si_st_armesg ; wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0] st_tmp_armesg ; wire [C_NUM_SLAVE_SLOTS*P_AA_ARMESG_WIDTH-1:0] tmp_aa_armesg ; wire [P_AA_ARMESG_WIDTH-1:0] aa_mi_armesg ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] st_aa_arid ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] st_aa_araddr ; wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_arlen ; wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_arsize ; wire [C_NUM_SLAVE_SLOTS*2-1:0] st_aa_arlock ; wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_arprot ; wire [C_NUM_SLAVE_SLOTS*4-1:0] st_aa_arregion ; wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_arerror ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_aa_artarget_hot ; wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0] st_aa_artarget_enc ; wire [(C_NUM_MASTER_SLOTS+1)-1:0] aa_mi_artarget_hot ; wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0] aa_mi_argrant_enc ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arvalid_qual ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arvalid ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arready ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_arvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_arready ; wire aa_mi_arvalid ; wire mi_awready_mux ; wire [C_NUM_SLAVE_SLOTS*P_ST_BMESG_WIDTH-1:0] st_si_bmesg ; wire [(C_NUM_MASTER_SLOTS+1)*P_ST_BMESG_WIDTH-1:0] st_mr_bmesg ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] st_mr_bid ; wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] st_mr_bresp ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0] st_mr_buser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_bvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_bready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_bready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_bid_target ; wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_mr_bid_target ; wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0] debug_bid_target_i ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] bid_match ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_bid ; wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] mi_bresp ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0] mi_buser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_bvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_bready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] bready_carry ; wire [C_NUM_SLAVE_SLOTS*P_ST_RMESG_WIDTH-1:0] st_si_rmesg ; wire [(C_NUM_MASTER_SLOTS+1)*P_ST_RMESG_WIDTH-1:0] st_mr_rmesg ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] st_mr_rid ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] st_mr_rdata ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0] st_mr_ruser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rlast ; wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] st_mr_rresp ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_rready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_rid_target ; wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_mr_rid_target ; wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0] debug_rid_target_i ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] rid_match ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_rid ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] mi_rdata ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0] mi_ruser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rlast ; wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] mi_rresp ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] rready_carry ; wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0] si_wr_wmesg ; wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0] wr_wm_wmesg ; wire [C_NUM_SLAVE_SLOTS*1-1:0] wr_wm_wlast ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] wr_tmp_wvalid ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] wr_tmp_wready ; wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_wm_wvalid ; wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_wm_wready ; wire [(C_NUM_MASTER_SLOTS+1)*P_WR_WMESG_WIDTH-1:0] wm_mr_wmesg ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] wm_mr_wdata ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0] wm_mr_wstrb ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] wm_mr_wid ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0] wm_mr_wuser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wlast ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wready ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] mi_wdata ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0] mi_wstrb ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0] mi_wuser ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_wid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wlast ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wready ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] w_cmd_push ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] w_cmd_pop ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] r_cmd_push ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] r_cmd_pop ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awmaxissuing ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_armaxissuing ; reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] w_issuing_cnt ; reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] r_issuing_cnt ; reg [8-1:0] debug_aw_trans_seq_i ; reg [8-1:0] debug_ar_trans_seq_i ; wire [(C_NUM_MASTER_SLOTS+1)*8-1:0] debug_w_trans_seq_i ; reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] debug_w_beat_cnt_i ; reg aresetn_d = 1'b0; // Reset delay register always @(posedge ACLK) begin if (~ARESETN) begin aresetn_d <= 1'b0; end else begin aresetn_d <= ARESETN; end end wire reset; assign reset = ~aresetn_d; generate for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_slave_slots if (C_S_AXI_SUPPORTS_READ[gen_si_slot]) begin : gen_si_read axi_crossbar_v2_1_si_transactor # // "ST": SI Transactor (read channel) ( .C_FAMILY (C_FAMILY), .C_SI (gen_si_slot), .C_DIR (P_READ), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_NUM_M (C_NUM_MASTER_SLOTS), .C_NUM_M_LOG (P_NUM_MASTER_SLOTS_LOG), .C_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE[gen_si_slot*32+:32]), .C_ACCEPTANCE_LOG (C_R_ACCEPT_WIDTH[gen_si_slot*32+:32]), .C_ID_WIDTH (C_AXI_ID_WIDTH), .C_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]), .C_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AMESG_WIDTH (P_ST_ARMESG_WIDTH), .C_RMESG_WIDTH (P_ST_RMESG_WIDTH), .C_BASE_ID (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]), .C_HIGH_ID (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]), .C_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]), .C_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_HIGH_ADDR (C_M_AXI_HIGH_ADDR), .C_TARGET_QUAL (P_S_AXI_READ_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_RANGE_CHECK (C_RANGE_CHECK), .C_ADDR_DECODE (C_ADDR_DECODE), .C_ERR_MODE (C_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) si_transactor_ar ( .ACLK (ACLK), .ARESET (reset), .S_AID (f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)), .S_AADDR (S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]), .S_ALEN (S_AXI_ARLEN[gen_si_slot*8+:8]), .S_ASIZE (S_AXI_ARSIZE[gen_si_slot*3+:3]), .S_ABURST (S_AXI_ARBURST[gen_si_slot*2+:2]), .S_ALOCK (S_AXI_ARLOCK[gen_si_slot*2+:2]), .S_APROT (S_AXI_ARPROT[gen_si_slot*3+:3]), // .S_AREGION (S_AXI_ARREGION[gen_si_slot*4+:4]), .S_AMESG (si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]), .S_AVALID (S_AXI_ARVALID[gen_si_slot]), .S_AREADY (S_AXI_ARREADY[gen_si_slot]), .M_AID (st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .M_AADDR (st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]), .M_ALEN (st_aa_arlen[gen_si_slot*8+:8]), .M_ASIZE (st_aa_arsize[gen_si_slot*3+:3]), .M_ALOCK (st_aa_arlock[gen_si_slot*2+:2]), .M_APROT (st_aa_arprot[gen_si_slot*3+:3]), .M_AREGION (st_aa_arregion[gen_si_slot*4+:4]), .M_AMESG (st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]), .M_ATARGET_HOT (st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_ATARGET_ENC (st_aa_artarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]), .M_AERROR (st_aa_arerror[gen_si_slot*8+:8]), .M_AVALID_QUAL (st_aa_arvalid_qual[gen_si_slot]), .M_AVALID (st_aa_arvalid[gen_si_slot]), .M_AREADY (st_aa_arready[gen_si_slot]), .S_RID (S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .S_RMESG (st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH]), .S_RLAST (S_AXI_RLAST[gen_si_slot]), .S_RVALID (S_AXI_RVALID[gen_si_slot]), .S_RREADY (S_AXI_RREADY[gen_si_slot]), .M_RID (st_mr_rid), .M_RLAST (st_mr_rlast), .M_RMESG (st_mr_rmesg), .M_RVALID (st_mr_rvalid), .M_RREADY (st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_RTARGET (st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .DEBUG_A_TRANS_SEQ (C_DEBUG ? debug_ar_trans_seq_i : 8'h0) ); assign si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH] = { S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH], S_AXI_ARQOS[gen_si_slot*4+:4], S_AXI_ARCACHE[gen_si_slot*4+:4], S_AXI_ARBURST[gen_si_slot*2+:2] }; assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = { st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH], st_aa_arregion[gen_si_slot*4+:4], st_aa_arprot[gen_si_slot*3+:3], st_aa_arlock[gen_si_slot*2+:2], st_aa_arsize[gen_si_slot*3+:3], st_aa_arlen[gen_si_slot*8+:8], st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH], st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] }; assign S_AXI_RRESP[gen_si_slot*2+:2] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:2]; assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2 +: C_AXI_RUSER_WIDTH]; assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2+C_AXI_RUSER_WIDTH +: C_AXI_DATA_WIDTH]; end else begin : gen_no_si_read assign S_AXI_ARREADY[gen_si_slot] = 1'b0; assign st_aa_arvalid[gen_si_slot] = 1'b0; assign st_aa_arvalid_qual[gen_si_slot] = 1'b1; assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = 0; assign S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign S_AXI_RRESP[gen_si_slot*2+:2] = 0; assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0; assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0; assign S_AXI_RVALID[gen_si_slot] = 1'b0; assign S_AXI_RLAST[gen_si_slot] = 1'b0; assign st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; assign st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; end // gen_si_read if (C_S_AXI_SUPPORTS_WRITE[gen_si_slot]) begin : gen_si_write axi_crossbar_v2_1_si_transactor # // "ST": SI Transactor (write channel) ( .C_FAMILY (C_FAMILY), .C_SI (gen_si_slot), .C_DIR (P_WRITE), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_NUM_M (C_NUM_MASTER_SLOTS), .C_NUM_M_LOG (P_NUM_MASTER_SLOTS_LOG), .C_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE[gen_si_slot*32+:32]), .C_ACCEPTANCE_LOG (C_W_ACCEPT_WIDTH[gen_si_slot*32+:32]), .C_ID_WIDTH (C_AXI_ID_WIDTH), .C_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]), .C_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AMESG_WIDTH (P_ST_AWMESG_WIDTH), .C_RMESG_WIDTH (P_ST_BMESG_WIDTH), .C_BASE_ID (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]), .C_HIGH_ID (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]), .C_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]), .C_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_HIGH_ADDR (C_M_AXI_HIGH_ADDR), .C_TARGET_QUAL (P_S_AXI_WRITE_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_RANGE_CHECK (C_RANGE_CHECK), .C_ADDR_DECODE (C_ADDR_DECODE), .C_ERR_MODE (C_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) si_transactor_aw ( .ACLK (ACLK), .ARESET (reset), .S_AID (f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)), .S_AADDR (S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]), .S_ALEN (S_AXI_AWLEN[gen_si_slot*8+:8]), .S_ASIZE (S_AXI_AWSIZE[gen_si_slot*3+:3]), .S_ABURST (S_AXI_AWBURST[gen_si_slot*2+:2]), .S_ALOCK (S_AXI_AWLOCK[gen_si_slot*2+:2]), .S_APROT (S_AXI_AWPROT[gen_si_slot*3+:3]), // .S_AREGION (S_AXI_AWREGION[gen_si_slot*4+:4]), .S_AMESG (si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]), .S_AVALID (S_AXI_AWVALID[gen_si_slot]), .S_AREADY (S_AXI_AWREADY[gen_si_slot]), .M_AID (st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .M_AADDR (st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]), .M_ALEN (st_aa_awlen[gen_si_slot*8+:8]), .M_ASIZE (st_aa_awsize[gen_si_slot*3+:3]), .M_ALOCK (st_aa_awlock[gen_si_slot*2+:2]), .M_APROT (st_aa_awprot[gen_si_slot*3+:3]), .M_AREGION (st_aa_awregion[gen_si_slot*4+:4]), .M_AMESG (st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]), .M_ATARGET_HOT (st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_ATARGET_ENC (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]), .M_AERROR (st_aa_awerror[gen_si_slot*8+:8]), .M_AVALID_QUAL (st_aa_awvalid_qual[gen_si_slot]), .M_AVALID (st_ss_awvalid[gen_si_slot]), .M_AREADY (st_ss_awready[gen_si_slot]), .S_RID (S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .S_RMESG (st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH]), .S_RLAST (), .S_RVALID (S_AXI_BVALID[gen_si_slot]), .S_RREADY (S_AXI_BREADY[gen_si_slot]), .M_RID (st_mr_bid), .M_RLAST ({(C_NUM_MASTER_SLOTS+1){1'b1}}), .M_RMESG (st_mr_bmesg), .M_RVALID (st_mr_bvalid), .M_RREADY (st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_RTARGET (st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .DEBUG_A_TRANS_SEQ (C_DEBUG ? debug_aw_trans_seq_i : 8'h0) ); // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order. assign si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH] = { S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH], S_AXI_AWQOS[gen_si_slot*4+:4], S_AXI_AWCACHE[gen_si_slot*4+:4], S_AXI_AWBURST[gen_si_slot*2+:2] }; assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = { st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH], st_aa_awregion[gen_si_slot*4+:4], st_aa_awprot[gen_si_slot*3+:3], st_aa_awlock[gen_si_slot*2+:2], st_aa_awsize[gen_si_slot*3+:3], st_aa_awlen[gen_si_slot*8+:8], st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH], st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] }; assign S_AXI_BRESP[gen_si_slot*2+:2] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:2]; assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+2 +: C_AXI_BUSER_WIDTH]; // AW SI-transactor transfer completes upon completion of both W-router address acceptance (command push) and AW arbitration axi_crossbar_v2_1_splitter # // "SS": Splitter from SI-Transactor (write channel) ( .C_NUM_M (2) ) splitter_aw_si ( .ACLK (ACLK), .ARESET (reset), .S_VALID (st_ss_awvalid[gen_si_slot]), .S_READY (st_ss_awready[gen_si_slot]), .M_VALID ({ss_wr_awvalid[gen_si_slot], ss_aa_awvalid[gen_si_slot]}), .M_READY ({ss_wr_awready[gen_si_slot], ss_aa_awready[gen_si_slot]}) ); axi_crossbar_v2_1_wdata_router # // "WR": Write data Router ( .C_FAMILY (C_FAMILY), .C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS+1), .C_SELECT_WIDTH (P_NUM_MASTER_SLOTS_LOG+1), .C_WMESG_WIDTH (P_WR_WMESG_WIDTH), .C_FIFO_DEPTH_LOG (C_W_ACCEPT_WIDTH[gen_si_slot*32+:6]) ) wdata_router_w ( .ACLK (ACLK), .ARESET (reset), // Write transfer input from the current SI-slot .S_WMESG (si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]), .S_WLAST (S_AXI_WLAST[gen_si_slot]), .S_WVALID (S_AXI_WVALID[gen_si_slot]), .S_WREADY (S_AXI_WREADY[gen_si_slot]), // Vector of write transfer outputs to each MI-slot's W-mux .M_WMESG (wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH]), .M_WLAST (wr_wm_wlast[gen_si_slot]), .M_WVALID (wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_WREADY (wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), // AW command push from local SI-slot .S_ASELECT (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]), // Target MI-slot .S_AVALID (ss_wr_awvalid[gen_si_slot]), .S_AREADY (ss_wr_awready[gen_si_slot]) ); assign si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH] = { ((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0), S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH], S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8], S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] }; end else begin : gen_no_si_write assign S_AXI_AWREADY[gen_si_slot] = 1'b0; assign ss_aa_awvalid[gen_si_slot] = 1'b0; assign st_aa_awvalid_qual[gen_si_slot] = 1'b1; assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = 0; assign S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign S_AXI_BRESP[gen_si_slot*2+:2] = 0; assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0; assign S_AXI_BVALID[gen_si_slot] = 1'b0; assign st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; assign S_AXI_WREADY[gen_si_slot] = 1'b0; assign wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH] = 0; assign wr_wm_wlast[gen_si_slot] = 1'b0; assign wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; assign st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; end // gen_si_write end // gen_slave_slots for (gen_mi_slot=0; gen_mi_slot<C_NUM_MASTER_SLOTS+1; gen_mi_slot=gen_mi_slot+1) begin : gen_master_slots if (P_M_AXI_SUPPORTS_READ[gen_mi_slot]) begin : gen_mi_read if (C_NUM_SLAVE_SLOTS>1) begin : gen_rid_decoder axi_crossbar_v2_1_addr_decoder # ( .C_FAMILY (C_FAMILY), .C_NUM_TARGETS (C_NUM_SLAVE_SLOTS), .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_NUM_RANGES (1), .C_ADDR_WIDTH (C_AXI_ID_WIDTH), .C_TARGET_ENC (C_DEBUG), .C_TARGET_HOT (1), .C_REGION_ENC (0), .C_BASE_ADDR (C_S_AXI_BASE_ID), .C_HIGH_ADDR (C_S_AXI_HIGH_ID), .C_TARGET_QUAL (P_M_AXI_READ_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]), .C_RESOLUTION (0) ) rid_decoder_inst ( .ADDR (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .TARGET_HOT (tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), .TARGET_ENC (debug_rid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]), .MATCH (rid_match[gen_mi_slot]), .REGION () ); end else begin : gen_no_rid_decoder assign tmp_mr_rid_target[gen_mi_slot] = 1'b1; // All response transfers route to solo SI-slot. assign rid_match[gen_mi_slot] = 1'b1; end assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = { st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH], st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH], st_mr_rresp[gen_mi_slot*2+:2] }; end else begin : gen_no_mi_read assign tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0; assign rid_match[gen_mi_slot] = 1'b0; assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = 0; end // gen_mi_read if (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]) begin : gen_mi_write if (C_NUM_SLAVE_SLOTS>1) begin : gen_bid_decoder axi_crossbar_v2_1_addr_decoder # ( .C_FAMILY (C_FAMILY), .C_NUM_TARGETS (C_NUM_SLAVE_SLOTS), .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_NUM_RANGES (1), .C_ADDR_WIDTH (C_AXI_ID_WIDTH), .C_TARGET_ENC (C_DEBUG), .C_TARGET_HOT (1), .C_REGION_ENC (0), .C_BASE_ADDR (C_S_AXI_BASE_ID), .C_HIGH_ADDR (C_S_AXI_HIGH_ID), .C_TARGET_QUAL (P_M_AXI_WRITE_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]), .C_RESOLUTION (0) ) bid_decoder_inst ( .ADDR (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .TARGET_HOT (tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), .TARGET_ENC (debug_bid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]), .MATCH (bid_match[gen_mi_slot]), .REGION () ); end else begin : gen_no_bid_decoder assign tmp_mr_bid_target[gen_mi_slot] = 1'b1; // All response transfers route to solo SI-slot. assign bid_match[gen_mi_slot] = 1'b1; end axi_crossbar_v2_1_wdata_mux # // "WM": Write data Mux, per MI-slot (incl error-handler) ( .C_FAMILY (C_FAMILY), .C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS), .C_SELECT_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_WMESG_WIDTH (P_WR_WMESG_WIDTH), .C_FIFO_DEPTH_LOG (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]) ) wdata_mux_w ( .ACLK (ACLK), .ARESET (reset), // Vector of write transfer inputs from each SI-slot's W-router .S_WMESG (wr_wm_wmesg), .S_WLAST (wr_wm_wlast), .S_WVALID (tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), .S_WREADY (tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), // Write transfer output to the current MI-slot .M_WMESG (wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]), .M_WLAST (wm_mr_wlast[gen_mi_slot]), .M_WVALID (wm_mr_wvalid[gen_mi_slot]), .M_WREADY (wm_mr_wready[gen_mi_slot]), // AW command push from AW arbiter output .S_ASELECT (aa_wm_awgrant_enc), // SI-slot selected by arbiter .S_AVALID (sa_wm_awvalid[gen_mi_slot]), .S_AREADY (sa_wm_awready[gen_mi_slot]) ); if (C_DEBUG) begin : gen_debug_w // DEBUG WRITE BEAT COUNTER always @(posedge ACLK) begin if (reset) begin debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0; end else begin if (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot]) begin if (mi_wlast[gen_mi_slot]) begin debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0; end else begin debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= debug_w_beat_cnt_i[gen_mi_slot*8+:8] + 1; end end end end // clocked process // DEBUG W-CHANNEL TRANSACTION SEQUENCE QUEUE axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]), .C_USE_FULL (0) ) debug_w_seq_fifo ( .ACLK (ACLK), .ARESET (reset), .S_MESG (debug_aw_trans_seq_i), .S_VALID (sa_wm_awvalid[gen_mi_slot]), .S_READY (), .M_MESG (debug_w_trans_seq_i[gen_mi_slot*8+:8]), .M_VALID (), .M_READY (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot] & mi_wlast[gen_mi_slot]) ); end // gen_debug_w assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH +: C_AXI_DATA_WIDTH]; assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8]; assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH]; assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+(C_AXI_DATA_WIDTH/8)+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH]; assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = { st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH], st_mr_bresp[gen_mi_slot*2+:2] }; end else begin : gen_no_mi_write assign tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0; assign bid_match[gen_mi_slot] = 1'b0; assign wm_mr_wvalid[gen_mi_slot] = 0; assign wm_mr_wlast[gen_mi_slot] = 0; assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0; assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = 0; assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = 0; assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = 0; assign tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0; assign sa_wm_awready[gen_mi_slot] = 0; end // gen_mi_write for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_trans_si // Transpose handshakes from W-router (SxM) to W-mux (MxS). assign tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot] = wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; assign wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot]; // Transpose response enables from ID decoders (MxS) to si_transactors (SxM). assign st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot]; assign st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot]; end // gen_trans_si assign bready_carry[gen_mi_slot] = st_tmp_bready[gen_mi_slot]; assign rready_carry[gen_mi_slot] = st_tmp_rready[gen_mi_slot]; for (gen_si_slot=1; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_resp_carry_si assign bready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = // Generate M_BREADY if ... bready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] | // For any SI-slot (OR carry-chain across all SI-slots), ... st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; // The write SI transactor indicates BREADY for that MI-slot. assign rready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = // Generate M_RREADY if ... rready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] | // For any SI-slot (OR carry-chain across all SI-slots), ... st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; // The write SI transactor indicates RREADY for that MI-slot. end // gen_resp_carry_si assign w_cmd_push[gen_mi_slot] = mi_awvalid[gen_mi_slot] && mi_awready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]; assign r_cmd_push[gen_mi_slot] = mi_arvalid[gen_mi_slot] && mi_arready[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot]; assign w_cmd_pop[gen_mi_slot] = st_mr_bvalid[gen_mi_slot] && st_mr_bready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]; assign r_cmd_pop[gen_mi_slot] = st_mr_rvalid[gen_mi_slot] && st_mr_rready[gen_mi_slot] && st_mr_rlast[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot]; // Disqualify arbitration of SI-slot if targeted MI-slot has reached its issuing limit. assign mi_awmaxissuing[gen_mi_slot] = (w_issuing_cnt[gen_mi_slot*8 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] == P_M_AXI_WRITE_ISSUING[gen_mi_slot*32 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~w_cmd_pop[gen_mi_slot]; assign mi_armaxissuing[gen_mi_slot] = (r_issuing_cnt[gen_mi_slot*8 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] == P_M_AXI_READ_ISSUING[gen_mi_slot*32 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~r_cmd_pop[gen_mi_slot]; always @(posedge ACLK) begin if (reset) begin w_issuing_cnt[gen_mi_slot*8+:8] <= 0; // Some high-order bits remain constant 0 r_issuing_cnt[gen_mi_slot*8+:8] <= 0; // Some high-order bits remain constant 0 end else begin if (w_cmd_push[gen_mi_slot] && ~w_cmd_pop[gen_mi_slot]) begin w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1; end else if (w_cmd_pop[gen_mi_slot] && ~w_cmd_push[gen_mi_slot] && (|w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1; end if (r_cmd_push[gen_mi_slot] && ~r_cmd_pop[gen_mi_slot]) begin r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1; end else if (r_cmd_pop[gen_mi_slot] && ~r_cmd_push[gen_mi_slot] && (|r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1; end end end // Clocked process // Reg-slice must break combinatorial path from M_BID and M_RID inputs to M_BREADY and M_RREADY outputs. // (See m_rready_i and m_resp_en combinatorial assignments in si_transactor.) // Reg-slice incurs +1 latency, but no bubble-cycles. axi_register_slice_v2_1_axi_register_slice # // "MR": MI-side R/B-channel Reg-slice, per MI-slot (pass-through if only 1 SI-slot configured) ( .C_FAMILY (C_FAMILY), .C_AXI_PROTOCOL ((C_AXI_PROTOCOL == P_AXI3) ? P_AXI3 : P_AXI4), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_ADDR_WIDTH (1), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AWUSER_WIDTH (1), .C_AXI_ARUSER_WIDTH (1), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_REG_CONFIG_AW (P_BYPASS), .C_REG_CONFIG_AR (P_BYPASS), .C_REG_CONFIG_W (P_BYPASS), .C_REG_CONFIG_R (P_M_AXI_SUPPORTS_READ[gen_mi_slot] ? P_FWD_REV : P_BYPASS), .C_REG_CONFIG_B (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot] ? P_SIMPLE : P_BYPASS) ) reg_slice_mi ( .aresetn (ARESETN), .aclk (ACLK), .s_axi_awid ({C_AXI_ID_WIDTH{1'b0}}), .s_axi_awaddr ({1{1'b0}}), .s_axi_awlen ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}), .s_axi_awsize ({3{1'b0}}), .s_axi_awburst ({2{1'b0}}), .s_axi_awlock ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}), .s_axi_awcache ({4{1'b0}}), .s_axi_awprot ({3{1'b0}}), .s_axi_awregion ({4{1'b0}}), .s_axi_awqos ({4{1'b0}}), .s_axi_awuser ({1{1'b0}}), .s_axi_awvalid ({1{1'b0}}), .s_axi_awready (), .s_axi_wid (wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .s_axi_wdata (wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]), .s_axi_wstrb (wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]), .s_axi_wlast (wm_mr_wlast[gen_mi_slot]), .s_axi_wuser (wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]), .s_axi_wvalid (wm_mr_wvalid[gen_mi_slot]), .s_axi_wready (wm_mr_wready[gen_mi_slot]), .s_axi_bid (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ), .s_axi_bresp (st_mr_bresp[gen_mi_slot*2+:2] ), .s_axi_buser (st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ), .s_axi_bvalid (st_mr_bvalid[gen_mi_slot*1+:1] ), .s_axi_bready (st_mr_bready[gen_mi_slot*1+:1] ), .s_axi_arid ({C_AXI_ID_WIDTH{1'b0}}), .s_axi_araddr ({1{1'b0}}), .s_axi_arlen ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}), .s_axi_arsize ({3{1'b0}}), .s_axi_arburst ({2{1'b0}}), .s_axi_arlock ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}), .s_axi_arcache ({4{1'b0}}), .s_axi_arprot ({3{1'b0}}), .s_axi_arregion ({4{1'b0}}), .s_axi_arqos ({4{1'b0}}), .s_axi_aruser ({1{1'b0}}), .s_axi_arvalid ({1{1'b0}}), .s_axi_arready (), .s_axi_rid (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ), .s_axi_rdata (st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] ), .s_axi_rresp (st_mr_rresp[gen_mi_slot*2+:2] ), .s_axi_rlast (st_mr_rlast[gen_mi_slot*1+:1] ), .s_axi_ruser (st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] ), .s_axi_rvalid (st_mr_rvalid[gen_mi_slot*1+:1] ), .s_axi_rready (st_mr_rready[gen_mi_slot*1+:1] ), .m_axi_awid (), .m_axi_awaddr (), .m_axi_awlen (), .m_axi_awsize (), .m_axi_awburst (), .m_axi_awlock (), .m_axi_awcache (), .m_axi_awprot (), .m_axi_awregion (), .m_axi_awqos (), .m_axi_awuser (), .m_axi_awvalid (), .m_axi_awready ({1{1'b0}}), .m_axi_wid (mi_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .m_axi_wdata (mi_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]), .m_axi_wstrb (mi_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]), .m_axi_wlast (mi_wlast[gen_mi_slot]), .m_axi_wuser (mi_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]), .m_axi_wvalid (mi_wvalid[gen_mi_slot]), .m_axi_wready (mi_wready[gen_mi_slot]), .m_axi_bid (mi_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ), .m_axi_bresp (mi_bresp[gen_mi_slot*2+:2] ), .m_axi_buser (mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ), .m_axi_bvalid (mi_bvalid[gen_mi_slot*1+:1] ), .m_axi_bready (mi_bready[gen_mi_slot*1+:1] ), .m_axi_arid (), .m_axi_araddr (), .m_axi_arlen (), .m_axi_arsize (), .m_axi_arburst (), .m_axi_arlock (), .m_axi_arcache (), .m_axi_arprot (), .m_axi_arregion (), .m_axi_arqos (), .m_axi_aruser (), .m_axi_arvalid (), .m_axi_arready ({1{1'b0}}), .m_axi_rid (mi_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ), .m_axi_rdata (mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] ), .m_axi_rresp (mi_rresp[gen_mi_slot*2+:2] ), .m_axi_rlast (mi_rlast[gen_mi_slot*1+:1] ), .m_axi_ruser (mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] ), .m_axi_rvalid (mi_rvalid[gen_mi_slot*1+:1] ), .m_axi_rready (mi_rready[gen_mi_slot*1+:1] ) ); end // gen_master_slots (Next gen_mi_slot) // Highest row of *ready_carry contains accumulated OR across all SI-slots, for each MI-slot. assign st_mr_bready = bready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1]; assign st_mr_rready = rready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1]; // Assign MI-side B, R and W channel ports (exclude error handler signals). assign mi_bid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_BID; assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID; assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP; assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER; assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS]; assign mi_rid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_RID; assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST; assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID; assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP; assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER; assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA; assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS]; assign M_AXI_WLAST = mi_wlast[0+:C_NUM_MASTER_SLOTS]; assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS]; assign M_AXI_WUSER = mi_wuser[0+:C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH]; assign M_AXI_WID = (C_AXI_PROTOCOL == P_AXI3) ? mi_wid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] : 0; assign M_AXI_WDATA = mi_wdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH]; assign M_AXI_WSTRB = mi_wstrb[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8]; assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY; axi_crossbar_v2_1_addr_arbiter # // "AA": Addr Arbiter (AW channel) ( .C_FAMILY (C_FAMILY), .C_NUM_M (C_NUM_MASTER_SLOTS+1), .C_NUM_S (C_NUM_SLAVE_SLOTS), .C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_MESG_WIDTH (P_AA_AWMESG_WIDTH), .C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY) ) addr_arbiter_aw ( .ACLK (ACLK), .ARESET (reset), // Vector of SI-side AW command request inputs .S_MESG (tmp_aa_awmesg), .S_TARGET_HOT (st_aa_awtarget_hot), .S_VALID (ss_aa_awvalid), .S_VALID_QUAL (st_aa_awvalid_qual), .S_READY (ss_aa_awready), // Granted AW command output .M_MESG (aa_mi_awmesg), .M_TARGET_HOT (aa_mi_awtarget_hot), // MI-slot targeted by granted command .M_GRANT_ENC (aa_wm_awgrant_enc), // SI-slot index of granted command .M_VALID (aa_sa_awvalid), .M_READY (aa_sa_awready), .ISSUING_LIMIT (mi_awmaxissuing) ); // Broadcast AW transfer payload to all MI-slots assign M_AXI_AWID = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[0+:C_AXI_ID_WIDTH]}}; assign M_AXI_AWADDR = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}}; assign M_AXI_AWLEN = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}}; assign M_AXI_AWSIZE = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}}; assign M_AXI_AWLOCK = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}}; assign M_AXI_AWPROT = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}}; assign M_AXI_AWREGION = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}}; assign M_AXI_AWBURST = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}}; assign M_AXI_AWCACHE = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}}; assign M_AXI_AWQOS = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}}; assign M_AXI_AWUSER = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_AWUSER_WIDTH]}}; axi_crossbar_v2_1_addr_arbiter # // "AA": Addr Arbiter (AR channel) ( .C_FAMILY (C_FAMILY), .C_NUM_M (C_NUM_MASTER_SLOTS+1), .C_NUM_S (C_NUM_SLAVE_SLOTS), .C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_MESG_WIDTH (P_AA_ARMESG_WIDTH), .C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY) ) addr_arbiter_ar ( .ACLK (ACLK), .ARESET (reset), // Vector of SI-side AR command request inputs .S_MESG (tmp_aa_armesg), .S_TARGET_HOT (st_aa_artarget_hot), .S_VALID_QUAL (st_aa_arvalid_qual), .S_VALID (st_aa_arvalid), .S_READY (st_aa_arready), // Granted AR command output .M_MESG (aa_mi_armesg), .M_TARGET_HOT (aa_mi_artarget_hot), // MI-slot targeted by granted command .M_GRANT_ENC (aa_mi_argrant_enc), .M_VALID (aa_mi_arvalid), // SI-slot index of granted command .M_READY (aa_mi_arready), .ISSUING_LIMIT (mi_armaxissuing) ); if (C_DEBUG) begin : gen_debug_trans_seq // DEBUG WRITE TRANSACTION SEQUENCE COUNTER always @(posedge ACLK) begin if (reset) begin debug_aw_trans_seq_i <= 1; end else begin if (aa_sa_awvalid && aa_sa_awready) begin debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1; end end end // DEBUG READ TRANSACTION SEQUENCE COUNTER always @(posedge ACLK) begin if (reset) begin debug_ar_trans_seq_i <= 1; end else begin if (aa_mi_arvalid && aa_mi_arready) begin debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1; end end end end // gen_debug_trans_seq // Broadcast AR transfer payload to all MI-slots assign M_AXI_ARID = {C_NUM_MASTER_SLOTS{aa_mi_armesg[0+:C_AXI_ID_WIDTH]}}; assign M_AXI_ARADDR = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}}; assign M_AXI_ARLEN = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}}; assign M_AXI_ARSIZE = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}}; assign M_AXI_ARLOCK = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}}; assign M_AXI_ARPROT = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}}; assign M_AXI_ARREGION = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}}; assign M_AXI_ARBURST = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}}; assign M_AXI_ARCACHE = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}}; assign M_AXI_ARQOS = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}}; assign M_AXI_ARUSER = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_ARUSER_WIDTH]}}; // AW arbiter command transfer completes upon completion of both M-side AW-channel transfer and W-mux address acceptance (command push). axi_crossbar_v2_1_splitter # // "SA": Splitter for Write Addr Arbiter ( .C_NUM_M (2) ) splitter_aw_mi ( .ACLK (ACLK), .ARESET (reset), .S_VALID (aa_sa_awvalid), .S_READY (aa_sa_awready), .M_VALID ({mi_awvalid_en, sa_wm_awvalid_en}), .M_READY ({mi_awready_mux, sa_wm_awready_mux}) ); assign mi_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{mi_awvalid_en}}; assign mi_awready_mux = |(aa_mi_awtarget_hot & mi_awready); assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS]; // Slot C_NUM_MASTER_SLOTS+1 is the error handler assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY; assign sa_wm_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{sa_wm_awvalid_en}}; assign sa_wm_awready_mux = |(aa_mi_awtarget_hot & sa_wm_awready); assign mi_arvalid = aa_mi_artarget_hot & {C_NUM_MASTER_SLOTS+1{aa_mi_arvalid}}; assign aa_mi_arready = |(aa_mi_artarget_hot & mi_arready); assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS]; // Slot C_NUM_MASTER_SLOTS+1 is the error handler assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY; // MI-slot # C_NUM_MASTER_SLOTS is the error handler if (C_RANGE_CHECK) begin : gen_decerr_slave axi_crossbar_v2_1_decerr_slave # ( .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_RESP (P_DECERR) ) decerr_slave_inst ( .S_AXI_ACLK (ACLK), .S_AXI_ARESET (reset), .S_AXI_AWID (aa_mi_awmesg[0+:C_AXI_ID_WIDTH]), .S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]), .S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]), .S_AXI_WLAST (mi_wlast[C_NUM_MASTER_SLOTS]), .S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]), .S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]), .S_AXI_BID (mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]), .S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]), .S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]), .S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]), .S_AXI_ARID (aa_mi_armesg[0+:C_AXI_ID_WIDTH]), .S_AXI_ARLEN (aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]), .S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]), .S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]), .S_AXI_RID (mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]), .S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]), .S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]), .S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]), .S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]), .S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS]) ); end else begin : gen_no_decerr_slave assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0; assign mi_wready[C_NUM_MASTER_SLOTS] = 1'b0; assign mi_arready[C_NUM_MASTER_SLOTS] = 1'b0; assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0; assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0; assign mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign mi_bresp[C_NUM_MASTER_SLOTS*2+:2] = 0; assign mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0; assign mi_bvalid[C_NUM_MASTER_SLOTS] = 1'b0; assign mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0; assign mi_rresp[C_NUM_MASTER_SLOTS*2+:2] = 0; assign mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0; assign mi_rlast[C_NUM_MASTER_SLOTS] = 1'b0; assign mi_rvalid[C_NUM_MASTER_SLOTS] = 1'b0; end // gen_decerr_slave endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: crossbar.v // // Description: // This module is a M-master to N-slave AXI axi_crossbar_v2_1_crossbar switch. // The interface of this module consists of a vectored slave and master interface // in which all slots are sized and synchronized to the native width and clock // of the interconnect. // The SAMD axi_crossbar_v2_1_crossbar supports only AXI4 and AXI3 protocols. // All width, clock and protocol conversions are done outside this block, as are // any pipeline registers or data FIFOs. // This module contains all arbitration, decoders and channel multiplexing logic. // It also contains the diagnostic registers and control interface. // //----------------------------------------------------------------------------- // // Structure: // crossbar // si_transactor // addr_decoder // comparator_static // mux_enc // axic_srl_fifo // arbiter_resp // splitter // wdata_router // axic_reg_srl_fifo // wdata_mux // axic_reg_srl_fifo // mux_enc // addr_decoder // comparator_static // axic_srl_fifo // axi_register_slice // addr_arbiter // mux_enc // decerr_slave // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_crossbar # ( parameter C_FAMILY = "none", parameter integer C_NUM_SLAVE_SLOTS = 1, parameter integer C_NUM_MASTER_SLOTS = 1, parameter integer C_NUM_ADDR_RANGES = 1, parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_PROTOCOL = 0, parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}}, parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}}, parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}}, parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}}, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE = {C_NUM_SLAVE_SLOTS{1'b1}}, parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ = {C_NUM_SLAVE_SLOTS{1'b1}}, parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE = {C_NUM_MASTER_SLOTS{1'b1}}, parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ = {C_NUM_MASTER_SLOTS{1'b1}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = {C_NUM_SLAVE_SLOTS{32'h00000000}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = {C_NUM_SLAVE_SLOTS{32'h00000001}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = {C_NUM_SLAVE_SLOTS{32'h00000001}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = {C_NUM_MASTER_SLOTS{32'h00000001}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = {C_NUM_MASTER_SLOTS{32'h00000001}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = {C_NUM_SLAVE_SLOTS{32'h00000000}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = {C_NUM_MASTER_SLOTS{32'h00000000}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}}, parameter integer C_RANGE_CHECK = 0, parameter integer C_ADDR_DECODE = 0, parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_W_ISSUE_WIDTH = {C_NUM_MASTER_SLOTS+1{32'h00000000}}, parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_R_ISSUE_WIDTH = {C_NUM_MASTER_SLOTS+1{32'h00000000}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_W_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_R_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}}, parameter integer C_DEBUG = 1 ) ( // Global Signals input wire ACLK, input wire ARESETN, // Slave Interface Write Address Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_AWLEN, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWSIZE, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWBURST, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWLOCK, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWCACHE, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWPROT, // input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWREGION, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWQOS, input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWREADY, // Slave Interface Write Data Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_WID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WLAST, input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WREADY, // Slave Interface Write Response Ports output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_BID, output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_BRESP, output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BVALID, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BREADY, // Slave Interface Read Address Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_ARID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_ARLEN, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARSIZE, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARBURST, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARLOCK, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARCACHE, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARPROT, // input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARREGION, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARQOS, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARREADY, // Slave Interface Read Data Ports output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_RID, output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_RRESP, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RLAST, output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RVALID, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RREADY, // Master Interface Write Address Port output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_AWLEN, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWSIZE, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWBURST, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWLOCK, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWCACHE, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWPROT, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWREGION, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWQOS, output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWREADY, // Master Interface Write Data Ports output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_WID, output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WLAST, output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WREADY, // Master Interface Write Response Ports input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_BID, input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_BRESP, input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BVALID, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BREADY, // Master Interface Read Address Port output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_ARID, output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_ARLEN, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARSIZE, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARBURST, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARLOCK, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARCACHE, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARPROT, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARREGION, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARQOS, output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARREADY, // Master Interface Read Data Ports input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_RID, input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_RRESP, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RLAST, input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RVALID, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RREADY ); localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; localparam integer P_WRITE = 0; localparam integer P_READ = 1; localparam integer P_NUM_MASTER_SLOTS_LOG = f_ceil_log2(C_NUM_MASTER_SLOTS); localparam integer P_NUM_SLAVE_SLOTS_LOG = f_ceil_log2((C_NUM_SLAVE_SLOTS>1) ? C_NUM_SLAVE_SLOTS : 2); localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1; localparam integer P_ST_AWMESG_WIDTH = 2+4+4 + C_AXI_AWUSER_WIDTH; localparam integer P_AA_AWMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_AWMESG_WIDTH; localparam integer P_ST_ARMESG_WIDTH = 2+4+4 + C_AXI_ARUSER_WIDTH; localparam integer P_AA_ARMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_ARMESG_WIDTH; localparam integer P_ST_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH; localparam integer P_ST_RMESG_WIDTH = 2 + C_AXI_RUSER_WIDTH + C_AXI_DATA_WIDTH; localparam integer P_WR_WMESG_WIDTH = C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH; localparam [31:0] P_BYPASS = 32'h00000000; localparam [31:0] P_FWD_REV = 32'h00000001; localparam [31:0] P_SIMPLE = 32'h00000007; localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_READ = {1'b1, C_M_AXI_SUPPORTS_READ[0+:C_NUM_MASTER_SLOTS]}; localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_WRITE = {1'b1, C_M_AXI_SUPPORTS_WRITE[0+:C_NUM_MASTER_SLOTS]}; localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_WRITE_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]}; localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_READ_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]}; localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_WRITE_CONNECTIVITY = f_si_write_connectivity(0); localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_READ_CONNECTIVITY = f_si_read_connectivity(0); localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_ISSUING = {32'h00000001, C_M_AXI_READ_ISSUING[0+:C_NUM_MASTER_SLOTS*32]}; localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_ISSUING = {32'h00000001, C_M_AXI_WRITE_ISSUING[0+:C_NUM_MASTER_SLOTS*32]}; localparam P_DECERR = 2'b11; //--------------------------------------------------------------------------- // Functions //--------------------------------------------------------------------------- // Ceiling of log2(x) function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2**acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value // only for end-point SI-slots function [C_AXI_ID_WIDTH-1:0] f_extend_ID ( input [C_AXI_ID_WIDTH-1:0] s_id, input integer slot ); begin f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH])); end endfunction // Write connectivity array transposed function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_write_connectivity ( input integer null_arg ); integer si_slot; integer mi_slot; reg [C_NUM_SLAVE_SLOTS*32-1:0] result; begin result = {C_NUM_SLAVE_SLOTS*32{1'b1}}; for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin result[si_slot*32+mi_slot] = C_M_AXI_WRITE_CONNECTIVITY[mi_slot*32+si_slot]; end end f_si_write_connectivity = result; end endfunction // Read connectivity array transposed function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_read_connectivity ( input integer null_arg ); integer si_slot; integer mi_slot; reg [C_NUM_SLAVE_SLOTS*32-1:0] result; begin result = {C_NUM_SLAVE_SLOTS*32{1'b1}}; for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin result[si_slot*32+mi_slot] = C_M_AXI_READ_CONNECTIVITY[mi_slot*32+si_slot]; end end f_si_read_connectivity = result; end endfunction genvar gen_si_slot; genvar gen_mi_slot; wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0] si_st_awmesg ; wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0] st_tmp_awmesg ; wire [C_NUM_SLAVE_SLOTS*P_AA_AWMESG_WIDTH-1:0] tmp_aa_awmesg ; wire [P_AA_AWMESG_WIDTH-1:0] aa_mi_awmesg ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] st_aa_awid ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] st_aa_awaddr ; wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_awlen ; wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_awsize ; wire [C_NUM_SLAVE_SLOTS*2-1:0] st_aa_awlock ; wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_awprot ; wire [C_NUM_SLAVE_SLOTS*4-1:0] st_aa_awregion ; wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_awerror ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_aa_awtarget_hot ; wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0] st_aa_awtarget_enc ; wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0] aa_wm_awgrant_enc ; wire [(C_NUM_MASTER_SLOTS+1)-1:0] aa_mi_awtarget_hot ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_awvalid_qual ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_ss_awvalid ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_ss_awready ; wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_wr_awvalid ; wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_wr_awready ; wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_aa_awvalid ; wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_aa_awready ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] sa_wm_awvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] sa_wm_awready ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awready ; wire aa_sa_awvalid ; wire aa_sa_awready ; wire aa_mi_arready ; wire mi_awvalid_en ; wire sa_wm_awvalid_en ; wire sa_wm_awready_mux ; wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0] si_st_armesg ; wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0] st_tmp_armesg ; wire [C_NUM_SLAVE_SLOTS*P_AA_ARMESG_WIDTH-1:0] tmp_aa_armesg ; wire [P_AA_ARMESG_WIDTH-1:0] aa_mi_armesg ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] st_aa_arid ; wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] st_aa_araddr ; wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_arlen ; wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_arsize ; wire [C_NUM_SLAVE_SLOTS*2-1:0] st_aa_arlock ; wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_arprot ; wire [C_NUM_SLAVE_SLOTS*4-1:0] st_aa_arregion ; wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_arerror ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_aa_artarget_hot ; wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0] st_aa_artarget_enc ; wire [(C_NUM_MASTER_SLOTS+1)-1:0] aa_mi_artarget_hot ; wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0] aa_mi_argrant_enc ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arvalid_qual ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arvalid ; wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arready ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_arvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_arready ; wire aa_mi_arvalid ; wire mi_awready_mux ; wire [C_NUM_SLAVE_SLOTS*P_ST_BMESG_WIDTH-1:0] st_si_bmesg ; wire [(C_NUM_MASTER_SLOTS+1)*P_ST_BMESG_WIDTH-1:0] st_mr_bmesg ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] st_mr_bid ; wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] st_mr_bresp ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0] st_mr_buser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_bvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_bready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_bready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_bid_target ; wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_mr_bid_target ; wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0] debug_bid_target_i ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] bid_match ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_bid ; wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] mi_bresp ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0] mi_buser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_bvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_bready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] bready_carry ; wire [C_NUM_SLAVE_SLOTS*P_ST_RMESG_WIDTH-1:0] st_si_rmesg ; wire [(C_NUM_MASTER_SLOTS+1)*P_ST_RMESG_WIDTH-1:0] st_mr_rmesg ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] st_mr_rid ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] st_mr_rdata ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0] st_mr_ruser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rlast ; wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] st_mr_rresp ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_rready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_rid_target ; wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_mr_rid_target ; wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0] debug_rid_target_i ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] rid_match ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_rid ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] mi_rdata ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0] mi_ruser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rlast ; wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] mi_rresp ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rready ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] rready_carry ; wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0] si_wr_wmesg ; wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0] wr_wm_wmesg ; wire [C_NUM_SLAVE_SLOTS*1-1:0] wr_wm_wlast ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] wr_tmp_wvalid ; wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] wr_tmp_wready ; wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_wm_wvalid ; wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_wm_wready ; wire [(C_NUM_MASTER_SLOTS+1)*P_WR_WMESG_WIDTH-1:0] wm_mr_wmesg ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] wm_mr_wdata ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0] wm_mr_wstrb ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] wm_mr_wid ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0] wm_mr_wuser ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wlast ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wready ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] mi_wdata ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0] mi_wstrb ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0] mi_wuser ; wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_wid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wlast ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wvalid ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wready ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] w_cmd_push ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] w_cmd_pop ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] r_cmd_push ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] r_cmd_pop ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awmaxissuing ; wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_armaxissuing ; reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] w_issuing_cnt ; reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] r_issuing_cnt ; reg [8-1:0] debug_aw_trans_seq_i ; reg [8-1:0] debug_ar_trans_seq_i ; wire [(C_NUM_MASTER_SLOTS+1)*8-1:0] debug_w_trans_seq_i ; reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] debug_w_beat_cnt_i ; reg aresetn_d = 1'b0; // Reset delay register always @(posedge ACLK) begin if (~ARESETN) begin aresetn_d <= 1'b0; end else begin aresetn_d <= ARESETN; end end wire reset; assign reset = ~aresetn_d; generate for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_slave_slots if (C_S_AXI_SUPPORTS_READ[gen_si_slot]) begin : gen_si_read axi_crossbar_v2_1_si_transactor # // "ST": SI Transactor (read channel) ( .C_FAMILY (C_FAMILY), .C_SI (gen_si_slot), .C_DIR (P_READ), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_NUM_M (C_NUM_MASTER_SLOTS), .C_NUM_M_LOG (P_NUM_MASTER_SLOTS_LOG), .C_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE[gen_si_slot*32+:32]), .C_ACCEPTANCE_LOG (C_R_ACCEPT_WIDTH[gen_si_slot*32+:32]), .C_ID_WIDTH (C_AXI_ID_WIDTH), .C_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]), .C_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AMESG_WIDTH (P_ST_ARMESG_WIDTH), .C_RMESG_WIDTH (P_ST_RMESG_WIDTH), .C_BASE_ID (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]), .C_HIGH_ID (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]), .C_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]), .C_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_HIGH_ADDR (C_M_AXI_HIGH_ADDR), .C_TARGET_QUAL (P_S_AXI_READ_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_RANGE_CHECK (C_RANGE_CHECK), .C_ADDR_DECODE (C_ADDR_DECODE), .C_ERR_MODE (C_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) si_transactor_ar ( .ACLK (ACLK), .ARESET (reset), .S_AID (f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)), .S_AADDR (S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]), .S_ALEN (S_AXI_ARLEN[gen_si_slot*8+:8]), .S_ASIZE (S_AXI_ARSIZE[gen_si_slot*3+:3]), .S_ABURST (S_AXI_ARBURST[gen_si_slot*2+:2]), .S_ALOCK (S_AXI_ARLOCK[gen_si_slot*2+:2]), .S_APROT (S_AXI_ARPROT[gen_si_slot*3+:3]), // .S_AREGION (S_AXI_ARREGION[gen_si_slot*4+:4]), .S_AMESG (si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]), .S_AVALID (S_AXI_ARVALID[gen_si_slot]), .S_AREADY (S_AXI_ARREADY[gen_si_slot]), .M_AID (st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .M_AADDR (st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]), .M_ALEN (st_aa_arlen[gen_si_slot*8+:8]), .M_ASIZE (st_aa_arsize[gen_si_slot*3+:3]), .M_ALOCK (st_aa_arlock[gen_si_slot*2+:2]), .M_APROT (st_aa_arprot[gen_si_slot*3+:3]), .M_AREGION (st_aa_arregion[gen_si_slot*4+:4]), .M_AMESG (st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]), .M_ATARGET_HOT (st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_ATARGET_ENC (st_aa_artarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]), .M_AERROR (st_aa_arerror[gen_si_slot*8+:8]), .M_AVALID_QUAL (st_aa_arvalid_qual[gen_si_slot]), .M_AVALID (st_aa_arvalid[gen_si_slot]), .M_AREADY (st_aa_arready[gen_si_slot]), .S_RID (S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .S_RMESG (st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH]), .S_RLAST (S_AXI_RLAST[gen_si_slot]), .S_RVALID (S_AXI_RVALID[gen_si_slot]), .S_RREADY (S_AXI_RREADY[gen_si_slot]), .M_RID (st_mr_rid), .M_RLAST (st_mr_rlast), .M_RMESG (st_mr_rmesg), .M_RVALID (st_mr_rvalid), .M_RREADY (st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_RTARGET (st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .DEBUG_A_TRANS_SEQ (C_DEBUG ? debug_ar_trans_seq_i : 8'h0) ); assign si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH] = { S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH], S_AXI_ARQOS[gen_si_slot*4+:4], S_AXI_ARCACHE[gen_si_slot*4+:4], S_AXI_ARBURST[gen_si_slot*2+:2] }; assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = { st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH], st_aa_arregion[gen_si_slot*4+:4], st_aa_arprot[gen_si_slot*3+:3], st_aa_arlock[gen_si_slot*2+:2], st_aa_arsize[gen_si_slot*3+:3], st_aa_arlen[gen_si_slot*8+:8], st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH], st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] }; assign S_AXI_RRESP[gen_si_slot*2+:2] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:2]; assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2 +: C_AXI_RUSER_WIDTH]; assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2+C_AXI_RUSER_WIDTH +: C_AXI_DATA_WIDTH]; end else begin : gen_no_si_read assign S_AXI_ARREADY[gen_si_slot] = 1'b0; assign st_aa_arvalid[gen_si_slot] = 1'b0; assign st_aa_arvalid_qual[gen_si_slot] = 1'b1; assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = 0; assign S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign S_AXI_RRESP[gen_si_slot*2+:2] = 0; assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0; assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0; assign S_AXI_RVALID[gen_si_slot] = 1'b0; assign S_AXI_RLAST[gen_si_slot] = 1'b0; assign st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; assign st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; end // gen_si_read if (C_S_AXI_SUPPORTS_WRITE[gen_si_slot]) begin : gen_si_write axi_crossbar_v2_1_si_transactor # // "ST": SI Transactor (write channel) ( .C_FAMILY (C_FAMILY), .C_SI (gen_si_slot), .C_DIR (P_WRITE), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_NUM_M (C_NUM_MASTER_SLOTS), .C_NUM_M_LOG (P_NUM_MASTER_SLOTS_LOG), .C_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE[gen_si_slot*32+:32]), .C_ACCEPTANCE_LOG (C_W_ACCEPT_WIDTH[gen_si_slot*32+:32]), .C_ID_WIDTH (C_AXI_ID_WIDTH), .C_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]), .C_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AMESG_WIDTH (P_ST_AWMESG_WIDTH), .C_RMESG_WIDTH (P_ST_BMESG_WIDTH), .C_BASE_ID (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]), .C_HIGH_ID (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]), .C_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]), .C_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_HIGH_ADDR (C_M_AXI_HIGH_ADDR), .C_TARGET_QUAL (P_S_AXI_WRITE_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_RANGE_CHECK (C_RANGE_CHECK), .C_ADDR_DECODE (C_ADDR_DECODE), .C_ERR_MODE (C_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) si_transactor_aw ( .ACLK (ACLK), .ARESET (reset), .S_AID (f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)), .S_AADDR (S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]), .S_ALEN (S_AXI_AWLEN[gen_si_slot*8+:8]), .S_ASIZE (S_AXI_AWSIZE[gen_si_slot*3+:3]), .S_ABURST (S_AXI_AWBURST[gen_si_slot*2+:2]), .S_ALOCK (S_AXI_AWLOCK[gen_si_slot*2+:2]), .S_APROT (S_AXI_AWPROT[gen_si_slot*3+:3]), // .S_AREGION (S_AXI_AWREGION[gen_si_slot*4+:4]), .S_AMESG (si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]), .S_AVALID (S_AXI_AWVALID[gen_si_slot]), .S_AREADY (S_AXI_AWREADY[gen_si_slot]), .M_AID (st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .M_AADDR (st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]), .M_ALEN (st_aa_awlen[gen_si_slot*8+:8]), .M_ASIZE (st_aa_awsize[gen_si_slot*3+:3]), .M_ALOCK (st_aa_awlock[gen_si_slot*2+:2]), .M_APROT (st_aa_awprot[gen_si_slot*3+:3]), .M_AREGION (st_aa_awregion[gen_si_slot*4+:4]), .M_AMESG (st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]), .M_ATARGET_HOT (st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_ATARGET_ENC (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]), .M_AERROR (st_aa_awerror[gen_si_slot*8+:8]), .M_AVALID_QUAL (st_aa_awvalid_qual[gen_si_slot]), .M_AVALID (st_ss_awvalid[gen_si_slot]), .M_AREADY (st_ss_awready[gen_si_slot]), .S_RID (S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .S_RMESG (st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH]), .S_RLAST (), .S_RVALID (S_AXI_BVALID[gen_si_slot]), .S_RREADY (S_AXI_BREADY[gen_si_slot]), .M_RID (st_mr_bid), .M_RLAST ({(C_NUM_MASTER_SLOTS+1){1'b1}}), .M_RMESG (st_mr_bmesg), .M_RVALID (st_mr_bvalid), .M_RREADY (st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_RTARGET (st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .DEBUG_A_TRANS_SEQ (C_DEBUG ? debug_aw_trans_seq_i : 8'h0) ); // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order. assign si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH] = { S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH], S_AXI_AWQOS[gen_si_slot*4+:4], S_AXI_AWCACHE[gen_si_slot*4+:4], S_AXI_AWBURST[gen_si_slot*2+:2] }; assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = { st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH], st_aa_awregion[gen_si_slot*4+:4], st_aa_awprot[gen_si_slot*3+:3], st_aa_awlock[gen_si_slot*2+:2], st_aa_awsize[gen_si_slot*3+:3], st_aa_awlen[gen_si_slot*8+:8], st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH], st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] }; assign S_AXI_BRESP[gen_si_slot*2+:2] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:2]; assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+2 +: C_AXI_BUSER_WIDTH]; // AW SI-transactor transfer completes upon completion of both W-router address acceptance (command push) and AW arbitration axi_crossbar_v2_1_splitter # // "SS": Splitter from SI-Transactor (write channel) ( .C_NUM_M (2) ) splitter_aw_si ( .ACLK (ACLK), .ARESET (reset), .S_VALID (st_ss_awvalid[gen_si_slot]), .S_READY (st_ss_awready[gen_si_slot]), .M_VALID ({ss_wr_awvalid[gen_si_slot], ss_aa_awvalid[gen_si_slot]}), .M_READY ({ss_wr_awready[gen_si_slot], ss_aa_awready[gen_si_slot]}) ); axi_crossbar_v2_1_wdata_router # // "WR": Write data Router ( .C_FAMILY (C_FAMILY), .C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS+1), .C_SELECT_WIDTH (P_NUM_MASTER_SLOTS_LOG+1), .C_WMESG_WIDTH (P_WR_WMESG_WIDTH), .C_FIFO_DEPTH_LOG (C_W_ACCEPT_WIDTH[gen_si_slot*32+:6]) ) wdata_router_w ( .ACLK (ACLK), .ARESET (reset), // Write transfer input from the current SI-slot .S_WMESG (si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]), .S_WLAST (S_AXI_WLAST[gen_si_slot]), .S_WVALID (S_AXI_WVALID[gen_si_slot]), .S_WREADY (S_AXI_WREADY[gen_si_slot]), // Vector of write transfer outputs to each MI-slot's W-mux .M_WMESG (wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH]), .M_WLAST (wr_wm_wlast[gen_si_slot]), .M_WVALID (wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), .M_WREADY (wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]), // AW command push from local SI-slot .S_ASELECT (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]), // Target MI-slot .S_AVALID (ss_wr_awvalid[gen_si_slot]), .S_AREADY (ss_wr_awready[gen_si_slot]) ); assign si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH] = { ((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0), S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH], S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8], S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] }; end else begin : gen_no_si_write assign S_AXI_AWREADY[gen_si_slot] = 1'b0; assign ss_aa_awvalid[gen_si_slot] = 1'b0; assign st_aa_awvalid_qual[gen_si_slot] = 1'b1; assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = 0; assign S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign S_AXI_BRESP[gen_si_slot*2+:2] = 0; assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0; assign S_AXI_BVALID[gen_si_slot] = 1'b0; assign st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; assign S_AXI_WREADY[gen_si_slot] = 1'b0; assign wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH] = 0; assign wr_wm_wlast[gen_si_slot] = 1'b0; assign wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; assign st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0; end // gen_si_write end // gen_slave_slots for (gen_mi_slot=0; gen_mi_slot<C_NUM_MASTER_SLOTS+1; gen_mi_slot=gen_mi_slot+1) begin : gen_master_slots if (P_M_AXI_SUPPORTS_READ[gen_mi_slot]) begin : gen_mi_read if (C_NUM_SLAVE_SLOTS>1) begin : gen_rid_decoder axi_crossbar_v2_1_addr_decoder # ( .C_FAMILY (C_FAMILY), .C_NUM_TARGETS (C_NUM_SLAVE_SLOTS), .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_NUM_RANGES (1), .C_ADDR_WIDTH (C_AXI_ID_WIDTH), .C_TARGET_ENC (C_DEBUG), .C_TARGET_HOT (1), .C_REGION_ENC (0), .C_BASE_ADDR (C_S_AXI_BASE_ID), .C_HIGH_ADDR (C_S_AXI_HIGH_ID), .C_TARGET_QUAL (P_M_AXI_READ_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]), .C_RESOLUTION (0) ) rid_decoder_inst ( .ADDR (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .TARGET_HOT (tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), .TARGET_ENC (debug_rid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]), .MATCH (rid_match[gen_mi_slot]), .REGION () ); end else begin : gen_no_rid_decoder assign tmp_mr_rid_target[gen_mi_slot] = 1'b1; // All response transfers route to solo SI-slot. assign rid_match[gen_mi_slot] = 1'b1; end assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = { st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH], st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH], st_mr_rresp[gen_mi_slot*2+:2] }; end else begin : gen_no_mi_read assign tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0; assign rid_match[gen_mi_slot] = 1'b0; assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = 0; end // gen_mi_read if (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]) begin : gen_mi_write if (C_NUM_SLAVE_SLOTS>1) begin : gen_bid_decoder axi_crossbar_v2_1_addr_decoder # ( .C_FAMILY (C_FAMILY), .C_NUM_TARGETS (C_NUM_SLAVE_SLOTS), .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_NUM_RANGES (1), .C_ADDR_WIDTH (C_AXI_ID_WIDTH), .C_TARGET_ENC (C_DEBUG), .C_TARGET_HOT (1), .C_REGION_ENC (0), .C_BASE_ADDR (C_S_AXI_BASE_ID), .C_HIGH_ADDR (C_S_AXI_HIGH_ID), .C_TARGET_QUAL (P_M_AXI_WRITE_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]), .C_RESOLUTION (0) ) bid_decoder_inst ( .ADDR (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .TARGET_HOT (tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), .TARGET_ENC (debug_bid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]), .MATCH (bid_match[gen_mi_slot]), .REGION () ); end else begin : gen_no_bid_decoder assign tmp_mr_bid_target[gen_mi_slot] = 1'b1; // All response transfers route to solo SI-slot. assign bid_match[gen_mi_slot] = 1'b1; end axi_crossbar_v2_1_wdata_mux # // "WM": Write data Mux, per MI-slot (incl error-handler) ( .C_FAMILY (C_FAMILY), .C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS), .C_SELECT_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_WMESG_WIDTH (P_WR_WMESG_WIDTH), .C_FIFO_DEPTH_LOG (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]) ) wdata_mux_w ( .ACLK (ACLK), .ARESET (reset), // Vector of write transfer inputs from each SI-slot's W-router .S_WMESG (wr_wm_wmesg), .S_WLAST (wr_wm_wlast), .S_WVALID (tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), .S_WREADY (tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]), // Write transfer output to the current MI-slot .M_WMESG (wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]), .M_WLAST (wm_mr_wlast[gen_mi_slot]), .M_WVALID (wm_mr_wvalid[gen_mi_slot]), .M_WREADY (wm_mr_wready[gen_mi_slot]), // AW command push from AW arbiter output .S_ASELECT (aa_wm_awgrant_enc), // SI-slot selected by arbiter .S_AVALID (sa_wm_awvalid[gen_mi_slot]), .S_AREADY (sa_wm_awready[gen_mi_slot]) ); if (C_DEBUG) begin : gen_debug_w // DEBUG WRITE BEAT COUNTER always @(posedge ACLK) begin if (reset) begin debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0; end else begin if (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot]) begin if (mi_wlast[gen_mi_slot]) begin debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0; end else begin debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= debug_w_beat_cnt_i[gen_mi_slot*8+:8] + 1; end end end end // clocked process // DEBUG W-CHANNEL TRANSACTION SEQUENCE QUEUE axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]), .C_USE_FULL (0) ) debug_w_seq_fifo ( .ACLK (ACLK), .ARESET (reset), .S_MESG (debug_aw_trans_seq_i), .S_VALID (sa_wm_awvalid[gen_mi_slot]), .S_READY (), .M_MESG (debug_w_trans_seq_i[gen_mi_slot*8+:8]), .M_VALID (), .M_READY (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot] & mi_wlast[gen_mi_slot]) ); end // gen_debug_w assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH +: C_AXI_DATA_WIDTH]; assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8]; assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH]; assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+(C_AXI_DATA_WIDTH/8)+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH]; assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = { st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH], st_mr_bresp[gen_mi_slot*2+:2] }; end else begin : gen_no_mi_write assign tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0; assign bid_match[gen_mi_slot] = 1'b0; assign wm_mr_wvalid[gen_mi_slot] = 0; assign wm_mr_wlast[gen_mi_slot] = 0; assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0; assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = 0; assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = 0; assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = 0; assign tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0; assign sa_wm_awready[gen_mi_slot] = 0; end // gen_mi_write for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_trans_si // Transpose handshakes from W-router (SxM) to W-mux (MxS). assign tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot] = wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; assign wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot]; // Transpose response enables from ID decoders (MxS) to si_transactors (SxM). assign st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot]; assign st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot]; end // gen_trans_si assign bready_carry[gen_mi_slot] = st_tmp_bready[gen_mi_slot]; assign rready_carry[gen_mi_slot] = st_tmp_rready[gen_mi_slot]; for (gen_si_slot=1; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_resp_carry_si assign bready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = // Generate M_BREADY if ... bready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] | // For any SI-slot (OR carry-chain across all SI-slots), ... st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; // The write SI transactor indicates BREADY for that MI-slot. assign rready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = // Generate M_RREADY if ... rready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] | // For any SI-slot (OR carry-chain across all SI-slots), ... st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; // The write SI transactor indicates RREADY for that MI-slot. end // gen_resp_carry_si assign w_cmd_push[gen_mi_slot] = mi_awvalid[gen_mi_slot] && mi_awready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]; assign r_cmd_push[gen_mi_slot] = mi_arvalid[gen_mi_slot] && mi_arready[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot]; assign w_cmd_pop[gen_mi_slot] = st_mr_bvalid[gen_mi_slot] && st_mr_bready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]; assign r_cmd_pop[gen_mi_slot] = st_mr_rvalid[gen_mi_slot] && st_mr_rready[gen_mi_slot] && st_mr_rlast[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot]; // Disqualify arbitration of SI-slot if targeted MI-slot has reached its issuing limit. assign mi_awmaxissuing[gen_mi_slot] = (w_issuing_cnt[gen_mi_slot*8 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] == P_M_AXI_WRITE_ISSUING[gen_mi_slot*32 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~w_cmd_pop[gen_mi_slot]; assign mi_armaxissuing[gen_mi_slot] = (r_issuing_cnt[gen_mi_slot*8 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] == P_M_AXI_READ_ISSUING[gen_mi_slot*32 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~r_cmd_pop[gen_mi_slot]; always @(posedge ACLK) begin if (reset) begin w_issuing_cnt[gen_mi_slot*8+:8] <= 0; // Some high-order bits remain constant 0 r_issuing_cnt[gen_mi_slot*8+:8] <= 0; // Some high-order bits remain constant 0 end else begin if (w_cmd_push[gen_mi_slot] && ~w_cmd_pop[gen_mi_slot]) begin w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1; end else if (w_cmd_pop[gen_mi_slot] && ~w_cmd_push[gen_mi_slot] && (|w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1; end if (r_cmd_push[gen_mi_slot] && ~r_cmd_pop[gen_mi_slot]) begin r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1; end else if (r_cmd_pop[gen_mi_slot] && ~r_cmd_push[gen_mi_slot] && (|r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1; end end end // Clocked process // Reg-slice must break combinatorial path from M_BID and M_RID inputs to M_BREADY and M_RREADY outputs. // (See m_rready_i and m_resp_en combinatorial assignments in si_transactor.) // Reg-slice incurs +1 latency, but no bubble-cycles. axi_register_slice_v2_1_axi_register_slice # // "MR": MI-side R/B-channel Reg-slice, per MI-slot (pass-through if only 1 SI-slot configured) ( .C_FAMILY (C_FAMILY), .C_AXI_PROTOCOL ((C_AXI_PROTOCOL == P_AXI3) ? P_AXI3 : P_AXI4), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_ADDR_WIDTH (1), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AWUSER_WIDTH (1), .C_AXI_ARUSER_WIDTH (1), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_REG_CONFIG_AW (P_BYPASS), .C_REG_CONFIG_AR (P_BYPASS), .C_REG_CONFIG_W (P_BYPASS), .C_REG_CONFIG_R (P_M_AXI_SUPPORTS_READ[gen_mi_slot] ? P_FWD_REV : P_BYPASS), .C_REG_CONFIG_B (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot] ? P_SIMPLE : P_BYPASS) ) reg_slice_mi ( .aresetn (ARESETN), .aclk (ACLK), .s_axi_awid ({C_AXI_ID_WIDTH{1'b0}}), .s_axi_awaddr ({1{1'b0}}), .s_axi_awlen ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}), .s_axi_awsize ({3{1'b0}}), .s_axi_awburst ({2{1'b0}}), .s_axi_awlock ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}), .s_axi_awcache ({4{1'b0}}), .s_axi_awprot ({3{1'b0}}), .s_axi_awregion ({4{1'b0}}), .s_axi_awqos ({4{1'b0}}), .s_axi_awuser ({1{1'b0}}), .s_axi_awvalid ({1{1'b0}}), .s_axi_awready (), .s_axi_wid (wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .s_axi_wdata (wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]), .s_axi_wstrb (wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]), .s_axi_wlast (wm_mr_wlast[gen_mi_slot]), .s_axi_wuser (wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]), .s_axi_wvalid (wm_mr_wvalid[gen_mi_slot]), .s_axi_wready (wm_mr_wready[gen_mi_slot]), .s_axi_bid (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ), .s_axi_bresp (st_mr_bresp[gen_mi_slot*2+:2] ), .s_axi_buser (st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ), .s_axi_bvalid (st_mr_bvalid[gen_mi_slot*1+:1] ), .s_axi_bready (st_mr_bready[gen_mi_slot*1+:1] ), .s_axi_arid ({C_AXI_ID_WIDTH{1'b0}}), .s_axi_araddr ({1{1'b0}}), .s_axi_arlen ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}), .s_axi_arsize ({3{1'b0}}), .s_axi_arburst ({2{1'b0}}), .s_axi_arlock ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}), .s_axi_arcache ({4{1'b0}}), .s_axi_arprot ({3{1'b0}}), .s_axi_arregion ({4{1'b0}}), .s_axi_arqos ({4{1'b0}}), .s_axi_aruser ({1{1'b0}}), .s_axi_arvalid ({1{1'b0}}), .s_axi_arready (), .s_axi_rid (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ), .s_axi_rdata (st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] ), .s_axi_rresp (st_mr_rresp[gen_mi_slot*2+:2] ), .s_axi_rlast (st_mr_rlast[gen_mi_slot*1+:1] ), .s_axi_ruser (st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] ), .s_axi_rvalid (st_mr_rvalid[gen_mi_slot*1+:1] ), .s_axi_rready (st_mr_rready[gen_mi_slot*1+:1] ), .m_axi_awid (), .m_axi_awaddr (), .m_axi_awlen (), .m_axi_awsize (), .m_axi_awburst (), .m_axi_awlock (), .m_axi_awcache (), .m_axi_awprot (), .m_axi_awregion (), .m_axi_awqos (), .m_axi_awuser (), .m_axi_awvalid (), .m_axi_awready ({1{1'b0}}), .m_axi_wid (mi_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .m_axi_wdata (mi_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]), .m_axi_wstrb (mi_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]), .m_axi_wlast (mi_wlast[gen_mi_slot]), .m_axi_wuser (mi_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]), .m_axi_wvalid (mi_wvalid[gen_mi_slot]), .m_axi_wready (mi_wready[gen_mi_slot]), .m_axi_bid (mi_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ), .m_axi_bresp (mi_bresp[gen_mi_slot*2+:2] ), .m_axi_buser (mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ), .m_axi_bvalid (mi_bvalid[gen_mi_slot*1+:1] ), .m_axi_bready (mi_bready[gen_mi_slot*1+:1] ), .m_axi_arid (), .m_axi_araddr (), .m_axi_arlen (), .m_axi_arsize (), .m_axi_arburst (), .m_axi_arlock (), .m_axi_arcache (), .m_axi_arprot (), .m_axi_arregion (), .m_axi_arqos (), .m_axi_aruser (), .m_axi_arvalid (), .m_axi_arready ({1{1'b0}}), .m_axi_rid (mi_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ), .m_axi_rdata (mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] ), .m_axi_rresp (mi_rresp[gen_mi_slot*2+:2] ), .m_axi_rlast (mi_rlast[gen_mi_slot*1+:1] ), .m_axi_ruser (mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] ), .m_axi_rvalid (mi_rvalid[gen_mi_slot*1+:1] ), .m_axi_rready (mi_rready[gen_mi_slot*1+:1] ) ); end // gen_master_slots (Next gen_mi_slot) // Highest row of *ready_carry contains accumulated OR across all SI-slots, for each MI-slot. assign st_mr_bready = bready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1]; assign st_mr_rready = rready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1]; // Assign MI-side B, R and W channel ports (exclude error handler signals). assign mi_bid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_BID; assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID; assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP; assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER; assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS]; assign mi_rid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_RID; assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST; assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID; assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP; assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER; assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA; assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS]; assign M_AXI_WLAST = mi_wlast[0+:C_NUM_MASTER_SLOTS]; assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS]; assign M_AXI_WUSER = mi_wuser[0+:C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH]; assign M_AXI_WID = (C_AXI_PROTOCOL == P_AXI3) ? mi_wid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] : 0; assign M_AXI_WDATA = mi_wdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH]; assign M_AXI_WSTRB = mi_wstrb[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8]; assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY; axi_crossbar_v2_1_addr_arbiter # // "AA": Addr Arbiter (AW channel) ( .C_FAMILY (C_FAMILY), .C_NUM_M (C_NUM_MASTER_SLOTS+1), .C_NUM_S (C_NUM_SLAVE_SLOTS), .C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_MESG_WIDTH (P_AA_AWMESG_WIDTH), .C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY) ) addr_arbiter_aw ( .ACLK (ACLK), .ARESET (reset), // Vector of SI-side AW command request inputs .S_MESG (tmp_aa_awmesg), .S_TARGET_HOT (st_aa_awtarget_hot), .S_VALID (ss_aa_awvalid), .S_VALID_QUAL (st_aa_awvalid_qual), .S_READY (ss_aa_awready), // Granted AW command output .M_MESG (aa_mi_awmesg), .M_TARGET_HOT (aa_mi_awtarget_hot), // MI-slot targeted by granted command .M_GRANT_ENC (aa_wm_awgrant_enc), // SI-slot index of granted command .M_VALID (aa_sa_awvalid), .M_READY (aa_sa_awready), .ISSUING_LIMIT (mi_awmaxissuing) ); // Broadcast AW transfer payload to all MI-slots assign M_AXI_AWID = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[0+:C_AXI_ID_WIDTH]}}; assign M_AXI_AWADDR = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}}; assign M_AXI_AWLEN = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}}; assign M_AXI_AWSIZE = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}}; assign M_AXI_AWLOCK = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}}; assign M_AXI_AWPROT = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}}; assign M_AXI_AWREGION = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}}; assign M_AXI_AWBURST = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}}; assign M_AXI_AWCACHE = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}}; assign M_AXI_AWQOS = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}}; assign M_AXI_AWUSER = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_AWUSER_WIDTH]}}; axi_crossbar_v2_1_addr_arbiter # // "AA": Addr Arbiter (AR channel) ( .C_FAMILY (C_FAMILY), .C_NUM_M (C_NUM_MASTER_SLOTS+1), .C_NUM_S (C_NUM_SLAVE_SLOTS), .C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_MESG_WIDTH (P_AA_ARMESG_WIDTH), .C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY) ) addr_arbiter_ar ( .ACLK (ACLK), .ARESET (reset), // Vector of SI-side AR command request inputs .S_MESG (tmp_aa_armesg), .S_TARGET_HOT (st_aa_artarget_hot), .S_VALID_QUAL (st_aa_arvalid_qual), .S_VALID (st_aa_arvalid), .S_READY (st_aa_arready), // Granted AR command output .M_MESG (aa_mi_armesg), .M_TARGET_HOT (aa_mi_artarget_hot), // MI-slot targeted by granted command .M_GRANT_ENC (aa_mi_argrant_enc), .M_VALID (aa_mi_arvalid), // SI-slot index of granted command .M_READY (aa_mi_arready), .ISSUING_LIMIT (mi_armaxissuing) ); if (C_DEBUG) begin : gen_debug_trans_seq // DEBUG WRITE TRANSACTION SEQUENCE COUNTER always @(posedge ACLK) begin if (reset) begin debug_aw_trans_seq_i <= 1; end else begin if (aa_sa_awvalid && aa_sa_awready) begin debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1; end end end // DEBUG READ TRANSACTION SEQUENCE COUNTER always @(posedge ACLK) begin if (reset) begin debug_ar_trans_seq_i <= 1; end else begin if (aa_mi_arvalid && aa_mi_arready) begin debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1; end end end end // gen_debug_trans_seq // Broadcast AR transfer payload to all MI-slots assign M_AXI_ARID = {C_NUM_MASTER_SLOTS{aa_mi_armesg[0+:C_AXI_ID_WIDTH]}}; assign M_AXI_ARADDR = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}}; assign M_AXI_ARLEN = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}}; assign M_AXI_ARSIZE = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}}; assign M_AXI_ARLOCK = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}}; assign M_AXI_ARPROT = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}}; assign M_AXI_ARREGION = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}}; assign M_AXI_ARBURST = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}}; assign M_AXI_ARCACHE = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}}; assign M_AXI_ARQOS = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}}; assign M_AXI_ARUSER = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_ARUSER_WIDTH]}}; // AW arbiter command transfer completes upon completion of both M-side AW-channel transfer and W-mux address acceptance (command push). axi_crossbar_v2_1_splitter # // "SA": Splitter for Write Addr Arbiter ( .C_NUM_M (2) ) splitter_aw_mi ( .ACLK (ACLK), .ARESET (reset), .S_VALID (aa_sa_awvalid), .S_READY (aa_sa_awready), .M_VALID ({mi_awvalid_en, sa_wm_awvalid_en}), .M_READY ({mi_awready_mux, sa_wm_awready_mux}) ); assign mi_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{mi_awvalid_en}}; assign mi_awready_mux = |(aa_mi_awtarget_hot & mi_awready); assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS]; // Slot C_NUM_MASTER_SLOTS+1 is the error handler assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY; assign sa_wm_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{sa_wm_awvalid_en}}; assign sa_wm_awready_mux = |(aa_mi_awtarget_hot & sa_wm_awready); assign mi_arvalid = aa_mi_artarget_hot & {C_NUM_MASTER_SLOTS+1{aa_mi_arvalid}}; assign aa_mi_arready = |(aa_mi_artarget_hot & mi_arready); assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS]; // Slot C_NUM_MASTER_SLOTS+1 is the error handler assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY; // MI-slot # C_NUM_MASTER_SLOTS is the error handler if (C_RANGE_CHECK) begin : gen_decerr_slave axi_crossbar_v2_1_decerr_slave # ( .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_RESP (P_DECERR) ) decerr_slave_inst ( .S_AXI_ACLK (ACLK), .S_AXI_ARESET (reset), .S_AXI_AWID (aa_mi_awmesg[0+:C_AXI_ID_WIDTH]), .S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]), .S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]), .S_AXI_WLAST (mi_wlast[C_NUM_MASTER_SLOTS]), .S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]), .S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]), .S_AXI_BID (mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]), .S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]), .S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]), .S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]), .S_AXI_ARID (aa_mi_armesg[0+:C_AXI_ID_WIDTH]), .S_AXI_ARLEN (aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]), .S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]), .S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]), .S_AXI_RID (mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]), .S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]), .S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]), .S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]), .S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]), .S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]), .S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS]) ); end else begin : gen_no_decerr_slave assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0; assign mi_wready[C_NUM_MASTER_SLOTS] = 1'b0; assign mi_arready[C_NUM_MASTER_SLOTS] = 1'b0; assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0; assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0; assign mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign mi_bresp[C_NUM_MASTER_SLOTS*2+:2] = 0; assign mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0; assign mi_bvalid[C_NUM_MASTER_SLOTS] = 1'b0; assign mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0; assign mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0; assign mi_rresp[C_NUM_MASTER_SLOTS*2+:2] = 0; assign mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0; assign mi_rlast[C_NUM_MASTER_SLOTS] = 1'b0; assign mi_rvalid[C_NUM_MASTER_SLOTS] = 1'b0; end // gen_decerr_slave endgenerate endmodule `default_nettype wire
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 03/12/2016 06:18:20 PM // Design Name: // Module Name: Mux_Array // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Mux_Array #(parameter SWR=26, parameter EWR=5) ( input wire clk, input wire rst, input wire load_i, input wire [SWR-1:0] Data_i, input wire FSM_left_right_i, input wire [EWR-1:0] Shift_Value_i, input wire bit_shift_i, output wire [SWR-1:0] Data_o ); //// wire [SWR-1:0] Data_array[EWR+1:0]; //////////////////7 genvar k;//Level ///////////////////77777 Rotate_Mux_Array #(.SWR(SWR)) first_rotate( .Data_i(Data_i), .select_i(FSM_left_right_i), .Data_o(Data_array [0][SWR-1:0]) ); generate for (k=0; k < 3; k=k+1) begin shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array( .Data_i(Data_array[k]), .select_i(Shift_Value_i[k]), .bit_shift_i(bit_shift_i), .Data_o(Data_array[k+1]) ); end endgenerate RegisterAdd #(.W(SWR)) Mid_Reg( .clk(clk), .rst(rst), .load(1'b1), .D(Data_array[3]), .Q(Data_array[4]) ); generate for (k=3; k < EWR; k=k+1) begin shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array( .Data_i(Data_array[k+1]), .select_i(Shift_Value_i[k]), .bit_shift_i(bit_shift_i), .Data_o(Data_array[k+2]) ); end endgenerate Rotate_Mux_Array #(.SWR(SWR)) last_rotate( .Data_i(Data_array[EWR+1]), .select_i(FSM_left_right_i), .Data_o(Data_o) ); endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 03/12/2016 06:18:20 PM // Design Name: // Module Name: Mux_Array // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Mux_Array #(parameter SWR=26, parameter EWR=5) ( input wire clk, input wire rst, input wire load_i, input wire [SWR-1:0] Data_i, input wire FSM_left_right_i, input wire [EWR-1:0] Shift_Value_i, input wire bit_shift_i, output wire [SWR-1:0] Data_o ); //// wire [SWR-1:0] Data_array[EWR+1:0]; //////////////////7 genvar k;//Level ///////////////////77777 Rotate_Mux_Array #(.SWR(SWR)) first_rotate( .Data_i(Data_i), .select_i(FSM_left_right_i), .Data_o(Data_array [0][SWR-1:0]) ); generate for (k=0; k < 3; k=k+1) begin shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array( .Data_i(Data_array[k]), .select_i(Shift_Value_i[k]), .bit_shift_i(bit_shift_i), .Data_o(Data_array[k+1]) ); end endgenerate RegisterAdd #(.W(SWR)) Mid_Reg( .clk(clk), .rst(rst), .load(1'b1), .D(Data_array[3]), .Q(Data_array[4]) ); generate for (k=3; k < EWR; k=k+1) begin shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array( .Data_i(Data_array[k+1]), .select_i(Shift_Value_i[k]), .bit_shift_i(bit_shift_i), .Data_o(Data_array[k+2]) ); end endgenerate Rotate_Mux_Array #(.SWR(SWR)) last_rotate( .Data_i(Data_array[EWR+1]), .select_i(FSM_left_right_i), .Data_o(Data_o) ); endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_intr_wr_mem.v * * Date : 2012-11 * * Description : Mimics interconnect for Writes between AFI and DDRC/OCM * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_intr_wr_mem( sw_clk, rstn, full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR ); `include "processing_system7_bfm_v2_0_5_local_params.v" /* local parameters for interconnect wr fifo model */ input sw_clk, rstn; output full; input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; output reg [max_burst_bits-1:0] WR_DATA; output reg [addr_width-1:0] WR_ADDR; output reg [max_burst_bytes_width:0] WR_BYTES; output reg [axi_qos_width-1:0] WR_QOS; reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0; reg [wr_fifo_data_bits-1:0] wr_fifo [0:intr_max_outstanding-1]; wire empty; assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0; assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0; parameter SEND_DATA = 0, WAIT_ACK = 1; reg state; task automatic write_mem; input [wr_fifo_data_bits-1:0] data; begin wr_fifo[wr_ptr[intr_cnt_width-2:0]] = data; if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) wr_ptr[intr_cnt_width-2:0] = 0; else wr_ptr = wr_ptr + 1; end endtask always@(negedge rstn or posedge sw_clk) begin if(!rstn) begin wr_ptr = 0; rd_ptr = 0; WR_DATA_VALID_DDR = 1'b0; WR_DATA_VALID_OCM = 1'b0; WR_QOS = 0; state = SEND_DATA; end else begin case(state) SEND_DATA :begin state = SEND_DATA; WR_DATA_VALID_OCM = 1'b0; WR_DATA_VALID_DDR = 1'b0; if(!empty) begin WR_DATA = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_data_msb : wr_data_lsb]; WR_ADDR = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb]; WR_BYTES = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_bytes_msb : wr_bytes_lsb]; WR_QOS = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_qos_msb : wr_qos_lsb]; state = WAIT_ACK; case(decode_address(wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb])) OCM_MEM : WR_DATA_VALID_OCM = 1; DDR_MEM : WR_DATA_VALID_DDR = 1; default : state = SEND_DATA; endcase if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) begin rd_ptr[intr_cnt_width-2:0] = 0; end else begin rd_ptr = rd_ptr+1; end end end WAIT_ACK :begin state = WAIT_ACK; if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin WR_DATA_VALID_OCM = 1'b0; WR_DATA_VALID_DDR = 1'b0; state = SEND_DATA; end end endcase end end endmodule
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: addr_arbiter.v // // Description: // Instantiates generic priority encoder. // Each request is qualified if its target has not reached its issuing limit. // Muxes mesg and target inputs based on arbitration results. //----------------------------------------------------------------------------- // // Structure: // addr_arbiter // mux_enc //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_addr_arbiter # ( parameter C_FAMILY = "none", parameter integer C_NUM_S = 1, parameter integer C_NUM_S_LOG = 1, parameter integer C_NUM_M = 1, parameter integer C_MESG_WIDTH = 1, parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY = {C_NUM_S{32'h00000000}} // Arbitration priority among each SI slot. // Higher values indicate higher priority. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 'h0-'hF. ) ( // Global Signals input wire ACLK, input wire ARESET, // Slave Ports input wire [C_NUM_S*C_MESG_WIDTH-1:0] S_MESG, input wire [C_NUM_S*C_NUM_M-1:0] S_TARGET_HOT, input wire [C_NUM_S-1:0] S_VALID, input wire [C_NUM_S-1:0] S_VALID_QUAL, output wire [C_NUM_S-1:0] S_READY, // Master Ports output wire [C_MESG_WIDTH-1:0] M_MESG, output wire [C_NUM_M-1:0] M_TARGET_HOT, output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, output wire M_VALID, input wire M_READY, // Sideband input input wire [C_NUM_M-1:0] ISSUING_LIMIT ); // Generates a mask for all input slots that are priority based function [C_NUM_S-1:0] f_prio_mask ( input integer null_arg ); reg [C_NUM_S-1:0] mask; integer i; begin mask = 0; for (i=0; i < C_NUM_S; i=i+1) begin mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0); end f_prio_mask = mask; end endfunction // Convert 16-bit one-hot to 4-bit binary function [3:0] f_hot2enc ( input [15:0] one_hot ); begin f_hot2enc[0] = |(one_hot & 16'b1010101010101010); f_hot2enc[1] = |(one_hot & 16'b1100110011001100); f_hot2enc[2] = |(one_hot & 16'b1111000011110000); f_hot2enc[3] = |(one_hot & 16'b1111111100000000); end endfunction localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0); reg m_valid_i; reg [C_NUM_S-1:0] s_ready_i; reg [C_NUM_S-1:0] qual_reg; reg [C_NUM_S-1:0] grant_hot; reg [C_NUM_S-1:0] last_rr_hot; reg any_grant; reg any_prio; reg found_prio; reg [C_NUM_S-1:0] which_prio_hot; reg [C_NUM_S-1:0] next_prio_hot; reg [C_NUM_S_LOG-1:0] which_prio_enc; reg [C_NUM_S_LOG-1:0] next_prio_enc; reg [4:0] current_highest; wire [C_NUM_S-1:0] valid_rr; reg [15:0] next_rr_hot; reg [C_NUM_S_LOG-1:0] next_rr_enc; reg [C_NUM_S*C_NUM_S-1:0] carry_rr; reg [C_NUM_S*C_NUM_S-1:0] mask_rr; reg found_rr; wire [C_NUM_S-1:0] next_hot; wire [C_NUM_S_LOG-1:0] next_enc; reg prio_stall; integer i; wire [C_NUM_S-1:0] valid_qual_i; reg [C_NUM_S_LOG-1:0] m_grant_enc_i; reg [C_NUM_M-1:0] m_target_hot_i; wire [C_NUM_M-1:0] m_target_hot_mux; reg [C_MESG_WIDTH-1:0] m_mesg_i; wire [C_MESG_WIDTH-1:0] m_mesg_mux; genvar gen_si; assign M_VALID = m_valid_i; assign S_READY = s_ready_i; assign M_GRANT_ENC = m_grant_enc_i; assign M_MESG = m_mesg_i; assign M_TARGET_HOT = m_target_hot_i; generate if (C_NUM_S>1) begin : gen_arbiter always @(posedge ACLK) begin if (ARESET) begin qual_reg <= 0; end else begin qual_reg <= valid_qual_i | ~S_VALID; // Don't disqualify when bus not VALID (valid_qual_i would be garbage) end end for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_req_qual assign valid_qual_i[gen_si] = S_VALID_QUAL[gen_si] & (|(S_TARGET_HOT[gen_si*C_NUM_M+:C_NUM_M] & ~ISSUING_LIMIT)); end ///////////////////////////////////////////////////////////////////////////// // Grant a new request when there is none still pending. // If no qualified requests found, de-assert M_VALID. ///////////////////////////////////////////////////////////////////////////// assign next_hot = found_prio ? next_prio_hot : next_rr_hot; assign next_enc = found_prio ? next_prio_enc : next_rr_enc; always @(posedge ACLK) begin if (ARESET) begin m_valid_i <= 0; s_ready_i <= 0; grant_hot <= 0; any_grant <= 1'b0; m_grant_enc_i <= 0; last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}}; m_target_hot_i <= 0; end else begin s_ready_i <= 0; if (m_valid_i) begin // Stall 1 cycle after each master-side completion. if (M_READY) begin // Master-side completion m_valid_i <= 1'b0; grant_hot <= 0; any_grant <= 1'b0; end end else if (any_grant) begin m_valid_i <= 1'b1; s_ready_i <= grant_hot; // Assert S_AW/READY for 1 cycle to complete SI address transfer (regardless of M_AREADY) end else begin if ((found_prio | found_rr) & ~prio_stall) begin // Waste 1 cycle and re-arbitrate if target of highest prio hit issuing limit in previous cycle (valid_qual_i). if (|(next_hot & valid_qual_i)) begin grant_hot <= next_hot; m_grant_enc_i <= next_enc; any_grant <= 1'b1; if (~found_prio) begin last_rr_hot <= next_rr_hot; end m_target_hot_i <= m_target_hot_mux; end end end end end ///////////////////////////////////////////////////////////////////////////// // Fixed Priority arbiter // Selects next request to grant from among inputs with PRIO > 0, if any. ///////////////////////////////////////////////////////////////////////////// always @ * begin : ALG_PRIO integer ip; any_prio = 1'b0; prio_stall = 1'b0; which_prio_hot = 0; which_prio_enc = 0; current_highest = 0; for (ip=0; ip < C_NUM_S; ip=ip+1) begin // Disqualify slot if target hit issuing limit (pass to lower prio slot). if (P_PRIO_MASK[ip] & S_VALID[ip] & qual_reg[ip]) begin if ({1'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest) begin current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4]; // Stall 1 cycle when highest prio is recovering from SI-side handshake. // (Do not allow lower-prio slot to win arbitration.) if (s_ready_i[ip]) begin any_prio = 1'b0; prio_stall = 1'b1; which_prio_hot = 0; which_prio_enc = 0; end else begin any_prio = 1'b1; which_prio_hot = 1'b1 << ip; which_prio_enc = ip; end end end end found_prio = any_prio; next_prio_hot = which_prio_hot; next_prio_enc = which_prio_enc; end ///////////////////////////////////////////////////////////////////////////// // Round-robin arbiter // Selects next request to grant from among inputs with PRIO = 0, if any. ///////////////////////////////////////////////////////////////////////////// // Disqualify slot if target hit issuing limit 2 or more cycles earlier (pass to next RR slot). // Disqualify for 1 cycle a slot that is recovering from SI-side handshake (s_ready_i), // and allow arbitration to pass to any other RR requester. assign valid_rr = ~P_PRIO_MASK & S_VALID & ~s_ready_i & qual_reg; always @ * begin : ALG_RR integer ir, jr, nr; next_rr_hot = 0; for (ir=0;ir<C_NUM_S;ir=ir+1) begin nr = (ir>0) ? (ir-1) : (C_NUM_S-1); carry_rr[ir*C_NUM_S] = last_rr_hot[nr]; mask_rr[ir*C_NUM_S] = ~valid_rr[nr]; for (jr=1;jr<C_NUM_S;jr=jr+1) begin nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1); carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]); if (jr < C_NUM_S-1) begin mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr]; end end next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1]; end next_rr_enc = f_hot2enc(next_rr_hot); found_rr = |(next_rr_hot); end generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_S), .C_SEL_WIDTH (C_NUM_S_LOG), .C_DATA_WIDTH (C_MESG_WIDTH) ) mux_mesg ( .S (m_grant_enc_i), .A (S_MESG), .O (m_mesg_mux), .OE (1'b1) ); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_S), .C_SEL_WIDTH (C_NUM_S_LOG), .C_DATA_WIDTH (C_NUM_M) ) si_amesg_mux_inst ( .S (next_enc), .A (S_TARGET_HOT), .O (m_target_hot_mux), .OE (1'b1) ); always @(posedge ACLK) begin if (ARESET) begin m_mesg_i <= 0; end else if (~m_valid_i) begin m_mesg_i <= m_mesg_mux; end end end else begin : gen_no_arbiter assign valid_qual_i = S_VALID_QUAL & |(S_TARGET_HOT & ~ISSUING_LIMIT); always @ (posedge ACLK) begin if (ARESET) begin m_valid_i <= 1'b0; s_ready_i <= 1'b0; m_grant_enc_i <= 0; end else begin s_ready_i <= 1'b0; if (m_valid_i) begin if (M_READY) begin m_valid_i <= 1'b0; end end else if (S_VALID[0] & valid_qual_i[0] & ~s_ready_i) begin m_valid_i <= 1'b1; s_ready_i <= 1'b1; m_target_hot_i <= S_TARGET_HOT; end end end always @(posedge ACLK) begin if (ARESET) begin m_mesg_i <= 0; end else if (~m_valid_i) begin m_mesg_i <= S_MESG; end end end // gen_arbiter endgenerate endmodule `default_nettype wire
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_intr_rd_mem.v * * Date : 2012-11 * * Description : Mimics interconnect for Reads between AFI and DDRC/OCM * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_intr_rd_mem( sw_clk, rstn, full, empty, req, invalid_rd_req, rd_info, RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR ); `include "processing_system7_bfm_v2_0_5_local_params.v" input sw_clk, rstn; output full, empty; input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM; input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM; input req, invalid_rd_req; input [rd_info_bits-1:0] rd_info; reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0; reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes wire full, empty; assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0; assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0; /* read from the fifo */ task read_mem; output [rd_afi_fifo_bits-1:0] data; begin data = rd_fifo[rd_ptr[intr_cnt_width-1:0]]; if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) rd_ptr[intr_cnt_width-2:0] = 0; else rd_ptr = rd_ptr + 1; end endtask reg state; reg invalid_rd; /* write in the fifo */ always@(negedge rstn or posedge sw_clk) begin if(!rstn) begin wr_ptr = 0; rd_ptr = 0; state = 0; invalid_rd = 0; end else begin case (state) 0 : begin state = 0; invalid_rd = 0; if(req)begin state = 1; invalid_rd = invalid_rd_req; end end 1 : begin state = 1; if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin if(RD_DATA_VALID_DDR) rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_DDR,rd_info}; else if(RD_DATA_VALID_OCM) rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_OCM,rd_info}; else rd_fifo[wr_ptr[intr_cnt_width-2:0]] = rd_info; if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) wr_ptr[intr_cnt_width-2:0] = 0; else wr_ptr = wr_ptr + 1; state = 0; invalid_rd = 0; end end endcase end end endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: AXI Splitter // Each transfer received on the AXI handshake slave port is replicated onto // each of the master ports, and is completed back to the slave (S_READY) // once all master ports have completed. // // M_VALID is asserted combinatorially from S_VALID assertion. // Each M_VALID is masked off beginning the cycle after each M_READY is // received (if S_READY remains low) until the cycle after both S_VALID // and S_READY are asserted. // S_READY is asserted combinatorially when the last (or all) of the M_READY // inputs have been received. // If all M_READYs are asserted when S_VALID is asserted, back-to-back // handshakes can occur without bubble cycles. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // splitter // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_splitter # ( parameter integer C_NUM_M = 2 // Number of master ports = [2:16] ) ( // Global Signals input wire ACLK, input wire ARESET, // Slave Port input wire S_VALID, output wire S_READY, // Master Ports output wire [C_NUM_M-1:0] M_VALID, input wire [C_NUM_M-1:0] M_READY ); reg [C_NUM_M-1:0] m_ready_d; wire s_ready_i; wire [C_NUM_M-1:0] m_valid_i; always @(posedge ACLK) begin if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}}; else m_ready_d <= m_ready_d | (m_valid_i & M_READY); end assign s_ready_i = &(m_ready_d | M_READY); assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d; assign M_VALID = m_valid_i; assign S_READY = s_ready_i; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: AXI Splitter // Each transfer received on the AXI handshake slave port is replicated onto // each of the master ports, and is completed back to the slave (S_READY) // once all master ports have completed. // // M_VALID is asserted combinatorially from S_VALID assertion. // Each M_VALID is masked off beginning the cycle after each M_READY is // received (if S_READY remains low) until the cycle after both S_VALID // and S_READY are asserted. // S_READY is asserted combinatorially when the last (or all) of the M_READY // inputs have been received. // If all M_READYs are asserted when S_VALID is asserted, back-to-back // handshakes can occur without bubble cycles. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // splitter // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_splitter # ( parameter integer C_NUM_M = 2 // Number of master ports = [2:16] ) ( // Global Signals input wire ACLK, input wire ARESET, // Slave Port input wire S_VALID, output wire S_READY, // Master Ports output wire [C_NUM_M-1:0] M_VALID, input wire [C_NUM_M-1:0] M_READY ); reg [C_NUM_M-1:0] m_ready_d; wire s_ready_i; wire [C_NUM_M-1:0] m_valid_i; always @(posedge ACLK) begin if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}}; else m_ready_d <= m_ready_d | (m_valid_i & M_READY); end assign s_ready_i = &(m_ready_d | M_READY); assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d; assign M_VALID = m_valid_i; assign S_READY = s_ready_i; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: AXI Splitter // Each transfer received on the AXI handshake slave port is replicated onto // each of the master ports, and is completed back to the slave (S_READY) // once all master ports have completed. // // M_VALID is asserted combinatorially from S_VALID assertion. // Each M_VALID is masked off beginning the cycle after each M_READY is // received (if S_READY remains low) until the cycle after both S_VALID // and S_READY are asserted. // S_READY is asserted combinatorially when the last (or all) of the M_READY // inputs have been received. // If all M_READYs are asserted when S_VALID is asserted, back-to-back // handshakes can occur without bubble cycles. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // splitter // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_splitter # ( parameter integer C_NUM_M = 2 // Number of master ports = [2:16] ) ( // Global Signals input wire ACLK, input wire ARESET, // Slave Port input wire S_VALID, output wire S_READY, // Master Ports output wire [C_NUM_M-1:0] M_VALID, input wire [C_NUM_M-1:0] M_READY ); reg [C_NUM_M-1:0] m_ready_d; wire s_ready_i; wire [C_NUM_M-1:0] m_valid_i; always @(posedge ACLK) begin if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}}; else m_ready_d <= m_ready_d | (m_valid_i & M_READY); end assign s_ready_i = &(m_ready_d | M_READY); assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d; assign M_VALID = m_valid_i; assign S_READY = s_ready_i; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: AXI Splitter // Each transfer received on the AXI handshake slave port is replicated onto // each of the master ports, and is completed back to the slave (S_READY) // once all master ports have completed. // // M_VALID is asserted combinatorially from S_VALID assertion. // Each M_VALID is masked off beginning the cycle after each M_READY is // received (if S_READY remains low) until the cycle after both S_VALID // and S_READY are asserted. // S_READY is asserted combinatorially when the last (or all) of the M_READY // inputs have been received. // If all M_READYs are asserted when S_VALID is asserted, back-to-back // handshakes can occur without bubble cycles. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // splitter // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_splitter # ( parameter integer C_NUM_M = 2 // Number of master ports = [2:16] ) ( // Global Signals input wire ACLK, input wire ARESET, // Slave Port input wire S_VALID, output wire S_READY, // Master Ports output wire [C_NUM_M-1:0] M_VALID, input wire [C_NUM_M-1:0] M_READY ); reg [C_NUM_M-1:0] m_ready_d; wire s_ready_i; wire [C_NUM_M-1:0] m_valid_i; always @(posedge ACLK) begin if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}}; else m_ready_d <= m_ready_d | (m_valid_i & M_READY); end assign s_ready_i = &(m_ready_d | M_READY); assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d; assign M_VALID = m_valid_i; assign S_READY = s_ready_i; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: AXI Splitter // Each transfer received on the AXI handshake slave port is replicated onto // each of the master ports, and is completed back to the slave (S_READY) // once all master ports have completed. // // M_VALID is asserted combinatorially from S_VALID assertion. // Each M_VALID is masked off beginning the cycle after each M_READY is // received (if S_READY remains low) until the cycle after both S_VALID // and S_READY are asserted. // S_READY is asserted combinatorially when the last (or all) of the M_READY // inputs have been received. // If all M_READYs are asserted when S_VALID is asserted, back-to-back // handshakes can occur without bubble cycles. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // splitter // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_splitter # ( parameter integer C_NUM_M = 2 // Number of master ports = [2:16] ) ( // Global Signals input wire ACLK, input wire ARESET, // Slave Port input wire S_VALID, output wire S_READY, // Master Ports output wire [C_NUM_M-1:0] M_VALID, input wire [C_NUM_M-1:0] M_READY ); reg [C_NUM_M-1:0] m_ready_d; wire s_ready_i; wire [C_NUM_M-1:0] m_valid_i; always @(posedge ACLK) begin if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}}; else m_ready_d <= m_ready_d | (m_valid_i & M_READY); end assign s_ready_i = &(m_ready_d | M_READY); assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d; assign M_VALID = m_valid_i; assign S_READY = s_ready_i; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: AXI Splitter // Each transfer received on the AXI handshake slave port is replicated onto // each of the master ports, and is completed back to the slave (S_READY) // once all master ports have completed. // // M_VALID is asserted combinatorially from S_VALID assertion. // Each M_VALID is masked off beginning the cycle after each M_READY is // received (if S_READY remains low) until the cycle after both S_VALID // and S_READY are asserted. // S_READY is asserted combinatorially when the last (or all) of the M_READY // inputs have been received. // If all M_READYs are asserted when S_VALID is asserted, back-to-back // handshakes can occur without bubble cycles. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // splitter // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_splitter # ( parameter integer C_NUM_M = 2 // Number of master ports = [2:16] ) ( // Global Signals input wire ACLK, input wire ARESET, // Slave Port input wire S_VALID, output wire S_READY, // Master Ports output wire [C_NUM_M-1:0] M_VALID, input wire [C_NUM_M-1:0] M_READY ); reg [C_NUM_M-1:0] m_ready_d; wire s_ready_i; wire [C_NUM_M-1:0] m_valid_i; always @(posedge ACLK) begin if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}}; else m_ready_d <= m_ready_d | (m_valid_i & M_READY); end assign s_ready_i = &(m_ready_d | M_READY); assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d; assign M_VALID = m_valid_i; assign S_READY = s_ready_i; endmodule
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: crossbar_sasd.v // // Description: // This module is a M-master to N-slave AXI axi_crossbar_v2_1_crossbar switch. // Single transaction issuing, single arbiter (both W&R), single data pathways. // The interface of this module consists of a vectored slave and master interface // in which all slots are sized and synchronized to the native width and clock // of the interconnect, and are all AXI4 protocol. // All width, clock and protocol conversions are done outside this block, as are // any pipeline registers or data FIFOs. // This module contains all arbitration, decoders and channel multiplexing logic. // It also contains the diagnostic registers and control interface. // //-------------------------------------------------------------------------- // // Structure: // crossbar_sasd // addr_arbiter_sasd // mux_enc // addr_decoder // comparator_static // splitter // mux_enc // axic_register_slice // decerr_slave // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_crossbar_sasd # ( parameter C_FAMILY = "none", parameter integer C_NUM_SLAVE_SLOTS = 1, parameter integer C_NUM_MASTER_SLOTS = 1, parameter integer C_NUM_ADDR_RANGES = 1, parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_PROTOCOL = 0, parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}}, parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}}, parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}}, parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}}, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE = {C_NUM_SLAVE_SLOTS{1'b1}}, parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ = {C_NUM_SLAVE_SLOTS{1'b1}}, parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE = {C_NUM_MASTER_SLOTS{1'b1}}, parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ = {C_NUM_MASTER_SLOTS{1'b1}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = {C_NUM_SLAVE_SLOTS{32'h00000000}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = {C_NUM_MASTER_SLOTS{32'h00000000}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}}, parameter integer C_R_REGISTER = 0, parameter integer C_RANGE_CHECK = 0, parameter integer C_ADDR_DECODE = 0, parameter integer C_DEBUG = 1 ) ( // Global Signals input wire ACLK, input wire ARESETN, // Slave Interface Write Address Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_AWLEN, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWSIZE, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWBURST, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWLOCK, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWCACHE, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWPROT, // input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWREGION, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWQOS, input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWREADY, // Slave Interface Write Data Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_WID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WLAST, input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WREADY, // Slave Interface Write Response Ports output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_BID, output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_BRESP, output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BVALID, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BREADY, // Slave Interface Read Address Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_ARID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_ARLEN, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARSIZE, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARBURST, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARLOCK, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARCACHE, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARPROT, // input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARREGION, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARQOS, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARREADY, // Slave Interface Read Data Ports output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_RID, output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_RRESP, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RLAST, output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RVALID, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RREADY, // Master Interface Write Address Port output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_AWLEN, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWSIZE, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWBURST, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWLOCK, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWCACHE, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWPROT, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWREGION, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWQOS, output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWREADY, // Master Interface Write Data Ports output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_WID, output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WLAST, output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WREADY, // Master Interface Write Response Ports input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_BID, // Unused input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_BRESP, input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BVALID, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BREADY, // Master Interface Read Address Port output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_ARID, output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_ARLEN, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARSIZE, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARBURST, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARLOCK, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARCACHE, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARPROT, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARREGION, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARQOS, output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARREADY, // Master Interface Read Data Ports input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_RID, // Unused input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_RRESP, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RLAST, input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RVALID, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RREADY ); localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; localparam integer P_NUM_MASTER_SLOTS_DE = C_RANGE_CHECK ? C_NUM_MASTER_SLOTS+1 : C_NUM_MASTER_SLOTS; localparam integer P_NUM_MASTER_SLOTS_LOG = (C_NUM_MASTER_SLOTS>1) ? f_ceil_log2(C_NUM_MASTER_SLOTS) : 1; localparam integer P_NUM_MASTER_SLOTS_DE_LOG = (P_NUM_MASTER_SLOTS_DE>1) ? f_ceil_log2(P_NUM_MASTER_SLOTS_DE) : 1; localparam integer P_NUM_SLAVE_SLOTS_LOG = (C_NUM_SLAVE_SLOTS>1) ? f_ceil_log2(C_NUM_SLAVE_SLOTS) : 1; localparam integer P_AXI_AUSER_WIDTH = (C_AXI_AWUSER_WIDTH > C_AXI_ARUSER_WIDTH) ? C_AXI_AWUSER_WIDTH : C_AXI_ARUSER_WIDTH; localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1; localparam integer P_AMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+2+4+4 + P_AXI_AUSER_WIDTH + 4; localparam integer P_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH; localparam integer P_RMESG_WIDTH = 1+2 + C_AXI_DATA_WIDTH + C_AXI_RUSER_WIDTH; localparam integer P_WMESG_WIDTH = 1 + C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH; localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001; localparam integer P_NONSECURE_BIT = 1; localparam [C_NUM_MASTER_SLOTS-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXILITE_MASK = f_m_axilite(0); // Mask of axilite rule-check MI-slots localparam [1:0] P_FIXED = 2'b00; localparam integer P_BYPASS = 0; localparam integer P_LIGHTWT = 7; localparam integer P_FULLY_REG = 1; localparam integer P_R_REG_CONFIG = C_R_REGISTER == 8 ? // "Automatic" reg-slice (C_RANGE_CHECK ? ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHTWT : P_FULLY_REG) : P_BYPASS) : // Bypass if no R-channel mux C_R_REGISTER; localparam P_DECERR = 2'b11; //--------------------------------------------------------------------------- // Functions //--------------------------------------------------------------------------- // Ceiling of log2(x) function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2**acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value // only for end-point SI-slots function [C_AXI_ID_WIDTH-1:0] f_extend_ID ( input [C_AXI_ID_WIDTH-1:0] s_id, input integer slot ); begin f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH])); end endfunction // Convert Bit32 vector of range [0,1] to Bit1 vector on MI function [C_NUM_MASTER_SLOTS-1:0] f_bit32to1_mi (input [C_NUM_MASTER_SLOTS*32-1:0] vec32); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_bit32to1_mi[mi] = vec32[mi*32]; end end endfunction // AxiLite error-checking mask (on MI) function [C_NUM_MASTER_SLOTS-1:0] f_m_axilite ( input integer null_arg ); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_m_axilite[mi] = (C_M_AXI_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE); end end endfunction genvar gen_si_slot; genvar gen_mi_slot; wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0] si_awmesg ; wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0] si_armesg ; wire [P_AMESG_WIDTH-1:0] aa_amesg ; wire [C_AXI_ID_WIDTH-1:0] mi_aid ; wire [C_AXI_ADDR_WIDTH-1:0] mi_aaddr ; wire [8-1:0] mi_alen ; wire [3-1:0] mi_asize ; wire [2-1:0] mi_alock ; wire [3-1:0] mi_aprot ; wire [2-1:0] mi_aburst ; wire [4-1:0] mi_acache ; wire [4-1:0] mi_aregion ; wire [4-1:0] mi_aqos ; wire [P_AXI_AUSER_WIDTH-1:0] mi_auser ; wire [4-1:0] target_region ; wire [C_NUM_SLAVE_SLOTS*1-1:0] aa_grant_hot ; wire [P_NUM_SLAVE_SLOTS_LOG-1:0] aa_grant_enc ; wire aa_grant_rnw ; wire aa_grant_any ; wire [C_NUM_MASTER_SLOTS-1:0] target_mi_hot ; wire [P_NUM_MASTER_SLOTS_LOG-1:0] target_mi_enc ; reg [P_NUM_MASTER_SLOTS_DE-1:0] m_atarget_hot ; reg [P_NUM_MASTER_SLOTS_DE_LOG-1:0] m_atarget_enc ; wire [P_NUM_MASTER_SLOTS_DE_LOG-1:0] m_atarget_enc_comb ; wire match; wire any_error ; wire [7:0] m_aerror_i ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_awvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_awready ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_arvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_arready ; wire aa_awvalid ; wire aa_awready ; wire aa_arvalid ; wire aa_arready ; wire mi_awvalid_en; wire mi_awready_mux; wire mi_arvalid_en; wire mi_arready_mux; wire w_transfer_en; wire w_complete_mux; wire b_transfer_en; wire b_complete_mux; wire r_transfer_en; wire r_complete_mux; wire target_secure; wire target_write; wire target_read; wire target_axilite; wire [P_BMESG_WIDTH-1:0] si_bmesg ; wire [P_NUM_MASTER_SLOTS_DE*P_BMESG_WIDTH-1:0] mi_bmesg ; wire [P_NUM_MASTER_SLOTS_DE*2-1:0] mi_bresp ; wire [P_NUM_MASTER_SLOTS_DE*C_AXI_BUSER_WIDTH-1:0] mi_buser ; wire [2-1:0] si_bresp ; wire [C_AXI_BUSER_WIDTH-1:0] si_buser ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_bvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_bready ; wire aa_bvalid ; wire aa_bready ; wire si_bready ; wire [C_NUM_SLAVE_SLOTS-1:0] si_bvalid; wire [P_RMESG_WIDTH-1:0] aa_rmesg ; wire [P_RMESG_WIDTH-1:0] sr_rmesg ; wire [P_NUM_MASTER_SLOTS_DE*P_RMESG_WIDTH-1:0] mi_rmesg ; wire [P_NUM_MASTER_SLOTS_DE*2-1:0] mi_rresp ; wire [P_NUM_MASTER_SLOTS_DE*C_AXI_RUSER_WIDTH-1:0] mi_ruser ; wire [P_NUM_MASTER_SLOTS_DE*C_AXI_DATA_WIDTH-1:0] mi_rdata ; wire [P_NUM_MASTER_SLOTS_DE*1-1:0] mi_rlast ; wire [2-1:0] si_rresp ; wire [C_AXI_RUSER_WIDTH-1:0] si_ruser ; wire [C_AXI_DATA_WIDTH-1:0] si_rdata ; wire si_rlast ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_rvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_rready ; wire aa_rvalid ; wire aa_rready ; wire sr_rvalid ; wire si_rready ; wire sr_rready ; wire [C_NUM_SLAVE_SLOTS-1:0] si_rvalid; wire [C_NUM_SLAVE_SLOTS*P_WMESG_WIDTH-1:0] si_wmesg ; wire [P_WMESG_WIDTH-1:0] mi_wmesg ; wire [C_AXI_ID_WIDTH-1:0] mi_wid ; wire [C_AXI_DATA_WIDTH-1:0] mi_wdata ; wire [C_AXI_DATA_WIDTH/8-1:0] mi_wstrb ; wire [C_AXI_WUSER_WIDTH-1:0] mi_wuser ; wire [1-1:0] mi_wlast ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_wvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_wready ; wire aa_wvalid ; wire aa_wready ; wire [C_NUM_SLAVE_SLOTS-1:0] si_wready; reg [7:0] debug_r_beat_cnt_i; reg [7:0] debug_w_beat_cnt_i; reg [7:0] debug_aw_trans_seq_i; reg [7:0] debug_ar_trans_seq_i; reg aresetn_d = 1'b0; // Reset delay register always @(posedge ACLK) begin if (~ARESETN) begin aresetn_d <= 1'b0; end else begin aresetn_d <= ARESETN; end end wire reset; assign reset = ~aresetn_d; generate axi_crossbar_v2_1_addr_arbiter_sasd # ( .C_FAMILY (C_FAMILY), .C_NUM_S (C_NUM_SLAVE_SLOTS), .C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_AMESG_WIDTH (P_AMESG_WIDTH), .C_GRANT_ENC (1), .C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY) ) addr_arbiter_inst ( .ACLK (ACLK), .ARESET (reset), // Vector of SI-side AW command request inputs .S_AWMESG (si_awmesg), .S_ARMESG (si_armesg), .S_AWVALID (S_AXI_AWVALID), .S_AWREADY (S_AXI_AWREADY), .S_ARVALID (S_AXI_ARVALID), .S_ARREADY (S_AXI_ARREADY), .M_GRANT_ENC (aa_grant_enc), .M_GRANT_HOT (aa_grant_hot), // SI-slot 1-hot mask of granted command .M_GRANT_ANY (aa_grant_any), .M_GRANT_RNW (aa_grant_rnw), .M_AMESG (aa_amesg), // Either S_AWMESG or S_ARMESG, as indicated by M_AWVALID and M_ARVALID. .M_AWVALID (aa_awvalid), .M_AWREADY (aa_awready), .M_ARVALID (aa_arvalid), .M_ARREADY (aa_arready) ); if (C_ADDR_DECODE) begin : gen_addr_decoder axi_crossbar_v2_1_addr_decoder # ( .C_FAMILY (C_FAMILY), .C_NUM_TARGETS (C_NUM_MASTER_SLOTS), .C_NUM_TARGETS_LOG (P_NUM_MASTER_SLOTS_LOG), .C_NUM_RANGES (C_NUM_ADDR_RANGES), .C_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_TARGET_ENC (1), .C_TARGET_HOT (1), .C_REGION_ENC (1), .C_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_HIGH_ADDR (C_M_AXI_HIGH_ADDR), .C_TARGET_QUAL ({C_NUM_MASTER_SLOTS{1'b1}}), .C_RESOLUTION (2) ) addr_decoder_inst ( .ADDR (mi_aaddr), .TARGET_HOT (target_mi_hot), .TARGET_ENC (target_mi_enc), .MATCH (match), .REGION (target_region) ); end else begin : gen_no_addr_decoder assign target_mi_hot = 1; assign match = 1'b1; assign target_region = 4'b0000; end // gen_addr_decoder // AW-channel arbiter command transfer completes upon completion of both M-side AW-channel transfer and B channel completion. axi_crossbar_v2_1_splitter # ( .C_NUM_M (3) ) splitter_aw ( .ACLK (ACLK), .ARESET (reset), .S_VALID (aa_awvalid), .S_READY (aa_awready), .M_VALID ({mi_awvalid_en, w_transfer_en, b_transfer_en}), .M_READY ({mi_awready_mux, w_complete_mux, b_complete_mux}) ); // AR-channel arbiter command transfer completes upon completion of both M-side AR-channel transfer and R channel completion. axi_crossbar_v2_1_splitter # ( .C_NUM_M (2) ) splitter_ar ( .ACLK (ACLK), .ARESET (reset), .S_VALID (aa_arvalid), .S_READY (aa_arready), .M_VALID ({mi_arvalid_en, r_transfer_en}), .M_READY ({mi_arready_mux, r_complete_mux}) ); assign target_secure = |(target_mi_hot & P_M_SECURE_MASK); assign target_write = |(target_mi_hot & C_M_AXI_SUPPORTS_WRITE); assign target_read = |(target_mi_hot & C_M_AXI_SUPPORTS_READ); assign target_axilite = |(target_mi_hot & P_M_AXILITE_MASK); assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition. assign m_aerror_i[0] = ~match; // Invalid target address assign m_aerror_i[1] = target_secure && mi_aprot[P_NONSECURE_BIT]; // TrustZone violation assign m_aerror_i[2] = target_axilite && ((mi_alen != 0) || (mi_asize[1:0] == 2'b11) || (mi_asize[2] == 1'b1)); // AxiLite access violation assign m_aerror_i[3] = (~aa_grant_rnw && ~target_write) || (aa_grant_rnw && ~target_read); // R/W direction unsupported by target assign m_aerror_i[7:4] = 4'b0000; // Reserved assign m_atarget_enc_comb = any_error ? (P_NUM_MASTER_SLOTS_DE-1) : target_mi_enc; // Select MI slot or decerr_slave always @(posedge ACLK) begin if (reset) begin m_atarget_hot <= 0; m_atarget_enc <= 0; end else begin m_atarget_hot <= {P_NUM_MASTER_SLOTS_DE{aa_grant_any}} & (any_error ? {1'b1, {C_NUM_MASTER_SLOTS{1'b0}}} : {1'b0, target_mi_hot}); // Select MI slot or decerr_slave m_atarget_enc <= m_atarget_enc_comb; end end // Receive AWREADY from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_awready_mux_inst ( .S (m_atarget_enc), .A (mi_awready), .O (mi_awready_mux), .OE (mi_awvalid_en) ); // Receive ARREADY from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_arready_mux_inst ( .S (m_atarget_enc), .A (mi_arready), .O (mi_arready_mux), .OE (mi_arvalid_en) ); assign mi_awvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_awvalid_en}}; // Assert AWVALID on targeted MI. assign mi_arvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_arvalid_en}}; // Assert ARVALID on targeted MI. assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS]; // Propagate to MI slots. assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS]; // Propagate to MI slots. assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY; // Copy from MI slots. assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY; // Copy from MI slots. // Receive WREADY from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_wready_mux_inst ( .S (m_atarget_enc), .A (mi_wready), .O (aa_wready), .OE (w_transfer_en) ); assign mi_wvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_wvalid}}; // Assert WVALID on targeted MI. assign si_wready = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_wready}}; // Assert WREADY on granted SI. assign S_AXI_WREADY = si_wready; assign w_complete_mux = aa_wready & aa_wvalid & mi_wlast; // W burst complete on on designated SI/MI. // Receive RREADY from granted SI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_DATA_WIDTH (1) ) si_rready_mux_inst ( .S (aa_grant_enc), .A (S_AXI_RREADY), .O (si_rready), .OE (r_transfer_en) ); assign sr_rready = si_rready & r_transfer_en; assign mi_rready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_rready}}; // Assert RREADY on targeted MI. assign si_rvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{sr_rvalid}}; // Assert RVALID on granted SI. assign S_AXI_RVALID = si_rvalid; assign r_complete_mux = sr_rready & sr_rvalid & si_rlast; // R burst complete on on designated SI/MI. // Receive BREADY from granted SI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_DATA_WIDTH (1) ) si_bready_mux_inst ( .S (aa_grant_enc), .A (S_AXI_BREADY), .O (si_bready), .OE (b_transfer_en) ); assign aa_bready = si_bready & b_transfer_en; assign mi_bready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_bready}}; // Assert BREADY on targeted MI. assign si_bvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_bvalid}}; // Assert BVALID on granted SI. assign S_AXI_BVALID = si_bvalid; assign b_complete_mux = aa_bready & aa_bvalid; // B transfer complete on on designated SI/MI. for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_si_amesg assign si_armesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = { // Concatenate from MSB to LSB 4'b0000, // S_AXI_ARREGION[gen_si_slot*4+:4], S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH +: C_AXI_ARUSER_WIDTH], S_AXI_ARQOS[gen_si_slot*4+:4], S_AXI_ARCACHE[gen_si_slot*4+:4], S_AXI_ARBURST[gen_si_slot*2+:2], S_AXI_ARPROT[gen_si_slot*3+:3], S_AXI_ARLOCK[gen_si_slot*2+:2], S_AXI_ARSIZE[gen_si_slot*3+:3], S_AXI_ARLEN[gen_si_slot*8+:8], S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH], f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH +: C_AXI_ID_WIDTH], gen_si_slot) }; assign si_awmesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = { // Concatenate from MSB to LSB 4'b0000, // S_AXI_AWREGION[gen_si_slot*4+:4], S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH +: C_AXI_AWUSER_WIDTH], S_AXI_AWQOS[gen_si_slot*4+:4], S_AXI_AWCACHE[gen_si_slot*4+:4], S_AXI_AWBURST[gen_si_slot*2+:2], S_AXI_AWPROT[gen_si_slot*3+:3], S_AXI_AWLOCK[gen_si_slot*2+:2], S_AXI_AWSIZE[gen_si_slot*3+:3], S_AXI_AWLEN[gen_si_slot*8+:8], S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH], f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) }; end // gen_si_amesg assign mi_aid = aa_amesg[0 +: C_AXI_ID_WIDTH]; assign mi_aaddr = aa_amesg[C_AXI_ID_WIDTH +: C_AXI_ADDR_WIDTH]; assign mi_alen = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +: 8]; assign mi_asize = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +: 3]; assign mi_alock = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +: 2]; assign mi_aprot = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +: 3]; assign mi_aburst = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +: 2]; assign mi_acache = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2 +: 4]; assign mi_aqos = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4 +: 4]; assign mi_auser = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4 +: P_AXI_AUSER_WIDTH]; assign mi_aregion = (C_ADDR_DECODE != 0) ? target_region : aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4+P_AXI_AUSER_WIDTH +: 4]; // Broadcast AW transfer payload to all MI-slots assign M_AXI_AWID = {C_NUM_MASTER_SLOTS{mi_aid}}; assign M_AXI_AWADDR = {C_NUM_MASTER_SLOTS{mi_aaddr}}; assign M_AXI_AWLEN = {C_NUM_MASTER_SLOTS{mi_alen }}; assign M_AXI_AWSIZE = {C_NUM_MASTER_SLOTS{mi_asize}}; assign M_AXI_AWLOCK = {C_NUM_MASTER_SLOTS{mi_alock}}; assign M_AXI_AWPROT = {C_NUM_MASTER_SLOTS{mi_aprot}}; assign M_AXI_AWREGION = {C_NUM_MASTER_SLOTS{mi_aregion}}; assign M_AXI_AWBURST = {C_NUM_MASTER_SLOTS{mi_aburst}}; assign M_AXI_AWCACHE = {C_NUM_MASTER_SLOTS{mi_acache}}; assign M_AXI_AWQOS = {C_NUM_MASTER_SLOTS{mi_aqos }}; assign M_AXI_AWUSER = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_AWUSER_WIDTH] }}; // Broadcast AR transfer payload to all MI-slots assign M_AXI_ARID = {C_NUM_MASTER_SLOTS{mi_aid}}; assign M_AXI_ARADDR = {C_NUM_MASTER_SLOTS{mi_aaddr}}; assign M_AXI_ARLEN = {C_NUM_MASTER_SLOTS{mi_alen }}; assign M_AXI_ARSIZE = {C_NUM_MASTER_SLOTS{mi_asize}}; assign M_AXI_ARLOCK = {C_NUM_MASTER_SLOTS{mi_alock}}; assign M_AXI_ARPROT = {C_NUM_MASTER_SLOTS{mi_aprot}}; assign M_AXI_ARREGION = {C_NUM_MASTER_SLOTS{mi_aregion}}; assign M_AXI_ARBURST = {C_NUM_MASTER_SLOTS{mi_aburst}}; assign M_AXI_ARCACHE = {C_NUM_MASTER_SLOTS{mi_acache}}; assign M_AXI_ARQOS = {C_NUM_MASTER_SLOTS{mi_aqos }}; assign M_AXI_ARUSER = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_ARUSER_WIDTH] }}; // W-channel MI handshakes assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS]; assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY; // Broadcast W transfer payload to all MI-slots assign M_AXI_WLAST = {C_NUM_MASTER_SLOTS{mi_wlast}}; assign M_AXI_WUSER = {C_NUM_MASTER_SLOTS{mi_wuser}}; assign M_AXI_WDATA = {C_NUM_MASTER_SLOTS{mi_wdata}}; assign M_AXI_WSTRB = {C_NUM_MASTER_SLOTS{mi_wstrb}}; assign M_AXI_WID = {C_NUM_MASTER_SLOTS{mi_wid}}; // Broadcast R transfer payload to all SI-slots assign S_AXI_RLAST = {C_NUM_SLAVE_SLOTS{si_rlast}}; assign S_AXI_RRESP = {C_NUM_SLAVE_SLOTS{si_rresp}}; assign S_AXI_RUSER = {C_NUM_SLAVE_SLOTS{si_ruser}}; assign S_AXI_RDATA = {C_NUM_SLAVE_SLOTS{si_rdata}}; assign S_AXI_RID = {C_NUM_SLAVE_SLOTS{mi_aid}}; // Broadcast B transfer payload to all SI-slots assign S_AXI_BRESP = {C_NUM_SLAVE_SLOTS{si_bresp}}; assign S_AXI_BUSER = {C_NUM_SLAVE_SLOTS{si_buser}}; assign S_AXI_BID = {C_NUM_SLAVE_SLOTS{mi_aid}}; if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux // SI WVALID mux. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_DATA_WIDTH (1) ) si_w_valid_mux_inst ( .S (aa_grant_enc), .A (S_AXI_WVALID), .O (aa_wvalid), .OE (w_transfer_en) ); // SI W-channel payload mux generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_DATA_WIDTH (P_WMESG_WIDTH) ) si_w_payload_mux_inst ( .S (aa_grant_enc), .A (si_wmesg), .O (mi_wmesg), .OE (1'b1) ); for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_wmesg assign si_wmesg[gen_si_slot*P_WMESG_WIDTH+:P_WMESG_WIDTH] = { // Concatenate from MSB to LSB ((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0), S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH], S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8], S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH], S_AXI_WLAST[gen_si_slot*1+:1] }; end // gen_wmesg assign mi_wlast = mi_wmesg[0]; assign mi_wdata = mi_wmesg[1 +: C_AXI_DATA_WIDTH]; assign mi_wstrb = mi_wmesg[1+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8]; assign mi_wuser = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH]; assign mi_wid = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH]; end else begin : gen_no_wmux assign aa_wvalid = w_transfer_en & S_AXI_WVALID; assign mi_wlast = S_AXI_WLAST; assign mi_wdata = S_AXI_WDATA; assign mi_wstrb = S_AXI_WSTRB; assign mi_wuser = S_AXI_WUSER; assign mi_wid = S_AXI_WID; end // gen_wmux // Receive RVALID from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_rvalid_mux_inst ( .S (m_atarget_enc), .A (mi_rvalid), .O (aa_rvalid), .OE (r_transfer_en) ); // MI R-channel payload mux generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (P_RMESG_WIDTH) ) mi_rmesg_mux_inst ( .S (m_atarget_enc), .A (mi_rmesg), .O (aa_rmesg), .OE (1'b1) ); axi_register_slice_v2_1_axic_register_slice # ( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (P_RMESG_WIDTH), .C_REG_CONFIG (P_R_REG_CONFIG) ) reg_slice_r ( // System Signals .ACLK(ACLK), .ARESET(reset), // Slave side .S_PAYLOAD_DATA(aa_rmesg), .S_VALID(aa_rvalid), .S_READY(aa_rready), // Master side .M_PAYLOAD_DATA(sr_rmesg), .M_VALID(sr_rvalid), .M_READY(sr_rready) ); assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID; assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST; assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP; assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER; assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA; assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS]; for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_rmesg assign mi_rmesg[gen_mi_slot*P_RMESG_WIDTH+:P_RMESG_WIDTH] = { // Concatenate from MSB to LSB mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH], mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH], mi_rresp[gen_mi_slot*2+:2], mi_rlast[gen_mi_slot*1+:1] }; end // gen_rmesg assign si_rlast = sr_rmesg[0]; assign si_rresp = sr_rmesg[1 +: 2]; assign si_rdata = sr_rmesg[1+2 +: C_AXI_DATA_WIDTH]; assign si_ruser = sr_rmesg[1+2+C_AXI_DATA_WIDTH +: C_AXI_RUSER_WIDTH]; // Receive BVALID from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_bvalid_mux_inst ( .S (m_atarget_enc), .A (mi_bvalid), .O (aa_bvalid), .OE (b_transfer_en) ); // MI B-channel payload mux generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (P_BMESG_WIDTH) ) mi_bmesg_mux_inst ( .S (m_atarget_enc), .A (mi_bmesg), .O (si_bmesg), .OE (1'b1) ); assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID; assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP; assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER; assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS]; for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_bmesg assign mi_bmesg[gen_mi_slot*P_BMESG_WIDTH+:P_BMESG_WIDTH] = { // Concatenate from MSB to LSB mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH], mi_bresp[gen_mi_slot*2+:2] }; end // gen_bmesg assign si_bresp = si_bmesg[0 +: 2]; assign si_buser = si_bmesg[2 +: C_AXI_BUSER_WIDTH]; if (C_DEBUG) begin : gen_debug_trans_seq // DEBUG WRITE TRANSACTION SEQUENCE COUNTER always @(posedge ACLK) begin if (reset) begin debug_aw_trans_seq_i <= 1; end else begin if (aa_awvalid && aa_awready) begin debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1; end end end // DEBUG READ TRANSACTION SEQUENCE COUNTER always @(posedge ACLK) begin if (reset) begin debug_ar_trans_seq_i <= 1; end else begin if (aa_arvalid && aa_arready) begin debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1; end end end // DEBUG WRITE BEAT COUNTER always @(posedge ACLK) begin if (reset) begin debug_w_beat_cnt_i <= 0; end else if (aa_wready & aa_wvalid) begin if (mi_wlast) begin debug_w_beat_cnt_i <= 0; end else begin debug_w_beat_cnt_i <= debug_w_beat_cnt_i + 1; end end end // Clocked process // DEBUG READ BEAT COUNTER always @(posedge ACLK) begin if (reset) begin debug_r_beat_cnt_i <= 0; end else if (sr_rready & sr_rvalid) begin if (si_rlast) begin debug_r_beat_cnt_i <= 0; end else begin debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1; end end end // Clocked process end // gen_debug_trans_seq if (C_RANGE_CHECK) begin : gen_decerr // Highest MI-slot (index C_NUM_MASTER_SLOTS) is the error handler axi_crossbar_v2_1_decerr_slave # ( .C_AXI_ID_WIDTH (1), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_RESP (P_DECERR) ) decerr_slave_inst ( .S_AXI_ACLK (ACLK), .S_AXI_ARESET (reset), .S_AXI_AWID (1'b0), .S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]), .S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]), .S_AXI_WLAST (mi_wlast), .S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]), .S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]), .S_AXI_BID (), .S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]), .S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]), .S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]), .S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]), .S_AXI_ARID (1'b0), .S_AXI_ARLEN (mi_alen), .S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]), .S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]), .S_AXI_RID (), .S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]), .S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]), .S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]), .S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]), .S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]), .S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS]) ); end // gen_decerr endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: crossbar_sasd.v // // Description: // This module is a M-master to N-slave AXI axi_crossbar_v2_1_crossbar switch. // Single transaction issuing, single arbiter (both W&R), single data pathways. // The interface of this module consists of a vectored slave and master interface // in which all slots are sized and synchronized to the native width and clock // of the interconnect, and are all AXI4 protocol. // All width, clock and protocol conversions are done outside this block, as are // any pipeline registers or data FIFOs. // This module contains all arbitration, decoders and channel multiplexing logic. // It also contains the diagnostic registers and control interface. // //-------------------------------------------------------------------------- // // Structure: // crossbar_sasd // addr_arbiter_sasd // mux_enc // addr_decoder // comparator_static // splitter // mux_enc // axic_register_slice // decerr_slave // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_crossbar_sasd # ( parameter C_FAMILY = "none", parameter integer C_NUM_SLAVE_SLOTS = 1, parameter integer C_NUM_MASTER_SLOTS = 1, parameter integer C_NUM_ADDR_RANGES = 1, parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_PROTOCOL = 0, parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}}, parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}}, parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}}, parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}}, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE = {C_NUM_SLAVE_SLOTS{1'b1}}, parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ = {C_NUM_SLAVE_SLOTS{1'b1}}, parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE = {C_NUM_MASTER_SLOTS{1'b1}}, parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ = {C_NUM_MASTER_SLOTS{1'b1}}, parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = {C_NUM_SLAVE_SLOTS{32'h00000000}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = {C_NUM_MASTER_SLOTS{32'h00000000}}, parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}}, parameter integer C_R_REGISTER = 0, parameter integer C_RANGE_CHECK = 0, parameter integer C_ADDR_DECODE = 0, parameter integer C_DEBUG = 1 ) ( // Global Signals input wire ACLK, input wire ARESETN, // Slave Interface Write Address Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_AWLEN, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWSIZE, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWBURST, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWLOCK, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWCACHE, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWPROT, // input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWREGION, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWQOS, input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWREADY, // Slave Interface Write Data Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_WID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WLAST, input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WREADY, // Slave Interface Write Response Ports output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_BID, output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_BRESP, output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BVALID, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BREADY, // Slave Interface Read Address Ports input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_ARID, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_ARLEN, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARSIZE, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARBURST, input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARLOCK, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARCACHE, input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARPROT, // input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARREGION, input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARQOS, input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARREADY, // Slave Interface Read Data Ports output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_RID, output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_RRESP, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RLAST, output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RVALID, input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RREADY, // Master Interface Write Address Port output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_AWLEN, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWSIZE, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWBURST, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWLOCK, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWCACHE, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWPROT, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWREGION, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWQOS, output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWREADY, // Master Interface Write Data Ports output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_WID, output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WLAST, output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WREADY, // Master Interface Write Response Ports input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_BID, // Unused input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_BRESP, input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BVALID, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BREADY, // Master Interface Read Address Port output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_ARID, output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_ARLEN, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARSIZE, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARBURST, output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARLOCK, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARCACHE, output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARPROT, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARREGION, output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARQOS, output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARVALID, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARREADY, // Master Interface Read Data Ports input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_RID, // Unused input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_RRESP, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RLAST, input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RVALID, output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RREADY ); localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; localparam integer P_NUM_MASTER_SLOTS_DE = C_RANGE_CHECK ? C_NUM_MASTER_SLOTS+1 : C_NUM_MASTER_SLOTS; localparam integer P_NUM_MASTER_SLOTS_LOG = (C_NUM_MASTER_SLOTS>1) ? f_ceil_log2(C_NUM_MASTER_SLOTS) : 1; localparam integer P_NUM_MASTER_SLOTS_DE_LOG = (P_NUM_MASTER_SLOTS_DE>1) ? f_ceil_log2(P_NUM_MASTER_SLOTS_DE) : 1; localparam integer P_NUM_SLAVE_SLOTS_LOG = (C_NUM_SLAVE_SLOTS>1) ? f_ceil_log2(C_NUM_SLAVE_SLOTS) : 1; localparam integer P_AXI_AUSER_WIDTH = (C_AXI_AWUSER_WIDTH > C_AXI_ARUSER_WIDTH) ? C_AXI_AWUSER_WIDTH : C_AXI_ARUSER_WIDTH; localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1; localparam integer P_AMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+2+4+4 + P_AXI_AUSER_WIDTH + 4; localparam integer P_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH; localparam integer P_RMESG_WIDTH = 1+2 + C_AXI_DATA_WIDTH + C_AXI_RUSER_WIDTH; localparam integer P_WMESG_WIDTH = 1 + C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH; localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001; localparam integer P_NONSECURE_BIT = 1; localparam [C_NUM_MASTER_SLOTS-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXILITE_MASK = f_m_axilite(0); // Mask of axilite rule-check MI-slots localparam [1:0] P_FIXED = 2'b00; localparam integer P_BYPASS = 0; localparam integer P_LIGHTWT = 7; localparam integer P_FULLY_REG = 1; localparam integer P_R_REG_CONFIG = C_R_REGISTER == 8 ? // "Automatic" reg-slice (C_RANGE_CHECK ? ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHTWT : P_FULLY_REG) : P_BYPASS) : // Bypass if no R-channel mux C_R_REGISTER; localparam P_DECERR = 2'b11; //--------------------------------------------------------------------------- // Functions //--------------------------------------------------------------------------- // Ceiling of log2(x) function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2**acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value // only for end-point SI-slots function [C_AXI_ID_WIDTH-1:0] f_extend_ID ( input [C_AXI_ID_WIDTH-1:0] s_id, input integer slot ); begin f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH])); end endfunction // Convert Bit32 vector of range [0,1] to Bit1 vector on MI function [C_NUM_MASTER_SLOTS-1:0] f_bit32to1_mi (input [C_NUM_MASTER_SLOTS*32-1:0] vec32); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_bit32to1_mi[mi] = vec32[mi*32]; end end endfunction // AxiLite error-checking mask (on MI) function [C_NUM_MASTER_SLOTS-1:0] f_m_axilite ( input integer null_arg ); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_m_axilite[mi] = (C_M_AXI_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE); end end endfunction genvar gen_si_slot; genvar gen_mi_slot; wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0] si_awmesg ; wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0] si_armesg ; wire [P_AMESG_WIDTH-1:0] aa_amesg ; wire [C_AXI_ID_WIDTH-1:0] mi_aid ; wire [C_AXI_ADDR_WIDTH-1:0] mi_aaddr ; wire [8-1:0] mi_alen ; wire [3-1:0] mi_asize ; wire [2-1:0] mi_alock ; wire [3-1:0] mi_aprot ; wire [2-1:0] mi_aburst ; wire [4-1:0] mi_acache ; wire [4-1:0] mi_aregion ; wire [4-1:0] mi_aqos ; wire [P_AXI_AUSER_WIDTH-1:0] mi_auser ; wire [4-1:0] target_region ; wire [C_NUM_SLAVE_SLOTS*1-1:0] aa_grant_hot ; wire [P_NUM_SLAVE_SLOTS_LOG-1:0] aa_grant_enc ; wire aa_grant_rnw ; wire aa_grant_any ; wire [C_NUM_MASTER_SLOTS-1:0] target_mi_hot ; wire [P_NUM_MASTER_SLOTS_LOG-1:0] target_mi_enc ; reg [P_NUM_MASTER_SLOTS_DE-1:0] m_atarget_hot ; reg [P_NUM_MASTER_SLOTS_DE_LOG-1:0] m_atarget_enc ; wire [P_NUM_MASTER_SLOTS_DE_LOG-1:0] m_atarget_enc_comb ; wire match; wire any_error ; wire [7:0] m_aerror_i ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_awvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_awready ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_arvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_arready ; wire aa_awvalid ; wire aa_awready ; wire aa_arvalid ; wire aa_arready ; wire mi_awvalid_en; wire mi_awready_mux; wire mi_arvalid_en; wire mi_arready_mux; wire w_transfer_en; wire w_complete_mux; wire b_transfer_en; wire b_complete_mux; wire r_transfer_en; wire r_complete_mux; wire target_secure; wire target_write; wire target_read; wire target_axilite; wire [P_BMESG_WIDTH-1:0] si_bmesg ; wire [P_NUM_MASTER_SLOTS_DE*P_BMESG_WIDTH-1:0] mi_bmesg ; wire [P_NUM_MASTER_SLOTS_DE*2-1:0] mi_bresp ; wire [P_NUM_MASTER_SLOTS_DE*C_AXI_BUSER_WIDTH-1:0] mi_buser ; wire [2-1:0] si_bresp ; wire [C_AXI_BUSER_WIDTH-1:0] si_buser ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_bvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_bready ; wire aa_bvalid ; wire aa_bready ; wire si_bready ; wire [C_NUM_SLAVE_SLOTS-1:0] si_bvalid; wire [P_RMESG_WIDTH-1:0] aa_rmesg ; wire [P_RMESG_WIDTH-1:0] sr_rmesg ; wire [P_NUM_MASTER_SLOTS_DE*P_RMESG_WIDTH-1:0] mi_rmesg ; wire [P_NUM_MASTER_SLOTS_DE*2-1:0] mi_rresp ; wire [P_NUM_MASTER_SLOTS_DE*C_AXI_RUSER_WIDTH-1:0] mi_ruser ; wire [P_NUM_MASTER_SLOTS_DE*C_AXI_DATA_WIDTH-1:0] mi_rdata ; wire [P_NUM_MASTER_SLOTS_DE*1-1:0] mi_rlast ; wire [2-1:0] si_rresp ; wire [C_AXI_RUSER_WIDTH-1:0] si_ruser ; wire [C_AXI_DATA_WIDTH-1:0] si_rdata ; wire si_rlast ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_rvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_rready ; wire aa_rvalid ; wire aa_rready ; wire sr_rvalid ; wire si_rready ; wire sr_rready ; wire [C_NUM_SLAVE_SLOTS-1:0] si_rvalid; wire [C_NUM_SLAVE_SLOTS*P_WMESG_WIDTH-1:0] si_wmesg ; wire [P_WMESG_WIDTH-1:0] mi_wmesg ; wire [C_AXI_ID_WIDTH-1:0] mi_wid ; wire [C_AXI_DATA_WIDTH-1:0] mi_wdata ; wire [C_AXI_DATA_WIDTH/8-1:0] mi_wstrb ; wire [C_AXI_WUSER_WIDTH-1:0] mi_wuser ; wire [1-1:0] mi_wlast ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_wvalid ; wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_wready ; wire aa_wvalid ; wire aa_wready ; wire [C_NUM_SLAVE_SLOTS-1:0] si_wready; reg [7:0] debug_r_beat_cnt_i; reg [7:0] debug_w_beat_cnt_i; reg [7:0] debug_aw_trans_seq_i; reg [7:0] debug_ar_trans_seq_i; reg aresetn_d = 1'b0; // Reset delay register always @(posedge ACLK) begin if (~ARESETN) begin aresetn_d <= 1'b0; end else begin aresetn_d <= ARESETN; end end wire reset; assign reset = ~aresetn_d; generate axi_crossbar_v2_1_addr_arbiter_sasd # ( .C_FAMILY (C_FAMILY), .C_NUM_S (C_NUM_SLAVE_SLOTS), .C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG), .C_AMESG_WIDTH (P_AMESG_WIDTH), .C_GRANT_ENC (1), .C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY) ) addr_arbiter_inst ( .ACLK (ACLK), .ARESET (reset), // Vector of SI-side AW command request inputs .S_AWMESG (si_awmesg), .S_ARMESG (si_armesg), .S_AWVALID (S_AXI_AWVALID), .S_AWREADY (S_AXI_AWREADY), .S_ARVALID (S_AXI_ARVALID), .S_ARREADY (S_AXI_ARREADY), .M_GRANT_ENC (aa_grant_enc), .M_GRANT_HOT (aa_grant_hot), // SI-slot 1-hot mask of granted command .M_GRANT_ANY (aa_grant_any), .M_GRANT_RNW (aa_grant_rnw), .M_AMESG (aa_amesg), // Either S_AWMESG or S_ARMESG, as indicated by M_AWVALID and M_ARVALID. .M_AWVALID (aa_awvalid), .M_AWREADY (aa_awready), .M_ARVALID (aa_arvalid), .M_ARREADY (aa_arready) ); if (C_ADDR_DECODE) begin : gen_addr_decoder axi_crossbar_v2_1_addr_decoder # ( .C_FAMILY (C_FAMILY), .C_NUM_TARGETS (C_NUM_MASTER_SLOTS), .C_NUM_TARGETS_LOG (P_NUM_MASTER_SLOTS_LOG), .C_NUM_RANGES (C_NUM_ADDR_RANGES), .C_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_TARGET_ENC (1), .C_TARGET_HOT (1), .C_REGION_ENC (1), .C_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_HIGH_ADDR (C_M_AXI_HIGH_ADDR), .C_TARGET_QUAL ({C_NUM_MASTER_SLOTS{1'b1}}), .C_RESOLUTION (2) ) addr_decoder_inst ( .ADDR (mi_aaddr), .TARGET_HOT (target_mi_hot), .TARGET_ENC (target_mi_enc), .MATCH (match), .REGION (target_region) ); end else begin : gen_no_addr_decoder assign target_mi_hot = 1; assign match = 1'b1; assign target_region = 4'b0000; end // gen_addr_decoder // AW-channel arbiter command transfer completes upon completion of both M-side AW-channel transfer and B channel completion. axi_crossbar_v2_1_splitter # ( .C_NUM_M (3) ) splitter_aw ( .ACLK (ACLK), .ARESET (reset), .S_VALID (aa_awvalid), .S_READY (aa_awready), .M_VALID ({mi_awvalid_en, w_transfer_en, b_transfer_en}), .M_READY ({mi_awready_mux, w_complete_mux, b_complete_mux}) ); // AR-channel arbiter command transfer completes upon completion of both M-side AR-channel transfer and R channel completion. axi_crossbar_v2_1_splitter # ( .C_NUM_M (2) ) splitter_ar ( .ACLK (ACLK), .ARESET (reset), .S_VALID (aa_arvalid), .S_READY (aa_arready), .M_VALID ({mi_arvalid_en, r_transfer_en}), .M_READY ({mi_arready_mux, r_complete_mux}) ); assign target_secure = |(target_mi_hot & P_M_SECURE_MASK); assign target_write = |(target_mi_hot & C_M_AXI_SUPPORTS_WRITE); assign target_read = |(target_mi_hot & C_M_AXI_SUPPORTS_READ); assign target_axilite = |(target_mi_hot & P_M_AXILITE_MASK); assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition. assign m_aerror_i[0] = ~match; // Invalid target address assign m_aerror_i[1] = target_secure && mi_aprot[P_NONSECURE_BIT]; // TrustZone violation assign m_aerror_i[2] = target_axilite && ((mi_alen != 0) || (mi_asize[1:0] == 2'b11) || (mi_asize[2] == 1'b1)); // AxiLite access violation assign m_aerror_i[3] = (~aa_grant_rnw && ~target_write) || (aa_grant_rnw && ~target_read); // R/W direction unsupported by target assign m_aerror_i[7:4] = 4'b0000; // Reserved assign m_atarget_enc_comb = any_error ? (P_NUM_MASTER_SLOTS_DE-1) : target_mi_enc; // Select MI slot or decerr_slave always @(posedge ACLK) begin if (reset) begin m_atarget_hot <= 0; m_atarget_enc <= 0; end else begin m_atarget_hot <= {P_NUM_MASTER_SLOTS_DE{aa_grant_any}} & (any_error ? {1'b1, {C_NUM_MASTER_SLOTS{1'b0}}} : {1'b0, target_mi_hot}); // Select MI slot or decerr_slave m_atarget_enc <= m_atarget_enc_comb; end end // Receive AWREADY from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_awready_mux_inst ( .S (m_atarget_enc), .A (mi_awready), .O (mi_awready_mux), .OE (mi_awvalid_en) ); // Receive ARREADY from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_arready_mux_inst ( .S (m_atarget_enc), .A (mi_arready), .O (mi_arready_mux), .OE (mi_arvalid_en) ); assign mi_awvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_awvalid_en}}; // Assert AWVALID on targeted MI. assign mi_arvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_arvalid_en}}; // Assert ARVALID on targeted MI. assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS]; // Propagate to MI slots. assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS]; // Propagate to MI slots. assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY; // Copy from MI slots. assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY; // Copy from MI slots. // Receive WREADY from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_wready_mux_inst ( .S (m_atarget_enc), .A (mi_wready), .O (aa_wready), .OE (w_transfer_en) ); assign mi_wvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_wvalid}}; // Assert WVALID on targeted MI. assign si_wready = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_wready}}; // Assert WREADY on granted SI. assign S_AXI_WREADY = si_wready; assign w_complete_mux = aa_wready & aa_wvalid & mi_wlast; // W burst complete on on designated SI/MI. // Receive RREADY from granted SI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_DATA_WIDTH (1) ) si_rready_mux_inst ( .S (aa_grant_enc), .A (S_AXI_RREADY), .O (si_rready), .OE (r_transfer_en) ); assign sr_rready = si_rready & r_transfer_en; assign mi_rready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_rready}}; // Assert RREADY on targeted MI. assign si_rvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{sr_rvalid}}; // Assert RVALID on granted SI. assign S_AXI_RVALID = si_rvalid; assign r_complete_mux = sr_rready & sr_rvalid & si_rlast; // R burst complete on on designated SI/MI. // Receive BREADY from granted SI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_DATA_WIDTH (1) ) si_bready_mux_inst ( .S (aa_grant_enc), .A (S_AXI_BREADY), .O (si_bready), .OE (b_transfer_en) ); assign aa_bready = si_bready & b_transfer_en; assign mi_bready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_bready}}; // Assert BREADY on targeted MI. assign si_bvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_bvalid}}; // Assert BVALID on granted SI. assign S_AXI_BVALID = si_bvalid; assign b_complete_mux = aa_bready & aa_bvalid; // B transfer complete on on designated SI/MI. for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_si_amesg assign si_armesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = { // Concatenate from MSB to LSB 4'b0000, // S_AXI_ARREGION[gen_si_slot*4+:4], S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH +: C_AXI_ARUSER_WIDTH], S_AXI_ARQOS[gen_si_slot*4+:4], S_AXI_ARCACHE[gen_si_slot*4+:4], S_AXI_ARBURST[gen_si_slot*2+:2], S_AXI_ARPROT[gen_si_slot*3+:3], S_AXI_ARLOCK[gen_si_slot*2+:2], S_AXI_ARSIZE[gen_si_slot*3+:3], S_AXI_ARLEN[gen_si_slot*8+:8], S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH], f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH +: C_AXI_ID_WIDTH], gen_si_slot) }; assign si_awmesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = { // Concatenate from MSB to LSB 4'b0000, // S_AXI_AWREGION[gen_si_slot*4+:4], S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH +: C_AXI_AWUSER_WIDTH], S_AXI_AWQOS[gen_si_slot*4+:4], S_AXI_AWCACHE[gen_si_slot*4+:4], S_AXI_AWBURST[gen_si_slot*2+:2], S_AXI_AWPROT[gen_si_slot*3+:3], S_AXI_AWLOCK[gen_si_slot*2+:2], S_AXI_AWSIZE[gen_si_slot*3+:3], S_AXI_AWLEN[gen_si_slot*8+:8], S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH], f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) }; end // gen_si_amesg assign mi_aid = aa_amesg[0 +: C_AXI_ID_WIDTH]; assign mi_aaddr = aa_amesg[C_AXI_ID_WIDTH +: C_AXI_ADDR_WIDTH]; assign mi_alen = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +: 8]; assign mi_asize = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +: 3]; assign mi_alock = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +: 2]; assign mi_aprot = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +: 3]; assign mi_aburst = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +: 2]; assign mi_acache = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2 +: 4]; assign mi_aqos = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4 +: 4]; assign mi_auser = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4 +: P_AXI_AUSER_WIDTH]; assign mi_aregion = (C_ADDR_DECODE != 0) ? target_region : aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4+P_AXI_AUSER_WIDTH +: 4]; // Broadcast AW transfer payload to all MI-slots assign M_AXI_AWID = {C_NUM_MASTER_SLOTS{mi_aid}}; assign M_AXI_AWADDR = {C_NUM_MASTER_SLOTS{mi_aaddr}}; assign M_AXI_AWLEN = {C_NUM_MASTER_SLOTS{mi_alen }}; assign M_AXI_AWSIZE = {C_NUM_MASTER_SLOTS{mi_asize}}; assign M_AXI_AWLOCK = {C_NUM_MASTER_SLOTS{mi_alock}}; assign M_AXI_AWPROT = {C_NUM_MASTER_SLOTS{mi_aprot}}; assign M_AXI_AWREGION = {C_NUM_MASTER_SLOTS{mi_aregion}}; assign M_AXI_AWBURST = {C_NUM_MASTER_SLOTS{mi_aburst}}; assign M_AXI_AWCACHE = {C_NUM_MASTER_SLOTS{mi_acache}}; assign M_AXI_AWQOS = {C_NUM_MASTER_SLOTS{mi_aqos }}; assign M_AXI_AWUSER = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_AWUSER_WIDTH] }}; // Broadcast AR transfer payload to all MI-slots assign M_AXI_ARID = {C_NUM_MASTER_SLOTS{mi_aid}}; assign M_AXI_ARADDR = {C_NUM_MASTER_SLOTS{mi_aaddr}}; assign M_AXI_ARLEN = {C_NUM_MASTER_SLOTS{mi_alen }}; assign M_AXI_ARSIZE = {C_NUM_MASTER_SLOTS{mi_asize}}; assign M_AXI_ARLOCK = {C_NUM_MASTER_SLOTS{mi_alock}}; assign M_AXI_ARPROT = {C_NUM_MASTER_SLOTS{mi_aprot}}; assign M_AXI_ARREGION = {C_NUM_MASTER_SLOTS{mi_aregion}}; assign M_AXI_ARBURST = {C_NUM_MASTER_SLOTS{mi_aburst}}; assign M_AXI_ARCACHE = {C_NUM_MASTER_SLOTS{mi_acache}}; assign M_AXI_ARQOS = {C_NUM_MASTER_SLOTS{mi_aqos }}; assign M_AXI_ARUSER = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_ARUSER_WIDTH] }}; // W-channel MI handshakes assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS]; assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY; // Broadcast W transfer payload to all MI-slots assign M_AXI_WLAST = {C_NUM_MASTER_SLOTS{mi_wlast}}; assign M_AXI_WUSER = {C_NUM_MASTER_SLOTS{mi_wuser}}; assign M_AXI_WDATA = {C_NUM_MASTER_SLOTS{mi_wdata}}; assign M_AXI_WSTRB = {C_NUM_MASTER_SLOTS{mi_wstrb}}; assign M_AXI_WID = {C_NUM_MASTER_SLOTS{mi_wid}}; // Broadcast R transfer payload to all SI-slots assign S_AXI_RLAST = {C_NUM_SLAVE_SLOTS{si_rlast}}; assign S_AXI_RRESP = {C_NUM_SLAVE_SLOTS{si_rresp}}; assign S_AXI_RUSER = {C_NUM_SLAVE_SLOTS{si_ruser}}; assign S_AXI_RDATA = {C_NUM_SLAVE_SLOTS{si_rdata}}; assign S_AXI_RID = {C_NUM_SLAVE_SLOTS{mi_aid}}; // Broadcast B transfer payload to all SI-slots assign S_AXI_BRESP = {C_NUM_SLAVE_SLOTS{si_bresp}}; assign S_AXI_BUSER = {C_NUM_SLAVE_SLOTS{si_buser}}; assign S_AXI_BID = {C_NUM_SLAVE_SLOTS{mi_aid}}; if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux // SI WVALID mux. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_DATA_WIDTH (1) ) si_w_valid_mux_inst ( .S (aa_grant_enc), .A (S_AXI_WVALID), .O (aa_wvalid), .OE (w_transfer_en) ); // SI W-channel payload mux generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG), .C_DATA_WIDTH (P_WMESG_WIDTH) ) si_w_payload_mux_inst ( .S (aa_grant_enc), .A (si_wmesg), .O (mi_wmesg), .OE (1'b1) ); for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_wmesg assign si_wmesg[gen_si_slot*P_WMESG_WIDTH+:P_WMESG_WIDTH] = { // Concatenate from MSB to LSB ((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0), S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH], S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8], S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH], S_AXI_WLAST[gen_si_slot*1+:1] }; end // gen_wmesg assign mi_wlast = mi_wmesg[0]; assign mi_wdata = mi_wmesg[1 +: C_AXI_DATA_WIDTH]; assign mi_wstrb = mi_wmesg[1+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8]; assign mi_wuser = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH]; assign mi_wid = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH]; end else begin : gen_no_wmux assign aa_wvalid = w_transfer_en & S_AXI_WVALID; assign mi_wlast = S_AXI_WLAST; assign mi_wdata = S_AXI_WDATA; assign mi_wstrb = S_AXI_WSTRB; assign mi_wuser = S_AXI_WUSER; assign mi_wid = S_AXI_WID; end // gen_wmux // Receive RVALID from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_rvalid_mux_inst ( .S (m_atarget_enc), .A (mi_rvalid), .O (aa_rvalid), .OE (r_transfer_en) ); // MI R-channel payload mux generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (P_RMESG_WIDTH) ) mi_rmesg_mux_inst ( .S (m_atarget_enc), .A (mi_rmesg), .O (aa_rmesg), .OE (1'b1) ); axi_register_slice_v2_1_axic_register_slice # ( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (P_RMESG_WIDTH), .C_REG_CONFIG (P_R_REG_CONFIG) ) reg_slice_r ( // System Signals .ACLK(ACLK), .ARESET(reset), // Slave side .S_PAYLOAD_DATA(aa_rmesg), .S_VALID(aa_rvalid), .S_READY(aa_rready), // Master side .M_PAYLOAD_DATA(sr_rmesg), .M_VALID(sr_rvalid), .M_READY(sr_rready) ); assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID; assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST; assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP; assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER; assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA; assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS]; for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_rmesg assign mi_rmesg[gen_mi_slot*P_RMESG_WIDTH+:P_RMESG_WIDTH] = { // Concatenate from MSB to LSB mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH], mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH], mi_rresp[gen_mi_slot*2+:2], mi_rlast[gen_mi_slot*1+:1] }; end // gen_rmesg assign si_rlast = sr_rmesg[0]; assign si_rresp = sr_rmesg[1 +: 2]; assign si_rdata = sr_rmesg[1+2 +: C_AXI_DATA_WIDTH]; assign si_ruser = sr_rmesg[1+2+C_AXI_DATA_WIDTH +: C_AXI_RUSER_WIDTH]; // Receive BVALID from targeted MI. generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (1) ) mi_bvalid_mux_inst ( .S (m_atarget_enc), .A (mi_bvalid), .O (aa_bvalid), .OE (b_transfer_en) ); // MI B-channel payload mux generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (P_NUM_MASTER_SLOTS_DE), .C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG), .C_DATA_WIDTH (P_BMESG_WIDTH) ) mi_bmesg_mux_inst ( .S (m_atarget_enc), .A (mi_bmesg), .O (si_bmesg), .OE (1'b1) ); assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID; assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP; assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER; assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS]; for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_bmesg assign mi_bmesg[gen_mi_slot*P_BMESG_WIDTH+:P_BMESG_WIDTH] = { // Concatenate from MSB to LSB mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH], mi_bresp[gen_mi_slot*2+:2] }; end // gen_bmesg assign si_bresp = si_bmesg[0 +: 2]; assign si_buser = si_bmesg[2 +: C_AXI_BUSER_WIDTH]; if (C_DEBUG) begin : gen_debug_trans_seq // DEBUG WRITE TRANSACTION SEQUENCE COUNTER always @(posedge ACLK) begin if (reset) begin debug_aw_trans_seq_i <= 1; end else begin if (aa_awvalid && aa_awready) begin debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1; end end end // DEBUG READ TRANSACTION SEQUENCE COUNTER always @(posedge ACLK) begin if (reset) begin debug_ar_trans_seq_i <= 1; end else begin if (aa_arvalid && aa_arready) begin debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1; end end end // DEBUG WRITE BEAT COUNTER always @(posedge ACLK) begin if (reset) begin debug_w_beat_cnt_i <= 0; end else if (aa_wready & aa_wvalid) begin if (mi_wlast) begin debug_w_beat_cnt_i <= 0; end else begin debug_w_beat_cnt_i <= debug_w_beat_cnt_i + 1; end end end // Clocked process // DEBUG READ BEAT COUNTER always @(posedge ACLK) begin if (reset) begin debug_r_beat_cnt_i <= 0; end else if (sr_rready & sr_rvalid) begin if (si_rlast) begin debug_r_beat_cnt_i <= 0; end else begin debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1; end end end // Clocked process end // gen_debug_trans_seq if (C_RANGE_CHECK) begin : gen_decerr // Highest MI-slot (index C_NUM_MASTER_SLOTS) is the error handler axi_crossbar_v2_1_decerr_slave # ( .C_AXI_ID_WIDTH (1), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_RESP (P_DECERR) ) decerr_slave_inst ( .S_AXI_ACLK (ACLK), .S_AXI_ARESET (reset), .S_AXI_AWID (1'b0), .S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]), .S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]), .S_AXI_WLAST (mi_wlast), .S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]), .S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]), .S_AXI_BID (), .S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]), .S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]), .S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]), .S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]), .S_AXI_ARID (1'b0), .S_AXI_ARLEN (mi_alen), .S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]), .S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]), .S_AXI_RID (), .S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]), .S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]), .S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]), .S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]), .S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]), .S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS]) ); end // gen_decerr endgenerate endmodule `default_nettype wire
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_arb_hp2_3.v * * Date : 2012-11 * * Description : Module that arbitrates between RD/WR requests from 2 ports. * Used for modelling the Top_Interconnect switch. *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_arb_hp2_3( sw_clk, rstn, w_qos_hp2, r_qos_hp2, w_qos_hp3, r_qos_hp3, wr_ack_ddr_hp2, wr_data_hp2, wr_addr_hp2, wr_bytes_hp2, wr_dv_ddr_hp2, rd_req_ddr_hp2, rd_addr_hp2, rd_bytes_hp2, rd_data_ddr_hp2, rd_dv_ddr_hp2, wr_ack_ddr_hp3, wr_data_hp3, wr_addr_hp3, wr_bytes_hp3, wr_dv_ddr_hp3, rd_req_ddr_hp3, rd_addr_hp3, rd_bytes_hp3, rd_data_ddr_hp3, rd_dv_ddr_hp3, ddr_wr_ack, ddr_wr_dv, ddr_rd_req, ddr_rd_dv, ddr_rd_qos, ddr_wr_qos, ddr_wr_addr, ddr_wr_data, ddr_wr_bytes, ddr_rd_addr, ddr_rd_data, ddr_rd_bytes ); `include "processing_system7_bfm_v2_0_5_local_params.v" input sw_clk; input rstn; input [axi_qos_width-1:0] w_qos_hp2; input [axi_qos_width-1:0] r_qos_hp2; input [axi_qos_width-1:0] w_qos_hp3; input [axi_qos_width-1:0] r_qos_hp3; input [axi_qos_width-1:0] ddr_rd_qos; input [axi_qos_width-1:0] ddr_wr_qos; output wr_ack_ddr_hp2; input [max_burst_bits-1:0] wr_data_hp2; input [addr_width-1:0] wr_addr_hp2; input [max_burst_bytes_width:0] wr_bytes_hp2; output wr_dv_ddr_hp2; input rd_req_ddr_hp2; input [addr_width-1:0] rd_addr_hp2; input [max_burst_bytes_width:0] rd_bytes_hp2; output [max_burst_bits-1:0] rd_data_ddr_hp2; output rd_dv_ddr_hp2; output wr_ack_ddr_hp3; input [max_burst_bits-1:0] wr_data_hp3; input [addr_width-1:0] wr_addr_hp3; input [max_burst_bytes_width:0] wr_bytes_hp3; output wr_dv_ddr_hp3; input rd_req_ddr_hp3; input [addr_width-1:0] rd_addr_hp3; input [max_burst_bytes_width:0] rd_bytes_hp3; output [max_burst_bits-1:0] rd_data_ddr_hp3; output rd_dv_ddr_hp3; input ddr_wr_ack; output ddr_wr_dv; output [addr_width-1:0]ddr_wr_addr; output [max_burst_bits-1:0]ddr_wr_data; output [max_burst_bytes_width:0]ddr_wr_bytes; input ddr_rd_dv; input [max_burst_bits-1:0] ddr_rd_data; output ddr_rd_req; output [addr_width-1:0] ddr_rd_addr; output [max_burst_bytes_width:0] ddr_rd_bytes; processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr( .rstn(rstn), .sw_clk(sw_clk), .qos1(w_qos_hp2), .qos2(w_qos_hp3), .prt_dv1(wr_dv_ddr_hp2), .prt_dv2(wr_dv_ddr_hp3), .prt_data1(wr_data_hp2), .prt_data2(wr_data_hp3), .prt_addr1(wr_addr_hp2), .prt_addr2(wr_addr_hp3), .prt_bytes1(wr_bytes_hp2), .prt_bytes2(wr_bytes_hp3), .prt_ack1(wr_ack_ddr_hp2), .prt_ack2(wr_ack_ddr_hp3), .prt_req(ddr_wr_dv), .prt_qos(ddr_wr_qos), .prt_data(ddr_wr_data), .prt_addr(ddr_wr_addr), .prt_bytes(ddr_wr_bytes), .prt_ack(ddr_wr_ack) ); processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd( .rstn(rstn), .sw_clk(sw_clk), .qos1(r_qos_hp2), .qos2(r_qos_hp3), .prt_req1(rd_req_ddr_hp2), .prt_req2(rd_req_ddr_hp3), .prt_data1(rd_data_ddr_hp2), .prt_data2(rd_data_ddr_hp3), .prt_addr1(rd_addr_hp2), .prt_addr2(rd_addr_hp3), .prt_bytes1(rd_bytes_hp2), .prt_bytes2(rd_bytes_hp3), .prt_dv1(rd_dv_ddr_hp2), .prt_dv2(rd_dv_ddr_hp3), .prt_req(ddr_rd_req), .prt_qos(ddr_rd_qos), .prt_data(ddr_rd_data), .prt_addr(ddr_rd_addr), .prt_bytes(ddr_rd_bytes), .prt_dv(ddr_rd_dv) ); endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_arb_hp2_3.v * * Date : 2012-11 * * Description : Module that arbitrates between RD/WR requests from 2 ports. * Used for modelling the Top_Interconnect switch. *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_arb_hp2_3( sw_clk, rstn, w_qos_hp2, r_qos_hp2, w_qos_hp3, r_qos_hp3, wr_ack_ddr_hp2, wr_data_hp2, wr_addr_hp2, wr_bytes_hp2, wr_dv_ddr_hp2, rd_req_ddr_hp2, rd_addr_hp2, rd_bytes_hp2, rd_data_ddr_hp2, rd_dv_ddr_hp2, wr_ack_ddr_hp3, wr_data_hp3, wr_addr_hp3, wr_bytes_hp3, wr_dv_ddr_hp3, rd_req_ddr_hp3, rd_addr_hp3, rd_bytes_hp3, rd_data_ddr_hp3, rd_dv_ddr_hp3, ddr_wr_ack, ddr_wr_dv, ddr_rd_req, ddr_rd_dv, ddr_rd_qos, ddr_wr_qos, ddr_wr_addr, ddr_wr_data, ddr_wr_bytes, ddr_rd_addr, ddr_rd_data, ddr_rd_bytes ); `include "processing_system7_bfm_v2_0_5_local_params.v" input sw_clk; input rstn; input [axi_qos_width-1:0] w_qos_hp2; input [axi_qos_width-1:0] r_qos_hp2; input [axi_qos_width-1:0] w_qos_hp3; input [axi_qos_width-1:0] r_qos_hp3; input [axi_qos_width-1:0] ddr_rd_qos; input [axi_qos_width-1:0] ddr_wr_qos; output wr_ack_ddr_hp2; input [max_burst_bits-1:0] wr_data_hp2; input [addr_width-1:0] wr_addr_hp2; input [max_burst_bytes_width:0] wr_bytes_hp2; output wr_dv_ddr_hp2; input rd_req_ddr_hp2; input [addr_width-1:0] rd_addr_hp2; input [max_burst_bytes_width:0] rd_bytes_hp2; output [max_burst_bits-1:0] rd_data_ddr_hp2; output rd_dv_ddr_hp2; output wr_ack_ddr_hp3; input [max_burst_bits-1:0] wr_data_hp3; input [addr_width-1:0] wr_addr_hp3; input [max_burst_bytes_width:0] wr_bytes_hp3; output wr_dv_ddr_hp3; input rd_req_ddr_hp3; input [addr_width-1:0] rd_addr_hp3; input [max_burst_bytes_width:0] rd_bytes_hp3; output [max_burst_bits-1:0] rd_data_ddr_hp3; output rd_dv_ddr_hp3; input ddr_wr_ack; output ddr_wr_dv; output [addr_width-1:0]ddr_wr_addr; output [max_burst_bits-1:0]ddr_wr_data; output [max_burst_bytes_width:0]ddr_wr_bytes; input ddr_rd_dv; input [max_burst_bits-1:0] ddr_rd_data; output ddr_rd_req; output [addr_width-1:0] ddr_rd_addr; output [max_burst_bytes_width:0] ddr_rd_bytes; processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr( .rstn(rstn), .sw_clk(sw_clk), .qos1(w_qos_hp2), .qos2(w_qos_hp3), .prt_dv1(wr_dv_ddr_hp2), .prt_dv2(wr_dv_ddr_hp3), .prt_data1(wr_data_hp2), .prt_data2(wr_data_hp3), .prt_addr1(wr_addr_hp2), .prt_addr2(wr_addr_hp3), .prt_bytes1(wr_bytes_hp2), .prt_bytes2(wr_bytes_hp3), .prt_ack1(wr_ack_ddr_hp2), .prt_ack2(wr_ack_ddr_hp3), .prt_req(ddr_wr_dv), .prt_qos(ddr_wr_qos), .prt_data(ddr_wr_data), .prt_addr(ddr_wr_addr), .prt_bytes(ddr_wr_bytes), .prt_ack(ddr_wr_ack) ); processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd( .rstn(rstn), .sw_clk(sw_clk), .qos1(r_qos_hp2), .qos2(r_qos_hp3), .prt_req1(rd_req_ddr_hp2), .prt_req2(rd_req_ddr_hp3), .prt_data1(rd_data_ddr_hp2), .prt_data2(rd_data_ddr_hp3), .prt_addr1(rd_addr_hp2), .prt_addr2(rd_addr_hp3), .prt_bytes1(rd_bytes_hp2), .prt_bytes2(rd_bytes_hp3), .prt_dv1(rd_dv_ddr_hp2), .prt_dv2(rd_dv_ddr_hp3), .prt_req(ddr_rd_req), .prt_qos(ddr_rd_qos), .prt_data(ddr_rd_data), .prt_addr(ddr_rd_addr), .prt_bytes(ddr_rd_bytes), .prt_dv(ddr_rd_dv) ); endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_gen_clock.v * * Date : 2012-11 * * Description : Module that generates FCLK clocks and internal clock for Zynq BFM. * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_gen_clock( ps_clk, sw_clk, fclk_clk3, fclk_clk2, fclk_clk1, fclk_clk0 ); input ps_clk; output sw_clk; output fclk_clk3; output fclk_clk2; output fclk_clk1; output fclk_clk0; parameter freq_clk3 = 50; parameter freq_clk2 = 50; parameter freq_clk1 = 50; parameter freq_clk0 = 50; reg clk0 = 1'b0; reg clk1 = 1'b0; reg clk2 = 1'b0; reg clk3 = 1'b0; reg sw_clk = 1'b0; assign fclk_clk0 = clk0; assign fclk_clk1 = clk1; assign fclk_clk2 = clk2; assign fclk_clk3 = clk3; real clk3_p = (1000.00/freq_clk3)/2; real clk2_p = (1000.00/freq_clk2)/2; real clk1_p = (1000.00/freq_clk1)/2; real clk0_p = (1000.00/freq_clk0)/2; always #(clk3_p) clk3 = !clk3; always #(clk2_p) clk2 = !clk2; always #(clk1_p) clk1 = !clk1; always #(clk0_p) clk0 = !clk0; always #(0.5) sw_clk = !sw_clk; endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_gen_clock.v * * Date : 2012-11 * * Description : Module that generates FCLK clocks and internal clock for Zynq BFM. * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_gen_clock( ps_clk, sw_clk, fclk_clk3, fclk_clk2, fclk_clk1, fclk_clk0 ); input ps_clk; output sw_clk; output fclk_clk3; output fclk_clk2; output fclk_clk1; output fclk_clk0; parameter freq_clk3 = 50; parameter freq_clk2 = 50; parameter freq_clk1 = 50; parameter freq_clk0 = 50; reg clk0 = 1'b0; reg clk1 = 1'b0; reg clk2 = 1'b0; reg clk3 = 1'b0; reg sw_clk = 1'b0; assign fclk_clk0 = clk0; assign fclk_clk1 = clk1; assign fclk_clk2 = clk2; assign fclk_clk3 = clk3; real clk3_p = (1000.00/freq_clk3)/2; real clk2_p = (1000.00/freq_clk2)/2; real clk1_p = (1000.00/freq_clk1)/2; real clk0_p = (1000.00/freq_clk0)/2; always #(clk3_p) clk3 = !clk3; always #(clk2_p) clk2 = !clk2; always #(clk1_p) clk1 = !clk1; always #(clk0_p) clk0 = !clk0; always #(0.5) sw_clk = !sw_clk; endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_ocmc.v * * Date : 2012-11 * * Description : Controller for OCM model * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_ocmc( rstn, sw_clk, /* Goes to port 0 of OCM */ ocm_wr_ack_port0, ocm_wr_dv_port0, ocm_rd_req_port0, ocm_rd_dv_port0, ocm_wr_addr_port0, ocm_wr_data_port0, ocm_wr_bytes_port0, ocm_rd_addr_port0, ocm_rd_data_port0, ocm_rd_bytes_port0, ocm_wr_qos_port0, ocm_rd_qos_port0, /* Goes to port 1 of OCM */ ocm_wr_ack_port1, ocm_wr_dv_port1, ocm_rd_req_port1, ocm_rd_dv_port1, ocm_wr_addr_port1, ocm_wr_data_port1, ocm_wr_bytes_port1, ocm_rd_addr_port1, ocm_rd_data_port1, ocm_rd_bytes_port1, ocm_wr_qos_port1, ocm_rd_qos_port1 ); `include "processing_system7_bfm_v2_0_5_local_params.v" input rstn; input sw_clk; output ocm_wr_ack_port0; input ocm_wr_dv_port0; input ocm_rd_req_port0; output ocm_rd_dv_port0; input[addr_width-1:0] ocm_wr_addr_port0; input[max_burst_bits-1:0] ocm_wr_data_port0; input[max_burst_bytes_width:0] ocm_wr_bytes_port0; input[addr_width-1:0] ocm_rd_addr_port0; output[max_burst_bits-1:0] ocm_rd_data_port0; input[max_burst_bytes_width:0] ocm_rd_bytes_port0; input [axi_qos_width-1:0] ocm_wr_qos_port0; input [axi_qos_width-1:0] ocm_rd_qos_port0; output ocm_wr_ack_port1; input ocm_wr_dv_port1; input ocm_rd_req_port1; output ocm_rd_dv_port1; input[addr_width-1:0] ocm_wr_addr_port1; input[max_burst_bits-1:0] ocm_wr_data_port1; input[max_burst_bytes_width:0] ocm_wr_bytes_port1; input[addr_width-1:0] ocm_rd_addr_port1; output[max_burst_bits-1:0] ocm_rd_data_port1; input[max_burst_bytes_width:0] ocm_rd_bytes_port1; input[axi_qos_width-1:0] ocm_wr_qos_port1; input[axi_qos_width-1:0] ocm_rd_qos_port1; wire [axi_qos_width-1:0] wr_qos; wire wr_req; wire [max_burst_bits-1:0] wr_data; wire [addr_width-1:0] wr_addr; wire [max_burst_bytes_width:0] wr_bytes; reg wr_ack; wire [axi_qos_width-1:0] rd_qos; reg [max_burst_bits-1:0] rd_data; wire [addr_width-1:0] rd_addr; wire [max_burst_bytes_width:0] rd_bytes; reg rd_dv; wire rd_req; processing_system7_bfm_v2_0_5_arb_wr ocm_write_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(ocm_wr_qos_port0), .qos2(ocm_wr_qos_port1), .prt_dv1(ocm_wr_dv_port0), .prt_dv2(ocm_wr_dv_port1), .prt_data1(ocm_wr_data_port0), .prt_data2(ocm_wr_data_port1), .prt_addr1(ocm_wr_addr_port0), .prt_addr2(ocm_wr_addr_port1), .prt_bytes1(ocm_wr_bytes_port0), .prt_bytes2(ocm_wr_bytes_port1), .prt_ack1(ocm_wr_ack_port0), .prt_ack2(ocm_wr_ack_port1), .prt_qos(wr_qos), .prt_req(wr_req), .prt_data(wr_data), .prt_addr(wr_addr), .prt_bytes(wr_bytes), .prt_ack(wr_ack) ); processing_system7_bfm_v2_0_5_arb_rd ocm_read_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(ocm_rd_qos_port0), .qos2(ocm_rd_qos_port1), .prt_req1(ocm_rd_req_port0), .prt_req2(ocm_rd_req_port1), .prt_data1(ocm_rd_data_port0), .prt_data2(ocm_rd_data_port1), .prt_addr1(ocm_rd_addr_port0), .prt_addr2(ocm_rd_addr_port1), .prt_bytes1(ocm_rd_bytes_port0), .prt_bytes2(ocm_rd_bytes_port1), .prt_dv1(ocm_rd_dv_port0), .prt_dv2(ocm_rd_dv_port1), .prt_qos(rd_qos), .prt_req(rd_req), .prt_data(rd_data), .prt_addr(rd_addr), .prt_bytes(rd_bytes), .prt_dv(rd_dv) ); processing_system7_bfm_v2_0_5_ocm_mem ocm(); reg [1:0] state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin wr_ack <= 0; rd_dv <= 0; state <= 2'd0; end else begin case(state) 0:begin state <= 0; wr_ack <= 0; rd_dv <= 0; if(wr_req) begin ocm.write_mem(wr_data , wr_addr, wr_bytes); wr_ack <= 1; state <= 1; end if(rd_req) begin ocm.read_mem(rd_data,rd_addr, rd_bytes); rd_dv <= 1; state <= 1; end end 1:begin wr_ack <= 0; rd_dv <= 0; state <= 0; end endcase end /// if end// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_ocmc.v * * Date : 2012-11 * * Description : Controller for OCM model * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_ocmc( rstn, sw_clk, /* Goes to port 0 of OCM */ ocm_wr_ack_port0, ocm_wr_dv_port0, ocm_rd_req_port0, ocm_rd_dv_port0, ocm_wr_addr_port0, ocm_wr_data_port0, ocm_wr_bytes_port0, ocm_rd_addr_port0, ocm_rd_data_port0, ocm_rd_bytes_port0, ocm_wr_qos_port0, ocm_rd_qos_port0, /* Goes to port 1 of OCM */ ocm_wr_ack_port1, ocm_wr_dv_port1, ocm_rd_req_port1, ocm_rd_dv_port1, ocm_wr_addr_port1, ocm_wr_data_port1, ocm_wr_bytes_port1, ocm_rd_addr_port1, ocm_rd_data_port1, ocm_rd_bytes_port1, ocm_wr_qos_port1, ocm_rd_qos_port1 ); `include "processing_system7_bfm_v2_0_5_local_params.v" input rstn; input sw_clk; output ocm_wr_ack_port0; input ocm_wr_dv_port0; input ocm_rd_req_port0; output ocm_rd_dv_port0; input[addr_width-1:0] ocm_wr_addr_port0; input[max_burst_bits-1:0] ocm_wr_data_port0; input[max_burst_bytes_width:0] ocm_wr_bytes_port0; input[addr_width-1:0] ocm_rd_addr_port0; output[max_burst_bits-1:0] ocm_rd_data_port0; input[max_burst_bytes_width:0] ocm_rd_bytes_port0; input [axi_qos_width-1:0] ocm_wr_qos_port0; input [axi_qos_width-1:0] ocm_rd_qos_port0; output ocm_wr_ack_port1; input ocm_wr_dv_port1; input ocm_rd_req_port1; output ocm_rd_dv_port1; input[addr_width-1:0] ocm_wr_addr_port1; input[max_burst_bits-1:0] ocm_wr_data_port1; input[max_burst_bytes_width:0] ocm_wr_bytes_port1; input[addr_width-1:0] ocm_rd_addr_port1; output[max_burst_bits-1:0] ocm_rd_data_port1; input[max_burst_bytes_width:0] ocm_rd_bytes_port1; input[axi_qos_width-1:0] ocm_wr_qos_port1; input[axi_qos_width-1:0] ocm_rd_qos_port1; wire [axi_qos_width-1:0] wr_qos; wire wr_req; wire [max_burst_bits-1:0] wr_data; wire [addr_width-1:0] wr_addr; wire [max_burst_bytes_width:0] wr_bytes; reg wr_ack; wire [axi_qos_width-1:0] rd_qos; reg [max_burst_bits-1:0] rd_data; wire [addr_width-1:0] rd_addr; wire [max_burst_bytes_width:0] rd_bytes; reg rd_dv; wire rd_req; processing_system7_bfm_v2_0_5_arb_wr ocm_write_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(ocm_wr_qos_port0), .qos2(ocm_wr_qos_port1), .prt_dv1(ocm_wr_dv_port0), .prt_dv2(ocm_wr_dv_port1), .prt_data1(ocm_wr_data_port0), .prt_data2(ocm_wr_data_port1), .prt_addr1(ocm_wr_addr_port0), .prt_addr2(ocm_wr_addr_port1), .prt_bytes1(ocm_wr_bytes_port0), .prt_bytes2(ocm_wr_bytes_port1), .prt_ack1(ocm_wr_ack_port0), .prt_ack2(ocm_wr_ack_port1), .prt_qos(wr_qos), .prt_req(wr_req), .prt_data(wr_data), .prt_addr(wr_addr), .prt_bytes(wr_bytes), .prt_ack(wr_ack) ); processing_system7_bfm_v2_0_5_arb_rd ocm_read_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(ocm_rd_qos_port0), .qos2(ocm_rd_qos_port1), .prt_req1(ocm_rd_req_port0), .prt_req2(ocm_rd_req_port1), .prt_data1(ocm_rd_data_port0), .prt_data2(ocm_rd_data_port1), .prt_addr1(ocm_rd_addr_port0), .prt_addr2(ocm_rd_addr_port1), .prt_bytes1(ocm_rd_bytes_port0), .prt_bytes2(ocm_rd_bytes_port1), .prt_dv1(ocm_rd_dv_port0), .prt_dv2(ocm_rd_dv_port1), .prt_qos(rd_qos), .prt_req(rd_req), .prt_data(rd_data), .prt_addr(rd_addr), .prt_bytes(rd_bytes), .prt_dv(rd_dv) ); processing_system7_bfm_v2_0_5_ocm_mem ocm(); reg [1:0] state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin wr_ack <= 0; rd_dv <= 0; state <= 2'd0; end else begin case(state) 0:begin state <= 0; wr_ack <= 0; rd_dv <= 0; if(wr_req) begin ocm.write_mem(wr_data , wr_addr, wr_bytes); wr_ack <= 1; state <= 1; end if(rd_req) begin ocm.read_mem(rd_data,rd_addr, rd_bytes); rd_dv <= 1; state <= 1; end end 1:begin wr_ack <= 0; rd_dv <= 0; state <= 0; end endcase end /// if end// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_fmsw_gp.v * * Date : 2012-11 * * Description : Mimics FMSW switch. * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_fmsw_gp( sw_clk, rstn, w_qos_gp0, r_qos_gp0, wr_ack_ocm_gp0, wr_ack_ddr_gp0, wr_data_gp0, wr_addr_gp0, wr_bytes_gp0, wr_dv_ocm_gp0, wr_dv_ddr_gp0, rd_req_ocm_gp0, rd_req_ddr_gp0, rd_req_reg_gp0, rd_addr_gp0, rd_bytes_gp0, rd_data_ocm_gp0, rd_data_ddr_gp0, rd_data_reg_gp0, rd_dv_ocm_gp0, rd_dv_ddr_gp0, rd_dv_reg_gp0, w_qos_gp1, r_qos_gp1, wr_ack_ocm_gp1, wr_ack_ddr_gp1, wr_data_gp1, wr_addr_gp1, wr_bytes_gp1, wr_dv_ocm_gp1, wr_dv_ddr_gp1, rd_req_ocm_gp1, rd_req_ddr_gp1, rd_req_reg_gp1, rd_addr_gp1, rd_bytes_gp1, rd_data_ocm_gp1, rd_data_ddr_gp1, rd_data_reg_gp1, rd_dv_ocm_gp1, rd_dv_ddr_gp1, rd_dv_reg_gp1, ocm_wr_ack, ocm_wr_dv, ocm_rd_req, ocm_rd_dv, ddr_wr_ack, ddr_wr_dv, ddr_rd_req, ddr_rd_dv, reg_rd_req, reg_rd_dv, ocm_wr_qos, ddr_wr_qos, ocm_rd_qos, ddr_rd_qos, reg_rd_qos, ocm_wr_addr, ocm_wr_data, ocm_wr_bytes, ocm_rd_addr, ocm_rd_data, ocm_rd_bytes, ddr_wr_addr, ddr_wr_data, ddr_wr_bytes, ddr_rd_addr, ddr_rd_data, ddr_rd_bytes, reg_rd_addr, reg_rd_data, reg_rd_bytes ); `include "processing_system7_bfm_v2_0_5_local_params.v" input sw_clk; input rstn; input [axi_qos_width-1:0]w_qos_gp0; input [axi_qos_width-1:0]r_qos_gp0; input [axi_qos_width-1:0]w_qos_gp1; input [axi_qos_width-1:0]r_qos_gp1; output [axi_qos_width-1:0]ocm_wr_qos; output [axi_qos_width-1:0]ocm_rd_qos; output [axi_qos_width-1:0]ddr_wr_qos; output [axi_qos_width-1:0]ddr_rd_qos; output [axi_qos_width-1:0]reg_rd_qos; output wr_ack_ocm_gp0; output wr_ack_ddr_gp0; input [max_burst_bits-1:0] wr_data_gp0; input [addr_width-1:0] wr_addr_gp0; input [max_burst_bytes_width:0] wr_bytes_gp0; output wr_dv_ocm_gp0; output wr_dv_ddr_gp0; input rd_req_ocm_gp0; input rd_req_ddr_gp0; input rd_req_reg_gp0; input [addr_width-1:0] rd_addr_gp0; input [max_burst_bytes_width:0] rd_bytes_gp0; output [max_burst_bits-1:0] rd_data_ocm_gp0; output [max_burst_bits-1:0] rd_data_ddr_gp0; output [max_burst_bits-1:0] rd_data_reg_gp0; output rd_dv_ocm_gp0; output rd_dv_ddr_gp0; output rd_dv_reg_gp0; output wr_ack_ocm_gp1; output wr_ack_ddr_gp1; input [max_burst_bits-1:0] wr_data_gp1; input [addr_width-1:0] wr_addr_gp1; input [max_burst_bytes_width:0] wr_bytes_gp1; output wr_dv_ocm_gp1; output wr_dv_ddr_gp1; input rd_req_ocm_gp1; input rd_req_ddr_gp1; input rd_req_reg_gp1; input [addr_width-1:0] rd_addr_gp1; input [max_burst_bytes_width:0] rd_bytes_gp1; output [max_burst_bits-1:0] rd_data_ocm_gp1; output [max_burst_bits-1:0] rd_data_ddr_gp1; output [max_burst_bits-1:0] rd_data_reg_gp1; output rd_dv_ocm_gp1; output rd_dv_ddr_gp1; output rd_dv_reg_gp1; input ocm_wr_ack; output ocm_wr_dv; output [addr_width-1:0]ocm_wr_addr; output [max_burst_bits-1:0]ocm_wr_data; output [max_burst_bytes_width:0]ocm_wr_bytes; input ocm_rd_dv; input [max_burst_bits-1:0] ocm_rd_data; output ocm_rd_req; output [addr_width-1:0] ocm_rd_addr; output [max_burst_bytes_width:0] ocm_rd_bytes; input ddr_wr_ack; output ddr_wr_dv; output [addr_width-1:0]ddr_wr_addr; output [max_burst_bits-1:0]ddr_wr_data; output [max_burst_bytes_width:0]ddr_wr_bytes; input ddr_rd_dv; input [max_burst_bits-1:0] ddr_rd_data; output ddr_rd_req; output [addr_width-1:0] ddr_rd_addr; output [max_burst_bytes_width:0] ddr_rd_bytes; input reg_rd_dv; input [max_burst_bits-1:0] reg_rd_data; output reg_rd_req; output [addr_width-1:0] reg_rd_addr; output [max_burst_bytes_width:0] reg_rd_bytes; processing_system7_bfm_v2_0_5_arb_wr ocm_gp_wr( .rstn(rstn), .sw_clk(sw_clk), .qos1(w_qos_gp0), .qos2(w_qos_gp1), .prt_dv1(wr_dv_ocm_gp0), .prt_dv2(wr_dv_ocm_gp1), .prt_data1(wr_data_gp0), .prt_data2(wr_data_gp1), .prt_addr1(wr_addr_gp0), .prt_addr2(wr_addr_gp1), .prt_bytes1(wr_bytes_gp0), .prt_bytes2(wr_bytes_gp1), .prt_ack1(wr_ack_ocm_gp0), .prt_ack2(wr_ack_ocm_gp1), .prt_req(ocm_wr_dv), .prt_qos(ocm_wr_qos), .prt_data(ocm_wr_data), .prt_addr(ocm_wr_addr), .prt_bytes(ocm_wr_bytes), .prt_ack(ocm_wr_ack) ); processing_system7_bfm_v2_0_5_arb_wr ddr_gp_wr( .rstn(rstn), .sw_clk(sw_clk), .qos1(w_qos_gp0), .qos2(w_qos_gp1), .prt_dv1(wr_dv_ddr_gp0), .prt_dv2(wr_dv_ddr_gp1), .prt_data1(wr_data_gp0), .prt_data2(wr_data_gp1), .prt_addr1(wr_addr_gp0), .prt_addr2(wr_addr_gp1), .prt_bytes1(wr_bytes_gp0), .prt_bytes2(wr_bytes_gp1), .prt_ack1(wr_ack_ddr_gp0), .prt_ack2(wr_ack_ddr_gp1), .prt_req(ddr_wr_dv), .prt_qos(ddr_wr_qos), .prt_data(ddr_wr_data), .prt_addr(ddr_wr_addr), .prt_bytes(ddr_wr_bytes), .prt_ack(ddr_wr_ack) ); processing_system7_bfm_v2_0_5_arb_rd ocm_gp_rd( .rstn(rstn), .sw_clk(sw_clk), .qos1(r_qos_gp0), .qos2(r_qos_gp1), .prt_req1(rd_req_ocm_gp0), .prt_req2(rd_req_ocm_gp1), .prt_data1(rd_data_ocm_gp0), .prt_data2(rd_data_ocm_gp1), .prt_addr1(rd_addr_gp0), .prt_addr2(rd_addr_gp1), .prt_bytes1(rd_bytes_gp0), .prt_bytes2(rd_bytes_gp1), .prt_dv1(rd_dv_ocm_gp0), .prt_dv2(rd_dv_ocm_gp1), .prt_req(ocm_rd_req), .prt_qos(ocm_rd_qos), .prt_data(ocm_rd_data), .prt_addr(ocm_rd_addr), .prt_bytes(ocm_rd_bytes), .prt_dv(ocm_rd_dv) ); processing_system7_bfm_v2_0_5_arb_rd ddr_gp_rd( .rstn(rstn), .sw_clk(sw_clk), .qos1(r_qos_gp0), .qos2(r_qos_gp1), .prt_req1(rd_req_ddr_gp0), .prt_req2(rd_req_ddr_gp1), .prt_data1(rd_data_ddr_gp0), .prt_data2(rd_data_ddr_gp1), .prt_addr1(rd_addr_gp0), .prt_addr2(rd_addr_gp1), .prt_bytes1(rd_bytes_gp0), .prt_bytes2(rd_bytes_gp1), .prt_dv1(rd_dv_ddr_gp0), .prt_dv2(rd_dv_ddr_gp1), .prt_req(ddr_rd_req), .prt_qos(ddr_rd_qos), .prt_data(ddr_rd_data), .prt_addr(ddr_rd_addr), .prt_bytes(ddr_rd_bytes), .prt_dv(ddr_rd_dv) ); processing_system7_bfm_v2_0_5_arb_rd reg_gp_rd( .rstn(rstn), .sw_clk(sw_clk), .qos1(r_qos_gp0), .qos2(r_qos_gp1), .prt_req1(rd_req_reg_gp0), .prt_req2(rd_req_reg_gp1), .prt_data1(rd_data_reg_gp0), .prt_data2(rd_data_reg_gp1), .prt_addr1(rd_addr_gp0), .prt_addr2(rd_addr_gp1), .prt_bytes1(rd_bytes_gp0), .prt_bytes2(rd_bytes_gp1), .prt_dv1(rd_dv_reg_gp0), .prt_dv2(rd_dv_reg_gp1), .prt_req(reg_rd_req), .prt_qos(reg_rd_qos), .prt_data(reg_rd_data), .prt_addr(reg_rd_addr), .prt_bytes(reg_rd_bytes), .prt_dv(reg_rd_dv) ); endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_arb_hp0_1.v * * Date : 2012-11 * * Description : Module that arbitrates between RD/WR requests from 2 ports. * Used for modelling the Top_Interconnect switch. *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_arb_hp0_1( sw_clk, rstn, w_qos_hp0, r_qos_hp0, w_qos_hp1, r_qos_hp1, wr_ack_ddr_hp0, wr_data_hp0, wr_addr_hp0, wr_bytes_hp0, wr_dv_ddr_hp0, rd_req_ddr_hp0, rd_addr_hp0, rd_bytes_hp0, rd_data_ddr_hp0, rd_dv_ddr_hp0, wr_ack_ddr_hp1, wr_data_hp1, wr_addr_hp1, wr_bytes_hp1, wr_dv_ddr_hp1, rd_req_ddr_hp1, rd_addr_hp1, rd_bytes_hp1, rd_data_ddr_hp1, rd_dv_ddr_hp1, ddr_wr_ack, ddr_wr_dv, ddr_rd_req, ddr_rd_dv, ddr_rd_qos, ddr_wr_qos, ddr_wr_addr, ddr_wr_data, ddr_wr_bytes, ddr_rd_addr, ddr_rd_data, ddr_rd_bytes ); `include "processing_system7_bfm_v2_0_5_local_params.v" input sw_clk; input rstn; input [axi_qos_width-1:0] w_qos_hp0; input [axi_qos_width-1:0] r_qos_hp0; input [axi_qos_width-1:0] w_qos_hp1; input [axi_qos_width-1:0] r_qos_hp1; input [axi_qos_width-1:0] ddr_rd_qos; input [axi_qos_width-1:0] ddr_wr_qos; output wr_ack_ddr_hp0; input [max_burst_bits-1:0] wr_data_hp0; input [addr_width-1:0] wr_addr_hp0; input [max_burst_bytes_width:0] wr_bytes_hp0; output wr_dv_ddr_hp0; input rd_req_ddr_hp0; input [addr_width-1:0] rd_addr_hp0; input [max_burst_bytes_width:0] rd_bytes_hp0; output [max_burst_bits-1:0] rd_data_ddr_hp0; output rd_dv_ddr_hp0; output wr_ack_ddr_hp1; input [max_burst_bits-1:0] wr_data_hp1; input [addr_width-1:0] wr_addr_hp1; input [max_burst_bytes_width:0] wr_bytes_hp1; output wr_dv_ddr_hp1; input rd_req_ddr_hp1; input [addr_width-1:0] rd_addr_hp1; input [max_burst_bytes_width:0] rd_bytes_hp1; output [max_burst_bits-1:0] rd_data_ddr_hp1; output rd_dv_ddr_hp1; input ddr_wr_ack; output ddr_wr_dv; output [addr_width-1:0]ddr_wr_addr; output [max_burst_bits-1:0]ddr_wr_data; output [max_burst_bytes_width:0]ddr_wr_bytes; input ddr_rd_dv; input [max_burst_bits-1:0] ddr_rd_data; output ddr_rd_req; output [addr_width-1:0] ddr_rd_addr; output [max_burst_bytes_width:0] ddr_rd_bytes; processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr( .rstn(rstn), .sw_clk(sw_clk), .qos1(w_qos_hp0), .qos2(w_qos_hp1), .prt_dv1(wr_dv_ddr_hp0), .prt_dv2(wr_dv_ddr_hp1), .prt_data1(wr_data_hp0), .prt_data2(wr_data_hp1), .prt_addr1(wr_addr_hp0), .prt_addr2(wr_addr_hp1), .prt_bytes1(wr_bytes_hp0), .prt_bytes2(wr_bytes_hp1), .prt_ack1(wr_ack_ddr_hp0), .prt_ack2(wr_ack_ddr_hp1), .prt_req(ddr_wr_dv), .prt_qos(ddr_wr_qos), .prt_data(ddr_wr_data), .prt_addr(ddr_wr_addr), .prt_bytes(ddr_wr_bytes), .prt_ack(ddr_wr_ack) ); processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd( .rstn(rstn), .sw_clk(sw_clk), .qos1(r_qos_hp0), .qos2(r_qos_hp1), .prt_req1(rd_req_ddr_hp0), .prt_req2(rd_req_ddr_hp1), .prt_data1(rd_data_ddr_hp0), .prt_data2(rd_data_ddr_hp1), .prt_addr1(rd_addr_hp0), .prt_addr2(rd_addr_hp1), .prt_bytes1(rd_bytes_hp0), .prt_bytes2(rd_bytes_hp1), .prt_dv1(rd_dv_ddr_hp0), .prt_dv2(rd_dv_ddr_hp1), .prt_qos(ddr_rd_qos), .prt_req(ddr_rd_req), .prt_data(ddr_rd_data), .prt_addr(ddr_rd_addr), .prt_bytes(ddr_rd_bytes), .prt_dv(ddr_rd_dv) ); endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_arb_hp0_1.v * * Date : 2012-11 * * Description : Module that arbitrates between RD/WR requests from 2 ports. * Used for modelling the Top_Interconnect switch. *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_arb_hp0_1( sw_clk, rstn, w_qos_hp0, r_qos_hp0, w_qos_hp1, r_qos_hp1, wr_ack_ddr_hp0, wr_data_hp0, wr_addr_hp0, wr_bytes_hp0, wr_dv_ddr_hp0, rd_req_ddr_hp0, rd_addr_hp0, rd_bytes_hp0, rd_data_ddr_hp0, rd_dv_ddr_hp0, wr_ack_ddr_hp1, wr_data_hp1, wr_addr_hp1, wr_bytes_hp1, wr_dv_ddr_hp1, rd_req_ddr_hp1, rd_addr_hp1, rd_bytes_hp1, rd_data_ddr_hp1, rd_dv_ddr_hp1, ddr_wr_ack, ddr_wr_dv, ddr_rd_req, ddr_rd_dv, ddr_rd_qos, ddr_wr_qos, ddr_wr_addr, ddr_wr_data, ddr_wr_bytes, ddr_rd_addr, ddr_rd_data, ddr_rd_bytes ); `include "processing_system7_bfm_v2_0_5_local_params.v" input sw_clk; input rstn; input [axi_qos_width-1:0] w_qos_hp0; input [axi_qos_width-1:0] r_qos_hp0; input [axi_qos_width-1:0] w_qos_hp1; input [axi_qos_width-1:0] r_qos_hp1; input [axi_qos_width-1:0] ddr_rd_qos; input [axi_qos_width-1:0] ddr_wr_qos; output wr_ack_ddr_hp0; input [max_burst_bits-1:0] wr_data_hp0; input [addr_width-1:0] wr_addr_hp0; input [max_burst_bytes_width:0] wr_bytes_hp0; output wr_dv_ddr_hp0; input rd_req_ddr_hp0; input [addr_width-1:0] rd_addr_hp0; input [max_burst_bytes_width:0] rd_bytes_hp0; output [max_burst_bits-1:0] rd_data_ddr_hp0; output rd_dv_ddr_hp0; output wr_ack_ddr_hp1; input [max_burst_bits-1:0] wr_data_hp1; input [addr_width-1:0] wr_addr_hp1; input [max_burst_bytes_width:0] wr_bytes_hp1; output wr_dv_ddr_hp1; input rd_req_ddr_hp1; input [addr_width-1:0] rd_addr_hp1; input [max_burst_bytes_width:0] rd_bytes_hp1; output [max_burst_bits-1:0] rd_data_ddr_hp1; output rd_dv_ddr_hp1; input ddr_wr_ack; output ddr_wr_dv; output [addr_width-1:0]ddr_wr_addr; output [max_burst_bits-1:0]ddr_wr_data; output [max_burst_bytes_width:0]ddr_wr_bytes; input ddr_rd_dv; input [max_burst_bits-1:0] ddr_rd_data; output ddr_rd_req; output [addr_width-1:0] ddr_rd_addr; output [max_burst_bytes_width:0] ddr_rd_bytes; processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr( .rstn(rstn), .sw_clk(sw_clk), .qos1(w_qos_hp0), .qos2(w_qos_hp1), .prt_dv1(wr_dv_ddr_hp0), .prt_dv2(wr_dv_ddr_hp1), .prt_data1(wr_data_hp0), .prt_data2(wr_data_hp1), .prt_addr1(wr_addr_hp0), .prt_addr2(wr_addr_hp1), .prt_bytes1(wr_bytes_hp0), .prt_bytes2(wr_bytes_hp1), .prt_ack1(wr_ack_ddr_hp0), .prt_ack2(wr_ack_ddr_hp1), .prt_req(ddr_wr_dv), .prt_qos(ddr_wr_qos), .prt_data(ddr_wr_data), .prt_addr(ddr_wr_addr), .prt_bytes(ddr_wr_bytes), .prt_ack(ddr_wr_ack) ); processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd( .rstn(rstn), .sw_clk(sw_clk), .qos1(r_qos_hp0), .qos2(r_qos_hp1), .prt_req1(rd_req_ddr_hp0), .prt_req2(rd_req_ddr_hp1), .prt_data1(rd_data_ddr_hp0), .prt_data2(rd_data_ddr_hp1), .prt_addr1(rd_addr_hp0), .prt_addr2(rd_addr_hp1), .prt_bytes1(rd_bytes_hp0), .prt_bytes2(rd_bytes_hp1), .prt_dv1(rd_dv_ddr_hp0), .prt_dv2(rd_dv_ddr_hp1), .prt_qos(ddr_rd_qos), .prt_req(ddr_rd_req), .prt_data(ddr_rd_data), .prt_addr(ddr_rd_addr), .prt_bytes(ddr_rd_bytes), .prt_dv(ddr_rd_dv) ); endmodule
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: decerr_slave.v // // Description: // Phantom slave interface used to complete W, R and B channel transfers when an // erroneous transaction is trapped in the crossbar. //-------------------------------------------------------------------------- // // Structure: // decerr_slave // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_decerr_slave # ( parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_PROTOCOL = 0, parameter integer C_RESP = 2'b11 ) ( input wire S_AXI_ACLK, input wire S_AXI_ARESET, input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, input wire S_AXI_WLAST, input wire S_AXI_WVALID, output wire S_AXI_WREADY, output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID, output wire [1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID, input wire [7:0] S_AXI_ARLEN, input wire S_AXI_ARVALID, output wire S_AXI_ARREADY, output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID, output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA, output wire [1:0] S_AXI_RRESP, output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire S_AXI_RLAST, output wire S_AXI_RVALID, input wire S_AXI_RREADY ); reg s_axi_awready_i; reg s_axi_wready_i; reg s_axi_bvalid_i; reg s_axi_arready_i; reg s_axi_rvalid_i; localparam P_WRITE_IDLE = 2'b00; localparam P_WRITE_DATA = 2'b01; localparam P_WRITE_RESP = 2'b10; localparam P_READ_IDLE = 1'b0; localparam P_READ_DATA = 1'b1; localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; assign S_AXI_BRESP = C_RESP; assign S_AXI_RRESP = C_RESP; assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}}; assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}}; assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}}; assign S_AXI_AWREADY = s_axi_awready_i; assign S_AXI_WREADY = s_axi_wready_i; assign S_AXI_BVALID = s_axi_bvalid_i; assign S_AXI_ARREADY = s_axi_arready_i; assign S_AXI_RVALID = s_axi_rvalid_i; generate if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite assign S_AXI_RLAST = 1'b1; assign S_AXI_BID = 0; assign S_AXI_RID = 0; always @(posedge S_AXI_ACLK) begin if (S_AXI_ARESET) begin s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b0; end else begin if (s_axi_bvalid_i) begin if (S_AXI_BREADY) begin s_axi_bvalid_i <= 1'b0; end end else if (S_AXI_AWVALID & S_AXI_WVALID) begin if (s_axi_awready_i) begin s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b1; end else begin s_axi_awready_i <= 1'b1; s_axi_wready_i <= 1'b1; end end end end always @(posedge S_AXI_ACLK) begin if (S_AXI_ARESET) begin s_axi_arready_i <= 1'b0; s_axi_rvalid_i <= 1'b0; end else begin if (s_axi_rvalid_i) begin if (S_AXI_RREADY) begin s_axi_rvalid_i <= 1'b0; end end else if (S_AXI_ARVALID & s_axi_arready_i) begin s_axi_arready_i <= 1'b0; s_axi_rvalid_i <= 1'b1; end else begin s_axi_arready_i <= 1'b1; end end end end else begin : gen_axi reg s_axi_rlast_i; reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i; reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i; reg [7:0] read_cnt; reg [1:0] write_cs; reg [0:0] read_cs; assign S_AXI_RLAST = s_axi_rlast_i; assign S_AXI_BID = s_axi_bid_i; assign S_AXI_RID = s_axi_rid_i; always @(posedge S_AXI_ACLK) begin if (S_AXI_ARESET) begin write_cs <= P_WRITE_IDLE; s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b0; s_axi_bid_i <= 0; end else begin case (write_cs) P_WRITE_IDLE: begin if (S_AXI_AWVALID & s_axi_awready_i) begin s_axi_awready_i <= 1'b0; s_axi_bid_i <= S_AXI_AWID; s_axi_wready_i <= 1'b1; write_cs <= P_WRITE_DATA; end else begin s_axi_awready_i <= 1'b1; end end P_WRITE_DATA: begin if (S_AXI_WVALID & S_AXI_WLAST) begin s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b1; write_cs <= P_WRITE_RESP; end end P_WRITE_RESP: begin if (S_AXI_BREADY) begin s_axi_bvalid_i <= 1'b0; s_axi_awready_i <= 1'b1; write_cs <= P_WRITE_IDLE; end end endcase end end always @(posedge S_AXI_ACLK) begin if (S_AXI_ARESET) begin read_cs <= P_READ_IDLE; s_axi_arready_i <= 1'b0; s_axi_rvalid_i <= 1'b0; s_axi_rlast_i <= 1'b0; s_axi_rid_i <= 0; read_cnt <= 0; end else begin case (read_cs) P_READ_IDLE: begin if (S_AXI_ARVALID & s_axi_arready_i) begin s_axi_arready_i <= 1'b0; s_axi_rid_i <= S_AXI_ARID; read_cnt <= S_AXI_ARLEN; s_axi_rvalid_i <= 1'b1; if (S_AXI_ARLEN == 0) begin s_axi_rlast_i <= 1'b1; end else begin s_axi_rlast_i <= 1'b0; end read_cs <= P_READ_DATA; end else begin s_axi_arready_i <= 1'b1; end end P_READ_DATA: begin if (S_AXI_RREADY) begin if (read_cnt == 0) begin s_axi_rvalid_i <= 1'b0; s_axi_rlast_i <= 1'b0; s_axi_arready_i <= 1'b1; read_cs <= P_READ_IDLE; end else begin if (read_cnt == 1) begin s_axi_rlast_i <= 1'b1; end read_cnt <= read_cnt - 1; end end end endcase end end end endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: si_transactor.v // // Description: // This module manages multi-threaded transactions for one SI-slot. // The module interface consists of a 1-slave to 1-master address channel, plus a // (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel. // The module maintains transaction thread control registers that count the // number of outstanding transations for each thread and the target MI-slot. // On the address channel, the module decodes addresses to select among MI-slots // accessible to the SI-slot where it is instantiated. // It then qualifies whether each received transaction // should be propagated as a request to the address channel arbiter. // Transactions are blocked while there is any outstanding transaction to a // different slave (MI-slot) for the requested ID thread (for deadlock avoidance). // On the response channel, the module mulitplexes transfers from each of the // MI-slots whenever a transfer targets the ID of an active thread, // arbitrating between MI-slots if multiple threads respond concurrently. // //-------------------------------------------------------------------------- // // Structure: // si_transactor // addr_decoder // comparator_static // mux_enc // axic_srl_fifo // arbiter_resp // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_si_transactor # ( parameter C_FAMILY = "none", parameter integer C_SI = 0, // SI-slot number of current instance. parameter integer C_DIR = 0, // Direction: 0 = Write; 1 = Read. parameter integer C_NUM_ADDR_RANGES = 1, parameter integer C_NUM_M = 2, parameter integer C_NUM_M_LOG = 1, parameter integer C_ACCEPTANCE = 1, // Acceptance limit of this SI-slot. parameter integer C_ACCEPTANCE_LOG = 0, // Width of acceptance counter for this SI-slot. parameter integer C_ID_WIDTH = 1, parameter integer C_THREAD_ID_WIDTH = 0, parameter integer C_ADDR_WIDTH = 32, parameter integer C_AMESG_WIDTH = 1, // Used for AW or AR channel payload, depending on instantiation. parameter integer C_RMESG_WIDTH = 1, // Used for B or R channel payload, depending on instantiation. parameter [C_ID_WIDTH-1:0] C_BASE_ID = {C_ID_WIDTH{1'b0}}, parameter [C_ID_WIDTH-1:0] C_HIGH_ID = {C_ID_WIDTH{1'b0}}, parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}}, parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}}, parameter integer C_SINGLE_THREAD = 0, parameter [C_NUM_M-1:0] C_TARGET_QUAL = {C_NUM_M{1'b1}}, parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE = {C_NUM_M{32'h00000000}}, parameter integer C_RANGE_CHECK = 0, parameter integer C_ADDR_DECODE =0, parameter [C_NUM_M*32-1:0] C_ERR_MODE = {C_NUM_M{32'h00000000}}, parameter integer C_DEBUG = 1 ) ( // Global Signals input wire ACLK, input wire ARESET, // Slave Address Channel Interface Ports input wire [C_ID_WIDTH-1:0] S_AID, input wire [C_ADDR_WIDTH-1:0] S_AADDR, input wire [8-1:0] S_ALEN, input wire [3-1:0] S_ASIZE, input wire [2-1:0] S_ABURST, input wire [2-1:0] S_ALOCK, input wire [3-1:0] S_APROT, // input wire [4-1:0] S_AREGION, input wire [C_AMESG_WIDTH-1:0] S_AMESG, input wire S_AVALID, output wire S_AREADY, // Master Address Channel Interface Ports output wire [C_ID_WIDTH-1:0] M_AID, output wire [C_ADDR_WIDTH-1:0] M_AADDR, output wire [8-1:0] M_ALEN, output wire [3-1:0] M_ASIZE, output wire [2-1:0] M_ALOCK, output wire [3-1:0] M_APROT, output wire [4-1:0] M_AREGION, output wire [C_AMESG_WIDTH-1:0] M_AMESG, output wire [(C_NUM_M+1)-1:0] M_ATARGET_HOT, output wire [(C_NUM_M_LOG+1)-1:0] M_ATARGET_ENC, output wire [7:0] M_AERROR, output wire M_AVALID_QUAL, output wire M_AVALID, input wire M_AREADY, // Slave Response Channel Interface Ports output wire [C_ID_WIDTH-1:0] S_RID, output wire [C_RMESG_WIDTH-1:0] S_RMESG, output wire S_RLAST, output wire S_RVALID, input wire S_RREADY, // Master Response Channel Interface Ports input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0] M_RID, input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0] M_RMESG, input wire [(C_NUM_M+1)-1:0] M_RLAST, input wire [(C_NUM_M+1)-1:0] M_RVALID, output wire [(C_NUM_M+1)-1:0] M_RREADY, input wire [(C_NUM_M+1)-1:0] M_RTARGET, // Does response ID from each MI-slot target this SI slot? input wire [8-1:0] DEBUG_A_TRANS_SEQ ); localparam integer P_WRITE = 0; localparam integer P_READ = 1; localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1; localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001; localparam integer P_NONSECURE_BIT = 1; localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1; localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0); // Mask of AxiLite MI-slots localparam [1:0] P_FIXED = 2'b00; localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1); localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1; localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH; localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE; localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots // Ceiling of log2(x) function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2**acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // AxiLite protocol flag vector function [C_NUM_M-1:0] f_m_axilite ( input integer null_arg ); integer mi; begin for (mi=0; mi<C_NUM_M; mi=mi+1) begin f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE); end end endfunction // Convert Bit32 vector of range [0,1] to Bit1 vector on MI function [C_NUM_M-1:0] f_bit32to1_mi (input [C_NUM_M*32-1:0] vec32); integer mi; begin for (mi=0; mi<C_NUM_M; mi=mi+1) begin f_bit32to1_mi[mi] = vec32[mi*32]; end end endfunction wire [C_NUM_M-1:0] target_mi_hot; wire [P_NUM_M_LOG_M1-1:0] target_mi_enc; wire [(C_NUM_M+1)-1:0] m_atarget_hot_i; wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i; wire match; wire [3:0] target_region; wire [3:0] m_aregion_i; wire m_avalid_i; wire s_aready_i; wire any_error; wire s_rvalid_i; wire [C_ID_WIDTH-1:0] s_rid_i; wire s_rlast_i; wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg; wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg; wire [(C_NUM_M+1)-1:0] m_rvalid_qual; wire [(C_NUM_M+1)-1:0] m_rready_arb; wire [(C_NUM_M+1)-1:0] m_rready_i; wire target_secure; wire target_axilite; wire m_avalid_qual_i; wire [7:0] m_aerror_i; genvar gen_mi; genvar gen_thread; generate if (C_ADDR_DECODE) begin : gen_addr_decoder axi_crossbar_v2_1_addr_decoder # ( .C_FAMILY (C_FAMILY), .C_NUM_TARGETS (C_NUM_M), .C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1), .C_NUM_RANGES (C_NUM_ADDR_RANGES), .C_ADDR_WIDTH (C_ADDR_WIDTH), .C_TARGET_ENC (1), .C_TARGET_HOT (1), .C_REGION_ENC (1), .C_BASE_ADDR (C_BASE_ADDR), .C_HIGH_ADDR (C_HIGH_ADDR), .C_TARGET_QUAL (C_TARGET_QUAL), .C_RESOLUTION (2) ) addr_decoder_inst ( .ADDR (S_AADDR), .TARGET_HOT (target_mi_hot), .TARGET_ENC (target_mi_enc), .MATCH (match), .REGION (target_region) ); end else begin : gen_no_addr_decoder assign target_mi_hot = 1; assign target_mi_enc = 0; assign match = 1'b1; assign target_region = 4'b0000; end endgenerate assign target_secure = |(target_mi_hot & P_M_SECURE_MASK); assign target_axilite = |(target_mi_hot & P_M_AXILITE); assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition. assign m_aerror_i[0] = ~match; // Invalid target address assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) || (S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1)); // AxiLite access violation assign m_aerror_i[7:3] = 5'b00000; // Reserved assign M_ATARGET_HOT = m_atarget_hot_i; assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot}); assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc); assign M_AVALID = m_avalid_i; assign m_avalid_i = S_AVALID; assign M_AVALID_QUAL = m_avalid_qual_i; assign S_AREADY = s_aready_i; assign s_aready_i = M_AREADY; assign M_AERROR = m_aerror_i; assign M_ATARGET_ENC = m_atarget_enc_i; assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000; // assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION; assign M_AREGION = m_aregion_i; assign M_AID = S_AID; assign M_AADDR = S_AADDR; assign M_ALEN = S_ALEN; assign M_ASIZE = S_ASIZE; assign M_ALOCK = S_ALOCK; assign M_APROT = S_APROT; assign M_AMESG = S_AMESG; assign S_RVALID = s_rvalid_i; assign M_RREADY = m_rready_i; assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH]; assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH]; assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1]; assign S_RID = s_rid_i; assign S_RLAST = s_rlast_i; assign m_rvalid_qual = M_RVALID & M_RTARGET; assign m_rready_i = m_rready_arb & M_RTARGET; generate for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order. assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = { M_RLAST[gen_mi], M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH], M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH] }; end // gen_rmesg_mi if (C_ACCEPTANCE == 1) begin : gen_single_issue wire cmd_push; wire cmd_pop; reg [(C_NUM_M+1)-1:0] active_target_hot; reg [P_NUM_M_DE_LOG-1:0] active_target_enc; reg accept_cnt; reg [8-1:0] debug_r_beat_cnt_i; wire [8-1:0] debug_r_trans_seq_i; assign cmd_push = M_AREADY; assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst assign m_avalid_qual_i = ~accept_cnt | cmd_pop; // Ready for arbitration if no outstanding transaction or transaction being completed always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 1'b0; active_target_enc <= 0; active_target_hot <= 0; end else begin if (cmd_push) begin active_target_enc <= m_atarget_enc_i; active_target_hot <= m_atarget_hot_i; accept_cnt <= 1'b1; end else if (cmd_pop) begin accept_cnt <= 1'b0; end end end // Clocked process assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}}; assign s_rvalid_i = |(active_target_hot & m_rvalid_qual); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_single_issue ( .S (active_target_enc), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1'b1) ); if (C_DEBUG) begin : gen_debug_r_single_issue // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i && S_RREADY) begin if (s_rlast_i) begin debug_r_beat_cnt_i <= 0; end else begin debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1; end end end else begin debug_r_beat_cnt_i <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_single_issue ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push), .S_READY (), .M_MESG (debug_r_trans_seq_i), .M_VALID (), .M_READY (cmd_pop) ); end // gen_debug_r end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread wire s_avalid_en; wire cmd_push; wire cmd_pop; reg [C_ID_WIDTH-1:0] active_id; reg [(C_NUM_M+1)-1:0] active_target_hot; reg [P_NUM_M_DE_LOG-1:0] active_target_enc; reg [4-1:0] active_region; reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt; reg [8-1:0] debug_r_beat_cnt_i; wire [8-1:0] debug_r_trans_seq_i; wire accept_limit ; // Implement single-region-per-ID cyclic dependency avoidance method. assign s_avalid_en = // This transaction is qualified to request arbitration if ... (accept_cnt == 0) || // Either there are no outstanding transactions, or ... (((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) && // the current transaction ID matches the previous, and ... (active_target_enc == m_atarget_enc_i) && // all outstanding transactions are to the same target MI ... (active_region == m_aregion_i)); // and to the same REGION. assign cmd_push = M_AREADY; assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop; // Allow next push if a transaction is currently being completed assign m_avalid_qual_i = s_avalid_en & ~accept_limit; always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 0; active_id <= 0; active_target_enc <= 0; active_target_hot <= 0; active_region <= 0; end else begin if (cmd_push) begin active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0]; active_target_enc <= m_atarget_enc_i; active_target_hot <= m_atarget_hot_i; active_region <= m_aregion_i; if (~cmd_pop) begin accept_cnt <= accept_cnt + 1; end end else begin if (cmd_pop & (accept_cnt != 0)) begin accept_cnt <= accept_cnt - 1; end end end end // Clocked process assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}}; assign s_rvalid_i = |(active_target_hot & m_rvalid_qual); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_single_thread ( .S (active_target_enc), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1'b1) ); if (C_DEBUG) begin : gen_debug_r_single_thread // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i && S_RREADY) begin if (s_rlast_i) begin debug_r_beat_cnt_i <= 0; end else begin debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1; end end end else begin debug_r_beat_cnt_i <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_single_thread ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push), .S_READY (), .M_MESG (debug_r_trans_seq_i), .M_VALID (), .M_READY (cmd_pop) ); end // gen_debug_r end else begin : gen_multi_thread wire [(P_NUM_M_DE_LOG)-1:0] resp_select; reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt; wire [P_NUM_THREADS-1:0] s_avalid_en; wire [P_NUM_THREADS-1:0] thread_valid; wire [P_NUM_THREADS-1:0] aid_match; wire [P_NUM_THREADS-1:0] rid_match; wire [P_NUM_THREADS-1:0] cmd_push; wire [P_NUM_THREADS-1:0] cmd_pop; wire [P_NUM_THREADS:0] accum_push; reg [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id; reg [P_NUM_THREADS*8-1:0] active_target; reg [P_NUM_THREADS*8-1:0] active_region; reg [P_NUM_THREADS*8-1:0] active_cnt; reg [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i; wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i; wire any_aid_match; wire any_rid_match; wire accept_limit; wire any_push; wire any_pop; axi_crossbar_v2_1_arbiter_resp # // Multi-thread response arbiter ( .C_FAMILY (C_FAMILY), .C_NUM_S (C_NUM_M+1), .C_NUM_S_LOG (P_NUM_M_DE_LOG), .C_GRANT_ENC (1), .C_GRANT_HOT (0) ) arbiter_resp_inst ( .ACLK (ACLK), .ARESET (ARESET), .S_VALID (m_rvalid_qual), .S_READY (m_rready_arb), .M_GRANT_HOT (), .M_GRANT_ENC (resp_select), .M_VALID (s_rvalid_i), .M_READY (S_RREADY) ); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_multi_thread ( .S (resp_select), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1'b1) ); assign any_push = M_AREADY; assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i; assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop; // Allow next push if a transaction is currently being completed assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit; // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads. assign any_aid_match = |aid_match; assign any_rid_match = |rid_match; assign accum_push[0] = 1'b0; always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 0; end else begin if (any_push & ~any_pop) begin accept_cnt <= accept_cnt + 1; end else if (any_pop & ~any_push & (accept_cnt != 0)) begin accept_cnt <= accept_cnt - 1; end end end // Clocked process for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0); assign aid_match[gen_thread] = // The currect thread is active for the requested transaction if thread_valid[gen_thread] && // this thread slot is not vacant, and ((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); // the requested ID matches the active ID for this thread. assign s_avalid_en[gen_thread] = // The current request is qualified against this thread slot if (~aid_match[gen_thread]) || // This thread slot is not active for the requested ID, or ((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) && // this outstanding transaction was to the same target and (m_aregion_i == active_region[gen_thread*8+:4])); // to the same region. // cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot. assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread]; assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread])); // cmd_pop points to the position of the active thread that matches the current RID. assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread]; always @(posedge ACLK) begin if (ARESET) begin active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0; active_target[gen_thread*8+:8] <= 0; active_region[gen_thread*8+:8] <= 0; active_cnt[gen_thread*8+:8] <= 0; end else begin if (cmd_push[gen_thread]) begin active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0]; active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i; active_region[gen_thread*8+:4] <= m_aregion_i; if (~cmd_pop[gen_thread]) begin active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1; end end else if (cmd_pop[gen_thread]) begin active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1; end end end // Clocked process if (C_DEBUG) begin : gen_debug_r_multi_thread // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin if (s_rlast_i) begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end else begin debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1; end end end else begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_multi_thread ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push[gen_thread]), .S_READY (), .M_MESG (debug_r_trans_seq_i[gen_thread*8+:8]), .M_VALID (), .M_READY (cmd_pop[gen_thread]) ); end // gen_debug_r_multi_thread end // Next gen_thread_loop end // thread control endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: si_transactor.v // // Description: // This module manages multi-threaded transactions for one SI-slot. // The module interface consists of a 1-slave to 1-master address channel, plus a // (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel. // The module maintains transaction thread control registers that count the // number of outstanding transations for each thread and the target MI-slot. // On the address channel, the module decodes addresses to select among MI-slots // accessible to the SI-slot where it is instantiated. // It then qualifies whether each received transaction // should be propagated as a request to the address channel arbiter. // Transactions are blocked while there is any outstanding transaction to a // different slave (MI-slot) for the requested ID thread (for deadlock avoidance). // On the response channel, the module mulitplexes transfers from each of the // MI-slots whenever a transfer targets the ID of an active thread, // arbitrating between MI-slots if multiple threads respond concurrently. // //-------------------------------------------------------------------------- // // Structure: // si_transactor // addr_decoder // comparator_static // mux_enc // axic_srl_fifo // arbiter_resp // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_si_transactor # ( parameter C_FAMILY = "none", parameter integer C_SI = 0, // SI-slot number of current instance. parameter integer C_DIR = 0, // Direction: 0 = Write; 1 = Read. parameter integer C_NUM_ADDR_RANGES = 1, parameter integer C_NUM_M = 2, parameter integer C_NUM_M_LOG = 1, parameter integer C_ACCEPTANCE = 1, // Acceptance limit of this SI-slot. parameter integer C_ACCEPTANCE_LOG = 0, // Width of acceptance counter for this SI-slot. parameter integer C_ID_WIDTH = 1, parameter integer C_THREAD_ID_WIDTH = 0, parameter integer C_ADDR_WIDTH = 32, parameter integer C_AMESG_WIDTH = 1, // Used for AW or AR channel payload, depending on instantiation. parameter integer C_RMESG_WIDTH = 1, // Used for B or R channel payload, depending on instantiation. parameter [C_ID_WIDTH-1:0] C_BASE_ID = {C_ID_WIDTH{1'b0}}, parameter [C_ID_WIDTH-1:0] C_HIGH_ID = {C_ID_WIDTH{1'b0}}, parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}}, parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}}, parameter integer C_SINGLE_THREAD = 0, parameter [C_NUM_M-1:0] C_TARGET_QUAL = {C_NUM_M{1'b1}}, parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE = {C_NUM_M{32'h00000000}}, parameter integer C_RANGE_CHECK = 0, parameter integer C_ADDR_DECODE =0, parameter [C_NUM_M*32-1:0] C_ERR_MODE = {C_NUM_M{32'h00000000}}, parameter integer C_DEBUG = 1 ) ( // Global Signals input wire ACLK, input wire ARESET, // Slave Address Channel Interface Ports input wire [C_ID_WIDTH-1:0] S_AID, input wire [C_ADDR_WIDTH-1:0] S_AADDR, input wire [8-1:0] S_ALEN, input wire [3-1:0] S_ASIZE, input wire [2-1:0] S_ABURST, input wire [2-1:0] S_ALOCK, input wire [3-1:0] S_APROT, // input wire [4-1:0] S_AREGION, input wire [C_AMESG_WIDTH-1:0] S_AMESG, input wire S_AVALID, output wire S_AREADY, // Master Address Channel Interface Ports output wire [C_ID_WIDTH-1:0] M_AID, output wire [C_ADDR_WIDTH-1:0] M_AADDR, output wire [8-1:0] M_ALEN, output wire [3-1:0] M_ASIZE, output wire [2-1:0] M_ALOCK, output wire [3-1:0] M_APROT, output wire [4-1:0] M_AREGION, output wire [C_AMESG_WIDTH-1:0] M_AMESG, output wire [(C_NUM_M+1)-1:0] M_ATARGET_HOT, output wire [(C_NUM_M_LOG+1)-1:0] M_ATARGET_ENC, output wire [7:0] M_AERROR, output wire M_AVALID_QUAL, output wire M_AVALID, input wire M_AREADY, // Slave Response Channel Interface Ports output wire [C_ID_WIDTH-1:0] S_RID, output wire [C_RMESG_WIDTH-1:0] S_RMESG, output wire S_RLAST, output wire S_RVALID, input wire S_RREADY, // Master Response Channel Interface Ports input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0] M_RID, input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0] M_RMESG, input wire [(C_NUM_M+1)-1:0] M_RLAST, input wire [(C_NUM_M+1)-1:0] M_RVALID, output wire [(C_NUM_M+1)-1:0] M_RREADY, input wire [(C_NUM_M+1)-1:0] M_RTARGET, // Does response ID from each MI-slot target this SI slot? input wire [8-1:0] DEBUG_A_TRANS_SEQ ); localparam integer P_WRITE = 0; localparam integer P_READ = 1; localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1; localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001; localparam integer P_NONSECURE_BIT = 1; localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1; localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0); // Mask of AxiLite MI-slots localparam [1:0] P_FIXED = 2'b00; localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1); localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1; localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH; localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE; localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots // Ceiling of log2(x) function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2**acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // AxiLite protocol flag vector function [C_NUM_M-1:0] f_m_axilite ( input integer null_arg ); integer mi; begin for (mi=0; mi<C_NUM_M; mi=mi+1) begin f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE); end end endfunction // Convert Bit32 vector of range [0,1] to Bit1 vector on MI function [C_NUM_M-1:0] f_bit32to1_mi (input [C_NUM_M*32-1:0] vec32); integer mi; begin for (mi=0; mi<C_NUM_M; mi=mi+1) begin f_bit32to1_mi[mi] = vec32[mi*32]; end end endfunction wire [C_NUM_M-1:0] target_mi_hot; wire [P_NUM_M_LOG_M1-1:0] target_mi_enc; wire [(C_NUM_M+1)-1:0] m_atarget_hot_i; wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i; wire match; wire [3:0] target_region; wire [3:0] m_aregion_i; wire m_avalid_i; wire s_aready_i; wire any_error; wire s_rvalid_i; wire [C_ID_WIDTH-1:0] s_rid_i; wire s_rlast_i; wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg; wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg; wire [(C_NUM_M+1)-1:0] m_rvalid_qual; wire [(C_NUM_M+1)-1:0] m_rready_arb; wire [(C_NUM_M+1)-1:0] m_rready_i; wire target_secure; wire target_axilite; wire m_avalid_qual_i; wire [7:0] m_aerror_i; genvar gen_mi; genvar gen_thread; generate if (C_ADDR_DECODE) begin : gen_addr_decoder axi_crossbar_v2_1_addr_decoder # ( .C_FAMILY (C_FAMILY), .C_NUM_TARGETS (C_NUM_M), .C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1), .C_NUM_RANGES (C_NUM_ADDR_RANGES), .C_ADDR_WIDTH (C_ADDR_WIDTH), .C_TARGET_ENC (1), .C_TARGET_HOT (1), .C_REGION_ENC (1), .C_BASE_ADDR (C_BASE_ADDR), .C_HIGH_ADDR (C_HIGH_ADDR), .C_TARGET_QUAL (C_TARGET_QUAL), .C_RESOLUTION (2) ) addr_decoder_inst ( .ADDR (S_AADDR), .TARGET_HOT (target_mi_hot), .TARGET_ENC (target_mi_enc), .MATCH (match), .REGION (target_region) ); end else begin : gen_no_addr_decoder assign target_mi_hot = 1; assign target_mi_enc = 0; assign match = 1'b1; assign target_region = 4'b0000; end endgenerate assign target_secure = |(target_mi_hot & P_M_SECURE_MASK); assign target_axilite = |(target_mi_hot & P_M_AXILITE); assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition. assign m_aerror_i[0] = ~match; // Invalid target address assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) || (S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1)); // AxiLite access violation assign m_aerror_i[7:3] = 5'b00000; // Reserved assign M_ATARGET_HOT = m_atarget_hot_i; assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot}); assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc); assign M_AVALID = m_avalid_i; assign m_avalid_i = S_AVALID; assign M_AVALID_QUAL = m_avalid_qual_i; assign S_AREADY = s_aready_i; assign s_aready_i = M_AREADY; assign M_AERROR = m_aerror_i; assign M_ATARGET_ENC = m_atarget_enc_i; assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000; // assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION; assign M_AREGION = m_aregion_i; assign M_AID = S_AID; assign M_AADDR = S_AADDR; assign M_ALEN = S_ALEN; assign M_ASIZE = S_ASIZE; assign M_ALOCK = S_ALOCK; assign M_APROT = S_APROT; assign M_AMESG = S_AMESG; assign S_RVALID = s_rvalid_i; assign M_RREADY = m_rready_i; assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH]; assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH]; assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1]; assign S_RID = s_rid_i; assign S_RLAST = s_rlast_i; assign m_rvalid_qual = M_RVALID & M_RTARGET; assign m_rready_i = m_rready_arb & M_RTARGET; generate for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order. assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = { M_RLAST[gen_mi], M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH], M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH] }; end // gen_rmesg_mi if (C_ACCEPTANCE == 1) begin : gen_single_issue wire cmd_push; wire cmd_pop; reg [(C_NUM_M+1)-1:0] active_target_hot; reg [P_NUM_M_DE_LOG-1:0] active_target_enc; reg accept_cnt; reg [8-1:0] debug_r_beat_cnt_i; wire [8-1:0] debug_r_trans_seq_i; assign cmd_push = M_AREADY; assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst assign m_avalid_qual_i = ~accept_cnt | cmd_pop; // Ready for arbitration if no outstanding transaction or transaction being completed always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 1'b0; active_target_enc <= 0; active_target_hot <= 0; end else begin if (cmd_push) begin active_target_enc <= m_atarget_enc_i; active_target_hot <= m_atarget_hot_i; accept_cnt <= 1'b1; end else if (cmd_pop) begin accept_cnt <= 1'b0; end end end // Clocked process assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}}; assign s_rvalid_i = |(active_target_hot & m_rvalid_qual); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_single_issue ( .S (active_target_enc), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1'b1) ); if (C_DEBUG) begin : gen_debug_r_single_issue // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i && S_RREADY) begin if (s_rlast_i) begin debug_r_beat_cnt_i <= 0; end else begin debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1; end end end else begin debug_r_beat_cnt_i <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_single_issue ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push), .S_READY (), .M_MESG (debug_r_trans_seq_i), .M_VALID (), .M_READY (cmd_pop) ); end // gen_debug_r end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread wire s_avalid_en; wire cmd_push; wire cmd_pop; reg [C_ID_WIDTH-1:0] active_id; reg [(C_NUM_M+1)-1:0] active_target_hot; reg [P_NUM_M_DE_LOG-1:0] active_target_enc; reg [4-1:0] active_region; reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt; reg [8-1:0] debug_r_beat_cnt_i; wire [8-1:0] debug_r_trans_seq_i; wire accept_limit ; // Implement single-region-per-ID cyclic dependency avoidance method. assign s_avalid_en = // This transaction is qualified to request arbitration if ... (accept_cnt == 0) || // Either there are no outstanding transactions, or ... (((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) && // the current transaction ID matches the previous, and ... (active_target_enc == m_atarget_enc_i) && // all outstanding transactions are to the same target MI ... (active_region == m_aregion_i)); // and to the same REGION. assign cmd_push = M_AREADY; assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop; // Allow next push if a transaction is currently being completed assign m_avalid_qual_i = s_avalid_en & ~accept_limit; always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 0; active_id <= 0; active_target_enc <= 0; active_target_hot <= 0; active_region <= 0; end else begin if (cmd_push) begin active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0]; active_target_enc <= m_atarget_enc_i; active_target_hot <= m_atarget_hot_i; active_region <= m_aregion_i; if (~cmd_pop) begin accept_cnt <= accept_cnt + 1; end end else begin if (cmd_pop & (accept_cnt != 0)) begin accept_cnt <= accept_cnt - 1; end end end end // Clocked process assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}}; assign s_rvalid_i = |(active_target_hot & m_rvalid_qual); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_single_thread ( .S (active_target_enc), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1'b1) ); if (C_DEBUG) begin : gen_debug_r_single_thread // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i && S_RREADY) begin if (s_rlast_i) begin debug_r_beat_cnt_i <= 0; end else begin debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1; end end end else begin debug_r_beat_cnt_i <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_single_thread ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push), .S_READY (), .M_MESG (debug_r_trans_seq_i), .M_VALID (), .M_READY (cmd_pop) ); end // gen_debug_r end else begin : gen_multi_thread wire [(P_NUM_M_DE_LOG)-1:0] resp_select; reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt; wire [P_NUM_THREADS-1:0] s_avalid_en; wire [P_NUM_THREADS-1:0] thread_valid; wire [P_NUM_THREADS-1:0] aid_match; wire [P_NUM_THREADS-1:0] rid_match; wire [P_NUM_THREADS-1:0] cmd_push; wire [P_NUM_THREADS-1:0] cmd_pop; wire [P_NUM_THREADS:0] accum_push; reg [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id; reg [P_NUM_THREADS*8-1:0] active_target; reg [P_NUM_THREADS*8-1:0] active_region; reg [P_NUM_THREADS*8-1:0] active_cnt; reg [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i; wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i; wire any_aid_match; wire any_rid_match; wire accept_limit; wire any_push; wire any_pop; axi_crossbar_v2_1_arbiter_resp # // Multi-thread response arbiter ( .C_FAMILY (C_FAMILY), .C_NUM_S (C_NUM_M+1), .C_NUM_S_LOG (P_NUM_M_DE_LOG), .C_GRANT_ENC (1), .C_GRANT_HOT (0) ) arbiter_resp_inst ( .ACLK (ACLK), .ARESET (ARESET), .S_VALID (m_rvalid_qual), .S_READY (m_rready_arb), .M_GRANT_HOT (), .M_GRANT_ENC (resp_select), .M_VALID (s_rvalid_i), .M_READY (S_RREADY) ); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_multi_thread ( .S (resp_select), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1'b1) ); assign any_push = M_AREADY; assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i; assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop; // Allow next push if a transaction is currently being completed assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit; // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads. assign any_aid_match = |aid_match; assign any_rid_match = |rid_match; assign accum_push[0] = 1'b0; always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 0; end else begin if (any_push & ~any_pop) begin accept_cnt <= accept_cnt + 1; end else if (any_pop & ~any_push & (accept_cnt != 0)) begin accept_cnt <= accept_cnt - 1; end end end // Clocked process for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0); assign aid_match[gen_thread] = // The currect thread is active for the requested transaction if thread_valid[gen_thread] && // this thread slot is not vacant, and ((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); // the requested ID matches the active ID for this thread. assign s_avalid_en[gen_thread] = // The current request is qualified against this thread slot if (~aid_match[gen_thread]) || // This thread slot is not active for the requested ID, or ((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) && // this outstanding transaction was to the same target and (m_aregion_i == active_region[gen_thread*8+:4])); // to the same region. // cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot. assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread]; assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread])); // cmd_pop points to the position of the active thread that matches the current RID. assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread]; always @(posedge ACLK) begin if (ARESET) begin active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0; active_target[gen_thread*8+:8] <= 0; active_region[gen_thread*8+:8] <= 0; active_cnt[gen_thread*8+:8] <= 0; end else begin if (cmd_push[gen_thread]) begin active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0]; active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i; active_region[gen_thread*8+:4] <= m_aregion_i; if (~cmd_pop[gen_thread]) begin active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1; end end else if (cmd_pop[gen_thread]) begin active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1; end end end // Clocked process if (C_DEBUG) begin : gen_debug_r_multi_thread // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin if (s_rlast_i) begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end else begin debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1; end end end else begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_multi_thread ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push[gen_thread]), .S_READY (), .M_MESG (debug_r_trans_seq_i[gen_thread*8+:8]), .M_VALID (), .M_READY (cmd_pop[gen_thread]) ); end // gen_debug_r_multi_thread end // Next gen_thread_loop end // thread control endgenerate endmodule `default_nettype wire
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Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: si_transactor.v // // Description: // This module manages multi-threaded transactions for one SI-slot. // The module interface consists of a 1-slave to 1-master address channel, plus a // (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel. // The module maintains transaction thread control registers that count the // number of outstanding transations for each thread and the target MI-slot. // On the address channel, the module decodes addresses to select among MI-slots // accessible to the SI-slot where it is instantiated. // It then qualifies whether each received transaction // should be propagated as a request to the address channel arbiter. // Transactions are blocked while there is any outstanding transaction to a // different slave (MI-slot) for the requested ID thread (for deadlock avoidance). // On the response channel, the module mulitplexes transfers from each of the // MI-slots whenever a transfer targets the ID of an active thread, // arbitrating between MI-slots if multiple threads respond concurrently. // //-------------------------------------------------------------------------- // // Structure: // si_transactor // addr_decoder // comparator_static // mux_enc // axic_srl_fifo // arbiter_resp // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_si_transactor # ( parameter C_FAMILY = "none", parameter integer C_SI = 0, // SI-slot number of current instance. parameter integer C_DIR = 0, // Direction: 0 = Write; 1 = Read. parameter integer C_NUM_ADDR_RANGES = 1, parameter integer C_NUM_M = 2, parameter integer C_NUM_M_LOG = 1, parameter integer C_ACCEPTANCE = 1, // Acceptance limit of this SI-slot. parameter integer C_ACCEPTANCE_LOG = 0, // Width of acceptance counter for this SI-slot. parameter integer C_ID_WIDTH = 1, parameter integer C_THREAD_ID_WIDTH = 0, parameter integer C_ADDR_WIDTH = 32, parameter integer C_AMESG_WIDTH = 1, // Used for AW or AR channel payload, depending on instantiation. parameter integer C_RMESG_WIDTH = 1, // Used for B or R channel payload, depending on instantiation. parameter [C_ID_WIDTH-1:0] C_BASE_ID = {C_ID_WIDTH{1'b0}}, parameter [C_ID_WIDTH-1:0] C_HIGH_ID = {C_ID_WIDTH{1'b0}}, parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}}, parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}}, parameter integer C_SINGLE_THREAD = 0, parameter [C_NUM_M-1:0] C_TARGET_QUAL = {C_NUM_M{1'b1}}, parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE = {C_NUM_M{32'h00000000}}, parameter integer C_RANGE_CHECK = 0, parameter integer C_ADDR_DECODE =0, parameter [C_NUM_M*32-1:0] C_ERR_MODE = {C_NUM_M{32'h00000000}}, parameter integer C_DEBUG = 1 ) ( // Global Signals input wire ACLK, input wire ARESET, // Slave Address Channel Interface Ports input wire [C_ID_WIDTH-1:0] S_AID, input wire [C_ADDR_WIDTH-1:0] S_AADDR, input wire [8-1:0] S_ALEN, input wire [3-1:0] S_ASIZE, input wire [2-1:0] S_ABURST, input wire [2-1:0] S_ALOCK, input wire [3-1:0] S_APROT, // input wire [4-1:0] S_AREGION, input wire [C_AMESG_WIDTH-1:0] S_AMESG, input wire S_AVALID, output wire S_AREADY, // Master Address Channel Interface Ports output wire [C_ID_WIDTH-1:0] M_AID, output wire [C_ADDR_WIDTH-1:0] M_AADDR, output wire [8-1:0] M_ALEN, output wire [3-1:0] M_ASIZE, output wire [2-1:0] M_ALOCK, output wire [3-1:0] M_APROT, output wire [4-1:0] M_AREGION, output wire [C_AMESG_WIDTH-1:0] M_AMESG, output wire [(C_NUM_M+1)-1:0] M_ATARGET_HOT, output wire [(C_NUM_M_LOG+1)-1:0] M_ATARGET_ENC, output wire [7:0] M_AERROR, output wire M_AVALID_QUAL, output wire M_AVALID, input wire M_AREADY, // Slave Response Channel Interface Ports output wire [C_ID_WIDTH-1:0] S_RID, output wire [C_RMESG_WIDTH-1:0] S_RMESG, output wire S_RLAST, output wire S_RVALID, input wire S_RREADY, // Master Response Channel Interface Ports input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0] M_RID, input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0] M_RMESG, input wire [(C_NUM_M+1)-1:0] M_RLAST, input wire [(C_NUM_M+1)-1:0] M_RVALID, output wire [(C_NUM_M+1)-1:0] M_RREADY, input wire [(C_NUM_M+1)-1:0] M_RTARGET, // Does response ID from each MI-slot target this SI slot? input wire [8-1:0] DEBUG_A_TRANS_SEQ ); localparam integer P_WRITE = 0; localparam integer P_READ = 1; localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1; localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001; localparam integer P_NONSECURE_BIT = 1; localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1; localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0); // Mask of AxiLite MI-slots localparam [1:0] P_FIXED = 2'b00; localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1); localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1; localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH; localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE; localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots // Ceiling of log2(x) function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2**acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // AxiLite protocol flag vector function [C_NUM_M-1:0] f_m_axilite ( input integer null_arg ); integer mi; begin for (mi=0; mi<C_NUM_M; mi=mi+1) begin f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE); end end endfunction // Convert Bit32 vector of range [0,1] to Bit1 vector on MI function [C_NUM_M-1:0] f_bit32to1_mi (input [C_NUM_M*32-1:0] vec32); integer mi; begin for (mi=0; mi<C_NUM_M; mi=mi+1) begin f_bit32to1_mi[mi] = vec32[mi*32]; end end endfunction wire [C_NUM_M-1:0] target_mi_hot; wire [P_NUM_M_LOG_M1-1:0] target_mi_enc; wire [(C_NUM_M+1)-1:0] m_atarget_hot_i; wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i; wire match; wire [3:0] target_region; wire [3:0] m_aregion_i; wire m_avalid_i; wire s_aready_i; wire any_error; wire s_rvalid_i; wire [C_ID_WIDTH-1:0] s_rid_i; wire s_rlast_i; wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg; wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg; wire [(C_NUM_M+1)-1:0] m_rvalid_qual; wire [(C_NUM_M+1)-1:0] m_rready_arb; wire [(C_NUM_M+1)-1:0] m_rready_i; wire target_secure; wire target_axilite; wire m_avalid_qual_i; wire [7:0] m_aerror_i; genvar gen_mi; genvar gen_thread; generate if (C_ADDR_DECODE) begin : gen_addr_decoder axi_crossbar_v2_1_addr_decoder # ( .C_FAMILY (C_FAMILY), .C_NUM_TARGETS (C_NUM_M), .C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1), .C_NUM_RANGES (C_NUM_ADDR_RANGES), .C_ADDR_WIDTH (C_ADDR_WIDTH), .C_TARGET_ENC (1), .C_TARGET_HOT (1), .C_REGION_ENC (1), .C_BASE_ADDR (C_BASE_ADDR), .C_HIGH_ADDR (C_HIGH_ADDR), .C_TARGET_QUAL (C_TARGET_QUAL), .C_RESOLUTION (2) ) addr_decoder_inst ( .ADDR (S_AADDR), .TARGET_HOT (target_mi_hot), .TARGET_ENC (target_mi_enc), .MATCH (match), .REGION (target_region) ); end else begin : gen_no_addr_decoder assign target_mi_hot = 1; assign target_mi_enc = 0; assign match = 1'b1; assign target_region = 4'b0000; end endgenerate assign target_secure = |(target_mi_hot & P_M_SECURE_MASK); assign target_axilite = |(target_mi_hot & P_M_AXILITE); assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition. assign m_aerror_i[0] = ~match; // Invalid target address assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) || (S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1)); // AxiLite access violation assign m_aerror_i[7:3] = 5'b00000; // Reserved assign M_ATARGET_HOT = m_atarget_hot_i; assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot}); assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc); assign M_AVALID = m_avalid_i; assign m_avalid_i = S_AVALID; assign M_AVALID_QUAL = m_avalid_qual_i; assign S_AREADY = s_aready_i; assign s_aready_i = M_AREADY; assign M_AERROR = m_aerror_i; assign M_ATARGET_ENC = m_atarget_enc_i; assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000; // assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION; assign M_AREGION = m_aregion_i; assign M_AID = S_AID; assign M_AADDR = S_AADDR; assign M_ALEN = S_ALEN; assign M_ASIZE = S_ASIZE; assign M_ALOCK = S_ALOCK; assign M_APROT = S_APROT; assign M_AMESG = S_AMESG; assign S_RVALID = s_rvalid_i; assign M_RREADY = m_rready_i; assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH]; assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH]; assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1]; assign S_RID = s_rid_i; assign S_RLAST = s_rlast_i; assign m_rvalid_qual = M_RVALID & M_RTARGET; assign m_rready_i = m_rready_arb & M_RTARGET; generate for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order. assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = { M_RLAST[gen_mi], M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH], M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH] }; end // gen_rmesg_mi if (C_ACCEPTANCE == 1) begin : gen_single_issue wire cmd_push; wire cmd_pop; reg [(C_NUM_M+1)-1:0] active_target_hot; reg [P_NUM_M_DE_LOG-1:0] active_target_enc; reg accept_cnt; reg [8-1:0] debug_r_beat_cnt_i; wire [8-1:0] debug_r_trans_seq_i; assign cmd_push = M_AREADY; assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst assign m_avalid_qual_i = ~accept_cnt | cmd_pop; // Ready for arbitration if no outstanding transaction or transaction being completed always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 1'b0; active_target_enc <= 0; active_target_hot <= 0; end else begin if (cmd_push) begin active_target_enc <= m_atarget_enc_i; active_target_hot <= m_atarget_hot_i; accept_cnt <= 1'b1; end else if (cmd_pop) begin accept_cnt <= 1'b0; end end end // Clocked process assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}}; assign s_rvalid_i = |(active_target_hot & m_rvalid_qual); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_single_issue ( .S (active_target_enc), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1'b1) ); if (C_DEBUG) begin : gen_debug_r_single_issue // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i && S_RREADY) begin if (s_rlast_i) begin debug_r_beat_cnt_i <= 0; end else begin debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1; end end end else begin debug_r_beat_cnt_i <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_single_issue ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push), .S_READY (), .M_MESG (debug_r_trans_seq_i), .M_VALID (), .M_READY (cmd_pop) ); end // gen_debug_r end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread wire s_avalid_en; wire cmd_push; wire cmd_pop; reg [C_ID_WIDTH-1:0] active_id; reg [(C_NUM_M+1)-1:0] active_target_hot; reg [P_NUM_M_DE_LOG-1:0] active_target_enc; reg [4-1:0] active_region; reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt; reg [8-1:0] debug_r_beat_cnt_i; wire [8-1:0] debug_r_trans_seq_i; wire accept_limit ; // Implement single-region-per-ID cyclic dependency avoidance method. assign s_avalid_en = // This transaction is qualified to request arbitration if ... (accept_cnt == 0) || // Either there are no outstanding transactions, or ... (((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) && // the current transaction ID matches the previous, and ... (active_target_enc == m_atarget_enc_i) && // all outstanding transactions are to the same target MI ... (active_region == m_aregion_i)); // and to the same REGION. assign cmd_push = M_AREADY; assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop; // Allow next push if a transaction is currently being completed assign m_avalid_qual_i = s_avalid_en & ~accept_limit; always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 0; active_id <= 0; active_target_enc <= 0; active_target_hot <= 0; active_region <= 0; end else begin if (cmd_push) begin active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0]; active_target_enc <= m_atarget_enc_i; active_target_hot <= m_atarget_hot_i; active_region <= m_aregion_i; if (~cmd_pop) begin accept_cnt <= accept_cnt + 1; end end else begin if (cmd_pop & (accept_cnt != 0)) begin accept_cnt <= accept_cnt - 1; end end end end // Clocked process assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}}; assign s_rvalid_i = |(active_target_hot & m_rvalid_qual); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_single_thread ( .S (active_target_enc), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1'b1) ); if (C_DEBUG) begin : gen_debug_r_single_thread // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i && S_RREADY) begin if (s_rlast_i) begin debug_r_beat_cnt_i <= 0; end else begin debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1; end end end else begin debug_r_beat_cnt_i <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_single_thread ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push), .S_READY (), .M_MESG (debug_r_trans_seq_i), .M_VALID (), .M_READY (cmd_pop) ); end // gen_debug_r end else begin : gen_multi_thread wire [(P_NUM_M_DE_LOG)-1:0] resp_select; reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt; wire [P_NUM_THREADS-1:0] s_avalid_en; wire [P_NUM_THREADS-1:0] thread_valid; wire [P_NUM_THREADS-1:0] aid_match; wire [P_NUM_THREADS-1:0] rid_match; wire [P_NUM_THREADS-1:0] cmd_push; wire [P_NUM_THREADS-1:0] cmd_pop; wire [P_NUM_THREADS:0] accum_push; reg [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id; reg [P_NUM_THREADS*8-1:0] active_target; reg [P_NUM_THREADS*8-1:0] active_region; reg [P_NUM_THREADS*8-1:0] active_cnt; reg [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i; wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i; wire any_aid_match; wire any_rid_match; wire accept_limit; wire any_push; wire any_pop; axi_crossbar_v2_1_arbiter_resp # // Multi-thread response arbiter ( .C_FAMILY (C_FAMILY), .C_NUM_S (C_NUM_M+1), .C_NUM_S_LOG (P_NUM_M_DE_LOG), .C_GRANT_ENC (1), .C_GRANT_HOT (0) ) arbiter_resp_inst ( .ACLK (ACLK), .ARESET (ARESET), .S_VALID (m_rvalid_qual), .S_READY (m_rready_arb), .M_GRANT_HOT (), .M_GRANT_ENC (resp_select), .M_VALID (s_rvalid_i), .M_READY (S_RREADY) ); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_multi_thread ( .S (resp_select), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1'b1) ); assign any_push = M_AREADY; assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i; assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop; // Allow next push if a transaction is currently being completed assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit; // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads. assign any_aid_match = |aid_match; assign any_rid_match = |rid_match; assign accum_push[0] = 1'b0; always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 0; end else begin if (any_push & ~any_pop) begin accept_cnt <= accept_cnt + 1; end else if (any_pop & ~any_push & (accept_cnt != 0)) begin accept_cnt <= accept_cnt - 1; end end end // Clocked process for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0); assign aid_match[gen_thread] = // The currect thread is active for the requested transaction if thread_valid[gen_thread] && // this thread slot is not vacant, and ((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); // the requested ID matches the active ID for this thread. assign s_avalid_en[gen_thread] = // The current request is qualified against this thread slot if (~aid_match[gen_thread]) || // This thread slot is not active for the requested ID, or ((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) && // this outstanding transaction was to the same target and (m_aregion_i == active_region[gen_thread*8+:4])); // to the same region. // cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot. assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread]; assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread])); // cmd_pop points to the position of the active thread that matches the current RID. assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread]; always @(posedge ACLK) begin if (ARESET) begin active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0; active_target[gen_thread*8+:8] <= 0; active_region[gen_thread*8+:8] <= 0; active_cnt[gen_thread*8+:8] <= 0; end else begin if (cmd_push[gen_thread]) begin active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0]; active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i; active_region[gen_thread*8+:4] <= m_aregion_i; if (~cmd_pop[gen_thread]) begin active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1; end end else if (cmd_pop[gen_thread]) begin active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1; end end end // Clocked process if (C_DEBUG) begin : gen_debug_r_multi_thread // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin if (s_rlast_i) begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end else begin debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1; end end end else begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_multi_thread ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push[gen_thread]), .S_READY (), .M_MESG (debug_r_trans_seq_i[gen_thread*8+:8]), .M_VALID (), .M_READY (cmd_pop[gen_thread]) ); end // gen_debug_r_multi_thread end // Next gen_thread_loop end // thread control endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: si_transactor.v // // Description: // This module manages multi-threaded transactions for one SI-slot. // The module interface consists of a 1-slave to 1-master address channel, plus a // (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel. // The module maintains transaction thread control registers that count the // number of outstanding transations for each thread and the target MI-slot. // On the address channel, the module decodes addresses to select among MI-slots // accessible to the SI-slot where it is instantiated. // It then qualifies whether each received transaction // should be propagated as a request to the address channel arbiter. // Transactions are blocked while there is any outstanding transaction to a // different slave (MI-slot) for the requested ID thread (for deadlock avoidance). // On the response channel, the module mulitplexes transfers from each of the // MI-slots whenever a transfer targets the ID of an active thread, // arbitrating between MI-slots if multiple threads respond concurrently. // //-------------------------------------------------------------------------- // // Structure: // si_transactor // addr_decoder // comparator_static // mux_enc // axic_srl_fifo // arbiter_resp // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_si_transactor # ( parameter C_FAMILY = "none", parameter integer C_SI = 0, // SI-slot number of current instance. parameter integer C_DIR = 0, // Direction: 0 = Write; 1 = Read. parameter integer C_NUM_ADDR_RANGES = 1, parameter integer C_NUM_M = 2, parameter integer C_NUM_M_LOG = 1, parameter integer C_ACCEPTANCE = 1, // Acceptance limit of this SI-slot. parameter integer C_ACCEPTANCE_LOG = 0, // Width of acceptance counter for this SI-slot. parameter integer C_ID_WIDTH = 1, parameter integer C_THREAD_ID_WIDTH = 0, parameter integer C_ADDR_WIDTH = 32, parameter integer C_AMESG_WIDTH = 1, // Used for AW or AR channel payload, depending on instantiation. parameter integer C_RMESG_WIDTH = 1, // Used for B or R channel payload, depending on instantiation. parameter [C_ID_WIDTH-1:0] C_BASE_ID = {C_ID_WIDTH{1'b0}}, parameter [C_ID_WIDTH-1:0] C_HIGH_ID = {C_ID_WIDTH{1'b0}}, parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}}, parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}}, parameter integer C_SINGLE_THREAD = 0, parameter [C_NUM_M-1:0] C_TARGET_QUAL = {C_NUM_M{1'b1}}, parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE = {C_NUM_M{32'h00000000}}, parameter integer C_RANGE_CHECK = 0, parameter integer C_ADDR_DECODE =0, parameter [C_NUM_M*32-1:0] C_ERR_MODE = {C_NUM_M{32'h00000000}}, parameter integer C_DEBUG = 1 ) ( // Global Signals input wire ACLK, input wire ARESET, // Slave Address Channel Interface Ports input wire [C_ID_WIDTH-1:0] S_AID, input wire [C_ADDR_WIDTH-1:0] S_AADDR, input wire [8-1:0] S_ALEN, input wire [3-1:0] S_ASIZE, input wire [2-1:0] S_ABURST, input wire [2-1:0] S_ALOCK, input wire [3-1:0] S_APROT, // input wire [4-1:0] S_AREGION, input wire [C_AMESG_WIDTH-1:0] S_AMESG, input wire S_AVALID, output wire S_AREADY, // Master Address Channel Interface Ports output wire [C_ID_WIDTH-1:0] M_AID, output wire [C_ADDR_WIDTH-1:0] M_AADDR, output wire [8-1:0] M_ALEN, output wire [3-1:0] M_ASIZE, output wire [2-1:0] M_ALOCK, output wire [3-1:0] M_APROT, output wire [4-1:0] M_AREGION, output wire [C_AMESG_WIDTH-1:0] M_AMESG, output wire [(C_NUM_M+1)-1:0] M_ATARGET_HOT, output wire [(C_NUM_M_LOG+1)-1:0] M_ATARGET_ENC, output wire [7:0] M_AERROR, output wire M_AVALID_QUAL, output wire M_AVALID, input wire M_AREADY, // Slave Response Channel Interface Ports output wire [C_ID_WIDTH-1:0] S_RID, output wire [C_RMESG_WIDTH-1:0] S_RMESG, output wire S_RLAST, output wire S_RVALID, input wire S_RREADY, // Master Response Channel Interface Ports input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0] M_RID, input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0] M_RMESG, input wire [(C_NUM_M+1)-1:0] M_RLAST, input wire [(C_NUM_M+1)-1:0] M_RVALID, output wire [(C_NUM_M+1)-1:0] M_RREADY, input wire [(C_NUM_M+1)-1:0] M_RTARGET, // Does response ID from each MI-slot target this SI slot? input wire [8-1:0] DEBUG_A_TRANS_SEQ ); localparam integer P_WRITE = 0; localparam integer P_READ = 1; localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1; localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001; localparam integer P_NONSECURE_BIT = 1; localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1; localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0); // Mask of AxiLite MI-slots localparam [1:0] P_FIXED = 2'b00; localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1); localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1; localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH; localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE; localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots // Ceiling of log2(x) function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2**acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // AxiLite protocol flag vector function [C_NUM_M-1:0] f_m_axilite ( input integer null_arg ); integer mi; begin for (mi=0; mi<C_NUM_M; mi=mi+1) begin f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE); end end endfunction // Convert Bit32 vector of range [0,1] to Bit1 vector on MI function [C_NUM_M-1:0] f_bit32to1_mi (input [C_NUM_M*32-1:0] vec32); integer mi; begin for (mi=0; mi<C_NUM_M; mi=mi+1) begin f_bit32to1_mi[mi] = vec32[mi*32]; end end endfunction wire [C_NUM_M-1:0] target_mi_hot; wire [P_NUM_M_LOG_M1-1:0] target_mi_enc; wire [(C_NUM_M+1)-1:0] m_atarget_hot_i; wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i; wire match; wire [3:0] target_region; wire [3:0] m_aregion_i; wire m_avalid_i; wire s_aready_i; wire any_error; wire s_rvalid_i; wire [C_ID_WIDTH-1:0] s_rid_i; wire s_rlast_i; wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg; wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg; wire [(C_NUM_M+1)-1:0] m_rvalid_qual; wire [(C_NUM_M+1)-1:0] m_rready_arb; wire [(C_NUM_M+1)-1:0] m_rready_i; wire target_secure; wire target_axilite; wire m_avalid_qual_i; wire [7:0] m_aerror_i; genvar gen_mi; genvar gen_thread; generate if (C_ADDR_DECODE) begin : gen_addr_decoder axi_crossbar_v2_1_addr_decoder # ( .C_FAMILY (C_FAMILY), .C_NUM_TARGETS (C_NUM_M), .C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1), .C_NUM_RANGES (C_NUM_ADDR_RANGES), .C_ADDR_WIDTH (C_ADDR_WIDTH), .C_TARGET_ENC (1), .C_TARGET_HOT (1), .C_REGION_ENC (1), .C_BASE_ADDR (C_BASE_ADDR), .C_HIGH_ADDR (C_HIGH_ADDR), .C_TARGET_QUAL (C_TARGET_QUAL), .C_RESOLUTION (2) ) addr_decoder_inst ( .ADDR (S_AADDR), .TARGET_HOT (target_mi_hot), .TARGET_ENC (target_mi_enc), .MATCH (match), .REGION (target_region) ); end else begin : gen_no_addr_decoder assign target_mi_hot = 1; assign target_mi_enc = 0; assign match = 1'b1; assign target_region = 4'b0000; end endgenerate assign target_secure = |(target_mi_hot & P_M_SECURE_MASK); assign target_axilite = |(target_mi_hot & P_M_AXILITE); assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition. assign m_aerror_i[0] = ~match; // Invalid target address assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) || (S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1)); // AxiLite access violation assign m_aerror_i[7:3] = 5'b00000; // Reserved assign M_ATARGET_HOT = m_atarget_hot_i; assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot}); assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc); assign M_AVALID = m_avalid_i; assign m_avalid_i = S_AVALID; assign M_AVALID_QUAL = m_avalid_qual_i; assign S_AREADY = s_aready_i; assign s_aready_i = M_AREADY; assign M_AERROR = m_aerror_i; assign M_ATARGET_ENC = m_atarget_enc_i; assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000; // assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION; assign M_AREGION = m_aregion_i; assign M_AID = S_AID; assign M_AADDR = S_AADDR; assign M_ALEN = S_ALEN; assign M_ASIZE = S_ASIZE; assign M_ALOCK = S_ALOCK; assign M_APROT = S_APROT; assign M_AMESG = S_AMESG; assign S_RVALID = s_rvalid_i; assign M_RREADY = m_rready_i; assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH]; assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH]; assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1]; assign S_RID = s_rid_i; assign S_RLAST = s_rlast_i; assign m_rvalid_qual = M_RVALID & M_RTARGET; assign m_rready_i = m_rready_arb & M_RTARGET; generate for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order. assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = { M_RLAST[gen_mi], M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH], M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH] }; end // gen_rmesg_mi if (C_ACCEPTANCE == 1) begin : gen_single_issue wire cmd_push; wire cmd_pop; reg [(C_NUM_M+1)-1:0] active_target_hot; reg [P_NUM_M_DE_LOG-1:0] active_target_enc; reg accept_cnt; reg [8-1:0] debug_r_beat_cnt_i; wire [8-1:0] debug_r_trans_seq_i; assign cmd_push = M_AREADY; assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst assign m_avalid_qual_i = ~accept_cnt | cmd_pop; // Ready for arbitration if no outstanding transaction or transaction being completed always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 1'b0; active_target_enc <= 0; active_target_hot <= 0; end else begin if (cmd_push) begin active_target_enc <= m_atarget_enc_i; active_target_hot <= m_atarget_hot_i; accept_cnt <= 1'b1; end else if (cmd_pop) begin accept_cnt <= 1'b0; end end end // Clocked process assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}}; assign s_rvalid_i = |(active_target_hot & m_rvalid_qual); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_single_issue ( .S (active_target_enc), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1'b1) ); if (C_DEBUG) begin : gen_debug_r_single_issue // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i && S_RREADY) begin if (s_rlast_i) begin debug_r_beat_cnt_i <= 0; end else begin debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1; end end end else begin debug_r_beat_cnt_i <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_single_issue ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push), .S_READY (), .M_MESG (debug_r_trans_seq_i), .M_VALID (), .M_READY (cmd_pop) ); end // gen_debug_r end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread wire s_avalid_en; wire cmd_push; wire cmd_pop; reg [C_ID_WIDTH-1:0] active_id; reg [(C_NUM_M+1)-1:0] active_target_hot; reg [P_NUM_M_DE_LOG-1:0] active_target_enc; reg [4-1:0] active_region; reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt; reg [8-1:0] debug_r_beat_cnt_i; wire [8-1:0] debug_r_trans_seq_i; wire accept_limit ; // Implement single-region-per-ID cyclic dependency avoidance method. assign s_avalid_en = // This transaction is qualified to request arbitration if ... (accept_cnt == 0) || // Either there are no outstanding transactions, or ... (((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) && // the current transaction ID matches the previous, and ... (active_target_enc == m_atarget_enc_i) && // all outstanding transactions are to the same target MI ... (active_region == m_aregion_i)); // and to the same REGION. assign cmd_push = M_AREADY; assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop; // Allow next push if a transaction is currently being completed assign m_avalid_qual_i = s_avalid_en & ~accept_limit; always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 0; active_id <= 0; active_target_enc <= 0; active_target_hot <= 0; active_region <= 0; end else begin if (cmd_push) begin active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0]; active_target_enc <= m_atarget_enc_i; active_target_hot <= m_atarget_hot_i; active_region <= m_aregion_i; if (~cmd_pop) begin accept_cnt <= accept_cnt + 1; end end else begin if (cmd_pop & (accept_cnt != 0)) begin accept_cnt <= accept_cnt - 1; end end end end // Clocked process assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}}; assign s_rvalid_i = |(active_target_hot & m_rvalid_qual); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_single_thread ( .S (active_target_enc), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1'b1) ); if (C_DEBUG) begin : gen_debug_r_single_thread // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i && S_RREADY) begin if (s_rlast_i) begin debug_r_beat_cnt_i <= 0; end else begin debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1; end end end else begin debug_r_beat_cnt_i <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_single_thread ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push), .S_READY (), .M_MESG (debug_r_trans_seq_i), .M_VALID (), .M_READY (cmd_pop) ); end // gen_debug_r end else begin : gen_multi_thread wire [(P_NUM_M_DE_LOG)-1:0] resp_select; reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt; wire [P_NUM_THREADS-1:0] s_avalid_en; wire [P_NUM_THREADS-1:0] thread_valid; wire [P_NUM_THREADS-1:0] aid_match; wire [P_NUM_THREADS-1:0] rid_match; wire [P_NUM_THREADS-1:0] cmd_push; wire [P_NUM_THREADS-1:0] cmd_pop; wire [P_NUM_THREADS:0] accum_push; reg [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id; reg [P_NUM_THREADS*8-1:0] active_target; reg [P_NUM_THREADS*8-1:0] active_region; reg [P_NUM_THREADS*8-1:0] active_cnt; reg [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i; wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i; wire any_aid_match; wire any_rid_match; wire accept_limit; wire any_push; wire any_pop; axi_crossbar_v2_1_arbiter_resp # // Multi-thread response arbiter ( .C_FAMILY (C_FAMILY), .C_NUM_S (C_NUM_M+1), .C_NUM_S_LOG (P_NUM_M_DE_LOG), .C_GRANT_ENC (1), .C_GRANT_HOT (0) ) arbiter_resp_inst ( .ACLK (ACLK), .ARESET (ARESET), .S_VALID (m_rvalid_qual), .S_READY (m_rready_arb), .M_GRANT_HOT (), .M_GRANT_ENC (resp_select), .M_VALID (s_rvalid_i), .M_READY (S_RREADY) ); generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY (C_FAMILY), .C_RATIO (C_NUM_M+1), .C_SEL_WIDTH (P_NUM_M_DE_LOG), .C_DATA_WIDTH (P_RMUX_MESG_WIDTH) ) mux_resp_multi_thread ( .S (resp_select), .A (mi_rmux_mesg), .O (si_rmux_mesg), .OE (1'b1) ); assign any_push = M_AREADY; assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i; assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop; // Allow next push if a transaction is currently being completed assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit; // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads. assign any_aid_match = |aid_match; assign any_rid_match = |rid_match; assign accum_push[0] = 1'b0; always @(posedge ACLK) begin if (ARESET) begin accept_cnt <= 0; end else begin if (any_push & ~any_pop) begin accept_cnt <= accept_cnt + 1; end else if (any_pop & ~any_push & (accept_cnt != 0)) begin accept_cnt <= accept_cnt - 1; end end end // Clocked process for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0); assign aid_match[gen_thread] = // The currect thread is active for the requested transaction if thread_valid[gen_thread] && // this thread slot is not vacant, and ((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); // the requested ID matches the active ID for this thread. assign s_avalid_en[gen_thread] = // The current request is qualified against this thread slot if (~aid_match[gen_thread]) || // This thread slot is not active for the requested ID, or ((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) && // this outstanding transaction was to the same target and (m_aregion_i == active_region[gen_thread*8+:4])); // to the same region. // cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot. assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread]; assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread])); // cmd_pop points to the position of the active thread that matches the current RID. assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread]; always @(posedge ACLK) begin if (ARESET) begin active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0; active_target[gen_thread*8+:8] <= 0; active_region[gen_thread*8+:8] <= 0; active_cnt[gen_thread*8+:8] <= 0; end else begin if (cmd_push[gen_thread]) begin active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0]; active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i; active_region[gen_thread*8+:4] <= m_aregion_i; if (~cmd_pop[gen_thread]) begin active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1; end end else if (cmd_pop[gen_thread]) begin active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1; end end end // Clocked process if (C_DEBUG) begin : gen_debug_r_multi_thread // DEBUG READ BEAT COUNTER (only meaningful for R-channel) always @(posedge ACLK) begin if (ARESET) begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end else if (C_DIR == P_READ) begin if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin if (s_rlast_i) begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end else begin debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1; end end end else begin debug_r_beat_cnt_i[gen_thread*8+:8] <= 0; end end // Clocked process // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO axi_data_fifo_v2_1_axic_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (8), .C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1), .C_USE_FULL (0) ) debug_r_seq_fifo_multi_thread ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (DEBUG_A_TRANS_SEQ), .S_VALID (cmd_push[gen_thread]), .S_READY (), .M_MESG (debug_r_trans_seq_i[gen_thread*8+:8]), .M_VALID (), .M_READY (cmd_pop[gen_thread]) ); end // gen_debug_r_multi_thread end // Next gen_thread_loop end // thread control endgenerate endmodule `default_nettype wire
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_interconnect_model.v * * Date : 2012-11 * * Description : Mimics Top_interconnect Switch. * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_interconnect_model ( rstn, sw_clk, w_qos_gp0, w_qos_gp1, w_qos_hp0, w_qos_hp1, w_qos_hp2, w_qos_hp3, r_qos_gp0, r_qos_gp1, r_qos_hp0, r_qos_hp1, r_qos_hp2, r_qos_hp3, wr_ack_ddr_gp0, wr_ack_ocm_gp0, wr_data_gp0, wr_addr_gp0, wr_bytes_gp0, wr_dv_ddr_gp0, wr_dv_ocm_gp0, rd_req_ddr_gp0, rd_req_ocm_gp0, rd_req_reg_gp0, rd_addr_gp0, rd_bytes_gp0, rd_data_ddr_gp0, rd_data_ocm_gp0, rd_data_reg_gp0, rd_dv_ddr_gp0, rd_dv_ocm_gp0, rd_dv_reg_gp0, wr_ack_ddr_gp1, wr_ack_ocm_gp1, wr_data_gp1, wr_addr_gp1, wr_bytes_gp1, wr_dv_ddr_gp1, wr_dv_ocm_gp1, rd_req_ddr_gp1, rd_req_ocm_gp1, rd_req_reg_gp1, rd_addr_gp1, rd_bytes_gp1, rd_data_ddr_gp1, rd_data_ocm_gp1, rd_data_reg_gp1, rd_dv_ddr_gp1, rd_dv_ocm_gp1, rd_dv_reg_gp1, wr_ack_ddr_hp0, wr_ack_ocm_hp0, wr_data_hp0, wr_addr_hp0, wr_bytes_hp0, wr_dv_ddr_hp0, wr_dv_ocm_hp0, rd_req_ddr_hp0, rd_req_ocm_hp0, rd_addr_hp0, rd_bytes_hp0, rd_data_ddr_hp0, rd_data_ocm_hp0, rd_dv_ddr_hp0, rd_dv_ocm_hp0, wr_ack_ddr_hp1, wr_ack_ocm_hp1, wr_data_hp1, wr_addr_hp1, wr_bytes_hp1, wr_dv_ddr_hp1, wr_dv_ocm_hp1, rd_req_ddr_hp1, rd_req_ocm_hp1, rd_addr_hp1, rd_bytes_hp1, rd_data_ddr_hp1, rd_data_ocm_hp1, rd_dv_ddr_hp1, rd_dv_ocm_hp1, wr_ack_ddr_hp2, wr_ack_ocm_hp2, wr_data_hp2, wr_addr_hp2, wr_bytes_hp2, wr_dv_ddr_hp2, wr_dv_ocm_hp2, rd_req_ddr_hp2, rd_req_ocm_hp2, rd_addr_hp2, rd_bytes_hp2, rd_data_ddr_hp2, rd_data_ocm_hp2, rd_dv_ddr_hp2, rd_dv_ocm_hp2, wr_ack_ddr_hp3, wr_ack_ocm_hp3, wr_data_hp3, wr_addr_hp3, wr_bytes_hp3, wr_dv_ddr_hp3, wr_dv_ocm_hp3, rd_req_ddr_hp3, rd_req_ocm_hp3, rd_addr_hp3, rd_bytes_hp3, rd_data_ddr_hp3, rd_data_ocm_hp3, rd_dv_ddr_hp3, rd_dv_ocm_hp3, /* Goes to port 1 of DDR */ ddr_wr_ack_port1, ddr_wr_dv_port1, ddr_rd_req_port1, ddr_rd_dv_port1, ddr_wr_addr_port1, ddr_wr_data_port1, ddr_wr_bytes_port1, ddr_rd_addr_port1, ddr_rd_data_port1, ddr_rd_bytes_port1, ddr_wr_qos_port1, ddr_rd_qos_port1, /* Goes to port2 of DDR */ ddr_wr_ack_port2, ddr_wr_dv_port2, ddr_rd_req_port2, ddr_rd_dv_port2, ddr_wr_addr_port2, ddr_wr_data_port2, ddr_wr_bytes_port2, ddr_rd_addr_port2, ddr_rd_data_port2, ddr_rd_bytes_port2, ddr_wr_qos_port2, ddr_rd_qos_port2, /* Goes to port3 of DDR */ ddr_wr_ack_port3, ddr_wr_dv_port3, ddr_rd_req_port3, ddr_rd_dv_port3, ddr_wr_addr_port3, ddr_wr_data_port3, ddr_wr_bytes_port3, ddr_rd_addr_port3, ddr_rd_data_port3, ddr_rd_bytes_port3, ddr_wr_qos_port3, ddr_rd_qos_port3, /* Goes to port1 of OCM */ ocm_wr_qos_port1, ocm_rd_qos_port1, ocm_wr_dv_port1, ocm_wr_data_port1, ocm_wr_addr_port1, ocm_wr_bytes_port1, ocm_wr_ack_port1, ocm_rd_req_port1, ocm_rd_data_port1, ocm_rd_addr_port1, ocm_rd_bytes_port1, ocm_rd_dv_port1, /* Goes to port1 for RegMap */ reg_rd_qos_port1, reg_rd_req_port1, reg_rd_data_port1, reg_rd_addr_port1, reg_rd_bytes_port1, reg_rd_dv_port1 ); `include "processing_system7_bfm_v2_0_5_local_params.v" input rstn; input sw_clk; input [axi_qos_width-1:0] w_qos_gp0; input [axi_qos_width-1:0] w_qos_gp1; input [axi_qos_width-1:0] w_qos_hp0; input [axi_qos_width-1:0] w_qos_hp1; input [axi_qos_width-1:0] w_qos_hp2; input [axi_qos_width-1:0] w_qos_hp3; input [axi_qos_width-1:0] r_qos_gp0; input [axi_qos_width-1:0] r_qos_gp1; input [axi_qos_width-1:0] r_qos_hp0; input [axi_qos_width-1:0] r_qos_hp1; input [axi_qos_width-1:0] r_qos_hp2; input [axi_qos_width-1:0] r_qos_hp3; output [axi_qos_width-1:0] ocm_wr_qos_port1; output [axi_qos_width-1:0] ocm_rd_qos_port1; output wr_ack_ddr_gp0; output wr_ack_ocm_gp0; input[max_burst_bits-1:0] wr_data_gp0; input[addr_width-1:0] wr_addr_gp0; input[max_burst_bytes_width:0] wr_bytes_gp0; input wr_dv_ddr_gp0; input wr_dv_ocm_gp0; input rd_req_ddr_gp0; input rd_req_ocm_gp0; input rd_req_reg_gp0; input[addr_width-1:0] rd_addr_gp0; input[max_burst_bytes_width:0] rd_bytes_gp0; output[max_burst_bits-1:0] rd_data_ddr_gp0; output[max_burst_bits-1:0] rd_data_ocm_gp0; output[max_burst_bits-1:0] rd_data_reg_gp0; output rd_dv_ddr_gp0; output rd_dv_ocm_gp0; output rd_dv_reg_gp0; output wr_ack_ddr_gp1; output wr_ack_ocm_gp1; input[max_burst_bits-1:0] wr_data_gp1; input[addr_width-1:0] wr_addr_gp1; input[max_burst_bytes_width:0] wr_bytes_gp1; input wr_dv_ddr_gp1; input wr_dv_ocm_gp1; input rd_req_ddr_gp1; input rd_req_ocm_gp1; input rd_req_reg_gp1; input[addr_width-1:0] rd_addr_gp1; input[max_burst_bytes_width:0] rd_bytes_gp1; output[max_burst_bits-1:0] rd_data_ddr_gp1; output[max_burst_bits-1:0] rd_data_ocm_gp1; output[max_burst_bits-1:0] rd_data_reg_gp1; output rd_dv_ddr_gp1; output rd_dv_ocm_gp1; output rd_dv_reg_gp1; output wr_ack_ddr_hp0; output wr_ack_ocm_hp0; input[max_burst_bits-1:0] wr_data_hp0; input[addr_width-1:0] wr_addr_hp0; input[max_burst_bytes_width:0] wr_bytes_hp0; input wr_dv_ddr_hp0; input wr_dv_ocm_hp0; input rd_req_ddr_hp0; input rd_req_ocm_hp0; input[addr_width-1:0] rd_addr_hp0; input[max_burst_bytes_width:0] rd_bytes_hp0; output[max_burst_bits-1:0] rd_data_ddr_hp0; output[max_burst_bits-1:0] rd_data_ocm_hp0; output rd_dv_ddr_hp0; output rd_dv_ocm_hp0; output wr_ack_ddr_hp1; output wr_ack_ocm_hp1; input[max_burst_bits-1:0] wr_data_hp1; input[addr_width-1:0] wr_addr_hp1; input[max_burst_bytes_width:0] wr_bytes_hp1; input wr_dv_ddr_hp1; input wr_dv_ocm_hp1; input rd_req_ddr_hp1; input rd_req_ocm_hp1; input[addr_width-1:0] rd_addr_hp1; input[max_burst_bytes_width:0] rd_bytes_hp1; output[max_burst_bits-1:0] rd_data_ddr_hp1; output[max_burst_bits-1:0] rd_data_ocm_hp1; output rd_dv_ddr_hp1; output rd_dv_ocm_hp1; output wr_ack_ddr_hp2; output wr_ack_ocm_hp2; input[max_burst_bits-1:0] wr_data_hp2; input[addr_width-1:0] wr_addr_hp2; input[max_burst_bytes_width:0] wr_bytes_hp2; input wr_dv_ddr_hp2; input wr_dv_ocm_hp2; input rd_req_ddr_hp2; input rd_req_ocm_hp2; input[addr_width-1:0] rd_addr_hp2; input[max_burst_bytes_width:0] rd_bytes_hp2; output[max_burst_bits-1:0] rd_data_ddr_hp2; output[max_burst_bits-1:0] rd_data_ocm_hp2; output rd_dv_ddr_hp2; output rd_dv_ocm_hp2; output wr_ack_ddr_hp3; output wr_ack_ocm_hp3; input[max_burst_bits-1:0] wr_data_hp3; input[addr_width-1:0] wr_addr_hp3; input[max_burst_bytes_width:0] wr_bytes_hp3; input wr_dv_ddr_hp3; input wr_dv_ocm_hp3; input rd_req_ddr_hp3; input rd_req_ocm_hp3; input[addr_width-1:0] rd_addr_hp3; input[max_burst_bytes_width:0] rd_bytes_hp3; output[max_burst_bits-1:0] rd_data_ddr_hp3; output[max_burst_bits-1:0] rd_data_ocm_hp3; output rd_dv_ddr_hp3; output rd_dv_ocm_hp3; /* Goes to port 1 of DDR */ input ddr_wr_ack_port1; output ddr_wr_dv_port1; output ddr_rd_req_port1; input ddr_rd_dv_port1; output[addr_width-1:0] ddr_wr_addr_port1; output[max_burst_bits-1:0] ddr_wr_data_port1; output[max_burst_bytes_width:0] ddr_wr_bytes_port1; output[addr_width-1:0] ddr_rd_addr_port1; input[max_burst_bits-1:0] ddr_rd_data_port1; output[max_burst_bytes_width:0] ddr_rd_bytes_port1; output [axi_qos_width-1:0] ddr_wr_qos_port1; output [axi_qos_width-1:0] ddr_rd_qos_port1; /* Goes to port2 of DDR */ input ddr_wr_ack_port2; output ddr_wr_dv_port2; output ddr_rd_req_port2; input ddr_rd_dv_port2; output[addr_width-1:0] ddr_wr_addr_port2; output[max_burst_bits-1:0] ddr_wr_data_port2; output[max_burst_bytes_width:0] ddr_wr_bytes_port2; output[addr_width-1:0] ddr_rd_addr_port2; input[max_burst_bits-1:0] ddr_rd_data_port2; output[max_burst_bytes_width:0] ddr_rd_bytes_port2; output [axi_qos_width-1:0] ddr_wr_qos_port2; output [axi_qos_width-1:0] ddr_rd_qos_port2; /* Goes to port3 of DDR */ input ddr_wr_ack_port3; output ddr_wr_dv_port3; output ddr_rd_req_port3; input ddr_rd_dv_port3; output[addr_width-1:0] ddr_wr_addr_port3; output[max_burst_bits-1:0] ddr_wr_data_port3; output[max_burst_bytes_width:0] ddr_wr_bytes_port3; output[addr_width-1:0] ddr_rd_addr_port3; input[max_burst_bits-1:0] ddr_rd_data_port3; output[max_burst_bytes_width:0] ddr_rd_bytes_port3; output [axi_qos_width-1:0] ddr_wr_qos_port3; output [axi_qos_width-1:0] ddr_rd_qos_port3; /* Goes to port1 of OCM */ input ocm_wr_ack_port1; output ocm_wr_dv_port1; output ocm_rd_req_port1; input ocm_rd_dv_port1; output[max_burst_bits-1:0] ocm_wr_data_port1; output[addr_width-1:0] ocm_wr_addr_port1; output[max_burst_bytes_width:0] ocm_wr_bytes_port1; input[max_burst_bits-1:0] ocm_rd_data_port1; output[addr_width-1:0] ocm_rd_addr_port1; output[max_burst_bytes_width:0] ocm_rd_bytes_port1; /* Goes to port1 of REG */ output [axi_qos_width-1:0] reg_rd_qos_port1; output reg_rd_req_port1; input reg_rd_dv_port1; input[max_burst_bits-1:0] reg_rd_data_port1; output[addr_width-1:0] reg_rd_addr_port1; output[max_burst_bytes_width:0] reg_rd_bytes_port1; wire ocm_wr_dv_osw0; wire ocm_wr_dv_osw1; wire[max_burst_bits-1:0] ocm_wr_data_osw0; wire[max_burst_bits-1:0] ocm_wr_data_osw1; wire[addr_width-1:0] ocm_wr_addr_osw0; wire[addr_width-1:0] ocm_wr_addr_osw1; wire[max_burst_bytes_width:0] ocm_wr_bytes_osw0; wire[max_burst_bytes_width:0] ocm_wr_bytes_osw1; wire ocm_wr_ack_osw0; wire ocm_wr_ack_osw1; wire ocm_rd_req_osw0; wire ocm_rd_req_osw1; wire[max_burst_bits-1:0] ocm_rd_data_osw0; wire[max_burst_bits-1:0] ocm_rd_data_osw1; wire[addr_width-1:0] ocm_rd_addr_osw0; wire[addr_width-1:0] ocm_rd_addr_osw1; wire[max_burst_bytes_width:0] ocm_rd_bytes_osw0; wire[max_burst_bytes_width:0] ocm_rd_bytes_osw1; wire ocm_rd_dv_osw0; wire ocm_rd_dv_osw1; wire [axi_qos_width-1:0] ocm_wr_qos_osw0; wire [axi_qos_width-1:0] ocm_wr_qos_osw1; wire [axi_qos_width-1:0] ocm_rd_qos_osw0; wire [axi_qos_width-1:0] ocm_rd_qos_osw1; processing_system7_bfm_v2_0_5_fmsw_gp fmsw ( .sw_clk(sw_clk), .rstn(rstn), .w_qos_gp0(w_qos_gp0), .r_qos_gp0(r_qos_gp0), .wr_ack_ocm_gp0(wr_ack_ocm_gp0), .wr_ack_ddr_gp0(wr_ack_ddr_gp0), .wr_data_gp0(wr_data_gp0), .wr_addr_gp0(wr_addr_gp0), .wr_bytes_gp0(wr_bytes_gp0), .wr_dv_ocm_gp0(wr_dv_ocm_gp0), .wr_dv_ddr_gp0(wr_dv_ddr_gp0), .rd_req_ocm_gp0(rd_req_ocm_gp0), .rd_req_ddr_gp0(rd_req_ddr_gp0), .rd_req_reg_gp0(rd_req_reg_gp0), .rd_addr_gp0(rd_addr_gp0), .rd_bytes_gp0(rd_bytes_gp0), .rd_data_ddr_gp0(rd_data_ddr_gp0), .rd_data_ocm_gp0(rd_data_ocm_gp0), .rd_data_reg_gp0(rd_data_reg_gp0), .rd_dv_ocm_gp0(rd_dv_ocm_gp0), .rd_dv_ddr_gp0(rd_dv_ddr_gp0), .rd_dv_reg_gp0(rd_dv_reg_gp0), .w_qos_gp1(w_qos_gp1), .r_qos_gp1(r_qos_gp1), .wr_ack_ocm_gp1(wr_ack_ocm_gp1), .wr_ack_ddr_gp1(wr_ack_ddr_gp1), .wr_data_gp1(wr_data_gp1), .wr_addr_gp1(wr_addr_gp1), .wr_bytes_gp1(wr_bytes_gp1), .wr_dv_ocm_gp1(wr_dv_ocm_gp1), .wr_dv_ddr_gp1(wr_dv_ddr_gp1), .rd_req_ocm_gp1(rd_req_ocm_gp1), .rd_req_ddr_gp1(rd_req_ddr_gp1), .rd_req_reg_gp1(rd_req_reg_gp1), .rd_addr_gp1(rd_addr_gp1), .rd_bytes_gp1(rd_bytes_gp1), .rd_data_ddr_gp1(rd_data_ddr_gp1), .rd_data_ocm_gp1(rd_data_ocm_gp1), .rd_data_reg_gp1(rd_data_reg_gp1), .rd_dv_ocm_gp1(rd_dv_ocm_gp1), .rd_dv_ddr_gp1(rd_dv_ddr_gp1), .rd_dv_reg_gp1(rd_dv_reg_gp1), .ocm_wr_ack (ocm_wr_ack_osw0), .ocm_wr_dv (ocm_wr_dv_osw0), .ocm_rd_req (ocm_rd_req_osw0), .ocm_rd_dv (ocm_rd_dv_osw0), .ocm_wr_addr(ocm_wr_addr_osw0), .ocm_wr_data(ocm_wr_data_osw0), .ocm_wr_bytes(ocm_wr_bytes_osw0), .ocm_rd_addr(ocm_rd_addr_osw0), .ocm_rd_data(ocm_rd_data_osw0), .ocm_rd_bytes(ocm_rd_bytes_osw0), .ocm_wr_qos(ocm_wr_qos_osw0), .ocm_rd_qos(ocm_rd_qos_osw0), .ddr_wr_qos(ddr_wr_qos_port1), .ddr_rd_qos(ddr_rd_qos_port1), .reg_rd_qos(reg_rd_qos_port1), .ddr_wr_ack(ddr_wr_ack_port1), .ddr_wr_dv(ddr_wr_dv_port1), .ddr_rd_req(ddr_rd_req_port1), .ddr_rd_dv(ddr_rd_dv_port1), .ddr_wr_addr(ddr_wr_addr_port1), .ddr_wr_data(ddr_wr_data_port1), .ddr_wr_bytes(ddr_wr_bytes_port1), .ddr_rd_addr(ddr_rd_addr_port1), .ddr_rd_data(ddr_rd_data_port1), .ddr_rd_bytes(ddr_rd_bytes_port1), .reg_rd_req(reg_rd_req_port1), .reg_rd_dv(reg_rd_dv_port1), .reg_rd_addr(reg_rd_addr_port1), .reg_rd_data(reg_rd_data_port1), .reg_rd_bytes(reg_rd_bytes_port1) ); processing_system7_bfm_v2_0_5_ssw_hp ssw( .sw_clk(sw_clk), .rstn(rstn), .w_qos_hp0(w_qos_hp0), .r_qos_hp0(r_qos_hp0), .w_qos_hp1(w_qos_hp1), .r_qos_hp1(r_qos_hp1), .w_qos_hp2(w_qos_hp2), .r_qos_hp2(r_qos_hp2), .w_qos_hp3(w_qos_hp3), .r_qos_hp3(r_qos_hp3), .wr_ack_ddr_hp0(wr_ack_ddr_hp0), .wr_data_hp0(wr_data_hp0), .wr_addr_hp0(wr_addr_hp0), .wr_bytes_hp0(wr_bytes_hp0), .wr_dv_ddr_hp0(wr_dv_ddr_hp0), .rd_req_ddr_hp0(rd_req_ddr_hp0), .rd_addr_hp0(rd_addr_hp0), .rd_bytes_hp0(rd_bytes_hp0), .rd_data_ddr_hp0(rd_data_ddr_hp0), .rd_data_ocm_hp0(rd_data_ocm_hp0), .rd_dv_ddr_hp0(rd_dv_ddr_hp0), .wr_ack_ocm_hp0(wr_ack_ocm_hp0), .wr_dv_ocm_hp0(wr_dv_ocm_hp0), .rd_req_ocm_hp0(rd_req_ocm_hp0), .rd_dv_ocm_hp0(rd_dv_ocm_hp0), .wr_ack_ddr_hp1(wr_ack_ddr_hp1), .wr_data_hp1(wr_data_hp1), .wr_addr_hp1(wr_addr_hp1), .wr_bytes_hp1(wr_bytes_hp1), .wr_dv_ddr_hp1(wr_dv_ddr_hp1), .rd_req_ddr_hp1(rd_req_ddr_hp1), .rd_addr_hp1(rd_addr_hp1), .rd_bytes_hp1(rd_bytes_hp1), .rd_data_ddr_hp1(rd_data_ddr_hp1), .rd_data_ocm_hp1(rd_data_ocm_hp1), .rd_dv_ddr_hp1(rd_dv_ddr_hp1), .wr_ack_ocm_hp1(wr_ack_ocm_hp1), .wr_dv_ocm_hp1(wr_dv_ocm_hp1), .rd_req_ocm_hp1(rd_req_ocm_hp1), .rd_dv_ocm_hp1(rd_dv_ocm_hp1), .wr_ack_ddr_hp2(wr_ack_ddr_hp2), .wr_data_hp2(wr_data_hp2), .wr_addr_hp2(wr_addr_hp2), .wr_bytes_hp2(wr_bytes_hp2), .wr_dv_ddr_hp2(wr_dv_ddr_hp2), .rd_req_ddr_hp2(rd_req_ddr_hp2), .rd_addr_hp2(rd_addr_hp2), .rd_bytes_hp2(rd_bytes_hp2), .rd_data_ddr_hp2(rd_data_ddr_hp2), .rd_data_ocm_hp2(rd_data_ocm_hp2), .rd_dv_ddr_hp2(rd_dv_ddr_hp2), .wr_ack_ocm_hp2(wr_ack_ocm_hp2), .wr_dv_ocm_hp2(wr_dv_ocm_hp2), .rd_req_ocm_hp2(rd_req_ocm_hp2), .rd_dv_ocm_hp2(rd_dv_ocm_hp2), .wr_ack_ddr_hp3(wr_ack_ddr_hp3), .wr_data_hp3(wr_data_hp3), .wr_addr_hp3(wr_addr_hp3), .wr_bytes_hp3(wr_bytes_hp3), .wr_dv_ddr_hp3(wr_dv_ddr_hp3), .rd_req_ddr_hp3(rd_req_ddr_hp3), .rd_addr_hp3(rd_addr_hp3), .rd_bytes_hp3(rd_bytes_hp3), .rd_data_ddr_hp3(rd_data_ddr_hp3), .rd_data_ocm_hp3(rd_data_ocm_hp3), .rd_dv_ddr_hp3(rd_dv_ddr_hp3), .wr_ack_ocm_hp3(wr_ack_ocm_hp3), .wr_dv_ocm_hp3(wr_dv_ocm_hp3), .rd_req_ocm_hp3(rd_req_ocm_hp3), .rd_dv_ocm_hp3(rd_dv_ocm_hp3), .ddr_wr_ack0(ddr_wr_ack_port2), .ddr_wr_dv0(ddr_wr_dv_port2), .ddr_rd_req0(ddr_rd_req_port2), .ddr_rd_dv0(ddr_rd_dv_port2), .ddr_wr_addr0(ddr_wr_addr_port2), .ddr_wr_data0(ddr_wr_data_port2), .ddr_wr_bytes0(ddr_wr_bytes_port2), .ddr_rd_addr0(ddr_rd_addr_port2), .ddr_rd_data0(ddr_rd_data_port2), .ddr_rd_bytes0(ddr_rd_bytes_port2), .ddr_wr_qos0(ddr_wr_qos_port2), .ddr_rd_qos0(ddr_rd_qos_port2), .ddr_wr_ack1(ddr_wr_ack_port3), .ddr_wr_dv1(ddr_wr_dv_port3), .ddr_rd_req1(ddr_rd_req_port3), .ddr_rd_dv1(ddr_rd_dv_port3), .ddr_wr_addr1(ddr_wr_addr_port3), .ddr_wr_data1(ddr_wr_data_port3), .ddr_wr_bytes1(ddr_wr_bytes_port3), .ddr_rd_addr1(ddr_rd_addr_port3), .ddr_rd_data1(ddr_rd_data_port3), .ddr_rd_bytes1(ddr_rd_bytes_port3), .ddr_wr_qos1(ddr_wr_qos_port3), .ddr_rd_qos1(ddr_rd_qos_port3), .ocm_wr_qos(ocm_wr_qos_osw1), .ocm_rd_qos(ocm_rd_qos_osw1), .ocm_wr_ack (ocm_wr_ack_osw1), .ocm_wr_dv (ocm_wr_dv_osw1), .ocm_rd_req (ocm_rd_req_osw1), .ocm_rd_dv (ocm_rd_dv_osw1), .ocm_wr_addr(ocm_wr_addr_osw1), .ocm_wr_data(ocm_wr_data_osw1), .ocm_wr_bytes(ocm_wr_bytes_osw1), .ocm_rd_addr(ocm_rd_addr_osw1), .ocm_rd_data(ocm_rd_data_osw1), .ocm_rd_bytes(ocm_rd_bytes_osw1) ); processing_system7_bfm_v2_0_5_arb_wr osw_wr ( .rstn(rstn), .sw_clk(sw_clk), .qos1(ocm_wr_qos_osw0), /// chk .qos2(ocm_wr_qos_osw1), /// chk .prt_dv1(ocm_wr_dv_osw0), .prt_dv2(ocm_wr_dv_osw1), .prt_data1(ocm_wr_data_osw0), .prt_data2(ocm_wr_data_osw1), .prt_addr1(ocm_wr_addr_osw0), .prt_addr2(ocm_wr_addr_osw1), .prt_bytes1(ocm_wr_bytes_osw0), .prt_bytes2(ocm_wr_bytes_osw1), .prt_ack1(ocm_wr_ack_osw0), .prt_ack2(ocm_wr_ack_osw1), .prt_req(ocm_wr_dv_port1), .prt_qos(ocm_wr_qos_port1), .prt_data(ocm_wr_data_port1), .prt_addr(ocm_wr_addr_port1), .prt_bytes(ocm_wr_bytes_port1), .prt_ack(ocm_wr_ack_port1) ); processing_system7_bfm_v2_0_5_arb_rd osw_rd( .rstn(rstn), .sw_clk(sw_clk), .qos1(ocm_rd_qos_osw0), // chk .qos2(ocm_rd_qos_osw1), // chk .prt_req1(ocm_rd_req_osw0), .prt_req2(ocm_rd_req_osw1), .prt_data1(ocm_rd_data_osw0), .prt_data2(ocm_rd_data_osw1), .prt_addr1(ocm_rd_addr_osw0), .prt_addr2(ocm_rd_addr_osw1), .prt_bytes1(ocm_rd_bytes_osw0), .prt_bytes2(ocm_rd_bytes_osw1), .prt_dv1(ocm_rd_dv_osw0), .prt_dv2(ocm_rd_dv_osw1), .prt_req(ocm_rd_req_port1), .prt_qos(ocm_rd_qos_port1), .prt_data(ocm_rd_data_port1), .prt_addr(ocm_rd_addr_port1), .prt_bytes(ocm_rd_bytes_port1), .prt_dv(ocm_rd_dv_port1) ); endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_gen_reset.v * * Date : 2012-11 * * Description : Module that generates FPGA_RESETs and synchronizes RESETs to the * respective clocks. *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_gen_reset( por_rst_n, sys_rst_n, rst_out_n, m_axi_gp0_clk, m_axi_gp1_clk, s_axi_gp0_clk, s_axi_gp1_clk, s_axi_hp0_clk, s_axi_hp1_clk, s_axi_hp2_clk, s_axi_hp3_clk, s_axi_acp_clk, m_axi_gp0_rstn, m_axi_gp1_rstn, s_axi_gp0_rstn, s_axi_gp1_rstn, s_axi_hp0_rstn, s_axi_hp1_rstn, s_axi_hp2_rstn, s_axi_hp3_rstn, s_axi_acp_rstn, fclk_reset3_n, fclk_reset2_n, fclk_reset1_n, fclk_reset0_n, fpga_acp_reset_n, fpga_gp_m0_reset_n, fpga_gp_m1_reset_n, fpga_gp_s0_reset_n, fpga_gp_s1_reset_n, fpga_hp_s0_reset_n, fpga_hp_s1_reset_n, fpga_hp_s2_reset_n, fpga_hp_s3_reset_n ); input por_rst_n; input sys_rst_n; input m_axi_gp0_clk; input m_axi_gp1_clk; input s_axi_gp0_clk; input s_axi_gp1_clk; input s_axi_hp0_clk; input s_axi_hp1_clk; input s_axi_hp2_clk; input s_axi_hp3_clk; input s_axi_acp_clk; output reg m_axi_gp0_rstn; output reg m_axi_gp1_rstn; output reg s_axi_gp0_rstn; output reg s_axi_gp1_rstn; output reg s_axi_hp0_rstn; output reg s_axi_hp1_rstn; output reg s_axi_hp2_rstn; output reg s_axi_hp3_rstn; output reg s_axi_acp_rstn; output rst_out_n; output fclk_reset3_n; output fclk_reset2_n; output fclk_reset1_n; output fclk_reset0_n; output fpga_acp_reset_n; output fpga_gp_m0_reset_n; output fpga_gp_m1_reset_n; output fpga_gp_s0_reset_n; output fpga_gp_s1_reset_n; output fpga_hp_s0_reset_n; output fpga_hp_s1_reset_n; output fpga_hp_s2_reset_n; output fpga_hp_s3_reset_n; reg [31:0] fabric_rst_n; reg r_m_axi_gp0_rstn; reg r_m_axi_gp1_rstn; reg r_s_axi_gp0_rstn; reg r_s_axi_gp1_rstn; reg r_s_axi_hp0_rstn; reg r_s_axi_hp1_rstn; reg r_s_axi_hp2_rstn; reg r_s_axi_hp3_rstn; reg r_s_axi_acp_rstn; assign rst_out_n = por_rst_n & sys_rst_n; assign fclk_reset0_n = !fabric_rst_n[0]; assign fclk_reset1_n = !fabric_rst_n[1]; assign fclk_reset2_n = !fabric_rst_n[2]; assign fclk_reset3_n = !fabric_rst_n[3]; assign fpga_acp_reset_n = !fabric_rst_n[24]; assign fpga_hp_s3_reset_n = !fabric_rst_n[23]; assign fpga_hp_s2_reset_n = !fabric_rst_n[22]; assign fpga_hp_s1_reset_n = !fabric_rst_n[21]; assign fpga_hp_s0_reset_n = !fabric_rst_n[20]; assign fpga_gp_s1_reset_n = !fabric_rst_n[17]; assign fpga_gp_s0_reset_n = !fabric_rst_n[16]; assign fpga_gp_m1_reset_n = !fabric_rst_n[13]; assign fpga_gp_m0_reset_n = !fabric_rst_n[12]; task fpga_soft_reset; input[31:0] reset_ctrl; begin fabric_rst_n[0] = reset_ctrl[0]; fabric_rst_n[1] = reset_ctrl[1]; fabric_rst_n[2] = reset_ctrl[2]; fabric_rst_n[3] = reset_ctrl[3]; fabric_rst_n[12] = reset_ctrl[12]; fabric_rst_n[13] = reset_ctrl[13]; fabric_rst_n[16] = reset_ctrl[16]; fabric_rst_n[17] = reset_ctrl[17]; fabric_rst_n[20] = reset_ctrl[20]; fabric_rst_n[21] = reset_ctrl[21]; fabric_rst_n[22] = reset_ctrl[22]; fabric_rst_n[23] = reset_ctrl[23]; fabric_rst_n[24] = reset_ctrl[24]; end endtask always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f; always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) m_axi_gp0_rstn = 1'b0; else m_axi_gp0_rstn = 1'b1; end always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) m_axi_gp1_rstn = 1'b0; else m_axi_gp1_rstn = 1'b1; end always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_gp0_rstn = 1'b0; else s_axi_gp0_rstn = 1'b1; end always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_gp1_rstn = 1'b0; else s_axi_gp1_rstn = 1'b1; end always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp0_rstn = 1'b0; else s_axi_hp0_rstn = 1'b1; end always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp1_rstn = 1'b0; else s_axi_hp1_rstn = 1'b1; end always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp2_rstn = 1'b0; else s_axi_hp2_rstn = 1'b1; end always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp3_rstn = 1'b0; else s_axi_hp3_rstn = 1'b1; end always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_acp_rstn = 1'b0; else s_axi_acp_rstn = 1'b1; end always@(*) begin if ((por_rst_n!= 1'b0) && (por_rst_n!= 1'b1) && (sys_rst_n != 1'b0) && (sys_rst_n != 1'b1)) begin $display(" Error:processing_system7_bfm_v2_0_5_gen_reset. PS_PORB and PS_SRSTB must be driven to known state"); $finish(); end end endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_gen_reset.v * * Date : 2012-11 * * Description : Module that generates FPGA_RESETs and synchronizes RESETs to the * respective clocks. *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_gen_reset( por_rst_n, sys_rst_n, rst_out_n, m_axi_gp0_clk, m_axi_gp1_clk, s_axi_gp0_clk, s_axi_gp1_clk, s_axi_hp0_clk, s_axi_hp1_clk, s_axi_hp2_clk, s_axi_hp3_clk, s_axi_acp_clk, m_axi_gp0_rstn, m_axi_gp1_rstn, s_axi_gp0_rstn, s_axi_gp1_rstn, s_axi_hp0_rstn, s_axi_hp1_rstn, s_axi_hp2_rstn, s_axi_hp3_rstn, s_axi_acp_rstn, fclk_reset3_n, fclk_reset2_n, fclk_reset1_n, fclk_reset0_n, fpga_acp_reset_n, fpga_gp_m0_reset_n, fpga_gp_m1_reset_n, fpga_gp_s0_reset_n, fpga_gp_s1_reset_n, fpga_hp_s0_reset_n, fpga_hp_s1_reset_n, fpga_hp_s2_reset_n, fpga_hp_s3_reset_n ); input por_rst_n; input sys_rst_n; input m_axi_gp0_clk; input m_axi_gp1_clk; input s_axi_gp0_clk; input s_axi_gp1_clk; input s_axi_hp0_clk; input s_axi_hp1_clk; input s_axi_hp2_clk; input s_axi_hp3_clk; input s_axi_acp_clk; output reg m_axi_gp0_rstn; output reg m_axi_gp1_rstn; output reg s_axi_gp0_rstn; output reg s_axi_gp1_rstn; output reg s_axi_hp0_rstn; output reg s_axi_hp1_rstn; output reg s_axi_hp2_rstn; output reg s_axi_hp3_rstn; output reg s_axi_acp_rstn; output rst_out_n; output fclk_reset3_n; output fclk_reset2_n; output fclk_reset1_n; output fclk_reset0_n; output fpga_acp_reset_n; output fpga_gp_m0_reset_n; output fpga_gp_m1_reset_n; output fpga_gp_s0_reset_n; output fpga_gp_s1_reset_n; output fpga_hp_s0_reset_n; output fpga_hp_s1_reset_n; output fpga_hp_s2_reset_n; output fpga_hp_s3_reset_n; reg [31:0] fabric_rst_n; reg r_m_axi_gp0_rstn; reg r_m_axi_gp1_rstn; reg r_s_axi_gp0_rstn; reg r_s_axi_gp1_rstn; reg r_s_axi_hp0_rstn; reg r_s_axi_hp1_rstn; reg r_s_axi_hp2_rstn; reg r_s_axi_hp3_rstn; reg r_s_axi_acp_rstn; assign rst_out_n = por_rst_n & sys_rst_n; assign fclk_reset0_n = !fabric_rst_n[0]; assign fclk_reset1_n = !fabric_rst_n[1]; assign fclk_reset2_n = !fabric_rst_n[2]; assign fclk_reset3_n = !fabric_rst_n[3]; assign fpga_acp_reset_n = !fabric_rst_n[24]; assign fpga_hp_s3_reset_n = !fabric_rst_n[23]; assign fpga_hp_s2_reset_n = !fabric_rst_n[22]; assign fpga_hp_s1_reset_n = !fabric_rst_n[21]; assign fpga_hp_s0_reset_n = !fabric_rst_n[20]; assign fpga_gp_s1_reset_n = !fabric_rst_n[17]; assign fpga_gp_s0_reset_n = !fabric_rst_n[16]; assign fpga_gp_m1_reset_n = !fabric_rst_n[13]; assign fpga_gp_m0_reset_n = !fabric_rst_n[12]; task fpga_soft_reset; input[31:0] reset_ctrl; begin fabric_rst_n[0] = reset_ctrl[0]; fabric_rst_n[1] = reset_ctrl[1]; fabric_rst_n[2] = reset_ctrl[2]; fabric_rst_n[3] = reset_ctrl[3]; fabric_rst_n[12] = reset_ctrl[12]; fabric_rst_n[13] = reset_ctrl[13]; fabric_rst_n[16] = reset_ctrl[16]; fabric_rst_n[17] = reset_ctrl[17]; fabric_rst_n[20] = reset_ctrl[20]; fabric_rst_n[21] = reset_ctrl[21]; fabric_rst_n[22] = reset_ctrl[22]; fabric_rst_n[23] = reset_ctrl[23]; fabric_rst_n[24] = reset_ctrl[24]; end endtask always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f; always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) m_axi_gp0_rstn = 1'b0; else m_axi_gp0_rstn = 1'b1; end always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) m_axi_gp1_rstn = 1'b0; else m_axi_gp1_rstn = 1'b1; end always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_gp0_rstn = 1'b0; else s_axi_gp0_rstn = 1'b1; end always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_gp1_rstn = 1'b0; else s_axi_gp1_rstn = 1'b1; end always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp0_rstn = 1'b0; else s_axi_hp0_rstn = 1'b1; end always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp1_rstn = 1'b0; else s_axi_hp1_rstn = 1'b1; end always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp2_rstn = 1'b0; else s_axi_hp2_rstn = 1'b1; end always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp3_rstn = 1'b0; else s_axi_hp3_rstn = 1'b1; end always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_acp_rstn = 1'b0; else s_axi_acp_rstn = 1'b1; end always@(*) begin if ((por_rst_n!= 1'b0) && (por_rst_n!= 1'b1) && (sys_rst_n != 1'b0) && (sys_rst_n != 1'b1)) begin $display(" Error:processing_system7_bfm_v2_0_5_gen_reset. PS_PORB and PS_SRSTB must be driven to known state"); $finish(); end end endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_gen_reset.v * * Date : 2012-11 * * Description : Module that generates FPGA_RESETs and synchronizes RESETs to the * respective clocks. *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_gen_reset( por_rst_n, sys_rst_n, rst_out_n, m_axi_gp0_clk, m_axi_gp1_clk, s_axi_gp0_clk, s_axi_gp1_clk, s_axi_hp0_clk, s_axi_hp1_clk, s_axi_hp2_clk, s_axi_hp3_clk, s_axi_acp_clk, m_axi_gp0_rstn, m_axi_gp1_rstn, s_axi_gp0_rstn, s_axi_gp1_rstn, s_axi_hp0_rstn, s_axi_hp1_rstn, s_axi_hp2_rstn, s_axi_hp3_rstn, s_axi_acp_rstn, fclk_reset3_n, fclk_reset2_n, fclk_reset1_n, fclk_reset0_n, fpga_acp_reset_n, fpga_gp_m0_reset_n, fpga_gp_m1_reset_n, fpga_gp_s0_reset_n, fpga_gp_s1_reset_n, fpga_hp_s0_reset_n, fpga_hp_s1_reset_n, fpga_hp_s2_reset_n, fpga_hp_s3_reset_n ); input por_rst_n; input sys_rst_n; input m_axi_gp0_clk; input m_axi_gp1_clk; input s_axi_gp0_clk; input s_axi_gp1_clk; input s_axi_hp0_clk; input s_axi_hp1_clk; input s_axi_hp2_clk; input s_axi_hp3_clk; input s_axi_acp_clk; output reg m_axi_gp0_rstn; output reg m_axi_gp1_rstn; output reg s_axi_gp0_rstn; output reg s_axi_gp1_rstn; output reg s_axi_hp0_rstn; output reg s_axi_hp1_rstn; output reg s_axi_hp2_rstn; output reg s_axi_hp3_rstn; output reg s_axi_acp_rstn; output rst_out_n; output fclk_reset3_n; output fclk_reset2_n; output fclk_reset1_n; output fclk_reset0_n; output fpga_acp_reset_n; output fpga_gp_m0_reset_n; output fpga_gp_m1_reset_n; output fpga_gp_s0_reset_n; output fpga_gp_s1_reset_n; output fpga_hp_s0_reset_n; output fpga_hp_s1_reset_n; output fpga_hp_s2_reset_n; output fpga_hp_s3_reset_n; reg [31:0] fabric_rst_n; reg r_m_axi_gp0_rstn; reg r_m_axi_gp1_rstn; reg r_s_axi_gp0_rstn; reg r_s_axi_gp1_rstn; reg r_s_axi_hp0_rstn; reg r_s_axi_hp1_rstn; reg r_s_axi_hp2_rstn; reg r_s_axi_hp3_rstn; reg r_s_axi_acp_rstn; assign rst_out_n = por_rst_n & sys_rst_n; assign fclk_reset0_n = !fabric_rst_n[0]; assign fclk_reset1_n = !fabric_rst_n[1]; assign fclk_reset2_n = !fabric_rst_n[2]; assign fclk_reset3_n = !fabric_rst_n[3]; assign fpga_acp_reset_n = !fabric_rst_n[24]; assign fpga_hp_s3_reset_n = !fabric_rst_n[23]; assign fpga_hp_s2_reset_n = !fabric_rst_n[22]; assign fpga_hp_s1_reset_n = !fabric_rst_n[21]; assign fpga_hp_s0_reset_n = !fabric_rst_n[20]; assign fpga_gp_s1_reset_n = !fabric_rst_n[17]; assign fpga_gp_s0_reset_n = !fabric_rst_n[16]; assign fpga_gp_m1_reset_n = !fabric_rst_n[13]; assign fpga_gp_m0_reset_n = !fabric_rst_n[12]; task fpga_soft_reset; input[31:0] reset_ctrl; begin fabric_rst_n[0] = reset_ctrl[0]; fabric_rst_n[1] = reset_ctrl[1]; fabric_rst_n[2] = reset_ctrl[2]; fabric_rst_n[3] = reset_ctrl[3]; fabric_rst_n[12] = reset_ctrl[12]; fabric_rst_n[13] = reset_ctrl[13]; fabric_rst_n[16] = reset_ctrl[16]; fabric_rst_n[17] = reset_ctrl[17]; fabric_rst_n[20] = reset_ctrl[20]; fabric_rst_n[21] = reset_ctrl[21]; fabric_rst_n[22] = reset_ctrl[22]; fabric_rst_n[23] = reset_ctrl[23]; fabric_rst_n[24] = reset_ctrl[24]; end endtask always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f; always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) m_axi_gp0_rstn = 1'b0; else m_axi_gp0_rstn = 1'b1; end always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) m_axi_gp1_rstn = 1'b0; else m_axi_gp1_rstn = 1'b1; end always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_gp0_rstn = 1'b0; else s_axi_gp0_rstn = 1'b1; end always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_gp1_rstn = 1'b0; else s_axi_gp1_rstn = 1'b1; end always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp0_rstn = 1'b0; else s_axi_hp0_rstn = 1'b1; end always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp1_rstn = 1'b0; else s_axi_hp1_rstn = 1'b1; end always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp2_rstn = 1'b0; else s_axi_hp2_rstn = 1'b1; end always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp3_rstn = 1'b0; else s_axi_hp3_rstn = 1'b1; end always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_acp_rstn = 1'b0; else s_axi_acp_rstn = 1'b1; end always@(*) begin if ((por_rst_n!= 1'b0) && (por_rst_n!= 1'b1) && (sys_rst_n != 1'b0) && (sys_rst_n != 1'b1)) begin $display(" Error:processing_system7_bfm_v2_0_5_gen_reset. PS_PORB and PS_SRSTB must be driven to known state"); $finish(); end end endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_gen_reset.v * * Date : 2012-11 * * Description : Module that generates FPGA_RESETs and synchronizes RESETs to the * respective clocks. *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_gen_reset( por_rst_n, sys_rst_n, rst_out_n, m_axi_gp0_clk, m_axi_gp1_clk, s_axi_gp0_clk, s_axi_gp1_clk, s_axi_hp0_clk, s_axi_hp1_clk, s_axi_hp2_clk, s_axi_hp3_clk, s_axi_acp_clk, m_axi_gp0_rstn, m_axi_gp1_rstn, s_axi_gp0_rstn, s_axi_gp1_rstn, s_axi_hp0_rstn, s_axi_hp1_rstn, s_axi_hp2_rstn, s_axi_hp3_rstn, s_axi_acp_rstn, fclk_reset3_n, fclk_reset2_n, fclk_reset1_n, fclk_reset0_n, fpga_acp_reset_n, fpga_gp_m0_reset_n, fpga_gp_m1_reset_n, fpga_gp_s0_reset_n, fpga_gp_s1_reset_n, fpga_hp_s0_reset_n, fpga_hp_s1_reset_n, fpga_hp_s2_reset_n, fpga_hp_s3_reset_n ); input por_rst_n; input sys_rst_n; input m_axi_gp0_clk; input m_axi_gp1_clk; input s_axi_gp0_clk; input s_axi_gp1_clk; input s_axi_hp0_clk; input s_axi_hp1_clk; input s_axi_hp2_clk; input s_axi_hp3_clk; input s_axi_acp_clk; output reg m_axi_gp0_rstn; output reg m_axi_gp1_rstn; output reg s_axi_gp0_rstn; output reg s_axi_gp1_rstn; output reg s_axi_hp0_rstn; output reg s_axi_hp1_rstn; output reg s_axi_hp2_rstn; output reg s_axi_hp3_rstn; output reg s_axi_acp_rstn; output rst_out_n; output fclk_reset3_n; output fclk_reset2_n; output fclk_reset1_n; output fclk_reset0_n; output fpga_acp_reset_n; output fpga_gp_m0_reset_n; output fpga_gp_m1_reset_n; output fpga_gp_s0_reset_n; output fpga_gp_s1_reset_n; output fpga_hp_s0_reset_n; output fpga_hp_s1_reset_n; output fpga_hp_s2_reset_n; output fpga_hp_s3_reset_n; reg [31:0] fabric_rst_n; reg r_m_axi_gp0_rstn; reg r_m_axi_gp1_rstn; reg r_s_axi_gp0_rstn; reg r_s_axi_gp1_rstn; reg r_s_axi_hp0_rstn; reg r_s_axi_hp1_rstn; reg r_s_axi_hp2_rstn; reg r_s_axi_hp3_rstn; reg r_s_axi_acp_rstn; assign rst_out_n = por_rst_n & sys_rst_n; assign fclk_reset0_n = !fabric_rst_n[0]; assign fclk_reset1_n = !fabric_rst_n[1]; assign fclk_reset2_n = !fabric_rst_n[2]; assign fclk_reset3_n = !fabric_rst_n[3]; assign fpga_acp_reset_n = !fabric_rst_n[24]; assign fpga_hp_s3_reset_n = !fabric_rst_n[23]; assign fpga_hp_s2_reset_n = !fabric_rst_n[22]; assign fpga_hp_s1_reset_n = !fabric_rst_n[21]; assign fpga_hp_s0_reset_n = !fabric_rst_n[20]; assign fpga_gp_s1_reset_n = !fabric_rst_n[17]; assign fpga_gp_s0_reset_n = !fabric_rst_n[16]; assign fpga_gp_m1_reset_n = !fabric_rst_n[13]; assign fpga_gp_m0_reset_n = !fabric_rst_n[12]; task fpga_soft_reset; input[31:0] reset_ctrl; begin fabric_rst_n[0] = reset_ctrl[0]; fabric_rst_n[1] = reset_ctrl[1]; fabric_rst_n[2] = reset_ctrl[2]; fabric_rst_n[3] = reset_ctrl[3]; fabric_rst_n[12] = reset_ctrl[12]; fabric_rst_n[13] = reset_ctrl[13]; fabric_rst_n[16] = reset_ctrl[16]; fabric_rst_n[17] = reset_ctrl[17]; fabric_rst_n[20] = reset_ctrl[20]; fabric_rst_n[21] = reset_ctrl[21]; fabric_rst_n[22] = reset_ctrl[22]; fabric_rst_n[23] = reset_ctrl[23]; fabric_rst_n[24] = reset_ctrl[24]; end endtask always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f; always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) m_axi_gp0_rstn = 1'b0; else m_axi_gp0_rstn = 1'b1; end always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) m_axi_gp1_rstn = 1'b0; else m_axi_gp1_rstn = 1'b1; end always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_gp0_rstn = 1'b0; else s_axi_gp0_rstn = 1'b1; end always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_gp1_rstn = 1'b0; else s_axi_gp1_rstn = 1'b1; end always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp0_rstn = 1'b0; else s_axi_hp0_rstn = 1'b1; end always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp1_rstn = 1'b0; else s_axi_hp1_rstn = 1'b1; end always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp2_rstn = 1'b0; else s_axi_hp2_rstn = 1'b1; end always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp3_rstn = 1'b0; else s_axi_hp3_rstn = 1'b1; end always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_acp_rstn = 1'b0; else s_axi_acp_rstn = 1'b1; end always@(*) begin if ((por_rst_n!= 1'b0) && (por_rst_n!= 1'b1) && (sys_rst_n != 1'b0) && (sys_rst_n != 1'b1)) begin $display(" Error:processing_system7_bfm_v2_0_5_gen_reset. PS_PORB and PS_SRSTB must be driven to known state"); $finish(); end end endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_gen_reset.v * * Date : 2012-11 * * Description : Module that generates FPGA_RESETs and synchronizes RESETs to the * respective clocks. *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_gen_reset( por_rst_n, sys_rst_n, rst_out_n, m_axi_gp0_clk, m_axi_gp1_clk, s_axi_gp0_clk, s_axi_gp1_clk, s_axi_hp0_clk, s_axi_hp1_clk, s_axi_hp2_clk, s_axi_hp3_clk, s_axi_acp_clk, m_axi_gp0_rstn, m_axi_gp1_rstn, s_axi_gp0_rstn, s_axi_gp1_rstn, s_axi_hp0_rstn, s_axi_hp1_rstn, s_axi_hp2_rstn, s_axi_hp3_rstn, s_axi_acp_rstn, fclk_reset3_n, fclk_reset2_n, fclk_reset1_n, fclk_reset0_n, fpga_acp_reset_n, fpga_gp_m0_reset_n, fpga_gp_m1_reset_n, fpga_gp_s0_reset_n, fpga_gp_s1_reset_n, fpga_hp_s0_reset_n, fpga_hp_s1_reset_n, fpga_hp_s2_reset_n, fpga_hp_s3_reset_n ); input por_rst_n; input sys_rst_n; input m_axi_gp0_clk; input m_axi_gp1_clk; input s_axi_gp0_clk; input s_axi_gp1_clk; input s_axi_hp0_clk; input s_axi_hp1_clk; input s_axi_hp2_clk; input s_axi_hp3_clk; input s_axi_acp_clk; output reg m_axi_gp0_rstn; output reg m_axi_gp1_rstn; output reg s_axi_gp0_rstn; output reg s_axi_gp1_rstn; output reg s_axi_hp0_rstn; output reg s_axi_hp1_rstn; output reg s_axi_hp2_rstn; output reg s_axi_hp3_rstn; output reg s_axi_acp_rstn; output rst_out_n; output fclk_reset3_n; output fclk_reset2_n; output fclk_reset1_n; output fclk_reset0_n; output fpga_acp_reset_n; output fpga_gp_m0_reset_n; output fpga_gp_m1_reset_n; output fpga_gp_s0_reset_n; output fpga_gp_s1_reset_n; output fpga_hp_s0_reset_n; output fpga_hp_s1_reset_n; output fpga_hp_s2_reset_n; output fpga_hp_s3_reset_n; reg [31:0] fabric_rst_n; reg r_m_axi_gp0_rstn; reg r_m_axi_gp1_rstn; reg r_s_axi_gp0_rstn; reg r_s_axi_gp1_rstn; reg r_s_axi_hp0_rstn; reg r_s_axi_hp1_rstn; reg r_s_axi_hp2_rstn; reg r_s_axi_hp3_rstn; reg r_s_axi_acp_rstn; assign rst_out_n = por_rst_n & sys_rst_n; assign fclk_reset0_n = !fabric_rst_n[0]; assign fclk_reset1_n = !fabric_rst_n[1]; assign fclk_reset2_n = !fabric_rst_n[2]; assign fclk_reset3_n = !fabric_rst_n[3]; assign fpga_acp_reset_n = !fabric_rst_n[24]; assign fpga_hp_s3_reset_n = !fabric_rst_n[23]; assign fpga_hp_s2_reset_n = !fabric_rst_n[22]; assign fpga_hp_s1_reset_n = !fabric_rst_n[21]; assign fpga_hp_s0_reset_n = !fabric_rst_n[20]; assign fpga_gp_s1_reset_n = !fabric_rst_n[17]; assign fpga_gp_s0_reset_n = !fabric_rst_n[16]; assign fpga_gp_m1_reset_n = !fabric_rst_n[13]; assign fpga_gp_m0_reset_n = !fabric_rst_n[12]; task fpga_soft_reset; input[31:0] reset_ctrl; begin fabric_rst_n[0] = reset_ctrl[0]; fabric_rst_n[1] = reset_ctrl[1]; fabric_rst_n[2] = reset_ctrl[2]; fabric_rst_n[3] = reset_ctrl[3]; fabric_rst_n[12] = reset_ctrl[12]; fabric_rst_n[13] = reset_ctrl[13]; fabric_rst_n[16] = reset_ctrl[16]; fabric_rst_n[17] = reset_ctrl[17]; fabric_rst_n[20] = reset_ctrl[20]; fabric_rst_n[21] = reset_ctrl[21]; fabric_rst_n[22] = reset_ctrl[22]; fabric_rst_n[23] = reset_ctrl[23]; fabric_rst_n[24] = reset_ctrl[24]; end endtask always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f; always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) m_axi_gp0_rstn = 1'b0; else m_axi_gp0_rstn = 1'b1; end always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) m_axi_gp1_rstn = 1'b0; else m_axi_gp1_rstn = 1'b1; end always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_gp0_rstn = 1'b0; else s_axi_gp0_rstn = 1'b1; end always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_gp1_rstn = 1'b0; else s_axi_gp1_rstn = 1'b1; end always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp0_rstn = 1'b0; else s_axi_hp0_rstn = 1'b1; end always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp1_rstn = 1'b0; else s_axi_hp1_rstn = 1'b1; end always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp2_rstn = 1'b0; else s_axi_hp2_rstn = 1'b1; end always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_hp3_rstn = 1'b0; else s_axi_hp3_rstn = 1'b1; end always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n)) begin if (!(por_rst_n & sys_rst_n)) s_axi_acp_rstn = 1'b0; else s_axi_acp_rstn = 1'b1; end always@(*) begin if ((por_rst_n!= 1'b0) && (por_rst_n!= 1'b1) && (sys_rst_n != 1'b0) && (sys_rst_n != 1'b1)) begin $display(" Error:processing_system7_bfm_v2_0_5_gen_reset. PS_PORB and PS_SRSTB must be driven to known state"); $finish(); end end endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_arb_wr.v * * Date : 2012-11 * * Description : Module that arbitrates between 2 write requests from 2 ports. * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_arb_wr( rstn, sw_clk, qos1, qos2, prt_dv1, prt_dv2, prt_data1, prt_data2, prt_addr1, prt_addr2, prt_bytes1, prt_bytes2, prt_ack1, prt_ack2, prt_qos, prt_req, prt_data, prt_addr, prt_bytes, prt_ack ); `include "processing_system7_bfm_v2_0_5_local_params.v" input rstn, sw_clk; input [axi_qos_width-1:0] qos1,qos2; input [max_burst_bits-1:0] prt_data1,prt_data2; input [addr_width-1:0] prt_addr1,prt_addr2; input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2; input prt_dv1, prt_dv2, prt_ack; output reg prt_ack1,prt_ack2,prt_req; output reg [max_burst_bits-1:0] prt_data; output reg [addr_width-1:0] prt_addr; output reg [max_burst_bytes_width:0] prt_bytes; output reg [axi_qos_width-1:0] prt_qos; parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11; reg [1:0] state,temp_state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin state = wait_req; prt_req = 1'b0; prt_ack1 = 1'b0; prt_ack2 = 1'b0; prt_qos = 0; end else begin case(state) wait_req:begin state = wait_req; prt_ack1 = 1'b0; prt_ack2 = 1'b0; prt_req = 1'b0; if(prt_dv1 && !prt_dv2) begin state = serv_req1; prt_req = 1; prt_data = prt_data1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; prt_qos = qos1; end else if(!prt_dv1 && prt_dv2) begin state = serv_req2; prt_req = 1; prt_qos = qos2; prt_data = prt_data2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; end else if(prt_dv1 && prt_dv2) begin if(qos1 > qos2) begin prt_req = 1; prt_qos = qos1; prt_data = prt_data1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end else if(qos1 < qos2) begin prt_req = 1; prt_qos = qos2; prt_data = prt_data2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; state = serv_req2; end else begin prt_req = 1; prt_qos = qos1; prt_data = prt_data1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end end end serv_req1:begin state = serv_req1; prt_ack2 = 1'b0; if(prt_ack) begin prt_ack1 = 1'b1; prt_req = 0; if(prt_dv2) begin prt_req = 1; prt_qos = qos2; prt_data = prt_data2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; state = serv_req2; end else begin // state = wait_req; state = wait_ack_low; end end end serv_req2:begin state = serv_req2; prt_ack1 = 1'b0; if(prt_ack) begin prt_ack2 = 1'b1; prt_req = 0; if(prt_dv1) begin prt_req = 1; prt_qos = qos1; prt_data = prt_data1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end else begin state = wait_ack_low; // state = wait_req; end end end wait_ack_low:begin prt_ack1 = 1'b0; prt_ack2 = 1'b0; state = wait_ack_low; if(!prt_ack) state = wait_req; end endcase end /// if else end /// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_arb_wr.v * * Date : 2012-11 * * Description : Module that arbitrates between 2 write requests from 2 ports. * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_arb_wr( rstn, sw_clk, qos1, qos2, prt_dv1, prt_dv2, prt_data1, prt_data2, prt_addr1, prt_addr2, prt_bytes1, prt_bytes2, prt_ack1, prt_ack2, prt_qos, prt_req, prt_data, prt_addr, prt_bytes, prt_ack ); `include "processing_system7_bfm_v2_0_5_local_params.v" input rstn, sw_clk; input [axi_qos_width-1:0] qos1,qos2; input [max_burst_bits-1:0] prt_data1,prt_data2; input [addr_width-1:0] prt_addr1,prt_addr2; input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2; input prt_dv1, prt_dv2, prt_ack; output reg prt_ack1,prt_ack2,prt_req; output reg [max_burst_bits-1:0] prt_data; output reg [addr_width-1:0] prt_addr; output reg [max_burst_bytes_width:0] prt_bytes; output reg [axi_qos_width-1:0] prt_qos; parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11; reg [1:0] state,temp_state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin state = wait_req; prt_req = 1'b0; prt_ack1 = 1'b0; prt_ack2 = 1'b0; prt_qos = 0; end else begin case(state) wait_req:begin state = wait_req; prt_ack1 = 1'b0; prt_ack2 = 1'b0; prt_req = 1'b0; if(prt_dv1 && !prt_dv2) begin state = serv_req1; prt_req = 1; prt_data = prt_data1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; prt_qos = qos1; end else if(!prt_dv1 && prt_dv2) begin state = serv_req2; prt_req = 1; prt_qos = qos2; prt_data = prt_data2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; end else if(prt_dv1 && prt_dv2) begin if(qos1 > qos2) begin prt_req = 1; prt_qos = qos1; prt_data = prt_data1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end else if(qos1 < qos2) begin prt_req = 1; prt_qos = qos2; prt_data = prt_data2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; state = serv_req2; end else begin prt_req = 1; prt_qos = qos1; prt_data = prt_data1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end end end serv_req1:begin state = serv_req1; prt_ack2 = 1'b0; if(prt_ack) begin prt_ack1 = 1'b1; prt_req = 0; if(prt_dv2) begin prt_req = 1; prt_qos = qos2; prt_data = prt_data2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; state = serv_req2; end else begin // state = wait_req; state = wait_ack_low; end end end serv_req2:begin state = serv_req2; prt_ack1 = 1'b0; if(prt_ack) begin prt_ack2 = 1'b1; prt_req = 0; if(prt_dv1) begin prt_req = 1; prt_qos = qos1; prt_data = prt_data1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end else begin state = wait_ack_low; // state = wait_req; end end end wait_ack_low:begin prt_ack1 = 1'b0; prt_ack2 = 1'b0; state = wait_ack_low; if(!prt_ack) state = wait_req; end endcase end /// if else end /// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_arb_wr.v * * Date : 2012-11 * * Description : Module that arbitrates between 2 write requests from 2 ports. * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_arb_wr( rstn, sw_clk, qos1, qos2, prt_dv1, prt_dv2, prt_data1, prt_data2, prt_addr1, prt_addr2, prt_bytes1, prt_bytes2, prt_ack1, prt_ack2, prt_qos, prt_req, prt_data, prt_addr, prt_bytes, prt_ack ); `include "processing_system7_bfm_v2_0_5_local_params.v" input rstn, sw_clk; input [axi_qos_width-1:0] qos1,qos2; input [max_burst_bits-1:0] prt_data1,prt_data2; input [addr_width-1:0] prt_addr1,prt_addr2; input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2; input prt_dv1, prt_dv2, prt_ack; output reg prt_ack1,prt_ack2,prt_req; output reg [max_burst_bits-1:0] prt_data; output reg [addr_width-1:0] prt_addr; output reg [max_burst_bytes_width:0] prt_bytes; output reg [axi_qos_width-1:0] prt_qos; parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11; reg [1:0] state,temp_state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin state = wait_req; prt_req = 1'b0; prt_ack1 = 1'b0; prt_ack2 = 1'b0; prt_qos = 0; end else begin case(state) wait_req:begin state = wait_req; prt_ack1 = 1'b0; prt_ack2 = 1'b0; prt_req = 1'b0; if(prt_dv1 && !prt_dv2) begin state = serv_req1; prt_req = 1; prt_data = prt_data1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; prt_qos = qos1; end else if(!prt_dv1 && prt_dv2) begin state = serv_req2; prt_req = 1; prt_qos = qos2; prt_data = prt_data2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; end else if(prt_dv1 && prt_dv2) begin if(qos1 > qos2) begin prt_req = 1; prt_qos = qos1; prt_data = prt_data1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end else if(qos1 < qos2) begin prt_req = 1; prt_qos = qos2; prt_data = prt_data2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; state = serv_req2; end else begin prt_req = 1; prt_qos = qos1; prt_data = prt_data1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end end end serv_req1:begin state = serv_req1; prt_ack2 = 1'b0; if(prt_ack) begin prt_ack1 = 1'b1; prt_req = 0; if(prt_dv2) begin prt_req = 1; prt_qos = qos2; prt_data = prt_data2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; state = serv_req2; end else begin // state = wait_req; state = wait_ack_low; end end end serv_req2:begin state = serv_req2; prt_ack1 = 1'b0; if(prt_ack) begin prt_ack2 = 1'b1; prt_req = 0; if(prt_dv1) begin prt_req = 1; prt_qos = qos1; prt_data = prt_data1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end else begin state = wait_ack_low; // state = wait_req; end end end wait_ack_low:begin prt_ack1 = 1'b0; prt_ack2 = 1'b0; state = wait_ack_low; if(!prt_ack) state = wait_req; end endcase end /// if else end /// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_afi_slave.v * * Date : 2012-11 * * Description : Model that acts as AFI port interface. It uses AXI3 Slave BFM * from Cadence. *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_afi_slave ( S_RESETN, S_ARREADY, S_AWREADY, S_BVALID, S_RLAST, S_RVALID, S_WREADY, S_BRESP, S_RRESP, S_RDATA, S_BID, S_RID, S_ACLK, S_ARVALID, S_AWVALID, S_BREADY, S_RREADY, S_WLAST, S_WVALID, S_ARBURST, S_ARLOCK, S_ARSIZE, S_AWBURST, S_AWLOCK, S_AWSIZE, S_ARPROT, S_AWPROT, S_ARADDR, S_AWADDR, S_WDATA, S_ARCACHE, S_ARLEN, S_AWCACHE, S_AWLEN, S_WSTRB, S_ARID, S_AWID, S_WID, S_AWQOS, S_ARQOS, SW_CLK, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR, WR_QOS, RD_REQ_DDR, RD_REQ_OCM, RD_ADDR, RD_DATA_OCM, RD_DATA_DDR, RD_BYTES, RD_QOS, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR, S_RDISSUECAP1_EN, S_WRISSUECAP1_EN, S_RCOUNT, S_WCOUNT, S_RACOUNT, S_WACOUNT ); parameter enable_this_port = 0; parameter slave_name = "Slave"; parameter data_bus_width = 32; parameter address_bus_width = 32; parameter id_bus_width = 6; parameter slave_base_address = 0; parameter slave_high_address = 4; parameter max_outstanding_transactions = 8; parameter exclusive_access_supported = 0; `include "processing_system7_bfm_v2_0_5_local_params.v" /* Local parameters only for this module */ /* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles. This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported. 1-bit extra width than the no.of.bits needed to represent the outstanding transactions Extra bit helps in generating the empty and full flags */ parameter int_cntr_width = clogb2(max_outstanding_transactions)+1; /* RESP data */ parameter rsp_fifo_bits = axi_rsp_width+id_bus_width; parameter rsp_lsb = 0; parameter rsp_msb = axi_rsp_width-1; parameter rsp_id_lsb = rsp_msb + 1; parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1; input S_RESETN; output S_ARREADY; output S_AWREADY; output S_BVALID; output S_RLAST; output S_RVALID; output S_WREADY; output [axi_rsp_width-1:0] S_BRESP; output [axi_rsp_width-1:0] S_RRESP; output [data_bus_width-1:0] S_RDATA; output [id_bus_width-1:0] S_BID; output [id_bus_width-1:0] S_RID; input S_ACLK; input S_ARVALID; input S_AWVALID; input S_BREADY; input S_RREADY; input S_WLAST; input S_WVALID; input [axi_brst_type_width-1:0] S_ARBURST; input [axi_lock_width-1:0] S_ARLOCK; input [axi_size_width-1:0] S_ARSIZE; input [axi_brst_type_width-1:0] S_AWBURST; input [axi_lock_width-1:0] S_AWLOCK; input [axi_size_width-1:0] S_AWSIZE; input [axi_prot_width-1:0] S_ARPROT; input [axi_prot_width-1:0] S_AWPROT; input [address_bus_width-1:0] S_ARADDR; input [address_bus_width-1:0] S_AWADDR; input [data_bus_width-1:0] S_WDATA; input [axi_cache_width-1:0] S_ARCACHE; input [axi_cache_width-1:0] S_ARLEN; input [axi_qos_width-1:0] S_ARQOS; input [axi_cache_width-1:0] S_AWCACHE; input [axi_len_width-1:0] S_AWLEN; input [axi_qos_width-1:0] S_AWQOS; input [(data_bus_width/8)-1:0] S_WSTRB; input [id_bus_width-1:0] S_ARID; input [id_bus_width-1:0] S_AWID; input [id_bus_width-1:0] S_WID; input SW_CLK; input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; output [max_burst_bits-1:0] WR_DATA; output [addr_width-1:0] WR_ADDR; output [max_transfer_bytes_width:0] WR_BYTES; output reg RD_REQ_OCM, RD_REQ_DDR; output reg [addr_width-1:0] RD_ADDR; input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM; output reg[max_transfer_bytes_width:0] RD_BYTES; input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR; output [axi_qos_width-1:0] WR_QOS; output reg [axi_qos_width-1:0] RD_QOS; input S_RDISSUECAP1_EN; input S_WRISSUECAP1_EN; output [7:0] S_RCOUNT; output [7:0] S_WCOUNT; output [2:0] S_RACOUNT; output [5:0] S_WACOUNT; wire net_ARVALID; wire net_AWVALID; wire net_WVALID; real s_aclk_period; cdn_axi3_slave_bfm #(slave_name, data_bus_width, address_bus_width, id_bus_width, slave_base_address, (slave_high_address- slave_base_address), max_outstanding_transactions, 0, ///MEMORY_MODEL_MODE, exclusive_access_supported) slave (.ACLK (S_ACLK), .ARESETn (S_RESETN), /// confirm this // Write Address Channel .AWID (S_AWID), .AWADDR (S_AWADDR), .AWLEN (S_AWLEN), .AWSIZE (S_AWSIZE), .AWBURST (S_AWBURST), .AWLOCK (S_AWLOCK), .AWCACHE (S_AWCACHE), .AWPROT (S_AWPROT), .AWVALID (net_AWVALID), .AWREADY (S_AWREADY), // Write Data Channel Signals. .WID (S_WID), .WDATA (S_WDATA), .WSTRB (S_WSTRB), .WLAST (S_WLAST), .WVALID (net_WVALID), .WREADY (S_WREADY), // Write Response Channel Signals. .BID (S_BID), .BRESP (S_BRESP), .BVALID (S_BVALID), .BREADY (S_BREADY), // Read Address Channel Signals. .ARID (S_ARID), .ARADDR (S_ARADDR), .ARLEN (S_ARLEN), .ARSIZE (S_ARSIZE), .ARBURST (S_ARBURST), .ARLOCK (S_ARLOCK), .ARCACHE (S_ARCACHE), .ARPROT (S_ARPROT), .ARVALID (net_ARVALID), .ARREADY (S_ARREADY), // Read Data Channel Signals. .RID (S_RID), .RDATA (S_RDATA), .RRESP (S_RRESP), .RLAST (S_RLAST), .RVALID (S_RVALID), .RREADY (S_RREADY)); wire wr_intr_fifo_full; reg temp_wr_intr_fifo_full; /* Interconnect WR_FIFO model instance */ processing_system7_bfm_v2_0_5_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR); /* Register the async 'full' signal to S_ACLK clock */ always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full; /* Latency type and Debug/Error Control */ reg[1:0] latency_type = RANDOM_CASE; reg DEBUG_INFO = 1; reg STOP_ON_ERROR = 1'b1; /* Internal nets/regs for calling slave BFM API's*/ reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1]; reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0; wire wr_fifo_empty; /* Store the awvalid receive time --- necessary for calculating the bresp latency */ reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0; real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received reg awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received /* Address Write Channel handshake*/ reg[int_cntr_width-1:0] aw_cnt = 0;// /* various FIFOs for storing the ADDR channel info */ reg [axi_size_width-1:0] awsize [0:max_outstanding_transactions-1]; reg [axi_prot_width-1:0] awprot [0:max_outstanding_transactions-1]; reg [axi_lock_width-1:0] awlock [0:max_outstanding_transactions-1]; reg [axi_cache_width-1:0] awcache [0:max_outstanding_transactions-1]; reg [axi_brst_type_width-1:0] awbrst [0:max_outstanding_transactions-1]; reg [axi_len_width-1:0] awlen [0:max_outstanding_transactions-1]; reg aw_flag [0:max_outstanding_transactions-1]; reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1]; reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1]; reg [axi_qos_width-1:0] awqos [0:max_outstanding_transactions-1]; wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached) /* internal fifos to store burst write data, ID & strobes*/ reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1]; reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer reg wlast_flag [0:max_outstanding_transactions-1]; // flag to indicate WLAST received wire wd_fifo_full; /* Write Data Channel and Write Response handshake signals*/ reg [int_cntr_width-1:0] wd_cnt = 0; reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data; reg [addr_width-1:0] aligned_wr_addr; reg [max_burst_bytes_width:0] valid_data_bytes; reg [int_cntr_width-1:0] wr_bresp_cnt = 0; reg [axi_rsp_width-1:0] bresp; reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response reg enable_write_bresp; reg [int_cntr_width-1:0] rd_bresp_cnt = 0; integer wr_latency_count; reg wr_delayed; wire bresp_fifo_empty; /* keep track of count values */ reg[7:0] wcount; reg[5:0] wacount; /* Qos*/ reg [axi_qos_width-1:0] ar_qos, aw_qos; initial begin if(DEBUG_INFO) begin if(enable_this_port) $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name); else $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name); end end /*--------------------------------------------------------------------------------*/ /* Store the Clock cycle time period */ always@(S_RESETN) begin if(S_RESETN) begin @(posedge S_ACLK); s_aclk_period = $time; @(posedge S_ACLK); s_aclk_period = $time - s_aclk_period; end end /*--------------------------------------------------------------------------------*/ initial slave.set_disable_reset_value_checks(1); initial begin repeat(2) @(posedge S_ACLK); if(!enable_this_port) begin slave.set_channel_level_info(0); slave.set_function_level_info(0); end slave.RESPONSE_TIMEOUT = 0; end /*--------------------------------------------------------------------------------*/ /* Set Latency type to be used */ task set_latency_type; input[1:0] lat; begin if(enable_this_port) latency_type = lat; else begin //if(DEBUG_INFO) $display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name); end end endtask /*--------------------------------------------------------------------------------*/ /* Set ARQoS to be used */ task set_arqos; input[axi_qos_width-1:0] qos; begin if(enable_this_port) ar_qos = qos; else begin if(DEBUG_INFO) $display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name); end end endtask /*--------------------------------------------------------------------------------*/ /* Set AWQoS to be used */ task set_awqos; input[axi_qos_width-1:0] qos; begin if(enable_this_port) aw_qos = qos; else begin if(DEBUG_INFO) $display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name); end end endtask /*--------------------------------------------------------------------------------*/ /* get the wr latency number */ function [31:0] get_wr_lat_number; input dummy; reg[1:0] temp; begin case(latency_type) BEST_CASE : get_wr_lat_number = afi_wr_min; AVG_CASE : get_wr_lat_number = afi_wr_avg; WORST_CASE : get_wr_lat_number = afi_wr_max; default : begin // RANDOM_CASE temp = $random; case(temp) 2'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min); 2'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg); default : get_wr_lat_number = ($random()%60+ afi_wr_max); endcase end endcase end endfunction /*--------------------------------------------------------------------------------*/ /* get the rd latency number */ function [31:0] get_rd_lat_number; input dummy; reg[1:0] temp; begin case(latency_type) BEST_CASE : get_rd_lat_number = afi_rd_min; AVG_CASE : get_rd_lat_number = afi_rd_avg; WORST_CASE : get_rd_lat_number = afi_rd_max; default : begin // RANDOM_CASE temp = $random; case(temp) 2'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min); 2'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg); default : get_rd_lat_number = ($random()%60+ afi_rd_max); endcase end endcase end endfunction /*--------------------------------------------------------------------------------*/ /* Check for any WRITE/READs when this port is disabled */ always@(S_AWVALID or S_WVALID or S_ARVALID) begin if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin $display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name); $stop; end end /*--------------------------------------------------------------------------------*/ assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0; assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0; assign net_WVALID = enable_this_port ? S_WVALID : 1'b0; assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0; assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0; assign bresp_fifo_full = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1'b1:1'b0; assign S_WCOUNT = wcount; assign S_WACOUNT = wacount; // FIFO_STATUS (only if AFI port) 1- full function automatic wrfifo_full ; input [axi_len_width:0] fifo_space_exp; integer fifo_space_left; begin fifo_space_left = afi_fifo_locations - wcount; if(fifo_space_left < fifo_space_exp) wrfifo_full = 1; else wrfifo_full = 0; end endfunction /*--------------------------------------------------------------------------------*/ /* Store the awvalid receive time --- necessary for calculating the bresp latency */ always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID ) begin if(!S_RESETN) aw_time_cnt = 0; else begin if(S_AWVALID) begin awvalid_receive_time[aw_time_cnt] = $time; awvalid_flag[aw_time_cnt] = 1'b1; aw_time_cnt = aw_time_cnt + 1; end end // else end /// always /*--------------------------------------------------------------------------------*/ always@(posedge S_ACLK) begin if(net_AWVALID && S_AWREADY) begin if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos; else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS; end end /* Address Write Channel handshake*/ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin aw_cnt = 0; wacount = 0; end else begin if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin slave.RECEIVE_WRITE_ADDRESS(0, id_invalid, awaddr[aw_cnt[int_cntr_width-2:0]], awlen[aw_cnt[int_cntr_width-2:0]], awsize[aw_cnt[int_cntr_width-2:0]], awbrst[aw_cnt[int_cntr_width-2:0]], awlock[aw_cnt[int_cntr_width-2:0]], awcache[aw_cnt[int_cntr_width-2:0]], awprot[aw_cnt[int_cntr_width-2:0]], awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID. aw_flag[aw_cnt[int_cntr_width-2:0]] = 1'b1; aw_cnt = aw_cnt + 1; wacount = wacount + 1; end // if (!aw_fifo_full) end /// if else end /// always /*--------------------------------------------------------------------------------*/ /* Write Data Channel Handshake */ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin wd_cnt = 0; end else begin if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]); wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1; wd_cnt = wd_cnt + 1; end end else begin if(!wrfifo_full(axi_burst_len+1) && S_WVALID) begin slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]); wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1; wd_cnt = wd_cnt + 1; end end /// if end /// else end /// always /*--------------------------------------------------------------------------------*/ /* Align the wrap data for write transaction */ task automatic get_wrap_aligned_wr_data; output [(data_bus_width*axi_burst_len)-1:0] aligned_data; output [addr_width-1:0] start_addr; /// aligned start address input [addr_width-1:0] addr; input [(data_bus_width*axi_burst_len)-1:0] b_data; input [max_burst_bytes_width:0] v_bytes; reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; integer wrp_bytes; integer i; begin start_addr = (addr/v_bytes) * v_bytes; wrp_bytes = addr - start_addr; wrp_data = b_data; temp_data = 0; wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8)); while(wrp_bytes > 0) begin /// get the data that is wrapped temp_data = temp_data << 8; temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8]; wrp_data = wrp_data << 8; wrp_bytes = wrp_bytes - 1; end wrp_bytes = addr - start_addr; wrp_data = b_data << (wrp_bytes*8); aligned_data = (temp_data | wrp_data); end endtask /*--------------------------------------------------------------------------------*/ /* Calculate the Response for each read/write transaction */ function [axi_rsp_width-1:0] calculate_resp; input [addr_width-1:0] awaddr; input [axi_prot_width-1:0] awprot; reg [axi_rsp_width-1:0] rsp; begin rsp = AXI_OK; /* Address Decode */ if(decode_address(awaddr) === INVALID_MEM_TYPE) begin rsp = AXI_SLV_ERR; //slave error $display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr); end else if(decode_address(awaddr) === REG_MEM) begin rsp = AXI_SLV_ERR; //slave error $display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr); end if(secure_access_enabled && awprot[1]) rsp = AXI_DEC_ERR; // decode error calculate_resp = rsp; end endfunction /*--------------------------------------------------------------------------------*/ reg[max_burst_bits-1:0] temp_wr_data; /* Store the Write response for each write transaction */ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin wr_fifo_wr_ptr = 0; wcount = 0; end else begin enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]]; /* calculate bresp only when AWVALID && WLAST is received */ if(enable_write_bresp) begin aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0; wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0; bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /* Fill AFI_WR_data FIFO */ if(bresp === AXI_OK ) begin if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address end else begin aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]]; aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ; end valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]; end else valid_data_bytes = 0; temp_wr_data = aligned_wr_data; wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes}; wcount = wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1; wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1; end end // else end // always /*--------------------------------------------------------------------------------*/ /* Send Write Response Channel handshake */ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin rd_bresp_cnt = 0; wr_latency_count = get_wr_lat_number(1); wr_delayed = 0; bresp_time_cnt = 0; end else begin wr_delayed = 1'b0; if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count)) wr_delayed = 1; if(!bresp_fifo_empty && wr_delayed) begin slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response ); wr_delayed = 0; awvalid_flag[bresp_time_cnt] = 1'b0; bresp_time_cnt = bresp_time_cnt+1; rd_bresp_cnt = rd_bresp_cnt + 1; wr_latency_count = get_wr_lat_number(1); end end // else end//always /*--------------------------------------------------------------------------------*/ /* Write Response Channel handshake */ reg wr_int_state; /* Reading from the wr_fifo and sending to Interconnect fifo*/ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin wr_int_state = 1'b0; wr_bresp_cnt = 0; wr_fifo_rd_ptr = 0; end else begin case(wr_int_state) 1'b0 : begin wr_int_state = 1'b0; if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes wr_int_state = 1'b1; /* start filling the write response fifo at the same time */ fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] = wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp wcount = wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length wacount = wacount - 1; wr_fifo_rd_ptr = wr_fifo_rd_ptr + 1; wr_bresp_cnt = wr_bresp_cnt+1; end end 1'b1 : begin wr_int_state = 0; end endcase end end /*--------------------------------------------------------------------------------*/ /*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/ /*-------------------------------- READ HANDSHAKE ---------------------------------------------*/ /* READ CHANNELS */ /* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */ reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0; real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info /* various FIFOs for storing the ADDR channel info */ reg [axi_size_width-1:0] arsize [0:max_outstanding_transactions-1]; reg [axi_prot_width-1:0] arprot [0:max_outstanding_transactions-1]; reg [axi_brst_type_width-1:0] arbrst [0:max_outstanding_transactions-1]; reg [axi_len_width-1:0] arlen [0:max_outstanding_transactions-1]; reg [axi_cache_width-1:0] arcache [0:max_outstanding_transactions-1]; reg [axi_lock_width-1:0] arlock [0:max_outstanding_transactions-1]; reg ar_flag [0:max_outstanding_transactions-1]; reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1]; reg [id_bus_width-1:0] arid [0:max_outstanding_transactions-1]; reg [axi_qos_width-1:0] arqos [0:max_outstanding_transactions-1]; wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached) reg [int_cntr_width-1:0] wr_rresp_cnt = 0; reg [axi_rsp_width-1:0] rresp; reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response reg enable_write_rresp; /* Send Read Response & Data Channel handshake */ integer rd_latency_count; reg rd_delayed; reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0; wire read_fifo_full; reg [7:0] rcount; reg [2:0] racount; wire rd_intr_fifo_full, rd_intr_fifo_empty; wire read_fifo_empty; /* signals to communicate with interconnect RD_FIFO model */ reg rd_req, invalid_rd_req; /* REad control Info 56:25 : Address (32) 24:22 : Size (3) 21:20 : BRST (2) 19:16 : LEN (4) 15:10 : RID (6) 9:8 : RRSP (2) 7:0 : byte cnt (8) */ reg [rd_info_bits-1:0] read_control_info; reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data; reg temp_rd_intr_fifo_empty; processing_system7_bfm_v2_0_5_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR); assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0; assign S_RCOUNT = rcount; assign S_RACOUNT = racount; /* Register the asynch signal empty coming from Interconnect READ FIFO */ always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty; // FIFO_STATUS (only if AFI port) 1- full function automatic rdfifo_full ; input [axi_len_width:0] fifo_space_exp; integer fifo_space_left; begin fifo_space_left = afi_fifo_locations - rcount; if(fifo_space_left < fifo_space_exp) rdfifo_full = 1; else rdfifo_full = 0; end endfunction /* Store the arvalid receive time --- necessary for calculating the bresp latency */ always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID ) begin if(!S_RESETN) ar_time_cnt = 0; else begin if(S_ARVALID) begin arvalid_receive_time[ar_time_cnt] = $time; arvalid_flag[ar_time_cnt] = 1'b1; ar_time_cnt = ar_time_cnt + 1; end end // else end /// always /*--------------------------------------------------------------------------------*/ always@(posedge S_ACLK) begin if(net_ARVALID && S_ARREADY) begin if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos; else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS; end end /* Address Read Channel handshake*/ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin ar_cnt = 0; racount = 0; end else begin if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full slave.RECEIVE_READ_ADDRESS(0, id_invalid, araddr[ar_cnt[int_cntr_width-2:0]], arlen[ar_cnt[int_cntr_width-2:0]], arsize[ar_cnt[int_cntr_width-2:0]], arbrst[ar_cnt[int_cntr_width-2:0]], arlock[ar_cnt[int_cntr_width-2:0]], arcache[ar_cnt[int_cntr_width-2:0]], arprot[ar_cnt[int_cntr_width-2:0]], arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID. ar_flag[ar_cnt[int_cntr_width-2:0]] = 1'b1; ar_cnt = ar_cnt+1; racount = racount + 1; end /// if(!ar_fifo_full) end /// if else end /// always*/ /*--------------------------------------------------------------------------------*/ /* Align Wrap data for read transaction*/ task automatic get_wrap_aligned_rd_data; output [(data_bus_width*axi_burst_len)-1:0] aligned_data; input [addr_width-1:0] addr; input [(data_bus_width*axi_burst_len)-1:0] b_data; input [max_burst_bytes_width:0] v_bytes; reg [addr_width-1:0] start_addr; reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; integer wrp_bytes; integer i; begin start_addr = (addr/v_bytes) * v_bytes; wrp_bytes = addr - start_addr; wrp_data = b_data; temp_data = 0; while(wrp_bytes > 0) begin /// get the data that is wrapped temp_data = temp_data >> 8; temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0]; wrp_data = wrp_data >> 8; wrp_bytes = wrp_bytes - 1; end temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8)); wrp_bytes = addr - start_addr; wrp_data = b_data >> (wrp_bytes*8); aligned_data = (temp_data | wrp_data); end endtask /*--------------------------------------------------------------------------------*/ parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1; reg rd_fifo_state; reg [addr_width-1:0] temp_read_address; reg [max_burst_bytes_width:0] temp_rd_valid_bytes; /* get the data from memory && also calculate the rresp*/ always@(negedge S_RESETN or posedge SW_CLK) begin if(!S_RESETN)begin wr_rresp_cnt =0; rd_fifo_state = RD_DATA_REQ; temp_rd_valid_bytes = 0; temp_read_address = 0; RD_REQ_DDR = 1'b0; RD_REQ_OCM = 1'b0; rd_req = 0; invalid_rd_req= 0; RD_QOS = 0; end else begin case(rd_fifo_state) RD_DATA_REQ : begin rd_fifo_state = RD_DATA_REQ; RD_REQ_DDR = 1'b0; RD_REQ_OCM = 1'b0; invalid_rd_req = 0; if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] = 0; rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]); temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8; if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes; else temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]]; if(rresp === AXI_OK) begin case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]); OCM_MEM : RD_REQ_OCM = 1; DDR_MEM : RD_REQ_DDR = 1; default : invalid_rd_req = 1; endcase end else invalid_rd_req = 1; RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]]; RD_BYTES = temp_rd_valid_bytes; RD_QOS = arqos[wr_rresp_cnt[int_cntr_width-2:0]]; rd_fifo_state = WAIT_RD_VALID; rd_req = 1; racount = racount - 1; read_control_info = {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes }; wr_rresp_cnt = wr_rresp_cnt + 1; end end WAIT_RD_VALID : begin rd_fifo_state = WAIT_RD_VALID; rd_req = 0; if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin RD_REQ_DDR = 1'b0; RD_REQ_OCM = 1'b0; invalid_rd_req = 0; rd_fifo_state = RD_DATA_REQ; end end endcase end /// else end /// always /*--------------------------------------------------------------------------------*/ /* thread to fill in the AFI RD_FIFO */ reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes reg tmp_state; always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN)begin rd_fifo_wr_ptr = 0; rcount = 0; tmp_state = 0; end else begin case(tmp_state) 0 : begin tmp_state = 0; if(!temp_rd_intr_fifo_empty) begin rd_intr_fifo.read_mem(temp_rd_data); tmp_state = 1; end end 1 : begin tmp_state = 1; if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data; rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1; rcount = rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length tmp_state = 0; end end endcase end end /*--------------------------------------------------------------------------------*/ reg[max_burst_bytes_width:0] rd_v_b; reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data; reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp; /* Read Data Channel handshake */ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN)begin rd_fifo_rd_ptr = 0; rd_latency_count = get_rd_lat_number(1); rd_delayed = 0; rresp_time_cnt = 0; rd_v_b = 0; end else begin if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin rd_delayed = 1; end if(!read_fifo_empty && rd_delayed)begin rd_delayed = 0; arvalid_flag[rresp_time_cnt] = 1'b0; tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]]; rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]); temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb]; if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b); temp_read_data = aligned_rd_data; end temp_read_rsp = 0; repeat(axi_burst_len) begin temp_read_rsp = temp_read_rsp >> axi_rsp_width; temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb]; end slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb], tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb], tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb], tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb], temp_read_data, temp_read_rsp); rcount = rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ; rresp_time_cnt = rresp_time_cnt+1; rd_latency_count = get_rd_lat_number(1); rd_fifo_rd_ptr = rd_fifo_rd_ptr+1; end end /// else end /// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_regc.v * * Date : 2012-11 * * Description : Controller for Register Map Memory * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_regc( rstn, sw_clk, /* Goes to port 0 of REG */ reg_rd_req_port0, reg_rd_dv_port0, reg_rd_addr_port0, reg_rd_data_port0, reg_rd_bytes_port0, reg_rd_qos_port0, /* Goes to port 1 of REG */ reg_rd_req_port1, reg_rd_dv_port1, reg_rd_addr_port1, reg_rd_data_port1, reg_rd_bytes_port1, reg_rd_qos_port1 ); input rstn; input sw_clk; input reg_rd_req_port0; output reg_rd_dv_port0; input[31:0] reg_rd_addr_port0; output[1023:0] reg_rd_data_port0; input[7:0] reg_rd_bytes_port0; input [3:0] reg_rd_qos_port0; input reg_rd_req_port1; output reg_rd_dv_port1; input[31:0] reg_rd_addr_port1; output[1023:0] reg_rd_data_port1; input[7:0] reg_rd_bytes_port1; input[3:0] reg_rd_qos_port1; wire [3:0] rd_qos; reg [1023:0] rd_data; wire [31:0] rd_addr; wire [7:0] rd_bytes; reg rd_dv; wire rd_req; processing_system7_bfm_v2_0_5_arb_rd reg_read_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(reg_rd_qos_port0), .qos2(reg_rd_qos_port1), .prt_req1(reg_rd_req_port0), .prt_req2(reg_rd_req_port1), .prt_data1(reg_rd_data_port0), .prt_data2(reg_rd_data_port1), .prt_addr1(reg_rd_addr_port0), .prt_addr2(reg_rd_addr_port1), .prt_bytes1(reg_rd_bytes_port0), .prt_bytes2(reg_rd_bytes_port1), .prt_dv1(reg_rd_dv_port0), .prt_dv2(reg_rd_dv_port1), .prt_qos(rd_qos), .prt_req(rd_req), .prt_data(rd_data), .prt_addr(rd_addr), .prt_bytes(rd_bytes), .prt_dv(rd_dv) ); processing_system7_bfm_v2_0_5_reg_map regm(); reg state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin rd_dv <= 0; state <= 0; end else begin case(state) 0:begin state <= 0; rd_dv <= 0; if(rd_req) begin regm.read_reg_mem(rd_data,rd_addr, rd_bytes); rd_dv <= 1; state <= 1; end end 1:begin rd_dv <= 0; state <= 0; end endcase end /// if end// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_regc.v * * Date : 2012-11 * * Description : Controller for Register Map Memory * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_regc( rstn, sw_clk, /* Goes to port 0 of REG */ reg_rd_req_port0, reg_rd_dv_port0, reg_rd_addr_port0, reg_rd_data_port0, reg_rd_bytes_port0, reg_rd_qos_port0, /* Goes to port 1 of REG */ reg_rd_req_port1, reg_rd_dv_port1, reg_rd_addr_port1, reg_rd_data_port1, reg_rd_bytes_port1, reg_rd_qos_port1 ); input rstn; input sw_clk; input reg_rd_req_port0; output reg_rd_dv_port0; input[31:0] reg_rd_addr_port0; output[1023:0] reg_rd_data_port0; input[7:0] reg_rd_bytes_port0; input [3:0] reg_rd_qos_port0; input reg_rd_req_port1; output reg_rd_dv_port1; input[31:0] reg_rd_addr_port1; output[1023:0] reg_rd_data_port1; input[7:0] reg_rd_bytes_port1; input[3:0] reg_rd_qos_port1; wire [3:0] rd_qos; reg [1023:0] rd_data; wire [31:0] rd_addr; wire [7:0] rd_bytes; reg rd_dv; wire rd_req; processing_system7_bfm_v2_0_5_arb_rd reg_read_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(reg_rd_qos_port0), .qos2(reg_rd_qos_port1), .prt_req1(reg_rd_req_port0), .prt_req2(reg_rd_req_port1), .prt_data1(reg_rd_data_port0), .prt_data2(reg_rd_data_port1), .prt_addr1(reg_rd_addr_port0), .prt_addr2(reg_rd_addr_port1), .prt_bytes1(reg_rd_bytes_port0), .prt_bytes2(reg_rd_bytes_port1), .prt_dv1(reg_rd_dv_port0), .prt_dv2(reg_rd_dv_port1), .prt_qos(rd_qos), .prt_req(rd_req), .prt_data(rd_data), .prt_addr(rd_addr), .prt_bytes(rd_bytes), .prt_dv(rd_dv) ); processing_system7_bfm_v2_0_5_reg_map regm(); reg state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin rd_dv <= 0; state <= 0; end else begin case(state) 0:begin state <= 0; rd_dv <= 0; if(rd_req) begin regm.read_reg_mem(rd_data,rd_addr, rd_bytes); rd_dv <= 1; state <= 1; end end 1:begin rd_dv <= 0; state <= 0; end endcase end /// if end// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_regc.v * * Date : 2012-11 * * Description : Controller for Register Map Memory * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_regc( rstn, sw_clk, /* Goes to port 0 of REG */ reg_rd_req_port0, reg_rd_dv_port0, reg_rd_addr_port0, reg_rd_data_port0, reg_rd_bytes_port0, reg_rd_qos_port0, /* Goes to port 1 of REG */ reg_rd_req_port1, reg_rd_dv_port1, reg_rd_addr_port1, reg_rd_data_port1, reg_rd_bytes_port1, reg_rd_qos_port1 ); input rstn; input sw_clk; input reg_rd_req_port0; output reg_rd_dv_port0; input[31:0] reg_rd_addr_port0; output[1023:0] reg_rd_data_port0; input[7:0] reg_rd_bytes_port0; input [3:0] reg_rd_qos_port0; input reg_rd_req_port1; output reg_rd_dv_port1; input[31:0] reg_rd_addr_port1; output[1023:0] reg_rd_data_port1; input[7:0] reg_rd_bytes_port1; input[3:0] reg_rd_qos_port1; wire [3:0] rd_qos; reg [1023:0] rd_data; wire [31:0] rd_addr; wire [7:0] rd_bytes; reg rd_dv; wire rd_req; processing_system7_bfm_v2_0_5_arb_rd reg_read_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(reg_rd_qos_port0), .qos2(reg_rd_qos_port1), .prt_req1(reg_rd_req_port0), .prt_req2(reg_rd_req_port1), .prt_data1(reg_rd_data_port0), .prt_data2(reg_rd_data_port1), .prt_addr1(reg_rd_addr_port0), .prt_addr2(reg_rd_addr_port1), .prt_bytes1(reg_rd_bytes_port0), .prt_bytes2(reg_rd_bytes_port1), .prt_dv1(reg_rd_dv_port0), .prt_dv2(reg_rd_dv_port1), .prt_qos(rd_qos), .prt_req(rd_req), .prt_data(rd_data), .prt_addr(rd_addr), .prt_bytes(rd_bytes), .prt_dv(rd_dv) ); processing_system7_bfm_v2_0_5_reg_map regm(); reg state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin rd_dv <= 0; state <= 0; end else begin case(state) 0:begin state <= 0; rd_dv <= 0; if(rd_req) begin regm.read_reg_mem(rd_data,rd_addr, rd_bytes); rd_dv <= 1; state <= 1; end end 1:begin rd_dv <= 0; state <= 0; end endcase end /// if end// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_regc.v * * Date : 2012-11 * * Description : Controller for Register Map Memory * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_regc( rstn, sw_clk, /* Goes to port 0 of REG */ reg_rd_req_port0, reg_rd_dv_port0, reg_rd_addr_port0, reg_rd_data_port0, reg_rd_bytes_port0, reg_rd_qos_port0, /* Goes to port 1 of REG */ reg_rd_req_port1, reg_rd_dv_port1, reg_rd_addr_port1, reg_rd_data_port1, reg_rd_bytes_port1, reg_rd_qos_port1 ); input rstn; input sw_clk; input reg_rd_req_port0; output reg_rd_dv_port0; input[31:0] reg_rd_addr_port0; output[1023:0] reg_rd_data_port0; input[7:0] reg_rd_bytes_port0; input [3:0] reg_rd_qos_port0; input reg_rd_req_port1; output reg_rd_dv_port1; input[31:0] reg_rd_addr_port1; output[1023:0] reg_rd_data_port1; input[7:0] reg_rd_bytes_port1; input[3:0] reg_rd_qos_port1; wire [3:0] rd_qos; reg [1023:0] rd_data; wire [31:0] rd_addr; wire [7:0] rd_bytes; reg rd_dv; wire rd_req; processing_system7_bfm_v2_0_5_arb_rd reg_read_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(reg_rd_qos_port0), .qos2(reg_rd_qos_port1), .prt_req1(reg_rd_req_port0), .prt_req2(reg_rd_req_port1), .prt_data1(reg_rd_data_port0), .prt_data2(reg_rd_data_port1), .prt_addr1(reg_rd_addr_port0), .prt_addr2(reg_rd_addr_port1), .prt_bytes1(reg_rd_bytes_port0), .prt_bytes2(reg_rd_bytes_port1), .prt_dv1(reg_rd_dv_port0), .prt_dv2(reg_rd_dv_port1), .prt_qos(rd_qos), .prt_req(rd_req), .prt_data(rd_data), .prt_addr(rd_addr), .prt_bytes(rd_bytes), .prt_dv(rd_dv) ); processing_system7_bfm_v2_0_5_reg_map regm(); reg state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin rd_dv <= 0; state <= 0; end else begin case(state) 0:begin state <= 0; rd_dv <= 0; if(rd_req) begin regm.read_reg_mem(rd_data,rd_addr, rd_bytes); rd_dv <= 1; state <= 1; end end 1:begin rd_dv <= 0; state <= 0; end endcase end /// if end// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_ssw_hp.v * * Date : 2012-11 * * Description : SSW switch Model * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_ssw_hp( sw_clk, rstn, w_qos_hp0, r_qos_hp0, w_qos_hp1, r_qos_hp1, w_qos_hp2, r_qos_hp2, w_qos_hp3, r_qos_hp3, wr_ack_ddr_hp0, wr_data_hp0, wr_addr_hp0, wr_bytes_hp0, wr_dv_ddr_hp0, rd_req_ddr_hp0, rd_addr_hp0, rd_bytes_hp0, rd_data_ddr_hp0, rd_dv_ddr_hp0, rd_data_ocm_hp0, wr_ack_ocm_hp0, wr_dv_ocm_hp0, rd_req_ocm_hp0, rd_dv_ocm_hp0, wr_ack_ddr_hp1, wr_data_hp1, wr_addr_hp1, wr_bytes_hp1, wr_dv_ddr_hp1, rd_req_ddr_hp1, rd_addr_hp1, rd_bytes_hp1, rd_data_ddr_hp1, rd_data_ocm_hp1, rd_dv_ddr_hp1, wr_ack_ocm_hp1, wr_dv_ocm_hp1, rd_req_ocm_hp1, rd_dv_ocm_hp1, wr_ack_ddr_hp2, wr_data_hp2, wr_addr_hp2, wr_bytes_hp2, wr_dv_ddr_hp2, rd_req_ddr_hp2, rd_addr_hp2, rd_bytes_hp2, rd_data_ddr_hp2, rd_data_ocm_hp2, rd_dv_ddr_hp2, wr_ack_ocm_hp2, wr_dv_ocm_hp2, rd_req_ocm_hp2, rd_dv_ocm_hp2, wr_ack_ddr_hp3, wr_data_hp3, wr_addr_hp3, wr_bytes_hp3, wr_dv_ddr_hp3, rd_req_ddr_hp3, rd_addr_hp3, rd_bytes_hp3, rd_data_ocm_hp3, rd_data_ddr_hp3, rd_dv_ddr_hp3, wr_ack_ocm_hp3, wr_dv_ocm_hp3, rd_req_ocm_hp3, rd_dv_ocm_hp3, ddr_wr_ack0, ddr_wr_dv0, ddr_rd_req0, ddr_rd_dv0, ddr_rd_qos0, ddr_wr_qos0, ddr_wr_addr0, ddr_wr_data0, ddr_wr_bytes0, ddr_rd_addr0, ddr_rd_data0, ddr_rd_bytes0, ddr_wr_ack1, ddr_wr_dv1, ddr_rd_req1, ddr_rd_dv1, ddr_rd_qos1, ddr_wr_qos1, ddr_wr_addr1, ddr_wr_data1, ddr_wr_bytes1, ddr_rd_addr1, ddr_rd_data1, ddr_rd_bytes1, ocm_wr_ack, ocm_wr_dv, ocm_rd_req, ocm_rd_dv, ocm_wr_qos, ocm_rd_qos, ocm_wr_addr, ocm_wr_data, ocm_wr_bytes, ocm_rd_addr, ocm_rd_data, ocm_rd_bytes ); input sw_clk; input rstn; input [3:0] w_qos_hp0; input [3:0] r_qos_hp0; input [3:0] w_qos_hp1; input [3:0] r_qos_hp1; input [3:0] w_qos_hp2; input [3:0] r_qos_hp2; input [3:0] w_qos_hp3; input [3:0] r_qos_hp3; output [3:0] ddr_rd_qos0; output [3:0] ddr_wr_qos0; output [3:0] ddr_rd_qos1; output [3:0] ddr_wr_qos1; output [3:0] ocm_wr_qos; output [3:0] ocm_rd_qos; output wr_ack_ddr_hp0; input [1023:0] wr_data_hp0; input [31:0] wr_addr_hp0; input [7:0] wr_bytes_hp0; output wr_dv_ddr_hp0; input rd_req_ddr_hp0; input [31:0] rd_addr_hp0; input [7:0] rd_bytes_hp0; output [1023:0] rd_data_ddr_hp0; output rd_dv_ddr_hp0; output wr_ack_ddr_hp1; input [1023:0] wr_data_hp1; input [31:0] wr_addr_hp1; input [7:0] wr_bytes_hp1; output wr_dv_ddr_hp1; input rd_req_ddr_hp1; input [31:0] rd_addr_hp1; input [7:0] rd_bytes_hp1; output [1023:0] rd_data_ddr_hp1; output rd_dv_ddr_hp1; output wr_ack_ddr_hp2; input [1023:0] wr_data_hp2; input [31:0] wr_addr_hp2; input [7:0] wr_bytes_hp2; output wr_dv_ddr_hp2; input rd_req_ddr_hp2; input [31:0] rd_addr_hp2; input [7:0] rd_bytes_hp2; output [1023:0] rd_data_ddr_hp2; output rd_dv_ddr_hp2; output wr_ack_ddr_hp3; input [1023:0] wr_data_hp3; input [31:0] wr_addr_hp3; input [7:0] wr_bytes_hp3; output wr_dv_ddr_hp3; input rd_req_ddr_hp3; input [31:0] rd_addr_hp3; input [7:0] rd_bytes_hp3; output [1023:0] rd_data_ddr_hp3; output rd_dv_ddr_hp3; input ddr_wr_ack0; output ddr_wr_dv0; output [31:0]ddr_wr_addr0; output [1023:0]ddr_wr_data0; output [7:0]ddr_wr_bytes0; input ddr_rd_dv0; input [1023:0] ddr_rd_data0; output ddr_rd_req0; output [31:0] ddr_rd_addr0; output [7:0] ddr_rd_bytes0; input ddr_wr_ack1; output ddr_wr_dv1; output [31:0]ddr_wr_addr1; output [1023:0]ddr_wr_data1; output [7:0]ddr_wr_bytes1; input ddr_rd_dv1; input [1023:0] ddr_rd_data1; output ddr_rd_req1; output [31:0] ddr_rd_addr1; output [7:0] ddr_rd_bytes1; output wr_ack_ocm_hp0; input wr_dv_ocm_hp0; input rd_req_ocm_hp0; output rd_dv_ocm_hp0; output [1023:0] rd_data_ocm_hp0; output wr_ack_ocm_hp1; input wr_dv_ocm_hp1; input rd_req_ocm_hp1; output rd_dv_ocm_hp1; output [1023:0] rd_data_ocm_hp1; output wr_ack_ocm_hp2; input wr_dv_ocm_hp2; input rd_req_ocm_hp2; output rd_dv_ocm_hp2; output [1023:0] rd_data_ocm_hp2; output wr_ack_ocm_hp3; input wr_dv_ocm_hp3; input rd_req_ocm_hp3; output rd_dv_ocm_hp3; output [1023:0] rd_data_ocm_hp3; input ocm_wr_ack; output ocm_wr_dv; output [31:0]ocm_wr_addr; output [1023:0]ocm_wr_data; output [7:0]ocm_wr_bytes; input ocm_rd_dv; input [1023:0] ocm_rd_data; output ocm_rd_req; output [31:0] ocm_rd_addr; output [7:0] ocm_rd_bytes; /* FOR DDR */ processing_system7_bfm_v2_0_5_arb_hp0_1 ddr_hp01 ( .sw_clk(sw_clk), .rstn(rstn), .w_qos_hp0(w_qos_hp0), .r_qos_hp0(r_qos_hp0), .w_qos_hp1(w_qos_hp1), .r_qos_hp1(r_qos_hp1), .wr_ack_ddr_hp0(wr_ack_ddr_hp0), .wr_data_hp0(wr_data_hp0), .wr_addr_hp0(wr_addr_hp0), .wr_bytes_hp0(wr_bytes_hp0), .wr_dv_ddr_hp0(wr_dv_ddr_hp0), .rd_req_ddr_hp0(rd_req_ddr_hp0), .rd_addr_hp0(rd_addr_hp0), .rd_bytes_hp0(rd_bytes_hp0), .rd_data_ddr_hp0(rd_data_ddr_hp0), .rd_dv_ddr_hp0(rd_dv_ddr_hp0), .wr_ack_ddr_hp1(wr_ack_ddr_hp1), .wr_data_hp1(wr_data_hp1), .wr_addr_hp1(wr_addr_hp1), .wr_bytes_hp1(wr_bytes_hp1), .wr_dv_ddr_hp1(wr_dv_ddr_hp1), .rd_req_ddr_hp1(rd_req_ddr_hp1), .rd_addr_hp1(rd_addr_hp1), .rd_bytes_hp1(rd_bytes_hp1), .rd_data_ddr_hp1(rd_data_ddr_hp1), .rd_dv_ddr_hp1(rd_dv_ddr_hp1), .ddr_wr_ack(ddr_wr_ack0), .ddr_wr_dv(ddr_wr_dv0), .ddr_rd_req(ddr_rd_req0), .ddr_rd_dv(ddr_rd_dv0), .ddr_rd_qos(ddr_rd_qos0), .ddr_wr_qos(ddr_wr_qos0), .ddr_wr_addr(ddr_wr_addr0), .ddr_wr_data(ddr_wr_data0), .ddr_wr_bytes(ddr_wr_bytes0), .ddr_rd_addr(ddr_rd_addr0), .ddr_rd_data(ddr_rd_data0), .ddr_rd_bytes(ddr_rd_bytes0) ); /* FOR DDR */ processing_system7_bfm_v2_0_5_arb_hp2_3 ddr_hp23 ( .sw_clk(sw_clk), .rstn(rstn), .w_qos_hp2(w_qos_hp2), .r_qos_hp2(r_qos_hp2), .w_qos_hp3(w_qos_hp3), .r_qos_hp3(r_qos_hp3), .wr_ack_ddr_hp2(wr_ack_ddr_hp2), .wr_data_hp2(wr_data_hp2), .wr_addr_hp2(wr_addr_hp2), .wr_bytes_hp2(wr_bytes_hp2), .wr_dv_ddr_hp2(wr_dv_ddr_hp2), .rd_req_ddr_hp2(rd_req_ddr_hp2), .rd_addr_hp2(rd_addr_hp2), .rd_bytes_hp2(rd_bytes_hp2), .rd_data_ddr_hp2(rd_data_ddr_hp2), .rd_dv_ddr_hp2(rd_dv_ddr_hp2), .wr_ack_ddr_hp3(wr_ack_ddr_hp3), .wr_data_hp3(wr_data_hp3), .wr_addr_hp3(wr_addr_hp3), .wr_bytes_hp3(wr_bytes_hp3), .wr_dv_ddr_hp3(wr_dv_ddr_hp3), .rd_req_ddr_hp3(rd_req_ddr_hp3), .rd_addr_hp3(rd_addr_hp3), .rd_bytes_hp3(rd_bytes_hp3), .rd_data_ddr_hp3(rd_data_ddr_hp3), .rd_dv_ddr_hp3(rd_dv_ddr_hp3), .ddr_wr_ack(ddr_wr_ack1), .ddr_wr_dv(ddr_wr_dv1), .ddr_rd_req(ddr_rd_req1), .ddr_rd_dv(ddr_rd_dv1), .ddr_rd_qos(ddr_rd_qos1), .ddr_wr_qos(ddr_wr_qos1), .ddr_wr_addr(ddr_wr_addr1), .ddr_wr_data(ddr_wr_data1), .ddr_wr_bytes(ddr_wr_bytes1), .ddr_rd_addr(ddr_rd_addr1), .ddr_rd_data(ddr_rd_data1), .ddr_rd_bytes(ddr_rd_bytes1) ); /* FOR OCM_WR */ processing_system7_bfm_v2_0_5_arb_wr_4 ocm_wr_hp( .rstn(rstn), .sw_clk(sw_clk), .qos1(w_qos_hp0), .qos2(w_qos_hp1), .qos3(w_qos_hp2), .qos4(w_qos_hp3), .prt_dv1(wr_dv_ocm_hp0), .prt_dv2(wr_dv_ocm_hp1), .prt_dv3(wr_dv_ocm_hp2), .prt_dv4(wr_dv_ocm_hp3), .prt_data1(wr_data_hp0), .prt_data2(wr_data_hp1), .prt_data3(wr_data_hp2), .prt_data4(wr_data_hp3), .prt_addr1(wr_addr_hp0), .prt_addr2(wr_addr_hp1), .prt_addr3(wr_addr_hp2), .prt_addr4(wr_addr_hp3), .prt_bytes1(wr_bytes_hp0), .prt_bytes2(wr_bytes_hp1), .prt_bytes3(wr_bytes_hp2), .prt_bytes4(wr_bytes_hp3), .prt_ack1(wr_ack_ocm_hp0), .prt_ack2(wr_ack_ocm_hp1), .prt_ack3(wr_ack_ocm_hp2), .prt_ack4(wr_ack_ocm_hp3), .prt_qos(ocm_wr_qos), .prt_req(ocm_wr_dv), .prt_data(ocm_wr_data), .prt_addr(ocm_wr_addr), .prt_bytes(ocm_wr_bytes), .prt_ack(ocm_wr_ack) ); /* FOR OCM_RD */ processing_system7_bfm_v2_0_5_arb_rd_4 ocm_rd_hp( .rstn(rstn), .sw_clk(sw_clk), .qos1(r_qos_hp0), .qos2(r_qos_hp1), .qos3(r_qos_hp2), .qos4(r_qos_hp3), .prt_req1(rd_req_ocm_hp0), .prt_req2(rd_req_ocm_hp1), .prt_req3(rd_req_ocm_hp2), .prt_req4(rd_req_ocm_hp3), .prt_data1(rd_data_ocm_hp0), .prt_data2(rd_data_ocm_hp1), .prt_data3(rd_data_ocm_hp2), .prt_data4(rd_data_ocm_hp3), .prt_addr1(rd_addr_hp0), .prt_addr2(rd_addr_hp1), .prt_addr3(rd_addr_hp2), .prt_addr4(rd_addr_hp3), .prt_bytes1(rd_bytes_hp0), .prt_bytes2(rd_bytes_hp1), .prt_bytes3(rd_bytes_hp2), .prt_bytes4(rd_bytes_hp3), .prt_dv1(rd_dv_ocm_hp0), .prt_dv2(rd_dv_ocm_hp1), .prt_dv3(rd_dv_ocm_hp2), .prt_dv4(rd_dv_ocm_hp3), .prt_qos(ocm_rd_qos), .prt_req(ocm_rd_req), .prt_data(ocm_rd_data), .prt_addr(ocm_rd_addr), .prt_bytes(ocm_rd_bytes), .prt_dv(ocm_rd_dv) ); endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_reg_map.v * * Date : 2012-11 * * Description : Controller for Register Map Memory * *****************************************************************************/ /*** WA for CR # 695818 ***/ `ifdef XILINX_SIMULATOR `define XSIM_ISIM `endif `ifdef XILINX_ISIM `define XSIM_ISIM `endif `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_reg_map(); `include "processing_system7_bfm_v2_0_5_local_params.v" /* Register definitions */ `include "processing_system7_bfm_v2_0_5_reg_params.v" parameter mem_size = 32'h2000_0000; ///as the memory is implemented 4 byte wide parameter xsim_mem_size = 32'h1000_0000; ///as the memory is implemented 4 byte wide 256 MB `ifdef XSIM_ISIM reg [data_width-1:0] reg_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem reg [data_width-1:0] reg_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem parameter addr_offset_bits = 26; `else reg /*sparse*/ [data_width-1:0] reg_mem [0:(mem_size/mem_width)-1]; // 512 MB needed for reg space parameter addr_offset_bits = 27; `endif /* preload reset_values from file */ task automatic pre_load_rst_values; input dummy; begin `include "processing_system7_bfm_v2_0_5_reg_init.v" /* This file has list of set_reset_data() calls to set the reset value for each register*/ end endtask /* writes the reset data into the reg memory */ task automatic set_reset_data; input [addr_width-1:0] address; input [data_width-1:0] data; reg [addr_width-1:0] addr; begin addr = address >> 2; `ifdef XSIM_ISIM case(addr[addr_width-1:addr_offset_bits]) 14 : reg_mem0[addr[addr_offset_bits-1:0]] = data; 15 : reg_mem1[addr[addr_offset_bits-1:0]] = data; endcase `else reg_mem[addr[addr_offset_bits-1:0]] = data; `endif end endtask /* writes the data into the reg memory */ task automatic set_data; input [addr_width-1:0] addr; input [data_width-1:0] data; begin `ifdef XSIM_ISIM case(addr[addr_width-1:addr_offset_bits]) 6'h0E : reg_mem0[addr[addr_offset_bits-1:0]] = data; 6'h0F : reg_mem1[addr[addr_offset_bits-1:0]] = data; endcase `else reg_mem[addr[addr_offset_bits-1:0]] = data; `endif end endtask /* get the read data from reg mem */ task automatic get_data; input [addr_width-1:0] addr; output [data_width-1:0] data; begin `ifdef XSIM_ISIM case(addr[addr_width-1:addr_offset_bits]) 6'h0E : data = reg_mem0[addr[addr_offset_bits-1:0]]; 6'h0F : data = reg_mem1[addr[addr_offset_bits-1:0]]; endcase `else data = reg_mem[addr[addr_offset_bits-1:0]]; `endif end endtask /* read chunk of registers */ task read_reg_mem; output[max_burst_bits-1 :0] data; input [addr_width-1:0] start_addr; input [max_burst_bytes_width:0] no_of_bytes; integer i; reg [addr_width-1:0] addr; reg [data_width-1:0] temp_rd_data; reg [max_burst_bits-1:0] temp_data; integer bytes_left; begin addr = start_addr >> shft_addr_bits; bytes_left = no_of_bytes; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : Reading Register Map starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); `endif /* Get first data ... if unaligned address */ get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits- data_width]); if(no_of_bytes < mem_width ) begin repeat(max_burst_bytes - mem_width) temp_data = temp_data >> 8; end else begin bytes_left = bytes_left - mem_width; addr = addr+1; /* Got first data */ while (bytes_left > (mem_width-1) ) begin temp_data = temp_data >> data_width; get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); addr = addr+1; bytes_left = bytes_left - mem_width; end /* Get last valid data in the burst*/ get_data(addr,temp_rd_data); while(bytes_left > 0) begin temp_data = temp_data >> 8; temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; temp_rd_data = temp_rd_data >> 8; bytes_left = bytes_left - 1; end /* align to the brst_byte length */ repeat(max_burst_bytes - no_of_bytes) temp_data = temp_data >> 8; end data = temp_data; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Reading Register Map starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); `endif end endtask initial begin pre_load_rst_values(1); end endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_reg_map.v * * Date : 2012-11 * * Description : Controller for Register Map Memory * *****************************************************************************/ /*** WA for CR # 695818 ***/ `ifdef XILINX_SIMULATOR `define XSIM_ISIM `endif `ifdef XILINX_ISIM `define XSIM_ISIM `endif `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_reg_map(); `include "processing_system7_bfm_v2_0_5_local_params.v" /* Register definitions */ `include "processing_system7_bfm_v2_0_5_reg_params.v" parameter mem_size = 32'h2000_0000; ///as the memory is implemented 4 byte wide parameter xsim_mem_size = 32'h1000_0000; ///as the memory is implemented 4 byte wide 256 MB `ifdef XSIM_ISIM reg [data_width-1:0] reg_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem reg [data_width-1:0] reg_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem parameter addr_offset_bits = 26; `else reg /*sparse*/ [data_width-1:0] reg_mem [0:(mem_size/mem_width)-1]; // 512 MB needed for reg space parameter addr_offset_bits = 27; `endif /* preload reset_values from file */ task automatic pre_load_rst_values; input dummy; begin `include "processing_system7_bfm_v2_0_5_reg_init.v" /* This file has list of set_reset_data() calls to set the reset value for each register*/ end endtask /* writes the reset data into the reg memory */ task automatic set_reset_data; input [addr_width-1:0] address; input [data_width-1:0] data; reg [addr_width-1:0] addr; begin addr = address >> 2; `ifdef XSIM_ISIM case(addr[addr_width-1:addr_offset_bits]) 14 : reg_mem0[addr[addr_offset_bits-1:0]] = data; 15 : reg_mem1[addr[addr_offset_bits-1:0]] = data; endcase `else reg_mem[addr[addr_offset_bits-1:0]] = data; `endif end endtask /* writes the data into the reg memory */ task automatic set_data; input [addr_width-1:0] addr; input [data_width-1:0] data; begin `ifdef XSIM_ISIM case(addr[addr_width-1:addr_offset_bits]) 6'h0E : reg_mem0[addr[addr_offset_bits-1:0]] = data; 6'h0F : reg_mem1[addr[addr_offset_bits-1:0]] = data; endcase `else reg_mem[addr[addr_offset_bits-1:0]] = data; `endif end endtask /* get the read data from reg mem */ task automatic get_data; input [addr_width-1:0] addr; output [data_width-1:0] data; begin `ifdef XSIM_ISIM case(addr[addr_width-1:addr_offset_bits]) 6'h0E : data = reg_mem0[addr[addr_offset_bits-1:0]]; 6'h0F : data = reg_mem1[addr[addr_offset_bits-1:0]]; endcase `else data = reg_mem[addr[addr_offset_bits-1:0]]; `endif end endtask /* read chunk of registers */ task read_reg_mem; output[max_burst_bits-1 :0] data; input [addr_width-1:0] start_addr; input [max_burst_bytes_width:0] no_of_bytes; integer i; reg [addr_width-1:0] addr; reg [data_width-1:0] temp_rd_data; reg [max_burst_bits-1:0] temp_data; integer bytes_left; begin addr = start_addr >> shft_addr_bits; bytes_left = no_of_bytes; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : Reading Register Map starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); `endif /* Get first data ... if unaligned address */ get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits- data_width]); if(no_of_bytes < mem_width ) begin repeat(max_burst_bytes - mem_width) temp_data = temp_data >> 8; end else begin bytes_left = bytes_left - mem_width; addr = addr+1; /* Got first data */ while (bytes_left > (mem_width-1) ) begin temp_data = temp_data >> data_width; get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); addr = addr+1; bytes_left = bytes_left - mem_width; end /* Get last valid data in the burst*/ get_data(addr,temp_rd_data); while(bytes_left > 0) begin temp_data = temp_data >> 8; temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; temp_rd_data = temp_rd_data >> 8; bytes_left = bytes_left - 1; end /* align to the brst_byte length */ repeat(max_burst_bytes - no_of_bytes) temp_data = temp_data >> 8; end data = temp_data; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Reading Register Map starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); `endif end endtask initial begin pre_load_rst_values(1); end endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_processing_system7_bfm.v * * Date : 2012-11 * * Description : Processing_system7_bfm Top (zynq_bfm top) * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_processing_system7_bfm ( CAN0_PHY_TX, CAN0_PHY_RX, CAN1_PHY_TX, CAN1_PHY_RX, ENET0_GMII_TX_EN, ENET0_GMII_TX_ER, ENET0_MDIO_MDC, ENET0_MDIO_O, ENET0_MDIO_T, ENET0_PTP_DELAY_REQ_RX, ENET0_PTP_DELAY_REQ_TX, ENET0_PTP_PDELAY_REQ_RX, ENET0_PTP_PDELAY_REQ_TX, ENET0_PTP_PDELAY_RESP_RX, ENET0_PTP_PDELAY_RESP_TX, ENET0_PTP_SYNC_FRAME_RX, ENET0_PTP_SYNC_FRAME_TX, ENET0_SOF_RX, ENET0_SOF_TX, ENET0_GMII_TXD, ENET0_GMII_COL, ENET0_GMII_CRS, ENET0_EXT_INTIN, ENET0_GMII_RX_CLK, ENET0_GMII_RX_DV, ENET0_GMII_RX_ER, ENET0_GMII_TX_CLK, ENET0_MDIO_I, ENET0_GMII_RXD, ENET1_GMII_TX_EN, ENET1_GMII_TX_ER, ENET1_MDIO_MDC, ENET1_MDIO_O, ENET1_MDIO_T, ENET1_PTP_DELAY_REQ_RX, ENET1_PTP_DELAY_REQ_TX, ENET1_PTP_PDELAY_REQ_RX, ENET1_PTP_PDELAY_REQ_TX, ENET1_PTP_PDELAY_RESP_RX, ENET1_PTP_PDELAY_RESP_TX, ENET1_PTP_SYNC_FRAME_RX, ENET1_PTP_SYNC_FRAME_TX, ENET1_SOF_RX, ENET1_SOF_TX, ENET1_GMII_TXD, ENET1_GMII_COL, ENET1_GMII_CRS, ENET1_EXT_INTIN, ENET1_GMII_RX_CLK, ENET1_GMII_RX_DV, ENET1_GMII_RX_ER, ENET1_GMII_TX_CLK, ENET1_MDIO_I, ENET1_GMII_RXD, GPIO_I, GPIO_O, GPIO_T, I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I, I2C0_SCL_O, I2C0_SCL_T, I2C1_SDA_I, I2C1_SDA_O, I2C1_SDA_T, I2C1_SCL_I, I2C1_SCL_O, I2C1_SCL_T, PJTAG_TCK, PJTAG_TMS, PJTAG_TD_I, PJTAG_TD_T, PJTAG_TD_O, SDIO0_CLK, SDIO0_CLK_FB, SDIO0_CMD_O, SDIO0_CMD_I, SDIO0_CMD_T, SDIO0_DATA_I, SDIO0_DATA_O, SDIO0_DATA_T, SDIO0_LED, SDIO0_CDN, SDIO0_WP, SDIO0_BUSPOW, SDIO0_BUSVOLT, SDIO1_CLK, SDIO1_CLK_FB, SDIO1_CMD_O, SDIO1_CMD_I, SDIO1_CMD_T, SDIO1_DATA_I, SDIO1_DATA_O, SDIO1_DATA_T, SDIO1_LED, SDIO1_CDN, SDIO1_WP, SDIO1_BUSPOW, SDIO1_BUSVOLT, SPI0_SCLK_I, SPI0_SCLK_O, SPI0_SCLK_T, SPI0_MOSI_I, SPI0_MOSI_O, SPI0_MOSI_T, SPI0_MISO_I, SPI0_MISO_O, SPI0_MISO_T, SPI0_SS_I, SPI0_SS_O, SPI0_SS1_O, SPI0_SS2_O, SPI0_SS_T, SPI1_SCLK_I, SPI1_SCLK_O, SPI1_SCLK_T, SPI1_MOSI_I, SPI1_MOSI_O, SPI1_MOSI_T, SPI1_MISO_I, SPI1_MISO_O, SPI1_MISO_T, SPI1_SS_I, SPI1_SS_O, SPI1_SS1_O, SPI1_SS2_O, SPI1_SS_T, UART0_DTRN, UART0_RTSN, UART0_TX, UART0_CTSN, UART0_DCDN, UART0_DSRN, UART0_RIN, UART0_RX, UART1_DTRN, UART1_RTSN, UART1_TX, UART1_CTSN, UART1_DCDN, UART1_DSRN, UART1_RIN, UART1_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, TTC0_CLK0_IN, TTC0_CLK1_IN, TTC0_CLK2_IN, TTC1_WAVE0_OUT, TTC1_WAVE1_OUT, TTC1_WAVE2_OUT, TTC1_CLK0_IN, TTC1_CLK1_IN, TTC1_CLK2_IN, WDT_CLK_IN, WDT_RST_OUT, TRACE_CLK, TRACE_CTL, TRACE_DATA, USB0_PORT_INDCTL, USB1_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB1_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, USB1_VBUS_PWRFAULT, SRAM_INTIN, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, M_AXI_GP1_ARVALID, M_AXI_GP1_AWVALID, M_AXI_GP1_BREADY, M_AXI_GP1_RREADY, M_AXI_GP1_WLAST, M_AXI_GP1_WVALID, M_AXI_GP1_ARID, M_AXI_GP1_AWID, M_AXI_GP1_WID, M_AXI_GP1_ARBURST, M_AXI_GP1_ARLOCK, M_AXI_GP1_ARSIZE, M_AXI_GP1_AWBURST, M_AXI_GP1_AWLOCK, M_AXI_GP1_AWSIZE, M_AXI_GP1_ARPROT, M_AXI_GP1_AWPROT, M_AXI_GP1_ARADDR, M_AXI_GP1_AWADDR, M_AXI_GP1_WDATA, M_AXI_GP1_ARCACHE, M_AXI_GP1_ARLEN, M_AXI_GP1_ARQOS, M_AXI_GP1_AWCACHE, M_AXI_GP1_AWLEN, M_AXI_GP1_AWQOS, M_AXI_GP1_WSTRB, M_AXI_GP1_ACLK, M_AXI_GP1_ARREADY, M_AXI_GP1_AWREADY, M_AXI_GP1_BVALID, M_AXI_GP1_RLAST, M_AXI_GP1_RVALID, M_AXI_GP1_WREADY, M_AXI_GP1_BID, M_AXI_GP1_RID, M_AXI_GP1_BRESP, M_AXI_GP1_RRESP, M_AXI_GP1_RDATA, S_AXI_GP0_ARREADY, S_AXI_GP0_AWREADY, S_AXI_GP0_BVALID, S_AXI_GP0_RLAST, S_AXI_GP0_RVALID, S_AXI_GP0_WREADY, S_AXI_GP0_BRESP, S_AXI_GP0_RRESP, S_AXI_GP0_RDATA, S_AXI_GP0_BID, S_AXI_GP0_RID, S_AXI_GP0_ACLK, S_AXI_GP0_ARVALID, S_AXI_GP0_AWVALID, S_AXI_GP0_BREADY, S_AXI_GP0_RREADY, S_AXI_GP0_WLAST, S_AXI_GP0_WVALID, S_AXI_GP0_ARBURST, S_AXI_GP0_ARLOCK, S_AXI_GP0_ARSIZE, S_AXI_GP0_AWBURST, S_AXI_GP0_AWLOCK, S_AXI_GP0_AWSIZE, S_AXI_GP0_ARPROT, S_AXI_GP0_AWPROT, S_AXI_GP0_ARADDR, S_AXI_GP0_AWADDR, S_AXI_GP0_WDATA, S_AXI_GP0_ARCACHE, S_AXI_GP0_ARLEN, S_AXI_GP0_ARQOS, S_AXI_GP0_AWCACHE, S_AXI_GP0_AWLEN, S_AXI_GP0_AWQOS, S_AXI_GP0_WSTRB, S_AXI_GP0_ARID, S_AXI_GP0_AWID, S_AXI_GP0_WID, S_AXI_GP1_ARREADY, S_AXI_GP1_AWREADY, S_AXI_GP1_BVALID, S_AXI_GP1_RLAST, S_AXI_GP1_RVALID, S_AXI_GP1_WREADY, S_AXI_GP1_BRESP, S_AXI_GP1_RRESP, S_AXI_GP1_RDATA, S_AXI_GP1_BID, S_AXI_GP1_RID, S_AXI_GP1_ACLK, S_AXI_GP1_ARVALID, S_AXI_GP1_AWVALID, S_AXI_GP1_BREADY, S_AXI_GP1_RREADY, S_AXI_GP1_WLAST, S_AXI_GP1_WVALID, S_AXI_GP1_ARBURST, S_AXI_GP1_ARLOCK, S_AXI_GP1_ARSIZE, S_AXI_GP1_AWBURST, S_AXI_GP1_AWLOCK, S_AXI_GP1_AWSIZE, S_AXI_GP1_ARPROT, S_AXI_GP1_AWPROT, S_AXI_GP1_ARADDR, S_AXI_GP1_AWADDR, S_AXI_GP1_WDATA, S_AXI_GP1_ARCACHE, S_AXI_GP1_ARLEN, S_AXI_GP1_ARQOS, S_AXI_GP1_AWCACHE, S_AXI_GP1_AWLEN, S_AXI_GP1_AWQOS, S_AXI_GP1_WSTRB, S_AXI_GP1_ARID, S_AXI_GP1_AWID, S_AXI_GP1_WID, S_AXI_ACP_AWREADY, S_AXI_ACP_ARREADY, S_AXI_ACP_BVALID, S_AXI_ACP_RLAST, S_AXI_ACP_RVALID, S_AXI_ACP_WREADY, S_AXI_ACP_BRESP, S_AXI_ACP_RRESP, S_AXI_ACP_BID, S_AXI_ACP_RID, S_AXI_ACP_RDATA, S_AXI_ACP_ACLK, S_AXI_ACP_ARVALID, S_AXI_ACP_AWVALID, S_AXI_ACP_BREADY, S_AXI_ACP_RREADY, S_AXI_ACP_WLAST, S_AXI_ACP_WVALID, S_AXI_ACP_ARID, S_AXI_ACP_ARPROT, S_AXI_ACP_AWID, S_AXI_ACP_AWPROT, S_AXI_ACP_WID, S_AXI_ACP_ARADDR, S_AXI_ACP_AWADDR, S_AXI_ACP_ARCACHE, S_AXI_ACP_ARLEN, S_AXI_ACP_ARQOS, S_AXI_ACP_AWCACHE, S_AXI_ACP_AWLEN, S_AXI_ACP_AWQOS, S_AXI_ACP_ARBURST, S_AXI_ACP_ARLOCK, S_AXI_ACP_ARSIZE, S_AXI_ACP_AWBURST, S_AXI_ACP_AWLOCK, S_AXI_ACP_AWSIZE, S_AXI_ACP_ARUSER, S_AXI_ACP_AWUSER, S_AXI_ACP_WDATA, S_AXI_ACP_WSTRB, S_AXI_HP0_ARREADY, S_AXI_HP0_AWREADY, S_AXI_HP0_BVALID, S_AXI_HP0_RLAST, S_AXI_HP0_RVALID, S_AXI_HP0_WREADY, S_AXI_HP0_BRESP, S_AXI_HP0_RRESP, S_AXI_HP0_BID, S_AXI_HP0_RID, S_AXI_HP0_RDATA, S_AXI_HP0_RCOUNT, S_AXI_HP0_WCOUNT, S_AXI_HP0_RACOUNT, S_AXI_HP0_WACOUNT, S_AXI_HP0_ACLK, S_AXI_HP0_ARVALID, S_AXI_HP0_AWVALID, S_AXI_HP0_BREADY, S_AXI_HP0_RDISSUECAP1_EN, S_AXI_HP0_RREADY, S_AXI_HP0_WLAST, S_AXI_HP0_WRISSUECAP1_EN, S_AXI_HP0_WVALID, S_AXI_HP0_ARBURST, S_AXI_HP0_ARLOCK, S_AXI_HP0_ARSIZE, S_AXI_HP0_AWBURST, S_AXI_HP0_AWLOCK, S_AXI_HP0_AWSIZE, S_AXI_HP0_ARPROT, S_AXI_HP0_AWPROT, S_AXI_HP0_ARADDR, S_AXI_HP0_AWADDR, S_AXI_HP0_ARCACHE, S_AXI_HP0_ARLEN, S_AXI_HP0_ARQOS, S_AXI_HP0_AWCACHE, S_AXI_HP0_AWLEN, S_AXI_HP0_AWQOS, S_AXI_HP0_ARID, S_AXI_HP0_AWID, S_AXI_HP0_WID, S_AXI_HP0_WDATA, S_AXI_HP0_WSTRB, S_AXI_HP1_ARREADY, S_AXI_HP1_AWREADY, S_AXI_HP1_BVALID, S_AXI_HP1_RLAST, S_AXI_HP1_RVALID, S_AXI_HP1_WREADY, S_AXI_HP1_BRESP, S_AXI_HP1_RRESP, S_AXI_HP1_BID, S_AXI_HP1_RID, S_AXI_HP1_RDATA, S_AXI_HP1_RCOUNT, S_AXI_HP1_WCOUNT, S_AXI_HP1_RACOUNT, S_AXI_HP1_WACOUNT, S_AXI_HP1_ACLK, S_AXI_HP1_ARVALID, S_AXI_HP1_AWVALID, S_AXI_HP1_BREADY, S_AXI_HP1_RDISSUECAP1_EN, S_AXI_HP1_RREADY, S_AXI_HP1_WLAST, S_AXI_HP1_WRISSUECAP1_EN, S_AXI_HP1_WVALID, S_AXI_HP1_ARBURST, S_AXI_HP1_ARLOCK, S_AXI_HP1_ARSIZE, S_AXI_HP1_AWBURST, S_AXI_HP1_AWLOCK, S_AXI_HP1_AWSIZE, S_AXI_HP1_ARPROT, S_AXI_HP1_AWPROT, S_AXI_HP1_ARADDR, S_AXI_HP1_AWADDR, S_AXI_HP1_ARCACHE, S_AXI_HP1_ARLEN, S_AXI_HP1_ARQOS, S_AXI_HP1_AWCACHE, S_AXI_HP1_AWLEN, S_AXI_HP1_AWQOS, S_AXI_HP1_ARID, S_AXI_HP1_AWID, S_AXI_HP1_WID, S_AXI_HP1_WDATA, S_AXI_HP1_WSTRB, S_AXI_HP2_ARREADY, S_AXI_HP2_AWREADY, S_AXI_HP2_BVALID, S_AXI_HP2_RLAST, S_AXI_HP2_RVALID, S_AXI_HP2_WREADY, S_AXI_HP2_BRESP, S_AXI_HP2_RRESP, S_AXI_HP2_BID, S_AXI_HP2_RID, S_AXI_HP2_RDATA, S_AXI_HP2_RCOUNT, S_AXI_HP2_WCOUNT, S_AXI_HP2_RACOUNT, S_AXI_HP2_WACOUNT, S_AXI_HP2_ACLK, S_AXI_HP2_ARVALID, S_AXI_HP2_AWVALID, S_AXI_HP2_BREADY, S_AXI_HP2_RDISSUECAP1_EN, S_AXI_HP2_RREADY, S_AXI_HP2_WLAST, S_AXI_HP2_WRISSUECAP1_EN, S_AXI_HP2_WVALID, S_AXI_HP2_ARBURST, S_AXI_HP2_ARLOCK, S_AXI_HP2_ARSIZE, S_AXI_HP2_AWBURST, S_AXI_HP2_AWLOCK, S_AXI_HP2_AWSIZE, S_AXI_HP2_ARPROT, S_AXI_HP2_AWPROT, S_AXI_HP2_ARADDR, S_AXI_HP2_AWADDR, S_AXI_HP2_ARCACHE, S_AXI_HP2_ARLEN, S_AXI_HP2_ARQOS, S_AXI_HP2_AWCACHE, S_AXI_HP2_AWLEN, S_AXI_HP2_AWQOS, S_AXI_HP2_ARID, S_AXI_HP2_AWID, S_AXI_HP2_WID, S_AXI_HP2_WDATA, S_AXI_HP2_WSTRB, S_AXI_HP3_ARREADY, S_AXI_HP3_AWREADY, S_AXI_HP3_BVALID, S_AXI_HP3_RLAST, S_AXI_HP3_RVALID, S_AXI_HP3_WREADY, S_AXI_HP3_BRESP, S_AXI_HP3_RRESP, S_AXI_HP3_BID, S_AXI_HP3_RID, S_AXI_HP3_RDATA, S_AXI_HP3_RCOUNT, S_AXI_HP3_WCOUNT, S_AXI_HP3_RACOUNT, S_AXI_HP3_WACOUNT, S_AXI_HP3_ACLK, S_AXI_HP3_ARVALID, S_AXI_HP3_AWVALID, S_AXI_HP3_BREADY, S_AXI_HP3_RDISSUECAP1_EN, S_AXI_HP3_RREADY, S_AXI_HP3_WLAST, S_AXI_HP3_WRISSUECAP1_EN, S_AXI_HP3_WVALID, S_AXI_HP3_ARBURST, S_AXI_HP3_ARLOCK, S_AXI_HP3_ARSIZE, S_AXI_HP3_AWBURST, S_AXI_HP3_AWLOCK, S_AXI_HP3_AWSIZE, S_AXI_HP3_ARPROT, S_AXI_HP3_AWPROT, S_AXI_HP3_ARADDR, S_AXI_HP3_AWADDR, S_AXI_HP3_ARCACHE, S_AXI_HP3_ARLEN, S_AXI_HP3_ARQOS, S_AXI_HP3_AWCACHE, S_AXI_HP3_AWLEN, S_AXI_HP3_AWQOS, S_AXI_HP3_ARID, S_AXI_HP3_AWID, S_AXI_HP3_WID, S_AXI_HP3_WDATA, S_AXI_HP3_WSTRB, DMA0_DATYPE, DMA0_DAVALID, DMA0_DRREADY, DMA0_ACLK, DMA0_DAREADY, DMA0_DRLAST, DMA0_DRVALID, DMA0_DRTYPE, DMA1_DATYPE, DMA1_DAVALID, DMA1_DRREADY, DMA1_ACLK, DMA1_DAREADY, DMA1_DRLAST, DMA1_DRVALID, DMA1_DRTYPE, DMA2_DATYPE, DMA2_DAVALID, DMA2_DRREADY, DMA2_ACLK, DMA2_DAREADY, DMA2_DRLAST, DMA2_DRVALID, DMA3_DRVALID, DMA3_DATYPE, DMA3_DAVALID, DMA3_DRREADY, DMA3_ACLK, DMA3_DAREADY, DMA3_DRLAST, DMA2_DRTYPE, DMA3_DRTYPE, FTMD_TRACEIN_DATA, FTMD_TRACEIN_VALID, FTMD_TRACEIN_CLK, FTMD_TRACEIN_ATID, FTMT_F2P_TRIG, FTMT_F2P_TRIGACK, FTMT_F2P_DEBUG, FTMT_P2F_TRIGACK, FTMT_P2F_TRIG, FTMT_P2F_DEBUG, FCLK_CLK3, FCLK_CLK2, FCLK_CLK1, FCLK_CLK0, FCLK_CLKTRIG3_N, FCLK_CLKTRIG2_N, FCLK_CLKTRIG1_N, FCLK_CLKTRIG0_N, FCLK_RESET3_N, FCLK_RESET2_N, FCLK_RESET1_N, FCLK_RESET0_N, FPGA_IDLE_N, DDR_ARB, IRQ_F2P, Core0_nFIQ, Core0_nIRQ, Core1_nFIQ, Core1_nIRQ, EVENT_EVENTO, EVENT_STANDBYWFE, EVENT_STANDBYWFI, EVENT_EVENTI, MIO, DDR_Clk, DDR_Clk_n, DDR_CKE, DDR_CS_n, DDR_RAS_n, DDR_CAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_ODT, DDR_DRSTB, DDR_DQ, DDR_DM, DDR_DQS, DDR_DQS_n, DDR_VRN, DDR_VRP, PS_SRSTB, PS_CLK, PS_PORB, IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC0, IRQ_P2F_DMAC1, IRQ_P2F_DMAC2, IRQ_P2F_DMAC3, IRQ_P2F_DMAC4, IRQ_P2F_DMAC5, IRQ_P2F_DMAC6, IRQ_P2F_DMAC7, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1 ); /* parameters for gen_clk */ parameter C_FCLK_CLK0_FREQ = 50; parameter C_FCLK_CLK1_FREQ = 50; parameter C_FCLK_CLK3_FREQ = 50; parameter C_FCLK_CLK2_FREQ = 50; parameter C_HIGH_OCM_EN = 0; /* parameters for HP ports */ parameter C_USE_S_AXI_HP0 = 0; parameter C_USE_S_AXI_HP1 = 0; parameter C_USE_S_AXI_HP2 = 0; parameter C_USE_S_AXI_HP3 = 0; parameter C_S_AXI_HP0_DATA_WIDTH = 32; parameter C_S_AXI_HP1_DATA_WIDTH = 32; parameter C_S_AXI_HP2_DATA_WIDTH = 32; parameter C_S_AXI_HP3_DATA_WIDTH = 32; parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12; parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12; parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0; parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0; /* Do we need these parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */ parameter C_S_AXI_HP0_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP1_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP2_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP3_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP0_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP1_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP2_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP3_HIGHADDR = 32'hFFFF_FFFF; /* parameters for GP and ACP ports */ parameter C_USE_M_AXI_GP0 = 0; parameter C_USE_M_AXI_GP1 = 0; parameter C_USE_S_AXI_GP0 = 1; parameter C_USE_S_AXI_GP1 = 1; /* Do we need this? parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0; parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0; parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/ parameter C_S_AXI_GP0_BASEADDR = 32'h0000_0000; parameter C_S_AXI_GP1_BASEADDR = 32'h0000_0000; parameter C_S_AXI_GP0_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_GP1_HIGHADDR = 32'hFFFF_FFFF; parameter C_USE_S_AXI_ACP = 1; parameter C_S_AXI_ACP_BASEADDR = 32'h0000_0000; parameter C_S_AXI_ACP_HIGHADDR = 32'hFFFF_FFFF; `include "processing_system7_bfm_v2_0_5_local_params.v" output CAN0_PHY_TX; input CAN0_PHY_RX; output CAN1_PHY_TX; input CAN1_PHY_RX; output ENET0_GMII_TX_EN; output ENET0_GMII_TX_ER; output ENET0_MDIO_MDC; output ENET0_MDIO_O; output ENET0_MDIO_T; output ENET0_PTP_DELAY_REQ_RX; output ENET0_PTP_DELAY_REQ_TX; output ENET0_PTP_PDELAY_REQ_RX; output ENET0_PTP_PDELAY_REQ_TX; output ENET0_PTP_PDELAY_RESP_RX; output ENET0_PTP_PDELAY_RESP_TX; output ENET0_PTP_SYNC_FRAME_RX; output ENET0_PTP_SYNC_FRAME_TX; output ENET0_SOF_RX; output ENET0_SOF_TX; output [7:0] ENET0_GMII_TXD; input ENET0_GMII_COL; input ENET0_GMII_CRS; input ENET0_EXT_INTIN; input ENET0_GMII_RX_CLK; input ENET0_GMII_RX_DV; input ENET0_GMII_RX_ER; input ENET0_GMII_TX_CLK; input ENET0_MDIO_I; input [7:0] ENET0_GMII_RXD; output ENET1_GMII_TX_EN; output ENET1_GMII_TX_ER; output ENET1_MDIO_MDC; output ENET1_MDIO_O; output ENET1_MDIO_T; output ENET1_PTP_DELAY_REQ_RX; output ENET1_PTP_DELAY_REQ_TX; output ENET1_PTP_PDELAY_REQ_RX; output ENET1_PTP_PDELAY_REQ_TX; output ENET1_PTP_PDELAY_RESP_RX; output ENET1_PTP_PDELAY_RESP_TX; output ENET1_PTP_SYNC_FRAME_RX; output ENET1_PTP_SYNC_FRAME_TX; output ENET1_SOF_RX; output ENET1_SOF_TX; output [7:0] ENET1_GMII_TXD; input ENET1_GMII_COL; input ENET1_GMII_CRS; input ENET1_EXT_INTIN; input ENET1_GMII_RX_CLK; input ENET1_GMII_RX_DV; input ENET1_GMII_RX_ER; input ENET1_GMII_TX_CLK; input ENET1_MDIO_I; input [7:0] ENET1_GMII_RXD; input [63:0] GPIO_I; output [63:0] GPIO_O; output [63:0] GPIO_T; input I2C0_SDA_I; output I2C0_SDA_O; output I2C0_SDA_T; input I2C0_SCL_I; output I2C0_SCL_O; output I2C0_SCL_T; input I2C1_SDA_I; output I2C1_SDA_O; output I2C1_SDA_T; input I2C1_SCL_I; output I2C1_SCL_O; output I2C1_SCL_T; input PJTAG_TCK; input PJTAG_TMS; input PJTAG_TD_I; output PJTAG_TD_T; output PJTAG_TD_O; output SDIO0_CLK; input SDIO0_CLK_FB; output SDIO0_CMD_O; input SDIO0_CMD_I; output SDIO0_CMD_T; input [3:0] SDIO0_DATA_I; output [3:0] SDIO0_DATA_O; output [3:0] SDIO0_DATA_T; output SDIO0_LED; input SDIO0_CDN; input SDIO0_WP; output SDIO0_BUSPOW; output [2:0] SDIO0_BUSVOLT; output SDIO1_CLK; input SDIO1_CLK_FB; output SDIO1_CMD_O; input SDIO1_CMD_I; output SDIO1_CMD_T; input [3:0] SDIO1_DATA_I; output [3:0] SDIO1_DATA_O; output [3:0] SDIO1_DATA_T; output SDIO1_LED; input SDIO1_CDN; input SDIO1_WP; output SDIO1_BUSPOW; output [2:0] SDIO1_BUSVOLT; input SPI0_SCLK_I; output SPI0_SCLK_O; output SPI0_SCLK_T; input SPI0_MOSI_I; output SPI0_MOSI_O; output SPI0_MOSI_T; input SPI0_MISO_I; output SPI0_MISO_O; output SPI0_MISO_T; input SPI0_SS_I; output SPI0_SS_O; output SPI0_SS1_O; output SPI0_SS2_O; output SPI0_SS_T; input SPI1_SCLK_I; output SPI1_SCLK_O; output SPI1_SCLK_T; input SPI1_MOSI_I; output SPI1_MOSI_O; output SPI1_MOSI_T; input SPI1_MISO_I; output SPI1_MISO_O; output SPI1_MISO_T; input SPI1_SS_I; output SPI1_SS_O; output SPI1_SS1_O; output SPI1_SS2_O; output SPI1_SS_T; output UART0_DTRN; output UART0_RTSN; output UART0_TX; input UART0_CTSN; input UART0_DCDN; input UART0_DSRN; input UART0_RIN; input UART0_RX; output UART1_DTRN; output UART1_RTSN; output UART1_TX; input UART1_CTSN; input UART1_DCDN; input UART1_DSRN; input UART1_RIN; input UART1_RX; output TTC0_WAVE0_OUT; output TTC0_WAVE1_OUT; output TTC0_WAVE2_OUT; input TTC0_CLK0_IN; input TTC0_CLK1_IN; input TTC0_CLK2_IN; output TTC1_WAVE0_OUT; output TTC1_WAVE1_OUT; output TTC1_WAVE2_OUT; input TTC1_CLK0_IN; input TTC1_CLK1_IN; input TTC1_CLK2_IN; input WDT_CLK_IN; output WDT_RST_OUT; input TRACE_CLK; output TRACE_CTL; output [31:0] TRACE_DATA; output [1:0] USB0_PORT_INDCTL; output [1:0] USB1_PORT_INDCTL; output USB0_VBUS_PWRSELECT; output USB1_VBUS_PWRSELECT; input USB0_VBUS_PWRFAULT; input USB1_VBUS_PWRFAULT; input SRAM_INTIN; output M_AXI_GP0_ARVALID; output M_AXI_GP0_AWVALID; output M_AXI_GP0_BREADY; output M_AXI_GP0_RREADY; output M_AXI_GP0_WLAST; output M_AXI_GP0_WVALID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID; output [1:0] M_AXI_GP0_ARBURST; output [1:0] M_AXI_GP0_ARLOCK; output [2:0] M_AXI_GP0_ARSIZE; output [1:0] M_AXI_GP0_AWBURST; output [1:0] M_AXI_GP0_AWLOCK; output [2:0] M_AXI_GP0_AWSIZE; output [2:0] M_AXI_GP0_ARPROT; output [2:0] M_AXI_GP0_AWPROT; output [31:0] M_AXI_GP0_ARADDR; output [31:0] M_AXI_GP0_AWADDR; output [31:0] M_AXI_GP0_WDATA; output [3:0] M_AXI_GP0_ARCACHE; output [3:0] M_AXI_GP0_ARLEN; output [3:0] M_AXI_GP0_ARQOS; output [3:0] M_AXI_GP0_AWCACHE; output [3:0] M_AXI_GP0_AWLEN; output [3:0] M_AXI_GP0_AWQOS; output [3:0] M_AXI_GP0_WSTRB; input M_AXI_GP0_ACLK; input M_AXI_GP0_ARREADY; input M_AXI_GP0_AWREADY; input M_AXI_GP0_BVALID; input M_AXI_GP0_RLAST; input M_AXI_GP0_RVALID; input M_AXI_GP0_WREADY; input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID; input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID; input [1:0] M_AXI_GP0_BRESP; input [1:0] M_AXI_GP0_RRESP; input [31:0] M_AXI_GP0_RDATA; output M_AXI_GP1_ARVALID; output M_AXI_GP1_AWVALID; output M_AXI_GP1_BREADY; output M_AXI_GP1_RREADY; output M_AXI_GP1_WLAST; output M_AXI_GP1_WVALID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID; output [1:0] M_AXI_GP1_ARBURST; output [1:0] M_AXI_GP1_ARLOCK; output [2:0] M_AXI_GP1_ARSIZE; output [1:0] M_AXI_GP1_AWBURST; output [1:0] M_AXI_GP1_AWLOCK; output [2:0] M_AXI_GP1_AWSIZE; output [2:0] M_AXI_GP1_ARPROT; output [2:0] M_AXI_GP1_AWPROT; output [31:0] M_AXI_GP1_ARADDR; output [31:0] M_AXI_GP1_AWADDR; output [31:0] M_AXI_GP1_WDATA; output [3:0] M_AXI_GP1_ARCACHE; output [3:0] M_AXI_GP1_ARLEN; output [3:0] M_AXI_GP1_ARQOS; output [3:0] M_AXI_GP1_AWCACHE; output [3:0] M_AXI_GP1_AWLEN; output [3:0] M_AXI_GP1_AWQOS; output [3:0] M_AXI_GP1_WSTRB; input M_AXI_GP1_ACLK; input M_AXI_GP1_ARREADY; input M_AXI_GP1_AWREADY; input M_AXI_GP1_BVALID; input M_AXI_GP1_RLAST; input M_AXI_GP1_RVALID; input M_AXI_GP1_WREADY; input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID; input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID; input [1:0] M_AXI_GP1_BRESP; input [1:0] M_AXI_GP1_RRESP; input [31:0] M_AXI_GP1_RDATA; output S_AXI_GP0_ARREADY; output S_AXI_GP0_AWREADY; output S_AXI_GP0_BVALID; output S_AXI_GP0_RLAST; output S_AXI_GP0_RVALID; output S_AXI_GP0_WREADY; output [1:0] S_AXI_GP0_BRESP; output [1:0] S_AXI_GP0_RRESP; output [31:0] S_AXI_GP0_RDATA; output [5:0] S_AXI_GP0_BID; output [5:0] S_AXI_GP0_RID; input S_AXI_GP0_ACLK; input S_AXI_GP0_ARVALID; input S_AXI_GP0_AWVALID; input S_AXI_GP0_BREADY; input S_AXI_GP0_RREADY; input S_AXI_GP0_WLAST; input S_AXI_GP0_WVALID; input [1:0] S_AXI_GP0_ARBURST; input [1:0] S_AXI_GP0_ARLOCK; input [2:0] S_AXI_GP0_ARSIZE; input [1:0] S_AXI_GP0_AWBURST; input [1:0] S_AXI_GP0_AWLOCK; input [2:0] S_AXI_GP0_AWSIZE; input [2:0] S_AXI_GP0_ARPROT; input [2:0] S_AXI_GP0_AWPROT; input [31:0] S_AXI_GP0_ARADDR; input [31:0] S_AXI_GP0_AWADDR; input [31:0] S_AXI_GP0_WDATA; input [3:0] S_AXI_GP0_ARCACHE; input [3:0] S_AXI_GP0_ARLEN; input [3:0] S_AXI_GP0_ARQOS; input [3:0] S_AXI_GP0_AWCACHE; input [3:0] S_AXI_GP0_AWLEN; input [3:0] S_AXI_GP0_AWQOS; input [3:0] S_AXI_GP0_WSTRB; input [5:0] S_AXI_GP0_ARID; input [5:0] S_AXI_GP0_AWID; input [5:0] S_AXI_GP0_WID; output S_AXI_GP1_ARREADY; output S_AXI_GP1_AWREADY; output S_AXI_GP1_BVALID; output S_AXI_GP1_RLAST; output S_AXI_GP1_RVALID; output S_AXI_GP1_WREADY; output [1:0] S_AXI_GP1_BRESP; output [1:0] S_AXI_GP1_RRESP; output [31:0] S_AXI_GP1_RDATA; output [5:0] S_AXI_GP1_BID; output [5:0] S_AXI_GP1_RID; input S_AXI_GP1_ACLK; input S_AXI_GP1_ARVALID; input S_AXI_GP1_AWVALID; input S_AXI_GP1_BREADY; input S_AXI_GP1_RREADY; input S_AXI_GP1_WLAST; input S_AXI_GP1_WVALID; input [1:0] S_AXI_GP1_ARBURST; input [1:0] S_AXI_GP1_ARLOCK; input [2:0] S_AXI_GP1_ARSIZE; input [1:0] S_AXI_GP1_AWBURST; input [1:0] S_AXI_GP1_AWLOCK; input [2:0] S_AXI_GP1_AWSIZE; input [2:0] S_AXI_GP1_ARPROT; input [2:0] S_AXI_GP1_AWPROT; input [31:0] S_AXI_GP1_ARADDR; input [31:0] S_AXI_GP1_AWADDR; input [31:0] S_AXI_GP1_WDATA; input [3:0] S_AXI_GP1_ARCACHE; input [3:0] S_AXI_GP1_ARLEN; input [3:0] S_AXI_GP1_ARQOS; input [3:0] S_AXI_GP1_AWCACHE; input [3:0] S_AXI_GP1_AWLEN; input [3:0] S_AXI_GP1_AWQOS; input [3:0] S_AXI_GP1_WSTRB; input [5:0] S_AXI_GP1_ARID; input [5:0] S_AXI_GP1_AWID; input [5:0] S_AXI_GP1_WID; output S_AXI_ACP_AWREADY; output S_AXI_ACP_ARREADY; output S_AXI_ACP_BVALID; output S_AXI_ACP_RLAST; output S_AXI_ACP_RVALID; output S_AXI_ACP_WREADY; output [1:0] S_AXI_ACP_BRESP; output [1:0] S_AXI_ACP_RRESP; output [2:0] S_AXI_ACP_BID; output [2:0] S_AXI_ACP_RID; output [63:0] S_AXI_ACP_RDATA; input S_AXI_ACP_ACLK; input S_AXI_ACP_ARVALID; input S_AXI_ACP_AWVALID; input S_AXI_ACP_BREADY; input S_AXI_ACP_RREADY; input S_AXI_ACP_WLAST; input S_AXI_ACP_WVALID; input [2:0] S_AXI_ACP_ARID; input [2:0] S_AXI_ACP_ARPROT; input [2:0] S_AXI_ACP_AWID; input [2:0] S_AXI_ACP_AWPROT; input [2:0] S_AXI_ACP_WID; input [31:0] S_AXI_ACP_ARADDR; input [31:0] S_AXI_ACP_AWADDR; input [3:0] S_AXI_ACP_ARCACHE; input [3:0] S_AXI_ACP_ARLEN; input [3:0] S_AXI_ACP_ARQOS; input [3:0] S_AXI_ACP_AWCACHE; input [3:0] S_AXI_ACP_AWLEN; input [3:0] S_AXI_ACP_AWQOS; input [1:0] S_AXI_ACP_ARBURST; input [1:0] S_AXI_ACP_ARLOCK; input [2:0] S_AXI_ACP_ARSIZE; input [1:0] S_AXI_ACP_AWBURST; input [1:0] S_AXI_ACP_AWLOCK; input [2:0] S_AXI_ACP_AWSIZE; input [4:0] S_AXI_ACP_ARUSER; input [4:0] S_AXI_ACP_AWUSER; input [63:0] S_AXI_ACP_WDATA; input [7:0] S_AXI_ACP_WSTRB; output S_AXI_HP0_ARREADY; output S_AXI_HP0_AWREADY; output S_AXI_HP0_BVALID; output S_AXI_HP0_RLAST; output S_AXI_HP0_RVALID; output S_AXI_HP0_WREADY; output [1:0] S_AXI_HP0_BRESP; output [1:0] S_AXI_HP0_RRESP; output [5:0] S_AXI_HP0_BID; output [5:0] S_AXI_HP0_RID; output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA; output [7:0] S_AXI_HP0_RCOUNT; output [7:0] S_AXI_HP0_WCOUNT; output [2:0] S_AXI_HP0_RACOUNT; output [5:0] S_AXI_HP0_WACOUNT; input S_AXI_HP0_ACLK; input S_AXI_HP0_ARVALID; input S_AXI_HP0_AWVALID; input S_AXI_HP0_BREADY; input S_AXI_HP0_RDISSUECAP1_EN; input S_AXI_HP0_RREADY; input S_AXI_HP0_WLAST; input S_AXI_HP0_WRISSUECAP1_EN; input S_AXI_HP0_WVALID; input [1:0] S_AXI_HP0_ARBURST; input [1:0] S_AXI_HP0_ARLOCK; input [2:0] S_AXI_HP0_ARSIZE; input [1:0] S_AXI_HP0_AWBURST; input [1:0] S_AXI_HP0_AWLOCK; input [2:0] S_AXI_HP0_AWSIZE; input [2:0] S_AXI_HP0_ARPROT; input [2:0] S_AXI_HP0_AWPROT; input [31:0] S_AXI_HP0_ARADDR; input [31:0] S_AXI_HP0_AWADDR; input [3:0] S_AXI_HP0_ARCACHE; input [3:0] S_AXI_HP0_ARLEN; input [3:0] S_AXI_HP0_ARQOS; input [3:0] S_AXI_HP0_AWCACHE; input [3:0] S_AXI_HP0_AWLEN; input [3:0] S_AXI_HP0_AWQOS; input [5:0] S_AXI_HP0_ARID; input [5:0] S_AXI_HP0_AWID; input [5:0] S_AXI_HP0_WID; input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA; input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB; output S_AXI_HP1_ARREADY; output S_AXI_HP1_AWREADY; output S_AXI_HP1_BVALID; output S_AXI_HP1_RLAST; output S_AXI_HP1_RVALID; output S_AXI_HP1_WREADY; output [1:0] S_AXI_HP1_BRESP; output [1:0] S_AXI_HP1_RRESP; output [5:0] S_AXI_HP1_BID; output [5:0] S_AXI_HP1_RID; output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA; output [7:0] S_AXI_HP1_RCOUNT; output [7:0] S_AXI_HP1_WCOUNT; output [2:0] S_AXI_HP1_RACOUNT; output [5:0] S_AXI_HP1_WACOUNT; input S_AXI_HP1_ACLK; input S_AXI_HP1_ARVALID; input S_AXI_HP1_AWVALID; input S_AXI_HP1_BREADY; input S_AXI_HP1_RDISSUECAP1_EN; input S_AXI_HP1_RREADY; input S_AXI_HP1_WLAST; input S_AXI_HP1_WRISSUECAP1_EN; input S_AXI_HP1_WVALID; input [1:0] S_AXI_HP1_ARBURST; input [1:0] S_AXI_HP1_ARLOCK; input [2:0] S_AXI_HP1_ARSIZE; input [1:0] S_AXI_HP1_AWBURST; input [1:0] S_AXI_HP1_AWLOCK; input [2:0] S_AXI_HP1_AWSIZE; input [2:0] S_AXI_HP1_ARPROT; input [2:0] S_AXI_HP1_AWPROT; input [31:0] S_AXI_HP1_ARADDR; input [31:0] S_AXI_HP1_AWADDR; input [3:0] S_AXI_HP1_ARCACHE; input [3:0] S_AXI_HP1_ARLEN; input [3:0] S_AXI_HP1_ARQOS; input [3:0] S_AXI_HP1_AWCACHE; input [3:0] S_AXI_HP1_AWLEN; input [3:0] S_AXI_HP1_AWQOS; input [5:0] S_AXI_HP1_ARID; input [5:0] S_AXI_HP1_AWID; input [5:0] S_AXI_HP1_WID; input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA; input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB; output S_AXI_HP2_ARREADY; output S_AXI_HP2_AWREADY; output S_AXI_HP2_BVALID; output S_AXI_HP2_RLAST; output S_AXI_HP2_RVALID; output S_AXI_HP2_WREADY; output [1:0] S_AXI_HP2_BRESP; output [1:0] S_AXI_HP2_RRESP; output [5:0] S_AXI_HP2_BID; output [5:0] S_AXI_HP2_RID; output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA; output [7:0] S_AXI_HP2_RCOUNT; output [7:0] S_AXI_HP2_WCOUNT; output [2:0] S_AXI_HP2_RACOUNT; output [5:0] S_AXI_HP2_WACOUNT; input S_AXI_HP2_ACLK; input S_AXI_HP2_ARVALID; input S_AXI_HP2_AWVALID; input S_AXI_HP2_BREADY; input S_AXI_HP2_RDISSUECAP1_EN; input S_AXI_HP2_RREADY; input S_AXI_HP2_WLAST; input S_AXI_HP2_WRISSUECAP1_EN; input S_AXI_HP2_WVALID; input [1:0] S_AXI_HP2_ARBURST; input [1:0] S_AXI_HP2_ARLOCK; input [2:0] S_AXI_HP2_ARSIZE; input [1:0] S_AXI_HP2_AWBURST; input [1:0] S_AXI_HP2_AWLOCK; input [2:0] S_AXI_HP2_AWSIZE; input [2:0] S_AXI_HP2_ARPROT; input [2:0] S_AXI_HP2_AWPROT; input [31:0] S_AXI_HP2_ARADDR; input [31:0] S_AXI_HP2_AWADDR; input [3:0] S_AXI_HP2_ARCACHE; input [3:0] S_AXI_HP2_ARLEN; input [3:0] S_AXI_HP2_ARQOS; input [3:0] S_AXI_HP2_AWCACHE; input [3:0] S_AXI_HP2_AWLEN; input [3:0] S_AXI_HP2_AWQOS; input [5:0] S_AXI_HP2_ARID; input [5:0] S_AXI_HP2_AWID; input [5:0] S_AXI_HP2_WID; input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA; input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB; output S_AXI_HP3_ARREADY; output S_AXI_HP3_AWREADY; output S_AXI_HP3_BVALID; output S_AXI_HP3_RLAST; output S_AXI_HP3_RVALID; output S_AXI_HP3_WREADY; output [1:0] S_AXI_HP3_BRESP; output [1:0] S_AXI_HP3_RRESP; output [5:0] S_AXI_HP3_BID; output [5:0] S_AXI_HP3_RID; output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA; output [7:0] S_AXI_HP3_RCOUNT; output [7:0] S_AXI_HP3_WCOUNT; output [2:0] S_AXI_HP3_RACOUNT; output [5:0] S_AXI_HP3_WACOUNT; input S_AXI_HP3_ACLK; input S_AXI_HP3_ARVALID; input S_AXI_HP3_AWVALID; input S_AXI_HP3_BREADY; input S_AXI_HP3_RDISSUECAP1_EN; input S_AXI_HP3_RREADY; input S_AXI_HP3_WLAST; input S_AXI_HP3_WRISSUECAP1_EN; input S_AXI_HP3_WVALID; input [1:0] S_AXI_HP3_ARBURST; input [1:0] S_AXI_HP3_ARLOCK; input [2:0] S_AXI_HP3_ARSIZE; input [1:0] S_AXI_HP3_AWBURST; input [1:0] S_AXI_HP3_AWLOCK; input [2:0] S_AXI_HP3_AWSIZE; input [2:0] S_AXI_HP3_ARPROT; input [2:0] S_AXI_HP3_AWPROT; input [31:0] S_AXI_HP3_ARADDR; input [31:0] S_AXI_HP3_AWADDR; input [3:0] S_AXI_HP3_ARCACHE; input [3:0] S_AXI_HP3_ARLEN; input [3:0] S_AXI_HP3_ARQOS; input [3:0] S_AXI_HP3_AWCACHE; input [3:0] S_AXI_HP3_AWLEN; input [3:0] S_AXI_HP3_AWQOS; input [5:0] S_AXI_HP3_ARID; input [5:0] S_AXI_HP3_AWID; input [5:0] S_AXI_HP3_WID; input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA; input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB; output [1:0] DMA0_DATYPE; output DMA0_DAVALID; output DMA0_DRREADY; input DMA0_ACLK; input DMA0_DAREADY; input DMA0_DRLAST; input DMA0_DRVALID; input [1:0] DMA0_DRTYPE; output [1:0] DMA1_DATYPE; output DMA1_DAVALID; output DMA1_DRREADY; input DMA1_ACLK; input DMA1_DAREADY; input DMA1_DRLAST; input DMA1_DRVALID; input [1:0] DMA1_DRTYPE; output [1:0] DMA2_DATYPE; output DMA2_DAVALID; output DMA2_DRREADY; input DMA2_ACLK; input DMA2_DAREADY; input DMA2_DRLAST; input DMA2_DRVALID; input DMA3_DRVALID; output [1:0] DMA3_DATYPE; output DMA3_DAVALID; output DMA3_DRREADY; input DMA3_ACLK; input DMA3_DAREADY; input DMA3_DRLAST; input [1:0] DMA2_DRTYPE; input [1:0] DMA3_DRTYPE; input [31:0] FTMD_TRACEIN_DATA; input FTMD_TRACEIN_VALID; input FTMD_TRACEIN_CLK; input [3:0] FTMD_TRACEIN_ATID; input [3:0] FTMT_F2P_TRIG; output [3:0] FTMT_F2P_TRIGACK; input [31:0] FTMT_F2P_DEBUG; input [3:0] FTMT_P2F_TRIGACK; output [3:0] FTMT_P2F_TRIG; output [31:0] FTMT_P2F_DEBUG; output FCLK_CLK3; output FCLK_CLK2; output FCLK_CLK1; output FCLK_CLK0; input FCLK_CLKTRIG3_N; input FCLK_CLKTRIG2_N; input FCLK_CLKTRIG1_N; input FCLK_CLKTRIG0_N; output FCLK_RESET3_N; output FCLK_RESET2_N; output FCLK_RESET1_N; output FCLK_RESET0_N; input FPGA_IDLE_N; input [3:0] DDR_ARB; input [irq_width-1:0] IRQ_F2P; input Core0_nFIQ; input Core0_nIRQ; input Core1_nFIQ; input Core1_nIRQ; output EVENT_EVENTO; output [1:0] EVENT_STANDBYWFE; output [1:0] EVENT_STANDBYWFI; input EVENT_EVENTI; inout [53:0] MIO; inout DDR_Clk; inout DDR_Clk_n; inout DDR_CKE; inout DDR_CS_n; inout DDR_RAS_n; inout DDR_CAS_n; output DDR_WEB; inout [2:0] DDR_BankAddr; inout [14:0] DDR_Addr; inout DDR_ODT; inout DDR_DRSTB; inout [31:0] DDR_DQ; inout [3:0] DDR_DM; inout [3:0] DDR_DQS; inout [3:0] DDR_DQS_n; inout DDR_VRN; inout DDR_VRP; /* Reset Input & Clock Input */ input PS_SRSTB; input PS_CLK; input PS_PORB; output IRQ_P2F_DMAC_ABORT; output IRQ_P2F_DMAC0; output IRQ_P2F_DMAC1; output IRQ_P2F_DMAC2; output IRQ_P2F_DMAC3; output IRQ_P2F_DMAC4; output IRQ_P2F_DMAC5; output IRQ_P2F_DMAC6; output IRQ_P2F_DMAC7; output IRQ_P2F_SMC; output IRQ_P2F_QSPI; output IRQ_P2F_CTI; output IRQ_P2F_GPIO; output IRQ_P2F_USB0; output IRQ_P2F_ENET0; output IRQ_P2F_ENET_WAKE0; output IRQ_P2F_SDIO0; output IRQ_P2F_I2C0; output IRQ_P2F_SPI0; output IRQ_P2F_UART0; output IRQ_P2F_CAN0; output IRQ_P2F_USB1; output IRQ_P2F_ENET1; output IRQ_P2F_ENET_WAKE1; output IRQ_P2F_SDIO1; output IRQ_P2F_I2C1; output IRQ_P2F_SPI1; output IRQ_P2F_UART1; output IRQ_P2F_CAN1; /* Internal wires/nets used for connectivity */ wire net_rstn; wire net_sw_clk; wire net_ocm_clk; wire net_arbiter_clk; wire net_axi_mgp0_rstn; wire net_axi_mgp1_rstn; wire net_axi_gp0_rstn; wire net_axi_gp1_rstn; wire net_axi_hp0_rstn; wire net_axi_hp1_rstn; wire net_axi_hp2_rstn; wire net_axi_hp3_rstn; wire net_axi_acp_rstn; wire [4:0] net_axi_acp_awuser; wire [4:0] net_axi_acp_aruser; /* Dummy */ assign net_axi_acp_awuser = S_AXI_ACP_AWUSER; assign net_axi_acp_aruser = S_AXI_ACP_ARUSER; /* Global variables */ reg DEBUG_INFO = 1; reg STOP_ON_ERROR = 1; /* local variable acting as semaphore for wait_mem_update and wait_reg_update task */ reg mem_update_key = 1; reg reg_update_key_0 = 1; reg reg_update_key_1 = 1; /* assignments and semantic checks for unused ports */ `include "processing_system7_bfm_v2_0_5_unused_ports.v" /* include api definition */ `include "processing_system7_bfm_v2_0_5_apis.v" /* Reset Generator */ processing_system7_bfm_v2_0_5_gen_reset gen_rst(.por_rst_n(PS_PORB), .sys_rst_n(PS_SRSTB), .rst_out_n(net_rstn), .m_axi_gp0_clk(M_AXI_GP0_ACLK), .m_axi_gp1_clk(M_AXI_GP1_ACLK), .s_axi_gp0_clk(S_AXI_GP0_ACLK), .s_axi_gp1_clk(S_AXI_GP1_ACLK), .s_axi_hp0_clk(S_AXI_HP0_ACLK), .s_axi_hp1_clk(S_AXI_HP1_ACLK), .s_axi_hp2_clk(S_AXI_HP2_ACLK), .s_axi_hp3_clk(S_AXI_HP3_ACLK), .s_axi_acp_clk(S_AXI_ACP_ACLK), .m_axi_gp0_rstn(net_axi_mgp0_rstn), .m_axi_gp1_rstn(net_axi_mgp1_rstn), .s_axi_gp0_rstn(net_axi_gp0_rstn), .s_axi_gp1_rstn(net_axi_gp1_rstn), .s_axi_hp0_rstn(net_axi_hp0_rstn), .s_axi_hp1_rstn(net_axi_hp1_rstn), .s_axi_hp2_rstn(net_axi_hp2_rstn), .s_axi_hp3_rstn(net_axi_hp3_rstn), .s_axi_acp_rstn(net_axi_acp_rstn), .fclk_reset3_n(FCLK_RESET3_N), .fclk_reset2_n(FCLK_RESET2_N), .fclk_reset1_n(FCLK_RESET1_N), .fclk_reset0_n(FCLK_RESET0_N), .fpga_acp_reset_n(), ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP) .fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN), .fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN), .fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN), .fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN), .fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN), .fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN), .fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN), .fpga_hp_s3_reset_n() ////S_AXI_HP3_ARESETN) ); /* Clock Generator */ processing_system7_bfm_v2_0_5_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ) gen_clk(.ps_clk(PS_CLK), .sw_clk(net_sw_clk), .fclk_clk3(FCLK_CLK3), .fclk_clk2(FCLK_CLK2), .fclk_clk1(FCLK_CLK1), .fclk_clk0(FCLK_CLK0) ); wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1; wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1; wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1; wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1; wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1; wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1; wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1; wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1; wire net_rd_req_reg_gp0, net_rd_req_reg_gp1; wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1; wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1; wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1; wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1; wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1; wire net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1; wire net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1; wire net_rd_dv_reg_gp0, net_rd_dv_reg_gp1; wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1; wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3; wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3; wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3; wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3; wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3; wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3; wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3; wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3; wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3; wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3; wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3; wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3; wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3; wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3; wire net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3; wire net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3; wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3; wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp; wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp; wire [max_burst_bits-1:0] net_wr_data_acp; wire [addr_width-1:0] net_wr_addr_acp; wire [max_burst_bytes_width:0] net_wr_bytes_acp; wire [axi_qos_width-1:0] net_wr_qos_acp; wire net_rd_req_ddr_acp, net_rd_req_ocm_acp; wire [addr_width-1:0] net_rd_addr_acp; wire [max_burst_bytes_width:0] net_rd_bytes_acp; wire [max_burst_bits-1:0] net_rd_data_ddr_acp; wire [max_burst_bits-1:0] net_rd_data_ocm_acp; wire net_rd_dv_ddr_acp,net_rd_dv_ocm_acp; wire [axi_qos_width-1:0] net_rd_qos_acp; wire ocm_wr_ack_port0; wire ocm_wr_dv_port0; wire ocm_rd_req_port0; wire ocm_rd_dv_port0; wire [addr_width-1:0] ocm_wr_addr_port0; wire [max_burst_bits-1:0] ocm_wr_data_port0; wire [max_burst_bytes_width:0] ocm_wr_bytes_port0; wire [addr_width-1:0] ocm_rd_addr_port0; wire [max_burst_bits-1:0] ocm_rd_data_port0; wire [max_burst_bytes_width:0] ocm_rd_bytes_port0; wire [axi_qos_width-1:0] ocm_wr_qos_port0; wire [axi_qos_width-1:0] ocm_rd_qos_port0; wire ocm_wr_ack_port1; wire ocm_wr_dv_port1; wire ocm_rd_req_port1; wire ocm_rd_dv_port1; wire [addr_width-1:0] ocm_wr_addr_port1; wire [max_burst_bits-1:0] ocm_wr_data_port1; wire [max_burst_bytes_width:0] ocm_wr_bytes_port1; wire [addr_width-1:0] ocm_rd_addr_port1; wire [max_burst_bits-1:0] ocm_rd_data_port1; wire [max_burst_bytes_width:0] ocm_rd_bytes_port1; wire [axi_qos_width-1:0] ocm_wr_qos_port1; wire [axi_qos_width-1:0] ocm_rd_qos_port1; wire ddr_wr_ack_port0; wire ddr_wr_dv_port0; wire ddr_rd_req_port0; wire ddr_rd_dv_port0; wire[addr_width-1:0] ddr_wr_addr_port0; wire[max_burst_bits-1:0] ddr_wr_data_port0; wire[max_burst_bytes_width:0] ddr_wr_bytes_port0; wire[addr_width-1:0] ddr_rd_addr_port0; wire[max_burst_bits-1:0] ddr_rd_data_port0; wire[max_burst_bytes_width:0] ddr_rd_bytes_port0; wire [axi_qos_width-1:0] ddr_wr_qos_port0; wire [axi_qos_width-1:0] ddr_rd_qos_port0; wire ddr_wr_ack_port1; wire ddr_wr_dv_port1; wire ddr_rd_req_port1; wire ddr_rd_dv_port1; wire[addr_width-1:0] ddr_wr_addr_port1; wire[max_burst_bits-1:0] ddr_wr_data_port1; wire[max_burst_bytes_width:0] ddr_wr_bytes_port1; wire[addr_width-1:0] ddr_rd_addr_port1; wire[max_burst_bits-1:0] ddr_rd_data_port1; wire[max_burst_bytes_width:0] ddr_rd_bytes_port1; wire[axi_qos_width-1:0] ddr_wr_qos_port1; wire[axi_qos_width-1:0] ddr_rd_qos_port1; wire ddr_wr_ack_port2; wire ddr_wr_dv_port2; wire ddr_rd_req_port2; wire ddr_rd_dv_port2; wire[addr_width-1:0] ddr_wr_addr_port2; wire[max_burst_bits-1:0] ddr_wr_data_port2; wire[max_burst_bytes_width:0] ddr_wr_bytes_port2; wire[addr_width-1:0] ddr_rd_addr_port2; wire[max_burst_bits-1:0] ddr_rd_data_port2; wire[max_burst_bytes_width:0] ddr_rd_bytes_port2; wire[axi_qos_width-1:0] ddr_wr_qos_port2; wire[axi_qos_width-1:0] ddr_rd_qos_port2; wire ddr_wr_ack_port3; wire ddr_wr_dv_port3; wire ddr_rd_req_port3; wire ddr_rd_dv_port3; wire[addr_width-1:0] ddr_wr_addr_port3; wire[max_burst_bits-1:0] ddr_wr_data_port3; wire[max_burst_bytes_width:0] ddr_wr_bytes_port3; wire[addr_width-1:0] ddr_rd_addr_port3; wire[max_burst_bits-1:0] ddr_rd_data_port3; wire[max_burst_bytes_width:0] ddr_rd_bytes_port3; wire[axi_qos_width-1:0] ddr_wr_qos_port3; wire[axi_qos_width-1:0] ddr_rd_qos_port3; wire reg_rd_req_port0; wire reg_rd_dv_port0; wire[addr_width-1:0] reg_rd_addr_port0; wire[max_burst_bits-1:0] reg_rd_data_port0; wire[max_burst_bytes_width:0] reg_rd_bytes_port0; wire [axi_qos_width-1:0] reg_rd_qos_port0; wire reg_rd_req_port1; wire reg_rd_dv_port1; wire[addr_width-1:0] reg_rd_addr_port1; wire[max_burst_bits-1:0] reg_rd_data_port1; wire[max_burst_bytes_width:0] reg_rd_bytes_port1; wire [axi_qos_width-1:0] reg_rd_qos_port1; wire [11:0] M_AXI_GP0_AWID_FULL; wire [11:0] M_AXI_GP0_WID_FULL; wire [11:0] M_AXI_GP0_ARID_FULL; wire [11:0] M_AXI_GP0_BID_FULL; wire [11:0] M_AXI_GP0_RID_FULL; wire [11:0] M_AXI_GP1_AWID_FULL; wire [11:0] M_AXI_GP1_WID_FULL; wire [11:0] M_AXI_GP1_ARID_FULL; wire [11:0] M_AXI_GP1_BID_FULL; wire [11:0] M_AXI_GP1_RID_FULL; function [5:0] compress_id; input [11:0] id; begin compress_id = id[5:0]; end endfunction function [11:0] uncompress_id; input [5:0] id; begin uncompress_id = {6'b110000, id[5:0]}; end endfunction assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL; assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL; assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL; assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID; assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID; assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL; assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL; assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL; assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID; assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID; processing_system7_bfm_v2_0_5_interconnect_model icm ( .rstn(net_rstn), .sw_clk(net_sw_clk), .w_qos_gp0(net_wr_qos_gp0), .w_qos_gp1(net_wr_qos_gp1), .w_qos_hp0(net_wr_qos_hp0), .w_qos_hp1(net_wr_qos_hp1), .w_qos_hp2(net_wr_qos_hp2), .w_qos_hp3(net_wr_qos_hp3), .r_qos_gp0(net_rd_qos_gp0), .r_qos_gp1(net_rd_qos_gp1), .r_qos_hp0(net_rd_qos_hp0), .r_qos_hp1(net_rd_qos_hp1), .r_qos_hp2(net_rd_qos_hp2), .r_qos_hp3(net_rd_qos_hp3), /* GP Slave ports access */ .wr_ack_ddr_gp0(net_wr_ack_ddr_gp0), .wr_ack_ocm_gp0(net_wr_ack_ocm_gp0), .wr_data_gp0(net_wr_data_gp0), .wr_addr_gp0(net_wr_addr_gp0), .wr_bytes_gp0(net_wr_bytes_gp0), .wr_dv_ddr_gp0(net_wr_dv_ddr_gp0), .wr_dv_ocm_gp0(net_wr_dv_ocm_gp0), .rd_req_ddr_gp0(net_rd_req_ddr_gp0), .rd_req_ocm_gp0(net_rd_req_ocm_gp0), .rd_req_reg_gp0(net_rd_req_reg_gp0), .rd_addr_gp0(net_rd_addr_gp0), .rd_bytes_gp0(net_rd_bytes_gp0), .rd_data_ddr_gp0(net_rd_data_ddr_gp0), .rd_data_ocm_gp0(net_rd_data_ocm_gp0), .rd_data_reg_gp0(net_rd_data_reg_gp0), .rd_dv_ddr_gp0(net_rd_dv_ddr_gp0), .rd_dv_ocm_gp0(net_rd_dv_ocm_gp0), .rd_dv_reg_gp0(net_rd_dv_reg_gp0), .wr_ack_ddr_gp1(net_wr_ack_ddr_gp1), .wr_ack_ocm_gp1(net_wr_ack_ocm_gp1), .wr_data_gp1(net_wr_data_gp1), .wr_addr_gp1(net_wr_addr_gp1), .wr_bytes_gp1(net_wr_bytes_gp1), .wr_dv_ddr_gp1(net_wr_dv_ddr_gp1), .wr_dv_ocm_gp1(net_wr_dv_ocm_gp1), .rd_req_ddr_gp1(net_rd_req_ddr_gp1), .rd_req_ocm_gp1(net_rd_req_ocm_gp1), .rd_req_reg_gp1(net_rd_req_reg_gp1), .rd_addr_gp1(net_rd_addr_gp1), .rd_bytes_gp1(net_rd_bytes_gp1), .rd_data_ddr_gp1(net_rd_data_ddr_gp1), .rd_data_ocm_gp1(net_rd_data_ocm_gp1), .rd_data_reg_gp1(net_rd_data_reg_gp1), .rd_dv_ddr_gp1(net_rd_dv_ddr_gp1), .rd_dv_ocm_gp1(net_rd_dv_ocm_gp1), .rd_dv_reg_gp1(net_rd_dv_reg_gp1), /* HP Slave ports access */ .wr_ack_ddr_hp0(net_wr_ack_ddr_hp0), .wr_ack_ocm_hp0(net_wr_ack_ocm_hp0), .wr_data_hp0(net_wr_data_hp0), .wr_addr_hp0(net_wr_addr_hp0), .wr_bytes_hp0(net_wr_bytes_hp0), .wr_dv_ddr_hp0(net_wr_dv_ddr_hp0), .wr_dv_ocm_hp0(net_wr_dv_ocm_hp0), .rd_req_ddr_hp0(net_rd_req_ddr_hp0), .rd_req_ocm_hp0(net_rd_req_ocm_hp0), .rd_addr_hp0(net_rd_addr_hp0), .rd_bytes_hp0(net_rd_bytes_hp0), .rd_data_ddr_hp0(net_rd_data_ddr_hp0), .rd_data_ocm_hp0(net_rd_data_ocm_hp0), .rd_dv_ddr_hp0(net_rd_dv_ddr_hp0), .rd_dv_ocm_hp0(net_rd_dv_ocm_hp0), .wr_ack_ddr_hp1(net_wr_ack_ddr_hp1), .wr_ack_ocm_hp1(net_wr_ack_ocm_hp1), .wr_data_hp1(net_wr_data_hp1), .wr_addr_hp1(net_wr_addr_hp1), .wr_bytes_hp1(net_wr_bytes_hp1), .wr_dv_ddr_hp1(net_wr_dv_ddr_hp1), .wr_dv_ocm_hp1(net_wr_dv_ocm_hp1), .rd_req_ddr_hp1(net_rd_req_ddr_hp1), .rd_req_ocm_hp1(net_rd_req_ocm_hp1), .rd_addr_hp1(net_rd_addr_hp1), .rd_bytes_hp1(net_rd_bytes_hp1), .rd_data_ddr_hp1(net_rd_data_ddr_hp1), .rd_data_ocm_hp1(net_rd_data_ocm_hp1), .rd_dv_ocm_hp1(net_rd_dv_ocm_hp1), .rd_dv_ddr_hp1(net_rd_dv_ddr_hp1), .wr_ack_ddr_hp2(net_wr_ack_ddr_hp2), .wr_ack_ocm_hp2(net_wr_ack_ocm_hp2), .wr_data_hp2(net_wr_data_hp2), .wr_addr_hp2(net_wr_addr_hp2), .wr_bytes_hp2(net_wr_bytes_hp2), .wr_dv_ocm_hp2(net_wr_dv_ocm_hp2), .wr_dv_ddr_hp2(net_wr_dv_ddr_hp2), .rd_req_ddr_hp2(net_rd_req_ddr_hp2), .rd_req_ocm_hp2(net_rd_req_ocm_hp2), .rd_addr_hp2(net_rd_addr_hp2), .rd_bytes_hp2(net_rd_bytes_hp2), .rd_data_ddr_hp2(net_rd_data_ddr_hp2), .rd_data_ocm_hp2(net_rd_data_ocm_hp2), .rd_dv_ddr_hp2(net_rd_dv_ddr_hp2), .rd_dv_ocm_hp2(net_rd_dv_ocm_hp2), .wr_ack_ocm_hp3(net_wr_ack_ocm_hp3), .wr_ack_ddr_hp3(net_wr_ack_ddr_hp3), .wr_data_hp3(net_wr_data_hp3), .wr_addr_hp3(net_wr_addr_hp3), .wr_bytes_hp3(net_wr_bytes_hp3), .wr_dv_ddr_hp3(net_wr_dv_ddr_hp3), .wr_dv_ocm_hp3(net_wr_dv_ocm_hp3), .rd_req_ddr_hp3(net_rd_req_ddr_hp3), .rd_req_ocm_hp3(net_rd_req_ocm_hp3), .rd_addr_hp3(net_rd_addr_hp3), .rd_bytes_hp3(net_rd_bytes_hp3), .rd_data_ddr_hp3(net_rd_data_ddr_hp3), .rd_data_ocm_hp3(net_rd_data_ocm_hp3), .rd_dv_ddr_hp3(net_rd_dv_ddr_hp3), .rd_dv_ocm_hp3(net_rd_dv_ocm_hp3), /* Goes to port 1 of DDR */ .ddr_wr_ack_port1(ddr_wr_ack_port1), .ddr_wr_dv_port1(ddr_wr_dv_port1), .ddr_rd_req_port1(ddr_rd_req_port1), .ddr_rd_dv_port1 (ddr_rd_dv_port1), .ddr_wr_addr_port1(ddr_wr_addr_port1), .ddr_wr_data_port1(ddr_wr_data_port1), .ddr_wr_bytes_port1(ddr_wr_bytes_port1), .ddr_rd_addr_port1(ddr_rd_addr_port1), .ddr_rd_data_port1(ddr_rd_data_port1), .ddr_rd_bytes_port1(ddr_rd_bytes_port1), .ddr_wr_qos_port1(ddr_wr_qos_port1), .ddr_rd_qos_port1(ddr_rd_qos_port1), /* Goes to port2 of DDR */ .ddr_wr_ack_port2 (ddr_wr_ack_port2), .ddr_wr_dv_port2 (ddr_wr_dv_port2), .ddr_rd_req_port2 (ddr_rd_req_port2), .ddr_rd_dv_port2 (ddr_rd_dv_port2), .ddr_wr_addr_port2(ddr_wr_addr_port2), .ddr_wr_data_port2(ddr_wr_data_port2), .ddr_wr_bytes_port2(ddr_wr_bytes_port2), .ddr_rd_addr_port2(ddr_rd_addr_port2), .ddr_rd_data_port2(ddr_rd_data_port2), .ddr_rd_bytes_port2(ddr_rd_bytes_port2), .ddr_wr_qos_port2 (ddr_wr_qos_port2), .ddr_rd_qos_port2 (ddr_rd_qos_port2), /* Goes to port3 of DDR */ .ddr_wr_ack_port3 (ddr_wr_ack_port3), .ddr_wr_dv_port3 (ddr_wr_dv_port3), .ddr_rd_req_port3 (ddr_rd_req_port3), .ddr_rd_dv_port3 (ddr_rd_dv_port3), .ddr_wr_addr_port3(ddr_wr_addr_port3), .ddr_wr_data_port3(ddr_wr_data_port3), .ddr_wr_bytes_port3(ddr_wr_bytes_port3), .ddr_rd_addr_port3(ddr_rd_addr_port3), .ddr_rd_data_port3(ddr_rd_data_port3), .ddr_rd_bytes_port3(ddr_rd_bytes_port3), .ddr_wr_qos_port3 (ddr_wr_qos_port3), .ddr_rd_qos_port3 (ddr_rd_qos_port3), /* Goes to port 0 of OCM */ .ocm_wr_ack_port1 (ocm_wr_ack_port1), .ocm_wr_dv_port1 (ocm_wr_dv_port1), .ocm_rd_req_port1 (ocm_rd_req_port1), .ocm_rd_dv_port1 (ocm_rd_dv_port1), .ocm_wr_addr_port1(ocm_wr_addr_port1), .ocm_wr_data_port1(ocm_wr_data_port1), .ocm_wr_bytes_port1(ocm_wr_bytes_port1), .ocm_rd_addr_port1(ocm_rd_addr_port1), .ocm_rd_data_port1(ocm_rd_data_port1), .ocm_rd_bytes_port1(ocm_rd_bytes_port1), .ocm_wr_qos_port1(ocm_wr_qos_port1), .ocm_rd_qos_port1(ocm_rd_qos_port1), /* Goes to port 0 of REG */ .reg_rd_qos_port1 (reg_rd_qos_port1) , .reg_rd_req_port1 (reg_rd_req_port1), .reg_rd_dv_port1 (reg_rd_dv_port1), .reg_rd_addr_port1(reg_rd_addr_port1), .reg_rd_data_port1(reg_rd_data_port1), .reg_rd_bytes_port1(reg_rd_bytes_port1) ); processing_system7_bfm_v2_0_5_ddrc ddrc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of DDR */ .ddr_wr_ack_port0 (ddr_wr_ack_port0), .ddr_wr_dv_port0 (ddr_wr_dv_port0), .ddr_rd_req_port0 (ddr_rd_req_port0), .ddr_rd_dv_port0 (ddr_rd_dv_port0), .ddr_wr_addr_port0(net_wr_addr_acp), .ddr_wr_data_port0(net_wr_data_acp), .ddr_wr_bytes_port0(net_wr_bytes_acp), .ddr_rd_addr_port0(net_rd_addr_acp), .ddr_rd_bytes_port0(net_rd_bytes_acp), .ddr_rd_data_port0(ddr_rd_data_port0), .ddr_wr_qos_port0 (net_wr_qos_acp), .ddr_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of DDR */ .ddr_wr_ack_port1 (ddr_wr_ack_port1), .ddr_wr_dv_port1 (ddr_wr_dv_port1), .ddr_rd_req_port1 (ddr_rd_req_port1), .ddr_rd_dv_port1 (ddr_rd_dv_port1), .ddr_wr_addr_port1(ddr_wr_addr_port1), .ddr_wr_data_port1(ddr_wr_data_port1), .ddr_wr_bytes_port1(ddr_wr_bytes_port1), .ddr_rd_addr_port1(ddr_rd_addr_port1), .ddr_rd_data_port1(ddr_rd_data_port1), .ddr_rd_bytes_port1(ddr_rd_bytes_port1), .ddr_wr_qos_port1 (ddr_wr_qos_port1), .ddr_rd_qos_port1 (ddr_rd_qos_port1), /* Goes to port2 of DDR */ .ddr_wr_ack_port2 (ddr_wr_ack_port2), .ddr_wr_dv_port2 (ddr_wr_dv_port2), .ddr_rd_req_port2 (ddr_rd_req_port2), .ddr_rd_dv_port2 (ddr_rd_dv_port2), .ddr_wr_addr_port2(ddr_wr_addr_port2), .ddr_wr_data_port2(ddr_wr_data_port2), .ddr_wr_bytes_port2(ddr_wr_bytes_port2), .ddr_rd_addr_port2(ddr_rd_addr_port2), .ddr_rd_data_port2(ddr_rd_data_port2), .ddr_rd_bytes_port2(ddr_rd_bytes_port2), .ddr_wr_qos_port2 (ddr_wr_qos_port2), .ddr_rd_qos_port2 (ddr_rd_qos_port2), /* Goes to port3 of DDR */ .ddr_wr_ack_port3 (ddr_wr_ack_port3), .ddr_wr_dv_port3 (ddr_wr_dv_port3), .ddr_rd_req_port3 (ddr_rd_req_port3), .ddr_rd_dv_port3 (ddr_rd_dv_port3), .ddr_wr_addr_port3(ddr_wr_addr_port3), .ddr_wr_data_port3(ddr_wr_data_port3), .ddr_wr_bytes_port3(ddr_wr_bytes_port3), .ddr_rd_addr_port3(ddr_rd_addr_port3), .ddr_rd_data_port3(ddr_rd_data_port3), .ddr_rd_bytes_port3(ddr_rd_bytes_port3), .ddr_wr_qos_port3 (ddr_wr_qos_port3), .ddr_rd_qos_port3 (ddr_rd_qos_port3) ); processing_system7_bfm_v2_0_5_ocmc ocmc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of OCM */ .ocm_wr_ack_port0 (ocm_wr_ack_port0), .ocm_wr_dv_port0 (ocm_wr_dv_port0), .ocm_rd_req_port0 (ocm_rd_req_port0), .ocm_rd_dv_port0 (ocm_rd_dv_port0), .ocm_wr_addr_port0(net_wr_addr_acp), .ocm_wr_data_port0(net_wr_data_acp), .ocm_wr_bytes_port0(net_wr_bytes_acp), .ocm_rd_addr_port0(net_rd_addr_acp), .ocm_rd_bytes_port0(net_rd_bytes_acp), .ocm_rd_data_port0(ocm_rd_data_port0), .ocm_wr_qos_port0 (net_wr_qos_acp), .ocm_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of OCM */ .ocm_wr_ack_port1 (ocm_wr_ack_port1), .ocm_wr_dv_port1 (ocm_wr_dv_port1), .ocm_rd_req_port1 (ocm_rd_req_port1), .ocm_rd_dv_port1 (ocm_rd_dv_port1), .ocm_wr_addr_port1(ocm_wr_addr_port1), .ocm_wr_data_port1(ocm_wr_data_port1), .ocm_wr_bytes_port1(ocm_wr_bytes_port1), .ocm_rd_addr_port1(ocm_rd_addr_port1), .ocm_rd_data_port1(ocm_rd_data_port1), .ocm_rd_bytes_port1(ocm_rd_bytes_port1), .ocm_wr_qos_port1(ocm_wr_qos_port1), .ocm_rd_qos_port1(ocm_rd_qos_port1) ); processing_system7_bfm_v2_0_5_regc regc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of REG */ .reg_rd_req_port0 (reg_rd_req_port0), .reg_rd_dv_port0 (reg_rd_dv_port0), .reg_rd_addr_port0(net_rd_addr_acp), .reg_rd_bytes_port0(net_rd_bytes_acp), .reg_rd_data_port0(reg_rd_data_port0), .reg_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of REG */ .reg_rd_req_port1 (reg_rd_req_port1), .reg_rd_dv_port1 (reg_rd_dv_port1), .reg_rd_addr_port1(reg_rd_addr_port1), .reg_rd_data_port1(reg_rd_data_port1), .reg_rd_bytes_port1(reg_rd_bytes_port1), .reg_rd_qos_port1(reg_rd_qos_port1) ); /* include axi_gp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_gp.v" /* include axi_hp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_hp.v" /* include axi_acp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_acp.v" endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_processing_system7_bfm.v * * Date : 2012-11 * * Description : Processing_system7_bfm Top (zynq_bfm top) * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_processing_system7_bfm ( CAN0_PHY_TX, CAN0_PHY_RX, CAN1_PHY_TX, CAN1_PHY_RX, ENET0_GMII_TX_EN, ENET0_GMII_TX_ER, ENET0_MDIO_MDC, ENET0_MDIO_O, ENET0_MDIO_T, ENET0_PTP_DELAY_REQ_RX, ENET0_PTP_DELAY_REQ_TX, ENET0_PTP_PDELAY_REQ_RX, ENET0_PTP_PDELAY_REQ_TX, ENET0_PTP_PDELAY_RESP_RX, ENET0_PTP_PDELAY_RESP_TX, ENET0_PTP_SYNC_FRAME_RX, ENET0_PTP_SYNC_FRAME_TX, ENET0_SOF_RX, ENET0_SOF_TX, ENET0_GMII_TXD, ENET0_GMII_COL, ENET0_GMII_CRS, ENET0_EXT_INTIN, ENET0_GMII_RX_CLK, ENET0_GMII_RX_DV, ENET0_GMII_RX_ER, ENET0_GMII_TX_CLK, ENET0_MDIO_I, ENET0_GMII_RXD, ENET1_GMII_TX_EN, ENET1_GMII_TX_ER, ENET1_MDIO_MDC, ENET1_MDIO_O, ENET1_MDIO_T, ENET1_PTP_DELAY_REQ_RX, ENET1_PTP_DELAY_REQ_TX, ENET1_PTP_PDELAY_REQ_RX, ENET1_PTP_PDELAY_REQ_TX, ENET1_PTP_PDELAY_RESP_RX, ENET1_PTP_PDELAY_RESP_TX, ENET1_PTP_SYNC_FRAME_RX, ENET1_PTP_SYNC_FRAME_TX, ENET1_SOF_RX, ENET1_SOF_TX, ENET1_GMII_TXD, ENET1_GMII_COL, ENET1_GMII_CRS, ENET1_EXT_INTIN, ENET1_GMII_RX_CLK, ENET1_GMII_RX_DV, ENET1_GMII_RX_ER, ENET1_GMII_TX_CLK, ENET1_MDIO_I, ENET1_GMII_RXD, GPIO_I, GPIO_O, GPIO_T, I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I, I2C0_SCL_O, I2C0_SCL_T, I2C1_SDA_I, I2C1_SDA_O, I2C1_SDA_T, I2C1_SCL_I, I2C1_SCL_O, I2C1_SCL_T, PJTAG_TCK, PJTAG_TMS, PJTAG_TD_I, PJTAG_TD_T, PJTAG_TD_O, SDIO0_CLK, SDIO0_CLK_FB, SDIO0_CMD_O, SDIO0_CMD_I, SDIO0_CMD_T, SDIO0_DATA_I, SDIO0_DATA_O, SDIO0_DATA_T, SDIO0_LED, SDIO0_CDN, SDIO0_WP, SDIO0_BUSPOW, SDIO0_BUSVOLT, SDIO1_CLK, SDIO1_CLK_FB, SDIO1_CMD_O, SDIO1_CMD_I, SDIO1_CMD_T, SDIO1_DATA_I, SDIO1_DATA_O, SDIO1_DATA_T, SDIO1_LED, SDIO1_CDN, SDIO1_WP, SDIO1_BUSPOW, SDIO1_BUSVOLT, SPI0_SCLK_I, SPI0_SCLK_O, SPI0_SCLK_T, SPI0_MOSI_I, SPI0_MOSI_O, SPI0_MOSI_T, SPI0_MISO_I, SPI0_MISO_O, SPI0_MISO_T, SPI0_SS_I, SPI0_SS_O, SPI0_SS1_O, SPI0_SS2_O, SPI0_SS_T, SPI1_SCLK_I, SPI1_SCLK_O, SPI1_SCLK_T, SPI1_MOSI_I, SPI1_MOSI_O, SPI1_MOSI_T, SPI1_MISO_I, SPI1_MISO_O, SPI1_MISO_T, SPI1_SS_I, SPI1_SS_O, SPI1_SS1_O, SPI1_SS2_O, SPI1_SS_T, UART0_DTRN, UART0_RTSN, UART0_TX, UART0_CTSN, UART0_DCDN, UART0_DSRN, UART0_RIN, UART0_RX, UART1_DTRN, UART1_RTSN, UART1_TX, UART1_CTSN, UART1_DCDN, UART1_DSRN, UART1_RIN, UART1_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, TTC0_CLK0_IN, TTC0_CLK1_IN, TTC0_CLK2_IN, TTC1_WAVE0_OUT, TTC1_WAVE1_OUT, TTC1_WAVE2_OUT, TTC1_CLK0_IN, TTC1_CLK1_IN, TTC1_CLK2_IN, WDT_CLK_IN, WDT_RST_OUT, TRACE_CLK, TRACE_CTL, TRACE_DATA, USB0_PORT_INDCTL, USB1_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB1_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, USB1_VBUS_PWRFAULT, SRAM_INTIN, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, M_AXI_GP1_ARVALID, M_AXI_GP1_AWVALID, M_AXI_GP1_BREADY, M_AXI_GP1_RREADY, M_AXI_GP1_WLAST, M_AXI_GP1_WVALID, M_AXI_GP1_ARID, M_AXI_GP1_AWID, M_AXI_GP1_WID, M_AXI_GP1_ARBURST, M_AXI_GP1_ARLOCK, M_AXI_GP1_ARSIZE, M_AXI_GP1_AWBURST, M_AXI_GP1_AWLOCK, M_AXI_GP1_AWSIZE, M_AXI_GP1_ARPROT, M_AXI_GP1_AWPROT, M_AXI_GP1_ARADDR, M_AXI_GP1_AWADDR, M_AXI_GP1_WDATA, M_AXI_GP1_ARCACHE, M_AXI_GP1_ARLEN, M_AXI_GP1_ARQOS, M_AXI_GP1_AWCACHE, M_AXI_GP1_AWLEN, M_AXI_GP1_AWQOS, M_AXI_GP1_WSTRB, M_AXI_GP1_ACLK, M_AXI_GP1_ARREADY, M_AXI_GP1_AWREADY, M_AXI_GP1_BVALID, M_AXI_GP1_RLAST, M_AXI_GP1_RVALID, M_AXI_GP1_WREADY, M_AXI_GP1_BID, M_AXI_GP1_RID, M_AXI_GP1_BRESP, M_AXI_GP1_RRESP, M_AXI_GP1_RDATA, S_AXI_GP0_ARREADY, S_AXI_GP0_AWREADY, S_AXI_GP0_BVALID, S_AXI_GP0_RLAST, S_AXI_GP0_RVALID, S_AXI_GP0_WREADY, S_AXI_GP0_BRESP, S_AXI_GP0_RRESP, S_AXI_GP0_RDATA, S_AXI_GP0_BID, S_AXI_GP0_RID, S_AXI_GP0_ACLK, S_AXI_GP0_ARVALID, S_AXI_GP0_AWVALID, S_AXI_GP0_BREADY, S_AXI_GP0_RREADY, S_AXI_GP0_WLAST, S_AXI_GP0_WVALID, S_AXI_GP0_ARBURST, S_AXI_GP0_ARLOCK, S_AXI_GP0_ARSIZE, S_AXI_GP0_AWBURST, S_AXI_GP0_AWLOCK, S_AXI_GP0_AWSIZE, S_AXI_GP0_ARPROT, S_AXI_GP0_AWPROT, S_AXI_GP0_ARADDR, S_AXI_GP0_AWADDR, S_AXI_GP0_WDATA, S_AXI_GP0_ARCACHE, S_AXI_GP0_ARLEN, S_AXI_GP0_ARQOS, S_AXI_GP0_AWCACHE, S_AXI_GP0_AWLEN, S_AXI_GP0_AWQOS, S_AXI_GP0_WSTRB, S_AXI_GP0_ARID, S_AXI_GP0_AWID, S_AXI_GP0_WID, S_AXI_GP1_ARREADY, S_AXI_GP1_AWREADY, S_AXI_GP1_BVALID, S_AXI_GP1_RLAST, S_AXI_GP1_RVALID, S_AXI_GP1_WREADY, S_AXI_GP1_BRESP, S_AXI_GP1_RRESP, S_AXI_GP1_RDATA, S_AXI_GP1_BID, S_AXI_GP1_RID, S_AXI_GP1_ACLK, S_AXI_GP1_ARVALID, S_AXI_GP1_AWVALID, S_AXI_GP1_BREADY, S_AXI_GP1_RREADY, S_AXI_GP1_WLAST, S_AXI_GP1_WVALID, S_AXI_GP1_ARBURST, S_AXI_GP1_ARLOCK, S_AXI_GP1_ARSIZE, S_AXI_GP1_AWBURST, S_AXI_GP1_AWLOCK, S_AXI_GP1_AWSIZE, S_AXI_GP1_ARPROT, S_AXI_GP1_AWPROT, S_AXI_GP1_ARADDR, S_AXI_GP1_AWADDR, S_AXI_GP1_WDATA, S_AXI_GP1_ARCACHE, S_AXI_GP1_ARLEN, S_AXI_GP1_ARQOS, S_AXI_GP1_AWCACHE, S_AXI_GP1_AWLEN, S_AXI_GP1_AWQOS, S_AXI_GP1_WSTRB, S_AXI_GP1_ARID, S_AXI_GP1_AWID, S_AXI_GP1_WID, S_AXI_ACP_AWREADY, S_AXI_ACP_ARREADY, S_AXI_ACP_BVALID, S_AXI_ACP_RLAST, S_AXI_ACP_RVALID, S_AXI_ACP_WREADY, S_AXI_ACP_BRESP, S_AXI_ACP_RRESP, S_AXI_ACP_BID, S_AXI_ACP_RID, S_AXI_ACP_RDATA, S_AXI_ACP_ACLK, S_AXI_ACP_ARVALID, S_AXI_ACP_AWVALID, S_AXI_ACP_BREADY, S_AXI_ACP_RREADY, S_AXI_ACP_WLAST, S_AXI_ACP_WVALID, S_AXI_ACP_ARID, S_AXI_ACP_ARPROT, S_AXI_ACP_AWID, S_AXI_ACP_AWPROT, S_AXI_ACP_WID, S_AXI_ACP_ARADDR, S_AXI_ACP_AWADDR, S_AXI_ACP_ARCACHE, S_AXI_ACP_ARLEN, S_AXI_ACP_ARQOS, S_AXI_ACP_AWCACHE, S_AXI_ACP_AWLEN, S_AXI_ACP_AWQOS, S_AXI_ACP_ARBURST, S_AXI_ACP_ARLOCK, S_AXI_ACP_ARSIZE, S_AXI_ACP_AWBURST, S_AXI_ACP_AWLOCK, S_AXI_ACP_AWSIZE, S_AXI_ACP_ARUSER, S_AXI_ACP_AWUSER, S_AXI_ACP_WDATA, S_AXI_ACP_WSTRB, S_AXI_HP0_ARREADY, S_AXI_HP0_AWREADY, S_AXI_HP0_BVALID, S_AXI_HP0_RLAST, S_AXI_HP0_RVALID, S_AXI_HP0_WREADY, S_AXI_HP0_BRESP, S_AXI_HP0_RRESP, S_AXI_HP0_BID, S_AXI_HP0_RID, S_AXI_HP0_RDATA, S_AXI_HP0_RCOUNT, S_AXI_HP0_WCOUNT, S_AXI_HP0_RACOUNT, S_AXI_HP0_WACOUNT, S_AXI_HP0_ACLK, S_AXI_HP0_ARVALID, S_AXI_HP0_AWVALID, S_AXI_HP0_BREADY, S_AXI_HP0_RDISSUECAP1_EN, S_AXI_HP0_RREADY, S_AXI_HP0_WLAST, S_AXI_HP0_WRISSUECAP1_EN, S_AXI_HP0_WVALID, S_AXI_HP0_ARBURST, S_AXI_HP0_ARLOCK, S_AXI_HP0_ARSIZE, S_AXI_HP0_AWBURST, S_AXI_HP0_AWLOCK, S_AXI_HP0_AWSIZE, S_AXI_HP0_ARPROT, S_AXI_HP0_AWPROT, S_AXI_HP0_ARADDR, S_AXI_HP0_AWADDR, S_AXI_HP0_ARCACHE, S_AXI_HP0_ARLEN, S_AXI_HP0_ARQOS, S_AXI_HP0_AWCACHE, S_AXI_HP0_AWLEN, S_AXI_HP0_AWQOS, S_AXI_HP0_ARID, S_AXI_HP0_AWID, S_AXI_HP0_WID, S_AXI_HP0_WDATA, S_AXI_HP0_WSTRB, S_AXI_HP1_ARREADY, S_AXI_HP1_AWREADY, S_AXI_HP1_BVALID, S_AXI_HP1_RLAST, S_AXI_HP1_RVALID, S_AXI_HP1_WREADY, S_AXI_HP1_BRESP, S_AXI_HP1_RRESP, S_AXI_HP1_BID, S_AXI_HP1_RID, S_AXI_HP1_RDATA, S_AXI_HP1_RCOUNT, S_AXI_HP1_WCOUNT, S_AXI_HP1_RACOUNT, S_AXI_HP1_WACOUNT, S_AXI_HP1_ACLK, S_AXI_HP1_ARVALID, S_AXI_HP1_AWVALID, S_AXI_HP1_BREADY, S_AXI_HP1_RDISSUECAP1_EN, S_AXI_HP1_RREADY, S_AXI_HP1_WLAST, S_AXI_HP1_WRISSUECAP1_EN, S_AXI_HP1_WVALID, S_AXI_HP1_ARBURST, S_AXI_HP1_ARLOCK, S_AXI_HP1_ARSIZE, S_AXI_HP1_AWBURST, S_AXI_HP1_AWLOCK, S_AXI_HP1_AWSIZE, S_AXI_HP1_ARPROT, S_AXI_HP1_AWPROT, S_AXI_HP1_ARADDR, S_AXI_HP1_AWADDR, S_AXI_HP1_ARCACHE, S_AXI_HP1_ARLEN, S_AXI_HP1_ARQOS, S_AXI_HP1_AWCACHE, S_AXI_HP1_AWLEN, S_AXI_HP1_AWQOS, S_AXI_HP1_ARID, S_AXI_HP1_AWID, S_AXI_HP1_WID, S_AXI_HP1_WDATA, S_AXI_HP1_WSTRB, S_AXI_HP2_ARREADY, S_AXI_HP2_AWREADY, S_AXI_HP2_BVALID, S_AXI_HP2_RLAST, S_AXI_HP2_RVALID, S_AXI_HP2_WREADY, S_AXI_HP2_BRESP, S_AXI_HP2_RRESP, S_AXI_HP2_BID, S_AXI_HP2_RID, S_AXI_HP2_RDATA, S_AXI_HP2_RCOUNT, S_AXI_HP2_WCOUNT, S_AXI_HP2_RACOUNT, S_AXI_HP2_WACOUNT, S_AXI_HP2_ACLK, S_AXI_HP2_ARVALID, S_AXI_HP2_AWVALID, S_AXI_HP2_BREADY, S_AXI_HP2_RDISSUECAP1_EN, S_AXI_HP2_RREADY, S_AXI_HP2_WLAST, S_AXI_HP2_WRISSUECAP1_EN, S_AXI_HP2_WVALID, S_AXI_HP2_ARBURST, S_AXI_HP2_ARLOCK, S_AXI_HP2_ARSIZE, S_AXI_HP2_AWBURST, S_AXI_HP2_AWLOCK, S_AXI_HP2_AWSIZE, S_AXI_HP2_ARPROT, S_AXI_HP2_AWPROT, S_AXI_HP2_ARADDR, S_AXI_HP2_AWADDR, S_AXI_HP2_ARCACHE, S_AXI_HP2_ARLEN, S_AXI_HP2_ARQOS, S_AXI_HP2_AWCACHE, S_AXI_HP2_AWLEN, S_AXI_HP2_AWQOS, S_AXI_HP2_ARID, S_AXI_HP2_AWID, S_AXI_HP2_WID, S_AXI_HP2_WDATA, S_AXI_HP2_WSTRB, S_AXI_HP3_ARREADY, S_AXI_HP3_AWREADY, S_AXI_HP3_BVALID, S_AXI_HP3_RLAST, S_AXI_HP3_RVALID, S_AXI_HP3_WREADY, S_AXI_HP3_BRESP, S_AXI_HP3_RRESP, S_AXI_HP3_BID, S_AXI_HP3_RID, S_AXI_HP3_RDATA, S_AXI_HP3_RCOUNT, S_AXI_HP3_WCOUNT, S_AXI_HP3_RACOUNT, S_AXI_HP3_WACOUNT, S_AXI_HP3_ACLK, S_AXI_HP3_ARVALID, S_AXI_HP3_AWVALID, S_AXI_HP3_BREADY, S_AXI_HP3_RDISSUECAP1_EN, S_AXI_HP3_RREADY, S_AXI_HP3_WLAST, S_AXI_HP3_WRISSUECAP1_EN, S_AXI_HP3_WVALID, S_AXI_HP3_ARBURST, S_AXI_HP3_ARLOCK, S_AXI_HP3_ARSIZE, S_AXI_HP3_AWBURST, S_AXI_HP3_AWLOCK, S_AXI_HP3_AWSIZE, S_AXI_HP3_ARPROT, S_AXI_HP3_AWPROT, S_AXI_HP3_ARADDR, S_AXI_HP3_AWADDR, S_AXI_HP3_ARCACHE, S_AXI_HP3_ARLEN, S_AXI_HP3_ARQOS, S_AXI_HP3_AWCACHE, S_AXI_HP3_AWLEN, S_AXI_HP3_AWQOS, S_AXI_HP3_ARID, S_AXI_HP3_AWID, S_AXI_HP3_WID, S_AXI_HP3_WDATA, S_AXI_HP3_WSTRB, DMA0_DATYPE, DMA0_DAVALID, DMA0_DRREADY, DMA0_ACLK, DMA0_DAREADY, DMA0_DRLAST, DMA0_DRVALID, DMA0_DRTYPE, DMA1_DATYPE, DMA1_DAVALID, DMA1_DRREADY, DMA1_ACLK, DMA1_DAREADY, DMA1_DRLAST, DMA1_DRVALID, DMA1_DRTYPE, DMA2_DATYPE, DMA2_DAVALID, DMA2_DRREADY, DMA2_ACLK, DMA2_DAREADY, DMA2_DRLAST, DMA2_DRVALID, DMA3_DRVALID, DMA3_DATYPE, DMA3_DAVALID, DMA3_DRREADY, DMA3_ACLK, DMA3_DAREADY, DMA3_DRLAST, DMA2_DRTYPE, DMA3_DRTYPE, FTMD_TRACEIN_DATA, FTMD_TRACEIN_VALID, FTMD_TRACEIN_CLK, FTMD_TRACEIN_ATID, FTMT_F2P_TRIG, FTMT_F2P_TRIGACK, FTMT_F2P_DEBUG, FTMT_P2F_TRIGACK, FTMT_P2F_TRIG, FTMT_P2F_DEBUG, FCLK_CLK3, FCLK_CLK2, FCLK_CLK1, FCLK_CLK0, FCLK_CLKTRIG3_N, FCLK_CLKTRIG2_N, FCLK_CLKTRIG1_N, FCLK_CLKTRIG0_N, FCLK_RESET3_N, FCLK_RESET2_N, FCLK_RESET1_N, FCLK_RESET0_N, FPGA_IDLE_N, DDR_ARB, IRQ_F2P, Core0_nFIQ, Core0_nIRQ, Core1_nFIQ, Core1_nIRQ, EVENT_EVENTO, EVENT_STANDBYWFE, EVENT_STANDBYWFI, EVENT_EVENTI, MIO, DDR_Clk, DDR_Clk_n, DDR_CKE, DDR_CS_n, DDR_RAS_n, DDR_CAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_ODT, DDR_DRSTB, DDR_DQ, DDR_DM, DDR_DQS, DDR_DQS_n, DDR_VRN, DDR_VRP, PS_SRSTB, PS_CLK, PS_PORB, IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC0, IRQ_P2F_DMAC1, IRQ_P2F_DMAC2, IRQ_P2F_DMAC3, IRQ_P2F_DMAC4, IRQ_P2F_DMAC5, IRQ_P2F_DMAC6, IRQ_P2F_DMAC7, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1 ); /* parameters for gen_clk */ parameter C_FCLK_CLK0_FREQ = 50; parameter C_FCLK_CLK1_FREQ = 50; parameter C_FCLK_CLK3_FREQ = 50; parameter C_FCLK_CLK2_FREQ = 50; parameter C_HIGH_OCM_EN = 0; /* parameters for HP ports */ parameter C_USE_S_AXI_HP0 = 0; parameter C_USE_S_AXI_HP1 = 0; parameter C_USE_S_AXI_HP2 = 0; parameter C_USE_S_AXI_HP3 = 0; parameter C_S_AXI_HP0_DATA_WIDTH = 32; parameter C_S_AXI_HP1_DATA_WIDTH = 32; parameter C_S_AXI_HP2_DATA_WIDTH = 32; parameter C_S_AXI_HP3_DATA_WIDTH = 32; parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12; parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12; parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0; parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0; /* Do we need these parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */ parameter C_S_AXI_HP0_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP1_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP2_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP3_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP0_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP1_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP2_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP3_HIGHADDR = 32'hFFFF_FFFF; /* parameters for GP and ACP ports */ parameter C_USE_M_AXI_GP0 = 0; parameter C_USE_M_AXI_GP1 = 0; parameter C_USE_S_AXI_GP0 = 1; parameter C_USE_S_AXI_GP1 = 1; /* Do we need this? parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0; parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0; parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/ parameter C_S_AXI_GP0_BASEADDR = 32'h0000_0000; parameter C_S_AXI_GP1_BASEADDR = 32'h0000_0000; parameter C_S_AXI_GP0_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_GP1_HIGHADDR = 32'hFFFF_FFFF; parameter C_USE_S_AXI_ACP = 1; parameter C_S_AXI_ACP_BASEADDR = 32'h0000_0000; parameter C_S_AXI_ACP_HIGHADDR = 32'hFFFF_FFFF; `include "processing_system7_bfm_v2_0_5_local_params.v" output CAN0_PHY_TX; input CAN0_PHY_RX; output CAN1_PHY_TX; input CAN1_PHY_RX; output ENET0_GMII_TX_EN; output ENET0_GMII_TX_ER; output ENET0_MDIO_MDC; output ENET0_MDIO_O; output ENET0_MDIO_T; output ENET0_PTP_DELAY_REQ_RX; output ENET0_PTP_DELAY_REQ_TX; output ENET0_PTP_PDELAY_REQ_RX; output ENET0_PTP_PDELAY_REQ_TX; output ENET0_PTP_PDELAY_RESP_RX; output ENET0_PTP_PDELAY_RESP_TX; output ENET0_PTP_SYNC_FRAME_RX; output ENET0_PTP_SYNC_FRAME_TX; output ENET0_SOF_RX; output ENET0_SOF_TX; output [7:0] ENET0_GMII_TXD; input ENET0_GMII_COL; input ENET0_GMII_CRS; input ENET0_EXT_INTIN; input ENET0_GMII_RX_CLK; input ENET0_GMII_RX_DV; input ENET0_GMII_RX_ER; input ENET0_GMII_TX_CLK; input ENET0_MDIO_I; input [7:0] ENET0_GMII_RXD; output ENET1_GMII_TX_EN; output ENET1_GMII_TX_ER; output ENET1_MDIO_MDC; output ENET1_MDIO_O; output ENET1_MDIO_T; output ENET1_PTP_DELAY_REQ_RX; output ENET1_PTP_DELAY_REQ_TX; output ENET1_PTP_PDELAY_REQ_RX; output ENET1_PTP_PDELAY_REQ_TX; output ENET1_PTP_PDELAY_RESP_RX; output ENET1_PTP_PDELAY_RESP_TX; output ENET1_PTP_SYNC_FRAME_RX; output ENET1_PTP_SYNC_FRAME_TX; output ENET1_SOF_RX; output ENET1_SOF_TX; output [7:0] ENET1_GMII_TXD; input ENET1_GMII_COL; input ENET1_GMII_CRS; input ENET1_EXT_INTIN; input ENET1_GMII_RX_CLK; input ENET1_GMII_RX_DV; input ENET1_GMII_RX_ER; input ENET1_GMII_TX_CLK; input ENET1_MDIO_I; input [7:0] ENET1_GMII_RXD; input [63:0] GPIO_I; output [63:0] GPIO_O; output [63:0] GPIO_T; input I2C0_SDA_I; output I2C0_SDA_O; output I2C0_SDA_T; input I2C0_SCL_I; output I2C0_SCL_O; output I2C0_SCL_T; input I2C1_SDA_I; output I2C1_SDA_O; output I2C1_SDA_T; input I2C1_SCL_I; output I2C1_SCL_O; output I2C1_SCL_T; input PJTAG_TCK; input PJTAG_TMS; input PJTAG_TD_I; output PJTAG_TD_T; output PJTAG_TD_O; output SDIO0_CLK; input SDIO0_CLK_FB; output SDIO0_CMD_O; input SDIO0_CMD_I; output SDIO0_CMD_T; input [3:0] SDIO0_DATA_I; output [3:0] SDIO0_DATA_O; output [3:0] SDIO0_DATA_T; output SDIO0_LED; input SDIO0_CDN; input SDIO0_WP; output SDIO0_BUSPOW; output [2:0] SDIO0_BUSVOLT; output SDIO1_CLK; input SDIO1_CLK_FB; output SDIO1_CMD_O; input SDIO1_CMD_I; output SDIO1_CMD_T; input [3:0] SDIO1_DATA_I; output [3:0] SDIO1_DATA_O; output [3:0] SDIO1_DATA_T; output SDIO1_LED; input SDIO1_CDN; input SDIO1_WP; output SDIO1_BUSPOW; output [2:0] SDIO1_BUSVOLT; input SPI0_SCLK_I; output SPI0_SCLK_O; output SPI0_SCLK_T; input SPI0_MOSI_I; output SPI0_MOSI_O; output SPI0_MOSI_T; input SPI0_MISO_I; output SPI0_MISO_O; output SPI0_MISO_T; input SPI0_SS_I; output SPI0_SS_O; output SPI0_SS1_O; output SPI0_SS2_O; output SPI0_SS_T; input SPI1_SCLK_I; output SPI1_SCLK_O; output SPI1_SCLK_T; input SPI1_MOSI_I; output SPI1_MOSI_O; output SPI1_MOSI_T; input SPI1_MISO_I; output SPI1_MISO_O; output SPI1_MISO_T; input SPI1_SS_I; output SPI1_SS_O; output SPI1_SS1_O; output SPI1_SS2_O; output SPI1_SS_T; output UART0_DTRN; output UART0_RTSN; output UART0_TX; input UART0_CTSN; input UART0_DCDN; input UART0_DSRN; input UART0_RIN; input UART0_RX; output UART1_DTRN; output UART1_RTSN; output UART1_TX; input UART1_CTSN; input UART1_DCDN; input UART1_DSRN; input UART1_RIN; input UART1_RX; output TTC0_WAVE0_OUT; output TTC0_WAVE1_OUT; output TTC0_WAVE2_OUT; input TTC0_CLK0_IN; input TTC0_CLK1_IN; input TTC0_CLK2_IN; output TTC1_WAVE0_OUT; output TTC1_WAVE1_OUT; output TTC1_WAVE2_OUT; input TTC1_CLK0_IN; input TTC1_CLK1_IN; input TTC1_CLK2_IN; input WDT_CLK_IN; output WDT_RST_OUT; input TRACE_CLK; output TRACE_CTL; output [31:0] TRACE_DATA; output [1:0] USB0_PORT_INDCTL; output [1:0] USB1_PORT_INDCTL; output USB0_VBUS_PWRSELECT; output USB1_VBUS_PWRSELECT; input USB0_VBUS_PWRFAULT; input USB1_VBUS_PWRFAULT; input SRAM_INTIN; output M_AXI_GP0_ARVALID; output M_AXI_GP0_AWVALID; output M_AXI_GP0_BREADY; output M_AXI_GP0_RREADY; output M_AXI_GP0_WLAST; output M_AXI_GP0_WVALID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID; output [1:0] M_AXI_GP0_ARBURST; output [1:0] M_AXI_GP0_ARLOCK; output [2:0] M_AXI_GP0_ARSIZE; output [1:0] M_AXI_GP0_AWBURST; output [1:0] M_AXI_GP0_AWLOCK; output [2:0] M_AXI_GP0_AWSIZE; output [2:0] M_AXI_GP0_ARPROT; output [2:0] M_AXI_GP0_AWPROT; output [31:0] M_AXI_GP0_ARADDR; output [31:0] M_AXI_GP0_AWADDR; output [31:0] M_AXI_GP0_WDATA; output [3:0] M_AXI_GP0_ARCACHE; output [3:0] M_AXI_GP0_ARLEN; output [3:0] M_AXI_GP0_ARQOS; output [3:0] M_AXI_GP0_AWCACHE; output [3:0] M_AXI_GP0_AWLEN; output [3:0] M_AXI_GP0_AWQOS; output [3:0] M_AXI_GP0_WSTRB; input M_AXI_GP0_ACLK; input M_AXI_GP0_ARREADY; input M_AXI_GP0_AWREADY; input M_AXI_GP0_BVALID; input M_AXI_GP0_RLAST; input M_AXI_GP0_RVALID; input M_AXI_GP0_WREADY; input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID; input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID; input [1:0] M_AXI_GP0_BRESP; input [1:0] M_AXI_GP0_RRESP; input [31:0] M_AXI_GP0_RDATA; output M_AXI_GP1_ARVALID; output M_AXI_GP1_AWVALID; output M_AXI_GP1_BREADY; output M_AXI_GP1_RREADY; output M_AXI_GP1_WLAST; output M_AXI_GP1_WVALID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID; output [1:0] M_AXI_GP1_ARBURST; output [1:0] M_AXI_GP1_ARLOCK; output [2:0] M_AXI_GP1_ARSIZE; output [1:0] M_AXI_GP1_AWBURST; output [1:0] M_AXI_GP1_AWLOCK; output [2:0] M_AXI_GP1_AWSIZE; output [2:0] M_AXI_GP1_ARPROT; output [2:0] M_AXI_GP1_AWPROT; output [31:0] M_AXI_GP1_ARADDR; output [31:0] M_AXI_GP1_AWADDR; output [31:0] M_AXI_GP1_WDATA; output [3:0] M_AXI_GP1_ARCACHE; output [3:0] M_AXI_GP1_ARLEN; output [3:0] M_AXI_GP1_ARQOS; output [3:0] M_AXI_GP1_AWCACHE; output [3:0] M_AXI_GP1_AWLEN; output [3:0] M_AXI_GP1_AWQOS; output [3:0] M_AXI_GP1_WSTRB; input M_AXI_GP1_ACLK; input M_AXI_GP1_ARREADY; input M_AXI_GP1_AWREADY; input M_AXI_GP1_BVALID; input M_AXI_GP1_RLAST; input M_AXI_GP1_RVALID; input M_AXI_GP1_WREADY; input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID; input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID; input [1:0] M_AXI_GP1_BRESP; input [1:0] M_AXI_GP1_RRESP; input [31:0] M_AXI_GP1_RDATA; output S_AXI_GP0_ARREADY; output S_AXI_GP0_AWREADY; output S_AXI_GP0_BVALID; output S_AXI_GP0_RLAST; output S_AXI_GP0_RVALID; output S_AXI_GP0_WREADY; output [1:0] S_AXI_GP0_BRESP; output [1:0] S_AXI_GP0_RRESP; output [31:0] S_AXI_GP0_RDATA; output [5:0] S_AXI_GP0_BID; output [5:0] S_AXI_GP0_RID; input S_AXI_GP0_ACLK; input S_AXI_GP0_ARVALID; input S_AXI_GP0_AWVALID; input S_AXI_GP0_BREADY; input S_AXI_GP0_RREADY; input S_AXI_GP0_WLAST; input S_AXI_GP0_WVALID; input [1:0] S_AXI_GP0_ARBURST; input [1:0] S_AXI_GP0_ARLOCK; input [2:0] S_AXI_GP0_ARSIZE; input [1:0] S_AXI_GP0_AWBURST; input [1:0] S_AXI_GP0_AWLOCK; input [2:0] S_AXI_GP0_AWSIZE; input [2:0] S_AXI_GP0_ARPROT; input [2:0] S_AXI_GP0_AWPROT; input [31:0] S_AXI_GP0_ARADDR; input [31:0] S_AXI_GP0_AWADDR; input [31:0] S_AXI_GP0_WDATA; input [3:0] S_AXI_GP0_ARCACHE; input [3:0] S_AXI_GP0_ARLEN; input [3:0] S_AXI_GP0_ARQOS; input [3:0] S_AXI_GP0_AWCACHE; input [3:0] S_AXI_GP0_AWLEN; input [3:0] S_AXI_GP0_AWQOS; input [3:0] S_AXI_GP0_WSTRB; input [5:0] S_AXI_GP0_ARID; input [5:0] S_AXI_GP0_AWID; input [5:0] S_AXI_GP0_WID; output S_AXI_GP1_ARREADY; output S_AXI_GP1_AWREADY; output S_AXI_GP1_BVALID; output S_AXI_GP1_RLAST; output S_AXI_GP1_RVALID; output S_AXI_GP1_WREADY; output [1:0] S_AXI_GP1_BRESP; output [1:0] S_AXI_GP1_RRESP; output [31:0] S_AXI_GP1_RDATA; output [5:0] S_AXI_GP1_BID; output [5:0] S_AXI_GP1_RID; input S_AXI_GP1_ACLK; input S_AXI_GP1_ARVALID; input S_AXI_GP1_AWVALID; input S_AXI_GP1_BREADY; input S_AXI_GP1_RREADY; input S_AXI_GP1_WLAST; input S_AXI_GP1_WVALID; input [1:0] S_AXI_GP1_ARBURST; input [1:0] S_AXI_GP1_ARLOCK; input [2:0] S_AXI_GP1_ARSIZE; input [1:0] S_AXI_GP1_AWBURST; input [1:0] S_AXI_GP1_AWLOCK; input [2:0] S_AXI_GP1_AWSIZE; input [2:0] S_AXI_GP1_ARPROT; input [2:0] S_AXI_GP1_AWPROT; input [31:0] S_AXI_GP1_ARADDR; input [31:0] S_AXI_GP1_AWADDR; input [31:0] S_AXI_GP1_WDATA; input [3:0] S_AXI_GP1_ARCACHE; input [3:0] S_AXI_GP1_ARLEN; input [3:0] S_AXI_GP1_ARQOS; input [3:0] S_AXI_GP1_AWCACHE; input [3:0] S_AXI_GP1_AWLEN; input [3:0] S_AXI_GP1_AWQOS; input [3:0] S_AXI_GP1_WSTRB; input [5:0] S_AXI_GP1_ARID; input [5:0] S_AXI_GP1_AWID; input [5:0] S_AXI_GP1_WID; output S_AXI_ACP_AWREADY; output S_AXI_ACP_ARREADY; output S_AXI_ACP_BVALID; output S_AXI_ACP_RLAST; output S_AXI_ACP_RVALID; output S_AXI_ACP_WREADY; output [1:0] S_AXI_ACP_BRESP; output [1:0] S_AXI_ACP_RRESP; output [2:0] S_AXI_ACP_BID; output [2:0] S_AXI_ACP_RID; output [63:0] S_AXI_ACP_RDATA; input S_AXI_ACP_ACLK; input S_AXI_ACP_ARVALID; input S_AXI_ACP_AWVALID; input S_AXI_ACP_BREADY; input S_AXI_ACP_RREADY; input S_AXI_ACP_WLAST; input S_AXI_ACP_WVALID; input [2:0] S_AXI_ACP_ARID; input [2:0] S_AXI_ACP_ARPROT; input [2:0] S_AXI_ACP_AWID; input [2:0] S_AXI_ACP_AWPROT; input [2:0] S_AXI_ACP_WID; input [31:0] S_AXI_ACP_ARADDR; input [31:0] S_AXI_ACP_AWADDR; input [3:0] S_AXI_ACP_ARCACHE; input [3:0] S_AXI_ACP_ARLEN; input [3:0] S_AXI_ACP_ARQOS; input [3:0] S_AXI_ACP_AWCACHE; input [3:0] S_AXI_ACP_AWLEN; input [3:0] S_AXI_ACP_AWQOS; input [1:0] S_AXI_ACP_ARBURST; input [1:0] S_AXI_ACP_ARLOCK; input [2:0] S_AXI_ACP_ARSIZE; input [1:0] S_AXI_ACP_AWBURST; input [1:0] S_AXI_ACP_AWLOCK; input [2:0] S_AXI_ACP_AWSIZE; input [4:0] S_AXI_ACP_ARUSER; input [4:0] S_AXI_ACP_AWUSER; input [63:0] S_AXI_ACP_WDATA; input [7:0] S_AXI_ACP_WSTRB; output S_AXI_HP0_ARREADY; output S_AXI_HP0_AWREADY; output S_AXI_HP0_BVALID; output S_AXI_HP0_RLAST; output S_AXI_HP0_RVALID; output S_AXI_HP0_WREADY; output [1:0] S_AXI_HP0_BRESP; output [1:0] S_AXI_HP0_RRESP; output [5:0] S_AXI_HP0_BID; output [5:0] S_AXI_HP0_RID; output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA; output [7:0] S_AXI_HP0_RCOUNT; output [7:0] S_AXI_HP0_WCOUNT; output [2:0] S_AXI_HP0_RACOUNT; output [5:0] S_AXI_HP0_WACOUNT; input S_AXI_HP0_ACLK; input S_AXI_HP0_ARVALID; input S_AXI_HP0_AWVALID; input S_AXI_HP0_BREADY; input S_AXI_HP0_RDISSUECAP1_EN; input S_AXI_HP0_RREADY; input S_AXI_HP0_WLAST; input S_AXI_HP0_WRISSUECAP1_EN; input S_AXI_HP0_WVALID; input [1:0] S_AXI_HP0_ARBURST; input [1:0] S_AXI_HP0_ARLOCK; input [2:0] S_AXI_HP0_ARSIZE; input [1:0] S_AXI_HP0_AWBURST; input [1:0] S_AXI_HP0_AWLOCK; input [2:0] S_AXI_HP0_AWSIZE; input [2:0] S_AXI_HP0_ARPROT; input [2:0] S_AXI_HP0_AWPROT; input [31:0] S_AXI_HP0_ARADDR; input [31:0] S_AXI_HP0_AWADDR; input [3:0] S_AXI_HP0_ARCACHE; input [3:0] S_AXI_HP0_ARLEN; input [3:0] S_AXI_HP0_ARQOS; input [3:0] S_AXI_HP0_AWCACHE; input [3:0] S_AXI_HP0_AWLEN; input [3:0] S_AXI_HP0_AWQOS; input [5:0] S_AXI_HP0_ARID; input [5:0] S_AXI_HP0_AWID; input [5:0] S_AXI_HP0_WID; input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA; input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB; output S_AXI_HP1_ARREADY; output S_AXI_HP1_AWREADY; output S_AXI_HP1_BVALID; output S_AXI_HP1_RLAST; output S_AXI_HP1_RVALID; output S_AXI_HP1_WREADY; output [1:0] S_AXI_HP1_BRESP; output [1:0] S_AXI_HP1_RRESP; output [5:0] S_AXI_HP1_BID; output [5:0] S_AXI_HP1_RID; output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA; output [7:0] S_AXI_HP1_RCOUNT; output [7:0] S_AXI_HP1_WCOUNT; output [2:0] S_AXI_HP1_RACOUNT; output [5:0] S_AXI_HP1_WACOUNT; input S_AXI_HP1_ACLK; input S_AXI_HP1_ARVALID; input S_AXI_HP1_AWVALID; input S_AXI_HP1_BREADY; input S_AXI_HP1_RDISSUECAP1_EN; input S_AXI_HP1_RREADY; input S_AXI_HP1_WLAST; input S_AXI_HP1_WRISSUECAP1_EN; input S_AXI_HP1_WVALID; input [1:0] S_AXI_HP1_ARBURST; input [1:0] S_AXI_HP1_ARLOCK; input [2:0] S_AXI_HP1_ARSIZE; input [1:0] S_AXI_HP1_AWBURST; input [1:0] S_AXI_HP1_AWLOCK; input [2:0] S_AXI_HP1_AWSIZE; input [2:0] S_AXI_HP1_ARPROT; input [2:0] S_AXI_HP1_AWPROT; input [31:0] S_AXI_HP1_ARADDR; input [31:0] S_AXI_HP1_AWADDR; input [3:0] S_AXI_HP1_ARCACHE; input [3:0] S_AXI_HP1_ARLEN; input [3:0] S_AXI_HP1_ARQOS; input [3:0] S_AXI_HP1_AWCACHE; input [3:0] S_AXI_HP1_AWLEN; input [3:0] S_AXI_HP1_AWQOS; input [5:0] S_AXI_HP1_ARID; input [5:0] S_AXI_HP1_AWID; input [5:0] S_AXI_HP1_WID; input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA; input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB; output S_AXI_HP2_ARREADY; output S_AXI_HP2_AWREADY; output S_AXI_HP2_BVALID; output S_AXI_HP2_RLAST; output S_AXI_HP2_RVALID; output S_AXI_HP2_WREADY; output [1:0] S_AXI_HP2_BRESP; output [1:0] S_AXI_HP2_RRESP; output [5:0] S_AXI_HP2_BID; output [5:0] S_AXI_HP2_RID; output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA; output [7:0] S_AXI_HP2_RCOUNT; output [7:0] S_AXI_HP2_WCOUNT; output [2:0] S_AXI_HP2_RACOUNT; output [5:0] S_AXI_HP2_WACOUNT; input S_AXI_HP2_ACLK; input S_AXI_HP2_ARVALID; input S_AXI_HP2_AWVALID; input S_AXI_HP2_BREADY; input S_AXI_HP2_RDISSUECAP1_EN; input S_AXI_HP2_RREADY; input S_AXI_HP2_WLAST; input S_AXI_HP2_WRISSUECAP1_EN; input S_AXI_HP2_WVALID; input [1:0] S_AXI_HP2_ARBURST; input [1:0] S_AXI_HP2_ARLOCK; input [2:0] S_AXI_HP2_ARSIZE; input [1:0] S_AXI_HP2_AWBURST; input [1:0] S_AXI_HP2_AWLOCK; input [2:0] S_AXI_HP2_AWSIZE; input [2:0] S_AXI_HP2_ARPROT; input [2:0] S_AXI_HP2_AWPROT; input [31:0] S_AXI_HP2_ARADDR; input [31:0] S_AXI_HP2_AWADDR; input [3:0] S_AXI_HP2_ARCACHE; input [3:0] S_AXI_HP2_ARLEN; input [3:0] S_AXI_HP2_ARQOS; input [3:0] S_AXI_HP2_AWCACHE; input [3:0] S_AXI_HP2_AWLEN; input [3:0] S_AXI_HP2_AWQOS; input [5:0] S_AXI_HP2_ARID; input [5:0] S_AXI_HP2_AWID; input [5:0] S_AXI_HP2_WID; input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA; input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB; output S_AXI_HP3_ARREADY; output S_AXI_HP3_AWREADY; output S_AXI_HP3_BVALID; output S_AXI_HP3_RLAST; output S_AXI_HP3_RVALID; output S_AXI_HP3_WREADY; output [1:0] S_AXI_HP3_BRESP; output [1:0] S_AXI_HP3_RRESP; output [5:0] S_AXI_HP3_BID; output [5:0] S_AXI_HP3_RID; output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA; output [7:0] S_AXI_HP3_RCOUNT; output [7:0] S_AXI_HP3_WCOUNT; output [2:0] S_AXI_HP3_RACOUNT; output [5:0] S_AXI_HP3_WACOUNT; input S_AXI_HP3_ACLK; input S_AXI_HP3_ARVALID; input S_AXI_HP3_AWVALID; input S_AXI_HP3_BREADY; input S_AXI_HP3_RDISSUECAP1_EN; input S_AXI_HP3_RREADY; input S_AXI_HP3_WLAST; input S_AXI_HP3_WRISSUECAP1_EN; input S_AXI_HP3_WVALID; input [1:0] S_AXI_HP3_ARBURST; input [1:0] S_AXI_HP3_ARLOCK; input [2:0] S_AXI_HP3_ARSIZE; input [1:0] S_AXI_HP3_AWBURST; input [1:0] S_AXI_HP3_AWLOCK; input [2:0] S_AXI_HP3_AWSIZE; input [2:0] S_AXI_HP3_ARPROT; input [2:0] S_AXI_HP3_AWPROT; input [31:0] S_AXI_HP3_ARADDR; input [31:0] S_AXI_HP3_AWADDR; input [3:0] S_AXI_HP3_ARCACHE; input [3:0] S_AXI_HP3_ARLEN; input [3:0] S_AXI_HP3_ARQOS; input [3:0] S_AXI_HP3_AWCACHE; input [3:0] S_AXI_HP3_AWLEN; input [3:0] S_AXI_HP3_AWQOS; input [5:0] S_AXI_HP3_ARID; input [5:0] S_AXI_HP3_AWID; input [5:0] S_AXI_HP3_WID; input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA; input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB; output [1:0] DMA0_DATYPE; output DMA0_DAVALID; output DMA0_DRREADY; input DMA0_ACLK; input DMA0_DAREADY; input DMA0_DRLAST; input DMA0_DRVALID; input [1:0] DMA0_DRTYPE; output [1:0] DMA1_DATYPE; output DMA1_DAVALID; output DMA1_DRREADY; input DMA1_ACLK; input DMA1_DAREADY; input DMA1_DRLAST; input DMA1_DRVALID; input [1:0] DMA1_DRTYPE; output [1:0] DMA2_DATYPE; output DMA2_DAVALID; output DMA2_DRREADY; input DMA2_ACLK; input DMA2_DAREADY; input DMA2_DRLAST; input DMA2_DRVALID; input DMA3_DRVALID; output [1:0] DMA3_DATYPE; output DMA3_DAVALID; output DMA3_DRREADY; input DMA3_ACLK; input DMA3_DAREADY; input DMA3_DRLAST; input [1:0] DMA2_DRTYPE; input [1:0] DMA3_DRTYPE; input [31:0] FTMD_TRACEIN_DATA; input FTMD_TRACEIN_VALID; input FTMD_TRACEIN_CLK; input [3:0] FTMD_TRACEIN_ATID; input [3:0] FTMT_F2P_TRIG; output [3:0] FTMT_F2P_TRIGACK; input [31:0] FTMT_F2P_DEBUG; input [3:0] FTMT_P2F_TRIGACK; output [3:0] FTMT_P2F_TRIG; output [31:0] FTMT_P2F_DEBUG; output FCLK_CLK3; output FCLK_CLK2; output FCLK_CLK1; output FCLK_CLK0; input FCLK_CLKTRIG3_N; input FCLK_CLKTRIG2_N; input FCLK_CLKTRIG1_N; input FCLK_CLKTRIG0_N; output FCLK_RESET3_N; output FCLK_RESET2_N; output FCLK_RESET1_N; output FCLK_RESET0_N; input FPGA_IDLE_N; input [3:0] DDR_ARB; input [irq_width-1:0] IRQ_F2P; input Core0_nFIQ; input Core0_nIRQ; input Core1_nFIQ; input Core1_nIRQ; output EVENT_EVENTO; output [1:0] EVENT_STANDBYWFE; output [1:0] EVENT_STANDBYWFI; input EVENT_EVENTI; inout [53:0] MIO; inout DDR_Clk; inout DDR_Clk_n; inout DDR_CKE; inout DDR_CS_n; inout DDR_RAS_n; inout DDR_CAS_n; output DDR_WEB; inout [2:0] DDR_BankAddr; inout [14:0] DDR_Addr; inout DDR_ODT; inout DDR_DRSTB; inout [31:0] DDR_DQ; inout [3:0] DDR_DM; inout [3:0] DDR_DQS; inout [3:0] DDR_DQS_n; inout DDR_VRN; inout DDR_VRP; /* Reset Input & Clock Input */ input PS_SRSTB; input PS_CLK; input PS_PORB; output IRQ_P2F_DMAC_ABORT; output IRQ_P2F_DMAC0; output IRQ_P2F_DMAC1; output IRQ_P2F_DMAC2; output IRQ_P2F_DMAC3; output IRQ_P2F_DMAC4; output IRQ_P2F_DMAC5; output IRQ_P2F_DMAC6; output IRQ_P2F_DMAC7; output IRQ_P2F_SMC; output IRQ_P2F_QSPI; output IRQ_P2F_CTI; output IRQ_P2F_GPIO; output IRQ_P2F_USB0; output IRQ_P2F_ENET0; output IRQ_P2F_ENET_WAKE0; output IRQ_P2F_SDIO0; output IRQ_P2F_I2C0; output IRQ_P2F_SPI0; output IRQ_P2F_UART0; output IRQ_P2F_CAN0; output IRQ_P2F_USB1; output IRQ_P2F_ENET1; output IRQ_P2F_ENET_WAKE1; output IRQ_P2F_SDIO1; output IRQ_P2F_I2C1; output IRQ_P2F_SPI1; output IRQ_P2F_UART1; output IRQ_P2F_CAN1; /* Internal wires/nets used for connectivity */ wire net_rstn; wire net_sw_clk; wire net_ocm_clk; wire net_arbiter_clk; wire net_axi_mgp0_rstn; wire net_axi_mgp1_rstn; wire net_axi_gp0_rstn; wire net_axi_gp1_rstn; wire net_axi_hp0_rstn; wire net_axi_hp1_rstn; wire net_axi_hp2_rstn; wire net_axi_hp3_rstn; wire net_axi_acp_rstn; wire [4:0] net_axi_acp_awuser; wire [4:0] net_axi_acp_aruser; /* Dummy */ assign net_axi_acp_awuser = S_AXI_ACP_AWUSER; assign net_axi_acp_aruser = S_AXI_ACP_ARUSER; /* Global variables */ reg DEBUG_INFO = 1; reg STOP_ON_ERROR = 1; /* local variable acting as semaphore for wait_mem_update and wait_reg_update task */ reg mem_update_key = 1; reg reg_update_key_0 = 1; reg reg_update_key_1 = 1; /* assignments and semantic checks for unused ports */ `include "processing_system7_bfm_v2_0_5_unused_ports.v" /* include api definition */ `include "processing_system7_bfm_v2_0_5_apis.v" /* Reset Generator */ processing_system7_bfm_v2_0_5_gen_reset gen_rst(.por_rst_n(PS_PORB), .sys_rst_n(PS_SRSTB), .rst_out_n(net_rstn), .m_axi_gp0_clk(M_AXI_GP0_ACLK), .m_axi_gp1_clk(M_AXI_GP1_ACLK), .s_axi_gp0_clk(S_AXI_GP0_ACLK), .s_axi_gp1_clk(S_AXI_GP1_ACLK), .s_axi_hp0_clk(S_AXI_HP0_ACLK), .s_axi_hp1_clk(S_AXI_HP1_ACLK), .s_axi_hp2_clk(S_AXI_HP2_ACLK), .s_axi_hp3_clk(S_AXI_HP3_ACLK), .s_axi_acp_clk(S_AXI_ACP_ACLK), .m_axi_gp0_rstn(net_axi_mgp0_rstn), .m_axi_gp1_rstn(net_axi_mgp1_rstn), .s_axi_gp0_rstn(net_axi_gp0_rstn), .s_axi_gp1_rstn(net_axi_gp1_rstn), .s_axi_hp0_rstn(net_axi_hp0_rstn), .s_axi_hp1_rstn(net_axi_hp1_rstn), .s_axi_hp2_rstn(net_axi_hp2_rstn), .s_axi_hp3_rstn(net_axi_hp3_rstn), .s_axi_acp_rstn(net_axi_acp_rstn), .fclk_reset3_n(FCLK_RESET3_N), .fclk_reset2_n(FCLK_RESET2_N), .fclk_reset1_n(FCLK_RESET1_N), .fclk_reset0_n(FCLK_RESET0_N), .fpga_acp_reset_n(), ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP) .fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN), .fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN), .fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN), .fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN), .fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN), .fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN), .fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN), .fpga_hp_s3_reset_n() ////S_AXI_HP3_ARESETN) ); /* Clock Generator */ processing_system7_bfm_v2_0_5_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ) gen_clk(.ps_clk(PS_CLK), .sw_clk(net_sw_clk), .fclk_clk3(FCLK_CLK3), .fclk_clk2(FCLK_CLK2), .fclk_clk1(FCLK_CLK1), .fclk_clk0(FCLK_CLK0) ); wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1; wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1; wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1; wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1; wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1; wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1; wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1; wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1; wire net_rd_req_reg_gp0, net_rd_req_reg_gp1; wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1; wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1; wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1; wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1; wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1; wire net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1; wire net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1; wire net_rd_dv_reg_gp0, net_rd_dv_reg_gp1; wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1; wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3; wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3; wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3; wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3; wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3; wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3; wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3; wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3; wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3; wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3; wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3; wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3; wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3; wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3; wire net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3; wire net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3; wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3; wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp; wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp; wire [max_burst_bits-1:0] net_wr_data_acp; wire [addr_width-1:0] net_wr_addr_acp; wire [max_burst_bytes_width:0] net_wr_bytes_acp; wire [axi_qos_width-1:0] net_wr_qos_acp; wire net_rd_req_ddr_acp, net_rd_req_ocm_acp; wire [addr_width-1:0] net_rd_addr_acp; wire [max_burst_bytes_width:0] net_rd_bytes_acp; wire [max_burst_bits-1:0] net_rd_data_ddr_acp; wire [max_burst_bits-1:0] net_rd_data_ocm_acp; wire net_rd_dv_ddr_acp,net_rd_dv_ocm_acp; wire [axi_qos_width-1:0] net_rd_qos_acp; wire ocm_wr_ack_port0; wire ocm_wr_dv_port0; wire ocm_rd_req_port0; wire ocm_rd_dv_port0; wire [addr_width-1:0] ocm_wr_addr_port0; wire [max_burst_bits-1:0] ocm_wr_data_port0; wire [max_burst_bytes_width:0] ocm_wr_bytes_port0; wire [addr_width-1:0] ocm_rd_addr_port0; wire [max_burst_bits-1:0] ocm_rd_data_port0; wire [max_burst_bytes_width:0] ocm_rd_bytes_port0; wire [axi_qos_width-1:0] ocm_wr_qos_port0; wire [axi_qos_width-1:0] ocm_rd_qos_port0; wire ocm_wr_ack_port1; wire ocm_wr_dv_port1; wire ocm_rd_req_port1; wire ocm_rd_dv_port1; wire [addr_width-1:0] ocm_wr_addr_port1; wire [max_burst_bits-1:0] ocm_wr_data_port1; wire [max_burst_bytes_width:0] ocm_wr_bytes_port1; wire [addr_width-1:0] ocm_rd_addr_port1; wire [max_burst_bits-1:0] ocm_rd_data_port1; wire [max_burst_bytes_width:0] ocm_rd_bytes_port1; wire [axi_qos_width-1:0] ocm_wr_qos_port1; wire [axi_qos_width-1:0] ocm_rd_qos_port1; wire ddr_wr_ack_port0; wire ddr_wr_dv_port0; wire ddr_rd_req_port0; wire ddr_rd_dv_port0; wire[addr_width-1:0] ddr_wr_addr_port0; wire[max_burst_bits-1:0] ddr_wr_data_port0; wire[max_burst_bytes_width:0] ddr_wr_bytes_port0; wire[addr_width-1:0] ddr_rd_addr_port0; wire[max_burst_bits-1:0] ddr_rd_data_port0; wire[max_burst_bytes_width:0] ddr_rd_bytes_port0; wire [axi_qos_width-1:0] ddr_wr_qos_port0; wire [axi_qos_width-1:0] ddr_rd_qos_port0; wire ddr_wr_ack_port1; wire ddr_wr_dv_port1; wire ddr_rd_req_port1; wire ddr_rd_dv_port1; wire[addr_width-1:0] ddr_wr_addr_port1; wire[max_burst_bits-1:0] ddr_wr_data_port1; wire[max_burst_bytes_width:0] ddr_wr_bytes_port1; wire[addr_width-1:0] ddr_rd_addr_port1; wire[max_burst_bits-1:0] ddr_rd_data_port1; wire[max_burst_bytes_width:0] ddr_rd_bytes_port1; wire[axi_qos_width-1:0] ddr_wr_qos_port1; wire[axi_qos_width-1:0] ddr_rd_qos_port1; wire ddr_wr_ack_port2; wire ddr_wr_dv_port2; wire ddr_rd_req_port2; wire ddr_rd_dv_port2; wire[addr_width-1:0] ddr_wr_addr_port2; wire[max_burst_bits-1:0] ddr_wr_data_port2; wire[max_burst_bytes_width:0] ddr_wr_bytes_port2; wire[addr_width-1:0] ddr_rd_addr_port2; wire[max_burst_bits-1:0] ddr_rd_data_port2; wire[max_burst_bytes_width:0] ddr_rd_bytes_port2; wire[axi_qos_width-1:0] ddr_wr_qos_port2; wire[axi_qos_width-1:0] ddr_rd_qos_port2; wire ddr_wr_ack_port3; wire ddr_wr_dv_port3; wire ddr_rd_req_port3; wire ddr_rd_dv_port3; wire[addr_width-1:0] ddr_wr_addr_port3; wire[max_burst_bits-1:0] ddr_wr_data_port3; wire[max_burst_bytes_width:0] ddr_wr_bytes_port3; wire[addr_width-1:0] ddr_rd_addr_port3; wire[max_burst_bits-1:0] ddr_rd_data_port3; wire[max_burst_bytes_width:0] ddr_rd_bytes_port3; wire[axi_qos_width-1:0] ddr_wr_qos_port3; wire[axi_qos_width-1:0] ddr_rd_qos_port3; wire reg_rd_req_port0; wire reg_rd_dv_port0; wire[addr_width-1:0] reg_rd_addr_port0; wire[max_burst_bits-1:0] reg_rd_data_port0; wire[max_burst_bytes_width:0] reg_rd_bytes_port0; wire [axi_qos_width-1:0] reg_rd_qos_port0; wire reg_rd_req_port1; wire reg_rd_dv_port1; wire[addr_width-1:0] reg_rd_addr_port1; wire[max_burst_bits-1:0] reg_rd_data_port1; wire[max_burst_bytes_width:0] reg_rd_bytes_port1; wire [axi_qos_width-1:0] reg_rd_qos_port1; wire [11:0] M_AXI_GP0_AWID_FULL; wire [11:0] M_AXI_GP0_WID_FULL; wire [11:0] M_AXI_GP0_ARID_FULL; wire [11:0] M_AXI_GP0_BID_FULL; wire [11:0] M_AXI_GP0_RID_FULL; wire [11:0] M_AXI_GP1_AWID_FULL; wire [11:0] M_AXI_GP1_WID_FULL; wire [11:0] M_AXI_GP1_ARID_FULL; wire [11:0] M_AXI_GP1_BID_FULL; wire [11:0] M_AXI_GP1_RID_FULL; function [5:0] compress_id; input [11:0] id; begin compress_id = id[5:0]; end endfunction function [11:0] uncompress_id; input [5:0] id; begin uncompress_id = {6'b110000, id[5:0]}; end endfunction assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL; assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL; assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL; assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID; assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID; assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL; assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL; assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL; assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID; assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID; processing_system7_bfm_v2_0_5_interconnect_model icm ( .rstn(net_rstn), .sw_clk(net_sw_clk), .w_qos_gp0(net_wr_qos_gp0), .w_qos_gp1(net_wr_qos_gp1), .w_qos_hp0(net_wr_qos_hp0), .w_qos_hp1(net_wr_qos_hp1), .w_qos_hp2(net_wr_qos_hp2), .w_qos_hp3(net_wr_qos_hp3), .r_qos_gp0(net_rd_qos_gp0), .r_qos_gp1(net_rd_qos_gp1), .r_qos_hp0(net_rd_qos_hp0), .r_qos_hp1(net_rd_qos_hp1), .r_qos_hp2(net_rd_qos_hp2), .r_qos_hp3(net_rd_qos_hp3), /* GP Slave ports access */ .wr_ack_ddr_gp0(net_wr_ack_ddr_gp0), .wr_ack_ocm_gp0(net_wr_ack_ocm_gp0), .wr_data_gp0(net_wr_data_gp0), .wr_addr_gp0(net_wr_addr_gp0), .wr_bytes_gp0(net_wr_bytes_gp0), .wr_dv_ddr_gp0(net_wr_dv_ddr_gp0), .wr_dv_ocm_gp0(net_wr_dv_ocm_gp0), .rd_req_ddr_gp0(net_rd_req_ddr_gp0), .rd_req_ocm_gp0(net_rd_req_ocm_gp0), .rd_req_reg_gp0(net_rd_req_reg_gp0), .rd_addr_gp0(net_rd_addr_gp0), .rd_bytes_gp0(net_rd_bytes_gp0), .rd_data_ddr_gp0(net_rd_data_ddr_gp0), .rd_data_ocm_gp0(net_rd_data_ocm_gp0), .rd_data_reg_gp0(net_rd_data_reg_gp0), .rd_dv_ddr_gp0(net_rd_dv_ddr_gp0), .rd_dv_ocm_gp0(net_rd_dv_ocm_gp0), .rd_dv_reg_gp0(net_rd_dv_reg_gp0), .wr_ack_ddr_gp1(net_wr_ack_ddr_gp1), .wr_ack_ocm_gp1(net_wr_ack_ocm_gp1), .wr_data_gp1(net_wr_data_gp1), .wr_addr_gp1(net_wr_addr_gp1), .wr_bytes_gp1(net_wr_bytes_gp1), .wr_dv_ddr_gp1(net_wr_dv_ddr_gp1), .wr_dv_ocm_gp1(net_wr_dv_ocm_gp1), .rd_req_ddr_gp1(net_rd_req_ddr_gp1), .rd_req_ocm_gp1(net_rd_req_ocm_gp1), .rd_req_reg_gp1(net_rd_req_reg_gp1), .rd_addr_gp1(net_rd_addr_gp1), .rd_bytes_gp1(net_rd_bytes_gp1), .rd_data_ddr_gp1(net_rd_data_ddr_gp1), .rd_data_ocm_gp1(net_rd_data_ocm_gp1), .rd_data_reg_gp1(net_rd_data_reg_gp1), .rd_dv_ddr_gp1(net_rd_dv_ddr_gp1), .rd_dv_ocm_gp1(net_rd_dv_ocm_gp1), .rd_dv_reg_gp1(net_rd_dv_reg_gp1), /* HP Slave ports access */ .wr_ack_ddr_hp0(net_wr_ack_ddr_hp0), .wr_ack_ocm_hp0(net_wr_ack_ocm_hp0), .wr_data_hp0(net_wr_data_hp0), .wr_addr_hp0(net_wr_addr_hp0), .wr_bytes_hp0(net_wr_bytes_hp0), .wr_dv_ddr_hp0(net_wr_dv_ddr_hp0), .wr_dv_ocm_hp0(net_wr_dv_ocm_hp0), .rd_req_ddr_hp0(net_rd_req_ddr_hp0), .rd_req_ocm_hp0(net_rd_req_ocm_hp0), .rd_addr_hp0(net_rd_addr_hp0), .rd_bytes_hp0(net_rd_bytes_hp0), .rd_data_ddr_hp0(net_rd_data_ddr_hp0), .rd_data_ocm_hp0(net_rd_data_ocm_hp0), .rd_dv_ddr_hp0(net_rd_dv_ddr_hp0), .rd_dv_ocm_hp0(net_rd_dv_ocm_hp0), .wr_ack_ddr_hp1(net_wr_ack_ddr_hp1), .wr_ack_ocm_hp1(net_wr_ack_ocm_hp1), .wr_data_hp1(net_wr_data_hp1), .wr_addr_hp1(net_wr_addr_hp1), .wr_bytes_hp1(net_wr_bytes_hp1), .wr_dv_ddr_hp1(net_wr_dv_ddr_hp1), .wr_dv_ocm_hp1(net_wr_dv_ocm_hp1), .rd_req_ddr_hp1(net_rd_req_ddr_hp1), .rd_req_ocm_hp1(net_rd_req_ocm_hp1), .rd_addr_hp1(net_rd_addr_hp1), .rd_bytes_hp1(net_rd_bytes_hp1), .rd_data_ddr_hp1(net_rd_data_ddr_hp1), .rd_data_ocm_hp1(net_rd_data_ocm_hp1), .rd_dv_ocm_hp1(net_rd_dv_ocm_hp1), .rd_dv_ddr_hp1(net_rd_dv_ddr_hp1), .wr_ack_ddr_hp2(net_wr_ack_ddr_hp2), .wr_ack_ocm_hp2(net_wr_ack_ocm_hp2), .wr_data_hp2(net_wr_data_hp2), .wr_addr_hp2(net_wr_addr_hp2), .wr_bytes_hp2(net_wr_bytes_hp2), .wr_dv_ocm_hp2(net_wr_dv_ocm_hp2), .wr_dv_ddr_hp2(net_wr_dv_ddr_hp2), .rd_req_ddr_hp2(net_rd_req_ddr_hp2), .rd_req_ocm_hp2(net_rd_req_ocm_hp2), .rd_addr_hp2(net_rd_addr_hp2), .rd_bytes_hp2(net_rd_bytes_hp2), .rd_data_ddr_hp2(net_rd_data_ddr_hp2), .rd_data_ocm_hp2(net_rd_data_ocm_hp2), .rd_dv_ddr_hp2(net_rd_dv_ddr_hp2), .rd_dv_ocm_hp2(net_rd_dv_ocm_hp2), .wr_ack_ocm_hp3(net_wr_ack_ocm_hp3), .wr_ack_ddr_hp3(net_wr_ack_ddr_hp3), .wr_data_hp3(net_wr_data_hp3), .wr_addr_hp3(net_wr_addr_hp3), .wr_bytes_hp3(net_wr_bytes_hp3), .wr_dv_ddr_hp3(net_wr_dv_ddr_hp3), .wr_dv_ocm_hp3(net_wr_dv_ocm_hp3), .rd_req_ddr_hp3(net_rd_req_ddr_hp3), .rd_req_ocm_hp3(net_rd_req_ocm_hp3), .rd_addr_hp3(net_rd_addr_hp3), .rd_bytes_hp3(net_rd_bytes_hp3), .rd_data_ddr_hp3(net_rd_data_ddr_hp3), .rd_data_ocm_hp3(net_rd_data_ocm_hp3), .rd_dv_ddr_hp3(net_rd_dv_ddr_hp3), .rd_dv_ocm_hp3(net_rd_dv_ocm_hp3), /* Goes to port 1 of DDR */ .ddr_wr_ack_port1(ddr_wr_ack_port1), .ddr_wr_dv_port1(ddr_wr_dv_port1), .ddr_rd_req_port1(ddr_rd_req_port1), .ddr_rd_dv_port1 (ddr_rd_dv_port1), .ddr_wr_addr_port1(ddr_wr_addr_port1), .ddr_wr_data_port1(ddr_wr_data_port1), .ddr_wr_bytes_port1(ddr_wr_bytes_port1), .ddr_rd_addr_port1(ddr_rd_addr_port1), .ddr_rd_data_port1(ddr_rd_data_port1), .ddr_rd_bytes_port1(ddr_rd_bytes_port1), .ddr_wr_qos_port1(ddr_wr_qos_port1), .ddr_rd_qos_port1(ddr_rd_qos_port1), /* Goes to port2 of DDR */ .ddr_wr_ack_port2 (ddr_wr_ack_port2), .ddr_wr_dv_port2 (ddr_wr_dv_port2), .ddr_rd_req_port2 (ddr_rd_req_port2), .ddr_rd_dv_port2 (ddr_rd_dv_port2), .ddr_wr_addr_port2(ddr_wr_addr_port2), .ddr_wr_data_port2(ddr_wr_data_port2), .ddr_wr_bytes_port2(ddr_wr_bytes_port2), .ddr_rd_addr_port2(ddr_rd_addr_port2), .ddr_rd_data_port2(ddr_rd_data_port2), .ddr_rd_bytes_port2(ddr_rd_bytes_port2), .ddr_wr_qos_port2 (ddr_wr_qos_port2), .ddr_rd_qos_port2 (ddr_rd_qos_port2), /* Goes to port3 of DDR */ .ddr_wr_ack_port3 (ddr_wr_ack_port3), .ddr_wr_dv_port3 (ddr_wr_dv_port3), .ddr_rd_req_port3 (ddr_rd_req_port3), .ddr_rd_dv_port3 (ddr_rd_dv_port3), .ddr_wr_addr_port3(ddr_wr_addr_port3), .ddr_wr_data_port3(ddr_wr_data_port3), .ddr_wr_bytes_port3(ddr_wr_bytes_port3), .ddr_rd_addr_port3(ddr_rd_addr_port3), .ddr_rd_data_port3(ddr_rd_data_port3), .ddr_rd_bytes_port3(ddr_rd_bytes_port3), .ddr_wr_qos_port3 (ddr_wr_qos_port3), .ddr_rd_qos_port3 (ddr_rd_qos_port3), /* Goes to port 0 of OCM */ .ocm_wr_ack_port1 (ocm_wr_ack_port1), .ocm_wr_dv_port1 (ocm_wr_dv_port1), .ocm_rd_req_port1 (ocm_rd_req_port1), .ocm_rd_dv_port1 (ocm_rd_dv_port1), .ocm_wr_addr_port1(ocm_wr_addr_port1), .ocm_wr_data_port1(ocm_wr_data_port1), .ocm_wr_bytes_port1(ocm_wr_bytes_port1), .ocm_rd_addr_port1(ocm_rd_addr_port1), .ocm_rd_data_port1(ocm_rd_data_port1), .ocm_rd_bytes_port1(ocm_rd_bytes_port1), .ocm_wr_qos_port1(ocm_wr_qos_port1), .ocm_rd_qos_port1(ocm_rd_qos_port1), /* Goes to port 0 of REG */ .reg_rd_qos_port1 (reg_rd_qos_port1) , .reg_rd_req_port1 (reg_rd_req_port1), .reg_rd_dv_port1 (reg_rd_dv_port1), .reg_rd_addr_port1(reg_rd_addr_port1), .reg_rd_data_port1(reg_rd_data_port1), .reg_rd_bytes_port1(reg_rd_bytes_port1) ); processing_system7_bfm_v2_0_5_ddrc ddrc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of DDR */ .ddr_wr_ack_port0 (ddr_wr_ack_port0), .ddr_wr_dv_port0 (ddr_wr_dv_port0), .ddr_rd_req_port0 (ddr_rd_req_port0), .ddr_rd_dv_port0 (ddr_rd_dv_port0), .ddr_wr_addr_port0(net_wr_addr_acp), .ddr_wr_data_port0(net_wr_data_acp), .ddr_wr_bytes_port0(net_wr_bytes_acp), .ddr_rd_addr_port0(net_rd_addr_acp), .ddr_rd_bytes_port0(net_rd_bytes_acp), .ddr_rd_data_port0(ddr_rd_data_port0), .ddr_wr_qos_port0 (net_wr_qos_acp), .ddr_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of DDR */ .ddr_wr_ack_port1 (ddr_wr_ack_port1), .ddr_wr_dv_port1 (ddr_wr_dv_port1), .ddr_rd_req_port1 (ddr_rd_req_port1), .ddr_rd_dv_port1 (ddr_rd_dv_port1), .ddr_wr_addr_port1(ddr_wr_addr_port1), .ddr_wr_data_port1(ddr_wr_data_port1), .ddr_wr_bytes_port1(ddr_wr_bytes_port1), .ddr_rd_addr_port1(ddr_rd_addr_port1), .ddr_rd_data_port1(ddr_rd_data_port1), .ddr_rd_bytes_port1(ddr_rd_bytes_port1), .ddr_wr_qos_port1 (ddr_wr_qos_port1), .ddr_rd_qos_port1 (ddr_rd_qos_port1), /* Goes to port2 of DDR */ .ddr_wr_ack_port2 (ddr_wr_ack_port2), .ddr_wr_dv_port2 (ddr_wr_dv_port2), .ddr_rd_req_port2 (ddr_rd_req_port2), .ddr_rd_dv_port2 (ddr_rd_dv_port2), .ddr_wr_addr_port2(ddr_wr_addr_port2), .ddr_wr_data_port2(ddr_wr_data_port2), .ddr_wr_bytes_port2(ddr_wr_bytes_port2), .ddr_rd_addr_port2(ddr_rd_addr_port2), .ddr_rd_data_port2(ddr_rd_data_port2), .ddr_rd_bytes_port2(ddr_rd_bytes_port2), .ddr_wr_qos_port2 (ddr_wr_qos_port2), .ddr_rd_qos_port2 (ddr_rd_qos_port2), /* Goes to port3 of DDR */ .ddr_wr_ack_port3 (ddr_wr_ack_port3), .ddr_wr_dv_port3 (ddr_wr_dv_port3), .ddr_rd_req_port3 (ddr_rd_req_port3), .ddr_rd_dv_port3 (ddr_rd_dv_port3), .ddr_wr_addr_port3(ddr_wr_addr_port3), .ddr_wr_data_port3(ddr_wr_data_port3), .ddr_wr_bytes_port3(ddr_wr_bytes_port3), .ddr_rd_addr_port3(ddr_rd_addr_port3), .ddr_rd_data_port3(ddr_rd_data_port3), .ddr_rd_bytes_port3(ddr_rd_bytes_port3), .ddr_wr_qos_port3 (ddr_wr_qos_port3), .ddr_rd_qos_port3 (ddr_rd_qos_port3) ); processing_system7_bfm_v2_0_5_ocmc ocmc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of OCM */ .ocm_wr_ack_port0 (ocm_wr_ack_port0), .ocm_wr_dv_port0 (ocm_wr_dv_port0), .ocm_rd_req_port0 (ocm_rd_req_port0), .ocm_rd_dv_port0 (ocm_rd_dv_port0), .ocm_wr_addr_port0(net_wr_addr_acp), .ocm_wr_data_port0(net_wr_data_acp), .ocm_wr_bytes_port0(net_wr_bytes_acp), .ocm_rd_addr_port0(net_rd_addr_acp), .ocm_rd_bytes_port0(net_rd_bytes_acp), .ocm_rd_data_port0(ocm_rd_data_port0), .ocm_wr_qos_port0 (net_wr_qos_acp), .ocm_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of OCM */ .ocm_wr_ack_port1 (ocm_wr_ack_port1), .ocm_wr_dv_port1 (ocm_wr_dv_port1), .ocm_rd_req_port1 (ocm_rd_req_port1), .ocm_rd_dv_port1 (ocm_rd_dv_port1), .ocm_wr_addr_port1(ocm_wr_addr_port1), .ocm_wr_data_port1(ocm_wr_data_port1), .ocm_wr_bytes_port1(ocm_wr_bytes_port1), .ocm_rd_addr_port1(ocm_rd_addr_port1), .ocm_rd_data_port1(ocm_rd_data_port1), .ocm_rd_bytes_port1(ocm_rd_bytes_port1), .ocm_wr_qos_port1(ocm_wr_qos_port1), .ocm_rd_qos_port1(ocm_rd_qos_port1) ); processing_system7_bfm_v2_0_5_regc regc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of REG */ .reg_rd_req_port0 (reg_rd_req_port0), .reg_rd_dv_port0 (reg_rd_dv_port0), .reg_rd_addr_port0(net_rd_addr_acp), .reg_rd_bytes_port0(net_rd_bytes_acp), .reg_rd_data_port0(reg_rd_data_port0), .reg_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of REG */ .reg_rd_req_port1 (reg_rd_req_port1), .reg_rd_dv_port1 (reg_rd_dv_port1), .reg_rd_addr_port1(reg_rd_addr_port1), .reg_rd_data_port1(reg_rd_data_port1), .reg_rd_bytes_port1(reg_rd_bytes_port1), .reg_rd_qos_port1(reg_rd_qos_port1) ); /* include axi_gp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_gp.v" /* include axi_hp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_hp.v" /* include axi_acp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_acp.v" endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_processing_system7_bfm.v * * Date : 2012-11 * * Description : Processing_system7_bfm Top (zynq_bfm top) * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_processing_system7_bfm ( CAN0_PHY_TX, CAN0_PHY_RX, CAN1_PHY_TX, CAN1_PHY_RX, ENET0_GMII_TX_EN, ENET0_GMII_TX_ER, ENET0_MDIO_MDC, ENET0_MDIO_O, ENET0_MDIO_T, ENET0_PTP_DELAY_REQ_RX, ENET0_PTP_DELAY_REQ_TX, ENET0_PTP_PDELAY_REQ_RX, ENET0_PTP_PDELAY_REQ_TX, ENET0_PTP_PDELAY_RESP_RX, ENET0_PTP_PDELAY_RESP_TX, ENET0_PTP_SYNC_FRAME_RX, ENET0_PTP_SYNC_FRAME_TX, ENET0_SOF_RX, ENET0_SOF_TX, ENET0_GMII_TXD, ENET0_GMII_COL, ENET0_GMII_CRS, ENET0_EXT_INTIN, ENET0_GMII_RX_CLK, ENET0_GMII_RX_DV, ENET0_GMII_RX_ER, ENET0_GMII_TX_CLK, ENET0_MDIO_I, ENET0_GMII_RXD, ENET1_GMII_TX_EN, ENET1_GMII_TX_ER, ENET1_MDIO_MDC, ENET1_MDIO_O, ENET1_MDIO_T, ENET1_PTP_DELAY_REQ_RX, ENET1_PTP_DELAY_REQ_TX, ENET1_PTP_PDELAY_REQ_RX, ENET1_PTP_PDELAY_REQ_TX, ENET1_PTP_PDELAY_RESP_RX, ENET1_PTP_PDELAY_RESP_TX, ENET1_PTP_SYNC_FRAME_RX, ENET1_PTP_SYNC_FRAME_TX, ENET1_SOF_RX, ENET1_SOF_TX, ENET1_GMII_TXD, ENET1_GMII_COL, ENET1_GMII_CRS, ENET1_EXT_INTIN, ENET1_GMII_RX_CLK, ENET1_GMII_RX_DV, ENET1_GMII_RX_ER, ENET1_GMII_TX_CLK, ENET1_MDIO_I, ENET1_GMII_RXD, GPIO_I, GPIO_O, GPIO_T, I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I, I2C0_SCL_O, I2C0_SCL_T, I2C1_SDA_I, I2C1_SDA_O, I2C1_SDA_T, I2C1_SCL_I, I2C1_SCL_O, I2C1_SCL_T, PJTAG_TCK, PJTAG_TMS, PJTAG_TD_I, PJTAG_TD_T, PJTAG_TD_O, SDIO0_CLK, SDIO0_CLK_FB, SDIO0_CMD_O, SDIO0_CMD_I, SDIO0_CMD_T, SDIO0_DATA_I, SDIO0_DATA_O, SDIO0_DATA_T, SDIO0_LED, SDIO0_CDN, SDIO0_WP, SDIO0_BUSPOW, SDIO0_BUSVOLT, SDIO1_CLK, SDIO1_CLK_FB, SDIO1_CMD_O, SDIO1_CMD_I, SDIO1_CMD_T, SDIO1_DATA_I, SDIO1_DATA_O, SDIO1_DATA_T, SDIO1_LED, SDIO1_CDN, SDIO1_WP, SDIO1_BUSPOW, SDIO1_BUSVOLT, SPI0_SCLK_I, SPI0_SCLK_O, SPI0_SCLK_T, SPI0_MOSI_I, SPI0_MOSI_O, SPI0_MOSI_T, SPI0_MISO_I, SPI0_MISO_O, SPI0_MISO_T, SPI0_SS_I, SPI0_SS_O, SPI0_SS1_O, SPI0_SS2_O, SPI0_SS_T, SPI1_SCLK_I, SPI1_SCLK_O, SPI1_SCLK_T, SPI1_MOSI_I, SPI1_MOSI_O, SPI1_MOSI_T, SPI1_MISO_I, SPI1_MISO_O, SPI1_MISO_T, SPI1_SS_I, SPI1_SS_O, SPI1_SS1_O, SPI1_SS2_O, SPI1_SS_T, UART0_DTRN, UART0_RTSN, UART0_TX, UART0_CTSN, UART0_DCDN, UART0_DSRN, UART0_RIN, UART0_RX, UART1_DTRN, UART1_RTSN, UART1_TX, UART1_CTSN, UART1_DCDN, UART1_DSRN, UART1_RIN, UART1_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, TTC0_CLK0_IN, TTC0_CLK1_IN, TTC0_CLK2_IN, TTC1_WAVE0_OUT, TTC1_WAVE1_OUT, TTC1_WAVE2_OUT, TTC1_CLK0_IN, TTC1_CLK1_IN, TTC1_CLK2_IN, WDT_CLK_IN, WDT_RST_OUT, TRACE_CLK, TRACE_CTL, TRACE_DATA, USB0_PORT_INDCTL, USB1_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB1_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, USB1_VBUS_PWRFAULT, SRAM_INTIN, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, M_AXI_GP1_ARVALID, M_AXI_GP1_AWVALID, M_AXI_GP1_BREADY, M_AXI_GP1_RREADY, M_AXI_GP1_WLAST, M_AXI_GP1_WVALID, M_AXI_GP1_ARID, M_AXI_GP1_AWID, M_AXI_GP1_WID, M_AXI_GP1_ARBURST, M_AXI_GP1_ARLOCK, M_AXI_GP1_ARSIZE, M_AXI_GP1_AWBURST, M_AXI_GP1_AWLOCK, M_AXI_GP1_AWSIZE, M_AXI_GP1_ARPROT, M_AXI_GP1_AWPROT, M_AXI_GP1_ARADDR, M_AXI_GP1_AWADDR, M_AXI_GP1_WDATA, M_AXI_GP1_ARCACHE, M_AXI_GP1_ARLEN, M_AXI_GP1_ARQOS, M_AXI_GP1_AWCACHE, M_AXI_GP1_AWLEN, M_AXI_GP1_AWQOS, M_AXI_GP1_WSTRB, M_AXI_GP1_ACLK, M_AXI_GP1_ARREADY, M_AXI_GP1_AWREADY, M_AXI_GP1_BVALID, M_AXI_GP1_RLAST, M_AXI_GP1_RVALID, M_AXI_GP1_WREADY, M_AXI_GP1_BID, M_AXI_GP1_RID, M_AXI_GP1_BRESP, M_AXI_GP1_RRESP, M_AXI_GP1_RDATA, S_AXI_GP0_ARREADY, S_AXI_GP0_AWREADY, S_AXI_GP0_BVALID, S_AXI_GP0_RLAST, S_AXI_GP0_RVALID, S_AXI_GP0_WREADY, S_AXI_GP0_BRESP, S_AXI_GP0_RRESP, S_AXI_GP0_RDATA, S_AXI_GP0_BID, S_AXI_GP0_RID, S_AXI_GP0_ACLK, S_AXI_GP0_ARVALID, S_AXI_GP0_AWVALID, S_AXI_GP0_BREADY, S_AXI_GP0_RREADY, S_AXI_GP0_WLAST, S_AXI_GP0_WVALID, S_AXI_GP0_ARBURST, S_AXI_GP0_ARLOCK, S_AXI_GP0_ARSIZE, S_AXI_GP0_AWBURST, S_AXI_GP0_AWLOCK, S_AXI_GP0_AWSIZE, S_AXI_GP0_ARPROT, S_AXI_GP0_AWPROT, S_AXI_GP0_ARADDR, S_AXI_GP0_AWADDR, S_AXI_GP0_WDATA, S_AXI_GP0_ARCACHE, S_AXI_GP0_ARLEN, S_AXI_GP0_ARQOS, S_AXI_GP0_AWCACHE, S_AXI_GP0_AWLEN, S_AXI_GP0_AWQOS, S_AXI_GP0_WSTRB, S_AXI_GP0_ARID, S_AXI_GP0_AWID, S_AXI_GP0_WID, S_AXI_GP1_ARREADY, S_AXI_GP1_AWREADY, S_AXI_GP1_BVALID, S_AXI_GP1_RLAST, S_AXI_GP1_RVALID, S_AXI_GP1_WREADY, S_AXI_GP1_BRESP, S_AXI_GP1_RRESP, S_AXI_GP1_RDATA, S_AXI_GP1_BID, S_AXI_GP1_RID, S_AXI_GP1_ACLK, S_AXI_GP1_ARVALID, S_AXI_GP1_AWVALID, S_AXI_GP1_BREADY, S_AXI_GP1_RREADY, S_AXI_GP1_WLAST, S_AXI_GP1_WVALID, S_AXI_GP1_ARBURST, S_AXI_GP1_ARLOCK, S_AXI_GP1_ARSIZE, S_AXI_GP1_AWBURST, S_AXI_GP1_AWLOCK, S_AXI_GP1_AWSIZE, S_AXI_GP1_ARPROT, S_AXI_GP1_AWPROT, S_AXI_GP1_ARADDR, S_AXI_GP1_AWADDR, S_AXI_GP1_WDATA, S_AXI_GP1_ARCACHE, S_AXI_GP1_ARLEN, S_AXI_GP1_ARQOS, S_AXI_GP1_AWCACHE, S_AXI_GP1_AWLEN, S_AXI_GP1_AWQOS, S_AXI_GP1_WSTRB, S_AXI_GP1_ARID, S_AXI_GP1_AWID, S_AXI_GP1_WID, S_AXI_ACP_AWREADY, S_AXI_ACP_ARREADY, S_AXI_ACP_BVALID, S_AXI_ACP_RLAST, S_AXI_ACP_RVALID, S_AXI_ACP_WREADY, S_AXI_ACP_BRESP, S_AXI_ACP_RRESP, S_AXI_ACP_BID, S_AXI_ACP_RID, S_AXI_ACP_RDATA, S_AXI_ACP_ACLK, S_AXI_ACP_ARVALID, S_AXI_ACP_AWVALID, S_AXI_ACP_BREADY, S_AXI_ACP_RREADY, S_AXI_ACP_WLAST, S_AXI_ACP_WVALID, S_AXI_ACP_ARID, S_AXI_ACP_ARPROT, S_AXI_ACP_AWID, S_AXI_ACP_AWPROT, S_AXI_ACP_WID, S_AXI_ACP_ARADDR, S_AXI_ACP_AWADDR, S_AXI_ACP_ARCACHE, S_AXI_ACP_ARLEN, S_AXI_ACP_ARQOS, S_AXI_ACP_AWCACHE, S_AXI_ACP_AWLEN, S_AXI_ACP_AWQOS, S_AXI_ACP_ARBURST, S_AXI_ACP_ARLOCK, S_AXI_ACP_ARSIZE, S_AXI_ACP_AWBURST, S_AXI_ACP_AWLOCK, S_AXI_ACP_AWSIZE, S_AXI_ACP_ARUSER, S_AXI_ACP_AWUSER, S_AXI_ACP_WDATA, S_AXI_ACP_WSTRB, S_AXI_HP0_ARREADY, S_AXI_HP0_AWREADY, S_AXI_HP0_BVALID, S_AXI_HP0_RLAST, S_AXI_HP0_RVALID, S_AXI_HP0_WREADY, S_AXI_HP0_BRESP, S_AXI_HP0_RRESP, S_AXI_HP0_BID, S_AXI_HP0_RID, S_AXI_HP0_RDATA, S_AXI_HP0_RCOUNT, S_AXI_HP0_WCOUNT, S_AXI_HP0_RACOUNT, S_AXI_HP0_WACOUNT, S_AXI_HP0_ACLK, S_AXI_HP0_ARVALID, S_AXI_HP0_AWVALID, S_AXI_HP0_BREADY, S_AXI_HP0_RDISSUECAP1_EN, S_AXI_HP0_RREADY, S_AXI_HP0_WLAST, S_AXI_HP0_WRISSUECAP1_EN, S_AXI_HP0_WVALID, S_AXI_HP0_ARBURST, S_AXI_HP0_ARLOCK, S_AXI_HP0_ARSIZE, S_AXI_HP0_AWBURST, S_AXI_HP0_AWLOCK, S_AXI_HP0_AWSIZE, S_AXI_HP0_ARPROT, S_AXI_HP0_AWPROT, S_AXI_HP0_ARADDR, S_AXI_HP0_AWADDR, S_AXI_HP0_ARCACHE, S_AXI_HP0_ARLEN, S_AXI_HP0_ARQOS, S_AXI_HP0_AWCACHE, S_AXI_HP0_AWLEN, S_AXI_HP0_AWQOS, S_AXI_HP0_ARID, S_AXI_HP0_AWID, S_AXI_HP0_WID, S_AXI_HP0_WDATA, S_AXI_HP0_WSTRB, S_AXI_HP1_ARREADY, S_AXI_HP1_AWREADY, S_AXI_HP1_BVALID, S_AXI_HP1_RLAST, S_AXI_HP1_RVALID, S_AXI_HP1_WREADY, S_AXI_HP1_BRESP, S_AXI_HP1_RRESP, S_AXI_HP1_BID, S_AXI_HP1_RID, S_AXI_HP1_RDATA, S_AXI_HP1_RCOUNT, S_AXI_HP1_WCOUNT, S_AXI_HP1_RACOUNT, S_AXI_HP1_WACOUNT, S_AXI_HP1_ACLK, S_AXI_HP1_ARVALID, S_AXI_HP1_AWVALID, S_AXI_HP1_BREADY, S_AXI_HP1_RDISSUECAP1_EN, S_AXI_HP1_RREADY, S_AXI_HP1_WLAST, S_AXI_HP1_WRISSUECAP1_EN, S_AXI_HP1_WVALID, S_AXI_HP1_ARBURST, S_AXI_HP1_ARLOCK, S_AXI_HP1_ARSIZE, S_AXI_HP1_AWBURST, S_AXI_HP1_AWLOCK, S_AXI_HP1_AWSIZE, S_AXI_HP1_ARPROT, S_AXI_HP1_AWPROT, S_AXI_HP1_ARADDR, S_AXI_HP1_AWADDR, S_AXI_HP1_ARCACHE, S_AXI_HP1_ARLEN, S_AXI_HP1_ARQOS, S_AXI_HP1_AWCACHE, S_AXI_HP1_AWLEN, S_AXI_HP1_AWQOS, S_AXI_HP1_ARID, S_AXI_HP1_AWID, S_AXI_HP1_WID, S_AXI_HP1_WDATA, S_AXI_HP1_WSTRB, S_AXI_HP2_ARREADY, S_AXI_HP2_AWREADY, S_AXI_HP2_BVALID, S_AXI_HP2_RLAST, S_AXI_HP2_RVALID, S_AXI_HP2_WREADY, S_AXI_HP2_BRESP, S_AXI_HP2_RRESP, S_AXI_HP2_BID, S_AXI_HP2_RID, S_AXI_HP2_RDATA, S_AXI_HP2_RCOUNT, S_AXI_HP2_WCOUNT, S_AXI_HP2_RACOUNT, S_AXI_HP2_WACOUNT, S_AXI_HP2_ACLK, S_AXI_HP2_ARVALID, S_AXI_HP2_AWVALID, S_AXI_HP2_BREADY, S_AXI_HP2_RDISSUECAP1_EN, S_AXI_HP2_RREADY, S_AXI_HP2_WLAST, S_AXI_HP2_WRISSUECAP1_EN, S_AXI_HP2_WVALID, S_AXI_HP2_ARBURST, S_AXI_HP2_ARLOCK, S_AXI_HP2_ARSIZE, S_AXI_HP2_AWBURST, S_AXI_HP2_AWLOCK, S_AXI_HP2_AWSIZE, S_AXI_HP2_ARPROT, S_AXI_HP2_AWPROT, S_AXI_HP2_ARADDR, S_AXI_HP2_AWADDR, S_AXI_HP2_ARCACHE, S_AXI_HP2_ARLEN, S_AXI_HP2_ARQOS, S_AXI_HP2_AWCACHE, S_AXI_HP2_AWLEN, S_AXI_HP2_AWQOS, S_AXI_HP2_ARID, S_AXI_HP2_AWID, S_AXI_HP2_WID, S_AXI_HP2_WDATA, S_AXI_HP2_WSTRB, S_AXI_HP3_ARREADY, S_AXI_HP3_AWREADY, S_AXI_HP3_BVALID, S_AXI_HP3_RLAST, S_AXI_HP3_RVALID, S_AXI_HP3_WREADY, S_AXI_HP3_BRESP, S_AXI_HP3_RRESP, S_AXI_HP3_BID, S_AXI_HP3_RID, S_AXI_HP3_RDATA, S_AXI_HP3_RCOUNT, S_AXI_HP3_WCOUNT, S_AXI_HP3_RACOUNT, S_AXI_HP3_WACOUNT, S_AXI_HP3_ACLK, S_AXI_HP3_ARVALID, S_AXI_HP3_AWVALID, S_AXI_HP3_BREADY, S_AXI_HP3_RDISSUECAP1_EN, S_AXI_HP3_RREADY, S_AXI_HP3_WLAST, S_AXI_HP3_WRISSUECAP1_EN, S_AXI_HP3_WVALID, S_AXI_HP3_ARBURST, S_AXI_HP3_ARLOCK, S_AXI_HP3_ARSIZE, S_AXI_HP3_AWBURST, S_AXI_HP3_AWLOCK, S_AXI_HP3_AWSIZE, S_AXI_HP3_ARPROT, S_AXI_HP3_AWPROT, S_AXI_HP3_ARADDR, S_AXI_HP3_AWADDR, S_AXI_HP3_ARCACHE, S_AXI_HP3_ARLEN, S_AXI_HP3_ARQOS, S_AXI_HP3_AWCACHE, S_AXI_HP3_AWLEN, S_AXI_HP3_AWQOS, S_AXI_HP3_ARID, S_AXI_HP3_AWID, S_AXI_HP3_WID, S_AXI_HP3_WDATA, S_AXI_HP3_WSTRB, DMA0_DATYPE, DMA0_DAVALID, DMA0_DRREADY, DMA0_ACLK, DMA0_DAREADY, DMA0_DRLAST, DMA0_DRVALID, DMA0_DRTYPE, DMA1_DATYPE, DMA1_DAVALID, DMA1_DRREADY, DMA1_ACLK, DMA1_DAREADY, DMA1_DRLAST, DMA1_DRVALID, DMA1_DRTYPE, DMA2_DATYPE, DMA2_DAVALID, DMA2_DRREADY, DMA2_ACLK, DMA2_DAREADY, DMA2_DRLAST, DMA2_DRVALID, DMA3_DRVALID, DMA3_DATYPE, DMA3_DAVALID, DMA3_DRREADY, DMA3_ACLK, DMA3_DAREADY, DMA3_DRLAST, DMA2_DRTYPE, DMA3_DRTYPE, FTMD_TRACEIN_DATA, FTMD_TRACEIN_VALID, FTMD_TRACEIN_CLK, FTMD_TRACEIN_ATID, FTMT_F2P_TRIG, FTMT_F2P_TRIGACK, FTMT_F2P_DEBUG, FTMT_P2F_TRIGACK, FTMT_P2F_TRIG, FTMT_P2F_DEBUG, FCLK_CLK3, FCLK_CLK2, FCLK_CLK1, FCLK_CLK0, FCLK_CLKTRIG3_N, FCLK_CLKTRIG2_N, FCLK_CLKTRIG1_N, FCLK_CLKTRIG0_N, FCLK_RESET3_N, FCLK_RESET2_N, FCLK_RESET1_N, FCLK_RESET0_N, FPGA_IDLE_N, DDR_ARB, IRQ_F2P, Core0_nFIQ, Core0_nIRQ, Core1_nFIQ, Core1_nIRQ, EVENT_EVENTO, EVENT_STANDBYWFE, EVENT_STANDBYWFI, EVENT_EVENTI, MIO, DDR_Clk, DDR_Clk_n, DDR_CKE, DDR_CS_n, DDR_RAS_n, DDR_CAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_ODT, DDR_DRSTB, DDR_DQ, DDR_DM, DDR_DQS, DDR_DQS_n, DDR_VRN, DDR_VRP, PS_SRSTB, PS_CLK, PS_PORB, IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC0, IRQ_P2F_DMAC1, IRQ_P2F_DMAC2, IRQ_P2F_DMAC3, IRQ_P2F_DMAC4, IRQ_P2F_DMAC5, IRQ_P2F_DMAC6, IRQ_P2F_DMAC7, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1 ); /* parameters for gen_clk */ parameter C_FCLK_CLK0_FREQ = 50; parameter C_FCLK_CLK1_FREQ = 50; parameter C_FCLK_CLK3_FREQ = 50; parameter C_FCLK_CLK2_FREQ = 50; parameter C_HIGH_OCM_EN = 0; /* parameters for HP ports */ parameter C_USE_S_AXI_HP0 = 0; parameter C_USE_S_AXI_HP1 = 0; parameter C_USE_S_AXI_HP2 = 0; parameter C_USE_S_AXI_HP3 = 0; parameter C_S_AXI_HP0_DATA_WIDTH = 32; parameter C_S_AXI_HP1_DATA_WIDTH = 32; parameter C_S_AXI_HP2_DATA_WIDTH = 32; parameter C_S_AXI_HP3_DATA_WIDTH = 32; parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12; parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12; parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0; parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0; /* Do we need these parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */ parameter C_S_AXI_HP0_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP1_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP2_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP3_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP0_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP1_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP2_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP3_HIGHADDR = 32'hFFFF_FFFF; /* parameters for GP and ACP ports */ parameter C_USE_M_AXI_GP0 = 0; parameter C_USE_M_AXI_GP1 = 0; parameter C_USE_S_AXI_GP0 = 1; parameter C_USE_S_AXI_GP1 = 1; /* Do we need this? parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0; parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0; parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/ parameter C_S_AXI_GP0_BASEADDR = 32'h0000_0000; parameter C_S_AXI_GP1_BASEADDR = 32'h0000_0000; parameter C_S_AXI_GP0_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_GP1_HIGHADDR = 32'hFFFF_FFFF; parameter C_USE_S_AXI_ACP = 1; parameter C_S_AXI_ACP_BASEADDR = 32'h0000_0000; parameter C_S_AXI_ACP_HIGHADDR = 32'hFFFF_FFFF; `include "processing_system7_bfm_v2_0_5_local_params.v" output CAN0_PHY_TX; input CAN0_PHY_RX; output CAN1_PHY_TX; input CAN1_PHY_RX; output ENET0_GMII_TX_EN; output ENET0_GMII_TX_ER; output ENET0_MDIO_MDC; output ENET0_MDIO_O; output ENET0_MDIO_T; output ENET0_PTP_DELAY_REQ_RX; output ENET0_PTP_DELAY_REQ_TX; output ENET0_PTP_PDELAY_REQ_RX; output ENET0_PTP_PDELAY_REQ_TX; output ENET0_PTP_PDELAY_RESP_RX; output ENET0_PTP_PDELAY_RESP_TX; output ENET0_PTP_SYNC_FRAME_RX; output ENET0_PTP_SYNC_FRAME_TX; output ENET0_SOF_RX; output ENET0_SOF_TX; output [7:0] ENET0_GMII_TXD; input ENET0_GMII_COL; input ENET0_GMII_CRS; input ENET0_EXT_INTIN; input ENET0_GMII_RX_CLK; input ENET0_GMII_RX_DV; input ENET0_GMII_RX_ER; input ENET0_GMII_TX_CLK; input ENET0_MDIO_I; input [7:0] ENET0_GMII_RXD; output ENET1_GMII_TX_EN; output ENET1_GMII_TX_ER; output ENET1_MDIO_MDC; output ENET1_MDIO_O; output ENET1_MDIO_T; output ENET1_PTP_DELAY_REQ_RX; output ENET1_PTP_DELAY_REQ_TX; output ENET1_PTP_PDELAY_REQ_RX; output ENET1_PTP_PDELAY_REQ_TX; output ENET1_PTP_PDELAY_RESP_RX; output ENET1_PTP_PDELAY_RESP_TX; output ENET1_PTP_SYNC_FRAME_RX; output ENET1_PTP_SYNC_FRAME_TX; output ENET1_SOF_RX; output ENET1_SOF_TX; output [7:0] ENET1_GMII_TXD; input ENET1_GMII_COL; input ENET1_GMII_CRS; input ENET1_EXT_INTIN; input ENET1_GMII_RX_CLK; input ENET1_GMII_RX_DV; input ENET1_GMII_RX_ER; input ENET1_GMII_TX_CLK; input ENET1_MDIO_I; input [7:0] ENET1_GMII_RXD; input [63:0] GPIO_I; output [63:0] GPIO_O; output [63:0] GPIO_T; input I2C0_SDA_I; output I2C0_SDA_O; output I2C0_SDA_T; input I2C0_SCL_I; output I2C0_SCL_O; output I2C0_SCL_T; input I2C1_SDA_I; output I2C1_SDA_O; output I2C1_SDA_T; input I2C1_SCL_I; output I2C1_SCL_O; output I2C1_SCL_T; input PJTAG_TCK; input PJTAG_TMS; input PJTAG_TD_I; output PJTAG_TD_T; output PJTAG_TD_O; output SDIO0_CLK; input SDIO0_CLK_FB; output SDIO0_CMD_O; input SDIO0_CMD_I; output SDIO0_CMD_T; input [3:0] SDIO0_DATA_I; output [3:0] SDIO0_DATA_O; output [3:0] SDIO0_DATA_T; output SDIO0_LED; input SDIO0_CDN; input SDIO0_WP; output SDIO0_BUSPOW; output [2:0] SDIO0_BUSVOLT; output SDIO1_CLK; input SDIO1_CLK_FB; output SDIO1_CMD_O; input SDIO1_CMD_I; output SDIO1_CMD_T; input [3:0] SDIO1_DATA_I; output [3:0] SDIO1_DATA_O; output [3:0] SDIO1_DATA_T; output SDIO1_LED; input SDIO1_CDN; input SDIO1_WP; output SDIO1_BUSPOW; output [2:0] SDIO1_BUSVOLT; input SPI0_SCLK_I; output SPI0_SCLK_O; output SPI0_SCLK_T; input SPI0_MOSI_I; output SPI0_MOSI_O; output SPI0_MOSI_T; input SPI0_MISO_I; output SPI0_MISO_O; output SPI0_MISO_T; input SPI0_SS_I; output SPI0_SS_O; output SPI0_SS1_O; output SPI0_SS2_O; output SPI0_SS_T; input SPI1_SCLK_I; output SPI1_SCLK_O; output SPI1_SCLK_T; input SPI1_MOSI_I; output SPI1_MOSI_O; output SPI1_MOSI_T; input SPI1_MISO_I; output SPI1_MISO_O; output SPI1_MISO_T; input SPI1_SS_I; output SPI1_SS_O; output SPI1_SS1_O; output SPI1_SS2_O; output SPI1_SS_T; output UART0_DTRN; output UART0_RTSN; output UART0_TX; input UART0_CTSN; input UART0_DCDN; input UART0_DSRN; input UART0_RIN; input UART0_RX; output UART1_DTRN; output UART1_RTSN; output UART1_TX; input UART1_CTSN; input UART1_DCDN; input UART1_DSRN; input UART1_RIN; input UART1_RX; output TTC0_WAVE0_OUT; output TTC0_WAVE1_OUT; output TTC0_WAVE2_OUT; input TTC0_CLK0_IN; input TTC0_CLK1_IN; input TTC0_CLK2_IN; output TTC1_WAVE0_OUT; output TTC1_WAVE1_OUT; output TTC1_WAVE2_OUT; input TTC1_CLK0_IN; input TTC1_CLK1_IN; input TTC1_CLK2_IN; input WDT_CLK_IN; output WDT_RST_OUT; input TRACE_CLK; output TRACE_CTL; output [31:0] TRACE_DATA; output [1:0] USB0_PORT_INDCTL; output [1:0] USB1_PORT_INDCTL; output USB0_VBUS_PWRSELECT; output USB1_VBUS_PWRSELECT; input USB0_VBUS_PWRFAULT; input USB1_VBUS_PWRFAULT; input SRAM_INTIN; output M_AXI_GP0_ARVALID; output M_AXI_GP0_AWVALID; output M_AXI_GP0_BREADY; output M_AXI_GP0_RREADY; output M_AXI_GP0_WLAST; output M_AXI_GP0_WVALID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID; output [1:0] M_AXI_GP0_ARBURST; output [1:0] M_AXI_GP0_ARLOCK; output [2:0] M_AXI_GP0_ARSIZE; output [1:0] M_AXI_GP0_AWBURST; output [1:0] M_AXI_GP0_AWLOCK; output [2:0] M_AXI_GP0_AWSIZE; output [2:0] M_AXI_GP0_ARPROT; output [2:0] M_AXI_GP0_AWPROT; output [31:0] M_AXI_GP0_ARADDR; output [31:0] M_AXI_GP0_AWADDR; output [31:0] M_AXI_GP0_WDATA; output [3:0] M_AXI_GP0_ARCACHE; output [3:0] M_AXI_GP0_ARLEN; output [3:0] M_AXI_GP0_ARQOS; output [3:0] M_AXI_GP0_AWCACHE; output [3:0] M_AXI_GP0_AWLEN; output [3:0] M_AXI_GP0_AWQOS; output [3:0] M_AXI_GP0_WSTRB; input M_AXI_GP0_ACLK; input M_AXI_GP0_ARREADY; input M_AXI_GP0_AWREADY; input M_AXI_GP0_BVALID; input M_AXI_GP0_RLAST; input M_AXI_GP0_RVALID; input M_AXI_GP0_WREADY; input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID; input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID; input [1:0] M_AXI_GP0_BRESP; input [1:0] M_AXI_GP0_RRESP; input [31:0] M_AXI_GP0_RDATA; output M_AXI_GP1_ARVALID; output M_AXI_GP1_AWVALID; output M_AXI_GP1_BREADY; output M_AXI_GP1_RREADY; output M_AXI_GP1_WLAST; output M_AXI_GP1_WVALID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID; output [1:0] M_AXI_GP1_ARBURST; output [1:0] M_AXI_GP1_ARLOCK; output [2:0] M_AXI_GP1_ARSIZE; output [1:0] M_AXI_GP1_AWBURST; output [1:0] M_AXI_GP1_AWLOCK; output [2:0] M_AXI_GP1_AWSIZE; output [2:0] M_AXI_GP1_ARPROT; output [2:0] M_AXI_GP1_AWPROT; output [31:0] M_AXI_GP1_ARADDR; output [31:0] M_AXI_GP1_AWADDR; output [31:0] M_AXI_GP1_WDATA; output [3:0] M_AXI_GP1_ARCACHE; output [3:0] M_AXI_GP1_ARLEN; output [3:0] M_AXI_GP1_ARQOS; output [3:0] M_AXI_GP1_AWCACHE; output [3:0] M_AXI_GP1_AWLEN; output [3:0] M_AXI_GP1_AWQOS; output [3:0] M_AXI_GP1_WSTRB; input M_AXI_GP1_ACLK; input M_AXI_GP1_ARREADY; input M_AXI_GP1_AWREADY; input M_AXI_GP1_BVALID; input M_AXI_GP1_RLAST; input M_AXI_GP1_RVALID; input M_AXI_GP1_WREADY; input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID; input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID; input [1:0] M_AXI_GP1_BRESP; input [1:0] M_AXI_GP1_RRESP; input [31:0] M_AXI_GP1_RDATA; output S_AXI_GP0_ARREADY; output S_AXI_GP0_AWREADY; output S_AXI_GP0_BVALID; output S_AXI_GP0_RLAST; output S_AXI_GP0_RVALID; output S_AXI_GP0_WREADY; output [1:0] S_AXI_GP0_BRESP; output [1:0] S_AXI_GP0_RRESP; output [31:0] S_AXI_GP0_RDATA; output [5:0] S_AXI_GP0_BID; output [5:0] S_AXI_GP0_RID; input S_AXI_GP0_ACLK; input S_AXI_GP0_ARVALID; input S_AXI_GP0_AWVALID; input S_AXI_GP0_BREADY; input S_AXI_GP0_RREADY; input S_AXI_GP0_WLAST; input S_AXI_GP0_WVALID; input [1:0] S_AXI_GP0_ARBURST; input [1:0] S_AXI_GP0_ARLOCK; input [2:0] S_AXI_GP0_ARSIZE; input [1:0] S_AXI_GP0_AWBURST; input [1:0] S_AXI_GP0_AWLOCK; input [2:0] S_AXI_GP0_AWSIZE; input [2:0] S_AXI_GP0_ARPROT; input [2:0] S_AXI_GP0_AWPROT; input [31:0] S_AXI_GP0_ARADDR; input [31:0] S_AXI_GP0_AWADDR; input [31:0] S_AXI_GP0_WDATA; input [3:0] S_AXI_GP0_ARCACHE; input [3:0] S_AXI_GP0_ARLEN; input [3:0] S_AXI_GP0_ARQOS; input [3:0] S_AXI_GP0_AWCACHE; input [3:0] S_AXI_GP0_AWLEN; input [3:0] S_AXI_GP0_AWQOS; input [3:0] S_AXI_GP0_WSTRB; input [5:0] S_AXI_GP0_ARID; input [5:0] S_AXI_GP0_AWID; input [5:0] S_AXI_GP0_WID; output S_AXI_GP1_ARREADY; output S_AXI_GP1_AWREADY; output S_AXI_GP1_BVALID; output S_AXI_GP1_RLAST; output S_AXI_GP1_RVALID; output S_AXI_GP1_WREADY; output [1:0] S_AXI_GP1_BRESP; output [1:0] S_AXI_GP1_RRESP; output [31:0] S_AXI_GP1_RDATA; output [5:0] S_AXI_GP1_BID; output [5:0] S_AXI_GP1_RID; input S_AXI_GP1_ACLK; input S_AXI_GP1_ARVALID; input S_AXI_GP1_AWVALID; input S_AXI_GP1_BREADY; input S_AXI_GP1_RREADY; input S_AXI_GP1_WLAST; input S_AXI_GP1_WVALID; input [1:0] S_AXI_GP1_ARBURST; input [1:0] S_AXI_GP1_ARLOCK; input [2:0] S_AXI_GP1_ARSIZE; input [1:0] S_AXI_GP1_AWBURST; input [1:0] S_AXI_GP1_AWLOCK; input [2:0] S_AXI_GP1_AWSIZE; input [2:0] S_AXI_GP1_ARPROT; input [2:0] S_AXI_GP1_AWPROT; input [31:0] S_AXI_GP1_ARADDR; input [31:0] S_AXI_GP1_AWADDR; input [31:0] S_AXI_GP1_WDATA; input [3:0] S_AXI_GP1_ARCACHE; input [3:0] S_AXI_GP1_ARLEN; input [3:0] S_AXI_GP1_ARQOS; input [3:0] S_AXI_GP1_AWCACHE; input [3:0] S_AXI_GP1_AWLEN; input [3:0] S_AXI_GP1_AWQOS; input [3:0] S_AXI_GP1_WSTRB; input [5:0] S_AXI_GP1_ARID; input [5:0] S_AXI_GP1_AWID; input [5:0] S_AXI_GP1_WID; output S_AXI_ACP_AWREADY; output S_AXI_ACP_ARREADY; output S_AXI_ACP_BVALID; output S_AXI_ACP_RLAST; output S_AXI_ACP_RVALID; output S_AXI_ACP_WREADY; output [1:0] S_AXI_ACP_BRESP; output [1:0] S_AXI_ACP_RRESP; output [2:0] S_AXI_ACP_BID; output [2:0] S_AXI_ACP_RID; output [63:0] S_AXI_ACP_RDATA; input S_AXI_ACP_ACLK; input S_AXI_ACP_ARVALID; input S_AXI_ACP_AWVALID; input S_AXI_ACP_BREADY; input S_AXI_ACP_RREADY; input S_AXI_ACP_WLAST; input S_AXI_ACP_WVALID; input [2:0] S_AXI_ACP_ARID; input [2:0] S_AXI_ACP_ARPROT; input [2:0] S_AXI_ACP_AWID; input [2:0] S_AXI_ACP_AWPROT; input [2:0] S_AXI_ACP_WID; input [31:0] S_AXI_ACP_ARADDR; input [31:0] S_AXI_ACP_AWADDR; input [3:0] S_AXI_ACP_ARCACHE; input [3:0] S_AXI_ACP_ARLEN; input [3:0] S_AXI_ACP_ARQOS; input [3:0] S_AXI_ACP_AWCACHE; input [3:0] S_AXI_ACP_AWLEN; input [3:0] S_AXI_ACP_AWQOS; input [1:0] S_AXI_ACP_ARBURST; input [1:0] S_AXI_ACP_ARLOCK; input [2:0] S_AXI_ACP_ARSIZE; input [1:0] S_AXI_ACP_AWBURST; input [1:0] S_AXI_ACP_AWLOCK; input [2:0] S_AXI_ACP_AWSIZE; input [4:0] S_AXI_ACP_ARUSER; input [4:0] S_AXI_ACP_AWUSER; input [63:0] S_AXI_ACP_WDATA; input [7:0] S_AXI_ACP_WSTRB; output S_AXI_HP0_ARREADY; output S_AXI_HP0_AWREADY; output S_AXI_HP0_BVALID; output S_AXI_HP0_RLAST; output S_AXI_HP0_RVALID; output S_AXI_HP0_WREADY; output [1:0] S_AXI_HP0_BRESP; output [1:0] S_AXI_HP0_RRESP; output [5:0] S_AXI_HP0_BID; output [5:0] S_AXI_HP0_RID; output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA; output [7:0] S_AXI_HP0_RCOUNT; output [7:0] S_AXI_HP0_WCOUNT; output [2:0] S_AXI_HP0_RACOUNT; output [5:0] S_AXI_HP0_WACOUNT; input S_AXI_HP0_ACLK; input S_AXI_HP0_ARVALID; input S_AXI_HP0_AWVALID; input S_AXI_HP0_BREADY; input S_AXI_HP0_RDISSUECAP1_EN; input S_AXI_HP0_RREADY; input S_AXI_HP0_WLAST; input S_AXI_HP0_WRISSUECAP1_EN; input S_AXI_HP0_WVALID; input [1:0] S_AXI_HP0_ARBURST; input [1:0] S_AXI_HP0_ARLOCK; input [2:0] S_AXI_HP0_ARSIZE; input [1:0] S_AXI_HP0_AWBURST; input [1:0] S_AXI_HP0_AWLOCK; input [2:0] S_AXI_HP0_AWSIZE; input [2:0] S_AXI_HP0_ARPROT; input [2:0] S_AXI_HP0_AWPROT; input [31:0] S_AXI_HP0_ARADDR; input [31:0] S_AXI_HP0_AWADDR; input [3:0] S_AXI_HP0_ARCACHE; input [3:0] S_AXI_HP0_ARLEN; input [3:0] S_AXI_HP0_ARQOS; input [3:0] S_AXI_HP0_AWCACHE; input [3:0] S_AXI_HP0_AWLEN; input [3:0] S_AXI_HP0_AWQOS; input [5:0] S_AXI_HP0_ARID; input [5:0] S_AXI_HP0_AWID; input [5:0] S_AXI_HP0_WID; input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA; input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB; output S_AXI_HP1_ARREADY; output S_AXI_HP1_AWREADY; output S_AXI_HP1_BVALID; output S_AXI_HP1_RLAST; output S_AXI_HP1_RVALID; output S_AXI_HP1_WREADY; output [1:0] S_AXI_HP1_BRESP; output [1:0] S_AXI_HP1_RRESP; output [5:0] S_AXI_HP1_BID; output [5:0] S_AXI_HP1_RID; output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA; output [7:0] S_AXI_HP1_RCOUNT; output [7:0] S_AXI_HP1_WCOUNT; output [2:0] S_AXI_HP1_RACOUNT; output [5:0] S_AXI_HP1_WACOUNT; input S_AXI_HP1_ACLK; input S_AXI_HP1_ARVALID; input S_AXI_HP1_AWVALID; input S_AXI_HP1_BREADY; input S_AXI_HP1_RDISSUECAP1_EN; input S_AXI_HP1_RREADY; input S_AXI_HP1_WLAST; input S_AXI_HP1_WRISSUECAP1_EN; input S_AXI_HP1_WVALID; input [1:0] S_AXI_HP1_ARBURST; input [1:0] S_AXI_HP1_ARLOCK; input [2:0] S_AXI_HP1_ARSIZE; input [1:0] S_AXI_HP1_AWBURST; input [1:0] S_AXI_HP1_AWLOCK; input [2:0] S_AXI_HP1_AWSIZE; input [2:0] S_AXI_HP1_ARPROT; input [2:0] S_AXI_HP1_AWPROT; input [31:0] S_AXI_HP1_ARADDR; input [31:0] S_AXI_HP1_AWADDR; input [3:0] S_AXI_HP1_ARCACHE; input [3:0] S_AXI_HP1_ARLEN; input [3:0] S_AXI_HP1_ARQOS; input [3:0] S_AXI_HP1_AWCACHE; input [3:0] S_AXI_HP1_AWLEN; input [3:0] S_AXI_HP1_AWQOS; input [5:0] S_AXI_HP1_ARID; input [5:0] S_AXI_HP1_AWID; input [5:0] S_AXI_HP1_WID; input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA; input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB; output S_AXI_HP2_ARREADY; output S_AXI_HP2_AWREADY; output S_AXI_HP2_BVALID; output S_AXI_HP2_RLAST; output S_AXI_HP2_RVALID; output S_AXI_HP2_WREADY; output [1:0] S_AXI_HP2_BRESP; output [1:0] S_AXI_HP2_RRESP; output [5:0] S_AXI_HP2_BID; output [5:0] S_AXI_HP2_RID; output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA; output [7:0] S_AXI_HP2_RCOUNT; output [7:0] S_AXI_HP2_WCOUNT; output [2:0] S_AXI_HP2_RACOUNT; output [5:0] S_AXI_HP2_WACOUNT; input S_AXI_HP2_ACLK; input S_AXI_HP2_ARVALID; input S_AXI_HP2_AWVALID; input S_AXI_HP2_BREADY; input S_AXI_HP2_RDISSUECAP1_EN; input S_AXI_HP2_RREADY; input S_AXI_HP2_WLAST; input S_AXI_HP2_WRISSUECAP1_EN; input S_AXI_HP2_WVALID; input [1:0] S_AXI_HP2_ARBURST; input [1:0] S_AXI_HP2_ARLOCK; input [2:0] S_AXI_HP2_ARSIZE; input [1:0] S_AXI_HP2_AWBURST; input [1:0] S_AXI_HP2_AWLOCK; input [2:0] S_AXI_HP2_AWSIZE; input [2:0] S_AXI_HP2_ARPROT; input [2:0] S_AXI_HP2_AWPROT; input [31:0] S_AXI_HP2_ARADDR; input [31:0] S_AXI_HP2_AWADDR; input [3:0] S_AXI_HP2_ARCACHE; input [3:0] S_AXI_HP2_ARLEN; input [3:0] S_AXI_HP2_ARQOS; input [3:0] S_AXI_HP2_AWCACHE; input [3:0] S_AXI_HP2_AWLEN; input [3:0] S_AXI_HP2_AWQOS; input [5:0] S_AXI_HP2_ARID; input [5:0] S_AXI_HP2_AWID; input [5:0] S_AXI_HP2_WID; input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA; input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB; output S_AXI_HP3_ARREADY; output S_AXI_HP3_AWREADY; output S_AXI_HP3_BVALID; output S_AXI_HP3_RLAST; output S_AXI_HP3_RVALID; output S_AXI_HP3_WREADY; output [1:0] S_AXI_HP3_BRESP; output [1:0] S_AXI_HP3_RRESP; output [5:0] S_AXI_HP3_BID; output [5:0] S_AXI_HP3_RID; output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA; output [7:0] S_AXI_HP3_RCOUNT; output [7:0] S_AXI_HP3_WCOUNT; output [2:0] S_AXI_HP3_RACOUNT; output [5:0] S_AXI_HP3_WACOUNT; input S_AXI_HP3_ACLK; input S_AXI_HP3_ARVALID; input S_AXI_HP3_AWVALID; input S_AXI_HP3_BREADY; input S_AXI_HP3_RDISSUECAP1_EN; input S_AXI_HP3_RREADY; input S_AXI_HP3_WLAST; input S_AXI_HP3_WRISSUECAP1_EN; input S_AXI_HP3_WVALID; input [1:0] S_AXI_HP3_ARBURST; input [1:0] S_AXI_HP3_ARLOCK; input [2:0] S_AXI_HP3_ARSIZE; input [1:0] S_AXI_HP3_AWBURST; input [1:0] S_AXI_HP3_AWLOCK; input [2:0] S_AXI_HP3_AWSIZE; input [2:0] S_AXI_HP3_ARPROT; input [2:0] S_AXI_HP3_AWPROT; input [31:0] S_AXI_HP3_ARADDR; input [31:0] S_AXI_HP3_AWADDR; input [3:0] S_AXI_HP3_ARCACHE; input [3:0] S_AXI_HP3_ARLEN; input [3:0] S_AXI_HP3_ARQOS; input [3:0] S_AXI_HP3_AWCACHE; input [3:0] S_AXI_HP3_AWLEN; input [3:0] S_AXI_HP3_AWQOS; input [5:0] S_AXI_HP3_ARID; input [5:0] S_AXI_HP3_AWID; input [5:0] S_AXI_HP3_WID; input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA; input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB; output [1:0] DMA0_DATYPE; output DMA0_DAVALID; output DMA0_DRREADY; input DMA0_ACLK; input DMA0_DAREADY; input DMA0_DRLAST; input DMA0_DRVALID; input [1:0] DMA0_DRTYPE; output [1:0] DMA1_DATYPE; output DMA1_DAVALID; output DMA1_DRREADY; input DMA1_ACLK; input DMA1_DAREADY; input DMA1_DRLAST; input DMA1_DRVALID; input [1:0] DMA1_DRTYPE; output [1:0] DMA2_DATYPE; output DMA2_DAVALID; output DMA2_DRREADY; input DMA2_ACLK; input DMA2_DAREADY; input DMA2_DRLAST; input DMA2_DRVALID; input DMA3_DRVALID; output [1:0] DMA3_DATYPE; output DMA3_DAVALID; output DMA3_DRREADY; input DMA3_ACLK; input DMA3_DAREADY; input DMA3_DRLAST; input [1:0] DMA2_DRTYPE; input [1:0] DMA3_DRTYPE; input [31:0] FTMD_TRACEIN_DATA; input FTMD_TRACEIN_VALID; input FTMD_TRACEIN_CLK; input [3:0] FTMD_TRACEIN_ATID; input [3:0] FTMT_F2P_TRIG; output [3:0] FTMT_F2P_TRIGACK; input [31:0] FTMT_F2P_DEBUG; input [3:0] FTMT_P2F_TRIGACK; output [3:0] FTMT_P2F_TRIG; output [31:0] FTMT_P2F_DEBUG; output FCLK_CLK3; output FCLK_CLK2; output FCLK_CLK1; output FCLK_CLK0; input FCLK_CLKTRIG3_N; input FCLK_CLKTRIG2_N; input FCLK_CLKTRIG1_N; input FCLK_CLKTRIG0_N; output FCLK_RESET3_N; output FCLK_RESET2_N; output FCLK_RESET1_N; output FCLK_RESET0_N; input FPGA_IDLE_N; input [3:0] DDR_ARB; input [irq_width-1:0] IRQ_F2P; input Core0_nFIQ; input Core0_nIRQ; input Core1_nFIQ; input Core1_nIRQ; output EVENT_EVENTO; output [1:0] EVENT_STANDBYWFE; output [1:0] EVENT_STANDBYWFI; input EVENT_EVENTI; inout [53:0] MIO; inout DDR_Clk; inout DDR_Clk_n; inout DDR_CKE; inout DDR_CS_n; inout DDR_RAS_n; inout DDR_CAS_n; output DDR_WEB; inout [2:0] DDR_BankAddr; inout [14:0] DDR_Addr; inout DDR_ODT; inout DDR_DRSTB; inout [31:0] DDR_DQ; inout [3:0] DDR_DM; inout [3:0] DDR_DQS; inout [3:0] DDR_DQS_n; inout DDR_VRN; inout DDR_VRP; /* Reset Input & Clock Input */ input PS_SRSTB; input PS_CLK; input PS_PORB; output IRQ_P2F_DMAC_ABORT; output IRQ_P2F_DMAC0; output IRQ_P2F_DMAC1; output IRQ_P2F_DMAC2; output IRQ_P2F_DMAC3; output IRQ_P2F_DMAC4; output IRQ_P2F_DMAC5; output IRQ_P2F_DMAC6; output IRQ_P2F_DMAC7; output IRQ_P2F_SMC; output IRQ_P2F_QSPI; output IRQ_P2F_CTI; output IRQ_P2F_GPIO; output IRQ_P2F_USB0; output IRQ_P2F_ENET0; output IRQ_P2F_ENET_WAKE0; output IRQ_P2F_SDIO0; output IRQ_P2F_I2C0; output IRQ_P2F_SPI0; output IRQ_P2F_UART0; output IRQ_P2F_CAN0; output IRQ_P2F_USB1; output IRQ_P2F_ENET1; output IRQ_P2F_ENET_WAKE1; output IRQ_P2F_SDIO1; output IRQ_P2F_I2C1; output IRQ_P2F_SPI1; output IRQ_P2F_UART1; output IRQ_P2F_CAN1; /* Internal wires/nets used for connectivity */ wire net_rstn; wire net_sw_clk; wire net_ocm_clk; wire net_arbiter_clk; wire net_axi_mgp0_rstn; wire net_axi_mgp1_rstn; wire net_axi_gp0_rstn; wire net_axi_gp1_rstn; wire net_axi_hp0_rstn; wire net_axi_hp1_rstn; wire net_axi_hp2_rstn; wire net_axi_hp3_rstn; wire net_axi_acp_rstn; wire [4:0] net_axi_acp_awuser; wire [4:0] net_axi_acp_aruser; /* Dummy */ assign net_axi_acp_awuser = S_AXI_ACP_AWUSER; assign net_axi_acp_aruser = S_AXI_ACP_ARUSER; /* Global variables */ reg DEBUG_INFO = 1; reg STOP_ON_ERROR = 1; /* local variable acting as semaphore for wait_mem_update and wait_reg_update task */ reg mem_update_key = 1; reg reg_update_key_0 = 1; reg reg_update_key_1 = 1; /* assignments and semantic checks for unused ports */ `include "processing_system7_bfm_v2_0_5_unused_ports.v" /* include api definition */ `include "processing_system7_bfm_v2_0_5_apis.v" /* Reset Generator */ processing_system7_bfm_v2_0_5_gen_reset gen_rst(.por_rst_n(PS_PORB), .sys_rst_n(PS_SRSTB), .rst_out_n(net_rstn), .m_axi_gp0_clk(M_AXI_GP0_ACLK), .m_axi_gp1_clk(M_AXI_GP1_ACLK), .s_axi_gp0_clk(S_AXI_GP0_ACLK), .s_axi_gp1_clk(S_AXI_GP1_ACLK), .s_axi_hp0_clk(S_AXI_HP0_ACLK), .s_axi_hp1_clk(S_AXI_HP1_ACLK), .s_axi_hp2_clk(S_AXI_HP2_ACLK), .s_axi_hp3_clk(S_AXI_HP3_ACLK), .s_axi_acp_clk(S_AXI_ACP_ACLK), .m_axi_gp0_rstn(net_axi_mgp0_rstn), .m_axi_gp1_rstn(net_axi_mgp1_rstn), .s_axi_gp0_rstn(net_axi_gp0_rstn), .s_axi_gp1_rstn(net_axi_gp1_rstn), .s_axi_hp0_rstn(net_axi_hp0_rstn), .s_axi_hp1_rstn(net_axi_hp1_rstn), .s_axi_hp2_rstn(net_axi_hp2_rstn), .s_axi_hp3_rstn(net_axi_hp3_rstn), .s_axi_acp_rstn(net_axi_acp_rstn), .fclk_reset3_n(FCLK_RESET3_N), .fclk_reset2_n(FCLK_RESET2_N), .fclk_reset1_n(FCLK_RESET1_N), .fclk_reset0_n(FCLK_RESET0_N), .fpga_acp_reset_n(), ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP) .fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN), .fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN), .fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN), .fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN), .fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN), .fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN), .fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN), .fpga_hp_s3_reset_n() ////S_AXI_HP3_ARESETN) ); /* Clock Generator */ processing_system7_bfm_v2_0_5_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ) gen_clk(.ps_clk(PS_CLK), .sw_clk(net_sw_clk), .fclk_clk3(FCLK_CLK3), .fclk_clk2(FCLK_CLK2), .fclk_clk1(FCLK_CLK1), .fclk_clk0(FCLK_CLK0) ); wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1; wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1; wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1; wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1; wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1; wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1; wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1; wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1; wire net_rd_req_reg_gp0, net_rd_req_reg_gp1; wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1; wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1; wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1; wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1; wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1; wire net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1; wire net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1; wire net_rd_dv_reg_gp0, net_rd_dv_reg_gp1; wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1; wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3; wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3; wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3; wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3; wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3; wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3; wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3; wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3; wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3; wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3; wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3; wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3; wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3; wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3; wire net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3; wire net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3; wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3; wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp; wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp; wire [max_burst_bits-1:0] net_wr_data_acp; wire [addr_width-1:0] net_wr_addr_acp; wire [max_burst_bytes_width:0] net_wr_bytes_acp; wire [axi_qos_width-1:0] net_wr_qos_acp; wire net_rd_req_ddr_acp, net_rd_req_ocm_acp; wire [addr_width-1:0] net_rd_addr_acp; wire [max_burst_bytes_width:0] net_rd_bytes_acp; wire [max_burst_bits-1:0] net_rd_data_ddr_acp; wire [max_burst_bits-1:0] net_rd_data_ocm_acp; wire net_rd_dv_ddr_acp,net_rd_dv_ocm_acp; wire [axi_qos_width-1:0] net_rd_qos_acp; wire ocm_wr_ack_port0; wire ocm_wr_dv_port0; wire ocm_rd_req_port0; wire ocm_rd_dv_port0; wire [addr_width-1:0] ocm_wr_addr_port0; wire [max_burst_bits-1:0] ocm_wr_data_port0; wire [max_burst_bytes_width:0] ocm_wr_bytes_port0; wire [addr_width-1:0] ocm_rd_addr_port0; wire [max_burst_bits-1:0] ocm_rd_data_port0; wire [max_burst_bytes_width:0] ocm_rd_bytes_port0; wire [axi_qos_width-1:0] ocm_wr_qos_port0; wire [axi_qos_width-1:0] ocm_rd_qos_port0; wire ocm_wr_ack_port1; wire ocm_wr_dv_port1; wire ocm_rd_req_port1; wire ocm_rd_dv_port1; wire [addr_width-1:0] ocm_wr_addr_port1; wire [max_burst_bits-1:0] ocm_wr_data_port1; wire [max_burst_bytes_width:0] ocm_wr_bytes_port1; wire [addr_width-1:0] ocm_rd_addr_port1; wire [max_burst_bits-1:0] ocm_rd_data_port1; wire [max_burst_bytes_width:0] ocm_rd_bytes_port1; wire [axi_qos_width-1:0] ocm_wr_qos_port1; wire [axi_qos_width-1:0] ocm_rd_qos_port1; wire ddr_wr_ack_port0; wire ddr_wr_dv_port0; wire ddr_rd_req_port0; wire ddr_rd_dv_port0; wire[addr_width-1:0] ddr_wr_addr_port0; wire[max_burst_bits-1:0] ddr_wr_data_port0; wire[max_burst_bytes_width:0] ddr_wr_bytes_port0; wire[addr_width-1:0] ddr_rd_addr_port0; wire[max_burst_bits-1:0] ddr_rd_data_port0; wire[max_burst_bytes_width:0] ddr_rd_bytes_port0; wire [axi_qos_width-1:0] ddr_wr_qos_port0; wire [axi_qos_width-1:0] ddr_rd_qos_port0; wire ddr_wr_ack_port1; wire ddr_wr_dv_port1; wire ddr_rd_req_port1; wire ddr_rd_dv_port1; wire[addr_width-1:0] ddr_wr_addr_port1; wire[max_burst_bits-1:0] ddr_wr_data_port1; wire[max_burst_bytes_width:0] ddr_wr_bytes_port1; wire[addr_width-1:0] ddr_rd_addr_port1; wire[max_burst_bits-1:0] ddr_rd_data_port1; wire[max_burst_bytes_width:0] ddr_rd_bytes_port1; wire[axi_qos_width-1:0] ddr_wr_qos_port1; wire[axi_qos_width-1:0] ddr_rd_qos_port1; wire ddr_wr_ack_port2; wire ddr_wr_dv_port2; wire ddr_rd_req_port2; wire ddr_rd_dv_port2; wire[addr_width-1:0] ddr_wr_addr_port2; wire[max_burst_bits-1:0] ddr_wr_data_port2; wire[max_burst_bytes_width:0] ddr_wr_bytes_port2; wire[addr_width-1:0] ddr_rd_addr_port2; wire[max_burst_bits-1:0] ddr_rd_data_port2; wire[max_burst_bytes_width:0] ddr_rd_bytes_port2; wire[axi_qos_width-1:0] ddr_wr_qos_port2; wire[axi_qos_width-1:0] ddr_rd_qos_port2; wire ddr_wr_ack_port3; wire ddr_wr_dv_port3; wire ddr_rd_req_port3; wire ddr_rd_dv_port3; wire[addr_width-1:0] ddr_wr_addr_port3; wire[max_burst_bits-1:0] ddr_wr_data_port3; wire[max_burst_bytes_width:0] ddr_wr_bytes_port3; wire[addr_width-1:0] ddr_rd_addr_port3; wire[max_burst_bits-1:0] ddr_rd_data_port3; wire[max_burst_bytes_width:0] ddr_rd_bytes_port3; wire[axi_qos_width-1:0] ddr_wr_qos_port3; wire[axi_qos_width-1:0] ddr_rd_qos_port3; wire reg_rd_req_port0; wire reg_rd_dv_port0; wire[addr_width-1:0] reg_rd_addr_port0; wire[max_burst_bits-1:0] reg_rd_data_port0; wire[max_burst_bytes_width:0] reg_rd_bytes_port0; wire [axi_qos_width-1:0] reg_rd_qos_port0; wire reg_rd_req_port1; wire reg_rd_dv_port1; wire[addr_width-1:0] reg_rd_addr_port1; wire[max_burst_bits-1:0] reg_rd_data_port1; wire[max_burst_bytes_width:0] reg_rd_bytes_port1; wire [axi_qos_width-1:0] reg_rd_qos_port1; wire [11:0] M_AXI_GP0_AWID_FULL; wire [11:0] M_AXI_GP0_WID_FULL; wire [11:0] M_AXI_GP0_ARID_FULL; wire [11:0] M_AXI_GP0_BID_FULL; wire [11:0] M_AXI_GP0_RID_FULL; wire [11:0] M_AXI_GP1_AWID_FULL; wire [11:0] M_AXI_GP1_WID_FULL; wire [11:0] M_AXI_GP1_ARID_FULL; wire [11:0] M_AXI_GP1_BID_FULL; wire [11:0] M_AXI_GP1_RID_FULL; function [5:0] compress_id; input [11:0] id; begin compress_id = id[5:0]; end endfunction function [11:0] uncompress_id; input [5:0] id; begin uncompress_id = {6'b110000, id[5:0]}; end endfunction assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL; assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL; assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL; assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID; assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID; assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL; assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL; assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL; assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID; assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID; processing_system7_bfm_v2_0_5_interconnect_model icm ( .rstn(net_rstn), .sw_clk(net_sw_clk), .w_qos_gp0(net_wr_qos_gp0), .w_qos_gp1(net_wr_qos_gp1), .w_qos_hp0(net_wr_qos_hp0), .w_qos_hp1(net_wr_qos_hp1), .w_qos_hp2(net_wr_qos_hp2), .w_qos_hp3(net_wr_qos_hp3), .r_qos_gp0(net_rd_qos_gp0), .r_qos_gp1(net_rd_qos_gp1), .r_qos_hp0(net_rd_qos_hp0), .r_qos_hp1(net_rd_qos_hp1), .r_qos_hp2(net_rd_qos_hp2), .r_qos_hp3(net_rd_qos_hp3), /* GP Slave ports access */ .wr_ack_ddr_gp0(net_wr_ack_ddr_gp0), .wr_ack_ocm_gp0(net_wr_ack_ocm_gp0), .wr_data_gp0(net_wr_data_gp0), .wr_addr_gp0(net_wr_addr_gp0), .wr_bytes_gp0(net_wr_bytes_gp0), .wr_dv_ddr_gp0(net_wr_dv_ddr_gp0), .wr_dv_ocm_gp0(net_wr_dv_ocm_gp0), .rd_req_ddr_gp0(net_rd_req_ddr_gp0), .rd_req_ocm_gp0(net_rd_req_ocm_gp0), .rd_req_reg_gp0(net_rd_req_reg_gp0), .rd_addr_gp0(net_rd_addr_gp0), .rd_bytes_gp0(net_rd_bytes_gp0), .rd_data_ddr_gp0(net_rd_data_ddr_gp0), .rd_data_ocm_gp0(net_rd_data_ocm_gp0), .rd_data_reg_gp0(net_rd_data_reg_gp0), .rd_dv_ddr_gp0(net_rd_dv_ddr_gp0), .rd_dv_ocm_gp0(net_rd_dv_ocm_gp0), .rd_dv_reg_gp0(net_rd_dv_reg_gp0), .wr_ack_ddr_gp1(net_wr_ack_ddr_gp1), .wr_ack_ocm_gp1(net_wr_ack_ocm_gp1), .wr_data_gp1(net_wr_data_gp1), .wr_addr_gp1(net_wr_addr_gp1), .wr_bytes_gp1(net_wr_bytes_gp1), .wr_dv_ddr_gp1(net_wr_dv_ddr_gp1), .wr_dv_ocm_gp1(net_wr_dv_ocm_gp1), .rd_req_ddr_gp1(net_rd_req_ddr_gp1), .rd_req_ocm_gp1(net_rd_req_ocm_gp1), .rd_req_reg_gp1(net_rd_req_reg_gp1), .rd_addr_gp1(net_rd_addr_gp1), .rd_bytes_gp1(net_rd_bytes_gp1), .rd_data_ddr_gp1(net_rd_data_ddr_gp1), .rd_data_ocm_gp1(net_rd_data_ocm_gp1), .rd_data_reg_gp1(net_rd_data_reg_gp1), .rd_dv_ddr_gp1(net_rd_dv_ddr_gp1), .rd_dv_ocm_gp1(net_rd_dv_ocm_gp1), .rd_dv_reg_gp1(net_rd_dv_reg_gp1), /* HP Slave ports access */ .wr_ack_ddr_hp0(net_wr_ack_ddr_hp0), .wr_ack_ocm_hp0(net_wr_ack_ocm_hp0), .wr_data_hp0(net_wr_data_hp0), .wr_addr_hp0(net_wr_addr_hp0), .wr_bytes_hp0(net_wr_bytes_hp0), .wr_dv_ddr_hp0(net_wr_dv_ddr_hp0), .wr_dv_ocm_hp0(net_wr_dv_ocm_hp0), .rd_req_ddr_hp0(net_rd_req_ddr_hp0), .rd_req_ocm_hp0(net_rd_req_ocm_hp0), .rd_addr_hp0(net_rd_addr_hp0), .rd_bytes_hp0(net_rd_bytes_hp0), .rd_data_ddr_hp0(net_rd_data_ddr_hp0), .rd_data_ocm_hp0(net_rd_data_ocm_hp0), .rd_dv_ddr_hp0(net_rd_dv_ddr_hp0), .rd_dv_ocm_hp0(net_rd_dv_ocm_hp0), .wr_ack_ddr_hp1(net_wr_ack_ddr_hp1), .wr_ack_ocm_hp1(net_wr_ack_ocm_hp1), .wr_data_hp1(net_wr_data_hp1), .wr_addr_hp1(net_wr_addr_hp1), .wr_bytes_hp1(net_wr_bytes_hp1), .wr_dv_ddr_hp1(net_wr_dv_ddr_hp1), .wr_dv_ocm_hp1(net_wr_dv_ocm_hp1), .rd_req_ddr_hp1(net_rd_req_ddr_hp1), .rd_req_ocm_hp1(net_rd_req_ocm_hp1), .rd_addr_hp1(net_rd_addr_hp1), .rd_bytes_hp1(net_rd_bytes_hp1), .rd_data_ddr_hp1(net_rd_data_ddr_hp1), .rd_data_ocm_hp1(net_rd_data_ocm_hp1), .rd_dv_ocm_hp1(net_rd_dv_ocm_hp1), .rd_dv_ddr_hp1(net_rd_dv_ddr_hp1), .wr_ack_ddr_hp2(net_wr_ack_ddr_hp2), .wr_ack_ocm_hp2(net_wr_ack_ocm_hp2), .wr_data_hp2(net_wr_data_hp2), .wr_addr_hp2(net_wr_addr_hp2), .wr_bytes_hp2(net_wr_bytes_hp2), .wr_dv_ocm_hp2(net_wr_dv_ocm_hp2), .wr_dv_ddr_hp2(net_wr_dv_ddr_hp2), .rd_req_ddr_hp2(net_rd_req_ddr_hp2), .rd_req_ocm_hp2(net_rd_req_ocm_hp2), .rd_addr_hp2(net_rd_addr_hp2), .rd_bytes_hp2(net_rd_bytes_hp2), .rd_data_ddr_hp2(net_rd_data_ddr_hp2), .rd_data_ocm_hp2(net_rd_data_ocm_hp2), .rd_dv_ddr_hp2(net_rd_dv_ddr_hp2), .rd_dv_ocm_hp2(net_rd_dv_ocm_hp2), .wr_ack_ocm_hp3(net_wr_ack_ocm_hp3), .wr_ack_ddr_hp3(net_wr_ack_ddr_hp3), .wr_data_hp3(net_wr_data_hp3), .wr_addr_hp3(net_wr_addr_hp3), .wr_bytes_hp3(net_wr_bytes_hp3), .wr_dv_ddr_hp3(net_wr_dv_ddr_hp3), .wr_dv_ocm_hp3(net_wr_dv_ocm_hp3), .rd_req_ddr_hp3(net_rd_req_ddr_hp3), .rd_req_ocm_hp3(net_rd_req_ocm_hp3), .rd_addr_hp3(net_rd_addr_hp3), .rd_bytes_hp3(net_rd_bytes_hp3), .rd_data_ddr_hp3(net_rd_data_ddr_hp3), .rd_data_ocm_hp3(net_rd_data_ocm_hp3), .rd_dv_ddr_hp3(net_rd_dv_ddr_hp3), .rd_dv_ocm_hp3(net_rd_dv_ocm_hp3), /* Goes to port 1 of DDR */ .ddr_wr_ack_port1(ddr_wr_ack_port1), .ddr_wr_dv_port1(ddr_wr_dv_port1), .ddr_rd_req_port1(ddr_rd_req_port1), .ddr_rd_dv_port1 (ddr_rd_dv_port1), .ddr_wr_addr_port1(ddr_wr_addr_port1), .ddr_wr_data_port1(ddr_wr_data_port1), .ddr_wr_bytes_port1(ddr_wr_bytes_port1), .ddr_rd_addr_port1(ddr_rd_addr_port1), .ddr_rd_data_port1(ddr_rd_data_port1), .ddr_rd_bytes_port1(ddr_rd_bytes_port1), .ddr_wr_qos_port1(ddr_wr_qos_port1), .ddr_rd_qos_port1(ddr_rd_qos_port1), /* Goes to port2 of DDR */ .ddr_wr_ack_port2 (ddr_wr_ack_port2), .ddr_wr_dv_port2 (ddr_wr_dv_port2), .ddr_rd_req_port2 (ddr_rd_req_port2), .ddr_rd_dv_port2 (ddr_rd_dv_port2), .ddr_wr_addr_port2(ddr_wr_addr_port2), .ddr_wr_data_port2(ddr_wr_data_port2), .ddr_wr_bytes_port2(ddr_wr_bytes_port2), .ddr_rd_addr_port2(ddr_rd_addr_port2), .ddr_rd_data_port2(ddr_rd_data_port2), .ddr_rd_bytes_port2(ddr_rd_bytes_port2), .ddr_wr_qos_port2 (ddr_wr_qos_port2), .ddr_rd_qos_port2 (ddr_rd_qos_port2), /* Goes to port3 of DDR */ .ddr_wr_ack_port3 (ddr_wr_ack_port3), .ddr_wr_dv_port3 (ddr_wr_dv_port3), .ddr_rd_req_port3 (ddr_rd_req_port3), .ddr_rd_dv_port3 (ddr_rd_dv_port3), .ddr_wr_addr_port3(ddr_wr_addr_port3), .ddr_wr_data_port3(ddr_wr_data_port3), .ddr_wr_bytes_port3(ddr_wr_bytes_port3), .ddr_rd_addr_port3(ddr_rd_addr_port3), .ddr_rd_data_port3(ddr_rd_data_port3), .ddr_rd_bytes_port3(ddr_rd_bytes_port3), .ddr_wr_qos_port3 (ddr_wr_qos_port3), .ddr_rd_qos_port3 (ddr_rd_qos_port3), /* Goes to port 0 of OCM */ .ocm_wr_ack_port1 (ocm_wr_ack_port1), .ocm_wr_dv_port1 (ocm_wr_dv_port1), .ocm_rd_req_port1 (ocm_rd_req_port1), .ocm_rd_dv_port1 (ocm_rd_dv_port1), .ocm_wr_addr_port1(ocm_wr_addr_port1), .ocm_wr_data_port1(ocm_wr_data_port1), .ocm_wr_bytes_port1(ocm_wr_bytes_port1), .ocm_rd_addr_port1(ocm_rd_addr_port1), .ocm_rd_data_port1(ocm_rd_data_port1), .ocm_rd_bytes_port1(ocm_rd_bytes_port1), .ocm_wr_qos_port1(ocm_wr_qos_port1), .ocm_rd_qos_port1(ocm_rd_qos_port1), /* Goes to port 0 of REG */ .reg_rd_qos_port1 (reg_rd_qos_port1) , .reg_rd_req_port1 (reg_rd_req_port1), .reg_rd_dv_port1 (reg_rd_dv_port1), .reg_rd_addr_port1(reg_rd_addr_port1), .reg_rd_data_port1(reg_rd_data_port1), .reg_rd_bytes_port1(reg_rd_bytes_port1) ); processing_system7_bfm_v2_0_5_ddrc ddrc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of DDR */ .ddr_wr_ack_port0 (ddr_wr_ack_port0), .ddr_wr_dv_port0 (ddr_wr_dv_port0), .ddr_rd_req_port0 (ddr_rd_req_port0), .ddr_rd_dv_port0 (ddr_rd_dv_port0), .ddr_wr_addr_port0(net_wr_addr_acp), .ddr_wr_data_port0(net_wr_data_acp), .ddr_wr_bytes_port0(net_wr_bytes_acp), .ddr_rd_addr_port0(net_rd_addr_acp), .ddr_rd_bytes_port0(net_rd_bytes_acp), .ddr_rd_data_port0(ddr_rd_data_port0), .ddr_wr_qos_port0 (net_wr_qos_acp), .ddr_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of DDR */ .ddr_wr_ack_port1 (ddr_wr_ack_port1), .ddr_wr_dv_port1 (ddr_wr_dv_port1), .ddr_rd_req_port1 (ddr_rd_req_port1), .ddr_rd_dv_port1 (ddr_rd_dv_port1), .ddr_wr_addr_port1(ddr_wr_addr_port1), .ddr_wr_data_port1(ddr_wr_data_port1), .ddr_wr_bytes_port1(ddr_wr_bytes_port1), .ddr_rd_addr_port1(ddr_rd_addr_port1), .ddr_rd_data_port1(ddr_rd_data_port1), .ddr_rd_bytes_port1(ddr_rd_bytes_port1), .ddr_wr_qos_port1 (ddr_wr_qos_port1), .ddr_rd_qos_port1 (ddr_rd_qos_port1), /* Goes to port2 of DDR */ .ddr_wr_ack_port2 (ddr_wr_ack_port2), .ddr_wr_dv_port2 (ddr_wr_dv_port2), .ddr_rd_req_port2 (ddr_rd_req_port2), .ddr_rd_dv_port2 (ddr_rd_dv_port2), .ddr_wr_addr_port2(ddr_wr_addr_port2), .ddr_wr_data_port2(ddr_wr_data_port2), .ddr_wr_bytes_port2(ddr_wr_bytes_port2), .ddr_rd_addr_port2(ddr_rd_addr_port2), .ddr_rd_data_port2(ddr_rd_data_port2), .ddr_rd_bytes_port2(ddr_rd_bytes_port2), .ddr_wr_qos_port2 (ddr_wr_qos_port2), .ddr_rd_qos_port2 (ddr_rd_qos_port2), /* Goes to port3 of DDR */ .ddr_wr_ack_port3 (ddr_wr_ack_port3), .ddr_wr_dv_port3 (ddr_wr_dv_port3), .ddr_rd_req_port3 (ddr_rd_req_port3), .ddr_rd_dv_port3 (ddr_rd_dv_port3), .ddr_wr_addr_port3(ddr_wr_addr_port3), .ddr_wr_data_port3(ddr_wr_data_port3), .ddr_wr_bytes_port3(ddr_wr_bytes_port3), .ddr_rd_addr_port3(ddr_rd_addr_port3), .ddr_rd_data_port3(ddr_rd_data_port3), .ddr_rd_bytes_port3(ddr_rd_bytes_port3), .ddr_wr_qos_port3 (ddr_wr_qos_port3), .ddr_rd_qos_port3 (ddr_rd_qos_port3) ); processing_system7_bfm_v2_0_5_ocmc ocmc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of OCM */ .ocm_wr_ack_port0 (ocm_wr_ack_port0), .ocm_wr_dv_port0 (ocm_wr_dv_port0), .ocm_rd_req_port0 (ocm_rd_req_port0), .ocm_rd_dv_port0 (ocm_rd_dv_port0), .ocm_wr_addr_port0(net_wr_addr_acp), .ocm_wr_data_port0(net_wr_data_acp), .ocm_wr_bytes_port0(net_wr_bytes_acp), .ocm_rd_addr_port0(net_rd_addr_acp), .ocm_rd_bytes_port0(net_rd_bytes_acp), .ocm_rd_data_port0(ocm_rd_data_port0), .ocm_wr_qos_port0 (net_wr_qos_acp), .ocm_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of OCM */ .ocm_wr_ack_port1 (ocm_wr_ack_port1), .ocm_wr_dv_port1 (ocm_wr_dv_port1), .ocm_rd_req_port1 (ocm_rd_req_port1), .ocm_rd_dv_port1 (ocm_rd_dv_port1), .ocm_wr_addr_port1(ocm_wr_addr_port1), .ocm_wr_data_port1(ocm_wr_data_port1), .ocm_wr_bytes_port1(ocm_wr_bytes_port1), .ocm_rd_addr_port1(ocm_rd_addr_port1), .ocm_rd_data_port1(ocm_rd_data_port1), .ocm_rd_bytes_port1(ocm_rd_bytes_port1), .ocm_wr_qos_port1(ocm_wr_qos_port1), .ocm_rd_qos_port1(ocm_rd_qos_port1) ); processing_system7_bfm_v2_0_5_regc regc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of REG */ .reg_rd_req_port0 (reg_rd_req_port0), .reg_rd_dv_port0 (reg_rd_dv_port0), .reg_rd_addr_port0(net_rd_addr_acp), .reg_rd_bytes_port0(net_rd_bytes_acp), .reg_rd_data_port0(reg_rd_data_port0), .reg_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of REG */ .reg_rd_req_port1 (reg_rd_req_port1), .reg_rd_dv_port1 (reg_rd_dv_port1), .reg_rd_addr_port1(reg_rd_addr_port1), .reg_rd_data_port1(reg_rd_data_port1), .reg_rd_bytes_port1(reg_rd_bytes_port1), .reg_rd_qos_port1(reg_rd_qos_port1) ); /* include axi_gp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_gp.v" /* include axi_hp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_hp.v" /* include axi_acp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_acp.v" endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_processing_system7_bfm.v * * Date : 2012-11 * * Description : Processing_system7_bfm Top (zynq_bfm top) * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_processing_system7_bfm ( CAN0_PHY_TX, CAN0_PHY_RX, CAN1_PHY_TX, CAN1_PHY_RX, ENET0_GMII_TX_EN, ENET0_GMII_TX_ER, ENET0_MDIO_MDC, ENET0_MDIO_O, ENET0_MDIO_T, ENET0_PTP_DELAY_REQ_RX, ENET0_PTP_DELAY_REQ_TX, ENET0_PTP_PDELAY_REQ_RX, ENET0_PTP_PDELAY_REQ_TX, ENET0_PTP_PDELAY_RESP_RX, ENET0_PTP_PDELAY_RESP_TX, ENET0_PTP_SYNC_FRAME_RX, ENET0_PTP_SYNC_FRAME_TX, ENET0_SOF_RX, ENET0_SOF_TX, ENET0_GMII_TXD, ENET0_GMII_COL, ENET0_GMII_CRS, ENET0_EXT_INTIN, ENET0_GMII_RX_CLK, ENET0_GMII_RX_DV, ENET0_GMII_RX_ER, ENET0_GMII_TX_CLK, ENET0_MDIO_I, ENET0_GMII_RXD, ENET1_GMII_TX_EN, ENET1_GMII_TX_ER, ENET1_MDIO_MDC, ENET1_MDIO_O, ENET1_MDIO_T, ENET1_PTP_DELAY_REQ_RX, ENET1_PTP_DELAY_REQ_TX, ENET1_PTP_PDELAY_REQ_RX, ENET1_PTP_PDELAY_REQ_TX, ENET1_PTP_PDELAY_RESP_RX, ENET1_PTP_PDELAY_RESP_TX, ENET1_PTP_SYNC_FRAME_RX, ENET1_PTP_SYNC_FRAME_TX, ENET1_SOF_RX, ENET1_SOF_TX, ENET1_GMII_TXD, ENET1_GMII_COL, ENET1_GMII_CRS, ENET1_EXT_INTIN, ENET1_GMII_RX_CLK, ENET1_GMII_RX_DV, ENET1_GMII_RX_ER, ENET1_GMII_TX_CLK, ENET1_MDIO_I, ENET1_GMII_RXD, GPIO_I, GPIO_O, GPIO_T, I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I, I2C0_SCL_O, I2C0_SCL_T, I2C1_SDA_I, I2C1_SDA_O, I2C1_SDA_T, I2C1_SCL_I, I2C1_SCL_O, I2C1_SCL_T, PJTAG_TCK, PJTAG_TMS, PJTAG_TD_I, PJTAG_TD_T, PJTAG_TD_O, SDIO0_CLK, SDIO0_CLK_FB, SDIO0_CMD_O, SDIO0_CMD_I, SDIO0_CMD_T, SDIO0_DATA_I, SDIO0_DATA_O, SDIO0_DATA_T, SDIO0_LED, SDIO0_CDN, SDIO0_WP, SDIO0_BUSPOW, SDIO0_BUSVOLT, SDIO1_CLK, SDIO1_CLK_FB, SDIO1_CMD_O, SDIO1_CMD_I, SDIO1_CMD_T, SDIO1_DATA_I, SDIO1_DATA_O, SDIO1_DATA_T, SDIO1_LED, SDIO1_CDN, SDIO1_WP, SDIO1_BUSPOW, SDIO1_BUSVOLT, SPI0_SCLK_I, SPI0_SCLK_O, SPI0_SCLK_T, SPI0_MOSI_I, SPI0_MOSI_O, SPI0_MOSI_T, SPI0_MISO_I, SPI0_MISO_O, SPI0_MISO_T, SPI0_SS_I, SPI0_SS_O, SPI0_SS1_O, SPI0_SS2_O, SPI0_SS_T, SPI1_SCLK_I, SPI1_SCLK_O, SPI1_SCLK_T, SPI1_MOSI_I, SPI1_MOSI_O, SPI1_MOSI_T, SPI1_MISO_I, SPI1_MISO_O, SPI1_MISO_T, SPI1_SS_I, SPI1_SS_O, SPI1_SS1_O, SPI1_SS2_O, SPI1_SS_T, UART0_DTRN, UART0_RTSN, UART0_TX, UART0_CTSN, UART0_DCDN, UART0_DSRN, UART0_RIN, UART0_RX, UART1_DTRN, UART1_RTSN, UART1_TX, UART1_CTSN, UART1_DCDN, UART1_DSRN, UART1_RIN, UART1_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, TTC0_CLK0_IN, TTC0_CLK1_IN, TTC0_CLK2_IN, TTC1_WAVE0_OUT, TTC1_WAVE1_OUT, TTC1_WAVE2_OUT, TTC1_CLK0_IN, TTC1_CLK1_IN, TTC1_CLK2_IN, WDT_CLK_IN, WDT_RST_OUT, TRACE_CLK, TRACE_CTL, TRACE_DATA, USB0_PORT_INDCTL, USB1_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB1_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, USB1_VBUS_PWRFAULT, SRAM_INTIN, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, M_AXI_GP1_ARVALID, M_AXI_GP1_AWVALID, M_AXI_GP1_BREADY, M_AXI_GP1_RREADY, M_AXI_GP1_WLAST, M_AXI_GP1_WVALID, M_AXI_GP1_ARID, M_AXI_GP1_AWID, M_AXI_GP1_WID, M_AXI_GP1_ARBURST, M_AXI_GP1_ARLOCK, M_AXI_GP1_ARSIZE, M_AXI_GP1_AWBURST, M_AXI_GP1_AWLOCK, M_AXI_GP1_AWSIZE, M_AXI_GP1_ARPROT, M_AXI_GP1_AWPROT, M_AXI_GP1_ARADDR, M_AXI_GP1_AWADDR, M_AXI_GP1_WDATA, M_AXI_GP1_ARCACHE, M_AXI_GP1_ARLEN, M_AXI_GP1_ARQOS, M_AXI_GP1_AWCACHE, M_AXI_GP1_AWLEN, M_AXI_GP1_AWQOS, M_AXI_GP1_WSTRB, M_AXI_GP1_ACLK, M_AXI_GP1_ARREADY, M_AXI_GP1_AWREADY, M_AXI_GP1_BVALID, M_AXI_GP1_RLAST, M_AXI_GP1_RVALID, M_AXI_GP1_WREADY, M_AXI_GP1_BID, M_AXI_GP1_RID, M_AXI_GP1_BRESP, M_AXI_GP1_RRESP, M_AXI_GP1_RDATA, S_AXI_GP0_ARREADY, S_AXI_GP0_AWREADY, S_AXI_GP0_BVALID, S_AXI_GP0_RLAST, S_AXI_GP0_RVALID, S_AXI_GP0_WREADY, S_AXI_GP0_BRESP, S_AXI_GP0_RRESP, S_AXI_GP0_RDATA, S_AXI_GP0_BID, S_AXI_GP0_RID, S_AXI_GP0_ACLK, S_AXI_GP0_ARVALID, S_AXI_GP0_AWVALID, S_AXI_GP0_BREADY, S_AXI_GP0_RREADY, S_AXI_GP0_WLAST, S_AXI_GP0_WVALID, S_AXI_GP0_ARBURST, S_AXI_GP0_ARLOCK, S_AXI_GP0_ARSIZE, S_AXI_GP0_AWBURST, S_AXI_GP0_AWLOCK, S_AXI_GP0_AWSIZE, S_AXI_GP0_ARPROT, S_AXI_GP0_AWPROT, S_AXI_GP0_ARADDR, S_AXI_GP0_AWADDR, S_AXI_GP0_WDATA, S_AXI_GP0_ARCACHE, S_AXI_GP0_ARLEN, S_AXI_GP0_ARQOS, S_AXI_GP0_AWCACHE, S_AXI_GP0_AWLEN, S_AXI_GP0_AWQOS, S_AXI_GP0_WSTRB, S_AXI_GP0_ARID, S_AXI_GP0_AWID, S_AXI_GP0_WID, S_AXI_GP1_ARREADY, S_AXI_GP1_AWREADY, S_AXI_GP1_BVALID, S_AXI_GP1_RLAST, S_AXI_GP1_RVALID, S_AXI_GP1_WREADY, S_AXI_GP1_BRESP, S_AXI_GP1_RRESP, S_AXI_GP1_RDATA, S_AXI_GP1_BID, S_AXI_GP1_RID, S_AXI_GP1_ACLK, S_AXI_GP1_ARVALID, S_AXI_GP1_AWVALID, S_AXI_GP1_BREADY, S_AXI_GP1_RREADY, S_AXI_GP1_WLAST, S_AXI_GP1_WVALID, S_AXI_GP1_ARBURST, S_AXI_GP1_ARLOCK, S_AXI_GP1_ARSIZE, S_AXI_GP1_AWBURST, S_AXI_GP1_AWLOCK, S_AXI_GP1_AWSIZE, S_AXI_GP1_ARPROT, S_AXI_GP1_AWPROT, S_AXI_GP1_ARADDR, S_AXI_GP1_AWADDR, S_AXI_GP1_WDATA, S_AXI_GP1_ARCACHE, S_AXI_GP1_ARLEN, S_AXI_GP1_ARQOS, S_AXI_GP1_AWCACHE, S_AXI_GP1_AWLEN, S_AXI_GP1_AWQOS, S_AXI_GP1_WSTRB, S_AXI_GP1_ARID, S_AXI_GP1_AWID, S_AXI_GP1_WID, S_AXI_ACP_AWREADY, S_AXI_ACP_ARREADY, S_AXI_ACP_BVALID, S_AXI_ACP_RLAST, S_AXI_ACP_RVALID, S_AXI_ACP_WREADY, S_AXI_ACP_BRESP, S_AXI_ACP_RRESP, S_AXI_ACP_BID, S_AXI_ACP_RID, S_AXI_ACP_RDATA, S_AXI_ACP_ACLK, S_AXI_ACP_ARVALID, S_AXI_ACP_AWVALID, S_AXI_ACP_BREADY, S_AXI_ACP_RREADY, S_AXI_ACP_WLAST, S_AXI_ACP_WVALID, S_AXI_ACP_ARID, S_AXI_ACP_ARPROT, S_AXI_ACP_AWID, S_AXI_ACP_AWPROT, S_AXI_ACP_WID, S_AXI_ACP_ARADDR, S_AXI_ACP_AWADDR, S_AXI_ACP_ARCACHE, S_AXI_ACP_ARLEN, S_AXI_ACP_ARQOS, S_AXI_ACP_AWCACHE, S_AXI_ACP_AWLEN, S_AXI_ACP_AWQOS, S_AXI_ACP_ARBURST, S_AXI_ACP_ARLOCK, S_AXI_ACP_ARSIZE, S_AXI_ACP_AWBURST, S_AXI_ACP_AWLOCK, S_AXI_ACP_AWSIZE, S_AXI_ACP_ARUSER, S_AXI_ACP_AWUSER, S_AXI_ACP_WDATA, S_AXI_ACP_WSTRB, S_AXI_HP0_ARREADY, S_AXI_HP0_AWREADY, S_AXI_HP0_BVALID, S_AXI_HP0_RLAST, S_AXI_HP0_RVALID, S_AXI_HP0_WREADY, S_AXI_HP0_BRESP, S_AXI_HP0_RRESP, S_AXI_HP0_BID, S_AXI_HP0_RID, S_AXI_HP0_RDATA, S_AXI_HP0_RCOUNT, S_AXI_HP0_WCOUNT, S_AXI_HP0_RACOUNT, S_AXI_HP0_WACOUNT, S_AXI_HP0_ACLK, S_AXI_HP0_ARVALID, S_AXI_HP0_AWVALID, S_AXI_HP0_BREADY, S_AXI_HP0_RDISSUECAP1_EN, S_AXI_HP0_RREADY, S_AXI_HP0_WLAST, S_AXI_HP0_WRISSUECAP1_EN, S_AXI_HP0_WVALID, S_AXI_HP0_ARBURST, S_AXI_HP0_ARLOCK, S_AXI_HP0_ARSIZE, S_AXI_HP0_AWBURST, S_AXI_HP0_AWLOCK, S_AXI_HP0_AWSIZE, S_AXI_HP0_ARPROT, S_AXI_HP0_AWPROT, S_AXI_HP0_ARADDR, S_AXI_HP0_AWADDR, S_AXI_HP0_ARCACHE, S_AXI_HP0_ARLEN, S_AXI_HP0_ARQOS, S_AXI_HP0_AWCACHE, S_AXI_HP0_AWLEN, S_AXI_HP0_AWQOS, S_AXI_HP0_ARID, S_AXI_HP0_AWID, S_AXI_HP0_WID, S_AXI_HP0_WDATA, S_AXI_HP0_WSTRB, S_AXI_HP1_ARREADY, S_AXI_HP1_AWREADY, S_AXI_HP1_BVALID, S_AXI_HP1_RLAST, S_AXI_HP1_RVALID, S_AXI_HP1_WREADY, S_AXI_HP1_BRESP, S_AXI_HP1_RRESP, S_AXI_HP1_BID, S_AXI_HP1_RID, S_AXI_HP1_RDATA, S_AXI_HP1_RCOUNT, S_AXI_HP1_WCOUNT, S_AXI_HP1_RACOUNT, S_AXI_HP1_WACOUNT, S_AXI_HP1_ACLK, S_AXI_HP1_ARVALID, S_AXI_HP1_AWVALID, S_AXI_HP1_BREADY, S_AXI_HP1_RDISSUECAP1_EN, S_AXI_HP1_RREADY, S_AXI_HP1_WLAST, S_AXI_HP1_WRISSUECAP1_EN, S_AXI_HP1_WVALID, S_AXI_HP1_ARBURST, S_AXI_HP1_ARLOCK, S_AXI_HP1_ARSIZE, S_AXI_HP1_AWBURST, S_AXI_HP1_AWLOCK, S_AXI_HP1_AWSIZE, S_AXI_HP1_ARPROT, S_AXI_HP1_AWPROT, S_AXI_HP1_ARADDR, S_AXI_HP1_AWADDR, S_AXI_HP1_ARCACHE, S_AXI_HP1_ARLEN, S_AXI_HP1_ARQOS, S_AXI_HP1_AWCACHE, S_AXI_HP1_AWLEN, S_AXI_HP1_AWQOS, S_AXI_HP1_ARID, S_AXI_HP1_AWID, S_AXI_HP1_WID, S_AXI_HP1_WDATA, S_AXI_HP1_WSTRB, S_AXI_HP2_ARREADY, S_AXI_HP2_AWREADY, S_AXI_HP2_BVALID, S_AXI_HP2_RLAST, S_AXI_HP2_RVALID, S_AXI_HP2_WREADY, S_AXI_HP2_BRESP, S_AXI_HP2_RRESP, S_AXI_HP2_BID, S_AXI_HP2_RID, S_AXI_HP2_RDATA, S_AXI_HP2_RCOUNT, S_AXI_HP2_WCOUNT, S_AXI_HP2_RACOUNT, S_AXI_HP2_WACOUNT, S_AXI_HP2_ACLK, S_AXI_HP2_ARVALID, S_AXI_HP2_AWVALID, S_AXI_HP2_BREADY, S_AXI_HP2_RDISSUECAP1_EN, S_AXI_HP2_RREADY, S_AXI_HP2_WLAST, S_AXI_HP2_WRISSUECAP1_EN, S_AXI_HP2_WVALID, S_AXI_HP2_ARBURST, S_AXI_HP2_ARLOCK, S_AXI_HP2_ARSIZE, S_AXI_HP2_AWBURST, S_AXI_HP2_AWLOCK, S_AXI_HP2_AWSIZE, S_AXI_HP2_ARPROT, S_AXI_HP2_AWPROT, S_AXI_HP2_ARADDR, S_AXI_HP2_AWADDR, S_AXI_HP2_ARCACHE, S_AXI_HP2_ARLEN, S_AXI_HP2_ARQOS, S_AXI_HP2_AWCACHE, S_AXI_HP2_AWLEN, S_AXI_HP2_AWQOS, S_AXI_HP2_ARID, S_AXI_HP2_AWID, S_AXI_HP2_WID, S_AXI_HP2_WDATA, S_AXI_HP2_WSTRB, S_AXI_HP3_ARREADY, S_AXI_HP3_AWREADY, S_AXI_HP3_BVALID, S_AXI_HP3_RLAST, S_AXI_HP3_RVALID, S_AXI_HP3_WREADY, S_AXI_HP3_BRESP, S_AXI_HP3_RRESP, S_AXI_HP3_BID, S_AXI_HP3_RID, S_AXI_HP3_RDATA, S_AXI_HP3_RCOUNT, S_AXI_HP3_WCOUNT, S_AXI_HP3_RACOUNT, S_AXI_HP3_WACOUNT, S_AXI_HP3_ACLK, S_AXI_HP3_ARVALID, S_AXI_HP3_AWVALID, S_AXI_HP3_BREADY, S_AXI_HP3_RDISSUECAP1_EN, S_AXI_HP3_RREADY, S_AXI_HP3_WLAST, S_AXI_HP3_WRISSUECAP1_EN, S_AXI_HP3_WVALID, S_AXI_HP3_ARBURST, S_AXI_HP3_ARLOCK, S_AXI_HP3_ARSIZE, S_AXI_HP3_AWBURST, S_AXI_HP3_AWLOCK, S_AXI_HP3_AWSIZE, S_AXI_HP3_ARPROT, S_AXI_HP3_AWPROT, S_AXI_HP3_ARADDR, S_AXI_HP3_AWADDR, S_AXI_HP3_ARCACHE, S_AXI_HP3_ARLEN, S_AXI_HP3_ARQOS, S_AXI_HP3_AWCACHE, S_AXI_HP3_AWLEN, S_AXI_HP3_AWQOS, S_AXI_HP3_ARID, S_AXI_HP3_AWID, S_AXI_HP3_WID, S_AXI_HP3_WDATA, S_AXI_HP3_WSTRB, DMA0_DATYPE, DMA0_DAVALID, DMA0_DRREADY, DMA0_ACLK, DMA0_DAREADY, DMA0_DRLAST, DMA0_DRVALID, DMA0_DRTYPE, DMA1_DATYPE, DMA1_DAVALID, DMA1_DRREADY, DMA1_ACLK, DMA1_DAREADY, DMA1_DRLAST, DMA1_DRVALID, DMA1_DRTYPE, DMA2_DATYPE, DMA2_DAVALID, DMA2_DRREADY, DMA2_ACLK, DMA2_DAREADY, DMA2_DRLAST, DMA2_DRVALID, DMA3_DRVALID, DMA3_DATYPE, DMA3_DAVALID, DMA3_DRREADY, DMA3_ACLK, DMA3_DAREADY, DMA3_DRLAST, DMA2_DRTYPE, DMA3_DRTYPE, FTMD_TRACEIN_DATA, FTMD_TRACEIN_VALID, FTMD_TRACEIN_CLK, FTMD_TRACEIN_ATID, FTMT_F2P_TRIG, FTMT_F2P_TRIGACK, FTMT_F2P_DEBUG, FTMT_P2F_TRIGACK, FTMT_P2F_TRIG, FTMT_P2F_DEBUG, FCLK_CLK3, FCLK_CLK2, FCLK_CLK1, FCLK_CLK0, FCLK_CLKTRIG3_N, FCLK_CLKTRIG2_N, FCLK_CLKTRIG1_N, FCLK_CLKTRIG0_N, FCLK_RESET3_N, FCLK_RESET2_N, FCLK_RESET1_N, FCLK_RESET0_N, FPGA_IDLE_N, DDR_ARB, IRQ_F2P, Core0_nFIQ, Core0_nIRQ, Core1_nFIQ, Core1_nIRQ, EVENT_EVENTO, EVENT_STANDBYWFE, EVENT_STANDBYWFI, EVENT_EVENTI, MIO, DDR_Clk, DDR_Clk_n, DDR_CKE, DDR_CS_n, DDR_RAS_n, DDR_CAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_ODT, DDR_DRSTB, DDR_DQ, DDR_DM, DDR_DQS, DDR_DQS_n, DDR_VRN, DDR_VRP, PS_SRSTB, PS_CLK, PS_PORB, IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC0, IRQ_P2F_DMAC1, IRQ_P2F_DMAC2, IRQ_P2F_DMAC3, IRQ_P2F_DMAC4, IRQ_P2F_DMAC5, IRQ_P2F_DMAC6, IRQ_P2F_DMAC7, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1 ); /* parameters for gen_clk */ parameter C_FCLK_CLK0_FREQ = 50; parameter C_FCLK_CLK1_FREQ = 50; parameter C_FCLK_CLK3_FREQ = 50; parameter C_FCLK_CLK2_FREQ = 50; parameter C_HIGH_OCM_EN = 0; /* parameters for HP ports */ parameter C_USE_S_AXI_HP0 = 0; parameter C_USE_S_AXI_HP1 = 0; parameter C_USE_S_AXI_HP2 = 0; parameter C_USE_S_AXI_HP3 = 0; parameter C_S_AXI_HP0_DATA_WIDTH = 32; parameter C_S_AXI_HP1_DATA_WIDTH = 32; parameter C_S_AXI_HP2_DATA_WIDTH = 32; parameter C_S_AXI_HP3_DATA_WIDTH = 32; parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12; parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12; parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0; parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0; /* Do we need these parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */ parameter C_S_AXI_HP0_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP1_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP2_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP3_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP0_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP1_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP2_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP3_HIGHADDR = 32'hFFFF_FFFF; /* parameters for GP and ACP ports */ parameter C_USE_M_AXI_GP0 = 0; parameter C_USE_M_AXI_GP1 = 0; parameter C_USE_S_AXI_GP0 = 1; parameter C_USE_S_AXI_GP1 = 1; /* Do we need this? parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0; parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0; parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/ parameter C_S_AXI_GP0_BASEADDR = 32'h0000_0000; parameter C_S_AXI_GP1_BASEADDR = 32'h0000_0000; parameter C_S_AXI_GP0_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_GP1_HIGHADDR = 32'hFFFF_FFFF; parameter C_USE_S_AXI_ACP = 1; parameter C_S_AXI_ACP_BASEADDR = 32'h0000_0000; parameter C_S_AXI_ACP_HIGHADDR = 32'hFFFF_FFFF; `include "processing_system7_bfm_v2_0_5_local_params.v" output CAN0_PHY_TX; input CAN0_PHY_RX; output CAN1_PHY_TX; input CAN1_PHY_RX; output ENET0_GMII_TX_EN; output ENET0_GMII_TX_ER; output ENET0_MDIO_MDC; output ENET0_MDIO_O; output ENET0_MDIO_T; output ENET0_PTP_DELAY_REQ_RX; output ENET0_PTP_DELAY_REQ_TX; output ENET0_PTP_PDELAY_REQ_RX; output ENET0_PTP_PDELAY_REQ_TX; output ENET0_PTP_PDELAY_RESP_RX; output ENET0_PTP_PDELAY_RESP_TX; output ENET0_PTP_SYNC_FRAME_RX; output ENET0_PTP_SYNC_FRAME_TX; output ENET0_SOF_RX; output ENET0_SOF_TX; output [7:0] ENET0_GMII_TXD; input ENET0_GMII_COL; input ENET0_GMII_CRS; input ENET0_EXT_INTIN; input ENET0_GMII_RX_CLK; input ENET0_GMII_RX_DV; input ENET0_GMII_RX_ER; input ENET0_GMII_TX_CLK; input ENET0_MDIO_I; input [7:0] ENET0_GMII_RXD; output ENET1_GMII_TX_EN; output ENET1_GMII_TX_ER; output ENET1_MDIO_MDC; output ENET1_MDIO_O; output ENET1_MDIO_T; output ENET1_PTP_DELAY_REQ_RX; output ENET1_PTP_DELAY_REQ_TX; output ENET1_PTP_PDELAY_REQ_RX; output ENET1_PTP_PDELAY_REQ_TX; output ENET1_PTP_PDELAY_RESP_RX; output ENET1_PTP_PDELAY_RESP_TX; output ENET1_PTP_SYNC_FRAME_RX; output ENET1_PTP_SYNC_FRAME_TX; output ENET1_SOF_RX; output ENET1_SOF_TX; output [7:0] ENET1_GMII_TXD; input ENET1_GMII_COL; input ENET1_GMII_CRS; input ENET1_EXT_INTIN; input ENET1_GMII_RX_CLK; input ENET1_GMII_RX_DV; input ENET1_GMII_RX_ER; input ENET1_GMII_TX_CLK; input ENET1_MDIO_I; input [7:0] ENET1_GMII_RXD; input [63:0] GPIO_I; output [63:0] GPIO_O; output [63:0] GPIO_T; input I2C0_SDA_I; output I2C0_SDA_O; output I2C0_SDA_T; input I2C0_SCL_I; output I2C0_SCL_O; output I2C0_SCL_T; input I2C1_SDA_I; output I2C1_SDA_O; output I2C1_SDA_T; input I2C1_SCL_I; output I2C1_SCL_O; output I2C1_SCL_T; input PJTAG_TCK; input PJTAG_TMS; input PJTAG_TD_I; output PJTAG_TD_T; output PJTAG_TD_O; output SDIO0_CLK; input SDIO0_CLK_FB; output SDIO0_CMD_O; input SDIO0_CMD_I; output SDIO0_CMD_T; input [3:0] SDIO0_DATA_I; output [3:0] SDIO0_DATA_O; output [3:0] SDIO0_DATA_T; output SDIO0_LED; input SDIO0_CDN; input SDIO0_WP; output SDIO0_BUSPOW; output [2:0] SDIO0_BUSVOLT; output SDIO1_CLK; input SDIO1_CLK_FB; output SDIO1_CMD_O; input SDIO1_CMD_I; output SDIO1_CMD_T; input [3:0] SDIO1_DATA_I; output [3:0] SDIO1_DATA_O; output [3:0] SDIO1_DATA_T; output SDIO1_LED; input SDIO1_CDN; input SDIO1_WP; output SDIO1_BUSPOW; output [2:0] SDIO1_BUSVOLT; input SPI0_SCLK_I; output SPI0_SCLK_O; output SPI0_SCLK_T; input SPI0_MOSI_I; output SPI0_MOSI_O; output SPI0_MOSI_T; input SPI0_MISO_I; output SPI0_MISO_O; output SPI0_MISO_T; input SPI0_SS_I; output SPI0_SS_O; output SPI0_SS1_O; output SPI0_SS2_O; output SPI0_SS_T; input SPI1_SCLK_I; output SPI1_SCLK_O; output SPI1_SCLK_T; input SPI1_MOSI_I; output SPI1_MOSI_O; output SPI1_MOSI_T; input SPI1_MISO_I; output SPI1_MISO_O; output SPI1_MISO_T; input SPI1_SS_I; output SPI1_SS_O; output SPI1_SS1_O; output SPI1_SS2_O; output SPI1_SS_T; output UART0_DTRN; output UART0_RTSN; output UART0_TX; input UART0_CTSN; input UART0_DCDN; input UART0_DSRN; input UART0_RIN; input UART0_RX; output UART1_DTRN; output UART1_RTSN; output UART1_TX; input UART1_CTSN; input UART1_DCDN; input UART1_DSRN; input UART1_RIN; input UART1_RX; output TTC0_WAVE0_OUT; output TTC0_WAVE1_OUT; output TTC0_WAVE2_OUT; input TTC0_CLK0_IN; input TTC0_CLK1_IN; input TTC0_CLK2_IN; output TTC1_WAVE0_OUT; output TTC1_WAVE1_OUT; output TTC1_WAVE2_OUT; input TTC1_CLK0_IN; input TTC1_CLK1_IN; input TTC1_CLK2_IN; input WDT_CLK_IN; output WDT_RST_OUT; input TRACE_CLK; output TRACE_CTL; output [31:0] TRACE_DATA; output [1:0] USB0_PORT_INDCTL; output [1:0] USB1_PORT_INDCTL; output USB0_VBUS_PWRSELECT; output USB1_VBUS_PWRSELECT; input USB0_VBUS_PWRFAULT; input USB1_VBUS_PWRFAULT; input SRAM_INTIN; output M_AXI_GP0_ARVALID; output M_AXI_GP0_AWVALID; output M_AXI_GP0_BREADY; output M_AXI_GP0_RREADY; output M_AXI_GP0_WLAST; output M_AXI_GP0_WVALID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID; output [1:0] M_AXI_GP0_ARBURST; output [1:0] M_AXI_GP0_ARLOCK; output [2:0] M_AXI_GP0_ARSIZE; output [1:0] M_AXI_GP0_AWBURST; output [1:0] M_AXI_GP0_AWLOCK; output [2:0] M_AXI_GP0_AWSIZE; output [2:0] M_AXI_GP0_ARPROT; output [2:0] M_AXI_GP0_AWPROT; output [31:0] M_AXI_GP0_ARADDR; output [31:0] M_AXI_GP0_AWADDR; output [31:0] M_AXI_GP0_WDATA; output [3:0] M_AXI_GP0_ARCACHE; output [3:0] M_AXI_GP0_ARLEN; output [3:0] M_AXI_GP0_ARQOS; output [3:0] M_AXI_GP0_AWCACHE; output [3:0] M_AXI_GP0_AWLEN; output [3:0] M_AXI_GP0_AWQOS; output [3:0] M_AXI_GP0_WSTRB; input M_AXI_GP0_ACLK; input M_AXI_GP0_ARREADY; input M_AXI_GP0_AWREADY; input M_AXI_GP0_BVALID; input M_AXI_GP0_RLAST; input M_AXI_GP0_RVALID; input M_AXI_GP0_WREADY; input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID; input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID; input [1:0] M_AXI_GP0_BRESP; input [1:0] M_AXI_GP0_RRESP; input [31:0] M_AXI_GP0_RDATA; output M_AXI_GP1_ARVALID; output M_AXI_GP1_AWVALID; output M_AXI_GP1_BREADY; output M_AXI_GP1_RREADY; output M_AXI_GP1_WLAST; output M_AXI_GP1_WVALID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID; output [1:0] M_AXI_GP1_ARBURST; output [1:0] M_AXI_GP1_ARLOCK; output [2:0] M_AXI_GP1_ARSIZE; output [1:0] M_AXI_GP1_AWBURST; output [1:0] M_AXI_GP1_AWLOCK; output [2:0] M_AXI_GP1_AWSIZE; output [2:0] M_AXI_GP1_ARPROT; output [2:0] M_AXI_GP1_AWPROT; output [31:0] M_AXI_GP1_ARADDR; output [31:0] M_AXI_GP1_AWADDR; output [31:0] M_AXI_GP1_WDATA; output [3:0] M_AXI_GP1_ARCACHE; output [3:0] M_AXI_GP1_ARLEN; output [3:0] M_AXI_GP1_ARQOS; output [3:0] M_AXI_GP1_AWCACHE; output [3:0] M_AXI_GP1_AWLEN; output [3:0] M_AXI_GP1_AWQOS; output [3:0] M_AXI_GP1_WSTRB; input M_AXI_GP1_ACLK; input M_AXI_GP1_ARREADY; input M_AXI_GP1_AWREADY; input M_AXI_GP1_BVALID; input M_AXI_GP1_RLAST; input M_AXI_GP1_RVALID; input M_AXI_GP1_WREADY; input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID; input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID; input [1:0] M_AXI_GP1_BRESP; input [1:0] M_AXI_GP1_RRESP; input [31:0] M_AXI_GP1_RDATA; output S_AXI_GP0_ARREADY; output S_AXI_GP0_AWREADY; output S_AXI_GP0_BVALID; output S_AXI_GP0_RLAST; output S_AXI_GP0_RVALID; output S_AXI_GP0_WREADY; output [1:0] S_AXI_GP0_BRESP; output [1:0] S_AXI_GP0_RRESP; output [31:0] S_AXI_GP0_RDATA; output [5:0] S_AXI_GP0_BID; output [5:0] S_AXI_GP0_RID; input S_AXI_GP0_ACLK; input S_AXI_GP0_ARVALID; input S_AXI_GP0_AWVALID; input S_AXI_GP0_BREADY; input S_AXI_GP0_RREADY; input S_AXI_GP0_WLAST; input S_AXI_GP0_WVALID; input [1:0] S_AXI_GP0_ARBURST; input [1:0] S_AXI_GP0_ARLOCK; input [2:0] S_AXI_GP0_ARSIZE; input [1:0] S_AXI_GP0_AWBURST; input [1:0] S_AXI_GP0_AWLOCK; input [2:0] S_AXI_GP0_AWSIZE; input [2:0] S_AXI_GP0_ARPROT; input [2:0] S_AXI_GP0_AWPROT; input [31:0] S_AXI_GP0_ARADDR; input [31:0] S_AXI_GP0_AWADDR; input [31:0] S_AXI_GP0_WDATA; input [3:0] S_AXI_GP0_ARCACHE; input [3:0] S_AXI_GP0_ARLEN; input [3:0] S_AXI_GP0_ARQOS; input [3:0] S_AXI_GP0_AWCACHE; input [3:0] S_AXI_GP0_AWLEN; input [3:0] S_AXI_GP0_AWQOS; input [3:0] S_AXI_GP0_WSTRB; input [5:0] S_AXI_GP0_ARID; input [5:0] S_AXI_GP0_AWID; input [5:0] S_AXI_GP0_WID; output S_AXI_GP1_ARREADY; output S_AXI_GP1_AWREADY; output S_AXI_GP1_BVALID; output S_AXI_GP1_RLAST; output S_AXI_GP1_RVALID; output S_AXI_GP1_WREADY; output [1:0] S_AXI_GP1_BRESP; output [1:0] S_AXI_GP1_RRESP; output [31:0] S_AXI_GP1_RDATA; output [5:0] S_AXI_GP1_BID; output [5:0] S_AXI_GP1_RID; input S_AXI_GP1_ACLK; input S_AXI_GP1_ARVALID; input S_AXI_GP1_AWVALID; input S_AXI_GP1_BREADY; input S_AXI_GP1_RREADY; input S_AXI_GP1_WLAST; input S_AXI_GP1_WVALID; input [1:0] S_AXI_GP1_ARBURST; input [1:0] S_AXI_GP1_ARLOCK; input [2:0] S_AXI_GP1_ARSIZE; input [1:0] S_AXI_GP1_AWBURST; input [1:0] S_AXI_GP1_AWLOCK; input [2:0] S_AXI_GP1_AWSIZE; input [2:0] S_AXI_GP1_ARPROT; input [2:0] S_AXI_GP1_AWPROT; input [31:0] S_AXI_GP1_ARADDR; input [31:0] S_AXI_GP1_AWADDR; input [31:0] S_AXI_GP1_WDATA; input [3:0] S_AXI_GP1_ARCACHE; input [3:0] S_AXI_GP1_ARLEN; input [3:0] S_AXI_GP1_ARQOS; input [3:0] S_AXI_GP1_AWCACHE; input [3:0] S_AXI_GP1_AWLEN; input [3:0] S_AXI_GP1_AWQOS; input [3:0] S_AXI_GP1_WSTRB; input [5:0] S_AXI_GP1_ARID; input [5:0] S_AXI_GP1_AWID; input [5:0] S_AXI_GP1_WID; output S_AXI_ACP_AWREADY; output S_AXI_ACP_ARREADY; output S_AXI_ACP_BVALID; output S_AXI_ACP_RLAST; output S_AXI_ACP_RVALID; output S_AXI_ACP_WREADY; output [1:0] S_AXI_ACP_BRESP; output [1:0] S_AXI_ACP_RRESP; output [2:0] S_AXI_ACP_BID; output [2:0] S_AXI_ACP_RID; output [63:0] S_AXI_ACP_RDATA; input S_AXI_ACP_ACLK; input S_AXI_ACP_ARVALID; input S_AXI_ACP_AWVALID; input S_AXI_ACP_BREADY; input S_AXI_ACP_RREADY; input S_AXI_ACP_WLAST; input S_AXI_ACP_WVALID; input [2:0] S_AXI_ACP_ARID; input [2:0] S_AXI_ACP_ARPROT; input [2:0] S_AXI_ACP_AWID; input [2:0] S_AXI_ACP_AWPROT; input [2:0] S_AXI_ACP_WID; input [31:0] S_AXI_ACP_ARADDR; input [31:0] S_AXI_ACP_AWADDR; input [3:0] S_AXI_ACP_ARCACHE; input [3:0] S_AXI_ACP_ARLEN; input [3:0] S_AXI_ACP_ARQOS; input [3:0] S_AXI_ACP_AWCACHE; input [3:0] S_AXI_ACP_AWLEN; input [3:0] S_AXI_ACP_AWQOS; input [1:0] S_AXI_ACP_ARBURST; input [1:0] S_AXI_ACP_ARLOCK; input [2:0] S_AXI_ACP_ARSIZE; input [1:0] S_AXI_ACP_AWBURST; input [1:0] S_AXI_ACP_AWLOCK; input [2:0] S_AXI_ACP_AWSIZE; input [4:0] S_AXI_ACP_ARUSER; input [4:0] S_AXI_ACP_AWUSER; input [63:0] S_AXI_ACP_WDATA; input [7:0] S_AXI_ACP_WSTRB; output S_AXI_HP0_ARREADY; output S_AXI_HP0_AWREADY; output S_AXI_HP0_BVALID; output S_AXI_HP0_RLAST; output S_AXI_HP0_RVALID; output S_AXI_HP0_WREADY; output [1:0] S_AXI_HP0_BRESP; output [1:0] S_AXI_HP0_RRESP; output [5:0] S_AXI_HP0_BID; output [5:0] S_AXI_HP0_RID; output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA; output [7:0] S_AXI_HP0_RCOUNT; output [7:0] S_AXI_HP0_WCOUNT; output [2:0] S_AXI_HP0_RACOUNT; output [5:0] S_AXI_HP0_WACOUNT; input S_AXI_HP0_ACLK; input S_AXI_HP0_ARVALID; input S_AXI_HP0_AWVALID; input S_AXI_HP0_BREADY; input S_AXI_HP0_RDISSUECAP1_EN; input S_AXI_HP0_RREADY; input S_AXI_HP0_WLAST; input S_AXI_HP0_WRISSUECAP1_EN; input S_AXI_HP0_WVALID; input [1:0] S_AXI_HP0_ARBURST; input [1:0] S_AXI_HP0_ARLOCK; input [2:0] S_AXI_HP0_ARSIZE; input [1:0] S_AXI_HP0_AWBURST; input [1:0] S_AXI_HP0_AWLOCK; input [2:0] S_AXI_HP0_AWSIZE; input [2:0] S_AXI_HP0_ARPROT; input [2:0] S_AXI_HP0_AWPROT; input [31:0] S_AXI_HP0_ARADDR; input [31:0] S_AXI_HP0_AWADDR; input [3:0] S_AXI_HP0_ARCACHE; input [3:0] S_AXI_HP0_ARLEN; input [3:0] S_AXI_HP0_ARQOS; input [3:0] S_AXI_HP0_AWCACHE; input [3:0] S_AXI_HP0_AWLEN; input [3:0] S_AXI_HP0_AWQOS; input [5:0] S_AXI_HP0_ARID; input [5:0] S_AXI_HP0_AWID; input [5:0] S_AXI_HP0_WID; input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA; input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB; output S_AXI_HP1_ARREADY; output S_AXI_HP1_AWREADY; output S_AXI_HP1_BVALID; output S_AXI_HP1_RLAST; output S_AXI_HP1_RVALID; output S_AXI_HP1_WREADY; output [1:0] S_AXI_HP1_BRESP; output [1:0] S_AXI_HP1_RRESP; output [5:0] S_AXI_HP1_BID; output [5:0] S_AXI_HP1_RID; output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA; output [7:0] S_AXI_HP1_RCOUNT; output [7:0] S_AXI_HP1_WCOUNT; output [2:0] S_AXI_HP1_RACOUNT; output [5:0] S_AXI_HP1_WACOUNT; input S_AXI_HP1_ACLK; input S_AXI_HP1_ARVALID; input S_AXI_HP1_AWVALID; input S_AXI_HP1_BREADY; input S_AXI_HP1_RDISSUECAP1_EN; input S_AXI_HP1_RREADY; input S_AXI_HP1_WLAST; input S_AXI_HP1_WRISSUECAP1_EN; input S_AXI_HP1_WVALID; input [1:0] S_AXI_HP1_ARBURST; input [1:0] S_AXI_HP1_ARLOCK; input [2:0] S_AXI_HP1_ARSIZE; input [1:0] S_AXI_HP1_AWBURST; input [1:0] S_AXI_HP1_AWLOCK; input [2:0] S_AXI_HP1_AWSIZE; input [2:0] S_AXI_HP1_ARPROT; input [2:0] S_AXI_HP1_AWPROT; input [31:0] S_AXI_HP1_ARADDR; input [31:0] S_AXI_HP1_AWADDR; input [3:0] S_AXI_HP1_ARCACHE; input [3:0] S_AXI_HP1_ARLEN; input [3:0] S_AXI_HP1_ARQOS; input [3:0] S_AXI_HP1_AWCACHE; input [3:0] S_AXI_HP1_AWLEN; input [3:0] S_AXI_HP1_AWQOS; input [5:0] S_AXI_HP1_ARID; input [5:0] S_AXI_HP1_AWID; input [5:0] S_AXI_HP1_WID; input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA; input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB; output S_AXI_HP2_ARREADY; output S_AXI_HP2_AWREADY; output S_AXI_HP2_BVALID; output S_AXI_HP2_RLAST; output S_AXI_HP2_RVALID; output S_AXI_HP2_WREADY; output [1:0] S_AXI_HP2_BRESP; output [1:0] S_AXI_HP2_RRESP; output [5:0] S_AXI_HP2_BID; output [5:0] S_AXI_HP2_RID; output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA; output [7:0] S_AXI_HP2_RCOUNT; output [7:0] S_AXI_HP2_WCOUNT; output [2:0] S_AXI_HP2_RACOUNT; output [5:0] S_AXI_HP2_WACOUNT; input S_AXI_HP2_ACLK; input S_AXI_HP2_ARVALID; input S_AXI_HP2_AWVALID; input S_AXI_HP2_BREADY; input S_AXI_HP2_RDISSUECAP1_EN; input S_AXI_HP2_RREADY; input S_AXI_HP2_WLAST; input S_AXI_HP2_WRISSUECAP1_EN; input S_AXI_HP2_WVALID; input [1:0] S_AXI_HP2_ARBURST; input [1:0] S_AXI_HP2_ARLOCK; input [2:0] S_AXI_HP2_ARSIZE; input [1:0] S_AXI_HP2_AWBURST; input [1:0] S_AXI_HP2_AWLOCK; input [2:0] S_AXI_HP2_AWSIZE; input [2:0] S_AXI_HP2_ARPROT; input [2:0] S_AXI_HP2_AWPROT; input [31:0] S_AXI_HP2_ARADDR; input [31:0] S_AXI_HP2_AWADDR; input [3:0] S_AXI_HP2_ARCACHE; input [3:0] S_AXI_HP2_ARLEN; input [3:0] S_AXI_HP2_ARQOS; input [3:0] S_AXI_HP2_AWCACHE; input [3:0] S_AXI_HP2_AWLEN; input [3:0] S_AXI_HP2_AWQOS; input [5:0] S_AXI_HP2_ARID; input [5:0] S_AXI_HP2_AWID; input [5:0] S_AXI_HP2_WID; input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA; input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB; output S_AXI_HP3_ARREADY; output S_AXI_HP3_AWREADY; output S_AXI_HP3_BVALID; output S_AXI_HP3_RLAST; output S_AXI_HP3_RVALID; output S_AXI_HP3_WREADY; output [1:0] S_AXI_HP3_BRESP; output [1:0] S_AXI_HP3_RRESP; output [5:0] S_AXI_HP3_BID; output [5:0] S_AXI_HP3_RID; output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA; output [7:0] S_AXI_HP3_RCOUNT; output [7:0] S_AXI_HP3_WCOUNT; output [2:0] S_AXI_HP3_RACOUNT; output [5:0] S_AXI_HP3_WACOUNT; input S_AXI_HP3_ACLK; input S_AXI_HP3_ARVALID; input S_AXI_HP3_AWVALID; input S_AXI_HP3_BREADY; input S_AXI_HP3_RDISSUECAP1_EN; input S_AXI_HP3_RREADY; input S_AXI_HP3_WLAST; input S_AXI_HP3_WRISSUECAP1_EN; input S_AXI_HP3_WVALID; input [1:0] S_AXI_HP3_ARBURST; input [1:0] S_AXI_HP3_ARLOCK; input [2:0] S_AXI_HP3_ARSIZE; input [1:0] S_AXI_HP3_AWBURST; input [1:0] S_AXI_HP3_AWLOCK; input [2:0] S_AXI_HP3_AWSIZE; input [2:0] S_AXI_HP3_ARPROT; input [2:0] S_AXI_HP3_AWPROT; input [31:0] S_AXI_HP3_ARADDR; input [31:0] S_AXI_HP3_AWADDR; input [3:0] S_AXI_HP3_ARCACHE; input [3:0] S_AXI_HP3_ARLEN; input [3:0] S_AXI_HP3_ARQOS; input [3:0] S_AXI_HP3_AWCACHE; input [3:0] S_AXI_HP3_AWLEN; input [3:0] S_AXI_HP3_AWQOS; input [5:0] S_AXI_HP3_ARID; input [5:0] S_AXI_HP3_AWID; input [5:0] S_AXI_HP3_WID; input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA; input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB; output [1:0] DMA0_DATYPE; output DMA0_DAVALID; output DMA0_DRREADY; input DMA0_ACLK; input DMA0_DAREADY; input DMA0_DRLAST; input DMA0_DRVALID; input [1:0] DMA0_DRTYPE; output [1:0] DMA1_DATYPE; output DMA1_DAVALID; output DMA1_DRREADY; input DMA1_ACLK; input DMA1_DAREADY; input DMA1_DRLAST; input DMA1_DRVALID; input [1:0] DMA1_DRTYPE; output [1:0] DMA2_DATYPE; output DMA2_DAVALID; output DMA2_DRREADY; input DMA2_ACLK; input DMA2_DAREADY; input DMA2_DRLAST; input DMA2_DRVALID; input DMA3_DRVALID; output [1:0] DMA3_DATYPE; output DMA3_DAVALID; output DMA3_DRREADY; input DMA3_ACLK; input DMA3_DAREADY; input DMA3_DRLAST; input [1:0] DMA2_DRTYPE; input [1:0] DMA3_DRTYPE; input [31:0] FTMD_TRACEIN_DATA; input FTMD_TRACEIN_VALID; input FTMD_TRACEIN_CLK; input [3:0] FTMD_TRACEIN_ATID; input [3:0] FTMT_F2P_TRIG; output [3:0] FTMT_F2P_TRIGACK; input [31:0] FTMT_F2P_DEBUG; input [3:0] FTMT_P2F_TRIGACK; output [3:0] FTMT_P2F_TRIG; output [31:0] FTMT_P2F_DEBUG; output FCLK_CLK3; output FCLK_CLK2; output FCLK_CLK1; output FCLK_CLK0; input FCLK_CLKTRIG3_N; input FCLK_CLKTRIG2_N; input FCLK_CLKTRIG1_N; input FCLK_CLKTRIG0_N; output FCLK_RESET3_N; output FCLK_RESET2_N; output FCLK_RESET1_N; output FCLK_RESET0_N; input FPGA_IDLE_N; input [3:0] DDR_ARB; input [irq_width-1:0] IRQ_F2P; input Core0_nFIQ; input Core0_nIRQ; input Core1_nFIQ; input Core1_nIRQ; output EVENT_EVENTO; output [1:0] EVENT_STANDBYWFE; output [1:0] EVENT_STANDBYWFI; input EVENT_EVENTI; inout [53:0] MIO; inout DDR_Clk; inout DDR_Clk_n; inout DDR_CKE; inout DDR_CS_n; inout DDR_RAS_n; inout DDR_CAS_n; output DDR_WEB; inout [2:0] DDR_BankAddr; inout [14:0] DDR_Addr; inout DDR_ODT; inout DDR_DRSTB; inout [31:0] DDR_DQ; inout [3:0] DDR_DM; inout [3:0] DDR_DQS; inout [3:0] DDR_DQS_n; inout DDR_VRN; inout DDR_VRP; /* Reset Input & Clock Input */ input PS_SRSTB; input PS_CLK; input PS_PORB; output IRQ_P2F_DMAC_ABORT; output IRQ_P2F_DMAC0; output IRQ_P2F_DMAC1; output IRQ_P2F_DMAC2; output IRQ_P2F_DMAC3; output IRQ_P2F_DMAC4; output IRQ_P2F_DMAC5; output IRQ_P2F_DMAC6; output IRQ_P2F_DMAC7; output IRQ_P2F_SMC; output IRQ_P2F_QSPI; output IRQ_P2F_CTI; output IRQ_P2F_GPIO; output IRQ_P2F_USB0; output IRQ_P2F_ENET0; output IRQ_P2F_ENET_WAKE0; output IRQ_P2F_SDIO0; output IRQ_P2F_I2C0; output IRQ_P2F_SPI0; output IRQ_P2F_UART0; output IRQ_P2F_CAN0; output IRQ_P2F_USB1; output IRQ_P2F_ENET1; output IRQ_P2F_ENET_WAKE1; output IRQ_P2F_SDIO1; output IRQ_P2F_I2C1; output IRQ_P2F_SPI1; output IRQ_P2F_UART1; output IRQ_P2F_CAN1; /* Internal wires/nets used for connectivity */ wire net_rstn; wire net_sw_clk; wire net_ocm_clk; wire net_arbiter_clk; wire net_axi_mgp0_rstn; wire net_axi_mgp1_rstn; wire net_axi_gp0_rstn; wire net_axi_gp1_rstn; wire net_axi_hp0_rstn; wire net_axi_hp1_rstn; wire net_axi_hp2_rstn; wire net_axi_hp3_rstn; wire net_axi_acp_rstn; wire [4:0] net_axi_acp_awuser; wire [4:0] net_axi_acp_aruser; /* Dummy */ assign net_axi_acp_awuser = S_AXI_ACP_AWUSER; assign net_axi_acp_aruser = S_AXI_ACP_ARUSER; /* Global variables */ reg DEBUG_INFO = 1; reg STOP_ON_ERROR = 1; /* local variable acting as semaphore for wait_mem_update and wait_reg_update task */ reg mem_update_key = 1; reg reg_update_key_0 = 1; reg reg_update_key_1 = 1; /* assignments and semantic checks for unused ports */ `include "processing_system7_bfm_v2_0_5_unused_ports.v" /* include api definition */ `include "processing_system7_bfm_v2_0_5_apis.v" /* Reset Generator */ processing_system7_bfm_v2_0_5_gen_reset gen_rst(.por_rst_n(PS_PORB), .sys_rst_n(PS_SRSTB), .rst_out_n(net_rstn), .m_axi_gp0_clk(M_AXI_GP0_ACLK), .m_axi_gp1_clk(M_AXI_GP1_ACLK), .s_axi_gp0_clk(S_AXI_GP0_ACLK), .s_axi_gp1_clk(S_AXI_GP1_ACLK), .s_axi_hp0_clk(S_AXI_HP0_ACLK), .s_axi_hp1_clk(S_AXI_HP1_ACLK), .s_axi_hp2_clk(S_AXI_HP2_ACLK), .s_axi_hp3_clk(S_AXI_HP3_ACLK), .s_axi_acp_clk(S_AXI_ACP_ACLK), .m_axi_gp0_rstn(net_axi_mgp0_rstn), .m_axi_gp1_rstn(net_axi_mgp1_rstn), .s_axi_gp0_rstn(net_axi_gp0_rstn), .s_axi_gp1_rstn(net_axi_gp1_rstn), .s_axi_hp0_rstn(net_axi_hp0_rstn), .s_axi_hp1_rstn(net_axi_hp1_rstn), .s_axi_hp2_rstn(net_axi_hp2_rstn), .s_axi_hp3_rstn(net_axi_hp3_rstn), .s_axi_acp_rstn(net_axi_acp_rstn), .fclk_reset3_n(FCLK_RESET3_N), .fclk_reset2_n(FCLK_RESET2_N), .fclk_reset1_n(FCLK_RESET1_N), .fclk_reset0_n(FCLK_RESET0_N), .fpga_acp_reset_n(), ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP) .fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN), .fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN), .fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN), .fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN), .fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN), .fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN), .fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN), .fpga_hp_s3_reset_n() ////S_AXI_HP3_ARESETN) ); /* Clock Generator */ processing_system7_bfm_v2_0_5_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ) gen_clk(.ps_clk(PS_CLK), .sw_clk(net_sw_clk), .fclk_clk3(FCLK_CLK3), .fclk_clk2(FCLK_CLK2), .fclk_clk1(FCLK_CLK1), .fclk_clk0(FCLK_CLK0) ); wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1; wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1; wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1; wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1; wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1; wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1; wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1; wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1; wire net_rd_req_reg_gp0, net_rd_req_reg_gp1; wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1; wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1; wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1; wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1; wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1; wire net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1; wire net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1; wire net_rd_dv_reg_gp0, net_rd_dv_reg_gp1; wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1; wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3; wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3; wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3; wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3; wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3; wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3; wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3; wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3; wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3; wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3; wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3; wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3; wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3; wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3; wire net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3; wire net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3; wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3; wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp; wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp; wire [max_burst_bits-1:0] net_wr_data_acp; wire [addr_width-1:0] net_wr_addr_acp; wire [max_burst_bytes_width:0] net_wr_bytes_acp; wire [axi_qos_width-1:0] net_wr_qos_acp; wire net_rd_req_ddr_acp, net_rd_req_ocm_acp; wire [addr_width-1:0] net_rd_addr_acp; wire [max_burst_bytes_width:0] net_rd_bytes_acp; wire [max_burst_bits-1:0] net_rd_data_ddr_acp; wire [max_burst_bits-1:0] net_rd_data_ocm_acp; wire net_rd_dv_ddr_acp,net_rd_dv_ocm_acp; wire [axi_qos_width-1:0] net_rd_qos_acp; wire ocm_wr_ack_port0; wire ocm_wr_dv_port0; wire ocm_rd_req_port0; wire ocm_rd_dv_port0; wire [addr_width-1:0] ocm_wr_addr_port0; wire [max_burst_bits-1:0] ocm_wr_data_port0; wire [max_burst_bytes_width:0] ocm_wr_bytes_port0; wire [addr_width-1:0] ocm_rd_addr_port0; wire [max_burst_bits-1:0] ocm_rd_data_port0; wire [max_burst_bytes_width:0] ocm_rd_bytes_port0; wire [axi_qos_width-1:0] ocm_wr_qos_port0; wire [axi_qos_width-1:0] ocm_rd_qos_port0; wire ocm_wr_ack_port1; wire ocm_wr_dv_port1; wire ocm_rd_req_port1; wire ocm_rd_dv_port1; wire [addr_width-1:0] ocm_wr_addr_port1; wire [max_burst_bits-1:0] ocm_wr_data_port1; wire [max_burst_bytes_width:0] ocm_wr_bytes_port1; wire [addr_width-1:0] ocm_rd_addr_port1; wire [max_burst_bits-1:0] ocm_rd_data_port1; wire [max_burst_bytes_width:0] ocm_rd_bytes_port1; wire [axi_qos_width-1:0] ocm_wr_qos_port1; wire [axi_qos_width-1:0] ocm_rd_qos_port1; wire ddr_wr_ack_port0; wire ddr_wr_dv_port0; wire ddr_rd_req_port0; wire ddr_rd_dv_port0; wire[addr_width-1:0] ddr_wr_addr_port0; wire[max_burst_bits-1:0] ddr_wr_data_port0; wire[max_burst_bytes_width:0] ddr_wr_bytes_port0; wire[addr_width-1:0] ddr_rd_addr_port0; wire[max_burst_bits-1:0] ddr_rd_data_port0; wire[max_burst_bytes_width:0] ddr_rd_bytes_port0; wire [axi_qos_width-1:0] ddr_wr_qos_port0; wire [axi_qos_width-1:0] ddr_rd_qos_port0; wire ddr_wr_ack_port1; wire ddr_wr_dv_port1; wire ddr_rd_req_port1; wire ddr_rd_dv_port1; wire[addr_width-1:0] ddr_wr_addr_port1; wire[max_burst_bits-1:0] ddr_wr_data_port1; wire[max_burst_bytes_width:0] ddr_wr_bytes_port1; wire[addr_width-1:0] ddr_rd_addr_port1; wire[max_burst_bits-1:0] ddr_rd_data_port1; wire[max_burst_bytes_width:0] ddr_rd_bytes_port1; wire[axi_qos_width-1:0] ddr_wr_qos_port1; wire[axi_qos_width-1:0] ddr_rd_qos_port1; wire ddr_wr_ack_port2; wire ddr_wr_dv_port2; wire ddr_rd_req_port2; wire ddr_rd_dv_port2; wire[addr_width-1:0] ddr_wr_addr_port2; wire[max_burst_bits-1:0] ddr_wr_data_port2; wire[max_burst_bytes_width:0] ddr_wr_bytes_port2; wire[addr_width-1:0] ddr_rd_addr_port2; wire[max_burst_bits-1:0] ddr_rd_data_port2; wire[max_burst_bytes_width:0] ddr_rd_bytes_port2; wire[axi_qos_width-1:0] ddr_wr_qos_port2; wire[axi_qos_width-1:0] ddr_rd_qos_port2; wire ddr_wr_ack_port3; wire ddr_wr_dv_port3; wire ddr_rd_req_port3; wire ddr_rd_dv_port3; wire[addr_width-1:0] ddr_wr_addr_port3; wire[max_burst_bits-1:0] ddr_wr_data_port3; wire[max_burst_bytes_width:0] ddr_wr_bytes_port3; wire[addr_width-1:0] ddr_rd_addr_port3; wire[max_burst_bits-1:0] ddr_rd_data_port3; wire[max_burst_bytes_width:0] ddr_rd_bytes_port3; wire[axi_qos_width-1:0] ddr_wr_qos_port3; wire[axi_qos_width-1:0] ddr_rd_qos_port3; wire reg_rd_req_port0; wire reg_rd_dv_port0; wire[addr_width-1:0] reg_rd_addr_port0; wire[max_burst_bits-1:0] reg_rd_data_port0; wire[max_burst_bytes_width:0] reg_rd_bytes_port0; wire [axi_qos_width-1:0] reg_rd_qos_port0; wire reg_rd_req_port1; wire reg_rd_dv_port1; wire[addr_width-1:0] reg_rd_addr_port1; wire[max_burst_bits-1:0] reg_rd_data_port1; wire[max_burst_bytes_width:0] reg_rd_bytes_port1; wire [axi_qos_width-1:0] reg_rd_qos_port1; wire [11:0] M_AXI_GP0_AWID_FULL; wire [11:0] M_AXI_GP0_WID_FULL; wire [11:0] M_AXI_GP0_ARID_FULL; wire [11:0] M_AXI_GP0_BID_FULL; wire [11:0] M_AXI_GP0_RID_FULL; wire [11:0] M_AXI_GP1_AWID_FULL; wire [11:0] M_AXI_GP1_WID_FULL; wire [11:0] M_AXI_GP1_ARID_FULL; wire [11:0] M_AXI_GP1_BID_FULL; wire [11:0] M_AXI_GP1_RID_FULL; function [5:0] compress_id; input [11:0] id; begin compress_id = id[5:0]; end endfunction function [11:0] uncompress_id; input [5:0] id; begin uncompress_id = {6'b110000, id[5:0]}; end endfunction assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL; assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL; assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL; assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID; assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID; assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL; assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL; assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL; assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID; assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID; processing_system7_bfm_v2_0_5_interconnect_model icm ( .rstn(net_rstn), .sw_clk(net_sw_clk), .w_qos_gp0(net_wr_qos_gp0), .w_qos_gp1(net_wr_qos_gp1), .w_qos_hp0(net_wr_qos_hp0), .w_qos_hp1(net_wr_qos_hp1), .w_qos_hp2(net_wr_qos_hp2), .w_qos_hp3(net_wr_qos_hp3), .r_qos_gp0(net_rd_qos_gp0), .r_qos_gp1(net_rd_qos_gp1), .r_qos_hp0(net_rd_qos_hp0), .r_qos_hp1(net_rd_qos_hp1), .r_qos_hp2(net_rd_qos_hp2), .r_qos_hp3(net_rd_qos_hp3), /* GP Slave ports access */ .wr_ack_ddr_gp0(net_wr_ack_ddr_gp0), .wr_ack_ocm_gp0(net_wr_ack_ocm_gp0), .wr_data_gp0(net_wr_data_gp0), .wr_addr_gp0(net_wr_addr_gp0), .wr_bytes_gp0(net_wr_bytes_gp0), .wr_dv_ddr_gp0(net_wr_dv_ddr_gp0), .wr_dv_ocm_gp0(net_wr_dv_ocm_gp0), .rd_req_ddr_gp0(net_rd_req_ddr_gp0), .rd_req_ocm_gp0(net_rd_req_ocm_gp0), .rd_req_reg_gp0(net_rd_req_reg_gp0), .rd_addr_gp0(net_rd_addr_gp0), .rd_bytes_gp0(net_rd_bytes_gp0), .rd_data_ddr_gp0(net_rd_data_ddr_gp0), .rd_data_ocm_gp0(net_rd_data_ocm_gp0), .rd_data_reg_gp0(net_rd_data_reg_gp0), .rd_dv_ddr_gp0(net_rd_dv_ddr_gp0), .rd_dv_ocm_gp0(net_rd_dv_ocm_gp0), .rd_dv_reg_gp0(net_rd_dv_reg_gp0), .wr_ack_ddr_gp1(net_wr_ack_ddr_gp1), .wr_ack_ocm_gp1(net_wr_ack_ocm_gp1), .wr_data_gp1(net_wr_data_gp1), .wr_addr_gp1(net_wr_addr_gp1), .wr_bytes_gp1(net_wr_bytes_gp1), .wr_dv_ddr_gp1(net_wr_dv_ddr_gp1), .wr_dv_ocm_gp1(net_wr_dv_ocm_gp1), .rd_req_ddr_gp1(net_rd_req_ddr_gp1), .rd_req_ocm_gp1(net_rd_req_ocm_gp1), .rd_req_reg_gp1(net_rd_req_reg_gp1), .rd_addr_gp1(net_rd_addr_gp1), .rd_bytes_gp1(net_rd_bytes_gp1), .rd_data_ddr_gp1(net_rd_data_ddr_gp1), .rd_data_ocm_gp1(net_rd_data_ocm_gp1), .rd_data_reg_gp1(net_rd_data_reg_gp1), .rd_dv_ddr_gp1(net_rd_dv_ddr_gp1), .rd_dv_ocm_gp1(net_rd_dv_ocm_gp1), .rd_dv_reg_gp1(net_rd_dv_reg_gp1), /* HP Slave ports access */ .wr_ack_ddr_hp0(net_wr_ack_ddr_hp0), .wr_ack_ocm_hp0(net_wr_ack_ocm_hp0), .wr_data_hp0(net_wr_data_hp0), .wr_addr_hp0(net_wr_addr_hp0), .wr_bytes_hp0(net_wr_bytes_hp0), .wr_dv_ddr_hp0(net_wr_dv_ddr_hp0), .wr_dv_ocm_hp0(net_wr_dv_ocm_hp0), .rd_req_ddr_hp0(net_rd_req_ddr_hp0), .rd_req_ocm_hp0(net_rd_req_ocm_hp0), .rd_addr_hp0(net_rd_addr_hp0), .rd_bytes_hp0(net_rd_bytes_hp0), .rd_data_ddr_hp0(net_rd_data_ddr_hp0), .rd_data_ocm_hp0(net_rd_data_ocm_hp0), .rd_dv_ddr_hp0(net_rd_dv_ddr_hp0), .rd_dv_ocm_hp0(net_rd_dv_ocm_hp0), .wr_ack_ddr_hp1(net_wr_ack_ddr_hp1), .wr_ack_ocm_hp1(net_wr_ack_ocm_hp1), .wr_data_hp1(net_wr_data_hp1), .wr_addr_hp1(net_wr_addr_hp1), .wr_bytes_hp1(net_wr_bytes_hp1), .wr_dv_ddr_hp1(net_wr_dv_ddr_hp1), .wr_dv_ocm_hp1(net_wr_dv_ocm_hp1), .rd_req_ddr_hp1(net_rd_req_ddr_hp1), .rd_req_ocm_hp1(net_rd_req_ocm_hp1), .rd_addr_hp1(net_rd_addr_hp1), .rd_bytes_hp1(net_rd_bytes_hp1), .rd_data_ddr_hp1(net_rd_data_ddr_hp1), .rd_data_ocm_hp1(net_rd_data_ocm_hp1), .rd_dv_ocm_hp1(net_rd_dv_ocm_hp1), .rd_dv_ddr_hp1(net_rd_dv_ddr_hp1), .wr_ack_ddr_hp2(net_wr_ack_ddr_hp2), .wr_ack_ocm_hp2(net_wr_ack_ocm_hp2), .wr_data_hp2(net_wr_data_hp2), .wr_addr_hp2(net_wr_addr_hp2), .wr_bytes_hp2(net_wr_bytes_hp2), .wr_dv_ocm_hp2(net_wr_dv_ocm_hp2), .wr_dv_ddr_hp2(net_wr_dv_ddr_hp2), .rd_req_ddr_hp2(net_rd_req_ddr_hp2), .rd_req_ocm_hp2(net_rd_req_ocm_hp2), .rd_addr_hp2(net_rd_addr_hp2), .rd_bytes_hp2(net_rd_bytes_hp2), .rd_data_ddr_hp2(net_rd_data_ddr_hp2), .rd_data_ocm_hp2(net_rd_data_ocm_hp2), .rd_dv_ddr_hp2(net_rd_dv_ddr_hp2), .rd_dv_ocm_hp2(net_rd_dv_ocm_hp2), .wr_ack_ocm_hp3(net_wr_ack_ocm_hp3), .wr_ack_ddr_hp3(net_wr_ack_ddr_hp3), .wr_data_hp3(net_wr_data_hp3), .wr_addr_hp3(net_wr_addr_hp3), .wr_bytes_hp3(net_wr_bytes_hp3), .wr_dv_ddr_hp3(net_wr_dv_ddr_hp3), .wr_dv_ocm_hp3(net_wr_dv_ocm_hp3), .rd_req_ddr_hp3(net_rd_req_ddr_hp3), .rd_req_ocm_hp3(net_rd_req_ocm_hp3), .rd_addr_hp3(net_rd_addr_hp3), .rd_bytes_hp3(net_rd_bytes_hp3), .rd_data_ddr_hp3(net_rd_data_ddr_hp3), .rd_data_ocm_hp3(net_rd_data_ocm_hp3), .rd_dv_ddr_hp3(net_rd_dv_ddr_hp3), .rd_dv_ocm_hp3(net_rd_dv_ocm_hp3), /* Goes to port 1 of DDR */ .ddr_wr_ack_port1(ddr_wr_ack_port1), .ddr_wr_dv_port1(ddr_wr_dv_port1), .ddr_rd_req_port1(ddr_rd_req_port1), .ddr_rd_dv_port1 (ddr_rd_dv_port1), .ddr_wr_addr_port1(ddr_wr_addr_port1), .ddr_wr_data_port1(ddr_wr_data_port1), .ddr_wr_bytes_port1(ddr_wr_bytes_port1), .ddr_rd_addr_port1(ddr_rd_addr_port1), .ddr_rd_data_port1(ddr_rd_data_port1), .ddr_rd_bytes_port1(ddr_rd_bytes_port1), .ddr_wr_qos_port1(ddr_wr_qos_port1), .ddr_rd_qos_port1(ddr_rd_qos_port1), /* Goes to port2 of DDR */ .ddr_wr_ack_port2 (ddr_wr_ack_port2), .ddr_wr_dv_port2 (ddr_wr_dv_port2), .ddr_rd_req_port2 (ddr_rd_req_port2), .ddr_rd_dv_port2 (ddr_rd_dv_port2), .ddr_wr_addr_port2(ddr_wr_addr_port2), .ddr_wr_data_port2(ddr_wr_data_port2), .ddr_wr_bytes_port2(ddr_wr_bytes_port2), .ddr_rd_addr_port2(ddr_rd_addr_port2), .ddr_rd_data_port2(ddr_rd_data_port2), .ddr_rd_bytes_port2(ddr_rd_bytes_port2), .ddr_wr_qos_port2 (ddr_wr_qos_port2), .ddr_rd_qos_port2 (ddr_rd_qos_port2), /* Goes to port3 of DDR */ .ddr_wr_ack_port3 (ddr_wr_ack_port3), .ddr_wr_dv_port3 (ddr_wr_dv_port3), .ddr_rd_req_port3 (ddr_rd_req_port3), .ddr_rd_dv_port3 (ddr_rd_dv_port3), .ddr_wr_addr_port3(ddr_wr_addr_port3), .ddr_wr_data_port3(ddr_wr_data_port3), .ddr_wr_bytes_port3(ddr_wr_bytes_port3), .ddr_rd_addr_port3(ddr_rd_addr_port3), .ddr_rd_data_port3(ddr_rd_data_port3), .ddr_rd_bytes_port3(ddr_rd_bytes_port3), .ddr_wr_qos_port3 (ddr_wr_qos_port3), .ddr_rd_qos_port3 (ddr_rd_qos_port3), /* Goes to port 0 of OCM */ .ocm_wr_ack_port1 (ocm_wr_ack_port1), .ocm_wr_dv_port1 (ocm_wr_dv_port1), .ocm_rd_req_port1 (ocm_rd_req_port1), .ocm_rd_dv_port1 (ocm_rd_dv_port1), .ocm_wr_addr_port1(ocm_wr_addr_port1), .ocm_wr_data_port1(ocm_wr_data_port1), .ocm_wr_bytes_port1(ocm_wr_bytes_port1), .ocm_rd_addr_port1(ocm_rd_addr_port1), .ocm_rd_data_port1(ocm_rd_data_port1), .ocm_rd_bytes_port1(ocm_rd_bytes_port1), .ocm_wr_qos_port1(ocm_wr_qos_port1), .ocm_rd_qos_port1(ocm_rd_qos_port1), /* Goes to port 0 of REG */ .reg_rd_qos_port1 (reg_rd_qos_port1) , .reg_rd_req_port1 (reg_rd_req_port1), .reg_rd_dv_port1 (reg_rd_dv_port1), .reg_rd_addr_port1(reg_rd_addr_port1), .reg_rd_data_port1(reg_rd_data_port1), .reg_rd_bytes_port1(reg_rd_bytes_port1) ); processing_system7_bfm_v2_0_5_ddrc ddrc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of DDR */ .ddr_wr_ack_port0 (ddr_wr_ack_port0), .ddr_wr_dv_port0 (ddr_wr_dv_port0), .ddr_rd_req_port0 (ddr_rd_req_port0), .ddr_rd_dv_port0 (ddr_rd_dv_port0), .ddr_wr_addr_port0(net_wr_addr_acp), .ddr_wr_data_port0(net_wr_data_acp), .ddr_wr_bytes_port0(net_wr_bytes_acp), .ddr_rd_addr_port0(net_rd_addr_acp), .ddr_rd_bytes_port0(net_rd_bytes_acp), .ddr_rd_data_port0(ddr_rd_data_port0), .ddr_wr_qos_port0 (net_wr_qos_acp), .ddr_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of DDR */ .ddr_wr_ack_port1 (ddr_wr_ack_port1), .ddr_wr_dv_port1 (ddr_wr_dv_port1), .ddr_rd_req_port1 (ddr_rd_req_port1), .ddr_rd_dv_port1 (ddr_rd_dv_port1), .ddr_wr_addr_port1(ddr_wr_addr_port1), .ddr_wr_data_port1(ddr_wr_data_port1), .ddr_wr_bytes_port1(ddr_wr_bytes_port1), .ddr_rd_addr_port1(ddr_rd_addr_port1), .ddr_rd_data_port1(ddr_rd_data_port1), .ddr_rd_bytes_port1(ddr_rd_bytes_port1), .ddr_wr_qos_port1 (ddr_wr_qos_port1), .ddr_rd_qos_port1 (ddr_rd_qos_port1), /* Goes to port2 of DDR */ .ddr_wr_ack_port2 (ddr_wr_ack_port2), .ddr_wr_dv_port2 (ddr_wr_dv_port2), .ddr_rd_req_port2 (ddr_rd_req_port2), .ddr_rd_dv_port2 (ddr_rd_dv_port2), .ddr_wr_addr_port2(ddr_wr_addr_port2), .ddr_wr_data_port2(ddr_wr_data_port2), .ddr_wr_bytes_port2(ddr_wr_bytes_port2), .ddr_rd_addr_port2(ddr_rd_addr_port2), .ddr_rd_data_port2(ddr_rd_data_port2), .ddr_rd_bytes_port2(ddr_rd_bytes_port2), .ddr_wr_qos_port2 (ddr_wr_qos_port2), .ddr_rd_qos_port2 (ddr_rd_qos_port2), /* Goes to port3 of DDR */ .ddr_wr_ack_port3 (ddr_wr_ack_port3), .ddr_wr_dv_port3 (ddr_wr_dv_port3), .ddr_rd_req_port3 (ddr_rd_req_port3), .ddr_rd_dv_port3 (ddr_rd_dv_port3), .ddr_wr_addr_port3(ddr_wr_addr_port3), .ddr_wr_data_port3(ddr_wr_data_port3), .ddr_wr_bytes_port3(ddr_wr_bytes_port3), .ddr_rd_addr_port3(ddr_rd_addr_port3), .ddr_rd_data_port3(ddr_rd_data_port3), .ddr_rd_bytes_port3(ddr_rd_bytes_port3), .ddr_wr_qos_port3 (ddr_wr_qos_port3), .ddr_rd_qos_port3 (ddr_rd_qos_port3) ); processing_system7_bfm_v2_0_5_ocmc ocmc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of OCM */ .ocm_wr_ack_port0 (ocm_wr_ack_port0), .ocm_wr_dv_port0 (ocm_wr_dv_port0), .ocm_rd_req_port0 (ocm_rd_req_port0), .ocm_rd_dv_port0 (ocm_rd_dv_port0), .ocm_wr_addr_port0(net_wr_addr_acp), .ocm_wr_data_port0(net_wr_data_acp), .ocm_wr_bytes_port0(net_wr_bytes_acp), .ocm_rd_addr_port0(net_rd_addr_acp), .ocm_rd_bytes_port0(net_rd_bytes_acp), .ocm_rd_data_port0(ocm_rd_data_port0), .ocm_wr_qos_port0 (net_wr_qos_acp), .ocm_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of OCM */ .ocm_wr_ack_port1 (ocm_wr_ack_port1), .ocm_wr_dv_port1 (ocm_wr_dv_port1), .ocm_rd_req_port1 (ocm_rd_req_port1), .ocm_rd_dv_port1 (ocm_rd_dv_port1), .ocm_wr_addr_port1(ocm_wr_addr_port1), .ocm_wr_data_port1(ocm_wr_data_port1), .ocm_wr_bytes_port1(ocm_wr_bytes_port1), .ocm_rd_addr_port1(ocm_rd_addr_port1), .ocm_rd_data_port1(ocm_rd_data_port1), .ocm_rd_bytes_port1(ocm_rd_bytes_port1), .ocm_wr_qos_port1(ocm_wr_qos_port1), .ocm_rd_qos_port1(ocm_rd_qos_port1) ); processing_system7_bfm_v2_0_5_regc regc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of REG */ .reg_rd_req_port0 (reg_rd_req_port0), .reg_rd_dv_port0 (reg_rd_dv_port0), .reg_rd_addr_port0(net_rd_addr_acp), .reg_rd_bytes_port0(net_rd_bytes_acp), .reg_rd_data_port0(reg_rd_data_port0), .reg_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of REG */ .reg_rd_req_port1 (reg_rd_req_port1), .reg_rd_dv_port1 (reg_rd_dv_port1), .reg_rd_addr_port1(reg_rd_addr_port1), .reg_rd_data_port1(reg_rd_data_port1), .reg_rd_bytes_port1(reg_rd_bytes_port1), .reg_rd_qos_port1(reg_rd_qos_port1) ); /* include axi_gp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_gp.v" /* include axi_hp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_hp.v" /* include axi_acp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_acp.v" endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_processing_system7_bfm.v * * Date : 2012-11 * * Description : Processing_system7_bfm Top (zynq_bfm top) * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_processing_system7_bfm ( CAN0_PHY_TX, CAN0_PHY_RX, CAN1_PHY_TX, CAN1_PHY_RX, ENET0_GMII_TX_EN, ENET0_GMII_TX_ER, ENET0_MDIO_MDC, ENET0_MDIO_O, ENET0_MDIO_T, ENET0_PTP_DELAY_REQ_RX, ENET0_PTP_DELAY_REQ_TX, ENET0_PTP_PDELAY_REQ_RX, ENET0_PTP_PDELAY_REQ_TX, ENET0_PTP_PDELAY_RESP_RX, ENET0_PTP_PDELAY_RESP_TX, ENET0_PTP_SYNC_FRAME_RX, ENET0_PTP_SYNC_FRAME_TX, ENET0_SOF_RX, ENET0_SOF_TX, ENET0_GMII_TXD, ENET0_GMII_COL, ENET0_GMII_CRS, ENET0_EXT_INTIN, ENET0_GMII_RX_CLK, ENET0_GMII_RX_DV, ENET0_GMII_RX_ER, ENET0_GMII_TX_CLK, ENET0_MDIO_I, ENET0_GMII_RXD, ENET1_GMII_TX_EN, ENET1_GMII_TX_ER, ENET1_MDIO_MDC, ENET1_MDIO_O, ENET1_MDIO_T, ENET1_PTP_DELAY_REQ_RX, ENET1_PTP_DELAY_REQ_TX, ENET1_PTP_PDELAY_REQ_RX, ENET1_PTP_PDELAY_REQ_TX, ENET1_PTP_PDELAY_RESP_RX, ENET1_PTP_PDELAY_RESP_TX, ENET1_PTP_SYNC_FRAME_RX, ENET1_PTP_SYNC_FRAME_TX, ENET1_SOF_RX, ENET1_SOF_TX, ENET1_GMII_TXD, ENET1_GMII_COL, ENET1_GMII_CRS, ENET1_EXT_INTIN, ENET1_GMII_RX_CLK, ENET1_GMII_RX_DV, ENET1_GMII_RX_ER, ENET1_GMII_TX_CLK, ENET1_MDIO_I, ENET1_GMII_RXD, GPIO_I, GPIO_O, GPIO_T, I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I, I2C0_SCL_O, I2C0_SCL_T, I2C1_SDA_I, I2C1_SDA_O, I2C1_SDA_T, I2C1_SCL_I, I2C1_SCL_O, I2C1_SCL_T, PJTAG_TCK, PJTAG_TMS, PJTAG_TD_I, PJTAG_TD_T, PJTAG_TD_O, SDIO0_CLK, SDIO0_CLK_FB, SDIO0_CMD_O, SDIO0_CMD_I, SDIO0_CMD_T, SDIO0_DATA_I, SDIO0_DATA_O, SDIO0_DATA_T, SDIO0_LED, SDIO0_CDN, SDIO0_WP, SDIO0_BUSPOW, SDIO0_BUSVOLT, SDIO1_CLK, SDIO1_CLK_FB, SDIO1_CMD_O, SDIO1_CMD_I, SDIO1_CMD_T, SDIO1_DATA_I, SDIO1_DATA_O, SDIO1_DATA_T, SDIO1_LED, SDIO1_CDN, SDIO1_WP, SDIO1_BUSPOW, SDIO1_BUSVOLT, SPI0_SCLK_I, SPI0_SCLK_O, SPI0_SCLK_T, SPI0_MOSI_I, SPI0_MOSI_O, SPI0_MOSI_T, SPI0_MISO_I, SPI0_MISO_O, SPI0_MISO_T, SPI0_SS_I, SPI0_SS_O, SPI0_SS1_O, SPI0_SS2_O, SPI0_SS_T, SPI1_SCLK_I, SPI1_SCLK_O, SPI1_SCLK_T, SPI1_MOSI_I, SPI1_MOSI_O, SPI1_MOSI_T, SPI1_MISO_I, SPI1_MISO_O, SPI1_MISO_T, SPI1_SS_I, SPI1_SS_O, SPI1_SS1_O, SPI1_SS2_O, SPI1_SS_T, UART0_DTRN, UART0_RTSN, UART0_TX, UART0_CTSN, UART0_DCDN, UART0_DSRN, UART0_RIN, UART0_RX, UART1_DTRN, UART1_RTSN, UART1_TX, UART1_CTSN, UART1_DCDN, UART1_DSRN, UART1_RIN, UART1_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, TTC0_CLK0_IN, TTC0_CLK1_IN, TTC0_CLK2_IN, TTC1_WAVE0_OUT, TTC1_WAVE1_OUT, TTC1_WAVE2_OUT, TTC1_CLK0_IN, TTC1_CLK1_IN, TTC1_CLK2_IN, WDT_CLK_IN, WDT_RST_OUT, TRACE_CLK, TRACE_CTL, TRACE_DATA, USB0_PORT_INDCTL, USB1_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB1_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, USB1_VBUS_PWRFAULT, SRAM_INTIN, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, M_AXI_GP1_ARVALID, M_AXI_GP1_AWVALID, M_AXI_GP1_BREADY, M_AXI_GP1_RREADY, M_AXI_GP1_WLAST, M_AXI_GP1_WVALID, M_AXI_GP1_ARID, M_AXI_GP1_AWID, M_AXI_GP1_WID, M_AXI_GP1_ARBURST, M_AXI_GP1_ARLOCK, M_AXI_GP1_ARSIZE, M_AXI_GP1_AWBURST, M_AXI_GP1_AWLOCK, M_AXI_GP1_AWSIZE, M_AXI_GP1_ARPROT, M_AXI_GP1_AWPROT, M_AXI_GP1_ARADDR, M_AXI_GP1_AWADDR, M_AXI_GP1_WDATA, M_AXI_GP1_ARCACHE, M_AXI_GP1_ARLEN, M_AXI_GP1_ARQOS, M_AXI_GP1_AWCACHE, M_AXI_GP1_AWLEN, M_AXI_GP1_AWQOS, M_AXI_GP1_WSTRB, M_AXI_GP1_ACLK, M_AXI_GP1_ARREADY, M_AXI_GP1_AWREADY, M_AXI_GP1_BVALID, M_AXI_GP1_RLAST, M_AXI_GP1_RVALID, M_AXI_GP1_WREADY, M_AXI_GP1_BID, M_AXI_GP1_RID, M_AXI_GP1_BRESP, M_AXI_GP1_RRESP, M_AXI_GP1_RDATA, S_AXI_GP0_ARREADY, S_AXI_GP0_AWREADY, S_AXI_GP0_BVALID, S_AXI_GP0_RLAST, S_AXI_GP0_RVALID, S_AXI_GP0_WREADY, S_AXI_GP0_BRESP, S_AXI_GP0_RRESP, S_AXI_GP0_RDATA, S_AXI_GP0_BID, S_AXI_GP0_RID, S_AXI_GP0_ACLK, S_AXI_GP0_ARVALID, S_AXI_GP0_AWVALID, S_AXI_GP0_BREADY, S_AXI_GP0_RREADY, S_AXI_GP0_WLAST, S_AXI_GP0_WVALID, S_AXI_GP0_ARBURST, S_AXI_GP0_ARLOCK, S_AXI_GP0_ARSIZE, S_AXI_GP0_AWBURST, S_AXI_GP0_AWLOCK, S_AXI_GP0_AWSIZE, S_AXI_GP0_ARPROT, S_AXI_GP0_AWPROT, S_AXI_GP0_ARADDR, S_AXI_GP0_AWADDR, S_AXI_GP0_WDATA, S_AXI_GP0_ARCACHE, S_AXI_GP0_ARLEN, S_AXI_GP0_ARQOS, S_AXI_GP0_AWCACHE, S_AXI_GP0_AWLEN, S_AXI_GP0_AWQOS, S_AXI_GP0_WSTRB, S_AXI_GP0_ARID, S_AXI_GP0_AWID, S_AXI_GP0_WID, S_AXI_GP1_ARREADY, S_AXI_GP1_AWREADY, S_AXI_GP1_BVALID, S_AXI_GP1_RLAST, S_AXI_GP1_RVALID, S_AXI_GP1_WREADY, S_AXI_GP1_BRESP, S_AXI_GP1_RRESP, S_AXI_GP1_RDATA, S_AXI_GP1_BID, S_AXI_GP1_RID, S_AXI_GP1_ACLK, S_AXI_GP1_ARVALID, S_AXI_GP1_AWVALID, S_AXI_GP1_BREADY, S_AXI_GP1_RREADY, S_AXI_GP1_WLAST, S_AXI_GP1_WVALID, S_AXI_GP1_ARBURST, S_AXI_GP1_ARLOCK, S_AXI_GP1_ARSIZE, S_AXI_GP1_AWBURST, S_AXI_GP1_AWLOCK, S_AXI_GP1_AWSIZE, S_AXI_GP1_ARPROT, S_AXI_GP1_AWPROT, S_AXI_GP1_ARADDR, S_AXI_GP1_AWADDR, S_AXI_GP1_WDATA, S_AXI_GP1_ARCACHE, S_AXI_GP1_ARLEN, S_AXI_GP1_ARQOS, S_AXI_GP1_AWCACHE, S_AXI_GP1_AWLEN, S_AXI_GP1_AWQOS, S_AXI_GP1_WSTRB, S_AXI_GP1_ARID, S_AXI_GP1_AWID, S_AXI_GP1_WID, S_AXI_ACP_AWREADY, S_AXI_ACP_ARREADY, S_AXI_ACP_BVALID, S_AXI_ACP_RLAST, S_AXI_ACP_RVALID, S_AXI_ACP_WREADY, S_AXI_ACP_BRESP, S_AXI_ACP_RRESP, S_AXI_ACP_BID, S_AXI_ACP_RID, S_AXI_ACP_RDATA, S_AXI_ACP_ACLK, S_AXI_ACP_ARVALID, S_AXI_ACP_AWVALID, S_AXI_ACP_BREADY, S_AXI_ACP_RREADY, S_AXI_ACP_WLAST, S_AXI_ACP_WVALID, S_AXI_ACP_ARID, S_AXI_ACP_ARPROT, S_AXI_ACP_AWID, S_AXI_ACP_AWPROT, S_AXI_ACP_WID, S_AXI_ACP_ARADDR, S_AXI_ACP_AWADDR, S_AXI_ACP_ARCACHE, S_AXI_ACP_ARLEN, S_AXI_ACP_ARQOS, S_AXI_ACP_AWCACHE, S_AXI_ACP_AWLEN, S_AXI_ACP_AWQOS, S_AXI_ACP_ARBURST, S_AXI_ACP_ARLOCK, S_AXI_ACP_ARSIZE, S_AXI_ACP_AWBURST, S_AXI_ACP_AWLOCK, S_AXI_ACP_AWSIZE, S_AXI_ACP_ARUSER, S_AXI_ACP_AWUSER, S_AXI_ACP_WDATA, S_AXI_ACP_WSTRB, S_AXI_HP0_ARREADY, S_AXI_HP0_AWREADY, S_AXI_HP0_BVALID, S_AXI_HP0_RLAST, S_AXI_HP0_RVALID, S_AXI_HP0_WREADY, S_AXI_HP0_BRESP, S_AXI_HP0_RRESP, S_AXI_HP0_BID, S_AXI_HP0_RID, S_AXI_HP0_RDATA, S_AXI_HP0_RCOUNT, S_AXI_HP0_WCOUNT, S_AXI_HP0_RACOUNT, S_AXI_HP0_WACOUNT, S_AXI_HP0_ACLK, S_AXI_HP0_ARVALID, S_AXI_HP0_AWVALID, S_AXI_HP0_BREADY, S_AXI_HP0_RDISSUECAP1_EN, S_AXI_HP0_RREADY, S_AXI_HP0_WLAST, S_AXI_HP0_WRISSUECAP1_EN, S_AXI_HP0_WVALID, S_AXI_HP0_ARBURST, S_AXI_HP0_ARLOCK, S_AXI_HP0_ARSIZE, S_AXI_HP0_AWBURST, S_AXI_HP0_AWLOCK, S_AXI_HP0_AWSIZE, S_AXI_HP0_ARPROT, S_AXI_HP0_AWPROT, S_AXI_HP0_ARADDR, S_AXI_HP0_AWADDR, S_AXI_HP0_ARCACHE, S_AXI_HP0_ARLEN, S_AXI_HP0_ARQOS, S_AXI_HP0_AWCACHE, S_AXI_HP0_AWLEN, S_AXI_HP0_AWQOS, S_AXI_HP0_ARID, S_AXI_HP0_AWID, S_AXI_HP0_WID, S_AXI_HP0_WDATA, S_AXI_HP0_WSTRB, S_AXI_HP1_ARREADY, S_AXI_HP1_AWREADY, S_AXI_HP1_BVALID, S_AXI_HP1_RLAST, S_AXI_HP1_RVALID, S_AXI_HP1_WREADY, S_AXI_HP1_BRESP, S_AXI_HP1_RRESP, S_AXI_HP1_BID, S_AXI_HP1_RID, S_AXI_HP1_RDATA, S_AXI_HP1_RCOUNT, S_AXI_HP1_WCOUNT, S_AXI_HP1_RACOUNT, S_AXI_HP1_WACOUNT, S_AXI_HP1_ACLK, S_AXI_HP1_ARVALID, S_AXI_HP1_AWVALID, S_AXI_HP1_BREADY, S_AXI_HP1_RDISSUECAP1_EN, S_AXI_HP1_RREADY, S_AXI_HP1_WLAST, S_AXI_HP1_WRISSUECAP1_EN, S_AXI_HP1_WVALID, S_AXI_HP1_ARBURST, S_AXI_HP1_ARLOCK, S_AXI_HP1_ARSIZE, S_AXI_HP1_AWBURST, S_AXI_HP1_AWLOCK, S_AXI_HP1_AWSIZE, S_AXI_HP1_ARPROT, S_AXI_HP1_AWPROT, S_AXI_HP1_ARADDR, S_AXI_HP1_AWADDR, S_AXI_HP1_ARCACHE, S_AXI_HP1_ARLEN, S_AXI_HP1_ARQOS, S_AXI_HP1_AWCACHE, S_AXI_HP1_AWLEN, S_AXI_HP1_AWQOS, S_AXI_HP1_ARID, S_AXI_HP1_AWID, S_AXI_HP1_WID, S_AXI_HP1_WDATA, S_AXI_HP1_WSTRB, S_AXI_HP2_ARREADY, S_AXI_HP2_AWREADY, S_AXI_HP2_BVALID, S_AXI_HP2_RLAST, S_AXI_HP2_RVALID, S_AXI_HP2_WREADY, S_AXI_HP2_BRESP, S_AXI_HP2_RRESP, S_AXI_HP2_BID, S_AXI_HP2_RID, S_AXI_HP2_RDATA, S_AXI_HP2_RCOUNT, S_AXI_HP2_WCOUNT, S_AXI_HP2_RACOUNT, S_AXI_HP2_WACOUNT, S_AXI_HP2_ACLK, S_AXI_HP2_ARVALID, S_AXI_HP2_AWVALID, S_AXI_HP2_BREADY, S_AXI_HP2_RDISSUECAP1_EN, S_AXI_HP2_RREADY, S_AXI_HP2_WLAST, S_AXI_HP2_WRISSUECAP1_EN, S_AXI_HP2_WVALID, S_AXI_HP2_ARBURST, S_AXI_HP2_ARLOCK, S_AXI_HP2_ARSIZE, S_AXI_HP2_AWBURST, S_AXI_HP2_AWLOCK, S_AXI_HP2_AWSIZE, S_AXI_HP2_ARPROT, S_AXI_HP2_AWPROT, S_AXI_HP2_ARADDR, S_AXI_HP2_AWADDR, S_AXI_HP2_ARCACHE, S_AXI_HP2_ARLEN, S_AXI_HP2_ARQOS, S_AXI_HP2_AWCACHE, S_AXI_HP2_AWLEN, S_AXI_HP2_AWQOS, S_AXI_HP2_ARID, S_AXI_HP2_AWID, S_AXI_HP2_WID, S_AXI_HP2_WDATA, S_AXI_HP2_WSTRB, S_AXI_HP3_ARREADY, S_AXI_HP3_AWREADY, S_AXI_HP3_BVALID, S_AXI_HP3_RLAST, S_AXI_HP3_RVALID, S_AXI_HP3_WREADY, S_AXI_HP3_BRESP, S_AXI_HP3_RRESP, S_AXI_HP3_BID, S_AXI_HP3_RID, S_AXI_HP3_RDATA, S_AXI_HP3_RCOUNT, S_AXI_HP3_WCOUNT, S_AXI_HP3_RACOUNT, S_AXI_HP3_WACOUNT, S_AXI_HP3_ACLK, S_AXI_HP3_ARVALID, S_AXI_HP3_AWVALID, S_AXI_HP3_BREADY, S_AXI_HP3_RDISSUECAP1_EN, S_AXI_HP3_RREADY, S_AXI_HP3_WLAST, S_AXI_HP3_WRISSUECAP1_EN, S_AXI_HP3_WVALID, S_AXI_HP3_ARBURST, S_AXI_HP3_ARLOCK, S_AXI_HP3_ARSIZE, S_AXI_HP3_AWBURST, S_AXI_HP3_AWLOCK, S_AXI_HP3_AWSIZE, S_AXI_HP3_ARPROT, S_AXI_HP3_AWPROT, S_AXI_HP3_ARADDR, S_AXI_HP3_AWADDR, S_AXI_HP3_ARCACHE, S_AXI_HP3_ARLEN, S_AXI_HP3_ARQOS, S_AXI_HP3_AWCACHE, S_AXI_HP3_AWLEN, S_AXI_HP3_AWQOS, S_AXI_HP3_ARID, S_AXI_HP3_AWID, S_AXI_HP3_WID, S_AXI_HP3_WDATA, S_AXI_HP3_WSTRB, DMA0_DATYPE, DMA0_DAVALID, DMA0_DRREADY, DMA0_ACLK, DMA0_DAREADY, DMA0_DRLAST, DMA0_DRVALID, DMA0_DRTYPE, DMA1_DATYPE, DMA1_DAVALID, DMA1_DRREADY, DMA1_ACLK, DMA1_DAREADY, DMA1_DRLAST, DMA1_DRVALID, DMA1_DRTYPE, DMA2_DATYPE, DMA2_DAVALID, DMA2_DRREADY, DMA2_ACLK, DMA2_DAREADY, DMA2_DRLAST, DMA2_DRVALID, DMA3_DRVALID, DMA3_DATYPE, DMA3_DAVALID, DMA3_DRREADY, DMA3_ACLK, DMA3_DAREADY, DMA3_DRLAST, DMA2_DRTYPE, DMA3_DRTYPE, FTMD_TRACEIN_DATA, FTMD_TRACEIN_VALID, FTMD_TRACEIN_CLK, FTMD_TRACEIN_ATID, FTMT_F2P_TRIG, FTMT_F2P_TRIGACK, FTMT_F2P_DEBUG, FTMT_P2F_TRIGACK, FTMT_P2F_TRIG, FTMT_P2F_DEBUG, FCLK_CLK3, FCLK_CLK2, FCLK_CLK1, FCLK_CLK0, FCLK_CLKTRIG3_N, FCLK_CLKTRIG2_N, FCLK_CLKTRIG1_N, FCLK_CLKTRIG0_N, FCLK_RESET3_N, FCLK_RESET2_N, FCLK_RESET1_N, FCLK_RESET0_N, FPGA_IDLE_N, DDR_ARB, IRQ_F2P, Core0_nFIQ, Core0_nIRQ, Core1_nFIQ, Core1_nIRQ, EVENT_EVENTO, EVENT_STANDBYWFE, EVENT_STANDBYWFI, EVENT_EVENTI, MIO, DDR_Clk, DDR_Clk_n, DDR_CKE, DDR_CS_n, DDR_RAS_n, DDR_CAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_ODT, DDR_DRSTB, DDR_DQ, DDR_DM, DDR_DQS, DDR_DQS_n, DDR_VRN, DDR_VRP, PS_SRSTB, PS_CLK, PS_PORB, IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC0, IRQ_P2F_DMAC1, IRQ_P2F_DMAC2, IRQ_P2F_DMAC3, IRQ_P2F_DMAC4, IRQ_P2F_DMAC5, IRQ_P2F_DMAC6, IRQ_P2F_DMAC7, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1 ); /* parameters for gen_clk */ parameter C_FCLK_CLK0_FREQ = 50; parameter C_FCLK_CLK1_FREQ = 50; parameter C_FCLK_CLK3_FREQ = 50; parameter C_FCLK_CLK2_FREQ = 50; parameter C_HIGH_OCM_EN = 0; /* parameters for HP ports */ parameter C_USE_S_AXI_HP0 = 0; parameter C_USE_S_AXI_HP1 = 0; parameter C_USE_S_AXI_HP2 = 0; parameter C_USE_S_AXI_HP3 = 0; parameter C_S_AXI_HP0_DATA_WIDTH = 32; parameter C_S_AXI_HP1_DATA_WIDTH = 32; parameter C_S_AXI_HP2_DATA_WIDTH = 32; parameter C_S_AXI_HP3_DATA_WIDTH = 32; parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12; parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12; parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0; parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0; /* Do we need these parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0; parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */ parameter C_S_AXI_HP0_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP1_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP2_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP3_BASEADDR = 32'h0000_0000; parameter C_S_AXI_HP0_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP1_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP2_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_HP3_HIGHADDR = 32'hFFFF_FFFF; /* parameters for GP and ACP ports */ parameter C_USE_M_AXI_GP0 = 0; parameter C_USE_M_AXI_GP1 = 0; parameter C_USE_S_AXI_GP0 = 1; parameter C_USE_S_AXI_GP1 = 1; /* Do we need this? parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0; parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0; parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0; parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/ parameter C_S_AXI_GP0_BASEADDR = 32'h0000_0000; parameter C_S_AXI_GP1_BASEADDR = 32'h0000_0000; parameter C_S_AXI_GP0_HIGHADDR = 32'hFFFF_FFFF; parameter C_S_AXI_GP1_HIGHADDR = 32'hFFFF_FFFF; parameter C_USE_S_AXI_ACP = 1; parameter C_S_AXI_ACP_BASEADDR = 32'h0000_0000; parameter C_S_AXI_ACP_HIGHADDR = 32'hFFFF_FFFF; `include "processing_system7_bfm_v2_0_5_local_params.v" output CAN0_PHY_TX; input CAN0_PHY_RX; output CAN1_PHY_TX; input CAN1_PHY_RX; output ENET0_GMII_TX_EN; output ENET0_GMII_TX_ER; output ENET0_MDIO_MDC; output ENET0_MDIO_O; output ENET0_MDIO_T; output ENET0_PTP_DELAY_REQ_RX; output ENET0_PTP_DELAY_REQ_TX; output ENET0_PTP_PDELAY_REQ_RX; output ENET0_PTP_PDELAY_REQ_TX; output ENET0_PTP_PDELAY_RESP_RX; output ENET0_PTP_PDELAY_RESP_TX; output ENET0_PTP_SYNC_FRAME_RX; output ENET0_PTP_SYNC_FRAME_TX; output ENET0_SOF_RX; output ENET0_SOF_TX; output [7:0] ENET0_GMII_TXD; input ENET0_GMII_COL; input ENET0_GMII_CRS; input ENET0_EXT_INTIN; input ENET0_GMII_RX_CLK; input ENET0_GMII_RX_DV; input ENET0_GMII_RX_ER; input ENET0_GMII_TX_CLK; input ENET0_MDIO_I; input [7:0] ENET0_GMII_RXD; output ENET1_GMII_TX_EN; output ENET1_GMII_TX_ER; output ENET1_MDIO_MDC; output ENET1_MDIO_O; output ENET1_MDIO_T; output ENET1_PTP_DELAY_REQ_RX; output ENET1_PTP_DELAY_REQ_TX; output ENET1_PTP_PDELAY_REQ_RX; output ENET1_PTP_PDELAY_REQ_TX; output ENET1_PTP_PDELAY_RESP_RX; output ENET1_PTP_PDELAY_RESP_TX; output ENET1_PTP_SYNC_FRAME_RX; output ENET1_PTP_SYNC_FRAME_TX; output ENET1_SOF_RX; output ENET1_SOF_TX; output [7:0] ENET1_GMII_TXD; input ENET1_GMII_COL; input ENET1_GMII_CRS; input ENET1_EXT_INTIN; input ENET1_GMII_RX_CLK; input ENET1_GMII_RX_DV; input ENET1_GMII_RX_ER; input ENET1_GMII_TX_CLK; input ENET1_MDIO_I; input [7:0] ENET1_GMII_RXD; input [63:0] GPIO_I; output [63:0] GPIO_O; output [63:0] GPIO_T; input I2C0_SDA_I; output I2C0_SDA_O; output I2C0_SDA_T; input I2C0_SCL_I; output I2C0_SCL_O; output I2C0_SCL_T; input I2C1_SDA_I; output I2C1_SDA_O; output I2C1_SDA_T; input I2C1_SCL_I; output I2C1_SCL_O; output I2C1_SCL_T; input PJTAG_TCK; input PJTAG_TMS; input PJTAG_TD_I; output PJTAG_TD_T; output PJTAG_TD_O; output SDIO0_CLK; input SDIO0_CLK_FB; output SDIO0_CMD_O; input SDIO0_CMD_I; output SDIO0_CMD_T; input [3:0] SDIO0_DATA_I; output [3:0] SDIO0_DATA_O; output [3:0] SDIO0_DATA_T; output SDIO0_LED; input SDIO0_CDN; input SDIO0_WP; output SDIO0_BUSPOW; output [2:0] SDIO0_BUSVOLT; output SDIO1_CLK; input SDIO1_CLK_FB; output SDIO1_CMD_O; input SDIO1_CMD_I; output SDIO1_CMD_T; input [3:0] SDIO1_DATA_I; output [3:0] SDIO1_DATA_O; output [3:0] SDIO1_DATA_T; output SDIO1_LED; input SDIO1_CDN; input SDIO1_WP; output SDIO1_BUSPOW; output [2:0] SDIO1_BUSVOLT; input SPI0_SCLK_I; output SPI0_SCLK_O; output SPI0_SCLK_T; input SPI0_MOSI_I; output SPI0_MOSI_O; output SPI0_MOSI_T; input SPI0_MISO_I; output SPI0_MISO_O; output SPI0_MISO_T; input SPI0_SS_I; output SPI0_SS_O; output SPI0_SS1_O; output SPI0_SS2_O; output SPI0_SS_T; input SPI1_SCLK_I; output SPI1_SCLK_O; output SPI1_SCLK_T; input SPI1_MOSI_I; output SPI1_MOSI_O; output SPI1_MOSI_T; input SPI1_MISO_I; output SPI1_MISO_O; output SPI1_MISO_T; input SPI1_SS_I; output SPI1_SS_O; output SPI1_SS1_O; output SPI1_SS2_O; output SPI1_SS_T; output UART0_DTRN; output UART0_RTSN; output UART0_TX; input UART0_CTSN; input UART0_DCDN; input UART0_DSRN; input UART0_RIN; input UART0_RX; output UART1_DTRN; output UART1_RTSN; output UART1_TX; input UART1_CTSN; input UART1_DCDN; input UART1_DSRN; input UART1_RIN; input UART1_RX; output TTC0_WAVE0_OUT; output TTC0_WAVE1_OUT; output TTC0_WAVE2_OUT; input TTC0_CLK0_IN; input TTC0_CLK1_IN; input TTC0_CLK2_IN; output TTC1_WAVE0_OUT; output TTC1_WAVE1_OUT; output TTC1_WAVE2_OUT; input TTC1_CLK0_IN; input TTC1_CLK1_IN; input TTC1_CLK2_IN; input WDT_CLK_IN; output WDT_RST_OUT; input TRACE_CLK; output TRACE_CTL; output [31:0] TRACE_DATA; output [1:0] USB0_PORT_INDCTL; output [1:0] USB1_PORT_INDCTL; output USB0_VBUS_PWRSELECT; output USB1_VBUS_PWRSELECT; input USB0_VBUS_PWRFAULT; input USB1_VBUS_PWRFAULT; input SRAM_INTIN; output M_AXI_GP0_ARVALID; output M_AXI_GP0_AWVALID; output M_AXI_GP0_BREADY; output M_AXI_GP0_RREADY; output M_AXI_GP0_WLAST; output M_AXI_GP0_WVALID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID; output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID; output [1:0] M_AXI_GP0_ARBURST; output [1:0] M_AXI_GP0_ARLOCK; output [2:0] M_AXI_GP0_ARSIZE; output [1:0] M_AXI_GP0_AWBURST; output [1:0] M_AXI_GP0_AWLOCK; output [2:0] M_AXI_GP0_AWSIZE; output [2:0] M_AXI_GP0_ARPROT; output [2:0] M_AXI_GP0_AWPROT; output [31:0] M_AXI_GP0_ARADDR; output [31:0] M_AXI_GP0_AWADDR; output [31:0] M_AXI_GP0_WDATA; output [3:0] M_AXI_GP0_ARCACHE; output [3:0] M_AXI_GP0_ARLEN; output [3:0] M_AXI_GP0_ARQOS; output [3:0] M_AXI_GP0_AWCACHE; output [3:0] M_AXI_GP0_AWLEN; output [3:0] M_AXI_GP0_AWQOS; output [3:0] M_AXI_GP0_WSTRB; input M_AXI_GP0_ACLK; input M_AXI_GP0_ARREADY; input M_AXI_GP0_AWREADY; input M_AXI_GP0_BVALID; input M_AXI_GP0_RLAST; input M_AXI_GP0_RVALID; input M_AXI_GP0_WREADY; input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID; input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID; input [1:0] M_AXI_GP0_BRESP; input [1:0] M_AXI_GP0_RRESP; input [31:0] M_AXI_GP0_RDATA; output M_AXI_GP1_ARVALID; output M_AXI_GP1_AWVALID; output M_AXI_GP1_BREADY; output M_AXI_GP1_RREADY; output M_AXI_GP1_WLAST; output M_AXI_GP1_WVALID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID; output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID; output [1:0] M_AXI_GP1_ARBURST; output [1:0] M_AXI_GP1_ARLOCK; output [2:0] M_AXI_GP1_ARSIZE; output [1:0] M_AXI_GP1_AWBURST; output [1:0] M_AXI_GP1_AWLOCK; output [2:0] M_AXI_GP1_AWSIZE; output [2:0] M_AXI_GP1_ARPROT; output [2:0] M_AXI_GP1_AWPROT; output [31:0] M_AXI_GP1_ARADDR; output [31:0] M_AXI_GP1_AWADDR; output [31:0] M_AXI_GP1_WDATA; output [3:0] M_AXI_GP1_ARCACHE; output [3:0] M_AXI_GP1_ARLEN; output [3:0] M_AXI_GP1_ARQOS; output [3:0] M_AXI_GP1_AWCACHE; output [3:0] M_AXI_GP1_AWLEN; output [3:0] M_AXI_GP1_AWQOS; output [3:0] M_AXI_GP1_WSTRB; input M_AXI_GP1_ACLK; input M_AXI_GP1_ARREADY; input M_AXI_GP1_AWREADY; input M_AXI_GP1_BVALID; input M_AXI_GP1_RLAST; input M_AXI_GP1_RVALID; input M_AXI_GP1_WREADY; input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID; input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID; input [1:0] M_AXI_GP1_BRESP; input [1:0] M_AXI_GP1_RRESP; input [31:0] M_AXI_GP1_RDATA; output S_AXI_GP0_ARREADY; output S_AXI_GP0_AWREADY; output S_AXI_GP0_BVALID; output S_AXI_GP0_RLAST; output S_AXI_GP0_RVALID; output S_AXI_GP0_WREADY; output [1:0] S_AXI_GP0_BRESP; output [1:0] S_AXI_GP0_RRESP; output [31:0] S_AXI_GP0_RDATA; output [5:0] S_AXI_GP0_BID; output [5:0] S_AXI_GP0_RID; input S_AXI_GP0_ACLK; input S_AXI_GP0_ARVALID; input S_AXI_GP0_AWVALID; input S_AXI_GP0_BREADY; input S_AXI_GP0_RREADY; input S_AXI_GP0_WLAST; input S_AXI_GP0_WVALID; input [1:0] S_AXI_GP0_ARBURST; input [1:0] S_AXI_GP0_ARLOCK; input [2:0] S_AXI_GP0_ARSIZE; input [1:0] S_AXI_GP0_AWBURST; input [1:0] S_AXI_GP0_AWLOCK; input [2:0] S_AXI_GP0_AWSIZE; input [2:0] S_AXI_GP0_ARPROT; input [2:0] S_AXI_GP0_AWPROT; input [31:0] S_AXI_GP0_ARADDR; input [31:0] S_AXI_GP0_AWADDR; input [31:0] S_AXI_GP0_WDATA; input [3:0] S_AXI_GP0_ARCACHE; input [3:0] S_AXI_GP0_ARLEN; input [3:0] S_AXI_GP0_ARQOS; input [3:0] S_AXI_GP0_AWCACHE; input [3:0] S_AXI_GP0_AWLEN; input [3:0] S_AXI_GP0_AWQOS; input [3:0] S_AXI_GP0_WSTRB; input [5:0] S_AXI_GP0_ARID; input [5:0] S_AXI_GP0_AWID; input [5:0] S_AXI_GP0_WID; output S_AXI_GP1_ARREADY; output S_AXI_GP1_AWREADY; output S_AXI_GP1_BVALID; output S_AXI_GP1_RLAST; output S_AXI_GP1_RVALID; output S_AXI_GP1_WREADY; output [1:0] S_AXI_GP1_BRESP; output [1:0] S_AXI_GP1_RRESP; output [31:0] S_AXI_GP1_RDATA; output [5:0] S_AXI_GP1_BID; output [5:0] S_AXI_GP1_RID; input S_AXI_GP1_ACLK; input S_AXI_GP1_ARVALID; input S_AXI_GP1_AWVALID; input S_AXI_GP1_BREADY; input S_AXI_GP1_RREADY; input S_AXI_GP1_WLAST; input S_AXI_GP1_WVALID; input [1:0] S_AXI_GP1_ARBURST; input [1:0] S_AXI_GP1_ARLOCK; input [2:0] S_AXI_GP1_ARSIZE; input [1:0] S_AXI_GP1_AWBURST; input [1:0] S_AXI_GP1_AWLOCK; input [2:0] S_AXI_GP1_AWSIZE; input [2:0] S_AXI_GP1_ARPROT; input [2:0] S_AXI_GP1_AWPROT; input [31:0] S_AXI_GP1_ARADDR; input [31:0] S_AXI_GP1_AWADDR; input [31:0] S_AXI_GP1_WDATA; input [3:0] S_AXI_GP1_ARCACHE; input [3:0] S_AXI_GP1_ARLEN; input [3:0] S_AXI_GP1_ARQOS; input [3:0] S_AXI_GP1_AWCACHE; input [3:0] S_AXI_GP1_AWLEN; input [3:0] S_AXI_GP1_AWQOS; input [3:0] S_AXI_GP1_WSTRB; input [5:0] S_AXI_GP1_ARID; input [5:0] S_AXI_GP1_AWID; input [5:0] S_AXI_GP1_WID; output S_AXI_ACP_AWREADY; output S_AXI_ACP_ARREADY; output S_AXI_ACP_BVALID; output S_AXI_ACP_RLAST; output S_AXI_ACP_RVALID; output S_AXI_ACP_WREADY; output [1:0] S_AXI_ACP_BRESP; output [1:0] S_AXI_ACP_RRESP; output [2:0] S_AXI_ACP_BID; output [2:0] S_AXI_ACP_RID; output [63:0] S_AXI_ACP_RDATA; input S_AXI_ACP_ACLK; input S_AXI_ACP_ARVALID; input S_AXI_ACP_AWVALID; input S_AXI_ACP_BREADY; input S_AXI_ACP_RREADY; input S_AXI_ACP_WLAST; input S_AXI_ACP_WVALID; input [2:0] S_AXI_ACP_ARID; input [2:0] S_AXI_ACP_ARPROT; input [2:0] S_AXI_ACP_AWID; input [2:0] S_AXI_ACP_AWPROT; input [2:0] S_AXI_ACP_WID; input [31:0] S_AXI_ACP_ARADDR; input [31:0] S_AXI_ACP_AWADDR; input [3:0] S_AXI_ACP_ARCACHE; input [3:0] S_AXI_ACP_ARLEN; input [3:0] S_AXI_ACP_ARQOS; input [3:0] S_AXI_ACP_AWCACHE; input [3:0] S_AXI_ACP_AWLEN; input [3:0] S_AXI_ACP_AWQOS; input [1:0] S_AXI_ACP_ARBURST; input [1:0] S_AXI_ACP_ARLOCK; input [2:0] S_AXI_ACP_ARSIZE; input [1:0] S_AXI_ACP_AWBURST; input [1:0] S_AXI_ACP_AWLOCK; input [2:0] S_AXI_ACP_AWSIZE; input [4:0] S_AXI_ACP_ARUSER; input [4:0] S_AXI_ACP_AWUSER; input [63:0] S_AXI_ACP_WDATA; input [7:0] S_AXI_ACP_WSTRB; output S_AXI_HP0_ARREADY; output S_AXI_HP0_AWREADY; output S_AXI_HP0_BVALID; output S_AXI_HP0_RLAST; output S_AXI_HP0_RVALID; output S_AXI_HP0_WREADY; output [1:0] S_AXI_HP0_BRESP; output [1:0] S_AXI_HP0_RRESP; output [5:0] S_AXI_HP0_BID; output [5:0] S_AXI_HP0_RID; output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA; output [7:0] S_AXI_HP0_RCOUNT; output [7:0] S_AXI_HP0_WCOUNT; output [2:0] S_AXI_HP0_RACOUNT; output [5:0] S_AXI_HP0_WACOUNT; input S_AXI_HP0_ACLK; input S_AXI_HP0_ARVALID; input S_AXI_HP0_AWVALID; input S_AXI_HP0_BREADY; input S_AXI_HP0_RDISSUECAP1_EN; input S_AXI_HP0_RREADY; input S_AXI_HP0_WLAST; input S_AXI_HP0_WRISSUECAP1_EN; input S_AXI_HP0_WVALID; input [1:0] S_AXI_HP0_ARBURST; input [1:0] S_AXI_HP0_ARLOCK; input [2:0] S_AXI_HP0_ARSIZE; input [1:0] S_AXI_HP0_AWBURST; input [1:0] S_AXI_HP0_AWLOCK; input [2:0] S_AXI_HP0_AWSIZE; input [2:0] S_AXI_HP0_ARPROT; input [2:0] S_AXI_HP0_AWPROT; input [31:0] S_AXI_HP0_ARADDR; input [31:0] S_AXI_HP0_AWADDR; input [3:0] S_AXI_HP0_ARCACHE; input [3:0] S_AXI_HP0_ARLEN; input [3:0] S_AXI_HP0_ARQOS; input [3:0] S_AXI_HP0_AWCACHE; input [3:0] S_AXI_HP0_AWLEN; input [3:0] S_AXI_HP0_AWQOS; input [5:0] S_AXI_HP0_ARID; input [5:0] S_AXI_HP0_AWID; input [5:0] S_AXI_HP0_WID; input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA; input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB; output S_AXI_HP1_ARREADY; output S_AXI_HP1_AWREADY; output S_AXI_HP1_BVALID; output S_AXI_HP1_RLAST; output S_AXI_HP1_RVALID; output S_AXI_HP1_WREADY; output [1:0] S_AXI_HP1_BRESP; output [1:0] S_AXI_HP1_RRESP; output [5:0] S_AXI_HP1_BID; output [5:0] S_AXI_HP1_RID; output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA; output [7:0] S_AXI_HP1_RCOUNT; output [7:0] S_AXI_HP1_WCOUNT; output [2:0] S_AXI_HP1_RACOUNT; output [5:0] S_AXI_HP1_WACOUNT; input S_AXI_HP1_ACLK; input S_AXI_HP1_ARVALID; input S_AXI_HP1_AWVALID; input S_AXI_HP1_BREADY; input S_AXI_HP1_RDISSUECAP1_EN; input S_AXI_HP1_RREADY; input S_AXI_HP1_WLAST; input S_AXI_HP1_WRISSUECAP1_EN; input S_AXI_HP1_WVALID; input [1:0] S_AXI_HP1_ARBURST; input [1:0] S_AXI_HP1_ARLOCK; input [2:0] S_AXI_HP1_ARSIZE; input [1:0] S_AXI_HP1_AWBURST; input [1:0] S_AXI_HP1_AWLOCK; input [2:0] S_AXI_HP1_AWSIZE; input [2:0] S_AXI_HP1_ARPROT; input [2:0] S_AXI_HP1_AWPROT; input [31:0] S_AXI_HP1_ARADDR; input [31:0] S_AXI_HP1_AWADDR; input [3:0] S_AXI_HP1_ARCACHE; input [3:0] S_AXI_HP1_ARLEN; input [3:0] S_AXI_HP1_ARQOS; input [3:0] S_AXI_HP1_AWCACHE; input [3:0] S_AXI_HP1_AWLEN; input [3:0] S_AXI_HP1_AWQOS; input [5:0] S_AXI_HP1_ARID; input [5:0] S_AXI_HP1_AWID; input [5:0] S_AXI_HP1_WID; input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA; input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB; output S_AXI_HP2_ARREADY; output S_AXI_HP2_AWREADY; output S_AXI_HP2_BVALID; output S_AXI_HP2_RLAST; output S_AXI_HP2_RVALID; output S_AXI_HP2_WREADY; output [1:0] S_AXI_HP2_BRESP; output [1:0] S_AXI_HP2_RRESP; output [5:0] S_AXI_HP2_BID; output [5:0] S_AXI_HP2_RID; output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA; output [7:0] S_AXI_HP2_RCOUNT; output [7:0] S_AXI_HP2_WCOUNT; output [2:0] S_AXI_HP2_RACOUNT; output [5:0] S_AXI_HP2_WACOUNT; input S_AXI_HP2_ACLK; input S_AXI_HP2_ARVALID; input S_AXI_HP2_AWVALID; input S_AXI_HP2_BREADY; input S_AXI_HP2_RDISSUECAP1_EN; input S_AXI_HP2_RREADY; input S_AXI_HP2_WLAST; input S_AXI_HP2_WRISSUECAP1_EN; input S_AXI_HP2_WVALID; input [1:0] S_AXI_HP2_ARBURST; input [1:0] S_AXI_HP2_ARLOCK; input [2:0] S_AXI_HP2_ARSIZE; input [1:0] S_AXI_HP2_AWBURST; input [1:0] S_AXI_HP2_AWLOCK; input [2:0] S_AXI_HP2_AWSIZE; input [2:0] S_AXI_HP2_ARPROT; input [2:0] S_AXI_HP2_AWPROT; input [31:0] S_AXI_HP2_ARADDR; input [31:0] S_AXI_HP2_AWADDR; input [3:0] S_AXI_HP2_ARCACHE; input [3:0] S_AXI_HP2_ARLEN; input [3:0] S_AXI_HP2_ARQOS; input [3:0] S_AXI_HP2_AWCACHE; input [3:0] S_AXI_HP2_AWLEN; input [3:0] S_AXI_HP2_AWQOS; input [5:0] S_AXI_HP2_ARID; input [5:0] S_AXI_HP2_AWID; input [5:0] S_AXI_HP2_WID; input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA; input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB; output S_AXI_HP3_ARREADY; output S_AXI_HP3_AWREADY; output S_AXI_HP3_BVALID; output S_AXI_HP3_RLAST; output S_AXI_HP3_RVALID; output S_AXI_HP3_WREADY; output [1:0] S_AXI_HP3_BRESP; output [1:0] S_AXI_HP3_RRESP; output [5:0] S_AXI_HP3_BID; output [5:0] S_AXI_HP3_RID; output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA; output [7:0] S_AXI_HP3_RCOUNT; output [7:0] S_AXI_HP3_WCOUNT; output [2:0] S_AXI_HP3_RACOUNT; output [5:0] S_AXI_HP3_WACOUNT; input S_AXI_HP3_ACLK; input S_AXI_HP3_ARVALID; input S_AXI_HP3_AWVALID; input S_AXI_HP3_BREADY; input S_AXI_HP3_RDISSUECAP1_EN; input S_AXI_HP3_RREADY; input S_AXI_HP3_WLAST; input S_AXI_HP3_WRISSUECAP1_EN; input S_AXI_HP3_WVALID; input [1:0] S_AXI_HP3_ARBURST; input [1:0] S_AXI_HP3_ARLOCK; input [2:0] S_AXI_HP3_ARSIZE; input [1:0] S_AXI_HP3_AWBURST; input [1:0] S_AXI_HP3_AWLOCK; input [2:0] S_AXI_HP3_AWSIZE; input [2:0] S_AXI_HP3_ARPROT; input [2:0] S_AXI_HP3_AWPROT; input [31:0] S_AXI_HP3_ARADDR; input [31:0] S_AXI_HP3_AWADDR; input [3:0] S_AXI_HP3_ARCACHE; input [3:0] S_AXI_HP3_ARLEN; input [3:0] S_AXI_HP3_ARQOS; input [3:0] S_AXI_HP3_AWCACHE; input [3:0] S_AXI_HP3_AWLEN; input [3:0] S_AXI_HP3_AWQOS; input [5:0] S_AXI_HP3_ARID; input [5:0] S_AXI_HP3_AWID; input [5:0] S_AXI_HP3_WID; input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA; input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB; output [1:0] DMA0_DATYPE; output DMA0_DAVALID; output DMA0_DRREADY; input DMA0_ACLK; input DMA0_DAREADY; input DMA0_DRLAST; input DMA0_DRVALID; input [1:0] DMA0_DRTYPE; output [1:0] DMA1_DATYPE; output DMA1_DAVALID; output DMA1_DRREADY; input DMA1_ACLK; input DMA1_DAREADY; input DMA1_DRLAST; input DMA1_DRVALID; input [1:0] DMA1_DRTYPE; output [1:0] DMA2_DATYPE; output DMA2_DAVALID; output DMA2_DRREADY; input DMA2_ACLK; input DMA2_DAREADY; input DMA2_DRLAST; input DMA2_DRVALID; input DMA3_DRVALID; output [1:0] DMA3_DATYPE; output DMA3_DAVALID; output DMA3_DRREADY; input DMA3_ACLK; input DMA3_DAREADY; input DMA3_DRLAST; input [1:0] DMA2_DRTYPE; input [1:0] DMA3_DRTYPE; input [31:0] FTMD_TRACEIN_DATA; input FTMD_TRACEIN_VALID; input FTMD_TRACEIN_CLK; input [3:0] FTMD_TRACEIN_ATID; input [3:0] FTMT_F2P_TRIG; output [3:0] FTMT_F2P_TRIGACK; input [31:0] FTMT_F2P_DEBUG; input [3:0] FTMT_P2F_TRIGACK; output [3:0] FTMT_P2F_TRIG; output [31:0] FTMT_P2F_DEBUG; output FCLK_CLK3; output FCLK_CLK2; output FCLK_CLK1; output FCLK_CLK0; input FCLK_CLKTRIG3_N; input FCLK_CLKTRIG2_N; input FCLK_CLKTRIG1_N; input FCLK_CLKTRIG0_N; output FCLK_RESET3_N; output FCLK_RESET2_N; output FCLK_RESET1_N; output FCLK_RESET0_N; input FPGA_IDLE_N; input [3:0] DDR_ARB; input [irq_width-1:0] IRQ_F2P; input Core0_nFIQ; input Core0_nIRQ; input Core1_nFIQ; input Core1_nIRQ; output EVENT_EVENTO; output [1:0] EVENT_STANDBYWFE; output [1:0] EVENT_STANDBYWFI; input EVENT_EVENTI; inout [53:0] MIO; inout DDR_Clk; inout DDR_Clk_n; inout DDR_CKE; inout DDR_CS_n; inout DDR_RAS_n; inout DDR_CAS_n; output DDR_WEB; inout [2:0] DDR_BankAddr; inout [14:0] DDR_Addr; inout DDR_ODT; inout DDR_DRSTB; inout [31:0] DDR_DQ; inout [3:0] DDR_DM; inout [3:0] DDR_DQS; inout [3:0] DDR_DQS_n; inout DDR_VRN; inout DDR_VRP; /* Reset Input & Clock Input */ input PS_SRSTB; input PS_CLK; input PS_PORB; output IRQ_P2F_DMAC_ABORT; output IRQ_P2F_DMAC0; output IRQ_P2F_DMAC1; output IRQ_P2F_DMAC2; output IRQ_P2F_DMAC3; output IRQ_P2F_DMAC4; output IRQ_P2F_DMAC5; output IRQ_P2F_DMAC6; output IRQ_P2F_DMAC7; output IRQ_P2F_SMC; output IRQ_P2F_QSPI; output IRQ_P2F_CTI; output IRQ_P2F_GPIO; output IRQ_P2F_USB0; output IRQ_P2F_ENET0; output IRQ_P2F_ENET_WAKE0; output IRQ_P2F_SDIO0; output IRQ_P2F_I2C0; output IRQ_P2F_SPI0; output IRQ_P2F_UART0; output IRQ_P2F_CAN0; output IRQ_P2F_USB1; output IRQ_P2F_ENET1; output IRQ_P2F_ENET_WAKE1; output IRQ_P2F_SDIO1; output IRQ_P2F_I2C1; output IRQ_P2F_SPI1; output IRQ_P2F_UART1; output IRQ_P2F_CAN1; /* Internal wires/nets used for connectivity */ wire net_rstn; wire net_sw_clk; wire net_ocm_clk; wire net_arbiter_clk; wire net_axi_mgp0_rstn; wire net_axi_mgp1_rstn; wire net_axi_gp0_rstn; wire net_axi_gp1_rstn; wire net_axi_hp0_rstn; wire net_axi_hp1_rstn; wire net_axi_hp2_rstn; wire net_axi_hp3_rstn; wire net_axi_acp_rstn; wire [4:0] net_axi_acp_awuser; wire [4:0] net_axi_acp_aruser; /* Dummy */ assign net_axi_acp_awuser = S_AXI_ACP_AWUSER; assign net_axi_acp_aruser = S_AXI_ACP_ARUSER; /* Global variables */ reg DEBUG_INFO = 1; reg STOP_ON_ERROR = 1; /* local variable acting as semaphore for wait_mem_update and wait_reg_update task */ reg mem_update_key = 1; reg reg_update_key_0 = 1; reg reg_update_key_1 = 1; /* assignments and semantic checks for unused ports */ `include "processing_system7_bfm_v2_0_5_unused_ports.v" /* include api definition */ `include "processing_system7_bfm_v2_0_5_apis.v" /* Reset Generator */ processing_system7_bfm_v2_0_5_gen_reset gen_rst(.por_rst_n(PS_PORB), .sys_rst_n(PS_SRSTB), .rst_out_n(net_rstn), .m_axi_gp0_clk(M_AXI_GP0_ACLK), .m_axi_gp1_clk(M_AXI_GP1_ACLK), .s_axi_gp0_clk(S_AXI_GP0_ACLK), .s_axi_gp1_clk(S_AXI_GP1_ACLK), .s_axi_hp0_clk(S_AXI_HP0_ACLK), .s_axi_hp1_clk(S_AXI_HP1_ACLK), .s_axi_hp2_clk(S_AXI_HP2_ACLK), .s_axi_hp3_clk(S_AXI_HP3_ACLK), .s_axi_acp_clk(S_AXI_ACP_ACLK), .m_axi_gp0_rstn(net_axi_mgp0_rstn), .m_axi_gp1_rstn(net_axi_mgp1_rstn), .s_axi_gp0_rstn(net_axi_gp0_rstn), .s_axi_gp1_rstn(net_axi_gp1_rstn), .s_axi_hp0_rstn(net_axi_hp0_rstn), .s_axi_hp1_rstn(net_axi_hp1_rstn), .s_axi_hp2_rstn(net_axi_hp2_rstn), .s_axi_hp3_rstn(net_axi_hp3_rstn), .s_axi_acp_rstn(net_axi_acp_rstn), .fclk_reset3_n(FCLK_RESET3_N), .fclk_reset2_n(FCLK_RESET2_N), .fclk_reset1_n(FCLK_RESET1_N), .fclk_reset0_n(FCLK_RESET0_N), .fpga_acp_reset_n(), ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP) .fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN), .fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN), .fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN), .fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN), .fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN), .fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN), .fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN), .fpga_hp_s3_reset_n() ////S_AXI_HP3_ARESETN) ); /* Clock Generator */ processing_system7_bfm_v2_0_5_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ) gen_clk(.ps_clk(PS_CLK), .sw_clk(net_sw_clk), .fclk_clk3(FCLK_CLK3), .fclk_clk2(FCLK_CLK2), .fclk_clk1(FCLK_CLK1), .fclk_clk0(FCLK_CLK0) ); wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1; wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1; wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1; wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1; wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1; wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1; wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1; wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1; wire net_rd_req_reg_gp0, net_rd_req_reg_gp1; wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1; wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1; wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1; wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1; wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1; wire net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1; wire net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1; wire net_rd_dv_reg_gp0, net_rd_dv_reg_gp1; wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1; wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3; wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3; wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3; wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3; wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3; wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3; wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3; wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3; wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3; wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3; wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3; wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3; wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3; wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3; wire net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3; wire net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3; wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3; wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp; wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp; wire [max_burst_bits-1:0] net_wr_data_acp; wire [addr_width-1:0] net_wr_addr_acp; wire [max_burst_bytes_width:0] net_wr_bytes_acp; wire [axi_qos_width-1:0] net_wr_qos_acp; wire net_rd_req_ddr_acp, net_rd_req_ocm_acp; wire [addr_width-1:0] net_rd_addr_acp; wire [max_burst_bytes_width:0] net_rd_bytes_acp; wire [max_burst_bits-1:0] net_rd_data_ddr_acp; wire [max_burst_bits-1:0] net_rd_data_ocm_acp; wire net_rd_dv_ddr_acp,net_rd_dv_ocm_acp; wire [axi_qos_width-1:0] net_rd_qos_acp; wire ocm_wr_ack_port0; wire ocm_wr_dv_port0; wire ocm_rd_req_port0; wire ocm_rd_dv_port0; wire [addr_width-1:0] ocm_wr_addr_port0; wire [max_burst_bits-1:0] ocm_wr_data_port0; wire [max_burst_bytes_width:0] ocm_wr_bytes_port0; wire [addr_width-1:0] ocm_rd_addr_port0; wire [max_burst_bits-1:0] ocm_rd_data_port0; wire [max_burst_bytes_width:0] ocm_rd_bytes_port0; wire [axi_qos_width-1:0] ocm_wr_qos_port0; wire [axi_qos_width-1:0] ocm_rd_qos_port0; wire ocm_wr_ack_port1; wire ocm_wr_dv_port1; wire ocm_rd_req_port1; wire ocm_rd_dv_port1; wire [addr_width-1:0] ocm_wr_addr_port1; wire [max_burst_bits-1:0] ocm_wr_data_port1; wire [max_burst_bytes_width:0] ocm_wr_bytes_port1; wire [addr_width-1:0] ocm_rd_addr_port1; wire [max_burst_bits-1:0] ocm_rd_data_port1; wire [max_burst_bytes_width:0] ocm_rd_bytes_port1; wire [axi_qos_width-1:0] ocm_wr_qos_port1; wire [axi_qos_width-1:0] ocm_rd_qos_port1; wire ddr_wr_ack_port0; wire ddr_wr_dv_port0; wire ddr_rd_req_port0; wire ddr_rd_dv_port0; wire[addr_width-1:0] ddr_wr_addr_port0; wire[max_burst_bits-1:0] ddr_wr_data_port0; wire[max_burst_bytes_width:0] ddr_wr_bytes_port0; wire[addr_width-1:0] ddr_rd_addr_port0; wire[max_burst_bits-1:0] ddr_rd_data_port0; wire[max_burst_bytes_width:0] ddr_rd_bytes_port0; wire [axi_qos_width-1:0] ddr_wr_qos_port0; wire [axi_qos_width-1:0] ddr_rd_qos_port0; wire ddr_wr_ack_port1; wire ddr_wr_dv_port1; wire ddr_rd_req_port1; wire ddr_rd_dv_port1; wire[addr_width-1:0] ddr_wr_addr_port1; wire[max_burst_bits-1:0] ddr_wr_data_port1; wire[max_burst_bytes_width:0] ddr_wr_bytes_port1; wire[addr_width-1:0] ddr_rd_addr_port1; wire[max_burst_bits-1:0] ddr_rd_data_port1; wire[max_burst_bytes_width:0] ddr_rd_bytes_port1; wire[axi_qos_width-1:0] ddr_wr_qos_port1; wire[axi_qos_width-1:0] ddr_rd_qos_port1; wire ddr_wr_ack_port2; wire ddr_wr_dv_port2; wire ddr_rd_req_port2; wire ddr_rd_dv_port2; wire[addr_width-1:0] ddr_wr_addr_port2; wire[max_burst_bits-1:0] ddr_wr_data_port2; wire[max_burst_bytes_width:0] ddr_wr_bytes_port2; wire[addr_width-1:0] ddr_rd_addr_port2; wire[max_burst_bits-1:0] ddr_rd_data_port2; wire[max_burst_bytes_width:0] ddr_rd_bytes_port2; wire[axi_qos_width-1:0] ddr_wr_qos_port2; wire[axi_qos_width-1:0] ddr_rd_qos_port2; wire ddr_wr_ack_port3; wire ddr_wr_dv_port3; wire ddr_rd_req_port3; wire ddr_rd_dv_port3; wire[addr_width-1:0] ddr_wr_addr_port3; wire[max_burst_bits-1:0] ddr_wr_data_port3; wire[max_burst_bytes_width:0] ddr_wr_bytes_port3; wire[addr_width-1:0] ddr_rd_addr_port3; wire[max_burst_bits-1:0] ddr_rd_data_port3; wire[max_burst_bytes_width:0] ddr_rd_bytes_port3; wire[axi_qos_width-1:0] ddr_wr_qos_port3; wire[axi_qos_width-1:0] ddr_rd_qos_port3; wire reg_rd_req_port0; wire reg_rd_dv_port0; wire[addr_width-1:0] reg_rd_addr_port0; wire[max_burst_bits-1:0] reg_rd_data_port0; wire[max_burst_bytes_width:0] reg_rd_bytes_port0; wire [axi_qos_width-1:0] reg_rd_qos_port0; wire reg_rd_req_port1; wire reg_rd_dv_port1; wire[addr_width-1:0] reg_rd_addr_port1; wire[max_burst_bits-1:0] reg_rd_data_port1; wire[max_burst_bytes_width:0] reg_rd_bytes_port1; wire [axi_qos_width-1:0] reg_rd_qos_port1; wire [11:0] M_AXI_GP0_AWID_FULL; wire [11:0] M_AXI_GP0_WID_FULL; wire [11:0] M_AXI_GP0_ARID_FULL; wire [11:0] M_AXI_GP0_BID_FULL; wire [11:0] M_AXI_GP0_RID_FULL; wire [11:0] M_AXI_GP1_AWID_FULL; wire [11:0] M_AXI_GP1_WID_FULL; wire [11:0] M_AXI_GP1_ARID_FULL; wire [11:0] M_AXI_GP1_BID_FULL; wire [11:0] M_AXI_GP1_RID_FULL; function [5:0] compress_id; input [11:0] id; begin compress_id = id[5:0]; end endfunction function [11:0] uncompress_id; input [5:0] id; begin uncompress_id = {6'b110000, id[5:0]}; end endfunction assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL; assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL; assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL; assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID; assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID; assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL; assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL; assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL; assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID; assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID; processing_system7_bfm_v2_0_5_interconnect_model icm ( .rstn(net_rstn), .sw_clk(net_sw_clk), .w_qos_gp0(net_wr_qos_gp0), .w_qos_gp1(net_wr_qos_gp1), .w_qos_hp0(net_wr_qos_hp0), .w_qos_hp1(net_wr_qos_hp1), .w_qos_hp2(net_wr_qos_hp2), .w_qos_hp3(net_wr_qos_hp3), .r_qos_gp0(net_rd_qos_gp0), .r_qos_gp1(net_rd_qos_gp1), .r_qos_hp0(net_rd_qos_hp0), .r_qos_hp1(net_rd_qos_hp1), .r_qos_hp2(net_rd_qos_hp2), .r_qos_hp3(net_rd_qos_hp3), /* GP Slave ports access */ .wr_ack_ddr_gp0(net_wr_ack_ddr_gp0), .wr_ack_ocm_gp0(net_wr_ack_ocm_gp0), .wr_data_gp0(net_wr_data_gp0), .wr_addr_gp0(net_wr_addr_gp0), .wr_bytes_gp0(net_wr_bytes_gp0), .wr_dv_ddr_gp0(net_wr_dv_ddr_gp0), .wr_dv_ocm_gp0(net_wr_dv_ocm_gp0), .rd_req_ddr_gp0(net_rd_req_ddr_gp0), .rd_req_ocm_gp0(net_rd_req_ocm_gp0), .rd_req_reg_gp0(net_rd_req_reg_gp0), .rd_addr_gp0(net_rd_addr_gp0), .rd_bytes_gp0(net_rd_bytes_gp0), .rd_data_ddr_gp0(net_rd_data_ddr_gp0), .rd_data_ocm_gp0(net_rd_data_ocm_gp0), .rd_data_reg_gp0(net_rd_data_reg_gp0), .rd_dv_ddr_gp0(net_rd_dv_ddr_gp0), .rd_dv_ocm_gp0(net_rd_dv_ocm_gp0), .rd_dv_reg_gp0(net_rd_dv_reg_gp0), .wr_ack_ddr_gp1(net_wr_ack_ddr_gp1), .wr_ack_ocm_gp1(net_wr_ack_ocm_gp1), .wr_data_gp1(net_wr_data_gp1), .wr_addr_gp1(net_wr_addr_gp1), .wr_bytes_gp1(net_wr_bytes_gp1), .wr_dv_ddr_gp1(net_wr_dv_ddr_gp1), .wr_dv_ocm_gp1(net_wr_dv_ocm_gp1), .rd_req_ddr_gp1(net_rd_req_ddr_gp1), .rd_req_ocm_gp1(net_rd_req_ocm_gp1), .rd_req_reg_gp1(net_rd_req_reg_gp1), .rd_addr_gp1(net_rd_addr_gp1), .rd_bytes_gp1(net_rd_bytes_gp1), .rd_data_ddr_gp1(net_rd_data_ddr_gp1), .rd_data_ocm_gp1(net_rd_data_ocm_gp1), .rd_data_reg_gp1(net_rd_data_reg_gp1), .rd_dv_ddr_gp1(net_rd_dv_ddr_gp1), .rd_dv_ocm_gp1(net_rd_dv_ocm_gp1), .rd_dv_reg_gp1(net_rd_dv_reg_gp1), /* HP Slave ports access */ .wr_ack_ddr_hp0(net_wr_ack_ddr_hp0), .wr_ack_ocm_hp0(net_wr_ack_ocm_hp0), .wr_data_hp0(net_wr_data_hp0), .wr_addr_hp0(net_wr_addr_hp0), .wr_bytes_hp0(net_wr_bytes_hp0), .wr_dv_ddr_hp0(net_wr_dv_ddr_hp0), .wr_dv_ocm_hp0(net_wr_dv_ocm_hp0), .rd_req_ddr_hp0(net_rd_req_ddr_hp0), .rd_req_ocm_hp0(net_rd_req_ocm_hp0), .rd_addr_hp0(net_rd_addr_hp0), .rd_bytes_hp0(net_rd_bytes_hp0), .rd_data_ddr_hp0(net_rd_data_ddr_hp0), .rd_data_ocm_hp0(net_rd_data_ocm_hp0), .rd_dv_ddr_hp0(net_rd_dv_ddr_hp0), .rd_dv_ocm_hp0(net_rd_dv_ocm_hp0), .wr_ack_ddr_hp1(net_wr_ack_ddr_hp1), .wr_ack_ocm_hp1(net_wr_ack_ocm_hp1), .wr_data_hp1(net_wr_data_hp1), .wr_addr_hp1(net_wr_addr_hp1), .wr_bytes_hp1(net_wr_bytes_hp1), .wr_dv_ddr_hp1(net_wr_dv_ddr_hp1), .wr_dv_ocm_hp1(net_wr_dv_ocm_hp1), .rd_req_ddr_hp1(net_rd_req_ddr_hp1), .rd_req_ocm_hp1(net_rd_req_ocm_hp1), .rd_addr_hp1(net_rd_addr_hp1), .rd_bytes_hp1(net_rd_bytes_hp1), .rd_data_ddr_hp1(net_rd_data_ddr_hp1), .rd_data_ocm_hp1(net_rd_data_ocm_hp1), .rd_dv_ocm_hp1(net_rd_dv_ocm_hp1), .rd_dv_ddr_hp1(net_rd_dv_ddr_hp1), .wr_ack_ddr_hp2(net_wr_ack_ddr_hp2), .wr_ack_ocm_hp2(net_wr_ack_ocm_hp2), .wr_data_hp2(net_wr_data_hp2), .wr_addr_hp2(net_wr_addr_hp2), .wr_bytes_hp2(net_wr_bytes_hp2), .wr_dv_ocm_hp2(net_wr_dv_ocm_hp2), .wr_dv_ddr_hp2(net_wr_dv_ddr_hp2), .rd_req_ddr_hp2(net_rd_req_ddr_hp2), .rd_req_ocm_hp2(net_rd_req_ocm_hp2), .rd_addr_hp2(net_rd_addr_hp2), .rd_bytes_hp2(net_rd_bytes_hp2), .rd_data_ddr_hp2(net_rd_data_ddr_hp2), .rd_data_ocm_hp2(net_rd_data_ocm_hp2), .rd_dv_ddr_hp2(net_rd_dv_ddr_hp2), .rd_dv_ocm_hp2(net_rd_dv_ocm_hp2), .wr_ack_ocm_hp3(net_wr_ack_ocm_hp3), .wr_ack_ddr_hp3(net_wr_ack_ddr_hp3), .wr_data_hp3(net_wr_data_hp3), .wr_addr_hp3(net_wr_addr_hp3), .wr_bytes_hp3(net_wr_bytes_hp3), .wr_dv_ddr_hp3(net_wr_dv_ddr_hp3), .wr_dv_ocm_hp3(net_wr_dv_ocm_hp3), .rd_req_ddr_hp3(net_rd_req_ddr_hp3), .rd_req_ocm_hp3(net_rd_req_ocm_hp3), .rd_addr_hp3(net_rd_addr_hp3), .rd_bytes_hp3(net_rd_bytes_hp3), .rd_data_ddr_hp3(net_rd_data_ddr_hp3), .rd_data_ocm_hp3(net_rd_data_ocm_hp3), .rd_dv_ddr_hp3(net_rd_dv_ddr_hp3), .rd_dv_ocm_hp3(net_rd_dv_ocm_hp3), /* Goes to port 1 of DDR */ .ddr_wr_ack_port1(ddr_wr_ack_port1), .ddr_wr_dv_port1(ddr_wr_dv_port1), .ddr_rd_req_port1(ddr_rd_req_port1), .ddr_rd_dv_port1 (ddr_rd_dv_port1), .ddr_wr_addr_port1(ddr_wr_addr_port1), .ddr_wr_data_port1(ddr_wr_data_port1), .ddr_wr_bytes_port1(ddr_wr_bytes_port1), .ddr_rd_addr_port1(ddr_rd_addr_port1), .ddr_rd_data_port1(ddr_rd_data_port1), .ddr_rd_bytes_port1(ddr_rd_bytes_port1), .ddr_wr_qos_port1(ddr_wr_qos_port1), .ddr_rd_qos_port1(ddr_rd_qos_port1), /* Goes to port2 of DDR */ .ddr_wr_ack_port2 (ddr_wr_ack_port2), .ddr_wr_dv_port2 (ddr_wr_dv_port2), .ddr_rd_req_port2 (ddr_rd_req_port2), .ddr_rd_dv_port2 (ddr_rd_dv_port2), .ddr_wr_addr_port2(ddr_wr_addr_port2), .ddr_wr_data_port2(ddr_wr_data_port2), .ddr_wr_bytes_port2(ddr_wr_bytes_port2), .ddr_rd_addr_port2(ddr_rd_addr_port2), .ddr_rd_data_port2(ddr_rd_data_port2), .ddr_rd_bytes_port2(ddr_rd_bytes_port2), .ddr_wr_qos_port2 (ddr_wr_qos_port2), .ddr_rd_qos_port2 (ddr_rd_qos_port2), /* Goes to port3 of DDR */ .ddr_wr_ack_port3 (ddr_wr_ack_port3), .ddr_wr_dv_port3 (ddr_wr_dv_port3), .ddr_rd_req_port3 (ddr_rd_req_port3), .ddr_rd_dv_port3 (ddr_rd_dv_port3), .ddr_wr_addr_port3(ddr_wr_addr_port3), .ddr_wr_data_port3(ddr_wr_data_port3), .ddr_wr_bytes_port3(ddr_wr_bytes_port3), .ddr_rd_addr_port3(ddr_rd_addr_port3), .ddr_rd_data_port3(ddr_rd_data_port3), .ddr_rd_bytes_port3(ddr_rd_bytes_port3), .ddr_wr_qos_port3 (ddr_wr_qos_port3), .ddr_rd_qos_port3 (ddr_rd_qos_port3), /* Goes to port 0 of OCM */ .ocm_wr_ack_port1 (ocm_wr_ack_port1), .ocm_wr_dv_port1 (ocm_wr_dv_port1), .ocm_rd_req_port1 (ocm_rd_req_port1), .ocm_rd_dv_port1 (ocm_rd_dv_port1), .ocm_wr_addr_port1(ocm_wr_addr_port1), .ocm_wr_data_port1(ocm_wr_data_port1), .ocm_wr_bytes_port1(ocm_wr_bytes_port1), .ocm_rd_addr_port1(ocm_rd_addr_port1), .ocm_rd_data_port1(ocm_rd_data_port1), .ocm_rd_bytes_port1(ocm_rd_bytes_port1), .ocm_wr_qos_port1(ocm_wr_qos_port1), .ocm_rd_qos_port1(ocm_rd_qos_port1), /* Goes to port 0 of REG */ .reg_rd_qos_port1 (reg_rd_qos_port1) , .reg_rd_req_port1 (reg_rd_req_port1), .reg_rd_dv_port1 (reg_rd_dv_port1), .reg_rd_addr_port1(reg_rd_addr_port1), .reg_rd_data_port1(reg_rd_data_port1), .reg_rd_bytes_port1(reg_rd_bytes_port1) ); processing_system7_bfm_v2_0_5_ddrc ddrc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of DDR */ .ddr_wr_ack_port0 (ddr_wr_ack_port0), .ddr_wr_dv_port0 (ddr_wr_dv_port0), .ddr_rd_req_port0 (ddr_rd_req_port0), .ddr_rd_dv_port0 (ddr_rd_dv_port0), .ddr_wr_addr_port0(net_wr_addr_acp), .ddr_wr_data_port0(net_wr_data_acp), .ddr_wr_bytes_port0(net_wr_bytes_acp), .ddr_rd_addr_port0(net_rd_addr_acp), .ddr_rd_bytes_port0(net_rd_bytes_acp), .ddr_rd_data_port0(ddr_rd_data_port0), .ddr_wr_qos_port0 (net_wr_qos_acp), .ddr_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of DDR */ .ddr_wr_ack_port1 (ddr_wr_ack_port1), .ddr_wr_dv_port1 (ddr_wr_dv_port1), .ddr_rd_req_port1 (ddr_rd_req_port1), .ddr_rd_dv_port1 (ddr_rd_dv_port1), .ddr_wr_addr_port1(ddr_wr_addr_port1), .ddr_wr_data_port1(ddr_wr_data_port1), .ddr_wr_bytes_port1(ddr_wr_bytes_port1), .ddr_rd_addr_port1(ddr_rd_addr_port1), .ddr_rd_data_port1(ddr_rd_data_port1), .ddr_rd_bytes_port1(ddr_rd_bytes_port1), .ddr_wr_qos_port1 (ddr_wr_qos_port1), .ddr_rd_qos_port1 (ddr_rd_qos_port1), /* Goes to port2 of DDR */ .ddr_wr_ack_port2 (ddr_wr_ack_port2), .ddr_wr_dv_port2 (ddr_wr_dv_port2), .ddr_rd_req_port2 (ddr_rd_req_port2), .ddr_rd_dv_port2 (ddr_rd_dv_port2), .ddr_wr_addr_port2(ddr_wr_addr_port2), .ddr_wr_data_port2(ddr_wr_data_port2), .ddr_wr_bytes_port2(ddr_wr_bytes_port2), .ddr_rd_addr_port2(ddr_rd_addr_port2), .ddr_rd_data_port2(ddr_rd_data_port2), .ddr_rd_bytes_port2(ddr_rd_bytes_port2), .ddr_wr_qos_port2 (ddr_wr_qos_port2), .ddr_rd_qos_port2 (ddr_rd_qos_port2), /* Goes to port3 of DDR */ .ddr_wr_ack_port3 (ddr_wr_ack_port3), .ddr_wr_dv_port3 (ddr_wr_dv_port3), .ddr_rd_req_port3 (ddr_rd_req_port3), .ddr_rd_dv_port3 (ddr_rd_dv_port3), .ddr_wr_addr_port3(ddr_wr_addr_port3), .ddr_wr_data_port3(ddr_wr_data_port3), .ddr_wr_bytes_port3(ddr_wr_bytes_port3), .ddr_rd_addr_port3(ddr_rd_addr_port3), .ddr_rd_data_port3(ddr_rd_data_port3), .ddr_rd_bytes_port3(ddr_rd_bytes_port3), .ddr_wr_qos_port3 (ddr_wr_qos_port3), .ddr_rd_qos_port3 (ddr_rd_qos_port3) ); processing_system7_bfm_v2_0_5_ocmc ocmc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of OCM */ .ocm_wr_ack_port0 (ocm_wr_ack_port0), .ocm_wr_dv_port0 (ocm_wr_dv_port0), .ocm_rd_req_port0 (ocm_rd_req_port0), .ocm_rd_dv_port0 (ocm_rd_dv_port0), .ocm_wr_addr_port0(net_wr_addr_acp), .ocm_wr_data_port0(net_wr_data_acp), .ocm_wr_bytes_port0(net_wr_bytes_acp), .ocm_rd_addr_port0(net_rd_addr_acp), .ocm_rd_bytes_port0(net_rd_bytes_acp), .ocm_rd_data_port0(ocm_rd_data_port0), .ocm_wr_qos_port0 (net_wr_qos_acp), .ocm_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of OCM */ .ocm_wr_ack_port1 (ocm_wr_ack_port1), .ocm_wr_dv_port1 (ocm_wr_dv_port1), .ocm_rd_req_port1 (ocm_rd_req_port1), .ocm_rd_dv_port1 (ocm_rd_dv_port1), .ocm_wr_addr_port1(ocm_wr_addr_port1), .ocm_wr_data_port1(ocm_wr_data_port1), .ocm_wr_bytes_port1(ocm_wr_bytes_port1), .ocm_rd_addr_port1(ocm_rd_addr_port1), .ocm_rd_data_port1(ocm_rd_data_port1), .ocm_rd_bytes_port1(ocm_rd_bytes_port1), .ocm_wr_qos_port1(ocm_wr_qos_port1), .ocm_rd_qos_port1(ocm_rd_qos_port1) ); processing_system7_bfm_v2_0_5_regc regc ( .rstn(net_rstn), .sw_clk(net_sw_clk), /* Goes to port 0 of REG */ .reg_rd_req_port0 (reg_rd_req_port0), .reg_rd_dv_port0 (reg_rd_dv_port0), .reg_rd_addr_port0(net_rd_addr_acp), .reg_rd_bytes_port0(net_rd_bytes_acp), .reg_rd_data_port0(reg_rd_data_port0), .reg_rd_qos_port0 (net_rd_qos_acp), /* Goes to port 1 of REG */ .reg_rd_req_port1 (reg_rd_req_port1), .reg_rd_dv_port1 (reg_rd_dv_port1), .reg_rd_addr_port1(reg_rd_addr_port1), .reg_rd_data_port1(reg_rd_data_port1), .reg_rd_bytes_port1(reg_rd_bytes_port1), .reg_rd_qos_port1(reg_rd_qos_port1) ); /* include axi_gp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_gp.v" /* include axi_hp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_hp.v" /* include axi_acp port instantiations */ `include "processing_system7_bfm_v2_0_5_axi_acp.v" endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_ddrc.v * * Date : 2012-11 * * Description : Module that acts as controller for sparse memory (DDR). * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_ddrc( rstn, sw_clk, /* Goes to port 0 of DDR */ ddr_wr_ack_port0, ddr_wr_dv_port0, ddr_rd_req_port0, ddr_rd_dv_port0, ddr_wr_addr_port0, ddr_wr_data_port0, ddr_wr_bytes_port0, ddr_rd_addr_port0, ddr_rd_data_port0, ddr_rd_bytes_port0, ddr_wr_qos_port0, ddr_rd_qos_port0, /* Goes to port 1 of DDR */ ddr_wr_ack_port1, ddr_wr_dv_port1, ddr_rd_req_port1, ddr_rd_dv_port1, ddr_wr_addr_port1, ddr_wr_data_port1, ddr_wr_bytes_port1, ddr_rd_addr_port1, ddr_rd_data_port1, ddr_rd_bytes_port1, ddr_wr_qos_port1, ddr_rd_qos_port1, /* Goes to port2 of DDR */ ddr_wr_ack_port2, ddr_wr_dv_port2, ddr_rd_req_port2, ddr_rd_dv_port2, ddr_wr_addr_port2, ddr_wr_data_port2, ddr_wr_bytes_port2, ddr_rd_addr_port2, ddr_rd_data_port2, ddr_rd_bytes_port2, ddr_wr_qos_port2, ddr_rd_qos_port2, /* Goes to port3 of DDR */ ddr_wr_ack_port3, ddr_wr_dv_port3, ddr_rd_req_port3, ddr_rd_dv_port3, ddr_wr_addr_port3, ddr_wr_data_port3, ddr_wr_bytes_port3, ddr_rd_addr_port3, ddr_rd_data_port3, ddr_rd_bytes_port3, ddr_wr_qos_port3, ddr_rd_qos_port3 ); `include "processing_system7_bfm_v2_0_5_local_params.v" input rstn; input sw_clk; output ddr_wr_ack_port0; input ddr_wr_dv_port0; input ddr_rd_req_port0; output ddr_rd_dv_port0; input[addr_width-1:0] ddr_wr_addr_port0; input[max_burst_bits-1:0] ddr_wr_data_port0; input[max_burst_bytes_width:0] ddr_wr_bytes_port0; input[addr_width-1:0] ddr_rd_addr_port0; output[max_burst_bits-1:0] ddr_rd_data_port0; input[max_burst_bytes_width:0] ddr_rd_bytes_port0; input [axi_qos_width-1:0] ddr_wr_qos_port0; input [axi_qos_width-1:0] ddr_rd_qos_port0; output ddr_wr_ack_port1; input ddr_wr_dv_port1; input ddr_rd_req_port1; output ddr_rd_dv_port1; input[addr_width-1:0] ddr_wr_addr_port1; input[max_burst_bits-1:0] ddr_wr_data_port1; input[max_burst_bytes_width:0] ddr_wr_bytes_port1; input[addr_width-1:0] ddr_rd_addr_port1; output[max_burst_bits-1:0] ddr_rd_data_port1; input[max_burst_bytes_width:0] ddr_rd_bytes_port1; input[axi_qos_width-1:0] ddr_wr_qos_port1; input[axi_qos_width-1:0] ddr_rd_qos_port1; output ddr_wr_ack_port2; input ddr_wr_dv_port2; input ddr_rd_req_port2; output ddr_rd_dv_port2; input[addr_width-1:0] ddr_wr_addr_port2; input[max_burst_bits-1:0] ddr_wr_data_port2; input[max_burst_bytes_width:0] ddr_wr_bytes_port2; input[addr_width-1:0] ddr_rd_addr_port2; output[max_burst_bits-1:0] ddr_rd_data_port2; input[max_burst_bytes_width:0] ddr_rd_bytes_port2; input[axi_qos_width-1:0] ddr_wr_qos_port2; input[axi_qos_width-1:0] ddr_rd_qos_port2; output ddr_wr_ack_port3; input ddr_wr_dv_port3; input ddr_rd_req_port3; output ddr_rd_dv_port3; input[addr_width-1:0] ddr_wr_addr_port3; input[max_burst_bits-1:0] ddr_wr_data_port3; input[max_burst_bytes_width:0] ddr_wr_bytes_port3; input[addr_width-1:0] ddr_rd_addr_port3; output[max_burst_bits-1:0] ddr_rd_data_port3; input[max_burst_bytes_width:0] ddr_rd_bytes_port3; input[axi_qos_width-1:0] ddr_wr_qos_port3; input[axi_qos_width-1:0] ddr_rd_qos_port3; wire [axi_qos_width-1:0] wr_qos; wire wr_req; wire [max_burst_bits-1:0] wr_data; wire [addr_width-1:0] wr_addr; wire [max_burst_bytes_width:0] wr_bytes; reg wr_ack; wire [axi_qos_width-1:0] rd_qos; reg [max_burst_bits-1:0] rd_data; wire [addr_width-1:0] rd_addr; wire [max_burst_bytes_width:0] rd_bytes; reg rd_dv; wire rd_req; processing_system7_bfm_v2_0_5_arb_wr_4 ddr_write_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(ddr_wr_qos_port0), .qos2(ddr_wr_qos_port1), .qos3(ddr_wr_qos_port2), .qos4(ddr_wr_qos_port3), .prt_dv1(ddr_wr_dv_port0), .prt_dv2(ddr_wr_dv_port1), .prt_dv3(ddr_wr_dv_port2), .prt_dv4(ddr_wr_dv_port3), .prt_data1(ddr_wr_data_port0), .prt_data2(ddr_wr_data_port1), .prt_data3(ddr_wr_data_port2), .prt_data4(ddr_wr_data_port3), .prt_addr1(ddr_wr_addr_port0), .prt_addr2(ddr_wr_addr_port1), .prt_addr3(ddr_wr_addr_port2), .prt_addr4(ddr_wr_addr_port3), .prt_bytes1(ddr_wr_bytes_port0), .prt_bytes2(ddr_wr_bytes_port1), .prt_bytes3(ddr_wr_bytes_port2), .prt_bytes4(ddr_wr_bytes_port3), .prt_ack1(ddr_wr_ack_port0), .prt_ack2(ddr_wr_ack_port1), .prt_ack3(ddr_wr_ack_port2), .prt_ack4(ddr_wr_ack_port3), .prt_qos(wr_qos), .prt_req(wr_req), .prt_data(wr_data), .prt_addr(wr_addr), .prt_bytes(wr_bytes), .prt_ack(wr_ack) ); processing_system7_bfm_v2_0_5_arb_rd_4 ddr_read_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(ddr_rd_qos_port0), .qos2(ddr_rd_qos_port1), .qos3(ddr_rd_qos_port2), .qos4(ddr_rd_qos_port3), .prt_req1(ddr_rd_req_port0), .prt_req2(ddr_rd_req_port1), .prt_req3(ddr_rd_req_port2), .prt_req4(ddr_rd_req_port3), .prt_data1(ddr_rd_data_port0), .prt_data2(ddr_rd_data_port1), .prt_data3(ddr_rd_data_port2), .prt_data4(ddr_rd_data_port3), .prt_addr1(ddr_rd_addr_port0), .prt_addr2(ddr_rd_addr_port1), .prt_addr3(ddr_rd_addr_port2), .prt_addr4(ddr_rd_addr_port3), .prt_bytes1(ddr_rd_bytes_port0), .prt_bytes2(ddr_rd_bytes_port1), .prt_bytes3(ddr_rd_bytes_port2), .prt_bytes4(ddr_rd_bytes_port3), .prt_dv1(ddr_rd_dv_port0), .prt_dv2(ddr_rd_dv_port1), .prt_dv3(ddr_rd_dv_port2), .prt_dv4(ddr_rd_dv_port3), .prt_qos(rd_qos), .prt_req(rd_req), .prt_data(rd_data), .prt_addr(rd_addr), .prt_bytes(rd_bytes), .prt_dv(rd_dv) ); processing_system7_bfm_v2_0_5_sparse_mem ddr(); reg [1:0] state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin wr_ack <= 0; rd_dv <= 0; state <= 2'd0; end else begin case(state) 0:begin state <= 0; wr_ack <= 0; rd_dv <= 0; if(wr_req) begin ddr.write_mem(wr_data , wr_addr, wr_bytes); wr_ack <= 1; state <= 1; end if(rd_req) begin ddr.read_mem(rd_data,rd_addr, rd_bytes); rd_dv <= 1; state <= 1; end end 1:begin wr_ack <= 0; rd_dv <= 0; state <= 0; end endcase end /// if end// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_ddrc.v * * Date : 2012-11 * * Description : Module that acts as controller for sparse memory (DDR). * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_ddrc( rstn, sw_clk, /* Goes to port 0 of DDR */ ddr_wr_ack_port0, ddr_wr_dv_port0, ddr_rd_req_port0, ddr_rd_dv_port0, ddr_wr_addr_port0, ddr_wr_data_port0, ddr_wr_bytes_port0, ddr_rd_addr_port0, ddr_rd_data_port0, ddr_rd_bytes_port0, ddr_wr_qos_port0, ddr_rd_qos_port0, /* Goes to port 1 of DDR */ ddr_wr_ack_port1, ddr_wr_dv_port1, ddr_rd_req_port1, ddr_rd_dv_port1, ddr_wr_addr_port1, ddr_wr_data_port1, ddr_wr_bytes_port1, ddr_rd_addr_port1, ddr_rd_data_port1, ddr_rd_bytes_port1, ddr_wr_qos_port1, ddr_rd_qos_port1, /* Goes to port2 of DDR */ ddr_wr_ack_port2, ddr_wr_dv_port2, ddr_rd_req_port2, ddr_rd_dv_port2, ddr_wr_addr_port2, ddr_wr_data_port2, ddr_wr_bytes_port2, ddr_rd_addr_port2, ddr_rd_data_port2, ddr_rd_bytes_port2, ddr_wr_qos_port2, ddr_rd_qos_port2, /* Goes to port3 of DDR */ ddr_wr_ack_port3, ddr_wr_dv_port3, ddr_rd_req_port3, ddr_rd_dv_port3, ddr_wr_addr_port3, ddr_wr_data_port3, ddr_wr_bytes_port3, ddr_rd_addr_port3, ddr_rd_data_port3, ddr_rd_bytes_port3, ddr_wr_qos_port3, ddr_rd_qos_port3 ); `include "processing_system7_bfm_v2_0_5_local_params.v" input rstn; input sw_clk; output ddr_wr_ack_port0; input ddr_wr_dv_port0; input ddr_rd_req_port0; output ddr_rd_dv_port0; input[addr_width-1:0] ddr_wr_addr_port0; input[max_burst_bits-1:0] ddr_wr_data_port0; input[max_burst_bytes_width:0] ddr_wr_bytes_port0; input[addr_width-1:0] ddr_rd_addr_port0; output[max_burst_bits-1:0] ddr_rd_data_port0; input[max_burst_bytes_width:0] ddr_rd_bytes_port0; input [axi_qos_width-1:0] ddr_wr_qos_port0; input [axi_qos_width-1:0] ddr_rd_qos_port0; output ddr_wr_ack_port1; input ddr_wr_dv_port1; input ddr_rd_req_port1; output ddr_rd_dv_port1; input[addr_width-1:0] ddr_wr_addr_port1; input[max_burst_bits-1:0] ddr_wr_data_port1; input[max_burst_bytes_width:0] ddr_wr_bytes_port1; input[addr_width-1:0] ddr_rd_addr_port1; output[max_burst_bits-1:0] ddr_rd_data_port1; input[max_burst_bytes_width:0] ddr_rd_bytes_port1; input[axi_qos_width-1:0] ddr_wr_qos_port1; input[axi_qos_width-1:0] ddr_rd_qos_port1; output ddr_wr_ack_port2; input ddr_wr_dv_port2; input ddr_rd_req_port2; output ddr_rd_dv_port2; input[addr_width-1:0] ddr_wr_addr_port2; input[max_burst_bits-1:0] ddr_wr_data_port2; input[max_burst_bytes_width:0] ddr_wr_bytes_port2; input[addr_width-1:0] ddr_rd_addr_port2; output[max_burst_bits-1:0] ddr_rd_data_port2; input[max_burst_bytes_width:0] ddr_rd_bytes_port2; input[axi_qos_width-1:0] ddr_wr_qos_port2; input[axi_qos_width-1:0] ddr_rd_qos_port2; output ddr_wr_ack_port3; input ddr_wr_dv_port3; input ddr_rd_req_port3; output ddr_rd_dv_port3; input[addr_width-1:0] ddr_wr_addr_port3; input[max_burst_bits-1:0] ddr_wr_data_port3; input[max_burst_bytes_width:0] ddr_wr_bytes_port3; input[addr_width-1:0] ddr_rd_addr_port3; output[max_burst_bits-1:0] ddr_rd_data_port3; input[max_burst_bytes_width:0] ddr_rd_bytes_port3; input[axi_qos_width-1:0] ddr_wr_qos_port3; input[axi_qos_width-1:0] ddr_rd_qos_port3; wire [axi_qos_width-1:0] wr_qos; wire wr_req; wire [max_burst_bits-1:0] wr_data; wire [addr_width-1:0] wr_addr; wire [max_burst_bytes_width:0] wr_bytes; reg wr_ack; wire [axi_qos_width-1:0] rd_qos; reg [max_burst_bits-1:0] rd_data; wire [addr_width-1:0] rd_addr; wire [max_burst_bytes_width:0] rd_bytes; reg rd_dv; wire rd_req; processing_system7_bfm_v2_0_5_arb_wr_4 ddr_write_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(ddr_wr_qos_port0), .qos2(ddr_wr_qos_port1), .qos3(ddr_wr_qos_port2), .qos4(ddr_wr_qos_port3), .prt_dv1(ddr_wr_dv_port0), .prt_dv2(ddr_wr_dv_port1), .prt_dv3(ddr_wr_dv_port2), .prt_dv4(ddr_wr_dv_port3), .prt_data1(ddr_wr_data_port0), .prt_data2(ddr_wr_data_port1), .prt_data3(ddr_wr_data_port2), .prt_data4(ddr_wr_data_port3), .prt_addr1(ddr_wr_addr_port0), .prt_addr2(ddr_wr_addr_port1), .prt_addr3(ddr_wr_addr_port2), .prt_addr4(ddr_wr_addr_port3), .prt_bytes1(ddr_wr_bytes_port0), .prt_bytes2(ddr_wr_bytes_port1), .prt_bytes3(ddr_wr_bytes_port2), .prt_bytes4(ddr_wr_bytes_port3), .prt_ack1(ddr_wr_ack_port0), .prt_ack2(ddr_wr_ack_port1), .prt_ack3(ddr_wr_ack_port2), .prt_ack4(ddr_wr_ack_port3), .prt_qos(wr_qos), .prt_req(wr_req), .prt_data(wr_data), .prt_addr(wr_addr), .prt_bytes(wr_bytes), .prt_ack(wr_ack) ); processing_system7_bfm_v2_0_5_arb_rd_4 ddr_read_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(ddr_rd_qos_port0), .qos2(ddr_rd_qos_port1), .qos3(ddr_rd_qos_port2), .qos4(ddr_rd_qos_port3), .prt_req1(ddr_rd_req_port0), .prt_req2(ddr_rd_req_port1), .prt_req3(ddr_rd_req_port2), .prt_req4(ddr_rd_req_port3), .prt_data1(ddr_rd_data_port0), .prt_data2(ddr_rd_data_port1), .prt_data3(ddr_rd_data_port2), .prt_data4(ddr_rd_data_port3), .prt_addr1(ddr_rd_addr_port0), .prt_addr2(ddr_rd_addr_port1), .prt_addr3(ddr_rd_addr_port2), .prt_addr4(ddr_rd_addr_port3), .prt_bytes1(ddr_rd_bytes_port0), .prt_bytes2(ddr_rd_bytes_port1), .prt_bytes3(ddr_rd_bytes_port2), .prt_bytes4(ddr_rd_bytes_port3), .prt_dv1(ddr_rd_dv_port0), .prt_dv2(ddr_rd_dv_port1), .prt_dv3(ddr_rd_dv_port2), .prt_dv4(ddr_rd_dv_port3), .prt_qos(rd_qos), .prt_req(rd_req), .prt_data(rd_data), .prt_addr(rd_addr), .prt_bytes(rd_bytes), .prt_dv(rd_dv) ); processing_system7_bfm_v2_0_5_sparse_mem ddr(); reg [1:0] state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin wr_ack <= 0; rd_dv <= 0; state <= 2'd0; end else begin case(state) 0:begin state <= 0; wr_ack <= 0; rd_dv <= 0; if(wr_req) begin ddr.write_mem(wr_data , wr_addr, wr_bytes); wr_ack <= 1; state <= 1; end if(rd_req) begin ddr.read_mem(rd_data,rd_addr, rd_bytes); rd_dv <= 1; state <= 1; end end 1:begin wr_ack <= 0; rd_dv <= 0; state <= 0; end endcase end /// if end// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_ddrc.v * * Date : 2012-11 * * Description : Module that acts as controller for sparse memory (DDR). * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_ddrc( rstn, sw_clk, /* Goes to port 0 of DDR */ ddr_wr_ack_port0, ddr_wr_dv_port0, ddr_rd_req_port0, ddr_rd_dv_port0, ddr_wr_addr_port0, ddr_wr_data_port0, ddr_wr_bytes_port0, ddr_rd_addr_port0, ddr_rd_data_port0, ddr_rd_bytes_port0, ddr_wr_qos_port0, ddr_rd_qos_port0, /* Goes to port 1 of DDR */ ddr_wr_ack_port1, ddr_wr_dv_port1, ddr_rd_req_port1, ddr_rd_dv_port1, ddr_wr_addr_port1, ddr_wr_data_port1, ddr_wr_bytes_port1, ddr_rd_addr_port1, ddr_rd_data_port1, ddr_rd_bytes_port1, ddr_wr_qos_port1, ddr_rd_qos_port1, /* Goes to port2 of DDR */ ddr_wr_ack_port2, ddr_wr_dv_port2, ddr_rd_req_port2, ddr_rd_dv_port2, ddr_wr_addr_port2, ddr_wr_data_port2, ddr_wr_bytes_port2, ddr_rd_addr_port2, ddr_rd_data_port2, ddr_rd_bytes_port2, ddr_wr_qos_port2, ddr_rd_qos_port2, /* Goes to port3 of DDR */ ddr_wr_ack_port3, ddr_wr_dv_port3, ddr_rd_req_port3, ddr_rd_dv_port3, ddr_wr_addr_port3, ddr_wr_data_port3, ddr_wr_bytes_port3, ddr_rd_addr_port3, ddr_rd_data_port3, ddr_rd_bytes_port3, ddr_wr_qos_port3, ddr_rd_qos_port3 ); `include "processing_system7_bfm_v2_0_5_local_params.v" input rstn; input sw_clk; output ddr_wr_ack_port0; input ddr_wr_dv_port0; input ddr_rd_req_port0; output ddr_rd_dv_port0; input[addr_width-1:0] ddr_wr_addr_port0; input[max_burst_bits-1:0] ddr_wr_data_port0; input[max_burst_bytes_width:0] ddr_wr_bytes_port0; input[addr_width-1:0] ddr_rd_addr_port0; output[max_burst_bits-1:0] ddr_rd_data_port0; input[max_burst_bytes_width:0] ddr_rd_bytes_port0; input [axi_qos_width-1:0] ddr_wr_qos_port0; input [axi_qos_width-1:0] ddr_rd_qos_port0; output ddr_wr_ack_port1; input ddr_wr_dv_port1; input ddr_rd_req_port1; output ddr_rd_dv_port1; input[addr_width-1:0] ddr_wr_addr_port1; input[max_burst_bits-1:0] ddr_wr_data_port1; input[max_burst_bytes_width:0] ddr_wr_bytes_port1; input[addr_width-1:0] ddr_rd_addr_port1; output[max_burst_bits-1:0] ddr_rd_data_port1; input[max_burst_bytes_width:0] ddr_rd_bytes_port1; input[axi_qos_width-1:0] ddr_wr_qos_port1; input[axi_qos_width-1:0] ddr_rd_qos_port1; output ddr_wr_ack_port2; input ddr_wr_dv_port2; input ddr_rd_req_port2; output ddr_rd_dv_port2; input[addr_width-1:0] ddr_wr_addr_port2; input[max_burst_bits-1:0] ddr_wr_data_port2; input[max_burst_bytes_width:0] ddr_wr_bytes_port2; input[addr_width-1:0] ddr_rd_addr_port2; output[max_burst_bits-1:0] ddr_rd_data_port2; input[max_burst_bytes_width:0] ddr_rd_bytes_port2; input[axi_qos_width-1:0] ddr_wr_qos_port2; input[axi_qos_width-1:0] ddr_rd_qos_port2; output ddr_wr_ack_port3; input ddr_wr_dv_port3; input ddr_rd_req_port3; output ddr_rd_dv_port3; input[addr_width-1:0] ddr_wr_addr_port3; input[max_burst_bits-1:0] ddr_wr_data_port3; input[max_burst_bytes_width:0] ddr_wr_bytes_port3; input[addr_width-1:0] ddr_rd_addr_port3; output[max_burst_bits-1:0] ddr_rd_data_port3; input[max_burst_bytes_width:0] ddr_rd_bytes_port3; input[axi_qos_width-1:0] ddr_wr_qos_port3; input[axi_qos_width-1:0] ddr_rd_qos_port3; wire [axi_qos_width-1:0] wr_qos; wire wr_req; wire [max_burst_bits-1:0] wr_data; wire [addr_width-1:0] wr_addr; wire [max_burst_bytes_width:0] wr_bytes; reg wr_ack; wire [axi_qos_width-1:0] rd_qos; reg [max_burst_bits-1:0] rd_data; wire [addr_width-1:0] rd_addr; wire [max_burst_bytes_width:0] rd_bytes; reg rd_dv; wire rd_req; processing_system7_bfm_v2_0_5_arb_wr_4 ddr_write_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(ddr_wr_qos_port0), .qos2(ddr_wr_qos_port1), .qos3(ddr_wr_qos_port2), .qos4(ddr_wr_qos_port3), .prt_dv1(ddr_wr_dv_port0), .prt_dv2(ddr_wr_dv_port1), .prt_dv3(ddr_wr_dv_port2), .prt_dv4(ddr_wr_dv_port3), .prt_data1(ddr_wr_data_port0), .prt_data2(ddr_wr_data_port1), .prt_data3(ddr_wr_data_port2), .prt_data4(ddr_wr_data_port3), .prt_addr1(ddr_wr_addr_port0), .prt_addr2(ddr_wr_addr_port1), .prt_addr3(ddr_wr_addr_port2), .prt_addr4(ddr_wr_addr_port3), .prt_bytes1(ddr_wr_bytes_port0), .prt_bytes2(ddr_wr_bytes_port1), .prt_bytes3(ddr_wr_bytes_port2), .prt_bytes4(ddr_wr_bytes_port3), .prt_ack1(ddr_wr_ack_port0), .prt_ack2(ddr_wr_ack_port1), .prt_ack3(ddr_wr_ack_port2), .prt_ack4(ddr_wr_ack_port3), .prt_qos(wr_qos), .prt_req(wr_req), .prt_data(wr_data), .prt_addr(wr_addr), .prt_bytes(wr_bytes), .prt_ack(wr_ack) ); processing_system7_bfm_v2_0_5_arb_rd_4 ddr_read_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(ddr_rd_qos_port0), .qos2(ddr_rd_qos_port1), .qos3(ddr_rd_qos_port2), .qos4(ddr_rd_qos_port3), .prt_req1(ddr_rd_req_port0), .prt_req2(ddr_rd_req_port1), .prt_req3(ddr_rd_req_port2), .prt_req4(ddr_rd_req_port3), .prt_data1(ddr_rd_data_port0), .prt_data2(ddr_rd_data_port1), .prt_data3(ddr_rd_data_port2), .prt_data4(ddr_rd_data_port3), .prt_addr1(ddr_rd_addr_port0), .prt_addr2(ddr_rd_addr_port1), .prt_addr3(ddr_rd_addr_port2), .prt_addr4(ddr_rd_addr_port3), .prt_bytes1(ddr_rd_bytes_port0), .prt_bytes2(ddr_rd_bytes_port1), .prt_bytes3(ddr_rd_bytes_port2), .prt_bytes4(ddr_rd_bytes_port3), .prt_dv1(ddr_rd_dv_port0), .prt_dv2(ddr_rd_dv_port1), .prt_dv3(ddr_rd_dv_port2), .prt_dv4(ddr_rd_dv_port3), .prt_qos(rd_qos), .prt_req(rd_req), .prt_data(rd_data), .prt_addr(rd_addr), .prt_bytes(rd_bytes), .prt_dv(rd_dv) ); processing_system7_bfm_v2_0_5_sparse_mem ddr(); reg [1:0] state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin wr_ack <= 0; rd_dv <= 0; state <= 2'd0; end else begin case(state) 0:begin state <= 0; wr_ack <= 0; rd_dv <= 0; if(wr_req) begin ddr.write_mem(wr_data , wr_addr, wr_bytes); wr_ack <= 1; state <= 1; end if(rd_req) begin ddr.read_mem(rd_data,rd_addr, rd_bytes); rd_dv <= 1; state <= 1; end end 1:begin wr_ack <= 0; rd_dv <= 0; state <= 0; end endcase end /// if end// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_ddrc.v * * Date : 2012-11 * * Description : Module that acts as controller for sparse memory (DDR). * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_ddrc( rstn, sw_clk, /* Goes to port 0 of DDR */ ddr_wr_ack_port0, ddr_wr_dv_port0, ddr_rd_req_port0, ddr_rd_dv_port0, ddr_wr_addr_port0, ddr_wr_data_port0, ddr_wr_bytes_port0, ddr_rd_addr_port0, ddr_rd_data_port0, ddr_rd_bytes_port0, ddr_wr_qos_port0, ddr_rd_qos_port0, /* Goes to port 1 of DDR */ ddr_wr_ack_port1, ddr_wr_dv_port1, ddr_rd_req_port1, ddr_rd_dv_port1, ddr_wr_addr_port1, ddr_wr_data_port1, ddr_wr_bytes_port1, ddr_rd_addr_port1, ddr_rd_data_port1, ddr_rd_bytes_port1, ddr_wr_qos_port1, ddr_rd_qos_port1, /* Goes to port2 of DDR */ ddr_wr_ack_port2, ddr_wr_dv_port2, ddr_rd_req_port2, ddr_rd_dv_port2, ddr_wr_addr_port2, ddr_wr_data_port2, ddr_wr_bytes_port2, ddr_rd_addr_port2, ddr_rd_data_port2, ddr_rd_bytes_port2, ddr_wr_qos_port2, ddr_rd_qos_port2, /* Goes to port3 of DDR */ ddr_wr_ack_port3, ddr_wr_dv_port3, ddr_rd_req_port3, ddr_rd_dv_port3, ddr_wr_addr_port3, ddr_wr_data_port3, ddr_wr_bytes_port3, ddr_rd_addr_port3, ddr_rd_data_port3, ddr_rd_bytes_port3, ddr_wr_qos_port3, ddr_rd_qos_port3 ); `include "processing_system7_bfm_v2_0_5_local_params.v" input rstn; input sw_clk; output ddr_wr_ack_port0; input ddr_wr_dv_port0; input ddr_rd_req_port0; output ddr_rd_dv_port0; input[addr_width-1:0] ddr_wr_addr_port0; input[max_burst_bits-1:0] ddr_wr_data_port0; input[max_burst_bytes_width:0] ddr_wr_bytes_port0; input[addr_width-1:0] ddr_rd_addr_port0; output[max_burst_bits-1:0] ddr_rd_data_port0; input[max_burst_bytes_width:0] ddr_rd_bytes_port0; input [axi_qos_width-1:0] ddr_wr_qos_port0; input [axi_qos_width-1:0] ddr_rd_qos_port0; output ddr_wr_ack_port1; input ddr_wr_dv_port1; input ddr_rd_req_port1; output ddr_rd_dv_port1; input[addr_width-1:0] ddr_wr_addr_port1; input[max_burst_bits-1:0] ddr_wr_data_port1; input[max_burst_bytes_width:0] ddr_wr_bytes_port1; input[addr_width-1:0] ddr_rd_addr_port1; output[max_burst_bits-1:0] ddr_rd_data_port1; input[max_burst_bytes_width:0] ddr_rd_bytes_port1; input[axi_qos_width-1:0] ddr_wr_qos_port1; input[axi_qos_width-1:0] ddr_rd_qos_port1; output ddr_wr_ack_port2; input ddr_wr_dv_port2; input ddr_rd_req_port2; output ddr_rd_dv_port2; input[addr_width-1:0] ddr_wr_addr_port2; input[max_burst_bits-1:0] ddr_wr_data_port2; input[max_burst_bytes_width:0] ddr_wr_bytes_port2; input[addr_width-1:0] ddr_rd_addr_port2; output[max_burst_bits-1:0] ddr_rd_data_port2; input[max_burst_bytes_width:0] ddr_rd_bytes_port2; input[axi_qos_width-1:0] ddr_wr_qos_port2; input[axi_qos_width-1:0] ddr_rd_qos_port2; output ddr_wr_ack_port3; input ddr_wr_dv_port3; input ddr_rd_req_port3; output ddr_rd_dv_port3; input[addr_width-1:0] ddr_wr_addr_port3; input[max_burst_bits-1:0] ddr_wr_data_port3; input[max_burst_bytes_width:0] ddr_wr_bytes_port3; input[addr_width-1:0] ddr_rd_addr_port3; output[max_burst_bits-1:0] ddr_rd_data_port3; input[max_burst_bytes_width:0] ddr_rd_bytes_port3; input[axi_qos_width-1:0] ddr_wr_qos_port3; input[axi_qos_width-1:0] ddr_rd_qos_port3; wire [axi_qos_width-1:0] wr_qos; wire wr_req; wire [max_burst_bits-1:0] wr_data; wire [addr_width-1:0] wr_addr; wire [max_burst_bytes_width:0] wr_bytes; reg wr_ack; wire [axi_qos_width-1:0] rd_qos; reg [max_burst_bits-1:0] rd_data; wire [addr_width-1:0] rd_addr; wire [max_burst_bytes_width:0] rd_bytes; reg rd_dv; wire rd_req; processing_system7_bfm_v2_0_5_arb_wr_4 ddr_write_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(ddr_wr_qos_port0), .qos2(ddr_wr_qos_port1), .qos3(ddr_wr_qos_port2), .qos4(ddr_wr_qos_port3), .prt_dv1(ddr_wr_dv_port0), .prt_dv2(ddr_wr_dv_port1), .prt_dv3(ddr_wr_dv_port2), .prt_dv4(ddr_wr_dv_port3), .prt_data1(ddr_wr_data_port0), .prt_data2(ddr_wr_data_port1), .prt_data3(ddr_wr_data_port2), .prt_data4(ddr_wr_data_port3), .prt_addr1(ddr_wr_addr_port0), .prt_addr2(ddr_wr_addr_port1), .prt_addr3(ddr_wr_addr_port2), .prt_addr4(ddr_wr_addr_port3), .prt_bytes1(ddr_wr_bytes_port0), .prt_bytes2(ddr_wr_bytes_port1), .prt_bytes3(ddr_wr_bytes_port2), .prt_bytes4(ddr_wr_bytes_port3), .prt_ack1(ddr_wr_ack_port0), .prt_ack2(ddr_wr_ack_port1), .prt_ack3(ddr_wr_ack_port2), .prt_ack4(ddr_wr_ack_port3), .prt_qos(wr_qos), .prt_req(wr_req), .prt_data(wr_data), .prt_addr(wr_addr), .prt_bytes(wr_bytes), .prt_ack(wr_ack) ); processing_system7_bfm_v2_0_5_arb_rd_4 ddr_read_ports ( .rstn(rstn), .sw_clk(sw_clk), .qos1(ddr_rd_qos_port0), .qos2(ddr_rd_qos_port1), .qos3(ddr_rd_qos_port2), .qos4(ddr_rd_qos_port3), .prt_req1(ddr_rd_req_port0), .prt_req2(ddr_rd_req_port1), .prt_req3(ddr_rd_req_port2), .prt_req4(ddr_rd_req_port3), .prt_data1(ddr_rd_data_port0), .prt_data2(ddr_rd_data_port1), .prt_data3(ddr_rd_data_port2), .prt_data4(ddr_rd_data_port3), .prt_addr1(ddr_rd_addr_port0), .prt_addr2(ddr_rd_addr_port1), .prt_addr3(ddr_rd_addr_port2), .prt_addr4(ddr_rd_addr_port3), .prt_bytes1(ddr_rd_bytes_port0), .prt_bytes2(ddr_rd_bytes_port1), .prt_bytes3(ddr_rd_bytes_port2), .prt_bytes4(ddr_rd_bytes_port3), .prt_dv1(ddr_rd_dv_port0), .prt_dv2(ddr_rd_dv_port1), .prt_dv3(ddr_rd_dv_port2), .prt_dv4(ddr_rd_dv_port3), .prt_qos(rd_qos), .prt_req(rd_req), .prt_data(rd_data), .prt_addr(rd_addr), .prt_bytes(rd_bytes), .prt_dv(rd_dv) ); processing_system7_bfm_v2_0_5_sparse_mem ddr(); reg [1:0] state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin wr_ack <= 0; rd_dv <= 0; state <= 2'd0; end else begin case(state) 0:begin state <= 0; wr_ack <= 0; rd_dv <= 0; if(wr_req) begin ddr.write_mem(wr_data , wr_addr, wr_bytes); wr_ack <= 1; state <= 1; end if(rd_req) begin ddr.read_mem(rd_data,rd_addr, rd_bytes); rd_dv <= 1; state <= 1; end end 1:begin wr_ack <= 0; rd_dv <= 0; state <= 0; end endcase end /// if end// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_arb_rd.v * * Date : 2012-11 * * Description : Module that arbitrates between 2 read requests from 2 ports. * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_arb_rd( rstn, sw_clk, qos1, qos2, prt_req1, prt_req2, prt_bytes1, prt_bytes2, prt_addr1, prt_addr2, prt_data1, prt_data2, prt_dv1, prt_dv2, prt_req, prt_qos, prt_addr, prt_bytes, prt_data, prt_dv ); `include "processing_system7_bfm_v2_0_5_local_params.v" input rstn, sw_clk; input [axi_qos_width-1:0] qos1,qos2; input prt_req1, prt_req2; input [addr_width-1:0] prt_addr1, prt_addr2; input [max_burst_bytes_width:0] prt_bytes1, prt_bytes2; output reg prt_dv1, prt_dv2; output reg [max_burst_bits-1:0] prt_data1,prt_data2; output reg prt_req; output reg [axi_qos_width-1:0] prt_qos; output reg [addr_width-1:0] prt_addr; output reg [max_burst_bytes_width:0] prt_bytes; input [max_burst_bits-1:0] prt_data; input prt_dv; parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_dv_low = 2'b11; reg [1:0] state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin state = wait_req; prt_req = 1'b0; prt_dv1 = 1'b0; prt_dv2 = 1'b0; prt_qos = 0; end else begin case(state) wait_req:begin state = wait_req; prt_dv1 = 1'b0; prt_dv2 = 1'b0; prt_req = 0; if(prt_req1 && !prt_req2) begin state = serv_req1; prt_req = 1; prt_qos = qos1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; end else if(!prt_req1 && prt_req2) begin state = serv_req2; prt_req = 1; prt_qos = qos2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; end else if(prt_req1 && prt_req2) begin if(qos1 > qos2) begin prt_req = 1; prt_qos = qos1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end else if(qos1 < qos2) begin prt_req = 1; prt_addr = prt_addr2; prt_qos = qos2; prt_bytes = prt_bytes2; state = serv_req2; end else begin prt_req = 1; prt_qos = qos1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end end end serv_req1:begin state = serv_req1; prt_dv2 = 1'b0; if(prt_dv) begin prt_dv1 = 1'b1; prt_data1 = prt_data; prt_req = 0; if(prt_req2) begin prt_req = 1; prt_qos = qos2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; state = serv_req2; end else begin state = wait_dv_low; //state = wait_req; end end end serv_req2:begin state = serv_req2; prt_dv1 = 1'b0; if(prt_dv) begin prt_dv2 = 1'b1; prt_data2 = prt_data; prt_req = 0; if(prt_req1) begin prt_req = 1; prt_qos = qos1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end else begin state = wait_dv_low; //state = wait_req; end end end wait_dv_low:begin prt_dv1 = 1'b0; prt_dv2 = 1'b0; state = wait_dv_low; if(!prt_dv) state = wait_req; end endcase end /// if else end /// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_arb_rd.v * * Date : 2012-11 * * Description : Module that arbitrates between 2 read requests from 2 ports. * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_arb_rd( rstn, sw_clk, qos1, qos2, prt_req1, prt_req2, prt_bytes1, prt_bytes2, prt_addr1, prt_addr2, prt_data1, prt_data2, prt_dv1, prt_dv2, prt_req, prt_qos, prt_addr, prt_bytes, prt_data, prt_dv ); `include "processing_system7_bfm_v2_0_5_local_params.v" input rstn, sw_clk; input [axi_qos_width-1:0] qos1,qos2; input prt_req1, prt_req2; input [addr_width-1:0] prt_addr1, prt_addr2; input [max_burst_bytes_width:0] prt_bytes1, prt_bytes2; output reg prt_dv1, prt_dv2; output reg [max_burst_bits-1:0] prt_data1,prt_data2; output reg prt_req; output reg [axi_qos_width-1:0] prt_qos; output reg [addr_width-1:0] prt_addr; output reg [max_burst_bytes_width:0] prt_bytes; input [max_burst_bits-1:0] prt_data; input prt_dv; parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_dv_low = 2'b11; reg [1:0] state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin state = wait_req; prt_req = 1'b0; prt_dv1 = 1'b0; prt_dv2 = 1'b0; prt_qos = 0; end else begin case(state) wait_req:begin state = wait_req; prt_dv1 = 1'b0; prt_dv2 = 1'b0; prt_req = 0; if(prt_req1 && !prt_req2) begin state = serv_req1; prt_req = 1; prt_qos = qos1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; end else if(!prt_req1 && prt_req2) begin state = serv_req2; prt_req = 1; prt_qos = qos2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; end else if(prt_req1 && prt_req2) begin if(qos1 > qos2) begin prt_req = 1; prt_qos = qos1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end else if(qos1 < qos2) begin prt_req = 1; prt_addr = prt_addr2; prt_qos = qos2; prt_bytes = prt_bytes2; state = serv_req2; end else begin prt_req = 1; prt_qos = qos1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end end end serv_req1:begin state = serv_req1; prt_dv2 = 1'b0; if(prt_dv) begin prt_dv1 = 1'b1; prt_data1 = prt_data; prt_req = 0; if(prt_req2) begin prt_req = 1; prt_qos = qos2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; state = serv_req2; end else begin state = wait_dv_low; //state = wait_req; end end end serv_req2:begin state = serv_req2; prt_dv1 = 1'b0; if(prt_dv) begin prt_dv2 = 1'b1; prt_data2 = prt_data; prt_req = 0; if(prt_req1) begin prt_req = 1; prt_qos = qos1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end else begin state = wait_dv_low; //state = wait_req; end end end wait_dv_low:begin prt_dv1 = 1'b0; prt_dv2 = 1'b0; state = wait_dv_low; if(!prt_dv) state = wait_req; end endcase end /// if else end /// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_arb_rd.v * * Date : 2012-11 * * Description : Module that arbitrates between 2 read requests from 2 ports. * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_arb_rd( rstn, sw_clk, qos1, qos2, prt_req1, prt_req2, prt_bytes1, prt_bytes2, prt_addr1, prt_addr2, prt_data1, prt_data2, prt_dv1, prt_dv2, prt_req, prt_qos, prt_addr, prt_bytes, prt_data, prt_dv ); `include "processing_system7_bfm_v2_0_5_local_params.v" input rstn, sw_clk; input [axi_qos_width-1:0] qos1,qos2; input prt_req1, prt_req2; input [addr_width-1:0] prt_addr1, prt_addr2; input [max_burst_bytes_width:0] prt_bytes1, prt_bytes2; output reg prt_dv1, prt_dv2; output reg [max_burst_bits-1:0] prt_data1,prt_data2; output reg prt_req; output reg [axi_qos_width-1:0] prt_qos; output reg [addr_width-1:0] prt_addr; output reg [max_burst_bytes_width:0] prt_bytes; input [max_burst_bits-1:0] prt_data; input prt_dv; parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_dv_low = 2'b11; reg [1:0] state; always@(posedge sw_clk or negedge rstn) begin if(!rstn) begin state = wait_req; prt_req = 1'b0; prt_dv1 = 1'b0; prt_dv2 = 1'b0; prt_qos = 0; end else begin case(state) wait_req:begin state = wait_req; prt_dv1 = 1'b0; prt_dv2 = 1'b0; prt_req = 0; if(prt_req1 && !prt_req2) begin state = serv_req1; prt_req = 1; prt_qos = qos1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; end else if(!prt_req1 && prt_req2) begin state = serv_req2; prt_req = 1; prt_qos = qos2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; end else if(prt_req1 && prt_req2) begin if(qos1 > qos2) begin prt_req = 1; prt_qos = qos1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end else if(qos1 < qos2) begin prt_req = 1; prt_addr = prt_addr2; prt_qos = qos2; prt_bytes = prt_bytes2; state = serv_req2; end else begin prt_req = 1; prt_qos = qos1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end end end serv_req1:begin state = serv_req1; prt_dv2 = 1'b0; if(prt_dv) begin prt_dv1 = 1'b1; prt_data1 = prt_data; prt_req = 0; if(prt_req2) begin prt_req = 1; prt_qos = qos2; prt_addr = prt_addr2; prt_bytes = prt_bytes2; state = serv_req2; end else begin state = wait_dv_low; //state = wait_req; end end end serv_req2:begin state = serv_req2; prt_dv1 = 1'b0; if(prt_dv) begin prt_dv2 = 1'b1; prt_data2 = prt_data; prt_req = 0; if(prt_req1) begin prt_req = 1; prt_qos = qos1; prt_addr = prt_addr1; prt_bytes = prt_bytes1; state = serv_req1; end else begin state = wait_dv_low; //state = wait_req; end end end wait_dv_low:begin prt_dv1 = 1'b0; prt_dv2 = 1'b0; state = wait_dv_low; if(!prt_dv) state = wait_req; end endcase end /// if else end /// always endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_5_ocm_mem.v * * Date : 2012-11 * * Description : Mimics OCM model * *****************************************************************************/ `timescale 1ns/1ps module processing_system7_bfm_v2_0_5_ocm_mem(); `include "processing_system7_bfm_v2_0_5_local_params.v" parameter mem_size = 32'h4_0000; /// 256 KB parameter mem_addr_width = clogb2(mem_size/mem_width); reg [data_width-1:0] ocm_memory [0:(mem_size/mem_width)-1]; /// 256 KB memory /* preload memory from file */ task automatic pre_load_mem_from_file; input [(max_chars*8)-1:0] file_name; input [addr_width-1:0] start_addr; input [int_width-1:0] no_of_bytes; $readmemh(file_name,ocm_memory,start_addr>>shft_addr_bits); endtask /* preload memory with some random data */ task automatic pre_load_mem; input [1:0] data_type; input [addr_width-1:0] start_addr; input [int_width-1:0] no_of_bytes; integer i; reg [mem_addr_width-1:0] addr; begin addr = start_addr >> shft_addr_bits; for (i = 0; i < no_of_bytes; i = i + mem_width) begin case(data_type) ALL_RANDOM : ocm_memory[addr] = $random; ALL_ZEROS : ocm_memory[addr] = 32'h0000_0000; ALL_ONES : ocm_memory[addr] = 32'hFFFF_FFFF; default : ocm_memory[addr] = $random; endcase addr = addr+1; end end endtask /* Write memory */ task write_mem; input [max_burst_bits-1 :0] data; input [addr_width-1:0] start_addr; input [max_burst_bytes_width:0] no_of_bytes; reg [mem_addr_width-1:0] addr; reg [max_burst_bits-1 :0] wr_temp_data; reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data; integer bytes_left; integer pre_pad_bytes; integer post_pad_bytes; begin addr = start_addr >> shft_addr_bits; wr_temp_data = data; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : Writing OCM Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data); `endif temp_data = wr_temp_data[data_width-1:0]; bytes_left = no_of_bytes; /* when the no. of bytes to be updated is less than mem_width */ if(bytes_left < mem_width) begin /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ if(start_addr[shft_addr_bits-1:0] > 0) begin temp_data = ocm_memory[addr]; pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; repeat(pre_pad_bytes) temp_data = temp_data << 8; repeat(pre_pad_bytes) begin temp_data = temp_data >> 8; temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; wr_temp_data = wr_temp_data >> 8; end bytes_left = bytes_left + pre_pad_bytes; end /* This is needed for post padding the data ...*/ post_pad_bytes = mem_width - bytes_left; post_pad_data = ocm_memory[addr]; repeat(post_pad_bytes) temp_data = temp_data << 8; repeat(bytes_left) post_pad_data = post_pad_data >> 8; repeat(post_pad_bytes) begin temp_data = temp_data >> 8; temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; post_pad_data = post_pad_data >> 8; end ocm_memory[addr] = temp_data; end else begin /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ if(start_addr[shft_addr_bits-1:0] > 0) begin temp_data = ocm_memory[addr]; pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; repeat(pre_pad_bytes) temp_data = temp_data << 8; repeat(pre_pad_bytes) begin temp_data = temp_data >> 8; temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; wr_temp_data = wr_temp_data >> 8; bytes_left = bytes_left -1; end end else begin wr_temp_data = wr_temp_data >> data_width; bytes_left = bytes_left - mem_width; end /* first data word end */ ocm_memory[addr] = temp_data; addr = addr + 1; while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes. ocm_memory[addr] = wr_temp_data[data_width-1:0]; addr = addr+1; wr_temp_data = wr_temp_data >> data_width; bytes_left = bytes_left - mem_width; end post_pad_data = ocm_memory[addr]; post_pad_bytes = mem_width - bytes_left; /* This is needed for last transfer in unaliged burst */ if(bytes_left > 0) begin temp_data = wr_temp_data[data_width-1:0]; repeat(post_pad_bytes) temp_data = temp_data << 8; repeat(bytes_left) post_pad_data = post_pad_data >> 8; repeat(post_pad_bytes) begin temp_data = temp_data >> 8; temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; post_pad_data = post_pad_data >> 8; end ocm_memory[addr] = temp_data; end end `ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing OCM Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr ); `endif end endtask /* read_memory */ task read_mem; output[max_burst_bits-1 :0] data; input [addr_width-1:0] start_addr; input [max_burst_bytes_width:0] no_of_bytes; integer i; reg [mem_addr_width-1:0] addr; reg [data_width-1:0] temp_rd_data; reg [max_burst_bits-1:0] temp_data; integer pre_bytes; integer bytes_left; begin addr = start_addr >> shft_addr_bits; pre_bytes = start_addr[shft_addr_bits-1:0]; bytes_left = no_of_bytes; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : Reading OCM Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); `endif /* Get first data ... if unaligned address */ temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr]; if(no_of_bytes < mem_width ) begin temp_data = temp_data >> (pre_bytes * 8); repeat(max_burst_bytes - mem_width) temp_data = temp_data >> 8; end else begin bytes_left = bytes_left - (mem_width - pre_bytes); addr = addr+1; /* Got first data */ while (bytes_left > (mem_width-1) ) begin temp_data = temp_data >> data_width; temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr]; addr = addr+1; bytes_left = bytes_left - mem_width; end /* Get last valid data in the burst*/ temp_rd_data = ocm_memory[addr]; while(bytes_left > 0) begin temp_data = temp_data >> 8; temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; temp_rd_data = temp_rd_data >> 8; bytes_left = bytes_left - 1; end /* align to the brst_byte length */ repeat(max_burst_bytes - no_of_bytes) temp_data = temp_data >> 8; end data = temp_data; `ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Reading OCM Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); `endif end endtask /* backdoor read to memory */ task peek_mem_to_file; input [(max_chars*8)-1:0] file_name; input [addr_width-1:0] start_addr; input [int_width-1:0] no_of_bytes; integer rd_fd; integer bytes; reg [addr_width-1:0] addr; reg [data_width-1:0] rd_data; begin rd_fd = $fopen(file_name,"w"); bytes = no_of_bytes; addr = start_addr >> shft_addr_bits; while (bytes > 0) begin rd_data = ocm_memory[addr]; $fdisplayh(rd_fd,rd_data); bytes = bytes - 4; addr = addr + 1; end end endtask endmodule