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// megafunction wizard: %ALTACCUMULATE%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altaccumulate
// ============================================================
// File Name: accum32.v
// Megafunction Name(s):
// altaccumulate
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result
//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
//synthesis_resources = lut 32
module accum32_accum_nta
(
aclr,
clken,
clock,
data,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] data;
output [31:0] result;
wire [0:0] wire_acc_cella_0cout;
wire [0:0] wire_acc_cella_1cout;
wire [0:0] wire_acc_cella_2cout;
wire [0:0] wire_acc_cella_3cout;
wire [0:0] wire_acc_cella_4cout;
wire [0:0] wire_acc_cella_5cout;
wire [0:0] wire_acc_cella_6cout;
wire [0:0] wire_acc_cella_7cout;
wire [0:0] wire_acc_cella_8cout;
wire [0:0] wire_acc_cella_9cout;
wire [0:0] wire_acc_cella_10cout;
wire [0:0] wire_acc_cella_11cout;
wire [0:0] wire_acc_cella_12cout;
wire [0:0] wire_acc_cella_13cout;
wire [0:0] wire_acc_cella_14cout;
wire [0:0] wire_acc_cella_15cout;
wire [0:0] wire_acc_cella_16cout;
wire [0:0] wire_acc_cella_17cout;
wire [0:0] wire_acc_cella_18cout;
wire [0:0] wire_acc_cella_19cout;
wire [0:0] wire_acc_cella_20cout;
wire [0:0] wire_acc_cella_21cout;
wire [0:0] wire_acc_cella_22cout;
wire [0:0] wire_acc_cella_23cout;
wire [0:0] wire_acc_cella_24cout;
wire [0:0] wire_acc_cella_25cout;
wire [0:0] wire_acc_cella_26cout;
wire [0:0] wire_acc_cella_27cout;
wire [0:0] wire_acc_cella_28cout;
wire [0:0] wire_acc_cella_29cout;
wire [0:0] wire_acc_cella_30cout;
wire [31:0] wire_acc_cella_dataa;
wire [31:0] wire_acc_cella_datab;
wire [31:0] wire_acc_cella_datac;
wire [31:0] wire_acc_cella_regout;
wire sload;
stratix_lcell acc_cella_0
(
.aclr(aclr),
.cin(1'b0),
.clk(clock),
.cout(wire_acc_cella_0cout[0:0]),
.dataa(wire_acc_cella_dataa[0:0]),
.datab(wire_acc_cella_datab[0:0]),
.datac(wire_acc_cella_datac[0:0]),
.ena(clken),
.regout(wire_acc_cella_regout[0:0]),
.sload(sload));
defparam
acc_cella_0.cin_used = "true",
acc_cella_0.lut_mask = "96e8",
acc_cella_0.operation_mode = "arithmetic",
acc_cella_0.sum_lutc_input = "cin",
acc_cella_0.synch_mode = "on",
acc_cella_0.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_1
(
.aclr(aclr),
.cin(wire_acc_cella_0cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_1cout[0:0]),
.dataa(wire_acc_cella_dataa[1:1]),
.datab(wire_acc_cella_datab[1:1]),
.datac(wire_acc_cella_datac[1:1]),
.ena(clken),
.regout(wire_acc_cella_regout[1:1]),
.sload(sload));
defparam
acc_cella_1.cin_used = "true",
acc_cella_1.lut_mask = "96e8",
acc_cella_1.operation_mode = "arithmetic",
acc_cella_1.sum_lutc_input = "cin",
acc_cella_1.synch_mode = "on",
acc_cella_1.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_2
(
.aclr(aclr),
.cin(wire_acc_cella_1cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_2cout[0:0]),
.dataa(wire_acc_cella_dataa[2:2]),
.datab(wire_acc_cella_datab[2:2]),
.datac(wire_acc_cella_datac[2:2]),
.ena(clken),
.regout(wire_acc_cella_regout[2:2]),
.sload(sload));
defparam
acc_cella_2.cin_used = "true",
acc_cella_2.lut_mask = "96e8",
acc_cella_2.operation_mode = "arithmetic",
acc_cella_2.sum_lutc_input = "cin",
acc_cella_2.synch_mode = "on",
acc_cella_2.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_3
(
.aclr(aclr),
.cin(wire_acc_cella_2cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_3cout[0:0]),
.dataa(wire_acc_cella_dataa[3:3]),
.datab(wire_acc_cella_datab[3:3]),
.datac(wire_acc_cella_datac[3:3]),
.ena(clken),
.regout(wire_acc_cella_regout[3:3]),
.sload(sload));
defparam
acc_cella_3.cin_used = "true",
acc_cella_3.lut_mask = "96e8",
acc_cella_3.operation_mode = "arithmetic",
acc_cella_3.sum_lutc_input = "cin",
acc_cella_3.synch_mode = "on",
acc_cella_3.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_4
(
.aclr(aclr),
.cin(wire_acc_cella_3cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_4cout[0:0]),
.dataa(wire_acc_cella_dataa[4:4]),
.datab(wire_acc_cella_datab[4:4]),
.datac(wire_acc_cella_datac[4:4]),
.ena(clken),
.regout(wire_acc_cella_regout[4:4]),
.sload(sload));
defparam
acc_cella_4.cin_used = "true",
acc_cella_4.lut_mask = "96e8",
acc_cella_4.operation_mode = "arithmetic",
acc_cella_4.sum_lutc_input = "cin",
acc_cella_4.synch_mode = "on",
acc_cella_4.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_5
(
.aclr(aclr),
.cin(wire_acc_cella_4cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_5cout[0:0]),
.dataa(wire_acc_cella_dataa[5:5]),
.datab(wire_acc_cella_datab[5:5]),
.datac(wire_acc_cella_datac[5:5]),
.ena(clken),
.regout(wire_acc_cella_regout[5:5]),
.sload(sload));
defparam
acc_cella_5.cin_used = "true",
acc_cella_5.lut_mask = "96e8",
acc_cella_5.operation_mode = "arithmetic",
acc_cella_5.sum_lutc_input = "cin",
acc_cella_5.synch_mode = "on",
acc_cella_5.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_6
(
.aclr(aclr),
.cin(wire_acc_cella_5cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_6cout[0:0]),
.dataa(wire_acc_cella_dataa[6:6]),
.datab(wire_acc_cella_datab[6:6]),
.datac(wire_acc_cella_datac[6:6]),
.ena(clken),
.regout(wire_acc_cella_regout[6:6]),
.sload(sload));
defparam
acc_cella_6.cin_used = "true",
acc_cella_6.lut_mask = "96e8",
acc_cella_6.operation_mode = "arithmetic",
acc_cella_6.sum_lutc_input = "cin",
acc_cella_6.synch_mode = "on",
acc_cella_6.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_7
(
.aclr(aclr),
.cin(wire_acc_cella_6cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_7cout[0:0]),
.dataa(wire_acc_cella_dataa[7:7]),
.datab(wire_acc_cella_datab[7:7]),
.datac(wire_acc_cella_datac[7:7]),
.ena(clken),
.regout(wire_acc_cella_regout[7:7]),
.sload(sload));
defparam
acc_cella_7.cin_used = "true",
acc_cella_7.lut_mask = "96e8",
acc_cella_7.operation_mode = "arithmetic",
acc_cella_7.sum_lutc_input = "cin",
acc_cella_7.synch_mode = "on",
acc_cella_7.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_8
(
.aclr(aclr),
.cin(wire_acc_cella_7cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_8cout[0:0]),
.dataa(wire_acc_cella_dataa[8:8]),
.datab(wire_acc_cella_datab[8:8]),
.datac(wire_acc_cella_datac[8:8]),
.ena(clken),
.regout(wire_acc_cella_regout[8:8]),
.sload(sload));
defparam
acc_cella_8.cin_used = "true",
acc_cella_8.lut_mask = "96e8",
acc_cella_8.operation_mode = "arithmetic",
acc_cella_8.sum_lutc_input = "cin",
acc_cella_8.synch_mode = "on",
acc_cella_8.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_9
(
.aclr(aclr),
.cin(wire_acc_cella_8cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_9cout[0:0]),
.dataa(wire_acc_cella_dataa[9:9]),
.datab(wire_acc_cella_datab[9:9]),
.datac(wire_acc_cella_datac[9:9]),
.ena(clken),
.regout(wire_acc_cella_regout[9:9]),
.sload(sload));
defparam
acc_cella_9.cin_used = "true",
acc_cella_9.lut_mask = "96e8",
acc_cella_9.operation_mode = "arithmetic",
acc_cella_9.sum_lutc_input = "cin",
acc_cella_9.synch_mode = "on",
acc_cella_9.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_10
(
.aclr(aclr),
.cin(wire_acc_cella_9cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_10cout[0:0]),
.dataa(wire_acc_cella_dataa[10:10]),
.datab(wire_acc_cella_datab[10:10]),
.datac(wire_acc_cella_datac[10:10]),
.ena(clken),
.regout(wire_acc_cella_regout[10:10]),
.sload(sload));
defparam
acc_cella_10.cin_used = "true",
acc_cella_10.lut_mask = "96e8",
acc_cella_10.operation_mode = "arithmetic",
acc_cella_10.sum_lutc_input = "cin",
acc_cella_10.synch_mode = "on",
acc_cella_10.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_11
(
.aclr(aclr),
.cin(wire_acc_cella_10cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_11cout[0:0]),
.dataa(wire_acc_cella_dataa[11:11]),
.datab(wire_acc_cella_datab[11:11]),
.datac(wire_acc_cella_datac[11:11]),
.ena(clken),
.regout(wire_acc_cella_regout[11:11]),
.sload(sload));
defparam
acc_cella_11.cin_used = "true",
acc_cella_11.lut_mask = "96e8",
acc_cella_11.operation_mode = "arithmetic",
acc_cella_11.sum_lutc_input = "cin",
acc_cella_11.synch_mode = "on",
acc_cella_11.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_12
(
.aclr(aclr),
.cin(wire_acc_cella_11cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_12cout[0:0]),
.dataa(wire_acc_cella_dataa[12:12]),
.datab(wire_acc_cella_datab[12:12]),
.datac(wire_acc_cella_datac[12:12]),
.ena(clken),
.regout(wire_acc_cella_regout[12:12]),
.sload(sload));
defparam
acc_cella_12.cin_used = "true",
acc_cella_12.lut_mask = "96e8",
acc_cella_12.operation_mode = "arithmetic",
acc_cella_12.sum_lutc_input = "cin",
acc_cella_12.synch_mode = "on",
acc_cella_12.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_13
(
.aclr(aclr),
.cin(wire_acc_cella_12cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_13cout[0:0]),
.dataa(wire_acc_cella_dataa[13:13]),
.datab(wire_acc_cella_datab[13:13]),
.datac(wire_acc_cella_datac[13:13]),
.ena(clken),
.regout(wire_acc_cella_regout[13:13]),
.sload(sload));
defparam
acc_cella_13.cin_used = "true",
acc_cella_13.lut_mask = "96e8",
acc_cella_13.operation_mode = "arithmetic",
acc_cella_13.sum_lutc_input = "cin",
acc_cella_13.synch_mode = "on",
acc_cella_13.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_14
(
.aclr(aclr),
.cin(wire_acc_cella_13cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_14cout[0:0]),
.dataa(wire_acc_cella_dataa[14:14]),
.datab(wire_acc_cella_datab[14:14]),
.datac(wire_acc_cella_datac[14:14]),
.ena(clken),
.regout(wire_acc_cella_regout[14:14]),
.sload(sload));
defparam
acc_cella_14.cin_used = "true",
acc_cella_14.lut_mask = "96e8",
acc_cella_14.operation_mode = "arithmetic",
acc_cella_14.sum_lutc_input = "cin",
acc_cella_14.synch_mode = "on",
acc_cella_14.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_15
(
.aclr(aclr),
.cin(wire_acc_cella_14cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_15cout[0:0]),
.dataa(wire_acc_cella_dataa[15:15]),
.datab(wire_acc_cella_datab[15:15]),
.datac(wire_acc_cella_datac[15:15]),
.ena(clken),
.regout(wire_acc_cella_regout[15:15]),
.sload(sload));
defparam
acc_cella_15.cin_used = "true",
acc_cella_15.lut_mask = "96e8",
acc_cella_15.operation_mode = "arithmetic",
acc_cella_15.sum_lutc_input = "cin",
acc_cella_15.synch_mode = "on",
acc_cella_15.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_16
(
.aclr(aclr),
.cin(wire_acc_cella_15cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_16cout[0:0]),
.dataa(wire_acc_cella_dataa[16:16]),
.datab(wire_acc_cella_datab[16:16]),
.datac(wire_acc_cella_datac[16:16]),
.ena(clken),
.regout(wire_acc_cella_regout[16:16]),
.sload(sload));
defparam
acc_cella_16.cin_used = "true",
acc_cella_16.lut_mask = "96e8",
acc_cella_16.operation_mode = "arithmetic",
acc_cella_16.sum_lutc_input = "cin",
acc_cella_16.synch_mode = "on",
acc_cella_16.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_17
(
.aclr(aclr),
.cin(wire_acc_cella_16cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_17cout[0:0]),
.dataa(wire_acc_cella_dataa[17:17]),
.datab(wire_acc_cella_datab[17:17]),
.datac(wire_acc_cella_datac[17:17]),
.ena(clken),
.regout(wire_acc_cella_regout[17:17]),
.sload(sload));
defparam
acc_cella_17.cin_used = "true",
acc_cella_17.lut_mask = "96e8",
acc_cella_17.operation_mode = "arithmetic",
acc_cella_17.sum_lutc_input = "cin",
acc_cella_17.synch_mode = "on",
acc_cella_17.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_18
(
.aclr(aclr),
.cin(wire_acc_cella_17cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_18cout[0:0]),
.dataa(wire_acc_cella_dataa[18:18]),
.datab(wire_acc_cella_datab[18:18]),
.datac(wire_acc_cella_datac[18:18]),
.ena(clken),
.regout(wire_acc_cella_regout[18:18]),
.sload(sload));
defparam
acc_cella_18.cin_used = "true",
acc_cella_18.lut_mask = "96e8",
acc_cella_18.operation_mode = "arithmetic",
acc_cella_18.sum_lutc_input = "cin",
acc_cella_18.synch_mode = "on",
acc_cella_18.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_19
(
.aclr(aclr),
.cin(wire_acc_cella_18cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_19cout[0:0]),
.dataa(wire_acc_cella_dataa[19:19]),
.datab(wire_acc_cella_datab[19:19]),
.datac(wire_acc_cella_datac[19:19]),
.ena(clken),
.regout(wire_acc_cella_regout[19:19]),
.sload(sload));
defparam
acc_cella_19.cin_used = "true",
acc_cella_19.lut_mask = "96e8",
acc_cella_19.operation_mode = "arithmetic",
acc_cella_19.sum_lutc_input = "cin",
acc_cella_19.synch_mode = "on",
acc_cella_19.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_20
(
.aclr(aclr),
.cin(wire_acc_cella_19cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_20cout[0:0]),
.dataa(wire_acc_cella_dataa[20:20]),
.datab(wire_acc_cella_datab[20:20]),
.datac(wire_acc_cella_datac[20:20]),
.ena(clken),
.regout(wire_acc_cella_regout[20:20]),
.sload(sload));
defparam
acc_cella_20.cin_used = "true",
acc_cella_20.lut_mask = "96e8",
acc_cella_20.operation_mode = "arithmetic",
acc_cella_20.sum_lutc_input = "cin",
acc_cella_20.synch_mode = "on",
acc_cella_20.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_21
(
.aclr(aclr),
.cin(wire_acc_cella_20cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_21cout[0:0]),
.dataa(wire_acc_cella_dataa[21:21]),
.datab(wire_acc_cella_datab[21:21]),
.datac(wire_acc_cella_datac[21:21]),
.ena(clken),
.regout(wire_acc_cella_regout[21:21]),
.sload(sload));
defparam
acc_cella_21.cin_used = "true",
acc_cella_21.lut_mask = "96e8",
acc_cella_21.operation_mode = "arithmetic",
acc_cella_21.sum_lutc_input = "cin",
acc_cella_21.synch_mode = "on",
acc_cella_21.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_22
(
.aclr(aclr),
.cin(wire_acc_cella_21cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_22cout[0:0]),
.dataa(wire_acc_cella_dataa[22:22]),
.datab(wire_acc_cella_datab[22:22]),
.datac(wire_acc_cella_datac[22:22]),
.ena(clken),
.regout(wire_acc_cella_regout[22:22]),
.sload(sload));
defparam
acc_cella_22.cin_used = "true",
acc_cella_22.lut_mask = "96e8",
acc_cella_22.operation_mode = "arithmetic",
acc_cella_22.sum_lutc_input = "cin",
acc_cella_22.synch_mode = "on",
acc_cella_22.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_23
(
.aclr(aclr),
.cin(wire_acc_cella_22cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_23cout[0:0]),
.dataa(wire_acc_cella_dataa[23:23]),
.datab(wire_acc_cella_datab[23:23]),
.datac(wire_acc_cella_datac[23:23]),
.ena(clken),
.regout(wire_acc_cella_regout[23:23]),
.sload(sload));
defparam
acc_cella_23.cin_used = "true",
acc_cella_23.lut_mask = "96e8",
acc_cella_23.operation_mode = "arithmetic",
acc_cella_23.sum_lutc_input = "cin",
acc_cella_23.synch_mode = "on",
acc_cella_23.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_24
(
.aclr(aclr),
.cin(wire_acc_cella_23cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_24cout[0:0]),
.dataa(wire_acc_cella_dataa[24:24]),
.datab(wire_acc_cella_datab[24:24]),
.datac(wire_acc_cella_datac[24:24]),
.ena(clken),
.regout(wire_acc_cella_regout[24:24]),
.sload(sload));
defparam
acc_cella_24.cin_used = "true",
acc_cella_24.lut_mask = "96e8",
acc_cella_24.operation_mode = "arithmetic",
acc_cella_24.sum_lutc_input = "cin",
acc_cella_24.synch_mode = "on",
acc_cella_24.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_25
(
.aclr(aclr),
.cin(wire_acc_cella_24cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_25cout[0:0]),
.dataa(wire_acc_cella_dataa[25:25]),
.datab(wire_acc_cella_datab[25:25]),
.datac(wire_acc_cella_datac[25:25]),
.ena(clken),
.regout(wire_acc_cella_regout[25:25]),
.sload(sload));
defparam
acc_cella_25.cin_used = "true",
acc_cella_25.lut_mask = "96e8",
acc_cella_25.operation_mode = "arithmetic",
acc_cella_25.sum_lutc_input = "cin",
acc_cella_25.synch_mode = "on",
acc_cella_25.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_26
(
.aclr(aclr),
.cin(wire_acc_cella_25cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_26cout[0:0]),
.dataa(wire_acc_cella_dataa[26:26]),
.datab(wire_acc_cella_datab[26:26]),
.datac(wire_acc_cella_datac[26:26]),
.ena(clken),
.regout(wire_acc_cella_regout[26:26]),
.sload(sload));
defparam
acc_cella_26.cin_used = "true",
acc_cella_26.lut_mask = "96e8",
acc_cella_26.operation_mode = "arithmetic",
acc_cella_26.sum_lutc_input = "cin",
acc_cella_26.synch_mode = "on",
acc_cella_26.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_27
(
.aclr(aclr),
.cin(wire_acc_cella_26cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_27cout[0:0]),
.dataa(wire_acc_cella_dataa[27:27]),
.datab(wire_acc_cella_datab[27:27]),
.datac(wire_acc_cella_datac[27:27]),
.ena(clken),
.regout(wire_acc_cella_regout[27:27]),
.sload(sload));
defparam
acc_cella_27.cin_used = "true",
acc_cella_27.lut_mask = "96e8",
acc_cella_27.operation_mode = "arithmetic",
acc_cella_27.sum_lutc_input = "cin",
acc_cella_27.synch_mode = "on",
acc_cella_27.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_28
(
.aclr(aclr),
.cin(wire_acc_cella_27cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_28cout[0:0]),
.dataa(wire_acc_cella_dataa[28:28]),
.datab(wire_acc_cella_datab[28:28]),
.datac(wire_acc_cella_datac[28:28]),
.ena(clken),
.regout(wire_acc_cella_regout[28:28]),
.sload(sload));
defparam
acc_cella_28.cin_used = "true",
acc_cella_28.lut_mask = "96e8",
acc_cella_28.operation_mode = "arithmetic",
acc_cella_28.sum_lutc_input = "cin",
acc_cella_28.synch_mode = "on",
acc_cella_28.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_29
(
.aclr(aclr),
.cin(wire_acc_cella_28cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_29cout[0:0]),
.dataa(wire_acc_cella_dataa[29:29]),
.datab(wire_acc_cella_datab[29:29]),
.datac(wire_acc_cella_datac[29:29]),
.ena(clken),
.regout(wire_acc_cella_regout[29:29]),
.sload(sload));
defparam
acc_cella_29.cin_used = "true",
acc_cella_29.lut_mask = "96e8",
acc_cella_29.operation_mode = "arithmetic",
acc_cella_29.sum_lutc_input = "cin",
acc_cella_29.synch_mode = "on",
acc_cella_29.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_30
(
.aclr(aclr),
.cin(wire_acc_cella_29cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_30cout[0:0]),
.dataa(wire_acc_cella_dataa[30:30]),
.datab(wire_acc_cella_datab[30:30]),
.datac(wire_acc_cella_datac[30:30]),
.ena(clken),
.regout(wire_acc_cella_regout[30:30]),
.sload(sload));
defparam
acc_cella_30.cin_used = "true",
acc_cella_30.lut_mask = "96e8",
acc_cella_30.operation_mode = "arithmetic",
acc_cella_30.sum_lutc_input = "cin",
acc_cella_30.synch_mode = "on",
acc_cella_30.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_31
(
.aclr(aclr),
.cin(wire_acc_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_acc_cella_dataa[31:31]),
.datab(wire_acc_cella_datab[31:31]),
.datac(wire_acc_cella_datac[31:31]),
.ena(clken),
.regout(wire_acc_cella_regout[31:31]),
.sload(sload));
defparam
acc_cella_31.cin_used = "true",
acc_cella_31.lut_mask = "9696",
acc_cella_31.operation_mode = "normal",
acc_cella_31.sum_lutc_input = "cin",
acc_cella_31.synch_mode = "on",
acc_cella_31.lpm_type = "stratix_lcell";
assign
wire_acc_cella_dataa = data,
wire_acc_cella_datab = wire_acc_cella_regout,
wire_acc_cella_datac = data;
assign
result = wire_acc_cella_regout,
sload = 1'b0;
endmodule //accum32_accum_nta
//VALID FILE
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
accum32_accum_nta accum32_accum_nta_component (
.clken (clken),
.aclr (aclr),
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: WIDTH_IN NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32"
// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
// Retrieval info: PRIVATE: CIN NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: COUT NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: WIDTH_IN NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:16:09 07/10/2009
// Design Name:
// Module Name: spi
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
reg [2:0] SSELr;
reg [2:0] SSELSCKr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
wire SSEL_inactive = SSELr[1];
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
assign endmessage = SSEL_endmessage;
assign startmessage = SSEL_startmessage;
// bit count for one SPI byte + byte count for the message
reg [2:0] bitcnt;
initial bitcnt = 3'b000;
wire bitcnt_msb = bitcnt[2];
reg [2:0] bitcnt_wrap_r;
always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
reg [31:0] byte_cnt_r;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
assign bit_cnt = bitcnt;
always @(posedge SCK) begin
if(SSELSCKr[1]) bitcnt <= 3'b000;
else bitcnt <= bitcnt + 3'b001;
end
always @(posedge SCK) begin
if(~SSELSCKr[1])
byte_data_received <= {byte_data_received[6:0], MOSI};
if(~SSELSCKr[1] && bitcnt==3'b111)
byte_received <= 1'b1;
else byte_received <= 1'b0;
end
//reg [2:0] byte_received_r;
//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
always @(posedge clk) begin
if(SSEL_inactive)
byte_cnt_r <= 16'h0000;
else if(byte_received_sync)
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
reg [7:0] byte_data_sent;
assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
reg cmd_ready_r;
reg param_ready_r;
reg cmd_ready_r2;
reg param_ready_r2;
assign cmd_ready = cmd_ready_r;
assign param_ready = param_ready_r;
assign cmd_data = cmd_data_r;
assign param_data = param_data_r;
assign byte_cnt = byte_cnt_r;
always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:16:09 07/10/2009
// Design Name:
// Module Name: spi
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
reg [2:0] SSELr;
reg [2:0] SSELSCKr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
wire SSEL_inactive = SSELr[1];
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
assign endmessage = SSEL_endmessage;
assign startmessage = SSEL_startmessage;
// bit count for one SPI byte + byte count for the message
reg [2:0] bitcnt;
initial bitcnt = 3'b000;
wire bitcnt_msb = bitcnt[2];
reg [2:0] bitcnt_wrap_r;
always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
reg [31:0] byte_cnt_r;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
assign bit_cnt = bitcnt;
always @(posedge SCK) begin
if(SSELSCKr[1]) bitcnt <= 3'b000;
else bitcnt <= bitcnt + 3'b001;
end
always @(posedge SCK) begin
if(~SSELSCKr[1])
byte_data_received <= {byte_data_received[6:0], MOSI};
if(~SSELSCKr[1] && bitcnt==3'b111)
byte_received <= 1'b1;
else byte_received <= 1'b0;
end
//reg [2:0] byte_received_r;
//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
always @(posedge clk) begin
if(SSEL_inactive)
byte_cnt_r <= 16'h0000;
else if(byte_received_sync)
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
reg [7:0] byte_data_sent;
assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
reg cmd_ready_r;
reg param_ready_r;
reg cmd_ready_r2;
reg param_ready_r2;
assign cmd_ready = cmd_ready_r;
assign param_ready = param_ready_r;
assign cmd_data = cmd_data_r;
assign param_data = param_data_r;
assign byte_cnt = byte_cnt_r;
always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:16:09 07/10/2009
// Design Name:
// Module Name: spi
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
reg [2:0] SSELr;
reg [2:0] SSELSCKr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
wire SSEL_inactive = SSELr[1];
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
assign endmessage = SSEL_endmessage;
assign startmessage = SSEL_startmessage;
// bit count for one SPI byte + byte count for the message
reg [2:0] bitcnt;
initial bitcnt = 3'b000;
wire bitcnt_msb = bitcnt[2];
reg [2:0] bitcnt_wrap_r;
always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
reg [31:0] byte_cnt_r;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
assign bit_cnt = bitcnt;
always @(posedge SCK) begin
if(SSELSCKr[1]) bitcnt <= 3'b000;
else bitcnt <= bitcnt + 3'b001;
end
always @(posedge SCK) begin
if(~SSELSCKr[1])
byte_data_received <= {byte_data_received[6:0], MOSI};
if(~SSELSCKr[1] && bitcnt==3'b111)
byte_received <= 1'b1;
else byte_received <= 1'b0;
end
//reg [2:0] byte_received_r;
//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
always @(posedge clk) begin
if(SSEL_inactive)
byte_cnt_r <= 16'h0000;
else if(byte_received_sync)
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
reg [7:0] byte_data_sent;
assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
reg cmd_ready_r;
reg param_ready_r;
reg cmd_ready_r2;
reg param_ready_r2;
assign cmd_ready = cmd_ready_r;
assign param_ready = param_ready_r;
assign cmd_data = cmd_data_r;
assign param_data = param_data_r;
assign byte_cnt = byte_cnt_r;
always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule
|
// Model of FIFO in Altera
module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 16;
parameter depth = 1024;
parameter addr_bits = 10;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [width-1:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [width-1:0] q;
output rdfull;
output rdempty;
output reg [addr_bits-1:0] rdusedw;
output wrfull;
output wrempty;
output reg [addr_bits-1:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [addr_bits-1:0] rdptr;
reg [addr_bits-1:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule // fifo
|
// Model of FIFO in Altera
module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 16;
parameter depth = 1024;
parameter addr_bits = 10;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [width-1:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [width-1:0] q;
output rdfull;
output rdempty;
output reg [addr_bits-1:0] rdusedw;
output wrfull;
output wrempty;
output reg [addr_bits-1:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [addr_bits-1:0] rdptr;
reg [addr_bits-1:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule // fifo
|
// Bidirectional registers
module bidir_reg
( inout wire [15:0] tristate,
input wire [15:0] oe,
input wire [15:0] reg_val );
// This would be much cleaner if all the tools
// supported "for generate"........
assign tristate[0] = oe[0] ? reg_val[0] : 1'bz;
assign tristate[1] = oe[1] ? reg_val[1] : 1'bz;
assign tristate[2] = oe[2] ? reg_val[2] : 1'bz;
assign tristate[3] = oe[3] ? reg_val[3] : 1'bz;
assign tristate[4] = oe[4] ? reg_val[4] : 1'bz;
assign tristate[5] = oe[5] ? reg_val[5] : 1'bz;
assign tristate[6] = oe[6] ? reg_val[6] : 1'bz;
assign tristate[7] = oe[7] ? reg_val[7] : 1'bz;
assign tristate[8] = oe[8] ? reg_val[8] : 1'bz;
assign tristate[9] = oe[9] ? reg_val[9] : 1'bz;
assign tristate[10] = oe[10] ? reg_val[10] : 1'bz;
assign tristate[11] = oe[11] ? reg_val[11] : 1'bz;
assign tristate[12] = oe[12] ? reg_val[12] : 1'bz;
assign tristate[13] = oe[13] ? reg_val[13] : 1'bz;
assign tristate[14] = oe[14] ? reg_val[14] : 1'bz;
assign tristate[15] = oe[15] ? reg_val[15] : 1'bz;
endmodule // bidir_reg
|
// Bidirectional registers
module bidir_reg
( inout wire [15:0] tristate,
input wire [15:0] oe,
input wire [15:0] reg_val );
// This would be much cleaner if all the tools
// supported "for generate"........
assign tristate[0] = oe[0] ? reg_val[0] : 1'bz;
assign tristate[1] = oe[1] ? reg_val[1] : 1'bz;
assign tristate[2] = oe[2] ? reg_val[2] : 1'bz;
assign tristate[3] = oe[3] ? reg_val[3] : 1'bz;
assign tristate[4] = oe[4] ? reg_val[4] : 1'bz;
assign tristate[5] = oe[5] ? reg_val[5] : 1'bz;
assign tristate[6] = oe[6] ? reg_val[6] : 1'bz;
assign tristate[7] = oe[7] ? reg_val[7] : 1'bz;
assign tristate[8] = oe[8] ? reg_val[8] : 1'bz;
assign tristate[9] = oe[9] ? reg_val[9] : 1'bz;
assign tristate[10] = oe[10] ? reg_val[10] : 1'bz;
assign tristate[11] = oe[11] ? reg_val[11] : 1'bz;
assign tristate[12] = oe[12] ? reg_val[12] : 1'bz;
assign tristate[13] = oe[13] ? reg_val[13] : 1'bz;
assign tristate[14] = oe[14] ? reg_val[14] : 1'bz;
assign tristate[15] = oe[15] ? reg_val[15] : 1'bz;
endmodule // bidir_reg
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: mylpm_addsub.v
// Megafunction Name(s):
// lpm_add_sub
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub lpm_add_sub_component (
.dataa (dataa),
.add_sub (add_sub),
.datab (datab),
.clock (clock),
.result (sub_wire0));
defparam
lpm_add_sub_component.lpm_width = 16,
lpm_add_sub_component.lpm_direction = "UNUSED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
lpm_add_sub_component.lpm_pipeline = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: Function NUMERIC "2"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: mylpm_addsub.v
// Megafunction Name(s):
// lpm_add_sub
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub lpm_add_sub_component (
.dataa (dataa),
.add_sub (add_sub),
.datab (datab),
.clock (clock),
.result (sub_wire0));
defparam
lpm_add_sub_component.lpm_width = 16,
lpm_add_sub_component.lpm_direction = "UNUSED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
lpm_add_sub_component.lpm_pipeline = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: Function NUMERIC "2"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: mylpm_addsub.v
// Megafunction Name(s):
// lpm_add_sub
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub lpm_add_sub_component (
.dataa (dataa),
.add_sub (add_sub),
.datab (datab),
.clock (clock),
.result (sub_wire0));
defparam
lpm_add_sub_component.lpm_width = 16,
lpm_add_sub_component.lpm_direction = "UNUSED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
lpm_add_sub_component.lpm_pipeline = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: Function NUMERIC "2"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
input clk_i;
input rst_i;
input ena_i;
input tx_empty_i;
input [11:0] tx_delay_i;
input [11:0] rx_delay_i;
output atr_tx_o;
reg [3:0] state;
reg [11:0] count;
`define ST_RX_DELAY 4'b0001
`define ST_RX 4'b0010
`define ST_TX_DELAY 4'b0100
`define ST_TX 4'b1000
always @(posedge clk_i)
if (rst_i | ~ena_i)
begin
state <= `ST_RX;
count <= 12'b0;
end
else
case (state)
`ST_RX:
if (!tx_empty_i)
begin
state <= `ST_TX_DELAY;
count <= tx_delay_i;
end
`ST_TX_DELAY:
if (count == 0)
state <= `ST_TX;
else
count <= count - 1;
`ST_TX:
if (tx_empty_i)
begin
state <= `ST_RX_DELAY;
count <= rx_delay_i;
end
`ST_RX_DELAY:
if (count == 0)
state <= `ST_RX;
else
count <= count - 1;
default: // Error
begin
state <= `ST_RX;
count <= 0;
end
endcase
assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
endmodule // atr_delay
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: dspclkpll.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dspclkpll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [5:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 15625,
altpll_component.clk0_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.pll_type = "AUTO",
altpll_component.clk1_multiply_by = 2,
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk1_time_delay = "0",
altpll_component.clk0_phase_shift = "0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_bb.v TRUE FALSE
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: dspclkpll.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dspclkpll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [5:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 15625,
altpll_component.clk0_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.pll_type = "AUTO",
altpll_component.clk1_multiply_by = 2,
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk1_time_delay = "0",
altpll_component.clk0_phase_shift = "0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_bb.v TRUE FALSE
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: dspclkpll.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dspclkpll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [5:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 15625,
altpll_component.clk0_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.pll_type = "AUTO",
altpll_component.clk1_multiply_by = 2,
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk1_time_delay = "0",
altpll_component.clk0_phase_shift = "0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_bb.v TRUE FALSE
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module strobe_gen
( input clock,
input reset,
input enable,
input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio
input strobe_in,
output wire strobe );
// parameter width = 8;
reg [7:0] counter;
assign strobe = ~|counter && enable && strobe_in;
always @(posedge clock)
if(reset | ~enable)
counter <= #1 8'd0;
else if(strobe_in)
if(counter == 0)
counter <= #1 rate;
else
counter <= #1 counter - 8'd1;
endmodule // strobe_gen
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module strobe_gen
( input clock,
input reset,
input enable,
input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio
input strobe_in,
output wire strobe );
// parameter width = 8;
reg [7:0] counter;
assign strobe = ~|counter && enable && strobe_in;
always @(posedge clock)
if(reset | ~enable)
counter <= #1 8'd0;
else if(strobe_in)
if(counter == 0)
counter <= #1 rate;
else
counter <= #1 counter - 8'd1;
endmodule // strobe_gen
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo );
parameter bitwidth = 16;
parameter zwidth = 16;
input clock;
input reset;
input enable;
input [bitwidth-1:0] xi, yi;
output [bitwidth-1:0] xo, yo;
input [zwidth-1:0] zi;
output [zwidth-1:0] zo;
reg [bitwidth+1:0] x0,y0;
reg [zwidth-2:0] z0;
wire [bitwidth+1:0] x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12;
wire [bitwidth+1:0] y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12;
wire [zwidth-2:0] z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12;
wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
// Compute consts. Would be easier if vlog had atan...
// see gen_cordic_consts.py
`define c00 16'd8192
`define c01 16'd4836
`define c02 16'd2555
`define c03 16'd1297
`define c04 16'd651
`define c05 16'd326
`define c06 16'd163
`define c07 16'd81
`define c08 16'd41
`define c09 16'd20
`define c10 16'd10
`define c11 16'd5
`define c12 16'd3
`define c13 16'd1
`define c14 16'd1
`define c15 16'd0
`define c16 16'd0
always @(posedge clock)
if(reset)
begin
x0 <= #1 0; y0 <= #1 0; z0 <= #1 0;
end
else if(enable)
begin
z0 <= #1 zi[zwidth-2:0];
case (zi[zwidth-1:zwidth-2])
2'b00, 2'b11 :
begin
x0 <= #1 xi_ext;
y0 <= #1 yi_ext;
end
2'b01, 2'b10 :
begin
x0 <= #1 -xi_ext;
y0 <= #1 -yi_ext;
end
endcase // case(zi[zwidth-1:zwidth-2])
end // else: !if(reset)
// FIXME need to handle variable number of stages
// FIXME should be able to narrow zwidth but quartus makes it bigger...
// This would be easier if arrays worked better in vlog...
cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,`c00,x1,y1,z1);
cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,`c01,x2,y2,z2);
cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,`c02,x3,y3,z3);
cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,`c03,x4,y4,z4);
cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,`c04,x5,y5,z5);
cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,`c05,x6,y6,z6);
cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,`c06,x7,y7,z7);
cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,`c07,x8,y8,z8);
cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,`c08,x9,y9,z9);
cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,`c09,x10,y10,z10);
cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,`c10,x11,y11,z11);
cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,`c11,x12,y12,z12);
assign xo = x12[bitwidth:1];
assign yo = y12[bitwidth:1];
//assign xo = x12[bitwidth+1:2]; // CORDIC gain is ~1.6, plus gain from rotating vectors
//assign yo = y12[bitwidth+1:2];
assign zo = z12;
endmodule // cordic
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo );
parameter bitwidth = 16;
parameter zwidth = 16;
input clock;
input reset;
input enable;
input [bitwidth-1:0] xi, yi;
output [bitwidth-1:0] xo, yo;
input [zwidth-1:0] zi;
output [zwidth-1:0] zo;
reg [bitwidth+1:0] x0,y0;
reg [zwidth-2:0] z0;
wire [bitwidth+1:0] x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12;
wire [bitwidth+1:0] y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12;
wire [zwidth-2:0] z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12;
wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
// Compute consts. Would be easier if vlog had atan...
// see gen_cordic_consts.py
`define c00 16'd8192
`define c01 16'd4836
`define c02 16'd2555
`define c03 16'd1297
`define c04 16'd651
`define c05 16'd326
`define c06 16'd163
`define c07 16'd81
`define c08 16'd41
`define c09 16'd20
`define c10 16'd10
`define c11 16'd5
`define c12 16'd3
`define c13 16'd1
`define c14 16'd1
`define c15 16'd0
`define c16 16'd0
always @(posedge clock)
if(reset)
begin
x0 <= #1 0; y0 <= #1 0; z0 <= #1 0;
end
else if(enable)
begin
z0 <= #1 zi[zwidth-2:0];
case (zi[zwidth-1:zwidth-2])
2'b00, 2'b11 :
begin
x0 <= #1 xi_ext;
y0 <= #1 yi_ext;
end
2'b01, 2'b10 :
begin
x0 <= #1 -xi_ext;
y0 <= #1 -yi_ext;
end
endcase // case(zi[zwidth-1:zwidth-2])
end // else: !if(reset)
// FIXME need to handle variable number of stages
// FIXME should be able to narrow zwidth but quartus makes it bigger...
// This would be easier if arrays worked better in vlog...
cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,`c00,x1,y1,z1);
cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,`c01,x2,y2,z2);
cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,`c02,x3,y3,z3);
cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,`c03,x4,y4,z4);
cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,`c04,x5,y5,z5);
cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,`c05,x6,y6,z6);
cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,`c06,x7,y7,z7);
cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,`c07,x8,y8,z8);
cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,`c08,x9,y9,z9);
cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,`c09,x10,y10,z10);
cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,`c10,x11,y11,z11);
cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,`c11,x12,y12,z12);
assign xo = x12[bitwidth:1];
assign yo = y12[bitwidth:1];
//assign xo = x12[bitwidth+1:2]; // CORDIC gain is ~1.6, plus gain from rotating vectors
//assign yo = y12[bitwidth+1:2];
assign zo = z12;
endmodule // cordic
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo );
parameter bitwidth = 16;
parameter zwidth = 16;
input clock;
input reset;
input enable;
input [bitwidth-1:0] xi, yi;
output [bitwidth-1:0] xo, yo;
input [zwidth-1:0] zi;
output [zwidth-1:0] zo;
reg [bitwidth+1:0] x0,y0;
reg [zwidth-2:0] z0;
wire [bitwidth+1:0] x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12;
wire [bitwidth+1:0] y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12;
wire [zwidth-2:0] z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12;
wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
// Compute consts. Would be easier if vlog had atan...
// see gen_cordic_consts.py
`define c00 16'd8192
`define c01 16'd4836
`define c02 16'd2555
`define c03 16'd1297
`define c04 16'd651
`define c05 16'd326
`define c06 16'd163
`define c07 16'd81
`define c08 16'd41
`define c09 16'd20
`define c10 16'd10
`define c11 16'd5
`define c12 16'd3
`define c13 16'd1
`define c14 16'd1
`define c15 16'd0
`define c16 16'd0
always @(posedge clock)
if(reset)
begin
x0 <= #1 0; y0 <= #1 0; z0 <= #1 0;
end
else if(enable)
begin
z0 <= #1 zi[zwidth-2:0];
case (zi[zwidth-1:zwidth-2])
2'b00, 2'b11 :
begin
x0 <= #1 xi_ext;
y0 <= #1 yi_ext;
end
2'b01, 2'b10 :
begin
x0 <= #1 -xi_ext;
y0 <= #1 -yi_ext;
end
endcase // case(zi[zwidth-1:zwidth-2])
end // else: !if(reset)
// FIXME need to handle variable number of stages
// FIXME should be able to narrow zwidth but quartus makes it bigger...
// This would be easier if arrays worked better in vlog...
cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,`c00,x1,y1,z1);
cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,`c01,x2,y2,z2);
cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,`c02,x3,y3,z3);
cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,`c03,x4,y4,z4);
cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,`c04,x5,y5,z5);
cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,`c05,x6,y6,z6);
cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,`c06,x7,y7,z7);
cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,`c07,x8,y8,z8);
cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,`c08,x9,y9,z9);
cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,`c09,x10,y10,z10);
cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,`c10,x11,y11,z11);
cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,`c11,x12,y12,z12);
assign xo = x12[bitwidth:1];
assign yo = y12[bitwidth:1];
//assign xo = x12[bitwidth+1:2]; // CORDIC gain is ~1.6, plus gain from rotating vectors
//assign yo = y12[bitwidth+1:2];
assign zo = z12;
endmodule // cordic
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_mux.v
//
// Description:
// Contains MI-side write command queue.
// SI-slot index selected by AW arbiter is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input from SI-slot selected by queue output is transferred to MI-side output .
//--------------------------------------------------------------------------
//
// Structure:
// wdata_mux
// axic_reg_srl_fifo
// mux_enc
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_wdata_mux #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload.
parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0] S_WMESG,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WLAST,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG,
output wire M_WLAST,
output wire M_WVALID,
input wire M_WREADY,
// Write Command Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // SI-slot index from AW arbiter
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_SLAVE_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
wire m_valid_i;
wire m_last_i;
wire [C_NUM_SLAVE_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
generate
if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux
// SI-side write command queue
axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (0)
)
wmux_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// Instantiate MUX
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (C_SELECT_WIDTH),
.C_DATA_WIDTH (C_WMESG_WIDTH)
) mux_w
(
.S (m_select_enc),
.A (S_WMESG),
.O (M_WMESG),
.OE (1'b1)
);
assign m_last_i = |(S_WLAST & m_select_hot);
assign m_valid_i = |(S_WVALID & m_select_hot);
assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY;
assign M_WLAST = m_last_i;
assign M_WVALID = m_valid_i & m_avalid;
assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}};
end else begin : gen_no_wmux
assign S_AREADY = 1'b1;
assign M_WVALID = S_WVALID;
assign S_WREADY = M_WREADY;
assign M_WLAST = S_WLAST;
assign M_WMESG = S_WMESG;
end
endgenerate
endmodule
`default_nettype wire
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Serial Control Bus from Cypress chip
module serial_io
( input master_clk,
input serial_clock,
input serial_data_in,
input enable,
input reset,
inout wire serial_data_out,
output reg [6:0] serial_addr,
output reg [31:0] serial_data,
output wire serial_strobe,
input wire [31:0] readback_0,
input wire [31:0] readback_1,
input wire [31:0] readback_2,
input wire [31:0] readback_3,
input wire [31:0] readback_4,
input wire [31:0] readback_5,
input wire [31:0] readback_6,
input wire [31:0] readback_7
);
reg is_read;
reg [7:0] ser_ctr;
reg write_done;
assign serial_data_out = is_read ? serial_data[31] : 1'bz;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
ser_ctr <= #1 8'd0;
else if(~enable)
ser_ctr <= #1 8'd0;
else if(ser_ctr == 39)
ser_ctr <= #1 8'd0;
else
ser_ctr <= #1 ser_ctr + 8'd1;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
is_read <= #1 1'b0;
else if(~enable)
is_read <= #1 1'b0;
else if((ser_ctr == 7)&&(serial_addr[6]==1))
is_read <= #1 1'b1;
always @(posedge serial_clock, posedge reset)
if(reset)
begin
serial_addr <= #1 7'b0;
serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else if(~enable)
begin
//serial_addr <= #1 7'b0;
//serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else
begin
if(~is_read && (ser_ctr == 39))
write_done <= #1 1'b1;
else
write_done <= #1 1'b0;
if(is_read & (ser_ctr==8))
case (serial_addr)
7'd1: serial_data <= #1 readback_0;
7'd2: serial_data <= #1 readback_1;
7'd3: serial_data <= #1 readback_2;
7'd4: serial_data <= #1 readback_3;
7'd5: serial_data <= #1 readback_4;
7'd6: serial_data <= #1 readback_5;
7'd7: serial_data <= #1 readback_6;
7'd8: serial_data <= #1 readback_7;
default: serial_data <= #1 32'd0;
endcase // case(serial_addr)
else if(ser_ctr >= 8)
serial_data <= #1 {serial_data[30:0],serial_data_in};
else if(ser_ctr < 8)
serial_addr <= #1 {serial_addr[5:0],serial_data_in};
end // else: !if(~enable)
reg enable_d1, enable_d2;
always @(posedge master_clk)
begin
enable_d1 <= #1 enable;
enable_d2 <= #1 enable_d1;
end
assign serial_strobe = enable_d2 & ~enable_d1;
endmodule // serial_io
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Serial Control Bus from Cypress chip
module serial_io
( input master_clk,
input serial_clock,
input serial_data_in,
input enable,
input reset,
inout wire serial_data_out,
output reg [6:0] serial_addr,
output reg [31:0] serial_data,
output wire serial_strobe,
input wire [31:0] readback_0,
input wire [31:0] readback_1,
input wire [31:0] readback_2,
input wire [31:0] readback_3,
input wire [31:0] readback_4,
input wire [31:0] readback_5,
input wire [31:0] readback_6,
input wire [31:0] readback_7
);
reg is_read;
reg [7:0] ser_ctr;
reg write_done;
assign serial_data_out = is_read ? serial_data[31] : 1'bz;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
ser_ctr <= #1 8'd0;
else if(~enable)
ser_ctr <= #1 8'd0;
else if(ser_ctr == 39)
ser_ctr <= #1 8'd0;
else
ser_ctr <= #1 ser_ctr + 8'd1;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
is_read <= #1 1'b0;
else if(~enable)
is_read <= #1 1'b0;
else if((ser_ctr == 7)&&(serial_addr[6]==1))
is_read <= #1 1'b1;
always @(posedge serial_clock, posedge reset)
if(reset)
begin
serial_addr <= #1 7'b0;
serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else if(~enable)
begin
//serial_addr <= #1 7'b0;
//serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else
begin
if(~is_read && (ser_ctr == 39))
write_done <= #1 1'b1;
else
write_done <= #1 1'b0;
if(is_read & (ser_ctr==8))
case (serial_addr)
7'd1: serial_data <= #1 readback_0;
7'd2: serial_data <= #1 readback_1;
7'd3: serial_data <= #1 readback_2;
7'd4: serial_data <= #1 readback_3;
7'd5: serial_data <= #1 readback_4;
7'd6: serial_data <= #1 readback_5;
7'd7: serial_data <= #1 readback_6;
7'd8: serial_data <= #1 readback_7;
default: serial_data <= #1 32'd0;
endcase // case(serial_addr)
else if(ser_ctr >= 8)
serial_data <= #1 {serial_data[30:0],serial_data_in};
else if(ser_ctr < 8)
serial_addr <= #1 {serial_addr[5:0],serial_data_in};
end // else: !if(~enable)
reg enable_d1, enable_d2;
always @(posedge master_clk)
begin
enable_d1 <= #1 enable;
enable_d2 <= #1 enable_d1;
end
assign serial_strobe = enable_d2 & ~enable_d1;
endmodule // serial_io
|
// -- (c) Copyright 2011-2014 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: axi_crossbar.v
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_axi_crossbar # (
parameter C_FAMILY = "rtl",
// FPGA Base Family. Current version: virtex6 or spartan6.
parameter integer C_NUM_SLAVE_SLOTS = 1,
// Number of Slave Interface (SI) slots for connecting
// to master IP. Range: 1-16.
parameter integer C_NUM_MASTER_SLOTS = 2,
// Number of Master Interface (MI) slots for connecting
// to slave IP. Range: 1-16.
parameter integer C_AXI_ID_WIDTH = 1,
// Width of ID signals propagated by the Interconnect.
// Width of ID signals produced on all MI slots.
// Range: 1-32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and
// m_axi_araddr for all SI/MI slots.
// Range: 1-64.
parameter integer C_AXI_DATA_WIDTH = 32,
// Data width of the internal interconnect write and read
// data paths.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_PROTOCOL = 0,
// 0 = "AXI4",
// 1 = "AXI3",
// 2 = "AXI4LITE"
// Propagate WID only when C_AXI_PROTOCOL = 1.
parameter integer C_NUM_ADDR_RANGES = 1,
// Number of BASE/HIGH_ADDR pairs per MI slot.
// Range: 1-16.
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = 128'h00000000001000000000000000000000,
// Base address of each range of each MI slot.
// For unused ranges, set C_M_AXI_BASE_ADDR[mm*aa*64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1'b1}}.
// (Bit positions above C_AXI_ADDR_WIDTH are ignored.)
// Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}.
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*32-1:0] C_M_AXI_ADDR_WIDTH = 64'H0000000c0000000c,
// Number of low-order address bits that are used to select locations within each address range of each MI slot.
// The High address of each range is derived as BASE_ADDR + 2**C_M_AXI_ADDR_WIDTH -1.
// For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0.
// For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000.
// Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}.
// Range: 0 - C_AXI_ADDR_WIDTH.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_BASE_ID = 32'h00000000,
// Base ID of each SI slot.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0 to 2**C_AXI_ID_WIDTH-1.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000,
// Number of low-order ID bits a connected master may vary to select a transaction thread.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0 - C_AXI_ID_WIDTH.
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of BUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,
// Multi-pathway write connectivity from each SI slot (N) to each
// MI slot (M):
// 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,
// Multi-pathway read connectivity from each SI slot (N) to each
// MI slot (M):
// 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
parameter integer C_R_REGISTER = 0,
// Insert register slice on R channel in the crossbar. (Valid only for SASD)
// Range: Reg-slice type (0-8).
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = 32'h00000000,
// 0 = Implement separate command queues per ID thread.
// 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0, 1
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = 32'H00000002,
// Maximum number of active write transactions that each SI
// slot can accept. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = 32'H00000002,
// Maximum number of active read transactions that each SI
// slot can accept. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = 64'H0000000400000004,
// Maximum number of data-active write transactions that
// each MI slot can generate at any one time. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = 64'H0000000400000004,
// Maximum number of active read transactions that
// each MI slot can generate at any one time. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = 32'h00000000,
// Arbitration priority among each SI slot.
// Higher values indicate higher priority.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0-15.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = 32'h00000000,
// Indicates whether each MI slot connects to a secure slave
// (allows only TrustZone secure access).
// Format: C_NUM_MASTER_SLOTS{Bit32}.
// Range: 0, 1
parameter integer C_CONNECTIVITY_MODE = 1
// 0 = Shared-Address Shared-Data (SASD).
// 1 = Shared-Address Multi-Data (SAMD).
// Default 1 (on) for simulation; default 0 (off) for implementation.
)
(
// Global Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_awburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awprot,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awregion,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awqos,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wlast,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_bresp,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_arburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arprot,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arregion,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arqos,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_rresp,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rlast,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rready,
// Master Interface Write Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_awburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awqos,
output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awready,
// Master Interface Write Data Ports
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wlast,
output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wready,
// Master Interface Write Response Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_bresp,
input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bready,
// Master Interface Read Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_arburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arqos,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arready,
// Master Interface Read Data Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_rresp,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rlast,
input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rready
);
localparam [64:0] P_ONES = {65{1'b1}};
localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_BASE_ID = f_base_id(0);
localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_HIGH_ID = f_high_id(0);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam [2:0] P_AXILITE_SIZE = 3'b010;
localparam [1:0] P_INCR = 2'b01;
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0);
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0);
localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0);
localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0);
localparam integer C_DEBUG = 1;
localparam integer P_RANGE_CHECK = 1;
// 1 (non-zero) = Detect and issue DECERR on the following conditions:
// a. address range mismatch (no valid MI slot)
// b. Burst or >32-bit transfer to AxiLite slave
// c. TrustZone access violation
// d. R/W direction unsupported by target
// 0 = Pass all transactions (no DECERR):
// a. Omit DECERR detection and response logic
// b. Omit address decoder and propagate s_axi_a*REGION to m_axi_a*REGION
// when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1.
// c. Unpredictable target MI-slot if address mismatch and >1 MI-slot
// d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave
// Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0.
localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) || (C_NUM_MASTER_SLOTS > 1) || (C_NUM_ADDR_RANGES > 1)) ? 1 : 0; // Always 1
localparam [C_NUM_MASTER_SLOTS*32-1:0] P_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}};
// Transaction error detection (per MI-slot)
// 0 = None; 1 = AXI4Lite burst violation
// Format: C_NUM_MASTER_SLOTS{Bit32};
localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8;
localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1;
localparam P_FAMILY = ((C_FAMILY == "virtex7") || (C_FAMILY == "kintex7") || (C_FAMILY == "artix7") || (C_FAMILY == "zynq")) ? C_FAMILY : "rtl";
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Widths of all write issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_write_issue_width_vec
(input null_arg);
integer mi;
reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
begin
result = 0;
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi*32+:32]);
end
result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;
f_write_issue_width_vec = result;
end
endfunction
// Widths of all read issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_read_issue_width_vec
(input null_arg);
integer mi;
reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
begin
result = 0;
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi*32+:32]);
end
result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;
f_read_issue_width_vec = result;
end
endfunction
// Widths of all write acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [C_NUM_SLAVE_SLOTS*32-1:0] f_write_accept_width_vec
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si*32+:32]);
end
f_write_accept_width_vec = result;
end
endfunction
// Widths of all read acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [C_NUM_SLAVE_SLOTS*32-1:0] f_read_accept_width_vec
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si*32+:32]);
end
f_read_accept_width_vec = result;
end
endfunction
// Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format
function [C_NUM_SLAVE_SLOTS*64-1:0] f_base_id
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH];
end
f_base_id = result;
end
endfunction
// Construct P_S_HIGH_ID vector
function [C_NUM_SLAVE_SLOTS*64-1:0] f_high_id
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :
(C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
end
f_high_id = result;
end
endfunction
// Construct P_M_HIGH_ADDR vector
function [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] f_high_addr
(input null_arg);
integer ar;
reg [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] result;
begin
result = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}};
for (ar=0; ar<C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES; ar=ar+1) begin
result[ar*64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar*32+:32] == 0) ? 64'h00000000_00000000 :
({1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} :
(C_M_AXI_BASE_ADDR[ar*64+:C_AXI_ADDR_WIDTH] | ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:7]}));
end
f_high_addr = result;
end
endfunction
// Generate a mask of valid ID bits for a given SI slot.
function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask
(input integer si);
begin
f_thread_id_mask =
(C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :
({C_AXI_ID_WIDTH{1'b0}} | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
end
endfunction
// Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value
// only for end-point SI-slots
function [C_AXI_ID_WIDTH-1:0] f_extend_ID (
input [C_AXI_ID_WIDTH-1:0] s_id,
input integer si
);
begin
f_extend_ID =
(C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? s_id :
(C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | (s_id & ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})));
end
endfunction
// Bit vector of SI slots with at least one write connection.
function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write
(input null_arg);
integer mi;
reg [C_NUM_SLAVE_SLOTS-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS{1'b0}};
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result = result | C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
end
f_s_supports_write = result;
end
endfunction
// Bit vector of SI slots with at least one read connection.
function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read
(input null_arg);
integer mi;
reg [C_NUM_SLAVE_SLOTS-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS{1'b0}};
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result = result | C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
end
f_s_supports_read = result;
end
endfunction
// Bit vector of MI slots with at least one write connection.
function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write
(input null_arg);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_supports_write[mi] = (|C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
end
end
endfunction
// Bit vector of MI slots with at least one read connection.
function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read
(input null_arg);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_supports_read[mi] = (|C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
end
end
endfunction
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_awid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_awaddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_awlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awburst ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awlock ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awcache ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awprot ;
// wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awregion ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awqos ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] si_cb_awuser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_wid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_wdata ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] si_cb_wstrb ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wlast ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] si_cb_wuser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_bid ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_bresp ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] si_cb_buser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_arid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_araddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_arlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arburst ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arlock ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arcache ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arprot ;
// wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arregion ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arqos ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] si_cb_aruser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_rid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_rdata ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_rresp ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rlast ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] si_cb_ruser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_awid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_awaddr ;
wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_awlen ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awsize ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awburst ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awlock ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awcache ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awprot ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awregion ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awqos ;
wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] cb_mi_awuser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_wid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_wdata ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] cb_mi_wstrb ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wlast ;
wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] cb_mi_wuser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_bid ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_bresp ;
wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] cb_mi_buser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_arid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_araddr ;
wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_arlen ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arsize ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arburst ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arlock ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arcache ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arprot ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arregion ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arqos ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] cb_mi_aruser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_rid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_rdata ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_rresp ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rlast ;
wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] cb_mi_ruser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rready ;
genvar slot;
generate
for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff
assign si_cb_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign si_cb_awlen[slot*8+:8] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awlen[slot*P_LEN+:P_LEN] : 0 ;
assign si_cb_awsize[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize[slot*3+:3] : P_AXILITE_SIZE ;
assign si_cb_awburst[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst[slot*2+:2] : P_INCR ;
assign si_cb_awlock[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_awlock[slot*P_LOCK+:1]} : 0 ;
assign si_cb_awcache[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache[slot*4+:4] : 0 ;
assign si_cb_awprot[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awprot[slot*3+:3] : 0 ;
assign si_cb_awqos[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos[slot*4+:4] : 0 ;
// assign si_cb_awregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion[slot*4+:4] : 0 ;
assign si_cb_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ;
assign si_cb_awvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awvalid[slot*1+:1] : 0 ;
assign si_cb_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3) ) ? (s_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign si_cb_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
assign si_cb_wlast[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast[slot*1+:1] : 1'b1 ;
assign si_cb_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ;
assign si_cb_wvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wvalid[slot*1+:1] : 0 ;
assign si_cb_bready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_bready[slot*1+:1] : 0 ;
assign si_cb_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign si_cb_arlen[slot*8+:8] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arlen[slot*P_LEN+:P_LEN] : 0 ;
assign si_cb_arsize[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize[slot*3+:3] : P_AXILITE_SIZE ;
assign si_cb_arburst[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst[slot*2+:2] : P_INCR ;
assign si_cb_arlock[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_arlock[slot*P_LOCK+:1]} : 0 ;
assign si_cb_arcache[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache[slot*4+:4] : 0 ;
assign si_cb_arprot[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arprot[slot*3+:3] : 0 ;
assign si_cb_arqos[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos[slot*4+:4] : 0 ;
// assign si_cb_arregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion[slot*4+:4] : 0 ;
assign si_cb_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ;
assign si_cb_arvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arvalid[slot*1+:1] : 0 ;
assign si_cb_rready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_rready[slot*1+:1] : 0 ;
assign s_axi_awready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_awready[slot*1+:1] : 0 ;
assign s_axi_wready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_wready[slot*1+:1] : 0 ;
assign s_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign s_axi_bresp[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bresp[slot*2+:2] : 0 ;
assign s_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ;
assign s_axi_bvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bvalid[slot*1+:1] : 0 ;
assign s_axi_arready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_arready[slot*1+:1] : 0 ;
assign s_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign s_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign s_axi_rresp[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rresp[slot*2+:2] : 0 ;
assign s_axi_rlast[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cb_rlast[slot*1+:1] : 0 ;
assign s_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ;
assign s_axi_rvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rvalid[slot*1+:1] : 0 ;
end // gen_si_tieoff
for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff
assign m_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign m_axi_awlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_awlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot*8+:4] : 0 ;
assign m_axi_awsize[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awsize[slot*3+:3] : 0 ;
assign m_axi_awburst[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awburst[slot*2+:2] : 0 ;
assign m_axi_awlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awlock[slot*2+:1] : 0 ;
assign m_axi_awcache[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awcache[slot*4+:4] : 0 ;
assign m_axi_awprot[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awprot[slot*3+:3] : 0 ;
assign m_axi_awregion[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_awregion[slot*4+:4] : 0 ;
assign m_axi_awqos[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awqos[slot*4+:4] : 0 ;
assign m_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ;
assign m_axi_awvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awvalid[slot*1+:1] : 0 ;
assign m_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign m_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
assign m_axi_wlast[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wlast[slot*1+:1] : 0 ;
assign m_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ;
assign m_axi_wvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wvalid[slot*1+:1] : 0 ;
assign m_axi_bready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_bready[slot*1+:1] : 0 ;
assign m_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign m_axi_arlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_arlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot*8+:4] : 0 ;
assign m_axi_arsize[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arsize[slot*3+:3] : 0 ;
assign m_axi_arburst[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arburst[slot*2+:2] : 0 ;
assign m_axi_arlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arlock[slot*2+:1] : 0 ;
assign m_axi_arcache[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arcache[slot*4+:4] : 0 ;
assign m_axi_arprot[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arprot[slot*3+:3] : 0 ;
assign m_axi_arregion[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_arregion[slot*4+:4] : 0 ;
assign m_axi_arqos[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arqos[slot*4+:4] : 0 ;
assign m_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ;
assign m_axi_arvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arvalid[slot*1+:1] : 0 ;
assign m_axi_rready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_rready[slot*1+:1] : 0 ;
assign cb_mi_awready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_awready[slot*1+:1] : 0 ;
assign cb_mi_wready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_wready[slot*1+:1] : 0 ;
assign cb_mi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign cb_mi_bresp[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bresp[slot*2+:2] : 0 ;
assign cb_mi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ;
assign cb_mi_bvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bvalid[slot*1+:1] : 0 ;
assign cb_mi_arready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_arready[slot*1+:1] : 0 ;
assign cb_mi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign cb_mi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign cb_mi_rresp[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rresp[slot*2+:2] : 0 ;
assign cb_mi_rlast[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast[slot*1+:1] : 1'b1 ;
assign cb_mi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ;
assign cb_mi_rvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rvalid[slot*1+:1] : 0 ;
end // gen_mi_tieoff
if ((C_CONNECTIVITY_MODE==0) || (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd
axi_crossbar_v2_1_crossbar_sasd #
(
.C_FAMILY (P_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_M_AXI_HIGH_ADDR (f_high_addr(0)),
.C_S_AXI_BASE_ID (P_S_AXI_BASE_ID),
.C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE),
.C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ),
.C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE),
.C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ),
.C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_R_REGISTER (C_R_REGISTER),
.C_RANGE_CHECK (P_RANGE_CHECK),
.C_ADDR_DECODE (P_ADDR_DECODE),
.C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
crossbar_sasd_0
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (si_cb_awid ),
.S_AXI_AWADDR (si_cb_awaddr ),
.S_AXI_AWLEN (si_cb_awlen ),
.S_AXI_AWSIZE (si_cb_awsize ),
.S_AXI_AWBURST (si_cb_awburst ),
.S_AXI_AWLOCK (si_cb_awlock ),
.S_AXI_AWCACHE (si_cb_awcache ),
.S_AXI_AWPROT (si_cb_awprot ),
// .S_AXI_AWREGION (si_cb_awregion ),
.S_AXI_AWQOS (si_cb_awqos ),
.S_AXI_AWUSER (si_cb_awuser ),
.S_AXI_AWVALID (si_cb_awvalid ),
.S_AXI_AWREADY (si_cb_awready ),
.S_AXI_WID (si_cb_wid ),
.S_AXI_WDATA (si_cb_wdata ),
.S_AXI_WSTRB (si_cb_wstrb ),
.S_AXI_WLAST (si_cb_wlast ),
.S_AXI_WUSER (si_cb_wuser ),
.S_AXI_WVALID (si_cb_wvalid ),
.S_AXI_WREADY (si_cb_wready ),
.S_AXI_BID (si_cb_bid ),
.S_AXI_BRESP (si_cb_bresp ),
.S_AXI_BUSER (si_cb_buser ),
.S_AXI_BVALID (si_cb_bvalid ),
.S_AXI_BREADY (si_cb_bready ),
.S_AXI_ARID (si_cb_arid ),
.S_AXI_ARADDR (si_cb_araddr ),
.S_AXI_ARLEN (si_cb_arlen ),
.S_AXI_ARSIZE (si_cb_arsize ),
.S_AXI_ARBURST (si_cb_arburst ),
.S_AXI_ARLOCK (si_cb_arlock ),
.S_AXI_ARCACHE (si_cb_arcache ),
.S_AXI_ARPROT (si_cb_arprot ),
// .S_AXI_ARREGION (si_cb_arregion ),
.S_AXI_ARQOS (si_cb_arqos ),
.S_AXI_ARUSER (si_cb_aruser ),
.S_AXI_ARVALID (si_cb_arvalid ),
.S_AXI_ARREADY (si_cb_arready ),
.S_AXI_RID (si_cb_rid ),
.S_AXI_RDATA (si_cb_rdata ),
.S_AXI_RRESP (si_cb_rresp ),
.S_AXI_RLAST (si_cb_rlast ),
.S_AXI_RUSER (si_cb_ruser ),
.S_AXI_RVALID (si_cb_rvalid ),
.S_AXI_RREADY (si_cb_rready ),
.M_AXI_AWID (cb_mi_awid ),
.M_AXI_AWADDR (cb_mi_awaddr ),
.M_AXI_AWLEN (cb_mi_awlen ),
.M_AXI_AWSIZE (cb_mi_awsize ),
.M_AXI_AWBURST (cb_mi_awburst ),
.M_AXI_AWLOCK (cb_mi_awlock ),
.M_AXI_AWCACHE (cb_mi_awcache ),
.M_AXI_AWPROT (cb_mi_awprot ),
.M_AXI_AWREGION (cb_mi_awregion ),
.M_AXI_AWQOS (cb_mi_awqos ),
.M_AXI_AWUSER (cb_mi_awuser ),
.M_AXI_AWVALID (cb_mi_awvalid ),
.M_AXI_AWREADY (cb_mi_awready ),
.M_AXI_WID (cb_mi_wid ),
.M_AXI_WDATA (cb_mi_wdata ),
.M_AXI_WSTRB (cb_mi_wstrb ),
.M_AXI_WLAST (cb_mi_wlast ),
.M_AXI_WUSER (cb_mi_wuser ),
.M_AXI_WVALID (cb_mi_wvalid ),
.M_AXI_WREADY (cb_mi_wready ),
.M_AXI_BID (cb_mi_bid ),
.M_AXI_BRESP (cb_mi_bresp ),
.M_AXI_BUSER (cb_mi_buser ),
.M_AXI_BVALID (cb_mi_bvalid ),
.M_AXI_BREADY (cb_mi_bready ),
.M_AXI_ARID (cb_mi_arid ),
.M_AXI_ARADDR (cb_mi_araddr ),
.M_AXI_ARLEN (cb_mi_arlen ),
.M_AXI_ARSIZE (cb_mi_arsize ),
.M_AXI_ARBURST (cb_mi_arburst ),
.M_AXI_ARLOCK (cb_mi_arlock ),
.M_AXI_ARCACHE (cb_mi_arcache ),
.M_AXI_ARPROT (cb_mi_arprot ),
.M_AXI_ARREGION (cb_mi_arregion ),
.M_AXI_ARQOS (cb_mi_arqos ),
.M_AXI_ARUSER (cb_mi_aruser ),
.M_AXI_ARVALID (cb_mi_arvalid ),
.M_AXI_ARREADY (cb_mi_arready ),
.M_AXI_RID (cb_mi_rid ),
.M_AXI_RDATA (cb_mi_rdata ),
.M_AXI_RRESP (cb_mi_rresp ),
.M_AXI_RLAST (cb_mi_rlast ),
.M_AXI_RUSER (cb_mi_ruser ),
.M_AXI_RVALID (cb_mi_rvalid ),
.M_AXI_RREADY (cb_mi_rready )
);
end else begin : gen_samd
axi_crossbar_v2_1_crossbar #
(
.C_FAMILY (P_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_S_AXI_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_M_AXI_HIGH_ADDR (f_high_addr(0)),
.C_S_AXI_BASE_ID (P_S_AXI_BASE_ID),
.C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE),
.C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ),
.C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE),
.C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ),
.C_M_AXI_WRITE_CONNECTIVITY (C_M_AXI_WRITE_CONNECTIVITY),
.C_M_AXI_READ_CONNECTIVITY (C_M_AXI_READ_CONNECTIVITY),
.C_S_AXI_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD),
.C_S_AXI_WRITE_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE),
.C_S_AXI_READ_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE),
.C_M_AXI_WRITE_ISSUING (C_M_AXI_WRITE_ISSUING),
.C_M_AXI_READ_ISSUING (C_M_AXI_READ_ISSUING),
.C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_RANGE_CHECK (P_RANGE_CHECK),
.C_ADDR_DECODE (P_ADDR_DECODE),
.C_W_ISSUE_WIDTH (f_write_issue_width_vec(0) ),
.C_R_ISSUE_WIDTH (f_read_issue_width_vec(0) ),
.C_W_ACCEPT_WIDTH (f_write_accept_width_vec(0)),
.C_R_ACCEPT_WIDTH (f_read_accept_width_vec(0)),
.C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
crossbar_samd
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (si_cb_awid ),
.S_AXI_AWADDR (si_cb_awaddr ),
.S_AXI_AWLEN (si_cb_awlen ),
.S_AXI_AWSIZE (si_cb_awsize ),
.S_AXI_AWBURST (si_cb_awburst ),
.S_AXI_AWLOCK (si_cb_awlock ),
.S_AXI_AWCACHE (si_cb_awcache ),
.S_AXI_AWPROT (si_cb_awprot ),
// .S_AXI_AWREGION (si_cb_awregion ),
.S_AXI_AWQOS (si_cb_awqos ),
.S_AXI_AWUSER (si_cb_awuser ),
.S_AXI_AWVALID (si_cb_awvalid ),
.S_AXI_AWREADY (si_cb_awready ),
.S_AXI_WID (si_cb_wid ),
.S_AXI_WDATA (si_cb_wdata ),
.S_AXI_WSTRB (si_cb_wstrb ),
.S_AXI_WLAST (si_cb_wlast ),
.S_AXI_WUSER (si_cb_wuser ),
.S_AXI_WVALID (si_cb_wvalid ),
.S_AXI_WREADY (si_cb_wready ),
.S_AXI_BID (si_cb_bid ),
.S_AXI_BRESP (si_cb_bresp ),
.S_AXI_BUSER (si_cb_buser ),
.S_AXI_BVALID (si_cb_bvalid ),
.S_AXI_BREADY (si_cb_bready ),
.S_AXI_ARID (si_cb_arid ),
.S_AXI_ARADDR (si_cb_araddr ),
.S_AXI_ARLEN (si_cb_arlen ),
.S_AXI_ARSIZE (si_cb_arsize ),
.S_AXI_ARBURST (si_cb_arburst ),
.S_AXI_ARLOCK (si_cb_arlock ),
.S_AXI_ARCACHE (si_cb_arcache ),
.S_AXI_ARPROT (si_cb_arprot ),
// .S_AXI_ARREGION (si_cb_arregion ),
.S_AXI_ARQOS (si_cb_arqos ),
.S_AXI_ARUSER (si_cb_aruser ),
.S_AXI_ARVALID (si_cb_arvalid ),
.S_AXI_ARREADY (si_cb_arready ),
.S_AXI_RID (si_cb_rid ),
.S_AXI_RDATA (si_cb_rdata ),
.S_AXI_RRESP (si_cb_rresp ),
.S_AXI_RLAST (si_cb_rlast ),
.S_AXI_RUSER (si_cb_ruser ),
.S_AXI_RVALID (si_cb_rvalid ),
.S_AXI_RREADY (si_cb_rready ),
.M_AXI_AWID (cb_mi_awid ),
.M_AXI_AWADDR (cb_mi_awaddr ),
.M_AXI_AWLEN (cb_mi_awlen ),
.M_AXI_AWSIZE (cb_mi_awsize ),
.M_AXI_AWBURST (cb_mi_awburst ),
.M_AXI_AWLOCK (cb_mi_awlock ),
.M_AXI_AWCACHE (cb_mi_awcache ),
.M_AXI_AWPROT (cb_mi_awprot ),
.M_AXI_AWREGION (cb_mi_awregion ),
.M_AXI_AWQOS (cb_mi_awqos ),
.M_AXI_AWUSER (cb_mi_awuser ),
.M_AXI_AWVALID (cb_mi_awvalid ),
.M_AXI_AWREADY (cb_mi_awready ),
.M_AXI_WID (cb_mi_wid ),
.M_AXI_WDATA (cb_mi_wdata ),
.M_AXI_WSTRB (cb_mi_wstrb ),
.M_AXI_WLAST (cb_mi_wlast ),
.M_AXI_WUSER (cb_mi_wuser ),
.M_AXI_WVALID (cb_mi_wvalid ),
.M_AXI_WREADY (cb_mi_wready ),
.M_AXI_BID (cb_mi_bid ),
.M_AXI_BRESP (cb_mi_bresp ),
.M_AXI_BUSER (cb_mi_buser ),
.M_AXI_BVALID (cb_mi_bvalid ),
.M_AXI_BREADY (cb_mi_bready ),
.M_AXI_ARID (cb_mi_arid ),
.M_AXI_ARADDR (cb_mi_araddr ),
.M_AXI_ARLEN (cb_mi_arlen ),
.M_AXI_ARSIZE (cb_mi_arsize ),
.M_AXI_ARBURST (cb_mi_arburst ),
.M_AXI_ARLOCK (cb_mi_arlock ),
.M_AXI_ARCACHE (cb_mi_arcache ),
.M_AXI_ARPROT (cb_mi_arprot ),
.M_AXI_ARREGION (cb_mi_arregion ),
.M_AXI_ARQOS (cb_mi_arqos ),
.M_AXI_ARUSER (cb_mi_aruser ),
.M_AXI_ARVALID (cb_mi_arvalid ),
.M_AXI_ARREADY (cb_mi_arready ),
.M_AXI_RID (cb_mi_rid ),
.M_AXI_RDATA (cb_mi_rdata ),
.M_AXI_RRESP (cb_mi_rresp ),
.M_AXI_RLAST (cb_mi_rlast ),
.M_AXI_RUSER (cb_mi_ruser ),
.M_AXI_RVALID (cb_mi_rvalid ),
.M_AXI_RREADY (cb_mi_rready )
);
end // gen_samd
// end // gen_crossbar
endgenerate
endmodule
`default_nettype wire
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// NOTE This only works for N=4, max decim rate of 128
// NOTE signal "rate" is ONE LESS THAN the actual rate
module cic_dec_shifter(rate,signal_in,signal_out);
parameter bw = 16;
parameter maxbitgain = 28;
input [7:0] rate;
input wire [bw+maxbitgain-1:0] signal_in;
output reg [bw-1:0] signal_out;
function [4:0] bitgain;
input [7:0] rate;
case(rate)
// Exact Cases -- N*log2(rate)
8'd4 : bitgain = 8;
8'd8 : bitgain = 12;
8'd16 : bitgain = 16;
8'd32 : bitgain = 20;
8'd64 : bitgain = 24;
8'd128 : bitgain = 28;
// Nearest without overflow -- ceil(N*log2(rate))
8'd5 : bitgain = 10;
8'd6 : bitgain = 11;
8'd7 : bitgain = 12;
8'd9 : bitgain = 13;
8'd10,8'd11 : bitgain = 14;
8'd12,8'd13 : bitgain = 15;
8'd14,8'd15 : bitgain = 16;
8'd17,8'd18,8'd19 : bitgain = 17;
8'd20,8'd21,8'd22 : bitgain = 18;
8'd23,8'd24,8'd25,8'd26 : bitgain = 19;
8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20;
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21;
8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22;
8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23;
8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24;
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25;
8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26;
8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27;
default : bitgain = 28;
endcase // case(rate)
endfunction // bitgain
wire [4:0] shift = bitgain(rate+1);
// We should be able to do this, but can't ....
// assign signal_out = signal_in[shift+bw-1:shift];
always @*
case(shift)
5'd8 : signal_out = signal_in[8+bw-1:8];
5'd10 : signal_out = signal_in[10+bw-1:10];
5'd11 : signal_out = signal_in[11+bw-1:11];
5'd12 : signal_out = signal_in[12+bw-1:12];
5'd13 : signal_out = signal_in[13+bw-1:13];
5'd14 : signal_out = signal_in[14+bw-1:14];
5'd15 : signal_out = signal_in[15+bw-1:15];
5'd16 : signal_out = signal_in[16+bw-1:16];
5'd17 : signal_out = signal_in[17+bw-1:17];
5'd18 : signal_out = signal_in[18+bw-1:18];
5'd19 : signal_out = signal_in[19+bw-1:19];
5'd20 : signal_out = signal_in[20+bw-1:20];
5'd21 : signal_out = signal_in[21+bw-1:21];
5'd22 : signal_out = signal_in[22+bw-1:22];
5'd23 : signal_out = signal_in[23+bw-1:23];
5'd24 : signal_out = signal_in[24+bw-1:24];
5'd25 : signal_out = signal_in[25+bw-1:25];
5'd26 : signal_out = signal_in[26+bw-1:26];
5'd27 : signal_out = signal_in[27+bw-1:27];
5'd28 : signal_out = signal_in[28+bw-1:28];
default : signal_out = signal_in[28+bw-1:28];
endcase // case(shift)
endmodule // cic_dec_shifter
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// NOTE This only works for N=4, max decim rate of 128
// NOTE signal "rate" is ONE LESS THAN the actual rate
module cic_dec_shifter(rate,signal_in,signal_out);
parameter bw = 16;
parameter maxbitgain = 28;
input [7:0] rate;
input wire [bw+maxbitgain-1:0] signal_in;
output reg [bw-1:0] signal_out;
function [4:0] bitgain;
input [7:0] rate;
case(rate)
// Exact Cases -- N*log2(rate)
8'd4 : bitgain = 8;
8'd8 : bitgain = 12;
8'd16 : bitgain = 16;
8'd32 : bitgain = 20;
8'd64 : bitgain = 24;
8'd128 : bitgain = 28;
// Nearest without overflow -- ceil(N*log2(rate))
8'd5 : bitgain = 10;
8'd6 : bitgain = 11;
8'd7 : bitgain = 12;
8'd9 : bitgain = 13;
8'd10,8'd11 : bitgain = 14;
8'd12,8'd13 : bitgain = 15;
8'd14,8'd15 : bitgain = 16;
8'd17,8'd18,8'd19 : bitgain = 17;
8'd20,8'd21,8'd22 : bitgain = 18;
8'd23,8'd24,8'd25,8'd26 : bitgain = 19;
8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20;
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21;
8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22;
8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23;
8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24;
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25;
8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26;
8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27;
default : bitgain = 28;
endcase // case(rate)
endfunction // bitgain
wire [4:0] shift = bitgain(rate+1);
// We should be able to do this, but can't ....
// assign signal_out = signal_in[shift+bw-1:shift];
always @*
case(shift)
5'd8 : signal_out = signal_in[8+bw-1:8];
5'd10 : signal_out = signal_in[10+bw-1:10];
5'd11 : signal_out = signal_in[11+bw-1:11];
5'd12 : signal_out = signal_in[12+bw-1:12];
5'd13 : signal_out = signal_in[13+bw-1:13];
5'd14 : signal_out = signal_in[14+bw-1:14];
5'd15 : signal_out = signal_in[15+bw-1:15];
5'd16 : signal_out = signal_in[16+bw-1:16];
5'd17 : signal_out = signal_in[17+bw-1:17];
5'd18 : signal_out = signal_in[18+bw-1:18];
5'd19 : signal_out = signal_in[19+bw-1:19];
5'd20 : signal_out = signal_in[20+bw-1:20];
5'd21 : signal_out = signal_in[21+bw-1:21];
5'd22 : signal_out = signal_in[22+bw-1:22];
5'd23 : signal_out = signal_in[23+bw-1:23];
5'd24 : signal_out = signal_in[24+bw-1:24];
5'd25 : signal_out = signal_in[25+bw-1:25];
5'd26 : signal_out = signal_in[26+bw-1:26];
5'd27 : signal_out = signal_in[27+bw-1:27];
5'd28 : signal_out = signal_in[28+bw-1:28];
default : signal_out = signal_in[28+bw-1:28];
endcase // case(shift)
endmodule // cic_dec_shifter
|
module mac (input clock, input reset, input enable, input clear,
input signed [15:0] x, input signed [15:0] y,
input [7:0] shift, output [15:0] z );
reg signed [30:0] product;
reg signed [39:0] z_int;
reg signed [15:0] z_shift;
reg enable_d1;
always @(posedge clock)
enable_d1 <= #1 enable;
always @(posedge clock)
if(reset | clear)
z_int <= #1 40'd0;
else if(enable_d1)
z_int <= #1 z_int + {{9{product[30]}},product};
always @(posedge clock)
product <= #1 x*y;
always @* // FIXME full case? parallel case?
case(shift)
//8'd0 : z_shift <= z_int[39:24];
//8'd1 : z_shift <= z_int[38:23];
//8'd2 : z_shift <= z_int[37:22];
//8'd3 : z_shift <= z_int[36:21];
//8'd4 : z_shift <= z_int[35:20];
//8'd5 : z_shift <= z_int[34:19];
8'd6 : z_shift <= z_int[33:18];
8'd7 : z_shift <= z_int[32:17];
8'd8 : z_shift <= z_int[31:16];
8'd9 : z_shift <= z_int[30:15];
8'd10 : z_shift <= z_int[29:14];
8'd11 : z_shift <= z_int[28:13];
//8'd12 : z_shift <= z_int[27:12];
//8'd13 : z_shift <= z_int[26:11];
//8'd14 : z_shift <= z_int[25:10];
//8'd15 : z_shift <= z_int[24:9];
//8'd16 : z_shift <= z_int[23:8];
//8'd17 : z_shift <= z_int[22:7];
//8'd18 : z_shift <= z_int[21:6];
//8'd19 : z_shift <= z_int[20:5];
//8'd20 : z_shift <= z_int[19:4];
//8'd21 : z_shift <= z_int[18:3];
//8'd22 : z_shift <= z_int[17:2];
//8'd23 : z_shift <= z_int[16:1];
//8'd24 : z_shift <= z_int[15:0];
default : z_shift <= z_int[15:0];
endcase // case(shift)
// FIXME do we need to saturate?
//assign z = z_shift;
assign z = z_int[15:0];
endmodule // mac
|
module mac (input clock, input reset, input enable, input clear,
input signed [15:0] x, input signed [15:0] y,
input [7:0] shift, output [15:0] z );
reg signed [30:0] product;
reg signed [39:0] z_int;
reg signed [15:0] z_shift;
reg enable_d1;
always @(posedge clock)
enable_d1 <= #1 enable;
always @(posedge clock)
if(reset | clear)
z_int <= #1 40'd0;
else if(enable_d1)
z_int <= #1 z_int + {{9{product[30]}},product};
always @(posedge clock)
product <= #1 x*y;
always @* // FIXME full case? parallel case?
case(shift)
//8'd0 : z_shift <= z_int[39:24];
//8'd1 : z_shift <= z_int[38:23];
//8'd2 : z_shift <= z_int[37:22];
//8'd3 : z_shift <= z_int[36:21];
//8'd4 : z_shift <= z_int[35:20];
//8'd5 : z_shift <= z_int[34:19];
8'd6 : z_shift <= z_int[33:18];
8'd7 : z_shift <= z_int[32:17];
8'd8 : z_shift <= z_int[31:16];
8'd9 : z_shift <= z_int[30:15];
8'd10 : z_shift <= z_int[29:14];
8'd11 : z_shift <= z_int[28:13];
//8'd12 : z_shift <= z_int[27:12];
//8'd13 : z_shift <= z_int[26:11];
//8'd14 : z_shift <= z_int[25:10];
//8'd15 : z_shift <= z_int[24:9];
//8'd16 : z_shift <= z_int[23:8];
//8'd17 : z_shift <= z_int[22:7];
//8'd18 : z_shift <= z_int[21:6];
//8'd19 : z_shift <= z_int[20:5];
//8'd20 : z_shift <= z_int[19:4];
//8'd21 : z_shift <= z_int[18:3];
//8'd22 : z_shift <= z_int[17:2];
//8'd23 : z_shift <= z_int[16:1];
//8'd24 : z_shift <= z_int[15:0];
default : z_shift <= z_int[15:0];
endcase // case(shift)
// FIXME do we need to saturate?
//assign z = z_shift;
assign z = z_int[15:0];
endmodule // mac
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_doubler.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 156 11/29/2004 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clk_doubler (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.activeclock (),
.areset (),
.clkbad (),
.clkena (),
.clkloss (),
.clkswitch (),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena (),
.fbin (),
.locked (),
.pfdena (),
.pllena (),
.scanaclr (),
.scanclk (),
.scandata (),
.scandataout (),
.scandone (),
.scanread (),
.scanwrite (),
.sclkout0 (),
.sclkout1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 2,
altpll_component.inclk0_input_frequency = 15625,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_4k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_4k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module tx_chain_hb
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input hb_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debug, output [15:0] hb_i_out
);
assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
wire [15:0] bb_i, bb_q;
wire [15:0] hb_i_out, hb_q_out;
halfband_interp hb
(.clock(clock),.reset(reset),.enable(enable),
.strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
.signal_in_i(i_in),.signal_in_q(q_in),
.signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
.debug(debug[12:0]));
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_i_out),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_q_out),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule // tx_chain
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module tx_chain_hb
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input hb_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debug, output [15:0] hb_i_out
);
assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
wire [15:0] bb_i, bb_q;
wire [15:0] hb_i_out, hb_q_out;
halfband_interp hb
(.clock(clock),.reset(reset),.enable(enable),
.strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
.signal_in_i(i_in),.signal_in_q(q_in),
.signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
.debug(debug[12:0]));
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_i_out),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_q_out),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule // tx_chain
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module tx_chain_hb
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input hb_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debug, output [15:0] hb_i_out
);
assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
wire [15:0] bb_i, bb_q;
wire [15:0] hb_i_out, hb_q_out;
halfband_interp hb
(.clock(clock),.reset(reset),.enable(enable),
.strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
.signal_in_i(i_in),.signal_in_q(q_in),
.signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
.debug(debug[12:0]));
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_i_out),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_q_out),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule // tx_chain
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module tx_chain_hb
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input hb_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debug, output [15:0] hb_i_out
);
assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
wire [15:0] bb_i, bb_q;
wire [15:0] hb_i_out, hb_q_out;
halfband_interp hb
(.clock(clock),.reset(reset),.enable(enable),
.strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
.signal_in_i(i_in),.signal_in_q(q_in),
.signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
.debug(debug[12:0]));
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_i_out),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_q_out),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule // tx_chain
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
// megafunction wizard: %DDR3 SDRAM High Performance Controller v10.0%
//GENERATION: XML
//Generated by DDR3 SDRAM High Performance Controller 10.0
//IPFS_FILES:
//RELATED_FILES:
//<< MEGAWIZARD PARSE FILE DDR310.0
//.
//<< START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 12: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 3: 0] mem_dm;
inout [ 31: 0] mem_dq;
inout [ 3: 0] mem_dqs;
inout [ 3: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 15: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 12: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 3: 0] mem_dm;
wire [ 31: 0] mem_dq;
wire [ 3: 0] mem_dqs;
wire [ 3: 0] mem_dqsn;
wire [ 23: 0] mem_local_addr;
wire [ 15: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [127: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 5: 0] mem_local_size;
wire [127: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 15: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_wdata_req (),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[12 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[3 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[3 : 0]),
.mem_dqsn (mem_dqsn[3 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[23 : 21]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[20 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[15 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< START MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< END MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< start europa
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
// megafunction wizard: %DDR3 SDRAM High Performance Controller v10.0%
//GENERATION: XML
//Generated by DDR3 SDRAM High Performance Controller 10.0
//IPFS_FILES:
//RELATED_FILES:
//<< MEGAWIZARD PARSE FILE DDR310.0
//.
//<< START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 12: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 3: 0] mem_dm;
inout [ 31: 0] mem_dq;
inout [ 3: 0] mem_dqs;
inout [ 3: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 15: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 12: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 3: 0] mem_dm;
wire [ 31: 0] mem_dq;
wire [ 3: 0] mem_dqs;
wire [ 3: 0] mem_dqsn;
wire [ 23: 0] mem_local_addr;
wire [ 15: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [127: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 5: 0] mem_local_size;
wire [127: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 15: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_wdata_req (),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[12 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[3 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[3 : 0]),
.mem_dqsn (mem_dqsn[3 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[23 : 21]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[20 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[15 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< START MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< END MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< start europa
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
// megafunction wizard: %DDR3 SDRAM High Performance Controller v10.0%
//GENERATION: XML
//Generated by DDR3 SDRAM High Performance Controller 10.0
//IPFS_FILES:
//RELATED_FILES:
//<< MEGAWIZARD PARSE FILE DDR310.0
//.
//<< START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 12: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 3: 0] mem_dm;
inout [ 31: 0] mem_dq;
inout [ 3: 0] mem_dqs;
inout [ 3: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 15: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 12: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 3: 0] mem_dm;
wire [ 31: 0] mem_dq;
wire [ 3: 0] mem_dqs;
wire [ 3: 0] mem_dqsn;
wire [ 23: 0] mem_local_addr;
wire [ 15: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [127: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 5: 0] mem_local_size;
wire [127: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 15: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_wdata_req (),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[12 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[3 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[3 : 0]),
.mem_dqsn (mem_dqsn[3 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[23 : 21]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[20 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[15 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< START MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< END MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< start europa
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
reg [7:0] counter;
// FIXME maybe should use PLL or switch to double edge version
always @(posedge in_clk or posedge reset)
if(reset)
counter <= #1 8'd0;
else if(counter == 0)
counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
else
counter <= #1 counter-8'd1;
always @(posedge in_clk or posedge reset)
if(reset)
out_clk <= #1 1'b0;
else if(counter == 0)
out_clk <= #1 ~out_clk;
endmodule // clk_divider
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
reg [7:0] counter;
// FIXME maybe should use PLL or switch to double edge version
always @(posedge in_clk or posedge reset)
if(reset)
counter <= #1 8'd0;
else if(counter == 0)
counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
else
counter <= #1 counter-8'd1;
always @(posedge in_clk or posedge reset)
if(reset)
out_clk <= #1 1'b0;
else if(counter == 0)
out_clk <= #1 ~out_clk;
endmodule // clk_divider
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
reg [7:0] counter;
// FIXME maybe should use PLL or switch to double edge version
always @(posedge in_clk or posedge reset)
if(reset)
counter <= #1 8'd0;
else if(counter == 0)
counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
else
counter <= #1 counter-8'd1;
always @(posedge in_clk or posedge reset)
if(reset)
out_clk <= #1 1'b0;
else if(counter == 0)
out_clk <= #1 ~out_clk;
endmodule // clk_divider
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cic_decim
( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
parameter bw = 16;
parameter N = 4;
parameter log2_of_max_rate = 7;
parameter maxbitgain = N * log2_of_max_rate;
input clock;
input reset;
input enable;
input [7:0] rate;
input strobe_in,strobe_out;
input [bw-1:0] signal_in;
output [bw-1:0] signal_out;
reg [bw-1:0] signal_out;
wire [bw-1:0] signal_out_unreg;
wire [bw+maxbitgain-1:0] signal_in_ext;
reg [bw+maxbitgain-1:0] integrator [0:N-1];
reg [bw+maxbitgain-1:0] differentiator [0:N-1];
reg [bw+maxbitgain-1:0] pipeline [0:N-1];
reg [bw+maxbitgain-1:0] sampler;
integer i;
sign_extend #(bw,bw+maxbitgain)
ext_input (.in(signal_in),.out(signal_in_ext));
always @(posedge clock)
if(reset)
for(i=0;i<N;i=i+1)
integrator[i] <= #1 0;
else if (enable && strobe_in)
begin
integrator[0] <= #1 integrator[0] + signal_in_ext;
for(i=1;i<N;i=i+1)
integrator[i] <= #1 integrator[i] + integrator[i-1];
end
always @(posedge clock)
if(reset)
begin
sampler <= #1 0;
for(i=0;i<N;i=i+1)
begin
pipeline[i] <= #1 0;
differentiator[i] <= #1 0;
end
end
else if (enable && strobe_out)
begin
sampler <= #1 integrator[N-1];
differentiator[0] <= #1 sampler;
pipeline[0] <= #1 sampler - differentiator[0];
for(i=1;i<N;i=i+1)
begin
differentiator[i] <= #1 pipeline[i-1];
pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
end
end // if (enable && strobe_out)
wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
cic_dec_shifter #(bw)
cic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg);
always @(posedge clock)
signal_out <= #1 signal_out_unreg;
endmodule // cic_decim
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cic_decim
( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
parameter bw = 16;
parameter N = 4;
parameter log2_of_max_rate = 7;
parameter maxbitgain = N * log2_of_max_rate;
input clock;
input reset;
input enable;
input [7:0] rate;
input strobe_in,strobe_out;
input [bw-1:0] signal_in;
output [bw-1:0] signal_out;
reg [bw-1:0] signal_out;
wire [bw-1:0] signal_out_unreg;
wire [bw+maxbitgain-1:0] signal_in_ext;
reg [bw+maxbitgain-1:0] integrator [0:N-1];
reg [bw+maxbitgain-1:0] differentiator [0:N-1];
reg [bw+maxbitgain-1:0] pipeline [0:N-1];
reg [bw+maxbitgain-1:0] sampler;
integer i;
sign_extend #(bw,bw+maxbitgain)
ext_input (.in(signal_in),.out(signal_in_ext));
always @(posedge clock)
if(reset)
for(i=0;i<N;i=i+1)
integrator[i] <= #1 0;
else if (enable && strobe_in)
begin
integrator[0] <= #1 integrator[0] + signal_in_ext;
for(i=1;i<N;i=i+1)
integrator[i] <= #1 integrator[i] + integrator[i-1];
end
always @(posedge clock)
if(reset)
begin
sampler <= #1 0;
for(i=0;i<N;i=i+1)
begin
pipeline[i] <= #1 0;
differentiator[i] <= #1 0;
end
end
else if (enable && strobe_out)
begin
sampler <= #1 integrator[N-1];
differentiator[0] <= #1 sampler;
pipeline[0] <= #1 sampler - differentiator[0];
for(i=1;i<N;i=i+1)
begin
differentiator[i] <= #1 pipeline[i-1];
pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
end
end // if (enable && strobe_out)
wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
cic_dec_shifter #(bw)
cic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg);
always @(posedge clock)
signal_out <= #1 signal_out_unreg;
endmodule // cic_decim
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cic_decim
( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
parameter bw = 16;
parameter N = 4;
parameter log2_of_max_rate = 7;
parameter maxbitgain = N * log2_of_max_rate;
input clock;
input reset;
input enable;
input [7:0] rate;
input strobe_in,strobe_out;
input [bw-1:0] signal_in;
output [bw-1:0] signal_out;
reg [bw-1:0] signal_out;
wire [bw-1:0] signal_out_unreg;
wire [bw+maxbitgain-1:0] signal_in_ext;
reg [bw+maxbitgain-1:0] integrator [0:N-1];
reg [bw+maxbitgain-1:0] differentiator [0:N-1];
reg [bw+maxbitgain-1:0] pipeline [0:N-1];
reg [bw+maxbitgain-1:0] sampler;
integer i;
sign_extend #(bw,bw+maxbitgain)
ext_input (.in(signal_in),.out(signal_in_ext));
always @(posedge clock)
if(reset)
for(i=0;i<N;i=i+1)
integrator[i] <= #1 0;
else if (enable && strobe_in)
begin
integrator[0] <= #1 integrator[0] + signal_in_ext;
for(i=1;i<N;i=i+1)
integrator[i] <= #1 integrator[i] + integrator[i-1];
end
always @(posedge clock)
if(reset)
begin
sampler <= #1 0;
for(i=0;i<N;i=i+1)
begin
pipeline[i] <= #1 0;
differentiator[i] <= #1 0;
end
end
else if (enable && strobe_out)
begin
sampler <= #1 integrator[N-1];
differentiator[0] <= #1 sampler;
pipeline[0] <= #1 sampler - differentiator[0];
for(i=1;i<N;i=i+1)
begin
differentiator[i] <= #1 pipeline[i-1];
pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
end
end // if (enable && strobe_out)
wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
cic_dec_shifter #(bw)
cic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg);
always @(posedge clock)
signal_out <= #1 signal_out_unreg;
endmodule // cic_decim
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cic_decim
( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
parameter bw = 16;
parameter N = 4;
parameter log2_of_max_rate = 7;
parameter maxbitgain = N * log2_of_max_rate;
input clock;
input reset;
input enable;
input [7:0] rate;
input strobe_in,strobe_out;
input [bw-1:0] signal_in;
output [bw-1:0] signal_out;
reg [bw-1:0] signal_out;
wire [bw-1:0] signal_out_unreg;
wire [bw+maxbitgain-1:0] signal_in_ext;
reg [bw+maxbitgain-1:0] integrator [0:N-1];
reg [bw+maxbitgain-1:0] differentiator [0:N-1];
reg [bw+maxbitgain-1:0] pipeline [0:N-1];
reg [bw+maxbitgain-1:0] sampler;
integer i;
sign_extend #(bw,bw+maxbitgain)
ext_input (.in(signal_in),.out(signal_in_ext));
always @(posedge clock)
if(reset)
for(i=0;i<N;i=i+1)
integrator[i] <= #1 0;
else if (enable && strobe_in)
begin
integrator[0] <= #1 integrator[0] + signal_in_ext;
for(i=1;i<N;i=i+1)
integrator[i] <= #1 integrator[i] + integrator[i-1];
end
always @(posedge clock)
if(reset)
begin
sampler <= #1 0;
for(i=0;i<N;i=i+1)
begin
pipeline[i] <= #1 0;
differentiator[i] <= #1 0;
end
end
else if (enable && strobe_out)
begin
sampler <= #1 integrator[N-1];
differentiator[0] <= #1 sampler;
pipeline[0] <= #1 sampler - differentiator[0];
for(i=1;i<N;i=i+1)
begin
differentiator[i] <= #1 pipeline[i-1];
pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
end
end // if (enable && strobe_out)
wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
cic_dec_shifter #(bw)
cic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg);
always @(posedge clock)
signal_out <= #1 signal_out_unreg;
endmodule // cic_decim
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_doubler.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 156 11/29/2004 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module clk_doubler (
inclk0,
c0);
input inclk0;
output c0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_doubler.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 156 11/29/2004 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module clk_doubler (
inclk0,
c0);
input inclk0;
output c0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_doubler.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 156 11/29/2004 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module clk_doubler (
inclk0,
c0);
input inclk0;
output c0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
|
// Model of FIFO in Altera
module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 4096;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output wrempty;
output [7:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [7:0] rdusedw;
reg [7:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
endmodule // fifo_1c_4k
|
// Model of FIFO in Altera
module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 4096;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output wrempty;
output [7:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [7:0] rdusedw;
reg [7:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
endmodule // fifo_1c_4k
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Vendor Independent FIFO module
// Width and Depth should be parameterizable
// Asynchronous clocks for each side
// Read side is read-acknowledge, not read-request
// FIFO does not enforce "don't write when full, don't read when empty"
// That is up to the connecting modules
// The FIFO only holds 2^N-1 entries, not 2^N
module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);
parameter width=32;
parameter depth=10;
input reset; // Asynchronous
input [width-1:0] data;
input write;
input wrclk;
output [depth-1:0] wr_used;
output [width-1:0] q;
input read_ack;
input rdclk;
output [depth-1:0] rd_used;
reg [depth-1:0] read_addr, write_addr,
read_addr_gray, read_addr_gray_sync,
write_addr_gray, write_addr_gray_sync;
// Pseudo-dual-port RAM
dpram #(.depth(10),.width(width),.size(1024))
fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write),
.rclk(rdclk), .rdata(q),.raddr(read_addr) );
wire [depth-1:0] wag,rag;
// Keep track of own side's pointer
always @(posedge wrclk or posedge reset)
if(reset) write_addr <= #1 0;
else if(write) write_addr <= #1 write_addr + 1;
always @(posedge rdclk or posedge reset)
if(reset) read_addr <= #1 0;
else if(read_ack) read_addr <= #1 read_addr + 1;
// Convert own side pointer to gray
bin2gray #(depth) write_b2g (write_addr,wag);
bin2gray #(depth) read_b2g (read_addr,rag);
// Latch it
always @(posedge wrclk or posedge reset)
if(reset) write_addr_gray <= #1 0;
else write_addr_gray <= #1 wag;
always @(posedge rdclk or posedge reset)
if(reset) read_addr_gray <= #1 0;
else read_addr_gray <= #1 rag;
// Send it to other side and latch
always @(posedge wrclk or posedge reset)
if(reset) read_addr_gray_sync <= #1 0;
else read_addr_gray_sync <= #1 read_addr_gray;
always @(posedge rdclk or posedge reset)
if(reset) write_addr_gray_sync <= #1 0;
else write_addr_gray_sync <= #1 write_addr_gray;
wire [depth-1:0] write_addr_sync, read_addr_sync;
// Convert back to binary
gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync);
gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync);
assign rd_used = write_addr_sync - read_addr;
assign wr_used = write_addr - read_addr_sync;
endmodule // fifo
module bin2gray(bin_val,gray_val);
parameter width = 8;
input [width-1:0] bin_val;
output reg [width-1:0] gray_val;
integer i;
always @*
begin
gray_val[width-1] = bin_val[width-1];
for(i=0;i<width-1;i=i+1)
gray_val[i] = bin_val[i] ^ bin_val[i+1];
end
endmodule // bin2gray
module gray2bin(gray_val,bin_val);
parameter width = 8;
input [width-1:0] gray_val;
output reg [width-1:0] bin_val;
integer i;
always @*
begin
bin_val[width-1] = gray_val[width-1];
for(i=width-2;i>=0;i=i-1)
bin_val[i] = bin_val[i+1] ^ gray_val[i];
end
endmodule // gray2bin
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Vendor Independent FIFO module
// Width and Depth should be parameterizable
// Asynchronous clocks for each side
// Read side is read-acknowledge, not read-request
// FIFO does not enforce "don't write when full, don't read when empty"
// That is up to the connecting modules
// The FIFO only holds 2^N-1 entries, not 2^N
module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);
parameter width=32;
parameter depth=10;
input reset; // Asynchronous
input [width-1:0] data;
input write;
input wrclk;
output [depth-1:0] wr_used;
output [width-1:0] q;
input read_ack;
input rdclk;
output [depth-1:0] rd_used;
reg [depth-1:0] read_addr, write_addr,
read_addr_gray, read_addr_gray_sync,
write_addr_gray, write_addr_gray_sync;
// Pseudo-dual-port RAM
dpram #(.depth(10),.width(width),.size(1024))
fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write),
.rclk(rdclk), .rdata(q),.raddr(read_addr) );
wire [depth-1:0] wag,rag;
// Keep track of own side's pointer
always @(posedge wrclk or posedge reset)
if(reset) write_addr <= #1 0;
else if(write) write_addr <= #1 write_addr + 1;
always @(posedge rdclk or posedge reset)
if(reset) read_addr <= #1 0;
else if(read_ack) read_addr <= #1 read_addr + 1;
// Convert own side pointer to gray
bin2gray #(depth) write_b2g (write_addr,wag);
bin2gray #(depth) read_b2g (read_addr,rag);
// Latch it
always @(posedge wrclk or posedge reset)
if(reset) write_addr_gray <= #1 0;
else write_addr_gray <= #1 wag;
always @(posedge rdclk or posedge reset)
if(reset) read_addr_gray <= #1 0;
else read_addr_gray <= #1 rag;
// Send it to other side and latch
always @(posedge wrclk or posedge reset)
if(reset) read_addr_gray_sync <= #1 0;
else read_addr_gray_sync <= #1 read_addr_gray;
always @(posedge rdclk or posedge reset)
if(reset) write_addr_gray_sync <= #1 0;
else write_addr_gray_sync <= #1 write_addr_gray;
wire [depth-1:0] write_addr_sync, read_addr_sync;
// Convert back to binary
gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync);
gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync);
assign rd_used = write_addr_sync - read_addr;
assign wr_used = write_addr - read_addr_sync;
endmodule // fifo
module bin2gray(bin_val,gray_val);
parameter width = 8;
input [width-1:0] bin_val;
output reg [width-1:0] gray_val;
integer i;
always @*
begin
gray_val[width-1] = bin_val[width-1];
for(i=0;i<width-1;i=i+1)
gray_val[i] = bin_val[i] ^ bin_val[i+1];
end
endmodule // bin2gray
module gray2bin(gray_val,bin_val);
parameter width = 8;
input [width-1:0] gray_val;
output reg [width-1:0] bin_val;
integer i;
always @*
begin
bin_val[width-1] = gray_val[width-1];
for(i=width-2;i>=0;i=i-1)
bin_val[i] = bin_val[i+1] ^ gray_val[i];
end
endmodule // gray2bin
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Vendor Independent FIFO module
// Width and Depth should be parameterizable
// Asynchronous clocks for each side
// Read side is read-acknowledge, not read-request
// FIFO does not enforce "don't write when full, don't read when empty"
// That is up to the connecting modules
// The FIFO only holds 2^N-1 entries, not 2^N
module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);
parameter width=32;
parameter depth=10;
input reset; // Asynchronous
input [width-1:0] data;
input write;
input wrclk;
output [depth-1:0] wr_used;
output [width-1:0] q;
input read_ack;
input rdclk;
output [depth-1:0] rd_used;
reg [depth-1:0] read_addr, write_addr,
read_addr_gray, read_addr_gray_sync,
write_addr_gray, write_addr_gray_sync;
// Pseudo-dual-port RAM
dpram #(.depth(10),.width(width),.size(1024))
fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write),
.rclk(rdclk), .rdata(q),.raddr(read_addr) );
wire [depth-1:0] wag,rag;
// Keep track of own side's pointer
always @(posedge wrclk or posedge reset)
if(reset) write_addr <= #1 0;
else if(write) write_addr <= #1 write_addr + 1;
always @(posedge rdclk or posedge reset)
if(reset) read_addr <= #1 0;
else if(read_ack) read_addr <= #1 read_addr + 1;
// Convert own side pointer to gray
bin2gray #(depth) write_b2g (write_addr,wag);
bin2gray #(depth) read_b2g (read_addr,rag);
// Latch it
always @(posedge wrclk or posedge reset)
if(reset) write_addr_gray <= #1 0;
else write_addr_gray <= #1 wag;
always @(posedge rdclk or posedge reset)
if(reset) read_addr_gray <= #1 0;
else read_addr_gray <= #1 rag;
// Send it to other side and latch
always @(posedge wrclk or posedge reset)
if(reset) read_addr_gray_sync <= #1 0;
else read_addr_gray_sync <= #1 read_addr_gray;
always @(posedge rdclk or posedge reset)
if(reset) write_addr_gray_sync <= #1 0;
else write_addr_gray_sync <= #1 write_addr_gray;
wire [depth-1:0] write_addr_sync, read_addr_sync;
// Convert back to binary
gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync);
gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync);
assign rd_used = write_addr_sync - read_addr;
assign wr_used = write_addr - read_addr_sync;
endmodule // fifo
module bin2gray(bin_val,gray_val);
parameter width = 8;
input [width-1:0] bin_val;
output reg [width-1:0] gray_val;
integer i;
always @*
begin
gray_val[width-1] = bin_val[width-1];
for(i=0;i<width-1;i=i+1)
gray_val[i] = bin_val[i] ^ bin_val[i+1];
end
endmodule // bin2gray
module gray2bin(gray_val,bin_val);
parameter width = 8;
input [width-1:0] gray_val;
output reg [width-1:0] bin_val;
integer i;
always @*
begin
bin_val[width-1] = gray_val[width-1];
for(i=width-2;i>=0;i=i-1)
bin_val[i] = bin_val[i+1] ^ gray_val[i];
end
endmodule // gray2bin
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Vendor Independent FIFO module
// Width and Depth should be parameterizable
// Asynchronous clocks for each side
// Read side is read-acknowledge, not read-request
// FIFO does not enforce "don't write when full, don't read when empty"
// That is up to the connecting modules
// The FIFO only holds 2^N-1 entries, not 2^N
module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);
parameter width=32;
parameter depth=10;
input reset; // Asynchronous
input [width-1:0] data;
input write;
input wrclk;
output [depth-1:0] wr_used;
output [width-1:0] q;
input read_ack;
input rdclk;
output [depth-1:0] rd_used;
reg [depth-1:0] read_addr, write_addr,
read_addr_gray, read_addr_gray_sync,
write_addr_gray, write_addr_gray_sync;
// Pseudo-dual-port RAM
dpram #(.depth(10),.width(width),.size(1024))
fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write),
.rclk(rdclk), .rdata(q),.raddr(read_addr) );
wire [depth-1:0] wag,rag;
// Keep track of own side's pointer
always @(posedge wrclk or posedge reset)
if(reset) write_addr <= #1 0;
else if(write) write_addr <= #1 write_addr + 1;
always @(posedge rdclk or posedge reset)
if(reset) read_addr <= #1 0;
else if(read_ack) read_addr <= #1 read_addr + 1;
// Convert own side pointer to gray
bin2gray #(depth) write_b2g (write_addr,wag);
bin2gray #(depth) read_b2g (read_addr,rag);
// Latch it
always @(posedge wrclk or posedge reset)
if(reset) write_addr_gray <= #1 0;
else write_addr_gray <= #1 wag;
always @(posedge rdclk or posedge reset)
if(reset) read_addr_gray <= #1 0;
else read_addr_gray <= #1 rag;
// Send it to other side and latch
always @(posedge wrclk or posedge reset)
if(reset) read_addr_gray_sync <= #1 0;
else read_addr_gray_sync <= #1 read_addr_gray;
always @(posedge rdclk or posedge reset)
if(reset) write_addr_gray_sync <= #1 0;
else write_addr_gray_sync <= #1 write_addr_gray;
wire [depth-1:0] write_addr_sync, read_addr_sync;
// Convert back to binary
gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync);
gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync);
assign rd_used = write_addr_sync - read_addr;
assign wr_used = write_addr - read_addr_sync;
endmodule // fifo
module bin2gray(bin_val,gray_val);
parameter width = 8;
input [width-1:0] bin_val;
output reg [width-1:0] gray_val;
integer i;
always @*
begin
gray_val[width-1] = bin_val[width-1];
for(i=0;i<width-1;i=i+1)
gray_val[i] = bin_val[i] ^ bin_val[i+1];
end
endmodule // bin2gray
module gray2bin(gray_val,bin_val);
parameter width = 8;
input [width-1:0] gray_val;
output reg [width-1:0] bin_val;
integer i;
always @*
begin
bin_val[width-1] = gray_val[width-1];
for(i=width-2;i>=0;i=i-1)
bin_val[i] = bin_val[i+1] ^ gray_val[i];
end
endmodule // gray2bin
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Vendor Independent FIFO module
// Width and Depth should be parameterizable
// Asynchronous clocks for each side
// Read side is read-acknowledge, not read-request
// FIFO does not enforce "don't write when full, don't read when empty"
// That is up to the connecting modules
// The FIFO only holds 2^N-1 entries, not 2^N
module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);
parameter width=32;
parameter depth=10;
input reset; // Asynchronous
input [width-1:0] data;
input write;
input wrclk;
output [depth-1:0] wr_used;
output [width-1:0] q;
input read_ack;
input rdclk;
output [depth-1:0] rd_used;
reg [depth-1:0] read_addr, write_addr,
read_addr_gray, read_addr_gray_sync,
write_addr_gray, write_addr_gray_sync;
// Pseudo-dual-port RAM
dpram #(.depth(10),.width(width),.size(1024))
fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write),
.rclk(rdclk), .rdata(q),.raddr(read_addr) );
wire [depth-1:0] wag,rag;
// Keep track of own side's pointer
always @(posedge wrclk or posedge reset)
if(reset) write_addr <= #1 0;
else if(write) write_addr <= #1 write_addr + 1;
always @(posedge rdclk or posedge reset)
if(reset) read_addr <= #1 0;
else if(read_ack) read_addr <= #1 read_addr + 1;
// Convert own side pointer to gray
bin2gray #(depth) write_b2g (write_addr,wag);
bin2gray #(depth) read_b2g (read_addr,rag);
// Latch it
always @(posedge wrclk or posedge reset)
if(reset) write_addr_gray <= #1 0;
else write_addr_gray <= #1 wag;
always @(posedge rdclk or posedge reset)
if(reset) read_addr_gray <= #1 0;
else read_addr_gray <= #1 rag;
// Send it to other side and latch
always @(posedge wrclk or posedge reset)
if(reset) read_addr_gray_sync <= #1 0;
else read_addr_gray_sync <= #1 read_addr_gray;
always @(posedge rdclk or posedge reset)
if(reset) write_addr_gray_sync <= #1 0;
else write_addr_gray_sync <= #1 write_addr_gray;
wire [depth-1:0] write_addr_sync, read_addr_sync;
// Convert back to binary
gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync);
gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync);
assign rd_used = write_addr_sync - read_addr;
assign wr_used = write_addr - read_addr_sync;
endmodule // fifo
module bin2gray(bin_val,gray_val);
parameter width = 8;
input [width-1:0] bin_val;
output reg [width-1:0] gray_val;
integer i;
always @*
begin
gray_val[width-1] = bin_val[width-1];
for(i=0;i<width-1;i=i+1)
gray_val[i] = bin_val[i] ^ bin_val[i+1];
end
endmodule // bin2gray
module gray2bin(gray_val,bin_val);
parameter width = 8;
input [width-1:0] gray_val;
output reg [width-1:0] bin_val;
integer i;
always @*
begin
bin_val[width-1] = gray_val[width-1];
for(i=width-2;i>=0;i=i-1)
bin_val[i] = bin_val[i+1] ^ gray_val[i];
end
endmodule // gray2bin
|
// Model of FIFO in Altera
module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 2048;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [10:0] rdusedw;
output wrfull;
output wrempty;
output [10:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [10:0] rdusedw;
reg [10:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule // fifo_1c_2k
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module gen_sync
( input clock,
input reset,
input enable,
input [7:0] rate,
output wire sync );
// parameter width = 8;
reg [7:0] counter;
assign sync = |(((rate+1)>>1)& counter);
always @(posedge clock)
if(reset || ~enable)
counter <= #1 0;
else if(counter == rate)
counter <= #1 0;
else
counter <= #1 counter + 8'd1;
endmodule // gen_sync
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module gen_sync
( input clock,
input reset,
input enable,
input [7:0] rate,
output wire sync );
// parameter width = 8;
reg [7:0] counter;
assign sync = |(((rate+1)>>1)& counter);
always @(posedge clock)
if(reset || ~enable)
counter <= #1 0;
else if(counter == rate)
counter <= #1 0;
else
counter <= #1 counter + 8'd1;
endmodule // gen_sync
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module gen_sync
( input clock,
input reset,
input enable,
input [7:0] rate,
output wire sync );
// parameter width = 8;
reg [7:0] counter;
assign sync = |(((rate+1)>>1)& counter);
always @(posedge clock)
if(reset || ~enable)
counter <= #1 0;
else if(counter == rate)
counter <= #1 0;
else
counter <= #1 counter + 8'd1;
endmodule // gen_sync
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module gen_sync
( input clock,
input reset,
input enable,
input [7:0] rate,
output wire sync );
// parameter width = 8;
reg [7:0] counter;
assign sync = |(((rate+1)>>1)& counter);
always @(posedge clock)
if(reset || ~enable)
counter <= #1 0;
else if(counter == rate)
counter <= #1 0;
else
counter <= #1 counter + 8'd1;
endmodule // gen_sync
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module gen_sync
( input clock,
input reset,
input enable,
input [7:0] rate,
output wire sync );
// parameter width = 8;
reg [7:0] counter;
assign sync = |(((rate+1)>>1)& counter);
always @(posedge clock)
if(reset || ~enable)
counter <= #1 0;
else if(counter == rate)
counter <= #1 0;
else
counter <= #1 counter + 8'd1;
endmodule // gen_sync
|
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module dspclkpll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
endmodule
|
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module dspclkpll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
endmodule
|
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module dspclkpll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
endmodule
|
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module dspclkpll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module addsub16 (
add_sub,
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
input aclr;
input clken;
output [15:0] result;
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module add32 (
dataa,
datab,
result)/* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
endmodule
|
// megafunction wizard: %FIFO%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_2k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=11 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//a_gray2bin device_family="Cyclone" WIDTH=11 bin gray
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_a_gray2bin_8m4
(
bin,
gray) /* synthesis synthesis_clearbox=1 */;
output [10:0] bin;
input [10:0] gray;
wire xor0;
wire xor1;
wire xor2;
wire xor3;
wire xor4;
wire xor5;
wire xor6;
wire xor7;
wire xor8;
wire xor9;
assign
bin = {gray[10], xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
xor0 = (gray[0] ^ xor1),
xor1 = (gray[1] ^ xor2),
xor2 = (gray[2] ^ xor3),
xor3 = (gray[3] ^ xor4),
xor4 = (gray[4] ^ xor5),
xor5 = (gray[5] ^ xor6),
xor6 = (gray[6] ^ xor7),
xor7 = (gray[7] ^ xor8),
xor8 = (gray[8] ^ xor9),
xor9 = (gray[10] ^ gray[9]);
endmodule //fifo_2k_a_gray2bin_8m4
//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=11 aclr clock cnt_en q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_a_graycounter_726
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [10:0] q;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire [0:0] wire_countera_4cout;
wire [0:0] wire_countera_5cout;
wire [0:0] wire_countera_6cout;
wire [0:0] wire_countera_7cout;
wire [0:0] wire_countera_8cout;
wire [0:0] wire_countera_9cout;
wire [10:0] wire_countera_regout;
wire wire_parity_cout;
wire wire_parity_regout;
wire [10:0] power_modified_counter_values;
wire sclr;
wire updown;
cyclone_lcell countera_0
(
.aclr(aclr),
.cin(wire_parity_cout),
.clk(clock),
.combout(),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(wire_countera_regout[0:0]),
.ena(1'b1),
.regout(wire_countera_regout[0:0]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_0.cin_used = "true",
countera_0.lut_mask = "c6a0",
countera_0.operation_mode = "arithmetic",
countera_0.sum_lutc_input = "cin",
countera_0.synch_mode = "on",
countera_0.lpm_type = "cyclone_lcell";
cyclone_lcell countera_1
(
.aclr(aclr),
.cin(wire_countera_0cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_1cout[0:0]),
.dataa(power_modified_counter_values[0]),
.datab(power_modified_counter_values[1]),
.ena(1'b1),
.regout(wire_countera_regout[1:1]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_1.cin_used = "true",
countera_1.lut_mask = "6c50",
countera_1.operation_mode = "arithmetic",
countera_1.sum_lutc_input = "cin",
countera_1.synch_mode = "on",
countera_1.lpm_type = "cyclone_lcell";
cyclone_lcell countera_2
(
.aclr(aclr),
.cin(wire_countera_1cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_2cout[0:0]),
.dataa(power_modified_counter_values[1]),
.datab(power_modified_counter_values[2]),
.ena(1'b1),
.regout(wire_countera_regout[2:2]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_2.cin_used = "true",
countera_2.lut_mask = "6c50",
countera_2.operation_mode = "arithmetic",
countera_2.sum_lutc_input = "cin",
countera_2.synch_mode = "on",
countera_2.lpm_type = "cyclone_lcell";
cyclone_lcell countera_3
(
.aclr(aclr),
.cin(wire_countera_2cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_3cout[0:0]),
.dataa(power_modified_counter_values[2]),
.datab(power_modified_counter_values[3]),
.ena(1'b1),
.regout(wire_countera_regout[3:3]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_3.cin_used = "true",
countera_3.lut_mask = "6c50",
countera_3.operation_mode = "arithmetic",
countera_3.sum_lutc_input = "cin",
countera_3.synch_mode = "on",
countera_3.lpm_type = "cyclone_lcell";
cyclone_lcell countera_4
(
.aclr(aclr),
.cin(wire_countera_3cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_4cout[0:0]),
.dataa(power_modified_counter_values[3]),
.datab(power_modified_counter_values[4]),
.ena(1'b1),
.regout(wire_countera_regout[4:4]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_4.cin_used = "true",
countera_4.lut_mask = "6c50",
countera_4.operation_mode = "arithmetic",
countera_4.sum_lutc_input = "cin",
countera_4.synch_mode = "on",
countera_4.lpm_type = "cyclone_lcell";
cyclone_lcell countera_5
(
.aclr(aclr),
.cin(wire_countera_4cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_5cout[0:0]),
.dataa(power_modified_counter_values[4]),
.datab(power_modified_counter_values[5]),
.ena(1'b1),
.regout(wire_countera_regout[5:5]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_5.cin_used = "true",
countera_5.lut_mask = "6c50",
countera_5.operation_mode = "arithmetic",
countera_5.sum_lutc_input = "cin",
countera_5.synch_mode = "on",
countera_5.lpm_type = "cyclone_lcell";
cyclone_lcell countera_6
(
.aclr(aclr),
.cin(wire_countera_5cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_6cout[0:0]),
.dataa(power_modified_counter_values[5]),
.datab(power_modified_counter_values[6]),
.ena(1'b1),
.regout(wire_countera_regout[6:6]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_6.cin_used = "true",
countera_6.lut_mask = "6c50",
countera_6.operation_mode = "arithmetic",
countera_6.sum_lutc_input = "cin",
countera_6.synch_mode = "on",
countera_6.lpm_type = "cyclone_lcell";
cyclone_lcell countera_7
(
.aclr(aclr),
.cin(wire_countera_6cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_7cout[0:0]),
.dataa(power_modified_counter_values[6]),
.datab(power_modified_counter_values[7]),
.ena(1'b1),
.regout(wire_countera_regout[7:7]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_7.cin_used = "true",
countera_7.lut_mask = "6c50",
countera_7.operation_mode = "arithmetic",
countera_7.sum_lutc_input = "cin",
countera_7.synch_mode = "on",
countera_7.lpm_type = "cyclone_lcell";
cyclone_lcell countera_8
(
.aclr(aclr),
.cin(wire_countera_7cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_8cout[0:0]),
.dataa(power_modified_counter_values[7]),
.datab(power_modified_counter_values[8]),
.ena(1'b1),
.regout(wire_countera_regout[8:8]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_8.cin_used = "true",
countera_8.lut_mask = "6c50",
countera_8.operation_mode = "arithmetic",
countera_8.sum_lutc_input = "cin",
countera_8.synch_mode = "on",
countera_8.lpm_type = "cyclone_lcell";
cyclone_lcell countera_9
(
.aclr(aclr),
.cin(wire_countera_8cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_9cout[0:0]),
.dataa(power_modified_counter_values[8]),
.datab(power_modified_counter_values[9]),
.ena(1'b1),
.regout(wire_countera_regout[9:9]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_9.cin_used = "true",
countera_9.lut_mask = "6c50",
countera_9.operation_mode = "arithmetic",
countera_9.sum_lutc_input = "cin",
countera_9.synch_mode = "on",
countera_9.lpm_type = "cyclone_lcell";
cyclone_lcell countera_10
(
.aclr(aclr),
.cin(wire_countera_9cout[0:0]),
.clk(clock),
.combout(),
.cout(),
.dataa(power_modified_counter_values[10]),
.ena(1'b1),
.regout(wire_countera_regout[10:10]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datab(1'b1),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_10.cin_used = "true",
countera_10.lut_mask = "5a5a",
countera_10.operation_mode = "normal",
countera_10.sum_lutc_input = "cin",
countera_10.synch_mode = "on",
countera_10.lpm_type = "cyclone_lcell";
cyclone_lcell parity
(
.aclr(aclr),
.cin(updown),
.clk(clock),
.combout(),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab(wire_parity_regout),
.ena(1'b1),
.regout(wire_parity_regout),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
parity.cin_used = "true",
parity.lut_mask = "6682",
parity.operation_mode = "arithmetic",
parity.synch_mode = "on",
parity.lpm_type = "cyclone_lcell";
assign
power_modified_counter_values = {wire_countera_regout[10:0]},
q = power_modified_counter_values,
sclr = 1'b0,
updown = 1'b1;
endmodule //fifo_2k_a_graycounter_726
//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=11 aclr clock cnt_en q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_a_graycounter_2r6
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [10:0] q;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire [0:0] wire_countera_4cout;
wire [0:0] wire_countera_5cout;
wire [0:0] wire_countera_6cout;
wire [0:0] wire_countera_7cout;
wire [0:0] wire_countera_8cout;
wire [0:0] wire_countera_9cout;
wire [10:0] wire_countera_regout;
wire wire_parity_cout;
wire wire_parity_regout;
wire [10:0] power_modified_counter_values;
wire sclr;
wire updown;
cyclone_lcell countera_0
(
.aclr(aclr),
.cin(wire_parity_cout),
.clk(clock),
.combout(),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(wire_countera_regout[0:0]),
.ena(1'b1),
.regout(wire_countera_regout[0:0]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_0.cin_used = "true",
countera_0.lut_mask = "c6a0",
countera_0.operation_mode = "arithmetic",
countera_0.sum_lutc_input = "cin",
countera_0.synch_mode = "on",
countera_0.lpm_type = "cyclone_lcell";
cyclone_lcell countera_1
(
.aclr(aclr),
.cin(wire_countera_0cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_1cout[0:0]),
.dataa(power_modified_counter_values[0]),
.datab(power_modified_counter_values[1]),
.ena(1'b1),
.regout(wire_countera_regout[1:1]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_1.cin_used = "true",
countera_1.lut_mask = "6c50",
countera_1.operation_mode = "arithmetic",
countera_1.sum_lutc_input = "cin",
countera_1.synch_mode = "on",
countera_1.lpm_type = "cyclone_lcell";
cyclone_lcell countera_2
(
.aclr(aclr),
.cin(wire_countera_1cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_2cout[0:0]),
.dataa(power_modified_counter_values[1]),
.datab(power_modified_counter_values[2]),
.ena(1'b1),
.regout(wire_countera_regout[2:2]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_2.cin_used = "true",
countera_2.lut_mask = "6c50",
countera_2.operation_mode = "arithmetic",
countera_2.sum_lutc_input = "cin",
countera_2.synch_mode = "on",
countera_2.lpm_type = "cyclone_lcell";
cyclone_lcell countera_3
(
.aclr(aclr),
.cin(wire_countera_2cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_3cout[0:0]),
.dataa(power_modified_counter_values[2]),
.datab(power_modified_counter_values[3]),
.ena(1'b1),
.regout(wire_countera_regout[3:3]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_3.cin_used = "true",
countera_3.lut_mask = "6c50",
countera_3.operation_mode = "arithmetic",
countera_3.sum_lutc_input = "cin",
countera_3.synch_mode = "on",
countera_3.lpm_type = "cyclone_lcell";
cyclone_lcell countera_4
(
.aclr(aclr),
.cin(wire_countera_3cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_4cout[0:0]),
.dataa(power_modified_counter_values[3]),
.datab(power_modified_counter_values[4]),
.ena(1'b1),
.regout(wire_countera_regout[4:4]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_4.cin_used = "true",
countera_4.lut_mask = "6c50",
countera_4.operation_mode = "arithmetic",
countera_4.sum_lutc_input = "cin",
countera_4.synch_mode = "on",
countera_4.lpm_type = "cyclone_lcell";
cyclone_lcell countera_5
(
.aclr(aclr),
.cin(wire_countera_4cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_5cout[0:0]),
.dataa(power_modified_counter_values[4]),
.datab(power_modified_counter_values[5]),
.ena(1'b1),
.regout(wire_countera_regout[5:5]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_5.cin_used = "true",
countera_5.lut_mask = "6c50",
countera_5.operation_mode = "arithmetic",
countera_5.sum_lutc_input = "cin",
countera_5.synch_mode = "on",
countera_5.lpm_type = "cyclone_lcell";
cyclone_lcell countera_6
(
.aclr(aclr),
.cin(wire_countera_5cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_6cout[0:0]),
.dataa(power_modified_counter_values[5]),
.datab(power_modified_counter_values[6]),
.ena(1'b1),
.regout(wire_countera_regout[6:6]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_6.cin_used = "true",
countera_6.lut_mask = "6c50",
countera_6.operation_mode = "arithmetic",
countera_6.sum_lutc_input = "cin",
countera_6.synch_mode = "on",
countera_6.lpm_type = "cyclone_lcell";
cyclone_lcell countera_7
(
.aclr(aclr),
.cin(wire_countera_6cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_7cout[0:0]),
.dataa(power_modified_counter_values[6]),
.datab(power_modified_counter_values[7]),
.ena(1'b1),
.regout(wire_countera_regout[7:7]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_7.cin_used = "true",
countera_7.lut_mask = "6c50",
countera_7.operation_mode = "arithmetic",
countera_7.sum_lutc_input = "cin",
countera_7.synch_mode = "on",
countera_7.lpm_type = "cyclone_lcell";
cyclone_lcell countera_8
(
.aclr(aclr),
.cin(wire_countera_7cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_8cout[0:0]),
.dataa(power_modified_counter_values[7]),
.datab(power_modified_counter_values[8]),
.ena(1'b1),
.regout(wire_countera_regout[8:8]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_8.cin_used = "true",
countera_8.lut_mask = "6c50",
countera_8.operation_mode = "arithmetic",
countera_8.sum_lutc_input = "cin",
countera_8.synch_mode = "on",
countera_8.lpm_type = "cyclone_lcell";
cyclone_lcell countera_9
(
.aclr(aclr),
.cin(wire_countera_8cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_9cout[0:0]),
.dataa(power_modified_counter_values[8]),
.datab(power_modified_counter_values[9]),
.ena(1'b1),
.regout(wire_countera_regout[9:9]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_9.cin_used = "true",
countera_9.lut_mask = "6c50",
countera_9.operation_mode = "arithmetic",
countera_9.sum_lutc_input = "cin",
countera_9.synch_mode = "on",
countera_9.lpm_type = "cyclone_lcell";
cyclone_lcell countera_10
(
.aclr(aclr),
.cin(wire_countera_9cout[0:0]),
.clk(clock),
.combout(),
.cout(),
.dataa(power_modified_counter_values[10]),
.ena(1'b1),
.regout(wire_countera_regout[10:10]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datab(1'b1),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_10.cin_used = "true",
countera_10.lut_mask = "5a5a",
countera_10.operation_mode = "normal",
countera_10.sum_lutc_input = "cin",
countera_10.synch_mode = "on",
countera_10.lpm_type = "cyclone_lcell";
cyclone_lcell parity
(
.aclr(aclr),
.cin(updown),
.clk(clock),
.combout(),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab((~ wire_parity_regout)),
.ena(1'b1),
.regout(wire_parity_regout),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
parity.cin_used = "true",
parity.lut_mask = "9982",
parity.operation_mode = "arithmetic",
parity.synch_mode = "on",
parity.lpm_type = "cyclone_lcell";
assign
power_modified_counter_values = {wire_countera_regout[10:1], (~ wire_countera_regout[0])},
q = power_modified_counter_values,
sclr = 1'b0,
updown = 1'b1;
endmodule //fifo_2k_a_graycounter_2r6
//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = M4K 8
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_altsyncram_6pl
(
address_a,
address_b,
clock0,
clock1,
clocken1,
data_a,
q_b,
wren_a) /* synthesis synthesis_clearbox=1 */;
input [10:0] address_a;
input [10:0] address_b;
input clock0;
input clock1;
input clocken1;
input [15:0] data_a;
output [15:0] q_b;
input wren_a;
wire [0:0] wire_ram_block3a_0portbdataout;
wire [0:0] wire_ram_block3a_1portbdataout;
wire [0:0] wire_ram_block3a_2portbdataout;
wire [0:0] wire_ram_block3a_3portbdataout;
wire [0:0] wire_ram_block3a_4portbdataout;
wire [0:0] wire_ram_block3a_5portbdataout;
wire [0:0] wire_ram_block3a_6portbdataout;
wire [0:0] wire_ram_block3a_7portbdataout;
wire [0:0] wire_ram_block3a_8portbdataout;
wire [0:0] wire_ram_block3a_9portbdataout;
wire [0:0] wire_ram_block3a_10portbdataout;
wire [0:0] wire_ram_block3a_11portbdataout;
wire [0:0] wire_ram_block3a_12portbdataout;
wire [0:0] wire_ram_block3a_13portbdataout;
wire [0:0] wire_ram_block3a_14portbdataout;
wire [0:0] wire_ram_block3a_15portbdataout;
wire [10:0] address_a_wire;
wire [10:0] address_b_wire;
cyclone_ram_block ram_block3a_0
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[0]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_0portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_0.connectivity_checking = "OFF",
ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
ram_block3a_0.operation_mode = "dual_port",
ram_block3a_0.port_a_address_width = 11,
ram_block3a_0.port_a_data_width = 1,
ram_block3a_0.port_a_first_address = 0,
ram_block3a_0.port_a_first_bit_number = 0,
ram_block3a_0.port_a_last_address = 2047,
ram_block3a_0.port_a_logical_ram_depth = 2048,
ram_block3a_0.port_a_logical_ram_width = 16,
ram_block3a_0.port_b_address_clear = "none",
ram_block3a_0.port_b_address_clock = "clock1",
ram_block3a_0.port_b_address_width = 11,
ram_block3a_0.port_b_data_out_clear = "none",
ram_block3a_0.port_b_data_out_clock = "none",
ram_block3a_0.port_b_data_width = 1,
ram_block3a_0.port_b_first_address = 0,
ram_block3a_0.port_b_first_bit_number = 0,
ram_block3a_0.port_b_last_address = 2047,
ram_block3a_0.port_b_logical_ram_depth = 2048,
ram_block3a_0.port_b_logical_ram_width = 16,
ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_0.ram_block_type = "auto",
ram_block3a_0.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_1
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[1]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_1portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_1.connectivity_checking = "OFF",
ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
ram_block3a_1.operation_mode = "dual_port",
ram_block3a_1.port_a_address_width = 11,
ram_block3a_1.port_a_data_width = 1,
ram_block3a_1.port_a_first_address = 0,
ram_block3a_1.port_a_first_bit_number = 1,
ram_block3a_1.port_a_last_address = 2047,
ram_block3a_1.port_a_logical_ram_depth = 2048,
ram_block3a_1.port_a_logical_ram_width = 16,
ram_block3a_1.port_b_address_clear = "none",
ram_block3a_1.port_b_address_clock = "clock1",
ram_block3a_1.port_b_address_width = 11,
ram_block3a_1.port_b_data_out_clear = "none",
ram_block3a_1.port_b_data_out_clock = "none",
ram_block3a_1.port_b_data_width = 1,
ram_block3a_1.port_b_first_address = 0,
ram_block3a_1.port_b_first_bit_number = 1,
ram_block3a_1.port_b_last_address = 2047,
ram_block3a_1.port_b_logical_ram_depth = 2048,
ram_block3a_1.port_b_logical_ram_width = 16,
ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_1.ram_block_type = "auto",
ram_block3a_1.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_2
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[2]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_2portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_2.connectivity_checking = "OFF",
ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
ram_block3a_2.operation_mode = "dual_port",
ram_block3a_2.port_a_address_width = 11,
ram_block3a_2.port_a_data_width = 1,
ram_block3a_2.port_a_first_address = 0,
ram_block3a_2.port_a_first_bit_number = 2,
ram_block3a_2.port_a_last_address = 2047,
ram_block3a_2.port_a_logical_ram_depth = 2048,
ram_block3a_2.port_a_logical_ram_width = 16,
ram_block3a_2.port_b_address_clear = "none",
ram_block3a_2.port_b_address_clock = "clock1",
ram_block3a_2.port_b_address_width = 11,
ram_block3a_2.port_b_data_out_clear = "none",
ram_block3a_2.port_b_data_out_clock = "none",
ram_block3a_2.port_b_data_width = 1,
ram_block3a_2.port_b_first_address = 0,
ram_block3a_2.port_b_first_bit_number = 2,
ram_block3a_2.port_b_last_address = 2047,
ram_block3a_2.port_b_logical_ram_depth = 2048,
ram_block3a_2.port_b_logical_ram_width = 16,
ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_2.ram_block_type = "auto",
ram_block3a_2.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_3
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[3]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_3portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_3.connectivity_checking = "OFF",
ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
ram_block3a_3.operation_mode = "dual_port",
ram_block3a_3.port_a_address_width = 11,
ram_block3a_3.port_a_data_width = 1,
ram_block3a_3.port_a_first_address = 0,
ram_block3a_3.port_a_first_bit_number = 3,
ram_block3a_3.port_a_last_address = 2047,
ram_block3a_3.port_a_logical_ram_depth = 2048,
ram_block3a_3.port_a_logical_ram_width = 16,
ram_block3a_3.port_b_address_clear = "none",
ram_block3a_3.port_b_address_clock = "clock1",
ram_block3a_3.port_b_address_width = 11,
ram_block3a_3.port_b_data_out_clear = "none",
ram_block3a_3.port_b_data_out_clock = "none",
ram_block3a_3.port_b_data_width = 1,
ram_block3a_3.port_b_first_address = 0,
ram_block3a_3.port_b_first_bit_number = 3,
ram_block3a_3.port_b_last_address = 2047,
ram_block3a_3.port_b_logical_ram_depth = 2048,
ram_block3a_3.port_b_logical_ram_width = 16,
ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_3.ram_block_type = "auto",
ram_block3a_3.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_4
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[4]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_4portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_4.connectivity_checking = "OFF",
ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
ram_block3a_4.operation_mode = "dual_port",
ram_block3a_4.port_a_address_width = 11,
ram_block3a_4.port_a_data_width = 1,
ram_block3a_4.port_a_first_address = 0,
ram_block3a_4.port_a_first_bit_number = 4,
ram_block3a_4.port_a_last_address = 2047,
ram_block3a_4.port_a_logical_ram_depth = 2048,
ram_block3a_4.port_a_logical_ram_width = 16,
ram_block3a_4.port_b_address_clear = "none",
ram_block3a_4.port_b_address_clock = "clock1",
ram_block3a_4.port_b_address_width = 11,
ram_block3a_4.port_b_data_out_clear = "none",
ram_block3a_4.port_b_data_out_clock = "none",
ram_block3a_4.port_b_data_width = 1,
ram_block3a_4.port_b_first_address = 0,
ram_block3a_4.port_b_first_bit_number = 4,
ram_block3a_4.port_b_last_address = 2047,
ram_block3a_4.port_b_logical_ram_depth = 2048,
ram_block3a_4.port_b_logical_ram_width = 16,
ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_4.ram_block_type = "auto",
ram_block3a_4.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_5
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[5]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_5portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_5.connectivity_checking = "OFF",
ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
ram_block3a_5.operation_mode = "dual_port",
ram_block3a_5.port_a_address_width = 11,
ram_block3a_5.port_a_data_width = 1,
ram_block3a_5.port_a_first_address = 0,
ram_block3a_5.port_a_first_bit_number = 5,
ram_block3a_5.port_a_last_address = 2047,
ram_block3a_5.port_a_logical_ram_depth = 2048,
ram_block3a_5.port_a_logical_ram_width = 16,
ram_block3a_5.port_b_address_clear = "none",
ram_block3a_5.port_b_address_clock = "clock1",
ram_block3a_5.port_b_address_width = 11,
ram_block3a_5.port_b_data_out_clear = "none",
ram_block3a_5.port_b_data_out_clock = "none",
ram_block3a_5.port_b_data_width = 1,
ram_block3a_5.port_b_first_address = 0,
ram_block3a_5.port_b_first_bit_number = 5,
ram_block3a_5.port_b_last_address = 2047,
ram_block3a_5.port_b_logical_ram_depth = 2048,
ram_block3a_5.port_b_logical_ram_width = 16,
ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_5.ram_block_type = "auto",
ram_block3a_5.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_6
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[6]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_6portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_6.connectivity_checking = "OFF",
ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
ram_block3a_6.operation_mode = "dual_port",
ram_block3a_6.port_a_address_width = 11,
ram_block3a_6.port_a_data_width = 1,
ram_block3a_6.port_a_first_address = 0,
ram_block3a_6.port_a_first_bit_number = 6,
ram_block3a_6.port_a_last_address = 2047,
ram_block3a_6.port_a_logical_ram_depth = 2048,
ram_block3a_6.port_a_logical_ram_width = 16,
ram_block3a_6.port_b_address_clear = "none",
ram_block3a_6.port_b_address_clock = "clock1",
ram_block3a_6.port_b_address_width = 11,
ram_block3a_6.port_b_data_out_clear = "none",
ram_block3a_6.port_b_data_out_clock = "none",
ram_block3a_6.port_b_data_width = 1,
ram_block3a_6.port_b_first_address = 0,
ram_block3a_6.port_b_first_bit_number = 6,
ram_block3a_6.port_b_last_address = 2047,
ram_block3a_6.port_b_logical_ram_depth = 2048,
ram_block3a_6.port_b_logical_ram_width = 16,
ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_6.ram_block_type = "auto",
ram_block3a_6.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_7
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[7]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_7portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_7.connectivity_checking = "OFF",
ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
ram_block3a_7.operation_mode = "dual_port",
ram_block3a_7.port_a_address_width = 11,
ram_block3a_7.port_a_data_width = 1,
ram_block3a_7.port_a_first_address = 0,
ram_block3a_7.port_a_first_bit_number = 7,
ram_block3a_7.port_a_last_address = 2047,
ram_block3a_7.port_a_logical_ram_depth = 2048,
ram_block3a_7.port_a_logical_ram_width = 16,
ram_block3a_7.port_b_address_clear = "none",
ram_block3a_7.port_b_address_clock = "clock1",
ram_block3a_7.port_b_address_width = 11,
ram_block3a_7.port_b_data_out_clear = "none",
ram_block3a_7.port_b_data_out_clock = "none",
ram_block3a_7.port_b_data_width = 1,
ram_block3a_7.port_b_first_address = 0,
ram_block3a_7.port_b_first_bit_number = 7,
ram_block3a_7.port_b_last_address = 2047,
ram_block3a_7.port_b_logical_ram_depth = 2048,
ram_block3a_7.port_b_logical_ram_width = 16,
ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_7.ram_block_type = "auto",
ram_block3a_7.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_8
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[8]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_8portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_8.connectivity_checking = "OFF",
ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
ram_block3a_8.operation_mode = "dual_port",
ram_block3a_8.port_a_address_width = 11,
ram_block3a_8.port_a_data_width = 1,
ram_block3a_8.port_a_first_address = 0,
ram_block3a_8.port_a_first_bit_number = 8,
ram_block3a_8.port_a_last_address = 2047,
ram_block3a_8.port_a_logical_ram_depth = 2048,
ram_block3a_8.port_a_logical_ram_width = 16,
ram_block3a_8.port_b_address_clear = "none",
ram_block3a_8.port_b_address_clock = "clock1",
ram_block3a_8.port_b_address_width = 11,
ram_block3a_8.port_b_data_out_clear = "none",
ram_block3a_8.port_b_data_out_clock = "none",
ram_block3a_8.port_b_data_width = 1,
ram_block3a_8.port_b_first_address = 0,
ram_block3a_8.port_b_first_bit_number = 8,
ram_block3a_8.port_b_last_address = 2047,
ram_block3a_8.port_b_logical_ram_depth = 2048,
ram_block3a_8.port_b_logical_ram_width = 16,
ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_8.ram_block_type = "auto",
ram_block3a_8.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_9
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[9]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_9portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_9.connectivity_checking = "OFF",
ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
ram_block3a_9.operation_mode = "dual_port",
ram_block3a_9.port_a_address_width = 11,
ram_block3a_9.port_a_data_width = 1,
ram_block3a_9.port_a_first_address = 0,
ram_block3a_9.port_a_first_bit_number = 9,
ram_block3a_9.port_a_last_address = 2047,
ram_block3a_9.port_a_logical_ram_depth = 2048,
ram_block3a_9.port_a_logical_ram_width = 16,
ram_block3a_9.port_b_address_clear = "none",
ram_block3a_9.port_b_address_clock = "clock1",
ram_block3a_9.port_b_address_width = 11,
ram_block3a_9.port_b_data_out_clear = "none",
ram_block3a_9.port_b_data_out_clock = "none",
ram_block3a_9.port_b_data_width = 1,
ram_block3a_9.port_b_first_address = 0,
ram_block3a_9.port_b_first_bit_number = 9,
ram_block3a_9.port_b_last_address = 2047,
ram_block3a_9.port_b_logical_ram_depth = 2048,
ram_block3a_9.port_b_logical_ram_width = 16,
ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_9.ram_block_type = "auto",
ram_block3a_9.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_10
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[10]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_10portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_10.connectivity_checking = "OFF",
ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
ram_block3a_10.operation_mode = "dual_port",
ram_block3a_10.port_a_address_width = 11,
ram_block3a_10.port_a_data_width = 1,
ram_block3a_10.port_a_first_address = 0,
ram_block3a_10.port_a_first_bit_number = 10,
ram_block3a_10.port_a_last_address = 2047,
ram_block3a_10.port_a_logical_ram_depth = 2048,
ram_block3a_10.port_a_logical_ram_width = 16,
ram_block3a_10.port_b_address_clear = "none",
ram_block3a_10.port_b_address_clock = "clock1",
ram_block3a_10.port_b_address_width = 11,
ram_block3a_10.port_b_data_out_clear = "none",
ram_block3a_10.port_b_data_out_clock = "none",
ram_block3a_10.port_b_data_width = 1,
ram_block3a_10.port_b_first_address = 0,
ram_block3a_10.port_b_first_bit_number = 10,
ram_block3a_10.port_b_last_address = 2047,
ram_block3a_10.port_b_logical_ram_depth = 2048,
ram_block3a_10.port_b_logical_ram_width = 16,
ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_10.ram_block_type = "auto",
ram_block3a_10.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_11
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[11]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_11portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_11.connectivity_checking = "OFF",
ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
ram_block3a_11.operation_mode = "dual_port",
ram_block3a_11.port_a_address_width = 11,
ram_block3a_11.port_a_data_width = 1,
ram_block3a_11.port_a_first_address = 0,
ram_block3a_11.port_a_first_bit_number = 11,
ram_block3a_11.port_a_last_address = 2047,
ram_block3a_11.port_a_logical_ram_depth = 2048,
ram_block3a_11.port_a_logical_ram_width = 16,
ram_block3a_11.port_b_address_clear = "none",
ram_block3a_11.port_b_address_clock = "clock1",
ram_block3a_11.port_b_address_width = 11,
ram_block3a_11.port_b_data_out_clear = "none",
ram_block3a_11.port_b_data_out_clock = "none",
ram_block3a_11.port_b_data_width = 1,
ram_block3a_11.port_b_first_address = 0,
ram_block3a_11.port_b_first_bit_number = 11,
ram_block3a_11.port_b_last_address = 2047,
ram_block3a_11.port_b_logical_ram_depth = 2048,
ram_block3a_11.port_b_logical_ram_width = 16,
ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_11.ram_block_type = "auto",
ram_block3a_11.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_12
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[12]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_12portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_12.connectivity_checking = "OFF",
ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
ram_block3a_12.operation_mode = "dual_port",
ram_block3a_12.port_a_address_width = 11,
ram_block3a_12.port_a_data_width = 1,
ram_block3a_12.port_a_first_address = 0,
ram_block3a_12.port_a_first_bit_number = 12,
ram_block3a_12.port_a_last_address = 2047,
ram_block3a_12.port_a_logical_ram_depth = 2048,
ram_block3a_12.port_a_logical_ram_width = 16,
ram_block3a_12.port_b_address_clear = "none",
ram_block3a_12.port_b_address_clock = "clock1",
ram_block3a_12.port_b_address_width = 11,
ram_block3a_12.port_b_data_out_clear = "none",
ram_block3a_12.port_b_data_out_clock = "none",
ram_block3a_12.port_b_data_width = 1,
ram_block3a_12.port_b_first_address = 0,
ram_block3a_12.port_b_first_bit_number = 12,
ram_block3a_12.port_b_last_address = 2047,
ram_block3a_12.port_b_logical_ram_depth = 2048,
ram_block3a_12.port_b_logical_ram_width = 16,
ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_12.ram_block_type = "auto",
ram_block3a_12.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_13
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[13]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_13portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_13.connectivity_checking = "OFF",
ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
ram_block3a_13.operation_mode = "dual_port",
ram_block3a_13.port_a_address_width = 11,
ram_block3a_13.port_a_data_width = 1,
ram_block3a_13.port_a_first_address = 0,
ram_block3a_13.port_a_first_bit_number = 13,
ram_block3a_13.port_a_last_address = 2047,
ram_block3a_13.port_a_logical_ram_depth = 2048,
ram_block3a_13.port_a_logical_ram_width = 16,
ram_block3a_13.port_b_address_clear = "none",
ram_block3a_13.port_b_address_clock = "clock1",
ram_block3a_13.port_b_address_width = 11,
ram_block3a_13.port_b_data_out_clear = "none",
ram_block3a_13.port_b_data_out_clock = "none",
ram_block3a_13.port_b_data_width = 1,
ram_block3a_13.port_b_first_address = 0,
ram_block3a_13.port_b_first_bit_number = 13,
ram_block3a_13.port_b_last_address = 2047,
ram_block3a_13.port_b_logical_ram_depth = 2048,
ram_block3a_13.port_b_logical_ram_width = 16,
ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_13.ram_block_type = "auto",
ram_block3a_13.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_14
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[14]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_14portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_14.connectivity_checking = "OFF",
ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
ram_block3a_14.operation_mode = "dual_port",
ram_block3a_14.port_a_address_width = 11,
ram_block3a_14.port_a_data_width = 1,
ram_block3a_14.port_a_first_address = 0,
ram_block3a_14.port_a_first_bit_number = 14,
ram_block3a_14.port_a_last_address = 2047,
ram_block3a_14.port_a_logical_ram_depth = 2048,
ram_block3a_14.port_a_logical_ram_width = 16,
ram_block3a_14.port_b_address_clear = "none",
ram_block3a_14.port_b_address_clock = "clock1",
ram_block3a_14.port_b_address_width = 11,
ram_block3a_14.port_b_data_out_clear = "none",
ram_block3a_14.port_b_data_out_clock = "none",
ram_block3a_14.port_b_data_width = 1,
ram_block3a_14.port_b_first_address = 0,
ram_block3a_14.port_b_first_bit_number = 14,
ram_block3a_14.port_b_last_address = 2047,
ram_block3a_14.port_b_logical_ram_depth = 2048,
ram_block3a_14.port_b_logical_ram_width = 16,
ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_14.ram_block_type = "auto",
ram_block3a_14.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_15
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[15]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_15portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_15.connectivity_checking = "OFF",
ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
ram_block3a_15.operation_mode = "dual_port",
ram_block3a_15.port_a_address_width = 11,
ram_block3a_15.port_a_data_width = 1,
ram_block3a_15.port_a_first_address = 0,
ram_block3a_15.port_a_first_bit_number = 15,
ram_block3a_15.port_a_last_address = 2047,
ram_block3a_15.port_a_logical_ram_depth = 2048,
ram_block3a_15.port_a_logical_ram_width = 16,
ram_block3a_15.port_b_address_clear = "none",
ram_block3a_15.port_b_address_clock = "clock1",
ram_block3a_15.port_b_address_width = 11,
ram_block3a_15.port_b_data_out_clear = "none",
ram_block3a_15.port_b_data_out_clock = "none",
ram_block3a_15.port_b_data_width = 1,
ram_block3a_15.port_b_first_address = 0,
ram_block3a_15.port_b_first_bit_number = 15,
ram_block3a_15.port_b_last_address = 2047,
ram_block3a_15.port_b_logical_ram_depth = 2048,
ram_block3a_15.port_b_logical_ram_width = 16,
ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_15.ram_block_type = "auto",
ram_block3a_15.lpm_type = "cyclone_ram_block";
assign
address_a_wire = address_a,
address_b_wire = address_b,
q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
endmodule //fifo_2k_altsyncram_6pl
//dffpipe DELAY=1 WIDTH=11 clock clrn d q
//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = lut 11
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_dffpipe_ab3
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [10:0] d;
output [10:0] q;
wire [10:0] wire_dffe4a_D;
reg [10:0] dffe4a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0];
// synopsys translate_off
initial
dffe4a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1];
// synopsys translate_off
initial
dffe4a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2];
// synopsys translate_off
initial
dffe4a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3];
// synopsys translate_off
initial
dffe4a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4];
// synopsys translate_off
initial
dffe4a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5];
// synopsys translate_off
initial
dffe4a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6];
// synopsys translate_off
initial
dffe4a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7];
// synopsys translate_off
initial
dffe4a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8];
// synopsys translate_off
initial
dffe4a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9];
// synopsys translate_off
initial
dffe4a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10];
assign
wire_dffe4a_D = (d & {11{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe4a,
sclr = 1'b0;
endmodule //fifo_2k_dffpipe_ab3
//dffpipe WIDTH=11 clock clrn d q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//dffpipe WIDTH=11 clock clrn d q
//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = lut 11
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_dffpipe_dm2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [10:0] d;
output [10:0] q;
wire [10:0] wire_dffe6a_D;
reg [10:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe6a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0];
// synopsys translate_off
initial
dffe6a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1];
// synopsys translate_off
initial
dffe6a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2];
// synopsys translate_off
initial
dffe6a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3];
// synopsys translate_off
initial
dffe6a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4];
// synopsys translate_off
initial
dffe6a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5];
// synopsys translate_off
initial
dffe6a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6];
// synopsys translate_off
initial
dffe6a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7];
// synopsys translate_off
initial
dffe6a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8];
// synopsys translate_off
initial
dffe6a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9];
// synopsys translate_off
initial
dffe6a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10];
assign
wire_dffe6a_D = (d & {11{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //fifo_2k_dffpipe_dm2
//synthesis_resources = lut 11
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_alt_synch_pipe_dm2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
input clock;
input clrn;
input [10:0] d;
output [10:0] q;
wire [10:0] wire_dffpipe5_q;
fifo_2k_dffpipe_dm2 dffpipe5
(
.clock(clock),
.clrn(clrn),
.d(d),
.q(wire_dffpipe5_q));
assign
q = wire_dffpipe5_q;
endmodule //fifo_2k_alt_synch_pipe_dm2
//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=11 dataa datab result
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 11
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_add_sub_a18
(
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input [10:0] dataa;
input [10:0] datab;
output [10:0] result;
wire [10:0] wire_add_sub_cella_combout;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [0:0] wire_add_sub_cella_7cout;
wire [0:0] wire_add_sub_cella_8cout;
wire [0:0] wire_add_sub_cella_9cout;
wire [10:0] wire_add_sub_cella_dataa;
wire [10:0] wire_add_sub_cella_datab;
cyclone_lcell add_sub_cella_0
(
.cin(1'b1),
.combout(wire_add_sub_cella_combout[0:0]),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "69b2",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_1
(
.cin(wire_add_sub_cella_0cout[0:0]),
.combout(wire_add_sub_cella_combout[1:1]),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "69b2",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_2
(
.cin(wire_add_sub_cella_1cout[0:0]),
.combout(wire_add_sub_cella_combout[2:2]),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "69b2",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_3
(
.cin(wire_add_sub_cella_2cout[0:0]),
.combout(wire_add_sub_cella_combout[3:3]),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "69b2",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_4
(
.cin(wire_add_sub_cella_3cout[0:0]),
.combout(wire_add_sub_cella_combout[4:4]),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "69b2",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_5
(
.cin(wire_add_sub_cella_4cout[0:0]),
.combout(wire_add_sub_cella_combout[5:5]),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "69b2",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_6
(
.cin(wire_add_sub_cella_5cout[0:0]),
.combout(wire_add_sub_cella_combout[6:6]),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "69b2",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_7
(
.cin(wire_add_sub_cella_6cout[0:0]),
.combout(wire_add_sub_cella_combout[7:7]),
.cout(wire_add_sub_cella_7cout[0:0]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "69b2",
add_sub_cella_7.operation_mode = "arithmetic",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_8
(
.cin(wire_add_sub_cella_7cout[0:0]),
.combout(wire_add_sub_cella_combout[8:8]),
.cout(wire_add_sub_cella_8cout[0:0]),
.dataa(wire_add_sub_cella_dataa[8:8]),
.datab(wire_add_sub_cella_datab[8:8]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_8.cin_used = "true",
add_sub_cella_8.lut_mask = "69b2",
add_sub_cella_8.operation_mode = "arithmetic",
add_sub_cella_8.sum_lutc_input = "cin",
add_sub_cella_8.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_9
(
.cin(wire_add_sub_cella_8cout[0:0]),
.combout(wire_add_sub_cella_combout[9:9]),
.cout(wire_add_sub_cella_9cout[0:0]),
.dataa(wire_add_sub_cella_dataa[9:9]),
.datab(wire_add_sub_cella_datab[9:9]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_9.cin_used = "true",
add_sub_cella_9.lut_mask = "69b2",
add_sub_cella_9.operation_mode = "arithmetic",
add_sub_cella_9.sum_lutc_input = "cin",
add_sub_cella_9.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_10
(
.cin(wire_add_sub_cella_9cout[0:0]),
.combout(wire_add_sub_cella_combout[10:10]),
.cout(),
.dataa(wire_add_sub_cella_dataa[10:10]),
.datab(wire_add_sub_cella_datab[10:10]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_10.cin_used = "true",
add_sub_cella_10.lut_mask = "6969",
add_sub_cella_10.operation_mode = "normal",
add_sub_cella_10.sum_lutc_input = "cin",
add_sub_cella_10.lpm_type = "cyclone_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_combout;
endmodule //fifo_2k_add_sub_a18
//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 97 M4K 8
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_dcfifo_0cq
(
aclr,
data,
q,
rdclk,
rdempty,
rdreq,
rdusedw,
wrclk,
wrfull,
wrreq,
wrusedw) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
input aclr;
input [15:0] data;
output [15:0] q;
input rdclk;
output rdempty;
input rdreq;
output [10:0] rdusedw;
input wrclk;
output wrfull;
input wrreq;
output [10:0] wrusedw;
wire [10:0] wire_rdptr_g_gray2bin_bin;
wire [10:0] wire_rs_dgwp_gray2bin_bin;
wire [10:0] wire_wrptr_g_gray2bin_bin;
wire [10:0] wire_ws_dgrp_gray2bin_bin;
wire [10:0] wire_rdptr_g_q;
wire [10:0] wire_rdptr_g1p_q;
wire [10:0] wire_wrptr_g1p_q;
wire [15:0] wire_fifo_ram_q_b;
reg [10:0] delayed_wrptr_g;
reg [10:0] wrptr_g;
wire [10:0] wire_rs_brp_q;
wire [10:0] wire_rs_bwp_q;
wire [10:0] wire_rs_dgwp_q;
wire [10:0] wire_ws_brp_q;
wire [10:0] wire_ws_bwp_q;
wire [10:0] wire_ws_dgrp_q;
wire [10:0] wire_rdusedw_sub_result;
wire [10:0] wire_wrusedw_sub_result;
reg wire_rdempty_eq_comp_aeb_int;
wire wire_rdempty_eq_comp_aeb;
wire [10:0] wire_rdempty_eq_comp_dataa;
wire [10:0] wire_rdempty_eq_comp_datab;
reg wire_wrfull_eq_comp_aeb_int;
wire wire_wrfull_eq_comp_aeb;
wire [10:0] wire_wrfull_eq_comp_dataa;
wire [10:0] wire_wrfull_eq_comp_datab;
wire int_rdempty;
wire int_wrfull;
wire valid_rdreq;
wire valid_wrreq;
fifo_2k_a_gray2bin_8m4 rdptr_g_gray2bin
(
.bin(wire_rdptr_g_gray2bin_bin),
.gray(wire_rdptr_g_q));
fifo_2k_a_gray2bin_8m4 rs_dgwp_gray2bin
(
.bin(wire_rs_dgwp_gray2bin_bin),
.gray(wire_rs_dgwp_q));
fifo_2k_a_gray2bin_8m4 wrptr_g_gray2bin
(
.bin(wire_wrptr_g_gray2bin_bin),
.gray(wrptr_g));
fifo_2k_a_gray2bin_8m4 ws_dgrp_gray2bin
(
.bin(wire_ws_dgrp_gray2bin_bin),
.gray(wire_ws_dgrp_q));
fifo_2k_a_graycounter_726 rdptr_g
(
.aclr(aclr),
.clock(rdclk),
.cnt_en(valid_rdreq),
.q(wire_rdptr_g_q));
fifo_2k_a_graycounter_2r6 rdptr_g1p
(
.aclr(aclr),
.clock(rdclk),
.cnt_en(valid_rdreq),
.q(wire_rdptr_g1p_q));
fifo_2k_a_graycounter_2r6 wrptr_g1p
(
.aclr(aclr),
.clock(wrclk),
.cnt_en(valid_wrreq),
.q(wire_wrptr_g1p_q));
fifo_2k_altsyncram_6pl fifo_ram
(
.address_a(wrptr_g),
.address_b(((wire_rdptr_g_q & {11{int_rdempty}}) | (wire_rdptr_g1p_q & {11{(~ int_rdempty)}}))),
.clock0(wrclk),
.clock1(rdclk),
.clocken1((valid_rdreq | int_rdempty)),
.data_a(data),
.q_b(wire_fifo_ram_q_b),
.wren_a(valid_wrreq));
// synopsys translate_off
initial
delayed_wrptr_g = 0;
// synopsys translate_on
always @ ( posedge wrclk or posedge aclr)
if (aclr == 1'b1) delayed_wrptr_g <= 11'b0;
else delayed_wrptr_g <= wrptr_g;
// synopsys translate_off
initial
wrptr_g = 0;
// synopsys translate_on
always @ ( posedge wrclk or posedge aclr)
if (aclr == 1'b1) wrptr_g <= 11'b0;
else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q;
fifo_2k_dffpipe_ab3 rs_brp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(wire_rdptr_g_gray2bin_bin),
.q(wire_rs_brp_q));
fifo_2k_dffpipe_ab3 rs_bwp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(wire_rs_dgwp_gray2bin_bin),
.q(wire_rs_bwp_q));
fifo_2k_alt_synch_pipe_dm2 rs_dgwp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(delayed_wrptr_g),
.q(wire_rs_dgwp_q));
fifo_2k_dffpipe_ab3 ws_brp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_ws_dgrp_gray2bin_bin),
.q(wire_ws_brp_q));
fifo_2k_dffpipe_ab3 ws_bwp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_wrptr_g_gray2bin_bin),
.q(wire_ws_bwp_q));
fifo_2k_alt_synch_pipe_dm2 ws_dgrp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_rdptr_g_q),
.q(wire_ws_dgrp_q));
fifo_2k_add_sub_a18 rdusedw_sub
(
.dataa(wire_rs_bwp_q),
.datab(wire_rs_brp_q),
.result(wire_rdusedw_sub_result));
fifo_2k_add_sub_a18 wrusedw_sub
(
.dataa(wire_ws_bwp_q),
.datab(wire_ws_brp_q),
.result(wire_wrusedw_sub_result));
always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab)
begin
wire_rdempty_eq_comp_aeb_int = 1'b1;
end
else
begin
wire_rdempty_eq_comp_aeb_int = 1'b0;
end
assign
wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
assign
wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab)
begin
wire_wrfull_eq_comp_aeb_int = 1'b1;
end
else
begin
wire_wrfull_eq_comp_aeb_int = 1'b0;
end
assign
wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
assign
wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
assign
int_rdempty = wire_rdempty_eq_comp_aeb,
int_wrfull = wire_wrfull_eq_comp_aeb,
q = wire_fifo_ram_q_b,
rdempty = int_rdempty,
rdusedw = wire_rdusedw_sub_result,
valid_rdreq = rdreq,
valid_wrreq = wrreq,
wrfull = int_wrfull,
wrusedw = wire_wrusedw_sub_result;
endmodule //fifo_2k_dcfifo_0cq
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_2k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [10:0] rdusedw;
output wrfull;
output [10:0] wrusedw;
wire sub_wire0;
wire [10:0] sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire [10:0] sub_wire4;
wire rdempty = sub_wire0;
wire [10:0] wrusedw = sub_wire1[10:0];
wire wrfull = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire [10:0] rdusedw = sub_wire4[10:0];
fifo_2k_dcfifo_0cq fifo_2k_dcfifo_0cq_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
endmodule
|
// megafunction wizard: %FIFO%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_2k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=11 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//a_gray2bin device_family="Cyclone" WIDTH=11 bin gray
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_a_gray2bin_8m4
(
bin,
gray) /* synthesis synthesis_clearbox=1 */;
output [10:0] bin;
input [10:0] gray;
wire xor0;
wire xor1;
wire xor2;
wire xor3;
wire xor4;
wire xor5;
wire xor6;
wire xor7;
wire xor8;
wire xor9;
assign
bin = {gray[10], xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
xor0 = (gray[0] ^ xor1),
xor1 = (gray[1] ^ xor2),
xor2 = (gray[2] ^ xor3),
xor3 = (gray[3] ^ xor4),
xor4 = (gray[4] ^ xor5),
xor5 = (gray[5] ^ xor6),
xor6 = (gray[6] ^ xor7),
xor7 = (gray[7] ^ xor8),
xor8 = (gray[8] ^ xor9),
xor9 = (gray[10] ^ gray[9]);
endmodule //fifo_2k_a_gray2bin_8m4
//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=11 aclr clock cnt_en q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_a_graycounter_726
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [10:0] q;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire [0:0] wire_countera_4cout;
wire [0:0] wire_countera_5cout;
wire [0:0] wire_countera_6cout;
wire [0:0] wire_countera_7cout;
wire [0:0] wire_countera_8cout;
wire [0:0] wire_countera_9cout;
wire [10:0] wire_countera_regout;
wire wire_parity_cout;
wire wire_parity_regout;
wire [10:0] power_modified_counter_values;
wire sclr;
wire updown;
cyclone_lcell countera_0
(
.aclr(aclr),
.cin(wire_parity_cout),
.clk(clock),
.combout(),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(wire_countera_regout[0:0]),
.ena(1'b1),
.regout(wire_countera_regout[0:0]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_0.cin_used = "true",
countera_0.lut_mask = "c6a0",
countera_0.operation_mode = "arithmetic",
countera_0.sum_lutc_input = "cin",
countera_0.synch_mode = "on",
countera_0.lpm_type = "cyclone_lcell";
cyclone_lcell countera_1
(
.aclr(aclr),
.cin(wire_countera_0cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_1cout[0:0]),
.dataa(power_modified_counter_values[0]),
.datab(power_modified_counter_values[1]),
.ena(1'b1),
.regout(wire_countera_regout[1:1]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_1.cin_used = "true",
countera_1.lut_mask = "6c50",
countera_1.operation_mode = "arithmetic",
countera_1.sum_lutc_input = "cin",
countera_1.synch_mode = "on",
countera_1.lpm_type = "cyclone_lcell";
cyclone_lcell countera_2
(
.aclr(aclr),
.cin(wire_countera_1cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_2cout[0:0]),
.dataa(power_modified_counter_values[1]),
.datab(power_modified_counter_values[2]),
.ena(1'b1),
.regout(wire_countera_regout[2:2]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_2.cin_used = "true",
countera_2.lut_mask = "6c50",
countera_2.operation_mode = "arithmetic",
countera_2.sum_lutc_input = "cin",
countera_2.synch_mode = "on",
countera_2.lpm_type = "cyclone_lcell";
cyclone_lcell countera_3
(
.aclr(aclr),
.cin(wire_countera_2cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_3cout[0:0]),
.dataa(power_modified_counter_values[2]),
.datab(power_modified_counter_values[3]),
.ena(1'b1),
.regout(wire_countera_regout[3:3]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_3.cin_used = "true",
countera_3.lut_mask = "6c50",
countera_3.operation_mode = "arithmetic",
countera_3.sum_lutc_input = "cin",
countera_3.synch_mode = "on",
countera_3.lpm_type = "cyclone_lcell";
cyclone_lcell countera_4
(
.aclr(aclr),
.cin(wire_countera_3cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_4cout[0:0]),
.dataa(power_modified_counter_values[3]),
.datab(power_modified_counter_values[4]),
.ena(1'b1),
.regout(wire_countera_regout[4:4]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_4.cin_used = "true",
countera_4.lut_mask = "6c50",
countera_4.operation_mode = "arithmetic",
countera_4.sum_lutc_input = "cin",
countera_4.synch_mode = "on",
countera_4.lpm_type = "cyclone_lcell";
cyclone_lcell countera_5
(
.aclr(aclr),
.cin(wire_countera_4cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_5cout[0:0]),
.dataa(power_modified_counter_values[4]),
.datab(power_modified_counter_values[5]),
.ena(1'b1),
.regout(wire_countera_regout[5:5]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_5.cin_used = "true",
countera_5.lut_mask = "6c50",
countera_5.operation_mode = "arithmetic",
countera_5.sum_lutc_input = "cin",
countera_5.synch_mode = "on",
countera_5.lpm_type = "cyclone_lcell";
cyclone_lcell countera_6
(
.aclr(aclr),
.cin(wire_countera_5cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_6cout[0:0]),
.dataa(power_modified_counter_values[5]),
.datab(power_modified_counter_values[6]),
.ena(1'b1),
.regout(wire_countera_regout[6:6]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_6.cin_used = "true",
countera_6.lut_mask = "6c50",
countera_6.operation_mode = "arithmetic",
countera_6.sum_lutc_input = "cin",
countera_6.synch_mode = "on",
countera_6.lpm_type = "cyclone_lcell";
cyclone_lcell countera_7
(
.aclr(aclr),
.cin(wire_countera_6cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_7cout[0:0]),
.dataa(power_modified_counter_values[6]),
.datab(power_modified_counter_values[7]),
.ena(1'b1),
.regout(wire_countera_regout[7:7]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_7.cin_used = "true",
countera_7.lut_mask = "6c50",
countera_7.operation_mode = "arithmetic",
countera_7.sum_lutc_input = "cin",
countera_7.synch_mode = "on",
countera_7.lpm_type = "cyclone_lcell";
cyclone_lcell countera_8
(
.aclr(aclr),
.cin(wire_countera_7cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_8cout[0:0]),
.dataa(power_modified_counter_values[7]),
.datab(power_modified_counter_values[8]),
.ena(1'b1),
.regout(wire_countera_regout[8:8]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_8.cin_used = "true",
countera_8.lut_mask = "6c50",
countera_8.operation_mode = "arithmetic",
countera_8.sum_lutc_input = "cin",
countera_8.synch_mode = "on",
countera_8.lpm_type = "cyclone_lcell";
cyclone_lcell countera_9
(
.aclr(aclr),
.cin(wire_countera_8cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_9cout[0:0]),
.dataa(power_modified_counter_values[8]),
.datab(power_modified_counter_values[9]),
.ena(1'b1),
.regout(wire_countera_regout[9:9]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_9.cin_used = "true",
countera_9.lut_mask = "6c50",
countera_9.operation_mode = "arithmetic",
countera_9.sum_lutc_input = "cin",
countera_9.synch_mode = "on",
countera_9.lpm_type = "cyclone_lcell";
cyclone_lcell countera_10
(
.aclr(aclr),
.cin(wire_countera_9cout[0:0]),
.clk(clock),
.combout(),
.cout(),
.dataa(power_modified_counter_values[10]),
.ena(1'b1),
.regout(wire_countera_regout[10:10]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datab(1'b1),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_10.cin_used = "true",
countera_10.lut_mask = "5a5a",
countera_10.operation_mode = "normal",
countera_10.sum_lutc_input = "cin",
countera_10.synch_mode = "on",
countera_10.lpm_type = "cyclone_lcell";
cyclone_lcell parity
(
.aclr(aclr),
.cin(updown),
.clk(clock),
.combout(),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab(wire_parity_regout),
.ena(1'b1),
.regout(wire_parity_regout),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
parity.cin_used = "true",
parity.lut_mask = "6682",
parity.operation_mode = "arithmetic",
parity.synch_mode = "on",
parity.lpm_type = "cyclone_lcell";
assign
power_modified_counter_values = {wire_countera_regout[10:0]},
q = power_modified_counter_values,
sclr = 1'b0,
updown = 1'b1;
endmodule //fifo_2k_a_graycounter_726
//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=11 aclr clock cnt_en q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_a_graycounter_2r6
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [10:0] q;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire [0:0] wire_countera_4cout;
wire [0:0] wire_countera_5cout;
wire [0:0] wire_countera_6cout;
wire [0:0] wire_countera_7cout;
wire [0:0] wire_countera_8cout;
wire [0:0] wire_countera_9cout;
wire [10:0] wire_countera_regout;
wire wire_parity_cout;
wire wire_parity_regout;
wire [10:0] power_modified_counter_values;
wire sclr;
wire updown;
cyclone_lcell countera_0
(
.aclr(aclr),
.cin(wire_parity_cout),
.clk(clock),
.combout(),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(wire_countera_regout[0:0]),
.ena(1'b1),
.regout(wire_countera_regout[0:0]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_0.cin_used = "true",
countera_0.lut_mask = "c6a0",
countera_0.operation_mode = "arithmetic",
countera_0.sum_lutc_input = "cin",
countera_0.synch_mode = "on",
countera_0.lpm_type = "cyclone_lcell";
cyclone_lcell countera_1
(
.aclr(aclr),
.cin(wire_countera_0cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_1cout[0:0]),
.dataa(power_modified_counter_values[0]),
.datab(power_modified_counter_values[1]),
.ena(1'b1),
.regout(wire_countera_regout[1:1]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_1.cin_used = "true",
countera_1.lut_mask = "6c50",
countera_1.operation_mode = "arithmetic",
countera_1.sum_lutc_input = "cin",
countera_1.synch_mode = "on",
countera_1.lpm_type = "cyclone_lcell";
cyclone_lcell countera_2
(
.aclr(aclr),
.cin(wire_countera_1cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_2cout[0:0]),
.dataa(power_modified_counter_values[1]),
.datab(power_modified_counter_values[2]),
.ena(1'b1),
.regout(wire_countera_regout[2:2]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_2.cin_used = "true",
countera_2.lut_mask = "6c50",
countera_2.operation_mode = "arithmetic",
countera_2.sum_lutc_input = "cin",
countera_2.synch_mode = "on",
countera_2.lpm_type = "cyclone_lcell";
cyclone_lcell countera_3
(
.aclr(aclr),
.cin(wire_countera_2cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_3cout[0:0]),
.dataa(power_modified_counter_values[2]),
.datab(power_modified_counter_values[3]),
.ena(1'b1),
.regout(wire_countera_regout[3:3]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_3.cin_used = "true",
countera_3.lut_mask = "6c50",
countera_3.operation_mode = "arithmetic",
countera_3.sum_lutc_input = "cin",
countera_3.synch_mode = "on",
countera_3.lpm_type = "cyclone_lcell";
cyclone_lcell countera_4
(
.aclr(aclr),
.cin(wire_countera_3cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_4cout[0:0]),
.dataa(power_modified_counter_values[3]),
.datab(power_modified_counter_values[4]),
.ena(1'b1),
.regout(wire_countera_regout[4:4]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_4.cin_used = "true",
countera_4.lut_mask = "6c50",
countera_4.operation_mode = "arithmetic",
countera_4.sum_lutc_input = "cin",
countera_4.synch_mode = "on",
countera_4.lpm_type = "cyclone_lcell";
cyclone_lcell countera_5
(
.aclr(aclr),
.cin(wire_countera_4cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_5cout[0:0]),
.dataa(power_modified_counter_values[4]),
.datab(power_modified_counter_values[5]),
.ena(1'b1),
.regout(wire_countera_regout[5:5]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_5.cin_used = "true",
countera_5.lut_mask = "6c50",
countera_5.operation_mode = "arithmetic",
countera_5.sum_lutc_input = "cin",
countera_5.synch_mode = "on",
countera_5.lpm_type = "cyclone_lcell";
cyclone_lcell countera_6
(
.aclr(aclr),
.cin(wire_countera_5cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_6cout[0:0]),
.dataa(power_modified_counter_values[5]),
.datab(power_modified_counter_values[6]),
.ena(1'b1),
.regout(wire_countera_regout[6:6]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_6.cin_used = "true",
countera_6.lut_mask = "6c50",
countera_6.operation_mode = "arithmetic",
countera_6.sum_lutc_input = "cin",
countera_6.synch_mode = "on",
countera_6.lpm_type = "cyclone_lcell";
cyclone_lcell countera_7
(
.aclr(aclr),
.cin(wire_countera_6cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_7cout[0:0]),
.dataa(power_modified_counter_values[6]),
.datab(power_modified_counter_values[7]),
.ena(1'b1),
.regout(wire_countera_regout[7:7]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_7.cin_used = "true",
countera_7.lut_mask = "6c50",
countera_7.operation_mode = "arithmetic",
countera_7.sum_lutc_input = "cin",
countera_7.synch_mode = "on",
countera_7.lpm_type = "cyclone_lcell";
cyclone_lcell countera_8
(
.aclr(aclr),
.cin(wire_countera_7cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_8cout[0:0]),
.dataa(power_modified_counter_values[7]),
.datab(power_modified_counter_values[8]),
.ena(1'b1),
.regout(wire_countera_regout[8:8]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_8.cin_used = "true",
countera_8.lut_mask = "6c50",
countera_8.operation_mode = "arithmetic",
countera_8.sum_lutc_input = "cin",
countera_8.synch_mode = "on",
countera_8.lpm_type = "cyclone_lcell";
cyclone_lcell countera_9
(
.aclr(aclr),
.cin(wire_countera_8cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_9cout[0:0]),
.dataa(power_modified_counter_values[8]),
.datab(power_modified_counter_values[9]),
.ena(1'b1),
.regout(wire_countera_regout[9:9]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_9.cin_used = "true",
countera_9.lut_mask = "6c50",
countera_9.operation_mode = "arithmetic",
countera_9.sum_lutc_input = "cin",
countera_9.synch_mode = "on",
countera_9.lpm_type = "cyclone_lcell";
cyclone_lcell countera_10
(
.aclr(aclr),
.cin(wire_countera_9cout[0:0]),
.clk(clock),
.combout(),
.cout(),
.dataa(power_modified_counter_values[10]),
.ena(1'b1),
.regout(wire_countera_regout[10:10]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datab(1'b1),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_10.cin_used = "true",
countera_10.lut_mask = "5a5a",
countera_10.operation_mode = "normal",
countera_10.sum_lutc_input = "cin",
countera_10.synch_mode = "on",
countera_10.lpm_type = "cyclone_lcell";
cyclone_lcell parity
(
.aclr(aclr),
.cin(updown),
.clk(clock),
.combout(),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab((~ wire_parity_regout)),
.ena(1'b1),
.regout(wire_parity_regout),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
parity.cin_used = "true",
parity.lut_mask = "9982",
parity.operation_mode = "arithmetic",
parity.synch_mode = "on",
parity.lpm_type = "cyclone_lcell";
assign
power_modified_counter_values = {wire_countera_regout[10:1], (~ wire_countera_regout[0])},
q = power_modified_counter_values,
sclr = 1'b0,
updown = 1'b1;
endmodule //fifo_2k_a_graycounter_2r6
//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = M4K 8
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_altsyncram_6pl
(
address_a,
address_b,
clock0,
clock1,
clocken1,
data_a,
q_b,
wren_a) /* synthesis synthesis_clearbox=1 */;
input [10:0] address_a;
input [10:0] address_b;
input clock0;
input clock1;
input clocken1;
input [15:0] data_a;
output [15:0] q_b;
input wren_a;
wire [0:0] wire_ram_block3a_0portbdataout;
wire [0:0] wire_ram_block3a_1portbdataout;
wire [0:0] wire_ram_block3a_2portbdataout;
wire [0:0] wire_ram_block3a_3portbdataout;
wire [0:0] wire_ram_block3a_4portbdataout;
wire [0:0] wire_ram_block3a_5portbdataout;
wire [0:0] wire_ram_block3a_6portbdataout;
wire [0:0] wire_ram_block3a_7portbdataout;
wire [0:0] wire_ram_block3a_8portbdataout;
wire [0:0] wire_ram_block3a_9portbdataout;
wire [0:0] wire_ram_block3a_10portbdataout;
wire [0:0] wire_ram_block3a_11portbdataout;
wire [0:0] wire_ram_block3a_12portbdataout;
wire [0:0] wire_ram_block3a_13portbdataout;
wire [0:0] wire_ram_block3a_14portbdataout;
wire [0:0] wire_ram_block3a_15portbdataout;
wire [10:0] address_a_wire;
wire [10:0] address_b_wire;
cyclone_ram_block ram_block3a_0
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[0]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_0portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_0.connectivity_checking = "OFF",
ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
ram_block3a_0.operation_mode = "dual_port",
ram_block3a_0.port_a_address_width = 11,
ram_block3a_0.port_a_data_width = 1,
ram_block3a_0.port_a_first_address = 0,
ram_block3a_0.port_a_first_bit_number = 0,
ram_block3a_0.port_a_last_address = 2047,
ram_block3a_0.port_a_logical_ram_depth = 2048,
ram_block3a_0.port_a_logical_ram_width = 16,
ram_block3a_0.port_b_address_clear = "none",
ram_block3a_0.port_b_address_clock = "clock1",
ram_block3a_0.port_b_address_width = 11,
ram_block3a_0.port_b_data_out_clear = "none",
ram_block3a_0.port_b_data_out_clock = "none",
ram_block3a_0.port_b_data_width = 1,
ram_block3a_0.port_b_first_address = 0,
ram_block3a_0.port_b_first_bit_number = 0,
ram_block3a_0.port_b_last_address = 2047,
ram_block3a_0.port_b_logical_ram_depth = 2048,
ram_block3a_0.port_b_logical_ram_width = 16,
ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_0.ram_block_type = "auto",
ram_block3a_0.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_1
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[1]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_1portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_1.connectivity_checking = "OFF",
ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
ram_block3a_1.operation_mode = "dual_port",
ram_block3a_1.port_a_address_width = 11,
ram_block3a_1.port_a_data_width = 1,
ram_block3a_1.port_a_first_address = 0,
ram_block3a_1.port_a_first_bit_number = 1,
ram_block3a_1.port_a_last_address = 2047,
ram_block3a_1.port_a_logical_ram_depth = 2048,
ram_block3a_1.port_a_logical_ram_width = 16,
ram_block3a_1.port_b_address_clear = "none",
ram_block3a_1.port_b_address_clock = "clock1",
ram_block3a_1.port_b_address_width = 11,
ram_block3a_1.port_b_data_out_clear = "none",
ram_block3a_1.port_b_data_out_clock = "none",
ram_block3a_1.port_b_data_width = 1,
ram_block3a_1.port_b_first_address = 0,
ram_block3a_1.port_b_first_bit_number = 1,
ram_block3a_1.port_b_last_address = 2047,
ram_block3a_1.port_b_logical_ram_depth = 2048,
ram_block3a_1.port_b_logical_ram_width = 16,
ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_1.ram_block_type = "auto",
ram_block3a_1.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_2
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[2]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_2portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_2.connectivity_checking = "OFF",
ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
ram_block3a_2.operation_mode = "dual_port",
ram_block3a_2.port_a_address_width = 11,
ram_block3a_2.port_a_data_width = 1,
ram_block3a_2.port_a_first_address = 0,
ram_block3a_2.port_a_first_bit_number = 2,
ram_block3a_2.port_a_last_address = 2047,
ram_block3a_2.port_a_logical_ram_depth = 2048,
ram_block3a_2.port_a_logical_ram_width = 16,
ram_block3a_2.port_b_address_clear = "none",
ram_block3a_2.port_b_address_clock = "clock1",
ram_block3a_2.port_b_address_width = 11,
ram_block3a_2.port_b_data_out_clear = "none",
ram_block3a_2.port_b_data_out_clock = "none",
ram_block3a_2.port_b_data_width = 1,
ram_block3a_2.port_b_first_address = 0,
ram_block3a_2.port_b_first_bit_number = 2,
ram_block3a_2.port_b_last_address = 2047,
ram_block3a_2.port_b_logical_ram_depth = 2048,
ram_block3a_2.port_b_logical_ram_width = 16,
ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_2.ram_block_type = "auto",
ram_block3a_2.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_3
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[3]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_3portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_3.connectivity_checking = "OFF",
ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
ram_block3a_3.operation_mode = "dual_port",
ram_block3a_3.port_a_address_width = 11,
ram_block3a_3.port_a_data_width = 1,
ram_block3a_3.port_a_first_address = 0,
ram_block3a_3.port_a_first_bit_number = 3,
ram_block3a_3.port_a_last_address = 2047,
ram_block3a_3.port_a_logical_ram_depth = 2048,
ram_block3a_3.port_a_logical_ram_width = 16,
ram_block3a_3.port_b_address_clear = "none",
ram_block3a_3.port_b_address_clock = "clock1",
ram_block3a_3.port_b_address_width = 11,
ram_block3a_3.port_b_data_out_clear = "none",
ram_block3a_3.port_b_data_out_clock = "none",
ram_block3a_3.port_b_data_width = 1,
ram_block3a_3.port_b_first_address = 0,
ram_block3a_3.port_b_first_bit_number = 3,
ram_block3a_3.port_b_last_address = 2047,
ram_block3a_3.port_b_logical_ram_depth = 2048,
ram_block3a_3.port_b_logical_ram_width = 16,
ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_3.ram_block_type = "auto",
ram_block3a_3.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_4
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[4]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_4portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_4.connectivity_checking = "OFF",
ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
ram_block3a_4.operation_mode = "dual_port",
ram_block3a_4.port_a_address_width = 11,
ram_block3a_4.port_a_data_width = 1,
ram_block3a_4.port_a_first_address = 0,
ram_block3a_4.port_a_first_bit_number = 4,
ram_block3a_4.port_a_last_address = 2047,
ram_block3a_4.port_a_logical_ram_depth = 2048,
ram_block3a_4.port_a_logical_ram_width = 16,
ram_block3a_4.port_b_address_clear = "none",
ram_block3a_4.port_b_address_clock = "clock1",
ram_block3a_4.port_b_address_width = 11,
ram_block3a_4.port_b_data_out_clear = "none",
ram_block3a_4.port_b_data_out_clock = "none",
ram_block3a_4.port_b_data_width = 1,
ram_block3a_4.port_b_first_address = 0,
ram_block3a_4.port_b_first_bit_number = 4,
ram_block3a_4.port_b_last_address = 2047,
ram_block3a_4.port_b_logical_ram_depth = 2048,
ram_block3a_4.port_b_logical_ram_width = 16,
ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_4.ram_block_type = "auto",
ram_block3a_4.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_5
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[5]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_5portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_5.connectivity_checking = "OFF",
ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
ram_block3a_5.operation_mode = "dual_port",
ram_block3a_5.port_a_address_width = 11,
ram_block3a_5.port_a_data_width = 1,
ram_block3a_5.port_a_first_address = 0,
ram_block3a_5.port_a_first_bit_number = 5,
ram_block3a_5.port_a_last_address = 2047,
ram_block3a_5.port_a_logical_ram_depth = 2048,
ram_block3a_5.port_a_logical_ram_width = 16,
ram_block3a_5.port_b_address_clear = "none",
ram_block3a_5.port_b_address_clock = "clock1",
ram_block3a_5.port_b_address_width = 11,
ram_block3a_5.port_b_data_out_clear = "none",
ram_block3a_5.port_b_data_out_clock = "none",
ram_block3a_5.port_b_data_width = 1,
ram_block3a_5.port_b_first_address = 0,
ram_block3a_5.port_b_first_bit_number = 5,
ram_block3a_5.port_b_last_address = 2047,
ram_block3a_5.port_b_logical_ram_depth = 2048,
ram_block3a_5.port_b_logical_ram_width = 16,
ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_5.ram_block_type = "auto",
ram_block3a_5.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_6
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[6]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_6portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_6.connectivity_checking = "OFF",
ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
ram_block3a_6.operation_mode = "dual_port",
ram_block3a_6.port_a_address_width = 11,
ram_block3a_6.port_a_data_width = 1,
ram_block3a_6.port_a_first_address = 0,
ram_block3a_6.port_a_first_bit_number = 6,
ram_block3a_6.port_a_last_address = 2047,
ram_block3a_6.port_a_logical_ram_depth = 2048,
ram_block3a_6.port_a_logical_ram_width = 16,
ram_block3a_6.port_b_address_clear = "none",
ram_block3a_6.port_b_address_clock = "clock1",
ram_block3a_6.port_b_address_width = 11,
ram_block3a_6.port_b_data_out_clear = "none",
ram_block3a_6.port_b_data_out_clock = "none",
ram_block3a_6.port_b_data_width = 1,
ram_block3a_6.port_b_first_address = 0,
ram_block3a_6.port_b_first_bit_number = 6,
ram_block3a_6.port_b_last_address = 2047,
ram_block3a_6.port_b_logical_ram_depth = 2048,
ram_block3a_6.port_b_logical_ram_width = 16,
ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_6.ram_block_type = "auto",
ram_block3a_6.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_7
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[7]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_7portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_7.connectivity_checking = "OFF",
ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
ram_block3a_7.operation_mode = "dual_port",
ram_block3a_7.port_a_address_width = 11,
ram_block3a_7.port_a_data_width = 1,
ram_block3a_7.port_a_first_address = 0,
ram_block3a_7.port_a_first_bit_number = 7,
ram_block3a_7.port_a_last_address = 2047,
ram_block3a_7.port_a_logical_ram_depth = 2048,
ram_block3a_7.port_a_logical_ram_width = 16,
ram_block3a_7.port_b_address_clear = "none",
ram_block3a_7.port_b_address_clock = "clock1",
ram_block3a_7.port_b_address_width = 11,
ram_block3a_7.port_b_data_out_clear = "none",
ram_block3a_7.port_b_data_out_clock = "none",
ram_block3a_7.port_b_data_width = 1,
ram_block3a_7.port_b_first_address = 0,
ram_block3a_7.port_b_first_bit_number = 7,
ram_block3a_7.port_b_last_address = 2047,
ram_block3a_7.port_b_logical_ram_depth = 2048,
ram_block3a_7.port_b_logical_ram_width = 16,
ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_7.ram_block_type = "auto",
ram_block3a_7.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_8
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[8]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_8portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_8.connectivity_checking = "OFF",
ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
ram_block3a_8.operation_mode = "dual_port",
ram_block3a_8.port_a_address_width = 11,
ram_block3a_8.port_a_data_width = 1,
ram_block3a_8.port_a_first_address = 0,
ram_block3a_8.port_a_first_bit_number = 8,
ram_block3a_8.port_a_last_address = 2047,
ram_block3a_8.port_a_logical_ram_depth = 2048,
ram_block3a_8.port_a_logical_ram_width = 16,
ram_block3a_8.port_b_address_clear = "none",
ram_block3a_8.port_b_address_clock = "clock1",
ram_block3a_8.port_b_address_width = 11,
ram_block3a_8.port_b_data_out_clear = "none",
ram_block3a_8.port_b_data_out_clock = "none",
ram_block3a_8.port_b_data_width = 1,
ram_block3a_8.port_b_first_address = 0,
ram_block3a_8.port_b_first_bit_number = 8,
ram_block3a_8.port_b_last_address = 2047,
ram_block3a_8.port_b_logical_ram_depth = 2048,
ram_block3a_8.port_b_logical_ram_width = 16,
ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_8.ram_block_type = "auto",
ram_block3a_8.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_9
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[9]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_9portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_9.connectivity_checking = "OFF",
ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
ram_block3a_9.operation_mode = "dual_port",
ram_block3a_9.port_a_address_width = 11,
ram_block3a_9.port_a_data_width = 1,
ram_block3a_9.port_a_first_address = 0,
ram_block3a_9.port_a_first_bit_number = 9,
ram_block3a_9.port_a_last_address = 2047,
ram_block3a_9.port_a_logical_ram_depth = 2048,
ram_block3a_9.port_a_logical_ram_width = 16,
ram_block3a_9.port_b_address_clear = "none",
ram_block3a_9.port_b_address_clock = "clock1",
ram_block3a_9.port_b_address_width = 11,
ram_block3a_9.port_b_data_out_clear = "none",
ram_block3a_9.port_b_data_out_clock = "none",
ram_block3a_9.port_b_data_width = 1,
ram_block3a_9.port_b_first_address = 0,
ram_block3a_9.port_b_first_bit_number = 9,
ram_block3a_9.port_b_last_address = 2047,
ram_block3a_9.port_b_logical_ram_depth = 2048,
ram_block3a_9.port_b_logical_ram_width = 16,
ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_9.ram_block_type = "auto",
ram_block3a_9.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_10
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[10]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_10portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_10.connectivity_checking = "OFF",
ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
ram_block3a_10.operation_mode = "dual_port",
ram_block3a_10.port_a_address_width = 11,
ram_block3a_10.port_a_data_width = 1,
ram_block3a_10.port_a_first_address = 0,
ram_block3a_10.port_a_first_bit_number = 10,
ram_block3a_10.port_a_last_address = 2047,
ram_block3a_10.port_a_logical_ram_depth = 2048,
ram_block3a_10.port_a_logical_ram_width = 16,
ram_block3a_10.port_b_address_clear = "none",
ram_block3a_10.port_b_address_clock = "clock1",
ram_block3a_10.port_b_address_width = 11,
ram_block3a_10.port_b_data_out_clear = "none",
ram_block3a_10.port_b_data_out_clock = "none",
ram_block3a_10.port_b_data_width = 1,
ram_block3a_10.port_b_first_address = 0,
ram_block3a_10.port_b_first_bit_number = 10,
ram_block3a_10.port_b_last_address = 2047,
ram_block3a_10.port_b_logical_ram_depth = 2048,
ram_block3a_10.port_b_logical_ram_width = 16,
ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_10.ram_block_type = "auto",
ram_block3a_10.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_11
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[11]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_11portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_11.connectivity_checking = "OFF",
ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
ram_block3a_11.operation_mode = "dual_port",
ram_block3a_11.port_a_address_width = 11,
ram_block3a_11.port_a_data_width = 1,
ram_block3a_11.port_a_first_address = 0,
ram_block3a_11.port_a_first_bit_number = 11,
ram_block3a_11.port_a_last_address = 2047,
ram_block3a_11.port_a_logical_ram_depth = 2048,
ram_block3a_11.port_a_logical_ram_width = 16,
ram_block3a_11.port_b_address_clear = "none",
ram_block3a_11.port_b_address_clock = "clock1",
ram_block3a_11.port_b_address_width = 11,
ram_block3a_11.port_b_data_out_clear = "none",
ram_block3a_11.port_b_data_out_clock = "none",
ram_block3a_11.port_b_data_width = 1,
ram_block3a_11.port_b_first_address = 0,
ram_block3a_11.port_b_first_bit_number = 11,
ram_block3a_11.port_b_last_address = 2047,
ram_block3a_11.port_b_logical_ram_depth = 2048,
ram_block3a_11.port_b_logical_ram_width = 16,
ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_11.ram_block_type = "auto",
ram_block3a_11.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_12
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[12]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_12portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_12.connectivity_checking = "OFF",
ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
ram_block3a_12.operation_mode = "dual_port",
ram_block3a_12.port_a_address_width = 11,
ram_block3a_12.port_a_data_width = 1,
ram_block3a_12.port_a_first_address = 0,
ram_block3a_12.port_a_first_bit_number = 12,
ram_block3a_12.port_a_last_address = 2047,
ram_block3a_12.port_a_logical_ram_depth = 2048,
ram_block3a_12.port_a_logical_ram_width = 16,
ram_block3a_12.port_b_address_clear = "none",
ram_block3a_12.port_b_address_clock = "clock1",
ram_block3a_12.port_b_address_width = 11,
ram_block3a_12.port_b_data_out_clear = "none",
ram_block3a_12.port_b_data_out_clock = "none",
ram_block3a_12.port_b_data_width = 1,
ram_block3a_12.port_b_first_address = 0,
ram_block3a_12.port_b_first_bit_number = 12,
ram_block3a_12.port_b_last_address = 2047,
ram_block3a_12.port_b_logical_ram_depth = 2048,
ram_block3a_12.port_b_logical_ram_width = 16,
ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_12.ram_block_type = "auto",
ram_block3a_12.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_13
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[13]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_13portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_13.connectivity_checking = "OFF",
ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
ram_block3a_13.operation_mode = "dual_port",
ram_block3a_13.port_a_address_width = 11,
ram_block3a_13.port_a_data_width = 1,
ram_block3a_13.port_a_first_address = 0,
ram_block3a_13.port_a_first_bit_number = 13,
ram_block3a_13.port_a_last_address = 2047,
ram_block3a_13.port_a_logical_ram_depth = 2048,
ram_block3a_13.port_a_logical_ram_width = 16,
ram_block3a_13.port_b_address_clear = "none",
ram_block3a_13.port_b_address_clock = "clock1",
ram_block3a_13.port_b_address_width = 11,
ram_block3a_13.port_b_data_out_clear = "none",
ram_block3a_13.port_b_data_out_clock = "none",
ram_block3a_13.port_b_data_width = 1,
ram_block3a_13.port_b_first_address = 0,
ram_block3a_13.port_b_first_bit_number = 13,
ram_block3a_13.port_b_last_address = 2047,
ram_block3a_13.port_b_logical_ram_depth = 2048,
ram_block3a_13.port_b_logical_ram_width = 16,
ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_13.ram_block_type = "auto",
ram_block3a_13.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_14
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[14]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_14portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_14.connectivity_checking = "OFF",
ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
ram_block3a_14.operation_mode = "dual_port",
ram_block3a_14.port_a_address_width = 11,
ram_block3a_14.port_a_data_width = 1,
ram_block3a_14.port_a_first_address = 0,
ram_block3a_14.port_a_first_bit_number = 14,
ram_block3a_14.port_a_last_address = 2047,
ram_block3a_14.port_a_logical_ram_depth = 2048,
ram_block3a_14.port_a_logical_ram_width = 16,
ram_block3a_14.port_b_address_clear = "none",
ram_block3a_14.port_b_address_clock = "clock1",
ram_block3a_14.port_b_address_width = 11,
ram_block3a_14.port_b_data_out_clear = "none",
ram_block3a_14.port_b_data_out_clock = "none",
ram_block3a_14.port_b_data_width = 1,
ram_block3a_14.port_b_first_address = 0,
ram_block3a_14.port_b_first_bit_number = 14,
ram_block3a_14.port_b_last_address = 2047,
ram_block3a_14.port_b_logical_ram_depth = 2048,
ram_block3a_14.port_b_logical_ram_width = 16,
ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_14.ram_block_type = "auto",
ram_block3a_14.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_15
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[15]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_15portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_15.connectivity_checking = "OFF",
ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
ram_block3a_15.operation_mode = "dual_port",
ram_block3a_15.port_a_address_width = 11,
ram_block3a_15.port_a_data_width = 1,
ram_block3a_15.port_a_first_address = 0,
ram_block3a_15.port_a_first_bit_number = 15,
ram_block3a_15.port_a_last_address = 2047,
ram_block3a_15.port_a_logical_ram_depth = 2048,
ram_block3a_15.port_a_logical_ram_width = 16,
ram_block3a_15.port_b_address_clear = "none",
ram_block3a_15.port_b_address_clock = "clock1",
ram_block3a_15.port_b_address_width = 11,
ram_block3a_15.port_b_data_out_clear = "none",
ram_block3a_15.port_b_data_out_clock = "none",
ram_block3a_15.port_b_data_width = 1,
ram_block3a_15.port_b_first_address = 0,
ram_block3a_15.port_b_first_bit_number = 15,
ram_block3a_15.port_b_last_address = 2047,
ram_block3a_15.port_b_logical_ram_depth = 2048,
ram_block3a_15.port_b_logical_ram_width = 16,
ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_15.ram_block_type = "auto",
ram_block3a_15.lpm_type = "cyclone_ram_block";
assign
address_a_wire = address_a,
address_b_wire = address_b,
q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
endmodule //fifo_2k_altsyncram_6pl
//dffpipe DELAY=1 WIDTH=11 clock clrn d q
//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = lut 11
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_dffpipe_ab3
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [10:0] d;
output [10:0] q;
wire [10:0] wire_dffe4a_D;
reg [10:0] dffe4a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0];
// synopsys translate_off
initial
dffe4a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1];
// synopsys translate_off
initial
dffe4a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2];
// synopsys translate_off
initial
dffe4a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3];
// synopsys translate_off
initial
dffe4a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4];
// synopsys translate_off
initial
dffe4a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5];
// synopsys translate_off
initial
dffe4a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6];
// synopsys translate_off
initial
dffe4a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7];
// synopsys translate_off
initial
dffe4a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8];
// synopsys translate_off
initial
dffe4a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9];
// synopsys translate_off
initial
dffe4a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10];
assign
wire_dffe4a_D = (d & {11{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe4a,
sclr = 1'b0;
endmodule //fifo_2k_dffpipe_ab3
//dffpipe WIDTH=11 clock clrn d q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//dffpipe WIDTH=11 clock clrn d q
//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = lut 11
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_dffpipe_dm2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [10:0] d;
output [10:0] q;
wire [10:0] wire_dffe6a_D;
reg [10:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe6a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0];
// synopsys translate_off
initial
dffe6a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1];
// synopsys translate_off
initial
dffe6a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2];
// synopsys translate_off
initial
dffe6a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3];
// synopsys translate_off
initial
dffe6a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4];
// synopsys translate_off
initial
dffe6a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5];
// synopsys translate_off
initial
dffe6a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6];
// synopsys translate_off
initial
dffe6a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7];
// synopsys translate_off
initial
dffe6a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8];
// synopsys translate_off
initial
dffe6a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9];
// synopsys translate_off
initial
dffe6a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10];
assign
wire_dffe6a_D = (d & {11{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //fifo_2k_dffpipe_dm2
//synthesis_resources = lut 11
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_alt_synch_pipe_dm2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
input clock;
input clrn;
input [10:0] d;
output [10:0] q;
wire [10:0] wire_dffpipe5_q;
fifo_2k_dffpipe_dm2 dffpipe5
(
.clock(clock),
.clrn(clrn),
.d(d),
.q(wire_dffpipe5_q));
assign
q = wire_dffpipe5_q;
endmodule //fifo_2k_alt_synch_pipe_dm2
//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=11 dataa datab result
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 11
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_add_sub_a18
(
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input [10:0] dataa;
input [10:0] datab;
output [10:0] result;
wire [10:0] wire_add_sub_cella_combout;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [0:0] wire_add_sub_cella_7cout;
wire [0:0] wire_add_sub_cella_8cout;
wire [0:0] wire_add_sub_cella_9cout;
wire [10:0] wire_add_sub_cella_dataa;
wire [10:0] wire_add_sub_cella_datab;
cyclone_lcell add_sub_cella_0
(
.cin(1'b1),
.combout(wire_add_sub_cella_combout[0:0]),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "69b2",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_1
(
.cin(wire_add_sub_cella_0cout[0:0]),
.combout(wire_add_sub_cella_combout[1:1]),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "69b2",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_2
(
.cin(wire_add_sub_cella_1cout[0:0]),
.combout(wire_add_sub_cella_combout[2:2]),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "69b2",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_3
(
.cin(wire_add_sub_cella_2cout[0:0]),
.combout(wire_add_sub_cella_combout[3:3]),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "69b2",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_4
(
.cin(wire_add_sub_cella_3cout[0:0]),
.combout(wire_add_sub_cella_combout[4:4]),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "69b2",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_5
(
.cin(wire_add_sub_cella_4cout[0:0]),
.combout(wire_add_sub_cella_combout[5:5]),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "69b2",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_6
(
.cin(wire_add_sub_cella_5cout[0:0]),
.combout(wire_add_sub_cella_combout[6:6]),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "69b2",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_7
(
.cin(wire_add_sub_cella_6cout[0:0]),
.combout(wire_add_sub_cella_combout[7:7]),
.cout(wire_add_sub_cella_7cout[0:0]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "69b2",
add_sub_cella_7.operation_mode = "arithmetic",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_8
(
.cin(wire_add_sub_cella_7cout[0:0]),
.combout(wire_add_sub_cella_combout[8:8]),
.cout(wire_add_sub_cella_8cout[0:0]),
.dataa(wire_add_sub_cella_dataa[8:8]),
.datab(wire_add_sub_cella_datab[8:8]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_8.cin_used = "true",
add_sub_cella_8.lut_mask = "69b2",
add_sub_cella_8.operation_mode = "arithmetic",
add_sub_cella_8.sum_lutc_input = "cin",
add_sub_cella_8.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_9
(
.cin(wire_add_sub_cella_8cout[0:0]),
.combout(wire_add_sub_cella_combout[9:9]),
.cout(wire_add_sub_cella_9cout[0:0]),
.dataa(wire_add_sub_cella_dataa[9:9]),
.datab(wire_add_sub_cella_datab[9:9]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_9.cin_used = "true",
add_sub_cella_9.lut_mask = "69b2",
add_sub_cella_9.operation_mode = "arithmetic",
add_sub_cella_9.sum_lutc_input = "cin",
add_sub_cella_9.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_10
(
.cin(wire_add_sub_cella_9cout[0:0]),
.combout(wire_add_sub_cella_combout[10:10]),
.cout(),
.dataa(wire_add_sub_cella_dataa[10:10]),
.datab(wire_add_sub_cella_datab[10:10]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_10.cin_used = "true",
add_sub_cella_10.lut_mask = "6969",
add_sub_cella_10.operation_mode = "normal",
add_sub_cella_10.sum_lutc_input = "cin",
add_sub_cella_10.lpm_type = "cyclone_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_combout;
endmodule //fifo_2k_add_sub_a18
//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 97 M4K 8
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_dcfifo_0cq
(
aclr,
data,
q,
rdclk,
rdempty,
rdreq,
rdusedw,
wrclk,
wrfull,
wrreq,
wrusedw) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
input aclr;
input [15:0] data;
output [15:0] q;
input rdclk;
output rdempty;
input rdreq;
output [10:0] rdusedw;
input wrclk;
output wrfull;
input wrreq;
output [10:0] wrusedw;
wire [10:0] wire_rdptr_g_gray2bin_bin;
wire [10:0] wire_rs_dgwp_gray2bin_bin;
wire [10:0] wire_wrptr_g_gray2bin_bin;
wire [10:0] wire_ws_dgrp_gray2bin_bin;
wire [10:0] wire_rdptr_g_q;
wire [10:0] wire_rdptr_g1p_q;
wire [10:0] wire_wrptr_g1p_q;
wire [15:0] wire_fifo_ram_q_b;
reg [10:0] delayed_wrptr_g;
reg [10:0] wrptr_g;
wire [10:0] wire_rs_brp_q;
wire [10:0] wire_rs_bwp_q;
wire [10:0] wire_rs_dgwp_q;
wire [10:0] wire_ws_brp_q;
wire [10:0] wire_ws_bwp_q;
wire [10:0] wire_ws_dgrp_q;
wire [10:0] wire_rdusedw_sub_result;
wire [10:0] wire_wrusedw_sub_result;
reg wire_rdempty_eq_comp_aeb_int;
wire wire_rdempty_eq_comp_aeb;
wire [10:0] wire_rdempty_eq_comp_dataa;
wire [10:0] wire_rdempty_eq_comp_datab;
reg wire_wrfull_eq_comp_aeb_int;
wire wire_wrfull_eq_comp_aeb;
wire [10:0] wire_wrfull_eq_comp_dataa;
wire [10:0] wire_wrfull_eq_comp_datab;
wire int_rdempty;
wire int_wrfull;
wire valid_rdreq;
wire valid_wrreq;
fifo_2k_a_gray2bin_8m4 rdptr_g_gray2bin
(
.bin(wire_rdptr_g_gray2bin_bin),
.gray(wire_rdptr_g_q));
fifo_2k_a_gray2bin_8m4 rs_dgwp_gray2bin
(
.bin(wire_rs_dgwp_gray2bin_bin),
.gray(wire_rs_dgwp_q));
fifo_2k_a_gray2bin_8m4 wrptr_g_gray2bin
(
.bin(wire_wrptr_g_gray2bin_bin),
.gray(wrptr_g));
fifo_2k_a_gray2bin_8m4 ws_dgrp_gray2bin
(
.bin(wire_ws_dgrp_gray2bin_bin),
.gray(wire_ws_dgrp_q));
fifo_2k_a_graycounter_726 rdptr_g
(
.aclr(aclr),
.clock(rdclk),
.cnt_en(valid_rdreq),
.q(wire_rdptr_g_q));
fifo_2k_a_graycounter_2r6 rdptr_g1p
(
.aclr(aclr),
.clock(rdclk),
.cnt_en(valid_rdreq),
.q(wire_rdptr_g1p_q));
fifo_2k_a_graycounter_2r6 wrptr_g1p
(
.aclr(aclr),
.clock(wrclk),
.cnt_en(valid_wrreq),
.q(wire_wrptr_g1p_q));
fifo_2k_altsyncram_6pl fifo_ram
(
.address_a(wrptr_g),
.address_b(((wire_rdptr_g_q & {11{int_rdempty}}) | (wire_rdptr_g1p_q & {11{(~ int_rdempty)}}))),
.clock0(wrclk),
.clock1(rdclk),
.clocken1((valid_rdreq | int_rdempty)),
.data_a(data),
.q_b(wire_fifo_ram_q_b),
.wren_a(valid_wrreq));
// synopsys translate_off
initial
delayed_wrptr_g = 0;
// synopsys translate_on
always @ ( posedge wrclk or posedge aclr)
if (aclr == 1'b1) delayed_wrptr_g <= 11'b0;
else delayed_wrptr_g <= wrptr_g;
// synopsys translate_off
initial
wrptr_g = 0;
// synopsys translate_on
always @ ( posedge wrclk or posedge aclr)
if (aclr == 1'b1) wrptr_g <= 11'b0;
else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q;
fifo_2k_dffpipe_ab3 rs_brp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(wire_rdptr_g_gray2bin_bin),
.q(wire_rs_brp_q));
fifo_2k_dffpipe_ab3 rs_bwp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(wire_rs_dgwp_gray2bin_bin),
.q(wire_rs_bwp_q));
fifo_2k_alt_synch_pipe_dm2 rs_dgwp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(delayed_wrptr_g),
.q(wire_rs_dgwp_q));
fifo_2k_dffpipe_ab3 ws_brp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_ws_dgrp_gray2bin_bin),
.q(wire_ws_brp_q));
fifo_2k_dffpipe_ab3 ws_bwp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_wrptr_g_gray2bin_bin),
.q(wire_ws_bwp_q));
fifo_2k_alt_synch_pipe_dm2 ws_dgrp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_rdptr_g_q),
.q(wire_ws_dgrp_q));
fifo_2k_add_sub_a18 rdusedw_sub
(
.dataa(wire_rs_bwp_q),
.datab(wire_rs_brp_q),
.result(wire_rdusedw_sub_result));
fifo_2k_add_sub_a18 wrusedw_sub
(
.dataa(wire_ws_bwp_q),
.datab(wire_ws_brp_q),
.result(wire_wrusedw_sub_result));
always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab)
begin
wire_rdempty_eq_comp_aeb_int = 1'b1;
end
else
begin
wire_rdempty_eq_comp_aeb_int = 1'b0;
end
assign
wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
assign
wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab)
begin
wire_wrfull_eq_comp_aeb_int = 1'b1;
end
else
begin
wire_wrfull_eq_comp_aeb_int = 1'b0;
end
assign
wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
assign
wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
assign
int_rdempty = wire_rdempty_eq_comp_aeb,
int_wrfull = wire_wrfull_eq_comp_aeb,
q = wire_fifo_ram_q_b,
rdempty = int_rdempty,
rdusedw = wire_rdusedw_sub_result,
valid_rdreq = rdreq,
valid_wrreq = wrreq,
wrfull = int_wrfull,
wrusedw = wire_wrusedw_sub_result;
endmodule //fifo_2k_dcfifo_0cq
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_2k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [10:0] rdusedw;
output wrfull;
output [10:0] wrusedw;
wire sub_wire0;
wire [10:0] sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire [10:0] sub_wire4;
wire rdempty = sub_wire0;
wire [10:0] wrusedw = sub_wire1[10:0];
wire wrfull = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire [10:0] rdusedw = sub_wire4[10:0];
fifo_2k_dcfifo_0cq fifo_2k_dcfifo_0cq_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE
|
// megafunction wizard: %FIFO%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_2k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=11 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//a_gray2bin device_family="Cyclone" WIDTH=11 bin gray
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_a_gray2bin_8m4
(
bin,
gray) /* synthesis synthesis_clearbox=1 */;
output [10:0] bin;
input [10:0] gray;
wire xor0;
wire xor1;
wire xor2;
wire xor3;
wire xor4;
wire xor5;
wire xor6;
wire xor7;
wire xor8;
wire xor9;
assign
bin = {gray[10], xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
xor0 = (gray[0] ^ xor1),
xor1 = (gray[1] ^ xor2),
xor2 = (gray[2] ^ xor3),
xor3 = (gray[3] ^ xor4),
xor4 = (gray[4] ^ xor5),
xor5 = (gray[5] ^ xor6),
xor6 = (gray[6] ^ xor7),
xor7 = (gray[7] ^ xor8),
xor8 = (gray[8] ^ xor9),
xor9 = (gray[10] ^ gray[9]);
endmodule //fifo_2k_a_gray2bin_8m4
//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=11 aclr clock cnt_en q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_a_graycounter_726
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [10:0] q;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire [0:0] wire_countera_4cout;
wire [0:0] wire_countera_5cout;
wire [0:0] wire_countera_6cout;
wire [0:0] wire_countera_7cout;
wire [0:0] wire_countera_8cout;
wire [0:0] wire_countera_9cout;
wire [10:0] wire_countera_regout;
wire wire_parity_cout;
wire wire_parity_regout;
wire [10:0] power_modified_counter_values;
wire sclr;
wire updown;
cyclone_lcell countera_0
(
.aclr(aclr),
.cin(wire_parity_cout),
.clk(clock),
.combout(),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(wire_countera_regout[0:0]),
.ena(1'b1),
.regout(wire_countera_regout[0:0]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_0.cin_used = "true",
countera_0.lut_mask = "c6a0",
countera_0.operation_mode = "arithmetic",
countera_0.sum_lutc_input = "cin",
countera_0.synch_mode = "on",
countera_0.lpm_type = "cyclone_lcell";
cyclone_lcell countera_1
(
.aclr(aclr),
.cin(wire_countera_0cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_1cout[0:0]),
.dataa(power_modified_counter_values[0]),
.datab(power_modified_counter_values[1]),
.ena(1'b1),
.regout(wire_countera_regout[1:1]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_1.cin_used = "true",
countera_1.lut_mask = "6c50",
countera_1.operation_mode = "arithmetic",
countera_1.sum_lutc_input = "cin",
countera_1.synch_mode = "on",
countera_1.lpm_type = "cyclone_lcell";
cyclone_lcell countera_2
(
.aclr(aclr),
.cin(wire_countera_1cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_2cout[0:0]),
.dataa(power_modified_counter_values[1]),
.datab(power_modified_counter_values[2]),
.ena(1'b1),
.regout(wire_countera_regout[2:2]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_2.cin_used = "true",
countera_2.lut_mask = "6c50",
countera_2.operation_mode = "arithmetic",
countera_2.sum_lutc_input = "cin",
countera_2.synch_mode = "on",
countera_2.lpm_type = "cyclone_lcell";
cyclone_lcell countera_3
(
.aclr(aclr),
.cin(wire_countera_2cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_3cout[0:0]),
.dataa(power_modified_counter_values[2]),
.datab(power_modified_counter_values[3]),
.ena(1'b1),
.regout(wire_countera_regout[3:3]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_3.cin_used = "true",
countera_3.lut_mask = "6c50",
countera_3.operation_mode = "arithmetic",
countera_3.sum_lutc_input = "cin",
countera_3.synch_mode = "on",
countera_3.lpm_type = "cyclone_lcell";
cyclone_lcell countera_4
(
.aclr(aclr),
.cin(wire_countera_3cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_4cout[0:0]),
.dataa(power_modified_counter_values[3]),
.datab(power_modified_counter_values[4]),
.ena(1'b1),
.regout(wire_countera_regout[4:4]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_4.cin_used = "true",
countera_4.lut_mask = "6c50",
countera_4.operation_mode = "arithmetic",
countera_4.sum_lutc_input = "cin",
countera_4.synch_mode = "on",
countera_4.lpm_type = "cyclone_lcell";
cyclone_lcell countera_5
(
.aclr(aclr),
.cin(wire_countera_4cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_5cout[0:0]),
.dataa(power_modified_counter_values[4]),
.datab(power_modified_counter_values[5]),
.ena(1'b1),
.regout(wire_countera_regout[5:5]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_5.cin_used = "true",
countera_5.lut_mask = "6c50",
countera_5.operation_mode = "arithmetic",
countera_5.sum_lutc_input = "cin",
countera_5.synch_mode = "on",
countera_5.lpm_type = "cyclone_lcell";
cyclone_lcell countera_6
(
.aclr(aclr),
.cin(wire_countera_5cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_6cout[0:0]),
.dataa(power_modified_counter_values[5]),
.datab(power_modified_counter_values[6]),
.ena(1'b1),
.regout(wire_countera_regout[6:6]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_6.cin_used = "true",
countera_6.lut_mask = "6c50",
countera_6.operation_mode = "arithmetic",
countera_6.sum_lutc_input = "cin",
countera_6.synch_mode = "on",
countera_6.lpm_type = "cyclone_lcell";
cyclone_lcell countera_7
(
.aclr(aclr),
.cin(wire_countera_6cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_7cout[0:0]),
.dataa(power_modified_counter_values[6]),
.datab(power_modified_counter_values[7]),
.ena(1'b1),
.regout(wire_countera_regout[7:7]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_7.cin_used = "true",
countera_7.lut_mask = "6c50",
countera_7.operation_mode = "arithmetic",
countera_7.sum_lutc_input = "cin",
countera_7.synch_mode = "on",
countera_7.lpm_type = "cyclone_lcell";
cyclone_lcell countera_8
(
.aclr(aclr),
.cin(wire_countera_7cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_8cout[0:0]),
.dataa(power_modified_counter_values[7]),
.datab(power_modified_counter_values[8]),
.ena(1'b1),
.regout(wire_countera_regout[8:8]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_8.cin_used = "true",
countera_8.lut_mask = "6c50",
countera_8.operation_mode = "arithmetic",
countera_8.sum_lutc_input = "cin",
countera_8.synch_mode = "on",
countera_8.lpm_type = "cyclone_lcell";
cyclone_lcell countera_9
(
.aclr(aclr),
.cin(wire_countera_8cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_9cout[0:0]),
.dataa(power_modified_counter_values[8]),
.datab(power_modified_counter_values[9]),
.ena(1'b1),
.regout(wire_countera_regout[9:9]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_9.cin_used = "true",
countera_9.lut_mask = "6c50",
countera_9.operation_mode = "arithmetic",
countera_9.sum_lutc_input = "cin",
countera_9.synch_mode = "on",
countera_9.lpm_type = "cyclone_lcell";
cyclone_lcell countera_10
(
.aclr(aclr),
.cin(wire_countera_9cout[0:0]),
.clk(clock),
.combout(),
.cout(),
.dataa(power_modified_counter_values[10]),
.ena(1'b1),
.regout(wire_countera_regout[10:10]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datab(1'b1),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_10.cin_used = "true",
countera_10.lut_mask = "5a5a",
countera_10.operation_mode = "normal",
countera_10.sum_lutc_input = "cin",
countera_10.synch_mode = "on",
countera_10.lpm_type = "cyclone_lcell";
cyclone_lcell parity
(
.aclr(aclr),
.cin(updown),
.clk(clock),
.combout(),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab(wire_parity_regout),
.ena(1'b1),
.regout(wire_parity_regout),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
parity.cin_used = "true",
parity.lut_mask = "6682",
parity.operation_mode = "arithmetic",
parity.synch_mode = "on",
parity.lpm_type = "cyclone_lcell";
assign
power_modified_counter_values = {wire_countera_regout[10:0]},
q = power_modified_counter_values,
sclr = 1'b0,
updown = 1'b1;
endmodule //fifo_2k_a_graycounter_726
//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=11 aclr clock cnt_en q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_a_graycounter_2r6
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [10:0] q;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire [0:0] wire_countera_4cout;
wire [0:0] wire_countera_5cout;
wire [0:0] wire_countera_6cout;
wire [0:0] wire_countera_7cout;
wire [0:0] wire_countera_8cout;
wire [0:0] wire_countera_9cout;
wire [10:0] wire_countera_regout;
wire wire_parity_cout;
wire wire_parity_regout;
wire [10:0] power_modified_counter_values;
wire sclr;
wire updown;
cyclone_lcell countera_0
(
.aclr(aclr),
.cin(wire_parity_cout),
.clk(clock),
.combout(),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(wire_countera_regout[0:0]),
.ena(1'b1),
.regout(wire_countera_regout[0:0]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_0.cin_used = "true",
countera_0.lut_mask = "c6a0",
countera_0.operation_mode = "arithmetic",
countera_0.sum_lutc_input = "cin",
countera_0.synch_mode = "on",
countera_0.lpm_type = "cyclone_lcell";
cyclone_lcell countera_1
(
.aclr(aclr),
.cin(wire_countera_0cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_1cout[0:0]),
.dataa(power_modified_counter_values[0]),
.datab(power_modified_counter_values[1]),
.ena(1'b1),
.regout(wire_countera_regout[1:1]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_1.cin_used = "true",
countera_1.lut_mask = "6c50",
countera_1.operation_mode = "arithmetic",
countera_1.sum_lutc_input = "cin",
countera_1.synch_mode = "on",
countera_1.lpm_type = "cyclone_lcell";
cyclone_lcell countera_2
(
.aclr(aclr),
.cin(wire_countera_1cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_2cout[0:0]),
.dataa(power_modified_counter_values[1]),
.datab(power_modified_counter_values[2]),
.ena(1'b1),
.regout(wire_countera_regout[2:2]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_2.cin_used = "true",
countera_2.lut_mask = "6c50",
countera_2.operation_mode = "arithmetic",
countera_2.sum_lutc_input = "cin",
countera_2.synch_mode = "on",
countera_2.lpm_type = "cyclone_lcell";
cyclone_lcell countera_3
(
.aclr(aclr),
.cin(wire_countera_2cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_3cout[0:0]),
.dataa(power_modified_counter_values[2]),
.datab(power_modified_counter_values[3]),
.ena(1'b1),
.regout(wire_countera_regout[3:3]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_3.cin_used = "true",
countera_3.lut_mask = "6c50",
countera_3.operation_mode = "arithmetic",
countera_3.sum_lutc_input = "cin",
countera_3.synch_mode = "on",
countera_3.lpm_type = "cyclone_lcell";
cyclone_lcell countera_4
(
.aclr(aclr),
.cin(wire_countera_3cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_4cout[0:0]),
.dataa(power_modified_counter_values[3]),
.datab(power_modified_counter_values[4]),
.ena(1'b1),
.regout(wire_countera_regout[4:4]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_4.cin_used = "true",
countera_4.lut_mask = "6c50",
countera_4.operation_mode = "arithmetic",
countera_4.sum_lutc_input = "cin",
countera_4.synch_mode = "on",
countera_4.lpm_type = "cyclone_lcell";
cyclone_lcell countera_5
(
.aclr(aclr),
.cin(wire_countera_4cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_5cout[0:0]),
.dataa(power_modified_counter_values[4]),
.datab(power_modified_counter_values[5]),
.ena(1'b1),
.regout(wire_countera_regout[5:5]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_5.cin_used = "true",
countera_5.lut_mask = "6c50",
countera_5.operation_mode = "arithmetic",
countera_5.sum_lutc_input = "cin",
countera_5.synch_mode = "on",
countera_5.lpm_type = "cyclone_lcell";
cyclone_lcell countera_6
(
.aclr(aclr),
.cin(wire_countera_5cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_6cout[0:0]),
.dataa(power_modified_counter_values[5]),
.datab(power_modified_counter_values[6]),
.ena(1'b1),
.regout(wire_countera_regout[6:6]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_6.cin_used = "true",
countera_6.lut_mask = "6c50",
countera_6.operation_mode = "arithmetic",
countera_6.sum_lutc_input = "cin",
countera_6.synch_mode = "on",
countera_6.lpm_type = "cyclone_lcell";
cyclone_lcell countera_7
(
.aclr(aclr),
.cin(wire_countera_6cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_7cout[0:0]),
.dataa(power_modified_counter_values[6]),
.datab(power_modified_counter_values[7]),
.ena(1'b1),
.regout(wire_countera_regout[7:7]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_7.cin_used = "true",
countera_7.lut_mask = "6c50",
countera_7.operation_mode = "arithmetic",
countera_7.sum_lutc_input = "cin",
countera_7.synch_mode = "on",
countera_7.lpm_type = "cyclone_lcell";
cyclone_lcell countera_8
(
.aclr(aclr),
.cin(wire_countera_7cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_8cout[0:0]),
.dataa(power_modified_counter_values[7]),
.datab(power_modified_counter_values[8]),
.ena(1'b1),
.regout(wire_countera_regout[8:8]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_8.cin_used = "true",
countera_8.lut_mask = "6c50",
countera_8.operation_mode = "arithmetic",
countera_8.sum_lutc_input = "cin",
countera_8.synch_mode = "on",
countera_8.lpm_type = "cyclone_lcell";
cyclone_lcell countera_9
(
.aclr(aclr),
.cin(wire_countera_8cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_9cout[0:0]),
.dataa(power_modified_counter_values[8]),
.datab(power_modified_counter_values[9]),
.ena(1'b1),
.regout(wire_countera_regout[9:9]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_9.cin_used = "true",
countera_9.lut_mask = "6c50",
countera_9.operation_mode = "arithmetic",
countera_9.sum_lutc_input = "cin",
countera_9.synch_mode = "on",
countera_9.lpm_type = "cyclone_lcell";
cyclone_lcell countera_10
(
.aclr(aclr),
.cin(wire_countera_9cout[0:0]),
.clk(clock),
.combout(),
.cout(),
.dataa(power_modified_counter_values[10]),
.ena(1'b1),
.regout(wire_countera_regout[10:10]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datab(1'b1),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_10.cin_used = "true",
countera_10.lut_mask = "5a5a",
countera_10.operation_mode = "normal",
countera_10.sum_lutc_input = "cin",
countera_10.synch_mode = "on",
countera_10.lpm_type = "cyclone_lcell";
cyclone_lcell parity
(
.aclr(aclr),
.cin(updown),
.clk(clock),
.combout(),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab((~ wire_parity_regout)),
.ena(1'b1),
.regout(wire_parity_regout),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
parity.cin_used = "true",
parity.lut_mask = "9982",
parity.operation_mode = "arithmetic",
parity.synch_mode = "on",
parity.lpm_type = "cyclone_lcell";
assign
power_modified_counter_values = {wire_countera_regout[10:1], (~ wire_countera_regout[0])},
q = power_modified_counter_values,
sclr = 1'b0,
updown = 1'b1;
endmodule //fifo_2k_a_graycounter_2r6
//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = M4K 8
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_altsyncram_6pl
(
address_a,
address_b,
clock0,
clock1,
clocken1,
data_a,
q_b,
wren_a) /* synthesis synthesis_clearbox=1 */;
input [10:0] address_a;
input [10:0] address_b;
input clock0;
input clock1;
input clocken1;
input [15:0] data_a;
output [15:0] q_b;
input wren_a;
wire [0:0] wire_ram_block3a_0portbdataout;
wire [0:0] wire_ram_block3a_1portbdataout;
wire [0:0] wire_ram_block3a_2portbdataout;
wire [0:0] wire_ram_block3a_3portbdataout;
wire [0:0] wire_ram_block3a_4portbdataout;
wire [0:0] wire_ram_block3a_5portbdataout;
wire [0:0] wire_ram_block3a_6portbdataout;
wire [0:0] wire_ram_block3a_7portbdataout;
wire [0:0] wire_ram_block3a_8portbdataout;
wire [0:0] wire_ram_block3a_9portbdataout;
wire [0:0] wire_ram_block3a_10portbdataout;
wire [0:0] wire_ram_block3a_11portbdataout;
wire [0:0] wire_ram_block3a_12portbdataout;
wire [0:0] wire_ram_block3a_13portbdataout;
wire [0:0] wire_ram_block3a_14portbdataout;
wire [0:0] wire_ram_block3a_15portbdataout;
wire [10:0] address_a_wire;
wire [10:0] address_b_wire;
cyclone_ram_block ram_block3a_0
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[0]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_0portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_0.connectivity_checking = "OFF",
ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
ram_block3a_0.operation_mode = "dual_port",
ram_block3a_0.port_a_address_width = 11,
ram_block3a_0.port_a_data_width = 1,
ram_block3a_0.port_a_first_address = 0,
ram_block3a_0.port_a_first_bit_number = 0,
ram_block3a_0.port_a_last_address = 2047,
ram_block3a_0.port_a_logical_ram_depth = 2048,
ram_block3a_0.port_a_logical_ram_width = 16,
ram_block3a_0.port_b_address_clear = "none",
ram_block3a_0.port_b_address_clock = "clock1",
ram_block3a_0.port_b_address_width = 11,
ram_block3a_0.port_b_data_out_clear = "none",
ram_block3a_0.port_b_data_out_clock = "none",
ram_block3a_0.port_b_data_width = 1,
ram_block3a_0.port_b_first_address = 0,
ram_block3a_0.port_b_first_bit_number = 0,
ram_block3a_0.port_b_last_address = 2047,
ram_block3a_0.port_b_logical_ram_depth = 2048,
ram_block3a_0.port_b_logical_ram_width = 16,
ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_0.ram_block_type = "auto",
ram_block3a_0.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_1
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[1]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_1portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_1.connectivity_checking = "OFF",
ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
ram_block3a_1.operation_mode = "dual_port",
ram_block3a_1.port_a_address_width = 11,
ram_block3a_1.port_a_data_width = 1,
ram_block3a_1.port_a_first_address = 0,
ram_block3a_1.port_a_first_bit_number = 1,
ram_block3a_1.port_a_last_address = 2047,
ram_block3a_1.port_a_logical_ram_depth = 2048,
ram_block3a_1.port_a_logical_ram_width = 16,
ram_block3a_1.port_b_address_clear = "none",
ram_block3a_1.port_b_address_clock = "clock1",
ram_block3a_1.port_b_address_width = 11,
ram_block3a_1.port_b_data_out_clear = "none",
ram_block3a_1.port_b_data_out_clock = "none",
ram_block3a_1.port_b_data_width = 1,
ram_block3a_1.port_b_first_address = 0,
ram_block3a_1.port_b_first_bit_number = 1,
ram_block3a_1.port_b_last_address = 2047,
ram_block3a_1.port_b_logical_ram_depth = 2048,
ram_block3a_1.port_b_logical_ram_width = 16,
ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_1.ram_block_type = "auto",
ram_block3a_1.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_2
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[2]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_2portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_2.connectivity_checking = "OFF",
ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
ram_block3a_2.operation_mode = "dual_port",
ram_block3a_2.port_a_address_width = 11,
ram_block3a_2.port_a_data_width = 1,
ram_block3a_2.port_a_first_address = 0,
ram_block3a_2.port_a_first_bit_number = 2,
ram_block3a_2.port_a_last_address = 2047,
ram_block3a_2.port_a_logical_ram_depth = 2048,
ram_block3a_2.port_a_logical_ram_width = 16,
ram_block3a_2.port_b_address_clear = "none",
ram_block3a_2.port_b_address_clock = "clock1",
ram_block3a_2.port_b_address_width = 11,
ram_block3a_2.port_b_data_out_clear = "none",
ram_block3a_2.port_b_data_out_clock = "none",
ram_block3a_2.port_b_data_width = 1,
ram_block3a_2.port_b_first_address = 0,
ram_block3a_2.port_b_first_bit_number = 2,
ram_block3a_2.port_b_last_address = 2047,
ram_block3a_2.port_b_logical_ram_depth = 2048,
ram_block3a_2.port_b_logical_ram_width = 16,
ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_2.ram_block_type = "auto",
ram_block3a_2.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_3
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[3]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_3portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_3.connectivity_checking = "OFF",
ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
ram_block3a_3.operation_mode = "dual_port",
ram_block3a_3.port_a_address_width = 11,
ram_block3a_3.port_a_data_width = 1,
ram_block3a_3.port_a_first_address = 0,
ram_block3a_3.port_a_first_bit_number = 3,
ram_block3a_3.port_a_last_address = 2047,
ram_block3a_3.port_a_logical_ram_depth = 2048,
ram_block3a_3.port_a_logical_ram_width = 16,
ram_block3a_3.port_b_address_clear = "none",
ram_block3a_3.port_b_address_clock = "clock1",
ram_block3a_3.port_b_address_width = 11,
ram_block3a_3.port_b_data_out_clear = "none",
ram_block3a_3.port_b_data_out_clock = "none",
ram_block3a_3.port_b_data_width = 1,
ram_block3a_3.port_b_first_address = 0,
ram_block3a_3.port_b_first_bit_number = 3,
ram_block3a_3.port_b_last_address = 2047,
ram_block3a_3.port_b_logical_ram_depth = 2048,
ram_block3a_3.port_b_logical_ram_width = 16,
ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_3.ram_block_type = "auto",
ram_block3a_3.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_4
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[4]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_4portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_4.connectivity_checking = "OFF",
ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
ram_block3a_4.operation_mode = "dual_port",
ram_block3a_4.port_a_address_width = 11,
ram_block3a_4.port_a_data_width = 1,
ram_block3a_4.port_a_first_address = 0,
ram_block3a_4.port_a_first_bit_number = 4,
ram_block3a_4.port_a_last_address = 2047,
ram_block3a_4.port_a_logical_ram_depth = 2048,
ram_block3a_4.port_a_logical_ram_width = 16,
ram_block3a_4.port_b_address_clear = "none",
ram_block3a_4.port_b_address_clock = "clock1",
ram_block3a_4.port_b_address_width = 11,
ram_block3a_4.port_b_data_out_clear = "none",
ram_block3a_4.port_b_data_out_clock = "none",
ram_block3a_4.port_b_data_width = 1,
ram_block3a_4.port_b_first_address = 0,
ram_block3a_4.port_b_first_bit_number = 4,
ram_block3a_4.port_b_last_address = 2047,
ram_block3a_4.port_b_logical_ram_depth = 2048,
ram_block3a_4.port_b_logical_ram_width = 16,
ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_4.ram_block_type = "auto",
ram_block3a_4.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_5
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[5]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_5portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_5.connectivity_checking = "OFF",
ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
ram_block3a_5.operation_mode = "dual_port",
ram_block3a_5.port_a_address_width = 11,
ram_block3a_5.port_a_data_width = 1,
ram_block3a_5.port_a_first_address = 0,
ram_block3a_5.port_a_first_bit_number = 5,
ram_block3a_5.port_a_last_address = 2047,
ram_block3a_5.port_a_logical_ram_depth = 2048,
ram_block3a_5.port_a_logical_ram_width = 16,
ram_block3a_5.port_b_address_clear = "none",
ram_block3a_5.port_b_address_clock = "clock1",
ram_block3a_5.port_b_address_width = 11,
ram_block3a_5.port_b_data_out_clear = "none",
ram_block3a_5.port_b_data_out_clock = "none",
ram_block3a_5.port_b_data_width = 1,
ram_block3a_5.port_b_first_address = 0,
ram_block3a_5.port_b_first_bit_number = 5,
ram_block3a_5.port_b_last_address = 2047,
ram_block3a_5.port_b_logical_ram_depth = 2048,
ram_block3a_5.port_b_logical_ram_width = 16,
ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_5.ram_block_type = "auto",
ram_block3a_5.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_6
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[6]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_6portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_6.connectivity_checking = "OFF",
ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
ram_block3a_6.operation_mode = "dual_port",
ram_block3a_6.port_a_address_width = 11,
ram_block3a_6.port_a_data_width = 1,
ram_block3a_6.port_a_first_address = 0,
ram_block3a_6.port_a_first_bit_number = 6,
ram_block3a_6.port_a_last_address = 2047,
ram_block3a_6.port_a_logical_ram_depth = 2048,
ram_block3a_6.port_a_logical_ram_width = 16,
ram_block3a_6.port_b_address_clear = "none",
ram_block3a_6.port_b_address_clock = "clock1",
ram_block3a_6.port_b_address_width = 11,
ram_block3a_6.port_b_data_out_clear = "none",
ram_block3a_6.port_b_data_out_clock = "none",
ram_block3a_6.port_b_data_width = 1,
ram_block3a_6.port_b_first_address = 0,
ram_block3a_6.port_b_first_bit_number = 6,
ram_block3a_6.port_b_last_address = 2047,
ram_block3a_6.port_b_logical_ram_depth = 2048,
ram_block3a_6.port_b_logical_ram_width = 16,
ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_6.ram_block_type = "auto",
ram_block3a_6.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_7
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[7]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_7portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_7.connectivity_checking = "OFF",
ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
ram_block3a_7.operation_mode = "dual_port",
ram_block3a_7.port_a_address_width = 11,
ram_block3a_7.port_a_data_width = 1,
ram_block3a_7.port_a_first_address = 0,
ram_block3a_7.port_a_first_bit_number = 7,
ram_block3a_7.port_a_last_address = 2047,
ram_block3a_7.port_a_logical_ram_depth = 2048,
ram_block3a_7.port_a_logical_ram_width = 16,
ram_block3a_7.port_b_address_clear = "none",
ram_block3a_7.port_b_address_clock = "clock1",
ram_block3a_7.port_b_address_width = 11,
ram_block3a_7.port_b_data_out_clear = "none",
ram_block3a_7.port_b_data_out_clock = "none",
ram_block3a_7.port_b_data_width = 1,
ram_block3a_7.port_b_first_address = 0,
ram_block3a_7.port_b_first_bit_number = 7,
ram_block3a_7.port_b_last_address = 2047,
ram_block3a_7.port_b_logical_ram_depth = 2048,
ram_block3a_7.port_b_logical_ram_width = 16,
ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_7.ram_block_type = "auto",
ram_block3a_7.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_8
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[8]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_8portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_8.connectivity_checking = "OFF",
ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
ram_block3a_8.operation_mode = "dual_port",
ram_block3a_8.port_a_address_width = 11,
ram_block3a_8.port_a_data_width = 1,
ram_block3a_8.port_a_first_address = 0,
ram_block3a_8.port_a_first_bit_number = 8,
ram_block3a_8.port_a_last_address = 2047,
ram_block3a_8.port_a_logical_ram_depth = 2048,
ram_block3a_8.port_a_logical_ram_width = 16,
ram_block3a_8.port_b_address_clear = "none",
ram_block3a_8.port_b_address_clock = "clock1",
ram_block3a_8.port_b_address_width = 11,
ram_block3a_8.port_b_data_out_clear = "none",
ram_block3a_8.port_b_data_out_clock = "none",
ram_block3a_8.port_b_data_width = 1,
ram_block3a_8.port_b_first_address = 0,
ram_block3a_8.port_b_first_bit_number = 8,
ram_block3a_8.port_b_last_address = 2047,
ram_block3a_8.port_b_logical_ram_depth = 2048,
ram_block3a_8.port_b_logical_ram_width = 16,
ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_8.ram_block_type = "auto",
ram_block3a_8.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_9
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[9]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_9portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_9.connectivity_checking = "OFF",
ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
ram_block3a_9.operation_mode = "dual_port",
ram_block3a_9.port_a_address_width = 11,
ram_block3a_9.port_a_data_width = 1,
ram_block3a_9.port_a_first_address = 0,
ram_block3a_9.port_a_first_bit_number = 9,
ram_block3a_9.port_a_last_address = 2047,
ram_block3a_9.port_a_logical_ram_depth = 2048,
ram_block3a_9.port_a_logical_ram_width = 16,
ram_block3a_9.port_b_address_clear = "none",
ram_block3a_9.port_b_address_clock = "clock1",
ram_block3a_9.port_b_address_width = 11,
ram_block3a_9.port_b_data_out_clear = "none",
ram_block3a_9.port_b_data_out_clock = "none",
ram_block3a_9.port_b_data_width = 1,
ram_block3a_9.port_b_first_address = 0,
ram_block3a_9.port_b_first_bit_number = 9,
ram_block3a_9.port_b_last_address = 2047,
ram_block3a_9.port_b_logical_ram_depth = 2048,
ram_block3a_9.port_b_logical_ram_width = 16,
ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_9.ram_block_type = "auto",
ram_block3a_9.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_10
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[10]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_10portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_10.connectivity_checking = "OFF",
ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
ram_block3a_10.operation_mode = "dual_port",
ram_block3a_10.port_a_address_width = 11,
ram_block3a_10.port_a_data_width = 1,
ram_block3a_10.port_a_first_address = 0,
ram_block3a_10.port_a_first_bit_number = 10,
ram_block3a_10.port_a_last_address = 2047,
ram_block3a_10.port_a_logical_ram_depth = 2048,
ram_block3a_10.port_a_logical_ram_width = 16,
ram_block3a_10.port_b_address_clear = "none",
ram_block3a_10.port_b_address_clock = "clock1",
ram_block3a_10.port_b_address_width = 11,
ram_block3a_10.port_b_data_out_clear = "none",
ram_block3a_10.port_b_data_out_clock = "none",
ram_block3a_10.port_b_data_width = 1,
ram_block3a_10.port_b_first_address = 0,
ram_block3a_10.port_b_first_bit_number = 10,
ram_block3a_10.port_b_last_address = 2047,
ram_block3a_10.port_b_logical_ram_depth = 2048,
ram_block3a_10.port_b_logical_ram_width = 16,
ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_10.ram_block_type = "auto",
ram_block3a_10.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_11
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[11]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_11portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_11.connectivity_checking = "OFF",
ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
ram_block3a_11.operation_mode = "dual_port",
ram_block3a_11.port_a_address_width = 11,
ram_block3a_11.port_a_data_width = 1,
ram_block3a_11.port_a_first_address = 0,
ram_block3a_11.port_a_first_bit_number = 11,
ram_block3a_11.port_a_last_address = 2047,
ram_block3a_11.port_a_logical_ram_depth = 2048,
ram_block3a_11.port_a_logical_ram_width = 16,
ram_block3a_11.port_b_address_clear = "none",
ram_block3a_11.port_b_address_clock = "clock1",
ram_block3a_11.port_b_address_width = 11,
ram_block3a_11.port_b_data_out_clear = "none",
ram_block3a_11.port_b_data_out_clock = "none",
ram_block3a_11.port_b_data_width = 1,
ram_block3a_11.port_b_first_address = 0,
ram_block3a_11.port_b_first_bit_number = 11,
ram_block3a_11.port_b_last_address = 2047,
ram_block3a_11.port_b_logical_ram_depth = 2048,
ram_block3a_11.port_b_logical_ram_width = 16,
ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_11.ram_block_type = "auto",
ram_block3a_11.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_12
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[12]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_12portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_12.connectivity_checking = "OFF",
ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
ram_block3a_12.operation_mode = "dual_port",
ram_block3a_12.port_a_address_width = 11,
ram_block3a_12.port_a_data_width = 1,
ram_block3a_12.port_a_first_address = 0,
ram_block3a_12.port_a_first_bit_number = 12,
ram_block3a_12.port_a_last_address = 2047,
ram_block3a_12.port_a_logical_ram_depth = 2048,
ram_block3a_12.port_a_logical_ram_width = 16,
ram_block3a_12.port_b_address_clear = "none",
ram_block3a_12.port_b_address_clock = "clock1",
ram_block3a_12.port_b_address_width = 11,
ram_block3a_12.port_b_data_out_clear = "none",
ram_block3a_12.port_b_data_out_clock = "none",
ram_block3a_12.port_b_data_width = 1,
ram_block3a_12.port_b_first_address = 0,
ram_block3a_12.port_b_first_bit_number = 12,
ram_block3a_12.port_b_last_address = 2047,
ram_block3a_12.port_b_logical_ram_depth = 2048,
ram_block3a_12.port_b_logical_ram_width = 16,
ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_12.ram_block_type = "auto",
ram_block3a_12.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_13
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[13]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_13portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_13.connectivity_checking = "OFF",
ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
ram_block3a_13.operation_mode = "dual_port",
ram_block3a_13.port_a_address_width = 11,
ram_block3a_13.port_a_data_width = 1,
ram_block3a_13.port_a_first_address = 0,
ram_block3a_13.port_a_first_bit_number = 13,
ram_block3a_13.port_a_last_address = 2047,
ram_block3a_13.port_a_logical_ram_depth = 2048,
ram_block3a_13.port_a_logical_ram_width = 16,
ram_block3a_13.port_b_address_clear = "none",
ram_block3a_13.port_b_address_clock = "clock1",
ram_block3a_13.port_b_address_width = 11,
ram_block3a_13.port_b_data_out_clear = "none",
ram_block3a_13.port_b_data_out_clock = "none",
ram_block3a_13.port_b_data_width = 1,
ram_block3a_13.port_b_first_address = 0,
ram_block3a_13.port_b_first_bit_number = 13,
ram_block3a_13.port_b_last_address = 2047,
ram_block3a_13.port_b_logical_ram_depth = 2048,
ram_block3a_13.port_b_logical_ram_width = 16,
ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_13.ram_block_type = "auto",
ram_block3a_13.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_14
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[14]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_14portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_14.connectivity_checking = "OFF",
ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
ram_block3a_14.operation_mode = "dual_port",
ram_block3a_14.port_a_address_width = 11,
ram_block3a_14.port_a_data_width = 1,
ram_block3a_14.port_a_first_address = 0,
ram_block3a_14.port_a_first_bit_number = 14,
ram_block3a_14.port_a_last_address = 2047,
ram_block3a_14.port_a_logical_ram_depth = 2048,
ram_block3a_14.port_a_logical_ram_width = 16,
ram_block3a_14.port_b_address_clear = "none",
ram_block3a_14.port_b_address_clock = "clock1",
ram_block3a_14.port_b_address_width = 11,
ram_block3a_14.port_b_data_out_clear = "none",
ram_block3a_14.port_b_data_out_clock = "none",
ram_block3a_14.port_b_data_width = 1,
ram_block3a_14.port_b_first_address = 0,
ram_block3a_14.port_b_first_bit_number = 14,
ram_block3a_14.port_b_last_address = 2047,
ram_block3a_14.port_b_logical_ram_depth = 2048,
ram_block3a_14.port_b_logical_ram_width = 16,
ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_14.ram_block_type = "auto",
ram_block3a_14.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_15
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[10:0]}),
.portadatain({data_a[15]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[10:0]}),
.portbdataout(wire_ram_block3a_15portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_15.connectivity_checking = "OFF",
ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
ram_block3a_15.operation_mode = "dual_port",
ram_block3a_15.port_a_address_width = 11,
ram_block3a_15.port_a_data_width = 1,
ram_block3a_15.port_a_first_address = 0,
ram_block3a_15.port_a_first_bit_number = 15,
ram_block3a_15.port_a_last_address = 2047,
ram_block3a_15.port_a_logical_ram_depth = 2048,
ram_block3a_15.port_a_logical_ram_width = 16,
ram_block3a_15.port_b_address_clear = "none",
ram_block3a_15.port_b_address_clock = "clock1",
ram_block3a_15.port_b_address_width = 11,
ram_block3a_15.port_b_data_out_clear = "none",
ram_block3a_15.port_b_data_out_clock = "none",
ram_block3a_15.port_b_data_width = 1,
ram_block3a_15.port_b_first_address = 0,
ram_block3a_15.port_b_first_bit_number = 15,
ram_block3a_15.port_b_last_address = 2047,
ram_block3a_15.port_b_logical_ram_depth = 2048,
ram_block3a_15.port_b_logical_ram_width = 16,
ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_15.ram_block_type = "auto",
ram_block3a_15.lpm_type = "cyclone_ram_block";
assign
address_a_wire = address_a,
address_b_wire = address_b,
q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
endmodule //fifo_2k_altsyncram_6pl
//dffpipe DELAY=1 WIDTH=11 clock clrn d q
//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = lut 11
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_dffpipe_ab3
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [10:0] d;
output [10:0] q;
wire [10:0] wire_dffe4a_D;
reg [10:0] dffe4a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0];
// synopsys translate_off
initial
dffe4a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1];
// synopsys translate_off
initial
dffe4a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2];
// synopsys translate_off
initial
dffe4a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3];
// synopsys translate_off
initial
dffe4a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4];
// synopsys translate_off
initial
dffe4a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5];
// synopsys translate_off
initial
dffe4a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6];
// synopsys translate_off
initial
dffe4a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7];
// synopsys translate_off
initial
dffe4a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8];
// synopsys translate_off
initial
dffe4a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9];
// synopsys translate_off
initial
dffe4a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10];
assign
wire_dffe4a_D = (d & {11{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe4a,
sclr = 1'b0;
endmodule //fifo_2k_dffpipe_ab3
//dffpipe WIDTH=11 clock clrn d q
//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//dffpipe WIDTH=11 clock clrn d q
//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
//synthesis_resources = lut 11
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_dffpipe_dm2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [10:0] d;
output [10:0] q;
wire [10:0] wire_dffe6a_D;
reg [10:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe6a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0];
// synopsys translate_off
initial
dffe6a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1];
// synopsys translate_off
initial
dffe6a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2];
// synopsys translate_off
initial
dffe6a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3];
// synopsys translate_off
initial
dffe6a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4];
// synopsys translate_off
initial
dffe6a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5];
// synopsys translate_off
initial
dffe6a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6];
// synopsys translate_off
initial
dffe6a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7];
// synopsys translate_off
initial
dffe6a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8];
// synopsys translate_off
initial
dffe6a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9];
// synopsys translate_off
initial
dffe6a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10];
assign
wire_dffe6a_D = (d & {11{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //fifo_2k_dffpipe_dm2
//synthesis_resources = lut 11
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_alt_synch_pipe_dm2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
input clock;
input clrn;
input [10:0] d;
output [10:0] q;
wire [10:0] wire_dffpipe5_q;
fifo_2k_dffpipe_dm2 dffpipe5
(
.clock(clock),
.clrn(clrn),
.d(d),
.q(wire_dffpipe5_q));
assign
q = wire_dffpipe5_q;
endmodule //fifo_2k_alt_synch_pipe_dm2
//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=11 dataa datab result
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 11
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_add_sub_a18
(
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input [10:0] dataa;
input [10:0] datab;
output [10:0] result;
wire [10:0] wire_add_sub_cella_combout;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [0:0] wire_add_sub_cella_7cout;
wire [0:0] wire_add_sub_cella_8cout;
wire [0:0] wire_add_sub_cella_9cout;
wire [10:0] wire_add_sub_cella_dataa;
wire [10:0] wire_add_sub_cella_datab;
cyclone_lcell add_sub_cella_0
(
.cin(1'b1),
.combout(wire_add_sub_cella_combout[0:0]),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "69b2",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_1
(
.cin(wire_add_sub_cella_0cout[0:0]),
.combout(wire_add_sub_cella_combout[1:1]),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "69b2",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_2
(
.cin(wire_add_sub_cella_1cout[0:0]),
.combout(wire_add_sub_cella_combout[2:2]),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "69b2",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_3
(
.cin(wire_add_sub_cella_2cout[0:0]),
.combout(wire_add_sub_cella_combout[3:3]),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "69b2",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_4
(
.cin(wire_add_sub_cella_3cout[0:0]),
.combout(wire_add_sub_cella_combout[4:4]),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "69b2",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_5
(
.cin(wire_add_sub_cella_4cout[0:0]),
.combout(wire_add_sub_cella_combout[5:5]),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "69b2",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_6
(
.cin(wire_add_sub_cella_5cout[0:0]),
.combout(wire_add_sub_cella_combout[6:6]),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "69b2",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_7
(
.cin(wire_add_sub_cella_6cout[0:0]),
.combout(wire_add_sub_cella_combout[7:7]),
.cout(wire_add_sub_cella_7cout[0:0]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "69b2",
add_sub_cella_7.operation_mode = "arithmetic",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_8
(
.cin(wire_add_sub_cella_7cout[0:0]),
.combout(wire_add_sub_cella_combout[8:8]),
.cout(wire_add_sub_cella_8cout[0:0]),
.dataa(wire_add_sub_cella_dataa[8:8]),
.datab(wire_add_sub_cella_datab[8:8]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_8.cin_used = "true",
add_sub_cella_8.lut_mask = "69b2",
add_sub_cella_8.operation_mode = "arithmetic",
add_sub_cella_8.sum_lutc_input = "cin",
add_sub_cella_8.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_9
(
.cin(wire_add_sub_cella_8cout[0:0]),
.combout(wire_add_sub_cella_combout[9:9]),
.cout(wire_add_sub_cella_9cout[0:0]),
.dataa(wire_add_sub_cella_dataa[9:9]),
.datab(wire_add_sub_cella_datab[9:9]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_9.cin_used = "true",
add_sub_cella_9.lut_mask = "69b2",
add_sub_cella_9.operation_mode = "arithmetic",
add_sub_cella_9.sum_lutc_input = "cin",
add_sub_cella_9.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_10
(
.cin(wire_add_sub_cella_9cout[0:0]),
.combout(wire_add_sub_cella_combout[10:10]),
.cout(),
.dataa(wire_add_sub_cella_dataa[10:10]),
.datab(wire_add_sub_cella_datab[10:10]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_10.cin_used = "true",
add_sub_cella_10.lut_mask = "6969",
add_sub_cella_10.operation_mode = "normal",
add_sub_cella_10.sum_lutc_input = "cin",
add_sub_cella_10.lpm_type = "cyclone_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_combout;
endmodule //fifo_2k_add_sub_a18
//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab
//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = lut 97 M4K 8
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fifo_2k_dcfifo_0cq
(
aclr,
data,
q,
rdclk,
rdempty,
rdreq,
rdusedw,
wrclk,
wrfull,
wrreq,
wrusedw) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
input aclr;
input [15:0] data;
output [15:0] q;
input rdclk;
output rdempty;
input rdreq;
output [10:0] rdusedw;
input wrclk;
output wrfull;
input wrreq;
output [10:0] wrusedw;
wire [10:0] wire_rdptr_g_gray2bin_bin;
wire [10:0] wire_rs_dgwp_gray2bin_bin;
wire [10:0] wire_wrptr_g_gray2bin_bin;
wire [10:0] wire_ws_dgrp_gray2bin_bin;
wire [10:0] wire_rdptr_g_q;
wire [10:0] wire_rdptr_g1p_q;
wire [10:0] wire_wrptr_g1p_q;
wire [15:0] wire_fifo_ram_q_b;
reg [10:0] delayed_wrptr_g;
reg [10:0] wrptr_g;
wire [10:0] wire_rs_brp_q;
wire [10:0] wire_rs_bwp_q;
wire [10:0] wire_rs_dgwp_q;
wire [10:0] wire_ws_brp_q;
wire [10:0] wire_ws_bwp_q;
wire [10:0] wire_ws_dgrp_q;
wire [10:0] wire_rdusedw_sub_result;
wire [10:0] wire_wrusedw_sub_result;
reg wire_rdempty_eq_comp_aeb_int;
wire wire_rdempty_eq_comp_aeb;
wire [10:0] wire_rdempty_eq_comp_dataa;
wire [10:0] wire_rdempty_eq_comp_datab;
reg wire_wrfull_eq_comp_aeb_int;
wire wire_wrfull_eq_comp_aeb;
wire [10:0] wire_wrfull_eq_comp_dataa;
wire [10:0] wire_wrfull_eq_comp_datab;
wire int_rdempty;
wire int_wrfull;
wire valid_rdreq;
wire valid_wrreq;
fifo_2k_a_gray2bin_8m4 rdptr_g_gray2bin
(
.bin(wire_rdptr_g_gray2bin_bin),
.gray(wire_rdptr_g_q));
fifo_2k_a_gray2bin_8m4 rs_dgwp_gray2bin
(
.bin(wire_rs_dgwp_gray2bin_bin),
.gray(wire_rs_dgwp_q));
fifo_2k_a_gray2bin_8m4 wrptr_g_gray2bin
(
.bin(wire_wrptr_g_gray2bin_bin),
.gray(wrptr_g));
fifo_2k_a_gray2bin_8m4 ws_dgrp_gray2bin
(
.bin(wire_ws_dgrp_gray2bin_bin),
.gray(wire_ws_dgrp_q));
fifo_2k_a_graycounter_726 rdptr_g
(
.aclr(aclr),
.clock(rdclk),
.cnt_en(valid_rdreq),
.q(wire_rdptr_g_q));
fifo_2k_a_graycounter_2r6 rdptr_g1p
(
.aclr(aclr),
.clock(rdclk),
.cnt_en(valid_rdreq),
.q(wire_rdptr_g1p_q));
fifo_2k_a_graycounter_2r6 wrptr_g1p
(
.aclr(aclr),
.clock(wrclk),
.cnt_en(valid_wrreq),
.q(wire_wrptr_g1p_q));
fifo_2k_altsyncram_6pl fifo_ram
(
.address_a(wrptr_g),
.address_b(((wire_rdptr_g_q & {11{int_rdempty}}) | (wire_rdptr_g1p_q & {11{(~ int_rdempty)}}))),
.clock0(wrclk),
.clock1(rdclk),
.clocken1((valid_rdreq | int_rdempty)),
.data_a(data),
.q_b(wire_fifo_ram_q_b),
.wren_a(valid_wrreq));
// synopsys translate_off
initial
delayed_wrptr_g = 0;
// synopsys translate_on
always @ ( posedge wrclk or posedge aclr)
if (aclr == 1'b1) delayed_wrptr_g <= 11'b0;
else delayed_wrptr_g <= wrptr_g;
// synopsys translate_off
initial
wrptr_g = 0;
// synopsys translate_on
always @ ( posedge wrclk or posedge aclr)
if (aclr == 1'b1) wrptr_g <= 11'b0;
else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q;
fifo_2k_dffpipe_ab3 rs_brp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(wire_rdptr_g_gray2bin_bin),
.q(wire_rs_brp_q));
fifo_2k_dffpipe_ab3 rs_bwp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(wire_rs_dgwp_gray2bin_bin),
.q(wire_rs_bwp_q));
fifo_2k_alt_synch_pipe_dm2 rs_dgwp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(delayed_wrptr_g),
.q(wire_rs_dgwp_q));
fifo_2k_dffpipe_ab3 ws_brp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_ws_dgrp_gray2bin_bin),
.q(wire_ws_brp_q));
fifo_2k_dffpipe_ab3 ws_bwp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_wrptr_g_gray2bin_bin),
.q(wire_ws_bwp_q));
fifo_2k_alt_synch_pipe_dm2 ws_dgrp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_rdptr_g_q),
.q(wire_ws_dgrp_q));
fifo_2k_add_sub_a18 rdusedw_sub
(
.dataa(wire_rs_bwp_q),
.datab(wire_rs_brp_q),
.result(wire_rdusedw_sub_result));
fifo_2k_add_sub_a18 wrusedw_sub
(
.dataa(wire_ws_bwp_q),
.datab(wire_ws_brp_q),
.result(wire_wrusedw_sub_result));
always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab)
begin
wire_rdempty_eq_comp_aeb_int = 1'b1;
end
else
begin
wire_rdempty_eq_comp_aeb_int = 1'b0;
end
assign
wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
assign
wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab)
begin
wire_wrfull_eq_comp_aeb_int = 1'b1;
end
else
begin
wire_wrfull_eq_comp_aeb_int = 1'b0;
end
assign
wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
assign
wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
assign
int_rdempty = wire_rdempty_eq_comp_aeb,
int_wrfull = wire_wrfull_eq_comp_aeb,
q = wire_fifo_ram_q_b,
rdempty = int_rdempty,
rdusedw = wire_rdusedw_sub_result,
valid_rdreq = rdreq,
valid_wrreq = wrreq,
wrfull = int_wrfull,
wrusedw = wire_wrusedw_sub_result;
endmodule //fifo_2k_dcfifo_0cq
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_2k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [10:0] rdusedw;
output wrfull;
output [10:0] wrusedw;
wire sub_wire0;
wire [10:0] sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire [10:0] sub_wire4;
wire rdempty = sub_wire0;
wire [10:0] wrusedw = sub_wire1[10:0];
wire wrfull = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire [10:0] rdusedw = sub_wire4[10:0];
fifo_2k_dcfifo_0cq fifo_2k_dcfifo_0cq_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
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|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2016/02/08 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2016/02/08 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2016/02/08 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2016/02/08 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_mc_phy_wrapper.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Oct 10 2010
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Wrapper file that encompasses the MC_PHY module
// instantiation and handles the vector remapping between
// the MC_PHY ports and the user's DDR3 ports. Vector
// remapping affects DDR3 control, address, and DQ/DQS/DM.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_mc_phy_wrapper #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter tCK = 2500, // ps
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter BANK_WIDTH = 3, // # of bank address
parameter CKE_WIDTH = 1, // # of clock enable outputs
parameter CS_WIDTH = 1, // # of chip select
parameter CK_WIDTH = 1, // # of CK
parameter CWL = 5, // CAS Write latency
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of data mask
parameter DQ_WIDTH = 16, // # of data bits
parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of strobe pairs
parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3)
parameter RANKS = 4, // # of ranks
parameter ODT_WIDTH = 1, // # of ODT outputs
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter REG_CTRL = "OFF", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // # of row/column address
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
parameter LP_DDR_CK_WIDTH = 2,
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// Parameters calculated outside of this block
parameter HIGHEST_BANK = 3, // Highest I/O bank index
parameter HIGHEST_LANE = 12, // Highest byte lane index
// ** Pin mapping parameters
// Parameters for mapping between hard PHY and physical DDR3 signals
// There are 2 classes of parameters:
// - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of
// 8-bit elements. Each element indicates the bank and byte lane
// location of that particular signal. The bit lane in this case
// doesn't need to be specified, either because there's only one
// pin pair in each byte lane that the DQS or CK pair can be
// located at, or in the case of CKE_ODT_BYTE_MAP, only the byte
// lane needs to be specified in order to determine which byte
// lane generates the RCLK (Note that CKE, and ODT must be located
// in the same bank, thus only one element in CKE_ODT_BYTE_MAP)
// [7:4] = bank # (0-4)
// [3:0] = byte lane # (0-3)
// - All other MAP parameters: These consist of 12-bit elements. Each
// element indicates the bank, byte lane, and bit lane location of
// that particular signal:
// [11:8] = bank # (0-4)
// [7:4] = byte lane # (0-3)
// [3:0] = bit lane # (0-11)
// Note that not all elements in all parameters will be used - it
// depends on the actual widths of the DDR3 buses. The parameters are
// structured to support a maximum of:
// - DQS groups: 18
// - data mask bits: 18
// In addition, the default parameter size of some of the parameters will
// support a certain number of bits, however, this can be expanded at
// compile time by expanding the width of the vector passed into this
// parameter
// - chip selects: 10
// - bank bits: 3
// - address bits: 16
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
// DATAx_MAP parameter is used for byte lane X in the design
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
// MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9]
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// Simulation options
parameter SIM_CAL_OPTION = "NONE",
// The PHY_CONTROL primitive in the bank where PLL exists is declared
// as the Master PHY_CONTROL.
parameter MASTER_PHY_CTL = 1,
parameter DRAM_WIDTH = 8
)
(
input rst,
input iddr_rst,
input clk,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input mmcm_ps_clk,
input idelayctrl_refclk,
input phy_cmd_wr_en,
input phy_data_wr_en,
input [31:0] phy_ctl_wd,
input phy_ctl_wr,
input phy_if_empty_def,
input phy_if_reset,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
output [4:0] idelaye2_init_val,
output [5:0] oclkdelay_init_val,
output if_empty,
output phy_ctl_full,
output phy_cmd_full,
output phy_data_full,
output phy_pre_data_a_full,
output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
output phy_mc_go,
input phy_write_calib,
input phy_read_calib,
input calib_in_common,
input [5:0] calib_sel,
input [DQS_CNT_WIDTH:0] byte_sel_cnt,
input [DRAM_WIDTH-1:0] fine_delay_incdec_pb,
input fine_delay_sel,
input [HIGHEST_BANK-1:0] calib_zero_inputs,
input [HIGHEST_BANK-1:0] calib_zero_ctrl,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
output [8:0] po_counter_read_val,
output [5:0] pi_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input [5:0] pi_counter_load_val,
input idelay_ce,
input idelay_inc,
input idelay_ld,
input idle,
output pi_phase_locked,
output pi_phase_locked_all,
output pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_out_of_range,
// From/to calibration logic/soft PHY
input phy_init_data_sel,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank,
input [nCK_PER_CLK-1:0] mux_cas_n,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n,
input [nCK_PER_CLK-1:0] mux_ras_n,
input [1:0] mux_odt,
input [nCK_PER_CLK-1:0] mux_cke,
input [nCK_PER_CLK-1:0] mux_we_n,
input [nCK_PER_CLK-1:0] parity_in,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask,
input mux_reset_n,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Memory I/F
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_parity,
output ddr_ras_n,
output ddr_we_n,
output ddr_reset_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
//output iodelay_ctrl_rdy,
output pd_out
,input dbg_pi_counter_read_en
,output ref_dll_lock
,input rst_phaser_ref
,output [11:0] dbg_pi_phase_locked_phy4lanes
,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes
);
function [71:0] generate_bytelanes_ddr_ck;
input [143:0] ck_byte_map;
integer v ;
begin
generate_bytelanes_ddr_ck = 'b0 ;
for (v = 0; v < CK_WIDTH; v = v + 1) begin
if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2)
generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1)
generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else
generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
end
end
endfunction
function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map;
input [143:0] ck_byte_map;
integer g;
begin
generate_ddr_ck_map = 'b0 ;
for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin
generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" :
(ck_byte_map[(g*8)+:4] == 4'd1) ? "B" :
(ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ;
generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" :
(ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location
end
end
endfunction
// Enable low power mode for input buffer
localparam IBUF_LOW_PWR
= (IBUF_LPWR_MODE == "OFF") ? "FALSE" :
((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL");
// Ratio of data to strobe
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
// number of data phases per internal clock
localparam PHASE_PER_CLK = 2*nCK_PER_CLK;
// used to determine routing to OUT_FIFO for control/address for 2:1
// vs. 4:1 memory:internal clock ratio modes
localparam PHASE_DIV = 4 / nCK_PER_CLK;
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
// Create an aggregate parameters for data mapping to reduce # of generate
// statements required in remapping code. Need to account for the case
// when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP
// parameter will have fewer than 8 elements used
localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0],
DATA16_MAP[12*DQ_PER_DQS-1:0],
DATA15_MAP[12*DQ_PER_DQS-1:0],
DATA14_MAP[12*DQ_PER_DQS-1:0],
DATA13_MAP[12*DQ_PER_DQS-1:0],
DATA12_MAP[12*DQ_PER_DQS-1:0],
DATA11_MAP[12*DQ_PER_DQS-1:0],
DATA10_MAP[12*DQ_PER_DQS-1:0],
DATA9_MAP[12*DQ_PER_DQS-1:0],
DATA8_MAP[12*DQ_PER_DQS-1:0],
DATA7_MAP[12*DQ_PER_DQS-1:0],
DATA6_MAP[12*DQ_PER_DQS-1:0],
DATA5_MAP[12*DQ_PER_DQS-1:0],
DATA4_MAP[12*DQ_PER_DQS-1:0],
DATA3_MAP[12*DQ_PER_DQS-1:0],
DATA2_MAP[12*DQ_PER_DQS-1:0],
DATA1_MAP[12*DQ_PER_DQS-1:0],
DATA0_MAP[12*DQ_PER_DQS-1:0]};
// Same deal, but for data mask mapping
localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP};
localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ;
localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ;
// Temporary parameters to determine which bank is outputting the CK/CK#
// Eventually there will be support for multiple CK/CK# output
//localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]);
//// Temporary method to force MC_PHY to generate ODDR associated with
//// CK/CK# output only for a single byte lane in the design. All banks
//// that won't be generating the CK/CK# will have "UNUSED" as their
//// PHY_GENERATE_DDR_CK parameter
//localparam TMP_PHY_0_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_1_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_2_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
// Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx
// which indicates which bit lanes in data byte lanes are
// output-only bitlanes (e.g. used specifically for data mask outputs)
function [143:0] calc_phy_bitlanes_outonly;
input [215:0] data_mask_in;
integer z;
begin
calc_phy_bitlanes_outonly = 'b0;
// Only enable BITLANES parameters for data masks if, well, if
// the data masks are actually enabled
if (USE_DM_PORT == 1)
for (z = 0; z < DM_WIDTH; z = z + 1)
calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] +
12*data_mask_in[(12*z+4)+:2] +
data_mask_in[12*z+:4]] = 1'b1;
end
endfunction
localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP);
localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0];
localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48];
localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96];
// Determine which bank and byte lane generates the RCLK used to clock
// out the auxilliary (ODT, CKE) outputs
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON
= (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON
= (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF
= (CKE_MAP[11:8] == 4'h0) ? 0 :
((CKE_MAP[11:8] == 4'h1) ? 1 :
((CKE_MAP[11:8] == 4'h2) ? 2 :
((CKE_MAP[11:8] == 4'h3) ? 3 :
((CKE_MAP[11:8] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF
= (CKE_MAP[7:4] == 4'h0) ? "A" :
((CKE_MAP[7:4] == 4'h1) ? "B" :
((CKE_MAP[7:4] == 4'h2) ? "C" :
((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ;
localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ;
//***************************************************************************
// OCLKDELAYED tap setting calculation:
// Parameters for calculating amount of phase shifting output clock to
// achieve 90 degree offset between DQS and DQ on writes
//***************************************************************************
//90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz
// and 1.25 for Mem_RefClk > 300 MHz
localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE";
//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400,
//DIV4: MemRefClk < 200 MHz
localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" :
tCK > 2500 ? "DIV2": "NONE";
localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 :
PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
// Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output
localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK;
// Whether OCLK_DELAY output comes inverted or not
localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0);
// Phaser-Out Stage3 Tap delay for 90 deg shift.
// Maximum tap delay is FreqRefClk period distributed over 64 taps
// localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV;
localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) -
(INT_DELAY + HALF_CYCLE_DELAY))
* 63 * FREQ_REF_DIV;
//localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY;
localparam integer PHY_0_A_PO_OCLK_DELAY_HW
= (tCK > 2273) ? 34 :
(tCK > 2000) ? 33 :
(tCK > 1724) ? 32 :
(tCK > 1515) ? 31 :
(tCK > 1315) ? 30 :
(tCK > 1136) ? 29 :
(tCK > 1021) ? 28 : 27;
// Note that simulation requires a different value than in H/W because of the
// difference in the way delays are modeled
localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ?
((tCK > 2500) ? 8 :
(DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) :
MC_OCLK_DELAY;
// Initial DQ IDELAY value
localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 :
(tCK < 1000) ? 0 :
(tCK < 1330) ? 0 :
(tCK < 2300) ? 0 :
(tCK < 2500) ? 2 : 0;
//localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0;
// Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3?
localparam PHY_0_RD_CMD_OFFSET_0 = 10;
localparam PHY_0_RD_CMD_OFFSET_1 = 10;
localparam PHY_0_RD_CMD_OFFSET_2 = 10;
localparam PHY_0_RD_CMD_OFFSET_3 = 10;
// 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing
localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4;
// 4:1 and 2:1 have different values
localparam PHY_0_WR_DURATION_0 = 7;
localparam PHY_0_WR_DURATION_1 = 7;
localparam PHY_0_WR_DURATION_2 = 7;
localparam PHY_0_WR_DURATION_3 = 7;
// Aux_out parameters for toggle mode (CKE)
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 :
(CWL < 7) ?
4 + ((CWL_M % 2) ? 0 : 1) :
5 + ((CWL_M % 2) ? 0 : 1);
// temporary parameter to enable/disable PHY PC counters. In both 4:1 and
// 2:1 cases, this should be disabled. For now, enable for 4:1 mode to
// avoid making too many changes at once.
localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE";
wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out;
wire [HIGHEST_LANE-1:0] mem_dqs_in;
wire [HIGHEST_LANE-1:0] mem_dqs_out;
wire [HIGHEST_LANE-1:0] mem_dqs_ts;
wire [HIGHEST_LANE*10-1:0] mem_dq_in;
wire [HIGHEST_LANE*12-1:0] mem_dq_out;
wire [HIGHEST_LANE*12-1:0] mem_dq_ts;
wire [DQ_WIDTH-1:0] in_dq;
wire [DQS_WIDTH-1:0] in_dqs;
wire [ROW_WIDTH-1:0] out_addr;
wire [BANK_WIDTH-1:0] out_ba;
wire out_cas_n;
wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n;
wire [DM_WIDTH-1:0] out_dm;
wire [ODT_WIDTH -1:0] out_odt;
wire [CKE_WIDTH -1 :0] out_cke ;
wire [DQ_WIDTH-1:0] out_dq;
wire [DQS_WIDTH-1:0] out_dqs;
wire out_parity;
wire out_ras_n;
wire out_we_n;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire phy_rd_en;
wire [DM_WIDTH-1:0] ts_dm;
wire [DQ_WIDTH-1:0] ts_dq;
wire [DQS_WIDTH-1:0] ts_dqs;
wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr;
wire [DQS_WIDTH-1:0] pd_out_pre;
//wire metaQ;
reg [31:0] phy_ctl_wd_i1;
reg [31:0] phy_ctl_wd_i2;
reg phy_ctl_wr_i1;
reg phy_ctl_wr_i2;
reg [5:0] data_offset_1_i1;
reg [5:0] data_offset_1_i2;
reg [5:0] data_offset_2_i1;
reg [5:0] data_offset_2_i2;
wire [31:0] phy_ctl_wd_temp;
wire phy_ctl_wr_temp;
wire [5:0] data_offset_1_temp;
wire [5:0] data_offset_2_temp;
wire [5:0] data_offset_1_of;
wire [5:0] data_offset_2_of;
wire [31:0] phy_ctl_wd_of;
wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */;
wire [3:0] phy_ctl_full_temp;
wire data_io_idle_pwrdwn;
reg [29:0] fine_delay_mod; //3 bit per DQ
reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb
(* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1;
// Always read from input data FIFOs when not empty
assign phy_rd_en = !if_empty;
// IDELAYE2 initial value
assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE;
assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY;
// Idle powerdown when there are no pending reads in the MC
assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0;
//***************************************************************************
// Auxiliary output steering
//***************************************************************************
// For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be
// mapped to ddr_odt and the aux_out[7:4] from one of the data banks
// will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the
// addr/ctl bank would bank would map to both ddr_odt and ddr_cke.
generate
if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins
if (CKE_WIDTH == 1) begin : gen_cke
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_cke_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke)
);
end else begin: gen_2rank_cke
OBUF u_cke0_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke[0])
);
OBUF u_cke1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_cke[1])
);
end
end
endgenerate
generate
if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins
if (USE_ODT_PORT == 1) begin : gen_use_odt
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_odt_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]),
.O (ddr_odt[0])
);
if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
OBUF u_odt2_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[2])
);
end
end else begin
assign ddr_odt = 'b0;
end
end
endgenerate
//***************************************************************************
// Read data bit steering
//***************************************************************************
// Transpose elements of rd_data_map to form final read data output:
// phy_din elements are grouped according to "physical bit" - e.g.
// for nCK_PER_CLK = 4, there are 8 data phases transfered per physical
// bit per clock cycle:
// = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2,
// dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0}
// whereas rd_data is are grouped according to "phase" - e.g.
// = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0,
// dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0}
// therefore rd_data is formed by transposing phy_din - e.g.
// for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY
// bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then
// the assignments for bits of rd_data corresponding to DQ[1:0]
// would be:
// {rd_data[112], rd_data[96], rd_data[80], rd_data[64],
// rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0]
// {rd_data[113], rd_data[97], rd_data[81], rd_data[65],
// rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8]
generate
genvar i, j;
for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1
for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2
assign rd_data[DQ_WIDTH*j + i]
= phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+
80*FULL_DATA_MAP[(12*i+4)+:2] +
8*FULL_DATA_MAP[12*i+:4]) + j];
end
end
endgenerate
//generage idelay_inc per bits
reg [11:0] cal_tmp;
reg [95:0] byte_sel_data_map;
assign byte_sel_cnt_w1 = byte_sel_cnt;
always @ (posedge clk) begin
byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96];
end
always @ (posedge clk) begin
fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00};
fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00};
fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00};
fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00};
fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00};
fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00};
fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00};
fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00};
fine_delay_sel_r <= #TCQ fine_delay_sel;
end
//***************************************************************************
// Control/address
//***************************************************************************
assign out_cas_n
= mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]];
generate
// if signal placed on bit lanes [0-9]
if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10
// Determine routing based on clock ratio mode. If running in 4:1
// mode, then all four bits from logic are used. If 2:1 mode, only
// 2-bits are provided by logic, and each bit is repeated 2x to form
// 4-bit input to IN_FIFO, e.g.
// 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]}
// 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]}
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*CAS_MAP[3:0])+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end else begin: gen_cas_ge10
// If signal is placed in bit lane [10] or [11], route to upper
// nibble of phy_dout lane [5] or [6] respectively (in this case
// phy_dout lane [5, 6] are multiplexed to take input for two
// different SDR signals - this is how bits[10,11] need to be
// provided to the OUT_FIFO
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*(CAS_MAP[3:0]-5) + 4)+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end
endgenerate
assign out_ras_n
= mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]];
generate
if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*RAS_MAP[3:0])+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end else begin: gen_ras_ge10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*(RAS_MAP[3:0]-5) + 4)+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end
endgenerate
assign out_we_n
= mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]];
generate
if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*WE_MAP[3:0])+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end else begin: gen_we_ge10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*(WE_MAP[3:0]-5) + 4)+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end
endgenerate
generate
if (REG_CTRL == "ON") begin: gen_parity_out
// Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs
assign out_parity
= mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] +
PARITY_MAP[3:0]];
if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*PARITY_MAP[3:0])+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end else begin: gen_ge10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*(PARITY_MAP[3:0]-5) + 4)+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end
end
endgenerate
//*****************************************************************
generate
genvar m, n,x;
//*****************************************************************
// Control/address (multi-bit) buses
//*****************************************************************
// Row/Column address
for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out
assign out_addr[m]
= mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] +
12*ADDR_MAP[(12*m+4)+:2] +
ADDR_MAP[12*m+:4]];
if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10
// For multi-bit buses, we also have to deal with transposition
// when going from the logic-side control bus to phy_dout
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*ADDR_MAP[12*m+:4] + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*(ADDR_MAP[12*m+:4]-5) + 4 + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Bank address
for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out
assign out_ba[m]
= mem_dq_out[48*BANK_MAP[(12*m+8)+:3] +
12*BANK_MAP[(12*m+4)+:2] +
BANK_MAP[12*m+:4]];
if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*BANK_MAP[12*m+:4] + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*(BANK_MAP[12*m+:4]-5) + 4 + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Chip select
if (USE_CS_PORT == 1) begin: gen_cs_n_out
for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out
assign out_cs_n[m]
= mem_dq_out[48*CS_MAP[(12*m+8)+:3] +
12*CS_MAP[(12*m+4)+:2] +
CS_MAP[12*m+:4]];
if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*CS_MAP[12*m+:4] + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*(CS_MAP[12*m+:4]-5) + 4 + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end
end
end
if(CKE_ODT_AUX == "FALSE") begin
// ODT_ports
wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ;
if(RANKS == 1) begin
for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin
assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ;
end
end else begin
for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin
assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ;
assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ;
end
end
if (USE_ODT_PORT == 1) begin: gen_odt_out
for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1
assign out_odt[m]
= mem_dq_out[48*ODT_MAP[(12*m+8)+:3] +
12*ODT_MAP[(12*m+4)+:2] +
ODT_MAP[12*m+:4]];
if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*ODT_MAP[12*m+:4] + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*(ODT_MAP[12*m+:4]-5) + 4 + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ;
for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin
assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ;
end
for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out
assign out_cke[m]
= mem_dq_out[48*CKE_MAP[(12*m+8)+:3] +
12*CKE_MAP[(12*m+4)+:2] +
CKE_MAP[12*m+:4]];
if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*CKE_MAP[12*m+:4] + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*(CKE_MAP[12*m+:4]-5) + 4 + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
//*****************************************************************
// Data mask
//*****************************************************************
if (USE_DM_PORT == 1) begin: gen_dm_out
for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out
assign out_dm[m]
= mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
assign ts_dm[m]
= mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] +
80*FULL_MASK_MAP[(12*m+4)+:2] +
8*FULL_MASK_MAP[12*m+:4] + n]
= mux_wrdata_mask[DM_WIDTH*n + m];
end
end
end
//*****************************************************************
// Input and output DQ
//*****************************************************************
for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout
// to MC_PHY
assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] +
10*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]]
= in_dq[m];
// to I/O buffers
assign out_dq[m]
= mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
assign ts_dq[m]
= mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] +
80*FULL_DATA_MAP[(12*m+4)+:2] +
8*FULL_DATA_MAP[12*m+:4] + n]
= mux_wrdata[DQ_WIDTH*n + m];
end
end
//*****************************************************************
// Input and output DQS
//*****************************************************************
for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout
// to MC_PHY
assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]
= in_dqs[m];
// to I/O buffers
assign out_dqs[m]
= mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
assign ts_dqs[m]
= mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
end
endgenerate
assign pd_out = pd_out_pre[byte_sel_cnt_w1];
//***************************************************************************
// Memory I/F output and I/O buffer instantiation
//***************************************************************************
// Note on instantiation - generally at the minimum, it's not required to
// instantiate the output buffers - they can be inferred by the synthesis
// tool, and there aren't any attributes that need to be associated with
// them. Consider as a future option to take out the OBUF instantiations
OBUF u_cas_n_obuf
(
.I (out_cas_n),
.O (ddr_cas_n)
);
OBUF u_ras_n_obuf
(
.I (out_ras_n),
.O (ddr_ras_n)
);
OBUF u_we_n_obuf
(
.I (out_we_n),
.O (ddr_we_n)
);
generate
genvar p;
for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf
OBUF u_addr_obuf
(
.I (out_addr[p]),
.O (ddr_addr[p])
);
end
for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf
OBUF u_bank_obuf
(
.I (out_ba[p]),
.O (ddr_ba[p])
);
end
if (USE_CS_PORT == 1) begin: gen_cs_n_obuf
for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf
OBUF u_cs_n_obuf
(
.I (out_cs_n[p]),
.O (ddr_cs_n[p])
);
end
end
if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo
if (USE_ODT_PORT== 1) begin: gen_odt_obuf
for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf
OBUF u_cs_n_obuf
(
.I (out_odt[p]),
.O (ddr_odt[p])
);
end
end
for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf
OBUF u_cs_n_obuf
(
.I (out_cke[p]),
.O (ddr_cke[p])
);
end
end
if (REG_CTRL == "ON") begin: gen_parity_obuf
// Generate addr/ctrl parity output only for DDR3 registered DIMMs
OBUF u_parity_obuf
(
.I (out_parity),
.O (ddr_parity)
);
end else begin: gen_parity_tieoff
assign ddr_parity = 1'b0;
end
if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf
// Generate reset output only for DDR3 and DDR2 RDIMMs
OBUF u_reset_obuf
(
.I (mux_reset_n),
.O (ddr_reset_n)
);
end else begin: gen_reset_tieoff
assign ddr_reset_n = 1'b1;
end
if (USE_DM_PORT == 1) begin: gen_dm_obuf
for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm
OBUFT u_dm_obuf
(
.I (out_dm[p]),
.T (ts_dm[p]),
.O (ddr_dm[p])
);
end
end else begin: gen_dm_tieoff
assign ddr_dm = 'b0;
end
if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else begin: gen_dq_iobuf_default
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end
//if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP
if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff
IOBUFDS_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v2_3_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
//end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR
end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff
IOBUFDS_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
//.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v2_3_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
end else begin: gen_dqs_iobuf_default
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end
end
end
endgenerate
always @(posedge clk) begin
phy_ctl_wd_i1 <= #TCQ phy_ctl_wd;
phy_ctl_wr_i1 <= #TCQ phy_ctl_wr;
phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1;
phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1;
data_offset_1_i1 <= #TCQ data_offset_1;
data_offset_1_i2 <= #TCQ data_offset_1_i1;
data_offset_2_i1 <= #TCQ data_offset_2;
data_offset_2_i2 <= #TCQ data_offset_2_i1;
end
// 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it.
// 2:1 mode the command goes through pre fifo
assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of;
assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of;
assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of;
assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of;
generate
begin
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (32)
)
phy_ctl_pre_fifo_0
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[1]),
.wr_en_in (phy_ctl_wr),
.d_in (phy_ctl_wd),
.wr_en_out (phy_ctl_wr_of),
.d_out (phy_ctl_wd_of)
);
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_1
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[2]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_1),
.wr_en_out (),
.d_out (data_offset_1_of)
);
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_2
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[3]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_2),
.wr_en_out (),
.d_out (data_offset_2_of)
);
end
endgenerate
//***************************************************************************
// Hard PHY instantiation
//***************************************************************************
assign phy_ctl_full = phy_ctl_full_temp[0];
mig_7series_v2_3_ddr_mc_phy #
(
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK),
.RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE),
//.CKE_ODT_AUX (CKE_ODT_AUX),
.GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP),
.BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK),
.NUM_DDR_CK (CK_WIDTH),
.LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
.PO_CTL_COARSE_BYPASS ("FALSE"),
.PHYCTL_CMD_FIFO ("FALSE"),
.PHY_CLK_RATIO (nCK_PER_CLK),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.PHY_FOUR_WINDOW_CLOCKS (63),
.PHY_EVENTS_DELAY (18),
.PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN
.PHY_SYNC_MODE ("FALSE"),
.SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"),
.PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE"
.PHY_0_GENERATE_IDELAYCTRL ("FALSE"),
.PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE
.PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PHY_0_RD_DURATION_0 (6),
.PHY_0_RD_DURATION_1 (6),
.PHY_0_RD_DURATION_2 (6),
.PHY_0_RD_DURATION_3 (6),
.PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5),
.PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV),
.PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK),
//.PHY_1_NUM_DDR_CK (1),
.PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK),
//.PHY_2_NUM_DDR_CK (1),
.PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.TCK (tCK),
.PHY_0_IODELAY_GRP (IODELAY_GRP),
.PHY_1_IODELAY_GRP (IODELAY_GRP),
.PHY_2_IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_mc_phy
(
.rst (rst),
// Don't use MC_PHY to generate DDR_RESET_N output. Instead
// generate this output outside of MC_PHY (and synchronous to CLK)
.ddr_rst_in_n (1'b1),
.phy_clk (clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
// Remove later - always same connection as phy_clk port
.mem_refclk_div4 (clk),
.pll_lock (pll_lock),
.auxout_clk (),
.sync_pulse (sync_pulse),
// IDELAYCTRL instantiated outside of mc_phy module
.idelayctrl_refclk (),
.phy_dout (phy_dout),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phy_ctl_wd (phy_ctl_wd_temp),
.phy_ctl_wr (phy_ctl_wr_temp),
.if_empty_def (phy_if_empty_def),
.if_rst (phy_if_reset),
.phyGo ('b1),
.aux_in_1 (aux_in_1),
.aux_in_2 (aux_in_2),
// No support yet for different data offsets for different I/O banks
// (possible use in supporting wider range of skew among bytes)
.data_offset_1 (data_offset_1_temp),
.data_offset_2 (data_offset_2_temp),
.cke_in (),
.if_a_empty (),
.if_empty (if_empty),
.if_empty_or (),
.if_empty_and (),
.of_ctl_a_full (),
// .of_data_a_full (phy_data_full),
.of_ctl_full (phy_cmd_full),
.of_data_full (),
.pre_data_a_full (phy_pre_data_a_full),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.input_sink (),
.phy_din (phy_din),
.phy_ctl_a_full (),
.phy_ctl_full (phy_ctl_full_temp),
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.mem_dqs_in (mem_dqs_in),
.aux_out (aux_out),
.phy_ctl_ready (),
.rst_out (),
.ddr_clk (ddr_clk),
//.rclk (),
.mcGo (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.calib_zero_lanes ('b0),
.po_fine_enable (po_fine_enable),
.po_coarse_enable (po_coarse_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (),
.po_fine_overflow (),
.po_counter_read_val (po_counter_read_val),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (dbg_pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (),
.pi_counter_read_val (pi_counter_read_val),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (),
.pi_dqs_found_any (pi_dqs_found),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
// Currently not being used. May be used in future if periodic
// reads become a requirement. This output could be used to signal
// a catastrophic failure in read capture and the need for
// re-calibration.
.pi_dqs_out_of_range (pi_dqs_out_of_range)
,.ref_dll_lock (ref_dll_lock)
,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes)
,.fine_delay (fine_delay_mod)
,.fine_delay_sel (fine_delay_sel_r)
// ,.rst_phaser_ref (rst_phaser_ref)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_mc_phy_wrapper.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Oct 10 2010
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Wrapper file that encompasses the MC_PHY module
// instantiation and handles the vector remapping between
// the MC_PHY ports and the user's DDR3 ports. Vector
// remapping affects DDR3 control, address, and DQ/DQS/DM.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_mc_phy_wrapper #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter tCK = 2500, // ps
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter BANK_WIDTH = 3, // # of bank address
parameter CKE_WIDTH = 1, // # of clock enable outputs
parameter CS_WIDTH = 1, // # of chip select
parameter CK_WIDTH = 1, // # of CK
parameter CWL = 5, // CAS Write latency
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of data mask
parameter DQ_WIDTH = 16, // # of data bits
parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of strobe pairs
parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3)
parameter RANKS = 4, // # of ranks
parameter ODT_WIDTH = 1, // # of ODT outputs
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter REG_CTRL = "OFF", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // # of row/column address
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
parameter LP_DDR_CK_WIDTH = 2,
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// Parameters calculated outside of this block
parameter HIGHEST_BANK = 3, // Highest I/O bank index
parameter HIGHEST_LANE = 12, // Highest byte lane index
// ** Pin mapping parameters
// Parameters for mapping between hard PHY and physical DDR3 signals
// There are 2 classes of parameters:
// - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of
// 8-bit elements. Each element indicates the bank and byte lane
// location of that particular signal. The bit lane in this case
// doesn't need to be specified, either because there's only one
// pin pair in each byte lane that the DQS or CK pair can be
// located at, or in the case of CKE_ODT_BYTE_MAP, only the byte
// lane needs to be specified in order to determine which byte
// lane generates the RCLK (Note that CKE, and ODT must be located
// in the same bank, thus only one element in CKE_ODT_BYTE_MAP)
// [7:4] = bank # (0-4)
// [3:0] = byte lane # (0-3)
// - All other MAP parameters: These consist of 12-bit elements. Each
// element indicates the bank, byte lane, and bit lane location of
// that particular signal:
// [11:8] = bank # (0-4)
// [7:4] = byte lane # (0-3)
// [3:0] = bit lane # (0-11)
// Note that not all elements in all parameters will be used - it
// depends on the actual widths of the DDR3 buses. The parameters are
// structured to support a maximum of:
// - DQS groups: 18
// - data mask bits: 18
// In addition, the default parameter size of some of the parameters will
// support a certain number of bits, however, this can be expanded at
// compile time by expanding the width of the vector passed into this
// parameter
// - chip selects: 10
// - bank bits: 3
// - address bits: 16
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
// DATAx_MAP parameter is used for byte lane X in the design
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
// MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9]
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// Simulation options
parameter SIM_CAL_OPTION = "NONE",
// The PHY_CONTROL primitive in the bank where PLL exists is declared
// as the Master PHY_CONTROL.
parameter MASTER_PHY_CTL = 1,
parameter DRAM_WIDTH = 8
)
(
input rst,
input iddr_rst,
input clk,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input mmcm_ps_clk,
input idelayctrl_refclk,
input phy_cmd_wr_en,
input phy_data_wr_en,
input [31:0] phy_ctl_wd,
input phy_ctl_wr,
input phy_if_empty_def,
input phy_if_reset,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
output [4:0] idelaye2_init_val,
output [5:0] oclkdelay_init_val,
output if_empty,
output phy_ctl_full,
output phy_cmd_full,
output phy_data_full,
output phy_pre_data_a_full,
output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
output phy_mc_go,
input phy_write_calib,
input phy_read_calib,
input calib_in_common,
input [5:0] calib_sel,
input [DQS_CNT_WIDTH:0] byte_sel_cnt,
input [DRAM_WIDTH-1:0] fine_delay_incdec_pb,
input fine_delay_sel,
input [HIGHEST_BANK-1:0] calib_zero_inputs,
input [HIGHEST_BANK-1:0] calib_zero_ctrl,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
output [8:0] po_counter_read_val,
output [5:0] pi_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input [5:0] pi_counter_load_val,
input idelay_ce,
input idelay_inc,
input idelay_ld,
input idle,
output pi_phase_locked,
output pi_phase_locked_all,
output pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_out_of_range,
// From/to calibration logic/soft PHY
input phy_init_data_sel,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank,
input [nCK_PER_CLK-1:0] mux_cas_n,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n,
input [nCK_PER_CLK-1:0] mux_ras_n,
input [1:0] mux_odt,
input [nCK_PER_CLK-1:0] mux_cke,
input [nCK_PER_CLK-1:0] mux_we_n,
input [nCK_PER_CLK-1:0] parity_in,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask,
input mux_reset_n,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Memory I/F
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_parity,
output ddr_ras_n,
output ddr_we_n,
output ddr_reset_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
//output iodelay_ctrl_rdy,
output pd_out
,input dbg_pi_counter_read_en
,output ref_dll_lock
,input rst_phaser_ref
,output [11:0] dbg_pi_phase_locked_phy4lanes
,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes
);
function [71:0] generate_bytelanes_ddr_ck;
input [143:0] ck_byte_map;
integer v ;
begin
generate_bytelanes_ddr_ck = 'b0 ;
for (v = 0; v < CK_WIDTH; v = v + 1) begin
if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2)
generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1)
generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else
generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
end
end
endfunction
function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map;
input [143:0] ck_byte_map;
integer g;
begin
generate_ddr_ck_map = 'b0 ;
for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin
generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" :
(ck_byte_map[(g*8)+:4] == 4'd1) ? "B" :
(ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ;
generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" :
(ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location
end
end
endfunction
// Enable low power mode for input buffer
localparam IBUF_LOW_PWR
= (IBUF_LPWR_MODE == "OFF") ? "FALSE" :
((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL");
// Ratio of data to strobe
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
// number of data phases per internal clock
localparam PHASE_PER_CLK = 2*nCK_PER_CLK;
// used to determine routing to OUT_FIFO for control/address for 2:1
// vs. 4:1 memory:internal clock ratio modes
localparam PHASE_DIV = 4 / nCK_PER_CLK;
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
// Create an aggregate parameters for data mapping to reduce # of generate
// statements required in remapping code. Need to account for the case
// when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP
// parameter will have fewer than 8 elements used
localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0],
DATA16_MAP[12*DQ_PER_DQS-1:0],
DATA15_MAP[12*DQ_PER_DQS-1:0],
DATA14_MAP[12*DQ_PER_DQS-1:0],
DATA13_MAP[12*DQ_PER_DQS-1:0],
DATA12_MAP[12*DQ_PER_DQS-1:0],
DATA11_MAP[12*DQ_PER_DQS-1:0],
DATA10_MAP[12*DQ_PER_DQS-1:0],
DATA9_MAP[12*DQ_PER_DQS-1:0],
DATA8_MAP[12*DQ_PER_DQS-1:0],
DATA7_MAP[12*DQ_PER_DQS-1:0],
DATA6_MAP[12*DQ_PER_DQS-1:0],
DATA5_MAP[12*DQ_PER_DQS-1:0],
DATA4_MAP[12*DQ_PER_DQS-1:0],
DATA3_MAP[12*DQ_PER_DQS-1:0],
DATA2_MAP[12*DQ_PER_DQS-1:0],
DATA1_MAP[12*DQ_PER_DQS-1:0],
DATA0_MAP[12*DQ_PER_DQS-1:0]};
// Same deal, but for data mask mapping
localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP};
localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ;
localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ;
// Temporary parameters to determine which bank is outputting the CK/CK#
// Eventually there will be support for multiple CK/CK# output
//localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]);
//// Temporary method to force MC_PHY to generate ODDR associated with
//// CK/CK# output only for a single byte lane in the design. All banks
//// that won't be generating the CK/CK# will have "UNUSED" as their
//// PHY_GENERATE_DDR_CK parameter
//localparam TMP_PHY_0_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_1_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_2_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
// Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx
// which indicates which bit lanes in data byte lanes are
// output-only bitlanes (e.g. used specifically for data mask outputs)
function [143:0] calc_phy_bitlanes_outonly;
input [215:0] data_mask_in;
integer z;
begin
calc_phy_bitlanes_outonly = 'b0;
// Only enable BITLANES parameters for data masks if, well, if
// the data masks are actually enabled
if (USE_DM_PORT == 1)
for (z = 0; z < DM_WIDTH; z = z + 1)
calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] +
12*data_mask_in[(12*z+4)+:2] +
data_mask_in[12*z+:4]] = 1'b1;
end
endfunction
localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP);
localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0];
localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48];
localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96];
// Determine which bank and byte lane generates the RCLK used to clock
// out the auxilliary (ODT, CKE) outputs
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON
= (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON
= (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF
= (CKE_MAP[11:8] == 4'h0) ? 0 :
((CKE_MAP[11:8] == 4'h1) ? 1 :
((CKE_MAP[11:8] == 4'h2) ? 2 :
((CKE_MAP[11:8] == 4'h3) ? 3 :
((CKE_MAP[11:8] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF
= (CKE_MAP[7:4] == 4'h0) ? "A" :
((CKE_MAP[7:4] == 4'h1) ? "B" :
((CKE_MAP[7:4] == 4'h2) ? "C" :
((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ;
localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ;
//***************************************************************************
// OCLKDELAYED tap setting calculation:
// Parameters for calculating amount of phase shifting output clock to
// achieve 90 degree offset between DQS and DQ on writes
//***************************************************************************
//90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz
// and 1.25 for Mem_RefClk > 300 MHz
localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE";
//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400,
//DIV4: MemRefClk < 200 MHz
localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" :
tCK > 2500 ? "DIV2": "NONE";
localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 :
PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
// Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output
localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK;
// Whether OCLK_DELAY output comes inverted or not
localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0);
// Phaser-Out Stage3 Tap delay for 90 deg shift.
// Maximum tap delay is FreqRefClk period distributed over 64 taps
// localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV;
localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) -
(INT_DELAY + HALF_CYCLE_DELAY))
* 63 * FREQ_REF_DIV;
//localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY;
localparam integer PHY_0_A_PO_OCLK_DELAY_HW
= (tCK > 2273) ? 34 :
(tCK > 2000) ? 33 :
(tCK > 1724) ? 32 :
(tCK > 1515) ? 31 :
(tCK > 1315) ? 30 :
(tCK > 1136) ? 29 :
(tCK > 1021) ? 28 : 27;
// Note that simulation requires a different value than in H/W because of the
// difference in the way delays are modeled
localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ?
((tCK > 2500) ? 8 :
(DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) :
MC_OCLK_DELAY;
// Initial DQ IDELAY value
localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 :
(tCK < 1000) ? 0 :
(tCK < 1330) ? 0 :
(tCK < 2300) ? 0 :
(tCK < 2500) ? 2 : 0;
//localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0;
// Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3?
localparam PHY_0_RD_CMD_OFFSET_0 = 10;
localparam PHY_0_RD_CMD_OFFSET_1 = 10;
localparam PHY_0_RD_CMD_OFFSET_2 = 10;
localparam PHY_0_RD_CMD_OFFSET_3 = 10;
// 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing
localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4;
// 4:1 and 2:1 have different values
localparam PHY_0_WR_DURATION_0 = 7;
localparam PHY_0_WR_DURATION_1 = 7;
localparam PHY_0_WR_DURATION_2 = 7;
localparam PHY_0_WR_DURATION_3 = 7;
// Aux_out parameters for toggle mode (CKE)
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 :
(CWL < 7) ?
4 + ((CWL_M % 2) ? 0 : 1) :
5 + ((CWL_M % 2) ? 0 : 1);
// temporary parameter to enable/disable PHY PC counters. In both 4:1 and
// 2:1 cases, this should be disabled. For now, enable for 4:1 mode to
// avoid making too many changes at once.
localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE";
wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out;
wire [HIGHEST_LANE-1:0] mem_dqs_in;
wire [HIGHEST_LANE-1:0] mem_dqs_out;
wire [HIGHEST_LANE-1:0] mem_dqs_ts;
wire [HIGHEST_LANE*10-1:0] mem_dq_in;
wire [HIGHEST_LANE*12-1:0] mem_dq_out;
wire [HIGHEST_LANE*12-1:0] mem_dq_ts;
wire [DQ_WIDTH-1:0] in_dq;
wire [DQS_WIDTH-1:0] in_dqs;
wire [ROW_WIDTH-1:0] out_addr;
wire [BANK_WIDTH-1:0] out_ba;
wire out_cas_n;
wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n;
wire [DM_WIDTH-1:0] out_dm;
wire [ODT_WIDTH -1:0] out_odt;
wire [CKE_WIDTH -1 :0] out_cke ;
wire [DQ_WIDTH-1:0] out_dq;
wire [DQS_WIDTH-1:0] out_dqs;
wire out_parity;
wire out_ras_n;
wire out_we_n;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire phy_rd_en;
wire [DM_WIDTH-1:0] ts_dm;
wire [DQ_WIDTH-1:0] ts_dq;
wire [DQS_WIDTH-1:0] ts_dqs;
wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr;
wire [DQS_WIDTH-1:0] pd_out_pre;
//wire metaQ;
reg [31:0] phy_ctl_wd_i1;
reg [31:0] phy_ctl_wd_i2;
reg phy_ctl_wr_i1;
reg phy_ctl_wr_i2;
reg [5:0] data_offset_1_i1;
reg [5:0] data_offset_1_i2;
reg [5:0] data_offset_2_i1;
reg [5:0] data_offset_2_i2;
wire [31:0] phy_ctl_wd_temp;
wire phy_ctl_wr_temp;
wire [5:0] data_offset_1_temp;
wire [5:0] data_offset_2_temp;
wire [5:0] data_offset_1_of;
wire [5:0] data_offset_2_of;
wire [31:0] phy_ctl_wd_of;
wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */;
wire [3:0] phy_ctl_full_temp;
wire data_io_idle_pwrdwn;
reg [29:0] fine_delay_mod; //3 bit per DQ
reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb
(* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1;
// Always read from input data FIFOs when not empty
assign phy_rd_en = !if_empty;
// IDELAYE2 initial value
assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE;
assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY;
// Idle powerdown when there are no pending reads in the MC
assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0;
//***************************************************************************
// Auxiliary output steering
//***************************************************************************
// For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be
// mapped to ddr_odt and the aux_out[7:4] from one of the data banks
// will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the
// addr/ctl bank would bank would map to both ddr_odt and ddr_cke.
generate
if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins
if (CKE_WIDTH == 1) begin : gen_cke
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_cke_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke)
);
end else begin: gen_2rank_cke
OBUF u_cke0_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke[0])
);
OBUF u_cke1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_cke[1])
);
end
end
endgenerate
generate
if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins
if (USE_ODT_PORT == 1) begin : gen_use_odt
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_odt_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]),
.O (ddr_odt[0])
);
if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
OBUF u_odt2_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[2])
);
end
end else begin
assign ddr_odt = 'b0;
end
end
endgenerate
//***************************************************************************
// Read data bit steering
//***************************************************************************
// Transpose elements of rd_data_map to form final read data output:
// phy_din elements are grouped according to "physical bit" - e.g.
// for nCK_PER_CLK = 4, there are 8 data phases transfered per physical
// bit per clock cycle:
// = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2,
// dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0}
// whereas rd_data is are grouped according to "phase" - e.g.
// = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0,
// dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0}
// therefore rd_data is formed by transposing phy_din - e.g.
// for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY
// bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then
// the assignments for bits of rd_data corresponding to DQ[1:0]
// would be:
// {rd_data[112], rd_data[96], rd_data[80], rd_data[64],
// rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0]
// {rd_data[113], rd_data[97], rd_data[81], rd_data[65],
// rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8]
generate
genvar i, j;
for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1
for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2
assign rd_data[DQ_WIDTH*j + i]
= phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+
80*FULL_DATA_MAP[(12*i+4)+:2] +
8*FULL_DATA_MAP[12*i+:4]) + j];
end
end
endgenerate
//generage idelay_inc per bits
reg [11:0] cal_tmp;
reg [95:0] byte_sel_data_map;
assign byte_sel_cnt_w1 = byte_sel_cnt;
always @ (posedge clk) begin
byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96];
end
always @ (posedge clk) begin
fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00};
fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00};
fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00};
fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00};
fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00};
fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00};
fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00};
fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00};
fine_delay_sel_r <= #TCQ fine_delay_sel;
end
//***************************************************************************
// Control/address
//***************************************************************************
assign out_cas_n
= mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]];
generate
// if signal placed on bit lanes [0-9]
if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10
// Determine routing based on clock ratio mode. If running in 4:1
// mode, then all four bits from logic are used. If 2:1 mode, only
// 2-bits are provided by logic, and each bit is repeated 2x to form
// 4-bit input to IN_FIFO, e.g.
// 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]}
// 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]}
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*CAS_MAP[3:0])+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end else begin: gen_cas_ge10
// If signal is placed in bit lane [10] or [11], route to upper
// nibble of phy_dout lane [5] or [6] respectively (in this case
// phy_dout lane [5, 6] are multiplexed to take input for two
// different SDR signals - this is how bits[10,11] need to be
// provided to the OUT_FIFO
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*(CAS_MAP[3:0]-5) + 4)+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end
endgenerate
assign out_ras_n
= mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]];
generate
if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*RAS_MAP[3:0])+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end else begin: gen_ras_ge10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*(RAS_MAP[3:0]-5) + 4)+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end
endgenerate
assign out_we_n
= mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]];
generate
if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*WE_MAP[3:0])+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end else begin: gen_we_ge10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*(WE_MAP[3:0]-5) + 4)+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end
endgenerate
generate
if (REG_CTRL == "ON") begin: gen_parity_out
// Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs
assign out_parity
= mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] +
PARITY_MAP[3:0]];
if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*PARITY_MAP[3:0])+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end else begin: gen_ge10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*(PARITY_MAP[3:0]-5) + 4)+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end
end
endgenerate
//*****************************************************************
generate
genvar m, n,x;
//*****************************************************************
// Control/address (multi-bit) buses
//*****************************************************************
// Row/Column address
for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out
assign out_addr[m]
= mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] +
12*ADDR_MAP[(12*m+4)+:2] +
ADDR_MAP[12*m+:4]];
if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10
// For multi-bit buses, we also have to deal with transposition
// when going from the logic-side control bus to phy_dout
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*ADDR_MAP[12*m+:4] + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*(ADDR_MAP[12*m+:4]-5) + 4 + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Bank address
for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out
assign out_ba[m]
= mem_dq_out[48*BANK_MAP[(12*m+8)+:3] +
12*BANK_MAP[(12*m+4)+:2] +
BANK_MAP[12*m+:4]];
if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*BANK_MAP[12*m+:4] + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*(BANK_MAP[12*m+:4]-5) + 4 + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Chip select
if (USE_CS_PORT == 1) begin: gen_cs_n_out
for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out
assign out_cs_n[m]
= mem_dq_out[48*CS_MAP[(12*m+8)+:3] +
12*CS_MAP[(12*m+4)+:2] +
CS_MAP[12*m+:4]];
if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*CS_MAP[12*m+:4] + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*(CS_MAP[12*m+:4]-5) + 4 + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end
end
end
if(CKE_ODT_AUX == "FALSE") begin
// ODT_ports
wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ;
if(RANKS == 1) begin
for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin
assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ;
end
end else begin
for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin
assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ;
assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ;
end
end
if (USE_ODT_PORT == 1) begin: gen_odt_out
for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1
assign out_odt[m]
= mem_dq_out[48*ODT_MAP[(12*m+8)+:3] +
12*ODT_MAP[(12*m+4)+:2] +
ODT_MAP[12*m+:4]];
if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*ODT_MAP[12*m+:4] + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*(ODT_MAP[12*m+:4]-5) + 4 + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ;
for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin
assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ;
end
for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out
assign out_cke[m]
= mem_dq_out[48*CKE_MAP[(12*m+8)+:3] +
12*CKE_MAP[(12*m+4)+:2] +
CKE_MAP[12*m+:4]];
if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*CKE_MAP[12*m+:4] + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*(CKE_MAP[12*m+:4]-5) + 4 + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
//*****************************************************************
// Data mask
//*****************************************************************
if (USE_DM_PORT == 1) begin: gen_dm_out
for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out
assign out_dm[m]
= mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
assign ts_dm[m]
= mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] +
80*FULL_MASK_MAP[(12*m+4)+:2] +
8*FULL_MASK_MAP[12*m+:4] + n]
= mux_wrdata_mask[DM_WIDTH*n + m];
end
end
end
//*****************************************************************
// Input and output DQ
//*****************************************************************
for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout
// to MC_PHY
assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] +
10*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]]
= in_dq[m];
// to I/O buffers
assign out_dq[m]
= mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
assign ts_dq[m]
= mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] +
80*FULL_DATA_MAP[(12*m+4)+:2] +
8*FULL_DATA_MAP[12*m+:4] + n]
= mux_wrdata[DQ_WIDTH*n + m];
end
end
//*****************************************************************
// Input and output DQS
//*****************************************************************
for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout
// to MC_PHY
assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]
= in_dqs[m];
// to I/O buffers
assign out_dqs[m]
= mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
assign ts_dqs[m]
= mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
end
endgenerate
assign pd_out = pd_out_pre[byte_sel_cnt_w1];
//***************************************************************************
// Memory I/F output and I/O buffer instantiation
//***************************************************************************
// Note on instantiation - generally at the minimum, it's not required to
// instantiate the output buffers - they can be inferred by the synthesis
// tool, and there aren't any attributes that need to be associated with
// them. Consider as a future option to take out the OBUF instantiations
OBUF u_cas_n_obuf
(
.I (out_cas_n),
.O (ddr_cas_n)
);
OBUF u_ras_n_obuf
(
.I (out_ras_n),
.O (ddr_ras_n)
);
OBUF u_we_n_obuf
(
.I (out_we_n),
.O (ddr_we_n)
);
generate
genvar p;
for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf
OBUF u_addr_obuf
(
.I (out_addr[p]),
.O (ddr_addr[p])
);
end
for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf
OBUF u_bank_obuf
(
.I (out_ba[p]),
.O (ddr_ba[p])
);
end
if (USE_CS_PORT == 1) begin: gen_cs_n_obuf
for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf
OBUF u_cs_n_obuf
(
.I (out_cs_n[p]),
.O (ddr_cs_n[p])
);
end
end
if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo
if (USE_ODT_PORT== 1) begin: gen_odt_obuf
for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf
OBUF u_cs_n_obuf
(
.I (out_odt[p]),
.O (ddr_odt[p])
);
end
end
for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf
OBUF u_cs_n_obuf
(
.I (out_cke[p]),
.O (ddr_cke[p])
);
end
end
if (REG_CTRL == "ON") begin: gen_parity_obuf
// Generate addr/ctrl parity output only for DDR3 registered DIMMs
OBUF u_parity_obuf
(
.I (out_parity),
.O (ddr_parity)
);
end else begin: gen_parity_tieoff
assign ddr_parity = 1'b0;
end
if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf
// Generate reset output only for DDR3 and DDR2 RDIMMs
OBUF u_reset_obuf
(
.I (mux_reset_n),
.O (ddr_reset_n)
);
end else begin: gen_reset_tieoff
assign ddr_reset_n = 1'b1;
end
if (USE_DM_PORT == 1) begin: gen_dm_obuf
for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm
OBUFT u_dm_obuf
(
.I (out_dm[p]),
.T (ts_dm[p]),
.O (ddr_dm[p])
);
end
end else begin: gen_dm_tieoff
assign ddr_dm = 'b0;
end
if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else begin: gen_dq_iobuf_default
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end
//if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP
if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff
IOBUFDS_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v2_3_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
//end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR
end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff
IOBUFDS_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
//.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v2_3_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
end else begin: gen_dqs_iobuf_default
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end
end
end
endgenerate
always @(posedge clk) begin
phy_ctl_wd_i1 <= #TCQ phy_ctl_wd;
phy_ctl_wr_i1 <= #TCQ phy_ctl_wr;
phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1;
phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1;
data_offset_1_i1 <= #TCQ data_offset_1;
data_offset_1_i2 <= #TCQ data_offset_1_i1;
data_offset_2_i1 <= #TCQ data_offset_2;
data_offset_2_i2 <= #TCQ data_offset_2_i1;
end
// 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it.
// 2:1 mode the command goes through pre fifo
assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of;
assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of;
assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of;
assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of;
generate
begin
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (32)
)
phy_ctl_pre_fifo_0
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[1]),
.wr_en_in (phy_ctl_wr),
.d_in (phy_ctl_wd),
.wr_en_out (phy_ctl_wr_of),
.d_out (phy_ctl_wd_of)
);
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_1
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[2]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_1),
.wr_en_out (),
.d_out (data_offset_1_of)
);
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_2
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[3]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_2),
.wr_en_out (),
.d_out (data_offset_2_of)
);
end
endgenerate
//***************************************************************************
// Hard PHY instantiation
//***************************************************************************
assign phy_ctl_full = phy_ctl_full_temp[0];
mig_7series_v2_3_ddr_mc_phy #
(
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK),
.RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE),
//.CKE_ODT_AUX (CKE_ODT_AUX),
.GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP),
.BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK),
.NUM_DDR_CK (CK_WIDTH),
.LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
.PO_CTL_COARSE_BYPASS ("FALSE"),
.PHYCTL_CMD_FIFO ("FALSE"),
.PHY_CLK_RATIO (nCK_PER_CLK),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.PHY_FOUR_WINDOW_CLOCKS (63),
.PHY_EVENTS_DELAY (18),
.PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN
.PHY_SYNC_MODE ("FALSE"),
.SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"),
.PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE"
.PHY_0_GENERATE_IDELAYCTRL ("FALSE"),
.PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE
.PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PHY_0_RD_DURATION_0 (6),
.PHY_0_RD_DURATION_1 (6),
.PHY_0_RD_DURATION_2 (6),
.PHY_0_RD_DURATION_3 (6),
.PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5),
.PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV),
.PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK),
//.PHY_1_NUM_DDR_CK (1),
.PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK),
//.PHY_2_NUM_DDR_CK (1),
.PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.TCK (tCK),
.PHY_0_IODELAY_GRP (IODELAY_GRP),
.PHY_1_IODELAY_GRP (IODELAY_GRP),
.PHY_2_IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_mc_phy
(
.rst (rst),
// Don't use MC_PHY to generate DDR_RESET_N output. Instead
// generate this output outside of MC_PHY (and synchronous to CLK)
.ddr_rst_in_n (1'b1),
.phy_clk (clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
// Remove later - always same connection as phy_clk port
.mem_refclk_div4 (clk),
.pll_lock (pll_lock),
.auxout_clk (),
.sync_pulse (sync_pulse),
// IDELAYCTRL instantiated outside of mc_phy module
.idelayctrl_refclk (),
.phy_dout (phy_dout),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phy_ctl_wd (phy_ctl_wd_temp),
.phy_ctl_wr (phy_ctl_wr_temp),
.if_empty_def (phy_if_empty_def),
.if_rst (phy_if_reset),
.phyGo ('b1),
.aux_in_1 (aux_in_1),
.aux_in_2 (aux_in_2),
// No support yet for different data offsets for different I/O banks
// (possible use in supporting wider range of skew among bytes)
.data_offset_1 (data_offset_1_temp),
.data_offset_2 (data_offset_2_temp),
.cke_in (),
.if_a_empty (),
.if_empty (if_empty),
.if_empty_or (),
.if_empty_and (),
.of_ctl_a_full (),
// .of_data_a_full (phy_data_full),
.of_ctl_full (phy_cmd_full),
.of_data_full (),
.pre_data_a_full (phy_pre_data_a_full),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.input_sink (),
.phy_din (phy_din),
.phy_ctl_a_full (),
.phy_ctl_full (phy_ctl_full_temp),
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.mem_dqs_in (mem_dqs_in),
.aux_out (aux_out),
.phy_ctl_ready (),
.rst_out (),
.ddr_clk (ddr_clk),
//.rclk (),
.mcGo (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.calib_zero_lanes ('b0),
.po_fine_enable (po_fine_enable),
.po_coarse_enable (po_coarse_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (),
.po_fine_overflow (),
.po_counter_read_val (po_counter_read_val),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (dbg_pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (),
.pi_counter_read_val (pi_counter_read_val),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (),
.pi_dqs_found_any (pi_dqs_found),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
// Currently not being used. May be used in future if periodic
// reads become a requirement. This output could be used to signal
// a catastrophic failure in read capture and the need for
// re-calibration.
.pi_dqs_out_of_range (pi_dqs_out_of_range)
,.ref_dll_lock (ref_dll_lock)
,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes)
,.fine_delay (fine_delay_mod)
,.fine_delay_sel (fine_delay_sel_r)
// ,.rst_phaser_ref (rst_phaser_ref)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// including negligence, or under any other theory of
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// related to, arising under or in connection with these
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_mc_phy_wrapper.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Oct 10 2010
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Wrapper file that encompasses the MC_PHY module
// instantiation and handles the vector remapping between
// the MC_PHY ports and the user's DDR3 ports. Vector
// remapping affects DDR3 control, address, and DQ/DQS/DM.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_mc_phy_wrapper #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter tCK = 2500, // ps
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter BANK_WIDTH = 3, // # of bank address
parameter CKE_WIDTH = 1, // # of clock enable outputs
parameter CS_WIDTH = 1, // # of chip select
parameter CK_WIDTH = 1, // # of CK
parameter CWL = 5, // CAS Write latency
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of data mask
parameter DQ_WIDTH = 16, // # of data bits
parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of strobe pairs
parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3)
parameter RANKS = 4, // # of ranks
parameter ODT_WIDTH = 1, // # of ODT outputs
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter REG_CTRL = "OFF", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // # of row/column address
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
parameter LP_DDR_CK_WIDTH = 2,
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// Parameters calculated outside of this block
parameter HIGHEST_BANK = 3, // Highest I/O bank index
parameter HIGHEST_LANE = 12, // Highest byte lane index
// ** Pin mapping parameters
// Parameters for mapping between hard PHY and physical DDR3 signals
// There are 2 classes of parameters:
// - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of
// 8-bit elements. Each element indicates the bank and byte lane
// location of that particular signal. The bit lane in this case
// doesn't need to be specified, either because there's only one
// pin pair in each byte lane that the DQS or CK pair can be
// located at, or in the case of CKE_ODT_BYTE_MAP, only the byte
// lane needs to be specified in order to determine which byte
// lane generates the RCLK (Note that CKE, and ODT must be located
// in the same bank, thus only one element in CKE_ODT_BYTE_MAP)
// [7:4] = bank # (0-4)
// [3:0] = byte lane # (0-3)
// - All other MAP parameters: These consist of 12-bit elements. Each
// element indicates the bank, byte lane, and bit lane location of
// that particular signal:
// [11:8] = bank # (0-4)
// [7:4] = byte lane # (0-3)
// [3:0] = bit lane # (0-11)
// Note that not all elements in all parameters will be used - it
// depends on the actual widths of the DDR3 buses. The parameters are
// structured to support a maximum of:
// - DQS groups: 18
// - data mask bits: 18
// In addition, the default parameter size of some of the parameters will
// support a certain number of bits, however, this can be expanded at
// compile time by expanding the width of the vector passed into this
// parameter
// - chip selects: 10
// - bank bits: 3
// - address bits: 16
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
// DATAx_MAP parameter is used for byte lane X in the design
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
// MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9]
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// Simulation options
parameter SIM_CAL_OPTION = "NONE",
// The PHY_CONTROL primitive in the bank where PLL exists is declared
// as the Master PHY_CONTROL.
parameter MASTER_PHY_CTL = 1,
parameter DRAM_WIDTH = 8
)
(
input rst,
input iddr_rst,
input clk,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input mmcm_ps_clk,
input idelayctrl_refclk,
input phy_cmd_wr_en,
input phy_data_wr_en,
input [31:0] phy_ctl_wd,
input phy_ctl_wr,
input phy_if_empty_def,
input phy_if_reset,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
output [4:0] idelaye2_init_val,
output [5:0] oclkdelay_init_val,
output if_empty,
output phy_ctl_full,
output phy_cmd_full,
output phy_data_full,
output phy_pre_data_a_full,
output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
output phy_mc_go,
input phy_write_calib,
input phy_read_calib,
input calib_in_common,
input [5:0] calib_sel,
input [DQS_CNT_WIDTH:0] byte_sel_cnt,
input [DRAM_WIDTH-1:0] fine_delay_incdec_pb,
input fine_delay_sel,
input [HIGHEST_BANK-1:0] calib_zero_inputs,
input [HIGHEST_BANK-1:0] calib_zero_ctrl,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
output [8:0] po_counter_read_val,
output [5:0] pi_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input [5:0] pi_counter_load_val,
input idelay_ce,
input idelay_inc,
input idelay_ld,
input idle,
output pi_phase_locked,
output pi_phase_locked_all,
output pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_out_of_range,
// From/to calibration logic/soft PHY
input phy_init_data_sel,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank,
input [nCK_PER_CLK-1:0] mux_cas_n,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n,
input [nCK_PER_CLK-1:0] mux_ras_n,
input [1:0] mux_odt,
input [nCK_PER_CLK-1:0] mux_cke,
input [nCK_PER_CLK-1:0] mux_we_n,
input [nCK_PER_CLK-1:0] parity_in,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask,
input mux_reset_n,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Memory I/F
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_parity,
output ddr_ras_n,
output ddr_we_n,
output ddr_reset_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
//output iodelay_ctrl_rdy,
output pd_out
,input dbg_pi_counter_read_en
,output ref_dll_lock
,input rst_phaser_ref
,output [11:0] dbg_pi_phase_locked_phy4lanes
,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes
);
function [71:0] generate_bytelanes_ddr_ck;
input [143:0] ck_byte_map;
integer v ;
begin
generate_bytelanes_ddr_ck = 'b0 ;
for (v = 0; v < CK_WIDTH; v = v + 1) begin
if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2)
generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1)
generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else
generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
end
end
endfunction
function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map;
input [143:0] ck_byte_map;
integer g;
begin
generate_ddr_ck_map = 'b0 ;
for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin
generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" :
(ck_byte_map[(g*8)+:4] == 4'd1) ? "B" :
(ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ;
generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" :
(ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location
end
end
endfunction
// Enable low power mode for input buffer
localparam IBUF_LOW_PWR
= (IBUF_LPWR_MODE == "OFF") ? "FALSE" :
((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL");
// Ratio of data to strobe
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
// number of data phases per internal clock
localparam PHASE_PER_CLK = 2*nCK_PER_CLK;
// used to determine routing to OUT_FIFO for control/address for 2:1
// vs. 4:1 memory:internal clock ratio modes
localparam PHASE_DIV = 4 / nCK_PER_CLK;
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
// Create an aggregate parameters for data mapping to reduce # of generate
// statements required in remapping code. Need to account for the case
// when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP
// parameter will have fewer than 8 elements used
localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0],
DATA16_MAP[12*DQ_PER_DQS-1:0],
DATA15_MAP[12*DQ_PER_DQS-1:0],
DATA14_MAP[12*DQ_PER_DQS-1:0],
DATA13_MAP[12*DQ_PER_DQS-1:0],
DATA12_MAP[12*DQ_PER_DQS-1:0],
DATA11_MAP[12*DQ_PER_DQS-1:0],
DATA10_MAP[12*DQ_PER_DQS-1:0],
DATA9_MAP[12*DQ_PER_DQS-1:0],
DATA8_MAP[12*DQ_PER_DQS-1:0],
DATA7_MAP[12*DQ_PER_DQS-1:0],
DATA6_MAP[12*DQ_PER_DQS-1:0],
DATA5_MAP[12*DQ_PER_DQS-1:0],
DATA4_MAP[12*DQ_PER_DQS-1:0],
DATA3_MAP[12*DQ_PER_DQS-1:0],
DATA2_MAP[12*DQ_PER_DQS-1:0],
DATA1_MAP[12*DQ_PER_DQS-1:0],
DATA0_MAP[12*DQ_PER_DQS-1:0]};
// Same deal, but for data mask mapping
localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP};
localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ;
localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ;
// Temporary parameters to determine which bank is outputting the CK/CK#
// Eventually there will be support for multiple CK/CK# output
//localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]);
//// Temporary method to force MC_PHY to generate ODDR associated with
//// CK/CK# output only for a single byte lane in the design. All banks
//// that won't be generating the CK/CK# will have "UNUSED" as their
//// PHY_GENERATE_DDR_CK parameter
//localparam TMP_PHY_0_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_1_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_2_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
// Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx
// which indicates which bit lanes in data byte lanes are
// output-only bitlanes (e.g. used specifically for data mask outputs)
function [143:0] calc_phy_bitlanes_outonly;
input [215:0] data_mask_in;
integer z;
begin
calc_phy_bitlanes_outonly = 'b0;
// Only enable BITLANES parameters for data masks if, well, if
// the data masks are actually enabled
if (USE_DM_PORT == 1)
for (z = 0; z < DM_WIDTH; z = z + 1)
calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] +
12*data_mask_in[(12*z+4)+:2] +
data_mask_in[12*z+:4]] = 1'b1;
end
endfunction
localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP);
localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0];
localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48];
localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96];
// Determine which bank and byte lane generates the RCLK used to clock
// out the auxilliary (ODT, CKE) outputs
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON
= (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON
= (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF
= (CKE_MAP[11:8] == 4'h0) ? 0 :
((CKE_MAP[11:8] == 4'h1) ? 1 :
((CKE_MAP[11:8] == 4'h2) ? 2 :
((CKE_MAP[11:8] == 4'h3) ? 3 :
((CKE_MAP[11:8] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF
= (CKE_MAP[7:4] == 4'h0) ? "A" :
((CKE_MAP[7:4] == 4'h1) ? "B" :
((CKE_MAP[7:4] == 4'h2) ? "C" :
((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ;
localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ;
//***************************************************************************
// OCLKDELAYED tap setting calculation:
// Parameters for calculating amount of phase shifting output clock to
// achieve 90 degree offset between DQS and DQ on writes
//***************************************************************************
//90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz
// and 1.25 for Mem_RefClk > 300 MHz
localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE";
//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400,
//DIV4: MemRefClk < 200 MHz
localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" :
tCK > 2500 ? "DIV2": "NONE";
localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 :
PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
// Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output
localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK;
// Whether OCLK_DELAY output comes inverted or not
localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0);
// Phaser-Out Stage3 Tap delay for 90 deg shift.
// Maximum tap delay is FreqRefClk period distributed over 64 taps
// localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV;
localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) -
(INT_DELAY + HALF_CYCLE_DELAY))
* 63 * FREQ_REF_DIV;
//localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY;
localparam integer PHY_0_A_PO_OCLK_DELAY_HW
= (tCK > 2273) ? 34 :
(tCK > 2000) ? 33 :
(tCK > 1724) ? 32 :
(tCK > 1515) ? 31 :
(tCK > 1315) ? 30 :
(tCK > 1136) ? 29 :
(tCK > 1021) ? 28 : 27;
// Note that simulation requires a different value than in H/W because of the
// difference in the way delays are modeled
localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ?
((tCK > 2500) ? 8 :
(DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) :
MC_OCLK_DELAY;
// Initial DQ IDELAY value
localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 :
(tCK < 1000) ? 0 :
(tCK < 1330) ? 0 :
(tCK < 2300) ? 0 :
(tCK < 2500) ? 2 : 0;
//localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0;
// Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3?
localparam PHY_0_RD_CMD_OFFSET_0 = 10;
localparam PHY_0_RD_CMD_OFFSET_1 = 10;
localparam PHY_0_RD_CMD_OFFSET_2 = 10;
localparam PHY_0_RD_CMD_OFFSET_3 = 10;
// 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing
localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4;
// 4:1 and 2:1 have different values
localparam PHY_0_WR_DURATION_0 = 7;
localparam PHY_0_WR_DURATION_1 = 7;
localparam PHY_0_WR_DURATION_2 = 7;
localparam PHY_0_WR_DURATION_3 = 7;
// Aux_out parameters for toggle mode (CKE)
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 :
(CWL < 7) ?
4 + ((CWL_M % 2) ? 0 : 1) :
5 + ((CWL_M % 2) ? 0 : 1);
// temporary parameter to enable/disable PHY PC counters. In both 4:1 and
// 2:1 cases, this should be disabled. For now, enable for 4:1 mode to
// avoid making too many changes at once.
localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE";
wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out;
wire [HIGHEST_LANE-1:0] mem_dqs_in;
wire [HIGHEST_LANE-1:0] mem_dqs_out;
wire [HIGHEST_LANE-1:0] mem_dqs_ts;
wire [HIGHEST_LANE*10-1:0] mem_dq_in;
wire [HIGHEST_LANE*12-1:0] mem_dq_out;
wire [HIGHEST_LANE*12-1:0] mem_dq_ts;
wire [DQ_WIDTH-1:0] in_dq;
wire [DQS_WIDTH-1:0] in_dqs;
wire [ROW_WIDTH-1:0] out_addr;
wire [BANK_WIDTH-1:0] out_ba;
wire out_cas_n;
wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n;
wire [DM_WIDTH-1:0] out_dm;
wire [ODT_WIDTH -1:0] out_odt;
wire [CKE_WIDTH -1 :0] out_cke ;
wire [DQ_WIDTH-1:0] out_dq;
wire [DQS_WIDTH-1:0] out_dqs;
wire out_parity;
wire out_ras_n;
wire out_we_n;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire phy_rd_en;
wire [DM_WIDTH-1:0] ts_dm;
wire [DQ_WIDTH-1:0] ts_dq;
wire [DQS_WIDTH-1:0] ts_dqs;
wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr;
wire [DQS_WIDTH-1:0] pd_out_pre;
//wire metaQ;
reg [31:0] phy_ctl_wd_i1;
reg [31:0] phy_ctl_wd_i2;
reg phy_ctl_wr_i1;
reg phy_ctl_wr_i2;
reg [5:0] data_offset_1_i1;
reg [5:0] data_offset_1_i2;
reg [5:0] data_offset_2_i1;
reg [5:0] data_offset_2_i2;
wire [31:0] phy_ctl_wd_temp;
wire phy_ctl_wr_temp;
wire [5:0] data_offset_1_temp;
wire [5:0] data_offset_2_temp;
wire [5:0] data_offset_1_of;
wire [5:0] data_offset_2_of;
wire [31:0] phy_ctl_wd_of;
wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */;
wire [3:0] phy_ctl_full_temp;
wire data_io_idle_pwrdwn;
reg [29:0] fine_delay_mod; //3 bit per DQ
reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb
(* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1;
// Always read from input data FIFOs when not empty
assign phy_rd_en = !if_empty;
// IDELAYE2 initial value
assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE;
assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY;
// Idle powerdown when there are no pending reads in the MC
assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0;
//***************************************************************************
// Auxiliary output steering
//***************************************************************************
// For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be
// mapped to ddr_odt and the aux_out[7:4] from one of the data banks
// will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the
// addr/ctl bank would bank would map to both ddr_odt and ddr_cke.
generate
if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins
if (CKE_WIDTH == 1) begin : gen_cke
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_cke_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke)
);
end else begin: gen_2rank_cke
OBUF u_cke0_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke[0])
);
OBUF u_cke1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_cke[1])
);
end
end
endgenerate
generate
if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins
if (USE_ODT_PORT == 1) begin : gen_use_odt
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_odt_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]),
.O (ddr_odt[0])
);
if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
OBUF u_odt2_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[2])
);
end
end else begin
assign ddr_odt = 'b0;
end
end
endgenerate
//***************************************************************************
// Read data bit steering
//***************************************************************************
// Transpose elements of rd_data_map to form final read data output:
// phy_din elements are grouped according to "physical bit" - e.g.
// for nCK_PER_CLK = 4, there are 8 data phases transfered per physical
// bit per clock cycle:
// = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2,
// dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0}
// whereas rd_data is are grouped according to "phase" - e.g.
// = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0,
// dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0}
// therefore rd_data is formed by transposing phy_din - e.g.
// for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY
// bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then
// the assignments for bits of rd_data corresponding to DQ[1:0]
// would be:
// {rd_data[112], rd_data[96], rd_data[80], rd_data[64],
// rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0]
// {rd_data[113], rd_data[97], rd_data[81], rd_data[65],
// rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8]
generate
genvar i, j;
for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1
for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2
assign rd_data[DQ_WIDTH*j + i]
= phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+
80*FULL_DATA_MAP[(12*i+4)+:2] +
8*FULL_DATA_MAP[12*i+:4]) + j];
end
end
endgenerate
//generage idelay_inc per bits
reg [11:0] cal_tmp;
reg [95:0] byte_sel_data_map;
assign byte_sel_cnt_w1 = byte_sel_cnt;
always @ (posedge clk) begin
byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96];
end
always @ (posedge clk) begin
fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00};
fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00};
fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00};
fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00};
fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00};
fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00};
fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00};
fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00};
fine_delay_sel_r <= #TCQ fine_delay_sel;
end
//***************************************************************************
// Control/address
//***************************************************************************
assign out_cas_n
= mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]];
generate
// if signal placed on bit lanes [0-9]
if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10
// Determine routing based on clock ratio mode. If running in 4:1
// mode, then all four bits from logic are used. If 2:1 mode, only
// 2-bits are provided by logic, and each bit is repeated 2x to form
// 4-bit input to IN_FIFO, e.g.
// 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]}
// 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]}
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*CAS_MAP[3:0])+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end else begin: gen_cas_ge10
// If signal is placed in bit lane [10] or [11], route to upper
// nibble of phy_dout lane [5] or [6] respectively (in this case
// phy_dout lane [5, 6] are multiplexed to take input for two
// different SDR signals - this is how bits[10,11] need to be
// provided to the OUT_FIFO
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*(CAS_MAP[3:0]-5) + 4)+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end
endgenerate
assign out_ras_n
= mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]];
generate
if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*RAS_MAP[3:0])+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end else begin: gen_ras_ge10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*(RAS_MAP[3:0]-5) + 4)+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end
endgenerate
assign out_we_n
= mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]];
generate
if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*WE_MAP[3:0])+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end else begin: gen_we_ge10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*(WE_MAP[3:0]-5) + 4)+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end
endgenerate
generate
if (REG_CTRL == "ON") begin: gen_parity_out
// Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs
assign out_parity
= mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] +
PARITY_MAP[3:0]];
if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*PARITY_MAP[3:0])+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end else begin: gen_ge10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*(PARITY_MAP[3:0]-5) + 4)+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end
end
endgenerate
//*****************************************************************
generate
genvar m, n,x;
//*****************************************************************
// Control/address (multi-bit) buses
//*****************************************************************
// Row/Column address
for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out
assign out_addr[m]
= mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] +
12*ADDR_MAP[(12*m+4)+:2] +
ADDR_MAP[12*m+:4]];
if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10
// For multi-bit buses, we also have to deal with transposition
// when going from the logic-side control bus to phy_dout
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*ADDR_MAP[12*m+:4] + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*(ADDR_MAP[12*m+:4]-5) + 4 + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Bank address
for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out
assign out_ba[m]
= mem_dq_out[48*BANK_MAP[(12*m+8)+:3] +
12*BANK_MAP[(12*m+4)+:2] +
BANK_MAP[12*m+:4]];
if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*BANK_MAP[12*m+:4] + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*(BANK_MAP[12*m+:4]-5) + 4 + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Chip select
if (USE_CS_PORT == 1) begin: gen_cs_n_out
for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out
assign out_cs_n[m]
= mem_dq_out[48*CS_MAP[(12*m+8)+:3] +
12*CS_MAP[(12*m+4)+:2] +
CS_MAP[12*m+:4]];
if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*CS_MAP[12*m+:4] + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*(CS_MAP[12*m+:4]-5) + 4 + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end
end
end
if(CKE_ODT_AUX == "FALSE") begin
// ODT_ports
wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ;
if(RANKS == 1) begin
for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin
assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ;
end
end else begin
for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin
assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ;
assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ;
end
end
if (USE_ODT_PORT == 1) begin: gen_odt_out
for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1
assign out_odt[m]
= mem_dq_out[48*ODT_MAP[(12*m+8)+:3] +
12*ODT_MAP[(12*m+4)+:2] +
ODT_MAP[12*m+:4]];
if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*ODT_MAP[12*m+:4] + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*(ODT_MAP[12*m+:4]-5) + 4 + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ;
for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin
assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ;
end
for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out
assign out_cke[m]
= mem_dq_out[48*CKE_MAP[(12*m+8)+:3] +
12*CKE_MAP[(12*m+4)+:2] +
CKE_MAP[12*m+:4]];
if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*CKE_MAP[12*m+:4] + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*(CKE_MAP[12*m+:4]-5) + 4 + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
//*****************************************************************
// Data mask
//*****************************************************************
if (USE_DM_PORT == 1) begin: gen_dm_out
for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out
assign out_dm[m]
= mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
assign ts_dm[m]
= mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] +
80*FULL_MASK_MAP[(12*m+4)+:2] +
8*FULL_MASK_MAP[12*m+:4] + n]
= mux_wrdata_mask[DM_WIDTH*n + m];
end
end
end
//*****************************************************************
// Input and output DQ
//*****************************************************************
for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout
// to MC_PHY
assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] +
10*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]]
= in_dq[m];
// to I/O buffers
assign out_dq[m]
= mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
assign ts_dq[m]
= mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] +
80*FULL_DATA_MAP[(12*m+4)+:2] +
8*FULL_DATA_MAP[12*m+:4] + n]
= mux_wrdata[DQ_WIDTH*n + m];
end
end
//*****************************************************************
// Input and output DQS
//*****************************************************************
for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout
// to MC_PHY
assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]
= in_dqs[m];
// to I/O buffers
assign out_dqs[m]
= mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
assign ts_dqs[m]
= mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
end
endgenerate
assign pd_out = pd_out_pre[byte_sel_cnt_w1];
//***************************************************************************
// Memory I/F output and I/O buffer instantiation
//***************************************************************************
// Note on instantiation - generally at the minimum, it's not required to
// instantiate the output buffers - they can be inferred by the synthesis
// tool, and there aren't any attributes that need to be associated with
// them. Consider as a future option to take out the OBUF instantiations
OBUF u_cas_n_obuf
(
.I (out_cas_n),
.O (ddr_cas_n)
);
OBUF u_ras_n_obuf
(
.I (out_ras_n),
.O (ddr_ras_n)
);
OBUF u_we_n_obuf
(
.I (out_we_n),
.O (ddr_we_n)
);
generate
genvar p;
for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf
OBUF u_addr_obuf
(
.I (out_addr[p]),
.O (ddr_addr[p])
);
end
for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf
OBUF u_bank_obuf
(
.I (out_ba[p]),
.O (ddr_ba[p])
);
end
if (USE_CS_PORT == 1) begin: gen_cs_n_obuf
for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf
OBUF u_cs_n_obuf
(
.I (out_cs_n[p]),
.O (ddr_cs_n[p])
);
end
end
if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo
if (USE_ODT_PORT== 1) begin: gen_odt_obuf
for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf
OBUF u_cs_n_obuf
(
.I (out_odt[p]),
.O (ddr_odt[p])
);
end
end
for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf
OBUF u_cs_n_obuf
(
.I (out_cke[p]),
.O (ddr_cke[p])
);
end
end
if (REG_CTRL == "ON") begin: gen_parity_obuf
// Generate addr/ctrl parity output only for DDR3 registered DIMMs
OBUF u_parity_obuf
(
.I (out_parity),
.O (ddr_parity)
);
end else begin: gen_parity_tieoff
assign ddr_parity = 1'b0;
end
if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf
// Generate reset output only for DDR3 and DDR2 RDIMMs
OBUF u_reset_obuf
(
.I (mux_reset_n),
.O (ddr_reset_n)
);
end else begin: gen_reset_tieoff
assign ddr_reset_n = 1'b1;
end
if (USE_DM_PORT == 1) begin: gen_dm_obuf
for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm
OBUFT u_dm_obuf
(
.I (out_dm[p]),
.T (ts_dm[p]),
.O (ddr_dm[p])
);
end
end else begin: gen_dm_tieoff
assign ddr_dm = 'b0;
end
if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else begin: gen_dq_iobuf_default
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end
//if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP
if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff
IOBUFDS_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v2_3_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
//end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR
end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff
IOBUFDS_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
//.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v2_3_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
end else begin: gen_dqs_iobuf_default
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end
end
end
endgenerate
always @(posedge clk) begin
phy_ctl_wd_i1 <= #TCQ phy_ctl_wd;
phy_ctl_wr_i1 <= #TCQ phy_ctl_wr;
phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1;
phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1;
data_offset_1_i1 <= #TCQ data_offset_1;
data_offset_1_i2 <= #TCQ data_offset_1_i1;
data_offset_2_i1 <= #TCQ data_offset_2;
data_offset_2_i2 <= #TCQ data_offset_2_i1;
end
// 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it.
// 2:1 mode the command goes through pre fifo
assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of;
assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of;
assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of;
assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of;
generate
begin
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (32)
)
phy_ctl_pre_fifo_0
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[1]),
.wr_en_in (phy_ctl_wr),
.d_in (phy_ctl_wd),
.wr_en_out (phy_ctl_wr_of),
.d_out (phy_ctl_wd_of)
);
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_1
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[2]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_1),
.wr_en_out (),
.d_out (data_offset_1_of)
);
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_2
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[3]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_2),
.wr_en_out (),
.d_out (data_offset_2_of)
);
end
endgenerate
//***************************************************************************
// Hard PHY instantiation
//***************************************************************************
assign phy_ctl_full = phy_ctl_full_temp[0];
mig_7series_v2_3_ddr_mc_phy #
(
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK),
.RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE),
//.CKE_ODT_AUX (CKE_ODT_AUX),
.GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP),
.BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK),
.NUM_DDR_CK (CK_WIDTH),
.LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
.PO_CTL_COARSE_BYPASS ("FALSE"),
.PHYCTL_CMD_FIFO ("FALSE"),
.PHY_CLK_RATIO (nCK_PER_CLK),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.PHY_FOUR_WINDOW_CLOCKS (63),
.PHY_EVENTS_DELAY (18),
.PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN
.PHY_SYNC_MODE ("FALSE"),
.SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"),
.PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE"
.PHY_0_GENERATE_IDELAYCTRL ("FALSE"),
.PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE
.PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PHY_0_RD_DURATION_0 (6),
.PHY_0_RD_DURATION_1 (6),
.PHY_0_RD_DURATION_2 (6),
.PHY_0_RD_DURATION_3 (6),
.PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5),
.PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV),
.PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK),
//.PHY_1_NUM_DDR_CK (1),
.PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK),
//.PHY_2_NUM_DDR_CK (1),
.PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.TCK (tCK),
.PHY_0_IODELAY_GRP (IODELAY_GRP),
.PHY_1_IODELAY_GRP (IODELAY_GRP),
.PHY_2_IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_mc_phy
(
.rst (rst),
// Don't use MC_PHY to generate DDR_RESET_N output. Instead
// generate this output outside of MC_PHY (and synchronous to CLK)
.ddr_rst_in_n (1'b1),
.phy_clk (clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
// Remove later - always same connection as phy_clk port
.mem_refclk_div4 (clk),
.pll_lock (pll_lock),
.auxout_clk (),
.sync_pulse (sync_pulse),
// IDELAYCTRL instantiated outside of mc_phy module
.idelayctrl_refclk (),
.phy_dout (phy_dout),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phy_ctl_wd (phy_ctl_wd_temp),
.phy_ctl_wr (phy_ctl_wr_temp),
.if_empty_def (phy_if_empty_def),
.if_rst (phy_if_reset),
.phyGo ('b1),
.aux_in_1 (aux_in_1),
.aux_in_2 (aux_in_2),
// No support yet for different data offsets for different I/O banks
// (possible use in supporting wider range of skew among bytes)
.data_offset_1 (data_offset_1_temp),
.data_offset_2 (data_offset_2_temp),
.cke_in (),
.if_a_empty (),
.if_empty (if_empty),
.if_empty_or (),
.if_empty_and (),
.of_ctl_a_full (),
// .of_data_a_full (phy_data_full),
.of_ctl_full (phy_cmd_full),
.of_data_full (),
.pre_data_a_full (phy_pre_data_a_full),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.input_sink (),
.phy_din (phy_din),
.phy_ctl_a_full (),
.phy_ctl_full (phy_ctl_full_temp),
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.mem_dqs_in (mem_dqs_in),
.aux_out (aux_out),
.phy_ctl_ready (),
.rst_out (),
.ddr_clk (ddr_clk),
//.rclk (),
.mcGo (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.calib_zero_lanes ('b0),
.po_fine_enable (po_fine_enable),
.po_coarse_enable (po_coarse_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (),
.po_fine_overflow (),
.po_counter_read_val (po_counter_read_val),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (dbg_pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (),
.pi_counter_read_val (pi_counter_read_val),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (),
.pi_dqs_found_any (pi_dqs_found),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
// Currently not being used. May be used in future if periodic
// reads become a requirement. This output could be used to signal
// a catastrophic failure in read capture and the need for
// re-calibration.
.pi_dqs_out_of_range (pi_dqs_out_of_range)
,.ref_dll_lock (ref_dll_lock)
,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes)
,.fine_delay (fine_delay_mod)
,.fine_delay_sel (fine_delay_sel_r)
// ,.rst_phaser_ref (rst_phaser_ref)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : mig_7series_v2_3_axi_fi_xor.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Tue Sept 21 2010
// \___\/\___\
//
//*****************************************************************************
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v2_3_fi_xor #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// External Memory Data Width
parameter integer DQ_WIDTH = 72,
parameter integer DQS_WIDTH = 9,
parameter integer nCK_PER_CLK = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_in ,
output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_out ,
input wire wrdata_en ,
input wire [DQS_WIDTH-1:0] fi_xor_we ,
input wire [DQ_WIDTH-1:0] fi_xor_wrdata
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [DQ_WIDTH-1:0] fi_xor_data = {DQ_WIDTH{1'b0}};
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// Register in the fi_xor_wrdata on a byte width basis
generate
begin
genvar i;
for (i = 0; i < DQS_WIDTH; i = i + 1) begin : assign_fi_xor_data
always @(posedge clk) begin
if (wrdata_en) begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= {DQ_PER_DQS{1'b0}};
end
else if (fi_xor_we[i]) begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_wrdata[i*DQ_PER_DQS+:DQ_PER_DQS];
end
else begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS];
end
end
end
end
endgenerate
assign wrdata_out[0+:DQ_WIDTH] = wrdata_in[0+:DQ_WIDTH] ^ fi_xor_data[0+:DQ_WIDTH];
// Pass through upper bits
assign wrdata_out[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH] = wrdata_in[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH];
endmodule
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : mig_7series_v2_3_axi_fi_xor.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Tue Sept 21 2010
// \___\/\___\
//
//*****************************************************************************
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v2_3_fi_xor #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// External Memory Data Width
parameter integer DQ_WIDTH = 72,
parameter integer DQS_WIDTH = 9,
parameter integer nCK_PER_CLK = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_in ,
output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_out ,
input wire wrdata_en ,
input wire [DQS_WIDTH-1:0] fi_xor_we ,
input wire [DQ_WIDTH-1:0] fi_xor_wrdata
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [DQ_WIDTH-1:0] fi_xor_data = {DQ_WIDTH{1'b0}};
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// Register in the fi_xor_wrdata on a byte width basis
generate
begin
genvar i;
for (i = 0; i < DQS_WIDTH; i = i + 1) begin : assign_fi_xor_data
always @(posedge clk) begin
if (wrdata_en) begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= {DQ_PER_DQS{1'b0}};
end
else if (fi_xor_we[i]) begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_wrdata[i*DQ_PER_DQS+:DQ_PER_DQS];
end
else begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS];
end
end
end
end
endgenerate
assign wrdata_out[0+:DQ_WIDTH] = wrdata_in[0+:DQ_WIDTH] ^ fi_xor_data[0+:DQ_WIDTH];
// Pass through upper bits
assign wrdata_out[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH] = wrdata_in[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH];
endmodule
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : mig_7series_v2_3_axi_fi_xor.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Tue Sept 21 2010
// \___\/\___\
//
//*****************************************************************************
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v2_3_fi_xor #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// External Memory Data Width
parameter integer DQ_WIDTH = 72,
parameter integer DQS_WIDTH = 9,
parameter integer nCK_PER_CLK = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_in ,
output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_out ,
input wire wrdata_en ,
input wire [DQS_WIDTH-1:0] fi_xor_we ,
input wire [DQ_WIDTH-1:0] fi_xor_wrdata
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [DQ_WIDTH-1:0] fi_xor_data = {DQ_WIDTH{1'b0}};
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// Register in the fi_xor_wrdata on a byte width basis
generate
begin
genvar i;
for (i = 0; i < DQS_WIDTH; i = i + 1) begin : assign_fi_xor_data
always @(posedge clk) begin
if (wrdata_en) begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= {DQ_PER_DQS{1'b0}};
end
else if (fi_xor_we[i]) begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_wrdata[i*DQ_PER_DQS+:DQ_PER_DQS];
end
else begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS];
end
end
end
end
endgenerate
assign wrdata_out[0+:DQ_WIDTH] = wrdata_in[0+:DQ_WIDTH] ^ fi_xor_data[0+:DQ_WIDTH];
// Pass through upper bits
assign wrdata_out[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH] = wrdata_in[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH];
endmodule
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : mig_7series_v2_3_axi_fi_xor.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Tue Sept 21 2010
// \___\/\___\
//
//*****************************************************************************
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v2_3_fi_xor #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// External Memory Data Width
parameter integer DQ_WIDTH = 72,
parameter integer DQS_WIDTH = 9,
parameter integer nCK_PER_CLK = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_in ,
output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_out ,
input wire wrdata_en ,
input wire [DQS_WIDTH-1:0] fi_xor_we ,
input wire [DQ_WIDTH-1:0] fi_xor_wrdata
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [DQ_WIDTH-1:0] fi_xor_data = {DQ_WIDTH{1'b0}};
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// Register in the fi_xor_wrdata on a byte width basis
generate
begin
genvar i;
for (i = 0; i < DQS_WIDTH; i = i + 1) begin : assign_fi_xor_data
always @(posedge clk) begin
if (wrdata_en) begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= {DQ_PER_DQS{1'b0}};
end
else if (fi_xor_we[i]) begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_wrdata[i*DQ_PER_DQS+:DQ_PER_DQS];
end
else begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS];
end
end
end
end
endgenerate
assign wrdata_out[0+:DQ_WIDTH] = wrdata_in[0+:DQ_WIDTH] ^ fi_xor_data[0+:DQ_WIDTH];
// Pass through upper bits
assign wrdata_out[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH] = wrdata_in[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH];
endmodule
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
//*****************************************************************************
// Top level memory sequencer structural block. This block
// instantiates the rank, bank, and column machines.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_mc #
(
parameter TCQ = 100, // clk->out delay(sim only)
parameter ADDR_CMD_MODE = "1T", // registered or
// 1Tfered mem?
parameter BANK_WIDTH = 3, // bank address width
parameter BM_CNT_WIDTH = 2, // # BM counter width
// i.e., log2(nBANK_MACHS)
parameter BURST_MODE = "8", // Burst length
parameter CL = 5, // Read CAS latency
// (in clk cyc)
parameter CMD_PIPE_PLUS1 = "ON", // add register stage
// between MC and PHY
parameter COL_WIDTH = 12, // column address width
parameter CS_WIDTH = 4, // # of unique CS outputs
parameter CWL = 5, // Write CAS latency
// (in clk cyc)
parameter DATA_BUF_ADDR_WIDTH = 8, // User request tag (e.g.
// user src/dest buf addr)
parameter DATA_BUF_OFFSET_WIDTH = 1, // User buffer offset width
parameter DATA_WIDTH = 64, // Data bus width
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3", // Memory I/F type:
// "DDR3", "DDR2"
parameter ECC = "OFF", // ECC ON/OFF?
parameter ECC_WIDTH = 8, // # of ECC bits
parameter MAINT_PRESCALER_PERIOD= 200000, // maintenance period (ps)
parameter MC_ERR_ADDR_WIDTH = 31, // # of error address bits
parameter nBANK_MACHS = 4, // # of bank machines (BM)
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
// frequency ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs
// per rank
parameter nREFRESH_BANK = 1, // # of REF cmds to pull-in
parameter nSLOTS = 1, // # DIMM slots in system
parameter ORDERING = "NORM", // request ordering mode
parameter PAYLOAD_WIDTH = 64, // Width of data payload
// from PHY
parameter RANK_WIDTH = 2, // # of bits to count ranks
parameter RANKS = 4, // # of ranks of DRAM
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // row address width
parameter RTT_NOM = "40", // Nominal ODT value
parameter RTT_WR = "120", // Write ODT value
parameter SLOT_0_CONFIG = 8'b0000_0101, // ranks allowed in slot 0
parameter SLOT_1_CONFIG = 8'b0000_1010, // ranks allowed in slot 1
parameter STARVE_LIMIT = 2, // max # of times a user
// request is allowed to
// lose arbitration when
// reordering is enabled
parameter tCK = 2500, // memory clk period(ps)
parameter tCKE = 10000, // CKE minimum pulse (ps)
parameter tFAW = 40000, // four activate window(ps)
parameter tRAS = 37500, // ACT->PRE cmd period (ps)
parameter tRCD = 12500, // ACT->R/W delay (ps)
parameter tREFI = 7800000, // average periodic
// refresh interval(ps)
parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal
parameter tRFC = 110000, // REF->ACT/REF delay (ps)
parameter tRP = 12500, // PRE cmd period (ps)
parameter tRRD = 10000, // ACT->ACT period (ps)
parameter tRTP = 7500, // Read->PRE cmd delay (ps)
parameter tWTR = 7500, // Internal write->read
// delay (ps)
// requiring DLL lock (CKs)
parameter tZQCS = 64, // ZQCS cmd period (CKs)
parameter tZQI = 128_000_000, // ZQCS interval (ps)
parameter tPRDI = 1_000_000, // pS
parameter USER_REFRESH = "OFF" // Whether user manages REF
)
(
// System inputs
input clk,
input rst,
// Physical memory slot presence
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// Native Interface
input [2:0] cmd,
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,
input hi_priority,
input size,
input [BANK_WIDTH-1:0] bank,
input [COL_WIDTH-1:0] col,
input [RANK_WIDTH-1:0] rank,
input [ROW_WIDTH-1:0] row,
input use_addr,
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data,
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask,
output accept,
output accept_ns,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data,
output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr,
output rd_data_en,
output rd_data_end,
output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset,
output reg [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr /* synthesis syn_maxfan = 30 */,
output reg wr_data_en,
output reg [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset /* synthesis syn_maxfan = 30 */,
output mc_read_idle,
output mc_ref_zq_wip,
// ECC interface
input correct_en,
input [2*nCK_PER_CLK-1:0] raw_not_ecc,
input [DQS_WIDTH - 1:0] fi_xor_we,
input [DQ_WIDTH -1 :0 ] fi_xor_wrdata,
output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr,
output [2*nCK_PER_CLK-1:0] ecc_single,
output [2*nCK_PER_CLK-1:0] ecc_multiple,
// User maintenance requests
input app_periodic_rd_req,
input app_ref_req,
input app_zq_req,
input app_sr_req,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
// MC <==> PHY Interface
output reg [nCK_PER_CLK-1:0] mc_ras_n,
output reg [nCK_PER_CLK-1:0] mc_cas_n,
output reg [nCK_PER_CLK-1:0] mc_we_n,
output reg [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output reg [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output reg [1:0] mc_odt,
output reg [nCK_PER_CLK-1:0] mc_cke,
output wire mc_reset_n,
output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata,
output wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0]mc_wrdata_mask,
output reg mc_wrdata_en,
output wire mc_cmd_wren,
output wire mc_ctl_wren,
output reg [2:0] mc_cmd,
output reg [5:0] mc_data_offset,
output reg [5:0] mc_data_offset_1,
output reg [5:0] mc_data_offset_2,
output reg [1:0] mc_cas_slot,
output reg [3:0] mc_aux_out0,
output reg [3:0] mc_aux_out1,
output reg [1:0] mc_rank_cnt,
input phy_mc_ctl_full,
input phy_mc_cmd_full,
input phy_mc_data_full,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data,
input phy_rddata_valid,
input init_calib_complete,
input [6*RANKS-1:0] calib_rd_data_offset,
input [6*RANKS-1:0] calib_rd_data_offset_1,
input [6*RANKS-1:0] calib_rd_data_offset_2
);
assign mc_reset_n = 1'b1; // never reset memory
assign mc_cmd_wren = 1'b1; // always write CMD FIFO(issue DSEL when idle)
assign mc_ctl_wren = 1'b1; // always write CTL FIFO(issue nondata when idle)
// Ensure there is always at least one rank present during operation
`ifdef MC_SVA
ranks_present: assert property
(@(posedge clk) (rst || (|(slot_0_present | slot_1_present))));
`endif
// Reserved. Do not change.
localparam nPHY_WRLAT = 2;
// always delay write data control unless ECC mode is enabled
localparam DELAY_WR_DATA_CNTRL = ECC == "ON" ? 0 : 1;
// Ensure that write control is delayed for appropriate CWL
/*`ifdef MC_SVA
delay_wr_data_zero_CWL_le_6: assert property
(@(posedge clk) ((CWL > 6) || (DELAY_WR_DATA_CNTRL == 0)));
`endif*/
// Never retrieve WR_DATA_ADDR early
localparam EARLY_WR_DATA_ADDR = "OFF";
//***************************************************************************
// Convert timing parameters from time to clock cycles
//***************************************************************************
localparam nCKE = cdiv(tCKE, tCK);
localparam nRP = cdiv(tRP, tCK);
localparam nRCD = cdiv(tRCD, tCK);
localparam nRAS = cdiv(tRAS, tCK);
localparam nFAW = cdiv(tFAW, tCK);
localparam nRFC = cdiv(tRFC, tCK);
// Convert tWR. As per specification, write recover for autoprecharge
// cycles doesn't support values of 9 and 11. Round up 9 to 10 and 11 to 12
localparam nWR_CK = cdiv(15000, tCK) ;
localparam nWR = (nWR_CK == 9) ? 10 : (nWR_CK == 11) ? 12 : nWR_CK;
// tRRD, tWTR at tRTP have a 4 cycle floor in DDR3 and 2 cycle floor in DDR2
localparam nRRD_CK = cdiv(tRRD, tCK);
localparam nRRD = (DRAM_TYPE == "DDR3") ? (nRRD_CK < 4) ? 4 : nRRD_CK
: (nRRD_CK < 2) ? 2 : nRRD_CK;
localparam nWTR_CK = cdiv(tWTR, tCK);
localparam nWTR = (DRAM_TYPE == "DDR3") ? (nWTR_CK < 4) ? 4 : nWTR_CK
: (nWTR_CK < 2) ? 2 : nWTR_CK;
localparam nRTP_CK = cdiv(tRTP, tCK);
localparam nRTP = (DRAM_TYPE == "DDR3") ? (nRTP_CK < 4) ? 4 : nRTP_CK
: (nRTP_CK < 2) ? 2 : nRTP_CK;
// Add a cycle to CL/CWL for the register in RDIMM devices
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
localparam CL_M = (REG_CTRL == "ON") ? CL + 1 : CL;
// Tuneable delay between read and write data on the DQ bus
localparam DQRD2DQWR_DLY = 4;
// CKE minimum pulse width for self-refresh (SRE->SRX minimum time)
localparam nCKESR = nCKE + 1;
// Delay from SRE to command requiring locked DLL. Currently fixed at 512 for
// all devices per JEDEC spec.
localparam tXSDLL = 512;
//***************************************************************************
// Set up maintenance counter dividers
//***************************************************************************
// CK clock divisor to generate maintenance prescaler period (round down)
localparam MAINT_PRESCALER_DIV = MAINT_PRESCALER_PERIOD / (tCK*nCK_PER_CLK);
// Maintenance prescaler divisor for refresh timer. Essentially, this is
// just (tREFI / MAINT_PRESCALER_PERIOD), but we must account for the worst
// case delay from the time we get a tick from the refresh counter to the
// time that we can actually issue the REF command. Thus, subtract tRCD, CL,
// data burst time and tRP for each implemented bank machine to ensure that
// all transactions can complete before tREFI expires
localparam REFRESH_TIMER_DIV =
USER_REFRESH == "ON" ? 0 :
(tREFI-((tRCD+((CL+4)*tCK)+tRP)*nBANK_MACHS)) / MAINT_PRESCALER_PERIOD;
// Periodic read (RESERVED - not currently required or supported in 7 series)
// tPRDI should only be set to 0
// localparam tPRDI = 0; // Do NOT change.
localparam PERIODIC_RD_TIMER_DIV = tPRDI / MAINT_PRESCALER_PERIOD;
// Convert maintenance prescaler from ps to ns
localparam MAINT_PRESCALER_PERIOD_NS = MAINT_PRESCALER_PERIOD / 1000;
// Maintenance prescaler divisor for ZQ calibration (ZQCS) timer
localparam ZQ_TIMER_DIV = tZQI / MAINT_PRESCALER_PERIOD_NS;
// Bus width required to broadcast a single bit rank signal among all the
// bank machines - 1 bit per rank, per bank
localparam RANK_BM_BV_WIDTH = nBANK_MACHS * RANKS;
//***************************************************************************
// Define 2T, CWL-even mode to enable multi-fabric-cycle 2T commands
//***************************************************************************
localparam EVEN_CWL_2T_MODE =
((ADDR_CMD_MODE == "2T") && (!(CWL % 2))) ? "ON" : "OFF";
//***************************************************************************
// Reserved feature control.
//***************************************************************************
// Open page wait mode is reserved.
// nOP_WAIT is the number of states a bank machine will park itself
// on an otherwise inactive open page before closing the page. If
// nOP_WAIT == 0, open page wait mode is disabled. If nOP_WAIT == -1,
// the bank machine will remain parked until the pool of idle bank machines
// are less than LOW_IDLE_CNT. At which point parked bank machines
// are selected to exit until the number of idle bank machines exceeds the
// LOW_IDLE_CNT.
localparam nOP_WAIT = 0; // Open page mode
localparam LOW_IDLE_CNT = 0; // Low idle bank machine threshold
//***************************************************************************
// Internal wires
//***************************************************************************
wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r;
wire [ROW_WIDTH-1:0] col_a;
wire [BANK_WIDTH-1:0] col_ba;
wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
wire col_periodic_rd;
wire [RANK_WIDTH-1:0] col_ra;
wire col_rmw;
wire col_rd_wr;
wire [ROW_WIDTH-1:0] col_row;
wire col_size;
wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
wire dq_busy_data;
wire ecc_status_valid;
wire [RANKS-1:0] inhbt_act_faw_r;
wire [RANKS-1:0] inhbt_rd;
wire [RANKS-1:0] inhbt_wr;
wire insert_maint_r1;
wire [RANK_WIDTH-1:0] maint_rank_r;
wire maint_req_r;
wire maint_wip_r;
wire maint_zq_r;
wire maint_sre_r;
wire maint_srx_r;
wire periodic_rd_ack_r;
wire periodic_rd_r;
wire [RANK_WIDTH-1:0] periodic_rd_rank_r;
wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r;
wire rd_rmw;
wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r;
wire [nBANK_MACHS-1:0] sending_col;
wire [nBANK_MACHS-1:0] sending_row;
wire sent_col;
wire sent_col_r;
wire wr_ecc_buf;
wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r;
// MC/PHY optional pipeline stage support
wire [nCK_PER_CLK-1:0] mc_ras_n_ns;
wire [nCK_PER_CLK-1:0] mc_cas_n_ns;
wire [nCK_PER_CLK-1:0] mc_we_n_ns;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address_ns;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank_ns;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_ns;
wire [1:0] mc_odt_ns;
wire [nCK_PER_CLK-1:0] mc_cke_ns;
wire [3:0] mc_aux_out0_ns;
wire [3:0] mc_aux_out1_ns;
wire [1:0] mc_rank_cnt_ns = col_ra;
wire [2:0] mc_cmd_ns;
wire [5:0] mc_data_offset_ns;
wire [5:0] mc_data_offset_1_ns;
wire [5:0] mc_data_offset_2_ns;
wire [1:0] mc_cas_slot_ns;
wire mc_wrdata_en_ns;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr_ns;
wire wr_data_en_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset_ns;
integer i;
// MC Read idle support
wire col_read_fifo_empty;
wire mc_read_idle_ns;
reg mc_read_idle_r;
// MC Maintenance in progress with bus idle indication
wire maint_ref_zq_wip;
wire mc_ref_zq_wip_ns;
reg mc_ref_zq_wip_r;
//***************************************************************************
// Function cdiv
// Description:
// This function performs ceiling division (divide and round-up)
// Inputs:
// num: integer to be divided
// div: divisor
// Outputs:
// cdiv: result of ceiling division (num/div, rounded up)
//***************************************************************************
function integer cdiv (input integer num, input integer div);
begin
// perform division, then add 1 if and only if remainder is non-zero
cdiv = (num/div) + (((num%div)>0) ? 1 : 0);
end
endfunction // cdiv
//***************************************************************************
// Optional pipeline register stage on MC/PHY interface
//***************************************************************************
generate
if (CMD_PIPE_PLUS1 == "ON") begin : cmd_pipe_plus // register interface
always @(posedge clk) begin
mc_address <= #TCQ mc_address_ns;
mc_bank <= #TCQ mc_bank_ns;
mc_cas_n <= #TCQ mc_cas_n_ns;
mc_cs_n <= #TCQ mc_cs_n_ns;
mc_odt <= #TCQ mc_odt_ns;
mc_cke <= #TCQ mc_cke_ns;
mc_aux_out0 <= #TCQ mc_aux_out0_ns;
mc_aux_out1 <= #TCQ mc_aux_out1_ns;
mc_cmd <= #TCQ mc_cmd_ns;
mc_ras_n <= #TCQ mc_ras_n_ns;
mc_we_n <= #TCQ mc_we_n_ns;
mc_data_offset <= #TCQ mc_data_offset_ns;
mc_data_offset_1 <= #TCQ mc_data_offset_1_ns;
mc_data_offset_2 <= #TCQ mc_data_offset_2_ns;
mc_cas_slot <= #TCQ mc_cas_slot_ns;
mc_wrdata_en <= #TCQ mc_wrdata_en_ns;
mc_rank_cnt <= #TCQ mc_rank_cnt_ns;
wr_data_addr <= #TCQ wr_data_addr_ns;
wr_data_en <= #TCQ wr_data_en_ns;
wr_data_offset <= #TCQ wr_data_offset_ns;
end // always @ (posedge clk)
end // block: cmd_pipe_plus
else begin : cmd_pipe_plus0 // don't register interface
always @( mc_address_ns or mc_aux_out0_ns or mc_aux_out1_ns or
mc_bank_ns or mc_cas_n_ns or mc_cmd_ns or mc_cs_n_ns or
mc_odt_ns or mc_cke_ns or mc_data_offset_ns or
mc_data_offset_1_ns or mc_data_offset_2_ns or mc_rank_cnt_ns or
mc_ras_n_ns or mc_we_n_ns or mc_wrdata_en_ns or
wr_data_addr_ns or wr_data_en_ns or wr_data_offset_ns or
mc_cas_slot_ns)
begin
mc_address = #TCQ mc_address_ns;
mc_bank = #TCQ mc_bank_ns;
mc_cas_n = #TCQ mc_cas_n_ns;
mc_cs_n = #TCQ mc_cs_n_ns;
mc_odt = #TCQ mc_odt_ns;
mc_cke = #TCQ mc_cke_ns;
mc_aux_out0 = #TCQ mc_aux_out0_ns;
mc_aux_out1 = #TCQ mc_aux_out1_ns;
mc_cmd = #TCQ mc_cmd_ns;
mc_ras_n = #TCQ mc_ras_n_ns;
mc_we_n = #TCQ mc_we_n_ns;
mc_data_offset = #TCQ mc_data_offset_ns;
mc_data_offset_1 = #TCQ mc_data_offset_1_ns;
mc_data_offset_2 = #TCQ mc_data_offset_2_ns;
mc_cas_slot = #TCQ mc_cas_slot_ns;
mc_wrdata_en = #TCQ mc_wrdata_en_ns;
mc_rank_cnt = #TCQ mc_rank_cnt_ns;
wr_data_addr = #TCQ wr_data_addr_ns;
wr_data_en = #TCQ wr_data_en_ns;
wr_data_offset = #TCQ wr_data_offset_ns;
end // always @ (...
end // block: cmd_pipe_plus0
endgenerate
//***************************************************************************
// Indicate when there are no pending reads so that input features can be
// powered down
//***************************************************************************
assign mc_read_idle_ns = col_read_fifo_empty & init_calib_complete;
always @(posedge clk) mc_read_idle_r <= #TCQ mc_read_idle_ns;
assign mc_read_idle = mc_read_idle_r;
//***************************************************************************
// Indicate when there is a refresh in progress and the bus is idle so that
// tap adjustments can be made
//***************************************************************************
assign mc_ref_zq_wip_ns = maint_ref_zq_wip && col_read_fifo_empty;
always @(posedge clk) mc_ref_zq_wip_r <= mc_ref_zq_wip_ns;
assign mc_ref_zq_wip = mc_ref_zq_wip_r;
//***************************************************************************
// Manage rank-level timing and maintanence
//***************************************************************************
mig_7series_v2_3_rank_mach #
(
// Parameters
.BURST_MODE (BURST_MODE),
.CL (CL),
.CWL (CWL),
.CS_WIDTH (CS_WIDTH),
.DQRD2DQWR_DLY (DQRD2DQWR_DLY),
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.nCKESR (nCKESR),
.nCK_PER_CLK (nCK_PER_CLK),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV)
)
rank_mach0
(
// Outputs
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_ref_zq_wip (maint_ref_zq_wip),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
// Inputs
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.col_rd_wr (col_rd_wr),
.clk (clk),
.init_calib_complete (init_calib_complete),
.insert_maint_r1 (insert_maint_r1),
.maint_wip_r (maint_wip_r),
.periodic_rd_ack_r (periodic_rd_ack_r),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.rst (rst),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0])
);
//***************************************************************************
// Manage requests, reordering and bank timing
//***************************************************************************
mig_7series_v2_3_bank_mach #
(
// Parameters
.TCQ (TCQ),
.EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.CL (CL_M),
.CWL (CWL_M),
.CKE_ODT_AUX (CKE_ODT_AUX),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.LOW_IDLE_CNT (LOW_IDLE_CNT),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.nOP_WAIT (nOP_WAIT),
.nRAS (nRAS),
.nRCD (nRCD),
.nRFC (nRFC),
.nRP (nRP),
.nRTP (nRTP),
.nSLOTS (nSLOTS),
.nWR (nWR),
.nXSDLL (tXSDLL),
.ORDERING (ORDERING),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.STARVE_LIMIT (STARVE_LIMIT),
.tZQCS (tZQCS)
)
bank_mach0
(
// Outputs
.accept (accept),
.accept_ns (accept_ns),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank_ns),
.mc_address (mc_address_ns),
.mc_ras_n (mc_ras_n_ns),
.mc_cas_n (mc_cas_n_ns),
.mc_we_n (mc_we_n_ns),
.mc_cs_n (mc_cs_n_ns),
.mc_odt (mc_odt_ns),
.mc_cke (mc_cke_ns),
.mc_aux_out0 (mc_aux_out0_ns),
.mc_aux_out1 (mc_aux_out1_ns),
.mc_cmd (mc_cmd_ns),
.mc_data_offset (mc_data_offset_ns),
.mc_data_offset_1 (mc_data_offset_1_ns),
.mc_data_offset_2 (mc_data_offset_2_ns),
.mc_cas_slot (mc_cas_slot_ns),
.insert_maint_r1 (insert_maint_r1),
.maint_wip_r (maint_wip_r),
.periodic_rd_ack_r (periodic_rd_ack_r),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sent_col (sent_col),
.sent_col_r (sent_col_r),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
// Inputs
.bank (bank[BANK_WIDTH-1:0]),
.calib_rddata_offset (calib_rd_data_offset),
.calib_rddata_offset_1 (calib_rd_data_offset_1),
.calib_rddata_offset_2 (calib_rd_data_offset_2),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.init_calib_complete (init_calib_complete),
.phy_rddata_valid (phy_rddata_valid),
.dq_busy_data (dq_busy_data),
.hi_priority (hi_priority),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rank (rank[RANK_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_rmw (rd_rmw),
.row (row[ROW_WIDTH-1:0]),
.rst (rst),
.size (size),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.use_addr (use_addr)
);
//***************************************************************************
// Manage DQ bus
//***************************************************************************
mig_7series_v2_3_col_mach #
(
// Parameters
.TCQ (TCQ),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DELAY_WR_DATA_CNTRL (DELAY_WR_DATA_CNTRL),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.nPHY_WRLAT (nPHY_WRLAT),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH)
)
col_mach0
(
// Outputs
.mc_wrdata_en (mc_wrdata_en_ns),
.dq_busy_data (dq_busy_data),
.ecc_err_addr (ecc_err_addr[MC_ERR_ADDR_WIDTH-1:0]),
.ecc_status_valid (ecc_status_valid),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.rd_rmw (rd_rmw),
.wr_data_addr (wr_data_addr_ns),
.wr_data_en (wr_data_en_ns),
.wr_data_offset (wr_data_offset_ns),
.wr_ecc_buf (wr_ecc_buf),
.col_read_fifo_empty (col_read_fifo_empty),
// Inputs
.clk (clk),
.rst (rst),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col)
);
//***************************************************************************
// Implement ECC
//***************************************************************************
// Total ECC word length = ECC code width + Data width
localparam CODE_WIDTH = DATA_WIDTH + ECC_WIDTH;
generate
if (ECC == "OFF") begin : ecc_off
assign rd_data = phy_rd_data;
assign mc_wrdata = wr_data;
assign mc_wrdata_mask = wr_data_mask;
assign ecc_single = 4'b0;
assign ecc_multiple = 4'b0;
end
else begin : ecc_on
wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_i;
// Merge and encode
mig_7series_v2_3_ecc_merge_enc #
(
// Parameters
.TCQ (TCQ),
.CODE_WIDTH (CODE_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ECC_WIDTH (ECC_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_merge_enc0
(
// Outputs
.mc_wrdata (mc_wrdata_i),
.mc_wrdata_mask (mc_wrdata_mask),
// Inputs
.clk (clk),
.rst (rst),
.h_rows (h_rows),
.rd_merge_data (rd_merge_data),
.raw_not_ecc (raw_not_ecc),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask)
);
// Decode and fix
mig_7series_v2_3_ecc_dec_fix #
(
// Parameters
.TCQ (TCQ),
.CODE_WIDTH (CODE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ECC_WIDTH (ECC_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_dec_fix0
(
// Outputs
.ecc_multiple (ecc_multiple),
.ecc_single (ecc_single),
.rd_data (rd_data),
// Inputs
.clk (clk),
.rst (rst),
.correct_en (correct_en),
.phy_rddata (phy_rd_data),
.ecc_status_valid (ecc_status_valid),
.h_rows (h_rows)
);
// ECC Buffer
mig_7series_v2_3_ecc_buf #
(
// Parameters
.TCQ (TCQ),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_buf0
(
// Outputs
.rd_merge_data (rd_merge_data),
// Inputs
.clk (clk),
.rst (rst),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_offset (wr_data_offset),
.wr_ecc_buf (wr_ecc_buf)
);
// Generate ECC table
mig_7series_v2_3_ecc_gen #
(
// Parameters
.CODE_WIDTH (CODE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.ECC_WIDTH (ECC_WIDTH)
)
ecc_gen0
(
// Outputs
.h_rows (h_rows)
);
if (ECC == "ON") begin : gen_fi_xor_inst
reg mc_wrdata_en_r;
wire mc_wrdata_en_i;
always @(posedge clk) begin
mc_wrdata_en_r <= mc_wrdata_en;
end
assign mc_wrdata_en_i = mc_wrdata_en_r;
mig_7series_v2_3_fi_xor #(
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
fi_xor0
(
.clk (clk),
.wrdata_in (mc_wrdata_i),
.wrdata_out (mc_wrdata),
.wrdata_en (mc_wrdata_en_i),
.fi_xor_we (fi_xor_we),
.fi_xor_wrdata (fi_xor_wrdata)
);
end
else begin : gen_wrdata_passthru
assign mc_wrdata = mc_wrdata_i;
end
`ifdef DISPLAY_H_MATRIX
integer i;
always @(negedge rst) begin
$display ("**********************************************");
$display ("H Matrix:");
for (i=0; i<ECC_WIDTH; i=i+1)
$display ("%b", h_rows[i*CODE_WIDTH+:CODE_WIDTH]);
$display ("**********************************************");
end
`endif
end
endgenerate
endmodule // mc
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_dqs_found_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Read leveling calibration logic
// NOTES:
// 1. Phaser_In DQSFOUND calibration
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $
**$Date: 2011/06/02 08:35:08 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_dqs_found_cal_hr #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter nCL = 5, // Read CAS latency
parameter AL = "0",
parameter nCWL = 5, // Write CAS latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter RANKS = 1, // # of memory ranks in the system
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate
parameter N_CTL_LANES = 3, // Number of control byte lanes
parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)
parameter HIGHEST_BANK = 3, // Sum of I/O Banks
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf
)
(
input clk,
input rst,
input dqsfound_retry,
// From phy_init
input pi_dqs_found_start,
input detect_pi_found_dqs,
input prech_done,
// DQSFOUND per Phaser_IN
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
// To phy_init
output [5:0] rd_data_offset_0,
output [5:0] rd_data_offset_1,
output [5:0] rd_data_offset_2,
output pi_dqs_found_rank_done,
output pi_dqs_found_done,
output reg pi_dqs_found_err,
output [6*RANKS-1:0] rd_data_offset_ranks_0,
output [6*RANKS-1:0] rd_data_offset_ranks_1,
output [6*RANKS-1:0] rd_data_offset_ranks_2,
output reg dqsfound_retry_done,
output reg dqs_found_prech_req,
//To MC
output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,
input [8:0] po_counter_read_val,
output rd_data_offset_cal_done,
output fine_adjust_done,
output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,
output reg ck_po_stg2_f_indec,
output reg ck_po_stg2_f_en,
output [255:0] dbg_dqs_found_cal
);
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Added to reduce simulation time
localparam LATENCY_FACTOR = 13;
localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),
(DATA_CTL_B4[2] & BYTE_LANES_B4[2]),
(DATA_CTL_B4[1] & BYTE_LANES_B4[1]),
(DATA_CTL_B4[0] & BYTE_LANES_B4[0]),
(DATA_CTL_B3[3] & BYTE_LANES_B3[3]),
(DATA_CTL_B3[2] & BYTE_LANES_B3[2]),
(DATA_CTL_B3[1] & BYTE_LANES_B3[1]),
(DATA_CTL_B3[0] & BYTE_LANES_B3[0]),
(DATA_CTL_B2[3] & BYTE_LANES_B2[3]),
(DATA_CTL_B2[2] & BYTE_LANES_B2[2]),
(DATA_CTL_B2[1] & BYTE_LANES_B2[1]),
(DATA_CTL_B2[0] & BYTE_LANES_B2[0]),
(DATA_CTL_B1[3] & BYTE_LANES_B1[3]),
(DATA_CTL_B1[2] & BYTE_LANES_B1[2]),
(DATA_CTL_B1[1] & BYTE_LANES_B1[1]),
(DATA_CTL_B1[0] & BYTE_LANES_B1[0]),
(DATA_CTL_B0[3] & BYTE_LANES_B0[3]),
(DATA_CTL_B0[2] & BYTE_LANES_B0[2]),
(DATA_CTL_B0[1] & BYTE_LANES_B0[1]),
(DATA_CTL_B0[0] & BYTE_LANES_B0[0])};
localparam FINE_ADJ_IDLE = 4'h0;
localparam RST_POSTWAIT = 4'h1;
localparam RST_POSTWAIT1 = 4'h2;
localparam RST_WAIT = 4'h3;
localparam FINE_ADJ_INIT = 4'h4;
localparam FINE_INC = 4'h5;
localparam FINE_INC_WAIT = 4'h6;
localparam FINE_INC_PREWAIT = 4'h7;
localparam DETECT_PREWAIT = 4'h8;
localparam DETECT_DQSFOUND = 4'h9;
localparam PRECH_WAIT = 4'hA;
localparam FINE_DEC = 4'hB;
localparam FINE_DEC_WAIT = 4'hC;
localparam FINE_DEC_PREWAIT = 4'hD;
localparam FINAL_WAIT = 4'hE;
localparam FINE_ADJ_DONE = 4'hF;
integer k,l,m,n,p,q,r,s;
reg dqs_found_start_r;
reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];
reg rank_done_r;
reg rank_done_r1;
reg dqs_found_done_r;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;
reg init_dqsfound_done_r;
reg init_dqsfound_done_r1;
reg init_dqsfound_done_r2;
reg init_dqsfound_done_r3;
reg init_dqsfound_done_r4;
reg init_dqsfound_done_r5;
reg [1:0] rnk_cnt_r;
reg [2:0 ] final_do_index[0:RANKS-1];
reg [5:0 ] final_do_max[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;
reg [10*HIGHEST_BANK-1:0] retry_cnt;
reg dqsfound_retry_r1;
wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;
// CK/Control byte lanes fine adjust stage
reg fine_adjust;
reg [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [3:0] fine_adj_state_r;
reg fine_adjust_done_r;
reg rst_dqs_find;
reg rst_dqs_find_r1;
reg rst_dqs_find_r2;
reg [5:0] init_dec_cnt;
reg [5:0] dec_cnt;
reg [5:0] inc_cnt;
reg final_dec_done;
reg init_dec_done;
reg first_fail_detect;
reg second_fail_detect;
reg [5:0] first_fail_taps;
reg [5:0] second_fail_taps;
reg [5:0] stable_pass_cnt;
reg [3:0] detect_rd_cnt;
//***************************************************************************
// Debug signals
//
//***************************************************************************
assign dbg_dqs_found_cal[5:0] = first_fail_taps;
assign dbg_dqs_found_cal[11:6] = second_fail_taps;
assign dbg_dqs_found_cal[12] = first_fail_detect;
assign dbg_dqs_found_cal[13] = second_fail_detect;
assign dbg_dqs_found_cal[14] = fine_adjust_done_r;
assign pi_dqs_found_rank_done = rank_done_r;
assign pi_dqs_found_done = dqs_found_done_r;
generate
genvar rnk_cnt;
if (HIGHEST_BANK == 3) begin // Three Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];
end
end else if (HIGHEST_BANK == 2) begin // Two Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end else begin // Single Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end
endgenerate
// final_data_offset is used during write calibration and during
// normal operation. One rd_data_offset value per rank for entire
// interface
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :
final_data_offset[rnk_cnt_r][12+:6];
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = 'd0;
end else begin
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = 'd0;
assign rd_data_offset_2 = 'd0;
end
endgenerate
assign rd_data_offset_cal_done = init_dqsfound_done_r;
assign fine_adjust_lane_cnt = ctl_lane_cnt;
//**************************************************************************
// DQSFOUND all and any generation
// pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are
// asserted
// pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx
// is asserted
//**************************************************************************
generate
if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))
assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;
else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))
assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))
assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))
assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};
endgenerate
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found
pi_dqs_found_all_bank[k] <= #TCQ 'b0;
pi_dqs_found_any_bank[k] <= #TCQ 'b0;
end
end else if (pi_dqs_found_start) begin
for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found
pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &
(!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &
(!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &
(!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);
pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |
(DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |
(DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |
(DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);
end
end
end
always @(posedge clk) begin
pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;
pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;
end
//*****************************************************************************
// Counter to increase number of 4 back-to-back reads per rd_data_offset and
// per CK/A/C tap value
//*****************************************************************************
always @(posedge clk) begin
if (rst || (detect_rd_cnt == 'd0))
detect_rd_cnt <= #TCQ NUM_READS;
else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
end
//**************************************************************************
// Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls
//
//**************************************************************************
assign fine_adjust_done = fine_adjust_done_r;
always @(posedge clk) begin
rst_dqs_find_r1 <= #TCQ rst_dqs_find;
rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;
end
always @(posedge clk) begin
if(rst)begin
fine_adjust <= #TCQ 1'b0;
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;
fine_adjust_done_r <= #TCQ 1'b0;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b0;
init_dec_cnt <= #TCQ 'd31;
dec_cnt <= #TCQ 'd0;
inc_cnt <= #TCQ 'd0;
init_dec_done <= #TCQ 1'b0;
final_dec_done <= #TCQ 1'b0;
first_fail_detect <= #TCQ 1'b0;
second_fail_detect <= #TCQ 1'b0;
first_fail_taps <= #TCQ 'd0;
second_fail_taps <= #TCQ 'd0;
stable_pass_cnt <= #TCQ 'd0;
dqs_found_prech_req<= #TCQ 1'b0;
end else begin
case (fine_adj_state_r)
FINE_ADJ_IDLE: begin
if (init_dqsfound_done_r5) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
rst_dqs_find <= #TCQ 1'b0;
end else begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
rst_dqs_find <= #TCQ 1'b1;
end
end
end
RST_WAIT: begin
if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin
rst_dqs_find <= #TCQ 1'b0;
if (|init_dec_cnt)
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else if (final_dec_done)
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
else
fine_adj_state_r <= #TCQ RST_POSTWAIT;
end
end
RST_POSTWAIT: begin
fine_adj_state_r <= #TCQ RST_POSTWAIT1;
end
RST_POSTWAIT1: begin
fine_adj_state_r <= #TCQ FINE_ADJ_INIT;
end
FINE_ADJ_INIT: begin
//if (detect_pi_found_dqs && (inc_cnt < 'd63))
fine_adj_state_r <= #TCQ FINE_INC;
end
FINE_INC: begin
fine_adj_state_r <= #TCQ FINE_INC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b1;
ck_po_stg2_f_en <= #TCQ 1'b1;
if (ctl_lane_cnt == N_CTL_LANES-1)
inc_cnt <= #TCQ inc_cnt + 1;
end
FINE_INC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
end
FINE_INC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_INC;
end
DETECT_PREWAIT: begin
if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))
fine_adj_state_r <= #TCQ DETECT_DQSFOUND;
else
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
DETECT_DQSFOUND: begin
if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ 'd0;
if (~first_fail_detect && (inc_cnt == 'd63)) begin
// First failing tap detected at 63 taps
// then decrement to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin
// First failing tap detected at greater than 30 taps
// then stop looking for second edge and decrement
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ (inc_cnt>>1) + 1;
end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin
// First failing tap detected, continue incrementing
// until either second failing tap detected or 63
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin
// Consecutive 30 taps of passing region was not found
// continue incrementing
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt == 'd63)) begin
if (stable_pass_cnt < 'd30) begin
// Consecutive 30 taps of passing region was not found
// from tap 0 to 63 so decrement back to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else begin
// Consecutive 30 taps of passing region was found
// between first_fail_taps and 63
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end else begin
// Second failing tap detected, decrement to center of
// failing taps
second_fail_detect <= #TCQ 1'b1;
second_fail_taps <= #TCQ inc_cnt;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
fine_adj_state_r <= #TCQ FINE_DEC;
end
end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) ||
(inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else if (inc_cnt < 'd63) begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end else begin
fine_adj_state_r <= #TCQ FINE_DEC;
if (~first_fail_detect || (first_fail_taps > 'd33))
// No failing taps detected, decrement by 31
dec_cnt <= #TCQ 'd32;
//else if (first_fail_detect && (stable_pass_cnt > 'd28))
// // First failing tap detected between 0 and 34
// // decrement midpoint between 63 and failing tap
// dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
else
// First failing tap detected
// decrement to midpoint between 63 and failing tap
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end
end
PRECH_WAIT: begin
if (prech_done) begin
dqs_found_prech_req <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
end
FINE_DEC: begin
fine_adj_state_r <= #TCQ FINE_DEC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b1;
if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))
init_dec_cnt <= #TCQ init_dec_cnt - 1;
else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))
dec_cnt <= #TCQ dec_cnt - 1;
end
FINE_DEC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else begin
fine_adj_state_r <= #TCQ FINAL_WAIT;
if ((init_dec_cnt == 'd0) && ~init_dec_done)
init_dec_done <= #TCQ 1'b1;
else
final_dec_done <= #TCQ 1'b1;
end
end
end
FINE_DEC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_DEC;
end
FINAL_WAIT: begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
FINE_ADJ_DONE: begin
if (&pi_dqs_found_all_bank) begin
fine_adjust_done_r <= #TCQ 1'b1;
rst_dqs_find <= #TCQ 1'b0;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
end
end
endcase
end
end
//*****************************************************************************
always@(posedge clk)
dqs_found_start_r <= #TCQ pi_dqs_found_start;
always @(posedge clk) begin
if (rst)
rnk_cnt_r <= #TCQ 2'b00;
else if (init_dqsfound_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r;
else if (rank_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
end
//*****************************************************************
// Read data_offset calibration done signal
//*****************************************************************
always @(posedge clk) begin
if (rst || (|pi_rst_stg1_cal_r))
init_dqsfound_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank) begin
if (rnk_cnt_r == RANKS-1)
init_dqsfound_done_r <= #TCQ 1'b1;
else
init_dqsfound_done_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst ||
(init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))
rank_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))
rank_done_r <= #TCQ 1'b1;
else
rank_done_r <= #TCQ 1'b0;
end
always @(posedge clk) begin
pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;
pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;
pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;
init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;
init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;
init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;
init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;
init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;
rank_done_r1 <= #TCQ rank_done_r;
dqsfound_retry_r1 <= #TCQ dqsfound_retry;
end
always @(posedge clk) begin
if (rst)
dqs_found_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&
(fine_adj_state_r == FINE_ADJ_DONE))
dqs_found_done_r <= #TCQ 1'b1;
else
dqs_found_done_r <= #TCQ 1'b0;
end
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)
pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[2]) ||
(pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[20+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[2])
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;
else
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[2] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[2] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop
rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&
//(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][12+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] + 1;
end
//*****************************************************************************
// Two I/O Bank Interface
//*****************************************************************************
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
//*****************************************************************************
// One I/O Bank Interface
//*****************************************************************************
end else begin // One I/O Bank Interface
// Read data offset value for all DQS in Bank0
always @(posedge clk) begin
if (rst) begin
for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop
rd_byte_data_offset[l] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r]
<= #TCQ rd_byte_data_offset[rnk_cnt_r] + 1;
end
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted even with 3 dqfound retries
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk) begin
if (rst)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};
else if (rst_dqs_find)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};
else
pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;
end
// Final read data offset value to be used during write calibration and
// normal operation
generate
genvar i;
genvar j;
for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop
reg [5:0] final_do_cand [RANKS-1:0];
// combinatorially select the candidate offset for the bank
// indexed by final_do_index
if (HIGHEST_BANK == 3) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = final_data_offset[i][17:12];
default: final_do_cand[i] = 'd0;
endcase
end
end else if (HIGHEST_BANK == 2) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end else begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = 'd0;
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end
always @(posedge clk) begin
if (rst)
final_do_max[i] <= #TCQ 0;
else begin
final_do_max[i] <= #TCQ final_do_max[i]; // default
case (final_do_index[i])
3'b000: if ( | DATA_PRESENT[3:0])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b001: if ( | DATA_PRESENT[7:4])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b010: if ( | DATA_PRESENT[11:8])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
default:
final_do_max[i] <= #TCQ final_do_max[i];
endcase
end
end
always @(posedge clk)
if (rst) begin
final_do_index[i] <= #TCQ 0;
end
else begin
final_do_index[i] <= #TCQ final_do_index[i] + 1;
end
for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop
always @(posedge clk) begin
if (rst) begin
final_data_offset[i][6*j+:6] <= #TCQ 'b0;
end
else begin
//if (dqsfound_retry[j])
// final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
//else
if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin
if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane
final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
if (CWL_M % 2) // odd latency CAS slot 1
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;
else // even latency CAS slot 0
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
end
end
else if (init_dqsfound_done_r5 ) begin
if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes
final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];
final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];
end
end
end
end
end
end
endgenerate
// Error generation in case pi_found_dqs signal from Phaser_IN
// is not asserted when a common rddata_offset value is used
always @(posedge clk) begin
pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_wr_data.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// User interface write data buffer. Consists of four counters,
// a pointer RAM and the write data storage RAM.
//
// All RAMs are implemented with distributed RAM.
//
// Whe ordering is set to STRICT or NORM, data moves through
// the write data buffer in strictly FIFO order. In RELAXED
// mode, data may be retired from the write data RAM in any
// order relative to the input order. This implementation
// supports all ordering modes.
//
// The pointer RAM stores a list of pointers to the write data storage RAM.
// This is a list of vacant entries. As data is written into the RAM, a
// pointer is pulled from the pointer RAM and used to index the write
// operation. In a semi autonomously manner, pointers are also pulled, in
// the same order, and provided to the command port as the data_buf_addr.
//
// When the MC reads data from the write data buffer, it uses the
// data_buf_addr provided with the command to extract the data from the
// write data buffer. It also writes this pointer into the end
// of the pointer RAM.
//
// The occupancy counter keeps track of how many entries are valid
// in the write data storage RAM. app_wdf_rdy and app_rdy will be
// de-asserted when there is no more storage in the write data buffer.
//
// Three sequentially incrementing counters/indexes are used to maintain
// and use the contents of the pointer RAM.
//
// The write buffer write data address index generates the pointer
// used to extract the write data address from the pointer RAM. It
// is incremented with each buffer write. The counter is actually one
// ahead of the current write address so that the actual data buffer
// write address can be registered to give a full state to propagate to
// the write data distributed RAMs.
//
// The data_buf_addr counter is used to extract the data_buf_addr for
// the command port. It is incremented as each command is written
// into the MC.
//
// The read data index points to the end of the list of free
// buffers. When the MC fetches data from the write data buffer, it
// provides the buffer address. The buffer address is used to fetch
// the data, but is also written into the pointer at the location indicated
// by the read data index.
//
// Enter and exiting a buffer full condition generates corner cases. Upon
// entering a full condition, incrementing the write buffer write data
// address index must be inhibited. When exiting the full condition,
// the just arrived pointer must propagate through the pointer RAM, then
// indexed by the current value of the write buffer write data
// address counter, the value is registered in the write buffer write
// data address register, then the counter can be advanced.
//
// The pointer RAM must be initialized with valid data after reset. This is
// accomplished by stepping through each pointer RAM entry and writing
// the locations address into the pointer RAM. For the FIFO modes, this means
// that buffer address will always proceed in a sequential order. In the
// RELAXED mode, the original write traversal will be in sequential
// order, but once the MC begins to retire out of order, the entries in
// the pointer RAM will become randomized. The ui_rd_data module provides
// the control information for the initialization process.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ui_wr_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter ECC = "OFF",
parameter nCK_PER_CLK = 2 ,
parameter ECC_TEST = "OFF",
parameter CWL = 5
)
(/*AUTOARG*/
// Outputs
app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask,
raw_not_ecc,
// Inputs
rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren,
app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted,
ram_init_done_r, ram_init_addr
);
input rst;
input clk;
input [APP_DATA_WIDTH-1:0] app_wdf_data;
input [APP_MASK_WIDTH-1:0] app_wdf_mask;
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc;
input app_wdf_wren;
input app_wdf_end;
reg [APP_DATA_WIDTH-1:0] app_wdf_data_r1;
reg [APP_MASK_WIDTH-1:0] app_wdf_mask_r1;
reg [2*nCK_PER_CLK-1:0] app_raw_not_ecc_r1 = 4'b0;
reg app_wdf_wren_r1;
reg app_wdf_end_r1;
reg app_wdf_rdy_r;
//Adding few copies of the app_wdf_rdy_r signal in order to meet
//timing. This is signal has a very high fanout. So grouped into
//few functional groups and alloted one copy per group.
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy1;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy2;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy3;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy4;
wire [APP_DATA_WIDTH-1:0] app_wdf_data_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_data_r1 : app_wdf_data;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_mask_r1 : app_wdf_mask;
wire app_wdf_wren_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_wren_r1 : app_wdf_wren);
wire app_wdf_end_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_end_r1 : app_wdf_end);
generate
if (ECC_TEST != "OFF") begin : ecc_on
always @(app_raw_not_ecc) app_raw_not_ecc_r1 = app_raw_not_ecc;
end
endgenerate
// Be explicit about the latch enable on these registers.
always @(posedge clk) begin
app_wdf_data_r1 <= #TCQ app_wdf_data_ns1;
app_wdf_mask_r1 <= #TCQ app_wdf_mask_ns1;
app_wdf_wren_r1 <= #TCQ app_wdf_wren_ns1;
app_wdf_end_r1 <= #TCQ app_wdf_end_ns1;
end
// The signals wr_data_addr and wr_data_offset come at different
// times depending on ECC and the value of CWL. The data portion
// always needs to look a the raw wires, the control portion needs
// to look at a delayed version when ECC is on and CWL != 8. The
// currently supported write data delays do not require this
// functionality, but preserve for future use.
input wr_data_offset;
input [3:0] wr_data_addr;
reg wr_data_offset_r;
reg [3:0] wr_data_addr_r;
generate
if (ECC == "OFF" || CWL >= 0) begin : pass_wr_addr
always @(wr_data_offset) wr_data_offset_r = wr_data_offset;
always @(wr_data_addr) wr_data_addr_r = wr_data_addr;
end
else begin : delay_wr_addr
always @(posedge clk) wr_data_offset_r <= #TCQ wr_data_offset;
always @(posedge clk) wr_data_addr_r <= #TCQ wr_data_addr;
end
endgenerate
// rd_data_cnt is the pointer RAM index for data read from the write data
// buffer. Ie, its the data on its way out to the DRAM.
input wr_data_en;
wire new_rd_data = wr_data_en && ~wr_data_offset_r;
reg [3:0] rd_data_indx_r;
reg rd_data_upd_indx_r;
generate begin : read_data_indx
reg [3:0] rd_data_indx_ns;
always @(/*AS*/new_rd_data or rd_data_indx_r or rst) begin
rd_data_indx_ns = rd_data_indx_r;
if (rst) rd_data_indx_ns = 5'b0;
else if (new_rd_data) rd_data_indx_ns = rd_data_indx_r + 5'h1;
end
always @(posedge clk) rd_data_indx_r <= #TCQ rd_data_indx_ns;
always @(posedge clk) rd_data_upd_indx_r <= #TCQ new_rd_data;
end
endgenerate
// data_buf_addr_cnt generates the pointer for the pointer RAM on behalf
// of data buf address that comes with the wr_data_en.
// The data buf address is written into the memory
// controller along with the command and address.
input wr_accepted;
reg [3:0] data_buf_addr_cnt_r;
generate begin : data_buf_address_counter
reg [3:0] data_buf_addr_cnt_ns;
always @(/*AS*/data_buf_addr_cnt_r or rst or wr_accepted) begin
data_buf_addr_cnt_ns = data_buf_addr_cnt_r;
if (rst) data_buf_addr_cnt_ns = 4'b0;
else if (wr_accepted) data_buf_addr_cnt_ns =
data_buf_addr_cnt_r + 4'h1;
end
always @(posedge clk) data_buf_addr_cnt_r <= #TCQ data_buf_addr_cnt_ns;
end
endgenerate
// Control writing data into the write data buffer.
wire wdf_rdy_ns;
always @( posedge clk ) begin
app_wdf_rdy_r_copy1 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy2 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy3 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy4 <= #TCQ wdf_rdy_ns;
end
wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1;
wire [3:0] wr_data_pntr;
wire [4:0] wb_wr_data_addr;
wire [4:0] wb_wr_data_addr_w;
reg [3:0] wr_data_indx_r;
generate begin : write_data_control
wire wr_data_addr_le = (wr_data_end && wdf_rdy_ns) ||
(rd_data_upd_indx_r && ~app_wdf_rdy_r_copy1);
// For pointer RAM. Initialize to one since this is one ahead of
// what's being registered in wb_wr_data_addr. Assumes pointer RAM
// has been initialized such that address equals contents.
reg [3:0] wr_data_indx_ns;
always @(/*AS*/rst or wr_data_addr_le or wr_data_indx_r) begin
wr_data_indx_ns = wr_data_indx_r;
if (rst) wr_data_indx_ns = 4'b1;
else if (wr_data_addr_le) wr_data_indx_ns = wr_data_indx_r + 4'h1;
end
always @(posedge clk) wr_data_indx_r <= #TCQ wr_data_indx_ns;
// Take pointer from pointer RAM and set into the write data address.
// Needs to be split into zeroth bit and everything else because synthesis
// tools don't always allow assigning bit vectors seperately. Bit zero of the
// address is computed via an entirely different algorithm.
reg [4:1] wb_wr_data_addr_ns;
reg [4:1] wb_wr_data_addr_r;
always @(/*AS*/rst or wb_wr_data_addr_r or wr_data_addr_le
or wr_data_pntr) begin
wb_wr_data_addr_ns = wb_wr_data_addr_r;
if (rst) wb_wr_data_addr_ns = 4'b0;
else if (wr_data_addr_le) wb_wr_data_addr_ns = wr_data_pntr;
end
always @(posedge clk) wb_wr_data_addr_r <= #TCQ wb_wr_data_addr_ns;
// If we see the first getting accepted, then
// second half is unconditionally accepted.
reg wb_wr_data_addr0_r;
wire wb_wr_data_addr0_ns = ~rst &&
((app_wdf_rdy_r_copy3 && app_wdf_wren_r1 && ~app_wdf_end_r1) ||
(wb_wr_data_addr0_r && ~app_wdf_wren_r1));
always @(posedge clk) wb_wr_data_addr0_r <= #TCQ wb_wr_data_addr0_ns;
assign wb_wr_data_addr = {wb_wr_data_addr_r, wb_wr_data_addr0_r};
assign wb_wr_data_addr_w = {wb_wr_data_addr_ns, wb_wr_data_addr0_ns};
end
endgenerate
// Keep track of how many entries in the queue hold data.
input ram_init_done_r;
output wire app_wdf_rdy;
generate begin : occupied_counter
//reg [4:0] occ_cnt_ns;
//reg [4:0] occ_cnt_r;
//always @(/*AS*/occ_cnt_r or rd_data_upd_indx_r or rst
// or wr_data_end) begin
// occ_cnt_ns = occ_cnt_r;
// if (rst) occ_cnt_ns = 5'b0;
// else case ({wr_data_end, rd_data_upd_indx_r})
// 2'b01 : occ_cnt_ns = occ_cnt_r - 5'b1;
// 2'b10 : occ_cnt_ns = occ_cnt_r + 5'b1;
// endcase // case ({wr_data_end, rd_data_upd_indx_r})
//end
//always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;
//assign wdf_rdy_ns = !(rst || ~ram_init_done_r || occ_cnt_ns[4]);
//always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
//assign app_wdf_rdy = app_wdf_rdy_r;
reg [15:0] occ_cnt;
always @(posedge clk) begin
if ( rst )
occ_cnt <= #TCQ 16'h0000;
else case ({wr_data_end, rd_data_upd_indx_r})
2'b01 : occ_cnt <= #TCQ {1'b0,occ_cnt[15:1]};
2'b10 : occ_cnt <= #TCQ {occ_cnt[14:0],1'b1};
endcase // case ({wr_data_end, rd_data_upd_indx_r})
end
assign wdf_rdy_ns = !(rst || ~ram_init_done_r || (occ_cnt[14] && wr_data_end && ~rd_data_upd_indx_r) || (occ_cnt[15] && ~rd_data_upd_indx_r));
always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
assign app_wdf_rdy = app_wdf_rdy_r;
`ifdef MC_SVA
wr_data_buffer_full: cover property (@(posedge clk)
(~rst && ~app_wdf_rdy_r));
// wr_data_buffer_inc_dec_15: cover property (@(posedge clk)
// (~rst && wr_data_end && rd_data_upd_indx_r && (occ_cnt_r == 5'hf)));
// wr_data_underflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f))));
// wr_data_overflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11))));
`endif
end // block: occupied_counter
endgenerate
// Keep track of how many write requests are in the memory controller. We
// must limit this to 16 because we only have that many data_buf_addrs to
// hand out. Since the memory controller queue and the write data buffer
// queue are distinct, the number of valid entries can be different.
// Throttle request acceptance once there are sixteen write requests in
// the memory controller. Note that there is still a requirement
// for a write reqeusts corresponding write data to be written into the
// write data queue with two states of the request.
output wire wr_req_16;
generate begin : wr_req_counter
reg [4:0] wr_req_cnt_ns;
reg [4:0] wr_req_cnt_r;
always @(/*AS*/rd_data_upd_indx_r or rst or wr_accepted
or wr_req_cnt_r) begin
wr_req_cnt_ns = wr_req_cnt_r;
if (rst) wr_req_cnt_ns = 5'b0;
else case ({wr_accepted, rd_data_upd_indx_r})
2'b01 : wr_req_cnt_ns = wr_req_cnt_r - 5'b1;
2'b10 : wr_req_cnt_ns = wr_req_cnt_r + 5'b1;
endcase // case ({wr_accepted, rd_data_upd_indx_r})
end
always @(posedge clk) wr_req_cnt_r <= #TCQ wr_req_cnt_ns;
assign wr_req_16 = (wr_req_cnt_ns == 5'h10);
`ifdef MC_SVA
wr_req_mc_full: cover property (@(posedge clk) (~rst && wr_req_16));
wr_req_mc_full_inc_dec_15: cover property (@(posedge clk)
(~rst && wr_accepted && rd_data_upd_indx_r && (wr_req_cnt_r == 5'hf)));
wr_req_underflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'b0) && (wr_req_cnt_ns == 5'h1f))));
wr_req_overflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'h10) && (wr_req_cnt_ns == 5'h11))));
`endif
end // block: wr_req_counter
endgenerate
// Instantiate pointer RAM. Made up of RAM32M in single write, two read
// port mode, 2 bit wide mode.
input [3:0] ram_init_addr;
output wire [3:0] wr_data_buf_addr;
localparam PNTR_RAM_CNT = 2;
generate begin : pointer_ram
wire pointer_we = new_rd_data || ~ram_init_done_r;
wire [3:0] pointer_wr_data = ram_init_done_r
? wr_data_addr_r
: ram_init_addr;
wire [3:0] pointer_wr_addr = ram_init_done_r
? rd_data_indx_r
: ram_init_addr;
genvar i;
for (i=0; i<PNTR_RAM_CNT; i=i+1) begin : rams
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(),
.DOB(wr_data_buf_addr[i*2+:2]),
.DOC(wr_data_pntr[i*2+:2]),
.DOD(),
.DIA(2'b0),
.DIB(pointer_wr_data[i*2+:2]),
.DIC(pointer_wr_data[i*2+:2]),
.DID(2'b0),
.ADDRA(5'b0),
.ADDRB({1'b0, data_buf_addr_cnt_r}),
.ADDRC({1'b0, wr_data_indx_r}),
.ADDRD({1'b0, pointer_wr_addr}),
.WE(pointer_we),
.WCLK(clk)
);
end // block : rams
end // block: pointer_ram
endgenerate
// Instantiate write data buffer. Depending on width of DQ bus and
// DRAM CK to fabric ratio, number of RAM32Ms is variable. RAM32Ms are
// used in single write, single read, 6 bit wide mode.
localparam WR_BUF_WIDTH =
APP_DATA_WIDTH + APP_MASK_WIDTH + (ECC_TEST == "OFF" ? 0 : 2*nCK_PER_CLK);
localparam FULL_RAM_CNT = (WR_BUF_WIDTH/6);
localparam REMAINDER = WR_BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] wr_buf_out_data_w;
reg [RAM_WIDTH-1:0] wr_buf_out_data;
generate
begin : write_buffer
wire [RAM_WIDTH-1:0] wr_buf_in_data;
if (REMAINDER == 0)
if (ECC_TEST == "OFF")
assign wr_buf_in_data = {app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data =
{app_raw_not_ecc_r1, app_wdf_mask_ns1, app_wdf_data_ns1};
else
if (ECC_TEST == "OFF")
assign wr_buf_in_data =
{{6-REMAINDER{1'b0}}, app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data = {{6-REMAINDER{1'b0}}, app_raw_not_ecc_r1,//app_raw_not_ecc_r1 is not ff
app_wdf_mask_ns1, app_wdf_data_ns1};
wire [4:0] rd_addr_w;
assign rd_addr_w = {wr_data_addr, wr_data_offset};
always @(posedge clk) wr_buf_out_data <= #TCQ wr_buf_out_data_w;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : wr_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(wr_buf_out_data_w[((i*6)+4)+:2]),
.DOB(wr_buf_out_data_w[((i*6)+2)+:2]),
.DOC(wr_buf_out_data_w[((i*6)+0)+:2]),
.DOD(),
.DIA(wr_buf_in_data[((i*6)+4)+:2]),
.DIB(wr_buf_in_data[((i*6)+2)+:2]),
.DIC(wr_buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(rd_addr_w),
.ADDRB(rd_addr_w),
.ADDRC(rd_addr_w),
.ADDRD(wb_wr_data_addr_w),
.WE(wdf_rdy_ns),
.WCLK(clk)
);
end // block: wr_buffer_ram
end
endgenerate
output [APP_DATA_WIDTH-1:0] wr_data;
output [APP_MASK_WIDTH-1:0] wr_data_mask;
assign {wr_data_mask, wr_data} = wr_buf_out_data[WR_BUF_WIDTH-1:0];
output [2*nCK_PER_CLK-1:0] raw_not_ecc;
generate
if (ECC_TEST == "OFF") assign raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
else assign raw_not_ecc = wr_buf_out_data[WR_BUF_WIDTH-1-:(2*nCK_PER_CLK)];
endgenerate
endmodule // ui_wr_data
// Local Variables:
// verilog-library-directories:(".")
// End:
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_wr_data.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// User interface write data buffer. Consists of four counters,
// a pointer RAM and the write data storage RAM.
//
// All RAMs are implemented with distributed RAM.
//
// Whe ordering is set to STRICT or NORM, data moves through
// the write data buffer in strictly FIFO order. In RELAXED
// mode, data may be retired from the write data RAM in any
// order relative to the input order. This implementation
// supports all ordering modes.
//
// The pointer RAM stores a list of pointers to the write data storage RAM.
// This is a list of vacant entries. As data is written into the RAM, a
// pointer is pulled from the pointer RAM and used to index the write
// operation. In a semi autonomously manner, pointers are also pulled, in
// the same order, and provided to the command port as the data_buf_addr.
//
// When the MC reads data from the write data buffer, it uses the
// data_buf_addr provided with the command to extract the data from the
// write data buffer. It also writes this pointer into the end
// of the pointer RAM.
//
// The occupancy counter keeps track of how many entries are valid
// in the write data storage RAM. app_wdf_rdy and app_rdy will be
// de-asserted when there is no more storage in the write data buffer.
//
// Three sequentially incrementing counters/indexes are used to maintain
// and use the contents of the pointer RAM.
//
// The write buffer write data address index generates the pointer
// used to extract the write data address from the pointer RAM. It
// is incremented with each buffer write. The counter is actually one
// ahead of the current write address so that the actual data buffer
// write address can be registered to give a full state to propagate to
// the write data distributed RAMs.
//
// The data_buf_addr counter is used to extract the data_buf_addr for
// the command port. It is incremented as each command is written
// into the MC.
//
// The read data index points to the end of the list of free
// buffers. When the MC fetches data from the write data buffer, it
// provides the buffer address. The buffer address is used to fetch
// the data, but is also written into the pointer at the location indicated
// by the read data index.
//
// Enter and exiting a buffer full condition generates corner cases. Upon
// entering a full condition, incrementing the write buffer write data
// address index must be inhibited. When exiting the full condition,
// the just arrived pointer must propagate through the pointer RAM, then
// indexed by the current value of the write buffer write data
// address counter, the value is registered in the write buffer write
// data address register, then the counter can be advanced.
//
// The pointer RAM must be initialized with valid data after reset. This is
// accomplished by stepping through each pointer RAM entry and writing
// the locations address into the pointer RAM. For the FIFO modes, this means
// that buffer address will always proceed in a sequential order. In the
// RELAXED mode, the original write traversal will be in sequential
// order, but once the MC begins to retire out of order, the entries in
// the pointer RAM will become randomized. The ui_rd_data module provides
// the control information for the initialization process.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ui_wr_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter ECC = "OFF",
parameter nCK_PER_CLK = 2 ,
parameter ECC_TEST = "OFF",
parameter CWL = 5
)
(/*AUTOARG*/
// Outputs
app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask,
raw_not_ecc,
// Inputs
rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren,
app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted,
ram_init_done_r, ram_init_addr
);
input rst;
input clk;
input [APP_DATA_WIDTH-1:0] app_wdf_data;
input [APP_MASK_WIDTH-1:0] app_wdf_mask;
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc;
input app_wdf_wren;
input app_wdf_end;
reg [APP_DATA_WIDTH-1:0] app_wdf_data_r1;
reg [APP_MASK_WIDTH-1:0] app_wdf_mask_r1;
reg [2*nCK_PER_CLK-1:0] app_raw_not_ecc_r1 = 4'b0;
reg app_wdf_wren_r1;
reg app_wdf_end_r1;
reg app_wdf_rdy_r;
//Adding few copies of the app_wdf_rdy_r signal in order to meet
//timing. This is signal has a very high fanout. So grouped into
//few functional groups and alloted one copy per group.
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy1;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy2;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy3;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy4;
wire [APP_DATA_WIDTH-1:0] app_wdf_data_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_data_r1 : app_wdf_data;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_mask_r1 : app_wdf_mask;
wire app_wdf_wren_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_wren_r1 : app_wdf_wren);
wire app_wdf_end_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_end_r1 : app_wdf_end);
generate
if (ECC_TEST != "OFF") begin : ecc_on
always @(app_raw_not_ecc) app_raw_not_ecc_r1 = app_raw_not_ecc;
end
endgenerate
// Be explicit about the latch enable on these registers.
always @(posedge clk) begin
app_wdf_data_r1 <= #TCQ app_wdf_data_ns1;
app_wdf_mask_r1 <= #TCQ app_wdf_mask_ns1;
app_wdf_wren_r1 <= #TCQ app_wdf_wren_ns1;
app_wdf_end_r1 <= #TCQ app_wdf_end_ns1;
end
// The signals wr_data_addr and wr_data_offset come at different
// times depending on ECC and the value of CWL. The data portion
// always needs to look a the raw wires, the control portion needs
// to look at a delayed version when ECC is on and CWL != 8. The
// currently supported write data delays do not require this
// functionality, but preserve for future use.
input wr_data_offset;
input [3:0] wr_data_addr;
reg wr_data_offset_r;
reg [3:0] wr_data_addr_r;
generate
if (ECC == "OFF" || CWL >= 0) begin : pass_wr_addr
always @(wr_data_offset) wr_data_offset_r = wr_data_offset;
always @(wr_data_addr) wr_data_addr_r = wr_data_addr;
end
else begin : delay_wr_addr
always @(posedge clk) wr_data_offset_r <= #TCQ wr_data_offset;
always @(posedge clk) wr_data_addr_r <= #TCQ wr_data_addr;
end
endgenerate
// rd_data_cnt is the pointer RAM index for data read from the write data
// buffer. Ie, its the data on its way out to the DRAM.
input wr_data_en;
wire new_rd_data = wr_data_en && ~wr_data_offset_r;
reg [3:0] rd_data_indx_r;
reg rd_data_upd_indx_r;
generate begin : read_data_indx
reg [3:0] rd_data_indx_ns;
always @(/*AS*/new_rd_data or rd_data_indx_r or rst) begin
rd_data_indx_ns = rd_data_indx_r;
if (rst) rd_data_indx_ns = 5'b0;
else if (new_rd_data) rd_data_indx_ns = rd_data_indx_r + 5'h1;
end
always @(posedge clk) rd_data_indx_r <= #TCQ rd_data_indx_ns;
always @(posedge clk) rd_data_upd_indx_r <= #TCQ new_rd_data;
end
endgenerate
// data_buf_addr_cnt generates the pointer for the pointer RAM on behalf
// of data buf address that comes with the wr_data_en.
// The data buf address is written into the memory
// controller along with the command and address.
input wr_accepted;
reg [3:0] data_buf_addr_cnt_r;
generate begin : data_buf_address_counter
reg [3:0] data_buf_addr_cnt_ns;
always @(/*AS*/data_buf_addr_cnt_r or rst or wr_accepted) begin
data_buf_addr_cnt_ns = data_buf_addr_cnt_r;
if (rst) data_buf_addr_cnt_ns = 4'b0;
else if (wr_accepted) data_buf_addr_cnt_ns =
data_buf_addr_cnt_r + 4'h1;
end
always @(posedge clk) data_buf_addr_cnt_r <= #TCQ data_buf_addr_cnt_ns;
end
endgenerate
// Control writing data into the write data buffer.
wire wdf_rdy_ns;
always @( posedge clk ) begin
app_wdf_rdy_r_copy1 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy2 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy3 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy4 <= #TCQ wdf_rdy_ns;
end
wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1;
wire [3:0] wr_data_pntr;
wire [4:0] wb_wr_data_addr;
wire [4:0] wb_wr_data_addr_w;
reg [3:0] wr_data_indx_r;
generate begin : write_data_control
wire wr_data_addr_le = (wr_data_end && wdf_rdy_ns) ||
(rd_data_upd_indx_r && ~app_wdf_rdy_r_copy1);
// For pointer RAM. Initialize to one since this is one ahead of
// what's being registered in wb_wr_data_addr. Assumes pointer RAM
// has been initialized such that address equals contents.
reg [3:0] wr_data_indx_ns;
always @(/*AS*/rst or wr_data_addr_le or wr_data_indx_r) begin
wr_data_indx_ns = wr_data_indx_r;
if (rst) wr_data_indx_ns = 4'b1;
else if (wr_data_addr_le) wr_data_indx_ns = wr_data_indx_r + 4'h1;
end
always @(posedge clk) wr_data_indx_r <= #TCQ wr_data_indx_ns;
// Take pointer from pointer RAM and set into the write data address.
// Needs to be split into zeroth bit and everything else because synthesis
// tools don't always allow assigning bit vectors seperately. Bit zero of the
// address is computed via an entirely different algorithm.
reg [4:1] wb_wr_data_addr_ns;
reg [4:1] wb_wr_data_addr_r;
always @(/*AS*/rst or wb_wr_data_addr_r or wr_data_addr_le
or wr_data_pntr) begin
wb_wr_data_addr_ns = wb_wr_data_addr_r;
if (rst) wb_wr_data_addr_ns = 4'b0;
else if (wr_data_addr_le) wb_wr_data_addr_ns = wr_data_pntr;
end
always @(posedge clk) wb_wr_data_addr_r <= #TCQ wb_wr_data_addr_ns;
// If we see the first getting accepted, then
// second half is unconditionally accepted.
reg wb_wr_data_addr0_r;
wire wb_wr_data_addr0_ns = ~rst &&
((app_wdf_rdy_r_copy3 && app_wdf_wren_r1 && ~app_wdf_end_r1) ||
(wb_wr_data_addr0_r && ~app_wdf_wren_r1));
always @(posedge clk) wb_wr_data_addr0_r <= #TCQ wb_wr_data_addr0_ns;
assign wb_wr_data_addr = {wb_wr_data_addr_r, wb_wr_data_addr0_r};
assign wb_wr_data_addr_w = {wb_wr_data_addr_ns, wb_wr_data_addr0_ns};
end
endgenerate
// Keep track of how many entries in the queue hold data.
input ram_init_done_r;
output wire app_wdf_rdy;
generate begin : occupied_counter
//reg [4:0] occ_cnt_ns;
//reg [4:0] occ_cnt_r;
//always @(/*AS*/occ_cnt_r or rd_data_upd_indx_r or rst
// or wr_data_end) begin
// occ_cnt_ns = occ_cnt_r;
// if (rst) occ_cnt_ns = 5'b0;
// else case ({wr_data_end, rd_data_upd_indx_r})
// 2'b01 : occ_cnt_ns = occ_cnt_r - 5'b1;
// 2'b10 : occ_cnt_ns = occ_cnt_r + 5'b1;
// endcase // case ({wr_data_end, rd_data_upd_indx_r})
//end
//always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;
//assign wdf_rdy_ns = !(rst || ~ram_init_done_r || occ_cnt_ns[4]);
//always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
//assign app_wdf_rdy = app_wdf_rdy_r;
reg [15:0] occ_cnt;
always @(posedge clk) begin
if ( rst )
occ_cnt <= #TCQ 16'h0000;
else case ({wr_data_end, rd_data_upd_indx_r})
2'b01 : occ_cnt <= #TCQ {1'b0,occ_cnt[15:1]};
2'b10 : occ_cnt <= #TCQ {occ_cnt[14:0],1'b1};
endcase // case ({wr_data_end, rd_data_upd_indx_r})
end
assign wdf_rdy_ns = !(rst || ~ram_init_done_r || (occ_cnt[14] && wr_data_end && ~rd_data_upd_indx_r) || (occ_cnt[15] && ~rd_data_upd_indx_r));
always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
assign app_wdf_rdy = app_wdf_rdy_r;
`ifdef MC_SVA
wr_data_buffer_full: cover property (@(posedge clk)
(~rst && ~app_wdf_rdy_r));
// wr_data_buffer_inc_dec_15: cover property (@(posedge clk)
// (~rst && wr_data_end && rd_data_upd_indx_r && (occ_cnt_r == 5'hf)));
// wr_data_underflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f))));
// wr_data_overflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11))));
`endif
end // block: occupied_counter
endgenerate
// Keep track of how many write requests are in the memory controller. We
// must limit this to 16 because we only have that many data_buf_addrs to
// hand out. Since the memory controller queue and the write data buffer
// queue are distinct, the number of valid entries can be different.
// Throttle request acceptance once there are sixteen write requests in
// the memory controller. Note that there is still a requirement
// for a write reqeusts corresponding write data to be written into the
// write data queue with two states of the request.
output wire wr_req_16;
generate begin : wr_req_counter
reg [4:0] wr_req_cnt_ns;
reg [4:0] wr_req_cnt_r;
always @(/*AS*/rd_data_upd_indx_r or rst or wr_accepted
or wr_req_cnt_r) begin
wr_req_cnt_ns = wr_req_cnt_r;
if (rst) wr_req_cnt_ns = 5'b0;
else case ({wr_accepted, rd_data_upd_indx_r})
2'b01 : wr_req_cnt_ns = wr_req_cnt_r - 5'b1;
2'b10 : wr_req_cnt_ns = wr_req_cnt_r + 5'b1;
endcase // case ({wr_accepted, rd_data_upd_indx_r})
end
always @(posedge clk) wr_req_cnt_r <= #TCQ wr_req_cnt_ns;
assign wr_req_16 = (wr_req_cnt_ns == 5'h10);
`ifdef MC_SVA
wr_req_mc_full: cover property (@(posedge clk) (~rst && wr_req_16));
wr_req_mc_full_inc_dec_15: cover property (@(posedge clk)
(~rst && wr_accepted && rd_data_upd_indx_r && (wr_req_cnt_r == 5'hf)));
wr_req_underflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'b0) && (wr_req_cnt_ns == 5'h1f))));
wr_req_overflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'h10) && (wr_req_cnt_ns == 5'h11))));
`endif
end // block: wr_req_counter
endgenerate
// Instantiate pointer RAM. Made up of RAM32M in single write, two read
// port mode, 2 bit wide mode.
input [3:0] ram_init_addr;
output wire [3:0] wr_data_buf_addr;
localparam PNTR_RAM_CNT = 2;
generate begin : pointer_ram
wire pointer_we = new_rd_data || ~ram_init_done_r;
wire [3:0] pointer_wr_data = ram_init_done_r
? wr_data_addr_r
: ram_init_addr;
wire [3:0] pointer_wr_addr = ram_init_done_r
? rd_data_indx_r
: ram_init_addr;
genvar i;
for (i=0; i<PNTR_RAM_CNT; i=i+1) begin : rams
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(),
.DOB(wr_data_buf_addr[i*2+:2]),
.DOC(wr_data_pntr[i*2+:2]),
.DOD(),
.DIA(2'b0),
.DIB(pointer_wr_data[i*2+:2]),
.DIC(pointer_wr_data[i*2+:2]),
.DID(2'b0),
.ADDRA(5'b0),
.ADDRB({1'b0, data_buf_addr_cnt_r}),
.ADDRC({1'b0, wr_data_indx_r}),
.ADDRD({1'b0, pointer_wr_addr}),
.WE(pointer_we),
.WCLK(clk)
);
end // block : rams
end // block: pointer_ram
endgenerate
// Instantiate write data buffer. Depending on width of DQ bus and
// DRAM CK to fabric ratio, number of RAM32Ms is variable. RAM32Ms are
// used in single write, single read, 6 bit wide mode.
localparam WR_BUF_WIDTH =
APP_DATA_WIDTH + APP_MASK_WIDTH + (ECC_TEST == "OFF" ? 0 : 2*nCK_PER_CLK);
localparam FULL_RAM_CNT = (WR_BUF_WIDTH/6);
localparam REMAINDER = WR_BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] wr_buf_out_data_w;
reg [RAM_WIDTH-1:0] wr_buf_out_data;
generate
begin : write_buffer
wire [RAM_WIDTH-1:0] wr_buf_in_data;
if (REMAINDER == 0)
if (ECC_TEST == "OFF")
assign wr_buf_in_data = {app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data =
{app_raw_not_ecc_r1, app_wdf_mask_ns1, app_wdf_data_ns1};
else
if (ECC_TEST == "OFF")
assign wr_buf_in_data =
{{6-REMAINDER{1'b0}}, app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data = {{6-REMAINDER{1'b0}}, app_raw_not_ecc_r1,//app_raw_not_ecc_r1 is not ff
app_wdf_mask_ns1, app_wdf_data_ns1};
wire [4:0] rd_addr_w;
assign rd_addr_w = {wr_data_addr, wr_data_offset};
always @(posedge clk) wr_buf_out_data <= #TCQ wr_buf_out_data_w;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : wr_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(wr_buf_out_data_w[((i*6)+4)+:2]),
.DOB(wr_buf_out_data_w[((i*6)+2)+:2]),
.DOC(wr_buf_out_data_w[((i*6)+0)+:2]),
.DOD(),
.DIA(wr_buf_in_data[((i*6)+4)+:2]),
.DIB(wr_buf_in_data[((i*6)+2)+:2]),
.DIC(wr_buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(rd_addr_w),
.ADDRB(rd_addr_w),
.ADDRC(rd_addr_w),
.ADDRD(wb_wr_data_addr_w),
.WE(wdf_rdy_ns),
.WCLK(clk)
);
end // block: wr_buffer_ram
end
endgenerate
output [APP_DATA_WIDTH-1:0] wr_data;
output [APP_MASK_WIDTH-1:0] wr_data_mask;
assign {wr_data_mask, wr_data} = wr_buf_out_data[WR_BUF_WIDTH-1:0];
output [2*nCK_PER_CLK-1:0] raw_not_ecc;
generate
if (ECC_TEST == "OFF") assign raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
else assign raw_not_ecc = wr_buf_out_data[WR_BUF_WIDTH-1-:(2*nCK_PER_CLK)];
endgenerate
endmodule // ui_wr_data
// Local Variables:
// verilog-library-directories:(".")
// End:
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// CRITICAL APPLICATIONS
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//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_wr_data.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// User interface write data buffer. Consists of four counters,
// a pointer RAM and the write data storage RAM.
//
// All RAMs are implemented with distributed RAM.
//
// Whe ordering is set to STRICT or NORM, data moves through
// the write data buffer in strictly FIFO order. In RELAXED
// mode, data may be retired from the write data RAM in any
// order relative to the input order. This implementation
// supports all ordering modes.
//
// The pointer RAM stores a list of pointers to the write data storage RAM.
// This is a list of vacant entries. As data is written into the RAM, a
// pointer is pulled from the pointer RAM and used to index the write
// operation. In a semi autonomously manner, pointers are also pulled, in
// the same order, and provided to the command port as the data_buf_addr.
//
// When the MC reads data from the write data buffer, it uses the
// data_buf_addr provided with the command to extract the data from the
// write data buffer. It also writes this pointer into the end
// of the pointer RAM.
//
// The occupancy counter keeps track of how many entries are valid
// in the write data storage RAM. app_wdf_rdy and app_rdy will be
// de-asserted when there is no more storage in the write data buffer.
//
// Three sequentially incrementing counters/indexes are used to maintain
// and use the contents of the pointer RAM.
//
// The write buffer write data address index generates the pointer
// used to extract the write data address from the pointer RAM. It
// is incremented with each buffer write. The counter is actually one
// ahead of the current write address so that the actual data buffer
// write address can be registered to give a full state to propagate to
// the write data distributed RAMs.
//
// The data_buf_addr counter is used to extract the data_buf_addr for
// the command port. It is incremented as each command is written
// into the MC.
//
// The read data index points to the end of the list of free
// buffers. When the MC fetches data from the write data buffer, it
// provides the buffer address. The buffer address is used to fetch
// the data, but is also written into the pointer at the location indicated
// by the read data index.
//
// Enter and exiting a buffer full condition generates corner cases. Upon
// entering a full condition, incrementing the write buffer write data
// address index must be inhibited. When exiting the full condition,
// the just arrived pointer must propagate through the pointer RAM, then
// indexed by the current value of the write buffer write data
// address counter, the value is registered in the write buffer write
// data address register, then the counter can be advanced.
//
// The pointer RAM must be initialized with valid data after reset. This is
// accomplished by stepping through each pointer RAM entry and writing
// the locations address into the pointer RAM. For the FIFO modes, this means
// that buffer address will always proceed in a sequential order. In the
// RELAXED mode, the original write traversal will be in sequential
// order, but once the MC begins to retire out of order, the entries in
// the pointer RAM will become randomized. The ui_rd_data module provides
// the control information for the initialization process.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ui_wr_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter ECC = "OFF",
parameter nCK_PER_CLK = 2 ,
parameter ECC_TEST = "OFF",
parameter CWL = 5
)
(/*AUTOARG*/
// Outputs
app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask,
raw_not_ecc,
// Inputs
rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren,
app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted,
ram_init_done_r, ram_init_addr
);
input rst;
input clk;
input [APP_DATA_WIDTH-1:0] app_wdf_data;
input [APP_MASK_WIDTH-1:0] app_wdf_mask;
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc;
input app_wdf_wren;
input app_wdf_end;
reg [APP_DATA_WIDTH-1:0] app_wdf_data_r1;
reg [APP_MASK_WIDTH-1:0] app_wdf_mask_r1;
reg [2*nCK_PER_CLK-1:0] app_raw_not_ecc_r1 = 4'b0;
reg app_wdf_wren_r1;
reg app_wdf_end_r1;
reg app_wdf_rdy_r;
//Adding few copies of the app_wdf_rdy_r signal in order to meet
//timing. This is signal has a very high fanout. So grouped into
//few functional groups and alloted one copy per group.
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy1;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy2;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy3;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy4;
wire [APP_DATA_WIDTH-1:0] app_wdf_data_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_data_r1 : app_wdf_data;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_mask_r1 : app_wdf_mask;
wire app_wdf_wren_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_wren_r1 : app_wdf_wren);
wire app_wdf_end_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_end_r1 : app_wdf_end);
generate
if (ECC_TEST != "OFF") begin : ecc_on
always @(app_raw_not_ecc) app_raw_not_ecc_r1 = app_raw_not_ecc;
end
endgenerate
// Be explicit about the latch enable on these registers.
always @(posedge clk) begin
app_wdf_data_r1 <= #TCQ app_wdf_data_ns1;
app_wdf_mask_r1 <= #TCQ app_wdf_mask_ns1;
app_wdf_wren_r1 <= #TCQ app_wdf_wren_ns1;
app_wdf_end_r1 <= #TCQ app_wdf_end_ns1;
end
// The signals wr_data_addr and wr_data_offset come at different
// times depending on ECC and the value of CWL. The data portion
// always needs to look a the raw wires, the control portion needs
// to look at a delayed version when ECC is on and CWL != 8. The
// currently supported write data delays do not require this
// functionality, but preserve for future use.
input wr_data_offset;
input [3:0] wr_data_addr;
reg wr_data_offset_r;
reg [3:0] wr_data_addr_r;
generate
if (ECC == "OFF" || CWL >= 0) begin : pass_wr_addr
always @(wr_data_offset) wr_data_offset_r = wr_data_offset;
always @(wr_data_addr) wr_data_addr_r = wr_data_addr;
end
else begin : delay_wr_addr
always @(posedge clk) wr_data_offset_r <= #TCQ wr_data_offset;
always @(posedge clk) wr_data_addr_r <= #TCQ wr_data_addr;
end
endgenerate
// rd_data_cnt is the pointer RAM index for data read from the write data
// buffer. Ie, its the data on its way out to the DRAM.
input wr_data_en;
wire new_rd_data = wr_data_en && ~wr_data_offset_r;
reg [3:0] rd_data_indx_r;
reg rd_data_upd_indx_r;
generate begin : read_data_indx
reg [3:0] rd_data_indx_ns;
always @(/*AS*/new_rd_data or rd_data_indx_r or rst) begin
rd_data_indx_ns = rd_data_indx_r;
if (rst) rd_data_indx_ns = 5'b0;
else if (new_rd_data) rd_data_indx_ns = rd_data_indx_r + 5'h1;
end
always @(posedge clk) rd_data_indx_r <= #TCQ rd_data_indx_ns;
always @(posedge clk) rd_data_upd_indx_r <= #TCQ new_rd_data;
end
endgenerate
// data_buf_addr_cnt generates the pointer for the pointer RAM on behalf
// of data buf address that comes with the wr_data_en.
// The data buf address is written into the memory
// controller along with the command and address.
input wr_accepted;
reg [3:0] data_buf_addr_cnt_r;
generate begin : data_buf_address_counter
reg [3:0] data_buf_addr_cnt_ns;
always @(/*AS*/data_buf_addr_cnt_r or rst or wr_accepted) begin
data_buf_addr_cnt_ns = data_buf_addr_cnt_r;
if (rst) data_buf_addr_cnt_ns = 4'b0;
else if (wr_accepted) data_buf_addr_cnt_ns =
data_buf_addr_cnt_r + 4'h1;
end
always @(posedge clk) data_buf_addr_cnt_r <= #TCQ data_buf_addr_cnt_ns;
end
endgenerate
// Control writing data into the write data buffer.
wire wdf_rdy_ns;
always @( posedge clk ) begin
app_wdf_rdy_r_copy1 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy2 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy3 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy4 <= #TCQ wdf_rdy_ns;
end
wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1;
wire [3:0] wr_data_pntr;
wire [4:0] wb_wr_data_addr;
wire [4:0] wb_wr_data_addr_w;
reg [3:0] wr_data_indx_r;
generate begin : write_data_control
wire wr_data_addr_le = (wr_data_end && wdf_rdy_ns) ||
(rd_data_upd_indx_r && ~app_wdf_rdy_r_copy1);
// For pointer RAM. Initialize to one since this is one ahead of
// what's being registered in wb_wr_data_addr. Assumes pointer RAM
// has been initialized such that address equals contents.
reg [3:0] wr_data_indx_ns;
always @(/*AS*/rst or wr_data_addr_le or wr_data_indx_r) begin
wr_data_indx_ns = wr_data_indx_r;
if (rst) wr_data_indx_ns = 4'b1;
else if (wr_data_addr_le) wr_data_indx_ns = wr_data_indx_r + 4'h1;
end
always @(posedge clk) wr_data_indx_r <= #TCQ wr_data_indx_ns;
// Take pointer from pointer RAM and set into the write data address.
// Needs to be split into zeroth bit and everything else because synthesis
// tools don't always allow assigning bit vectors seperately. Bit zero of the
// address is computed via an entirely different algorithm.
reg [4:1] wb_wr_data_addr_ns;
reg [4:1] wb_wr_data_addr_r;
always @(/*AS*/rst or wb_wr_data_addr_r or wr_data_addr_le
or wr_data_pntr) begin
wb_wr_data_addr_ns = wb_wr_data_addr_r;
if (rst) wb_wr_data_addr_ns = 4'b0;
else if (wr_data_addr_le) wb_wr_data_addr_ns = wr_data_pntr;
end
always @(posedge clk) wb_wr_data_addr_r <= #TCQ wb_wr_data_addr_ns;
// If we see the first getting accepted, then
// second half is unconditionally accepted.
reg wb_wr_data_addr0_r;
wire wb_wr_data_addr0_ns = ~rst &&
((app_wdf_rdy_r_copy3 && app_wdf_wren_r1 && ~app_wdf_end_r1) ||
(wb_wr_data_addr0_r && ~app_wdf_wren_r1));
always @(posedge clk) wb_wr_data_addr0_r <= #TCQ wb_wr_data_addr0_ns;
assign wb_wr_data_addr = {wb_wr_data_addr_r, wb_wr_data_addr0_r};
assign wb_wr_data_addr_w = {wb_wr_data_addr_ns, wb_wr_data_addr0_ns};
end
endgenerate
// Keep track of how many entries in the queue hold data.
input ram_init_done_r;
output wire app_wdf_rdy;
generate begin : occupied_counter
//reg [4:0] occ_cnt_ns;
//reg [4:0] occ_cnt_r;
//always @(/*AS*/occ_cnt_r or rd_data_upd_indx_r or rst
// or wr_data_end) begin
// occ_cnt_ns = occ_cnt_r;
// if (rst) occ_cnt_ns = 5'b0;
// else case ({wr_data_end, rd_data_upd_indx_r})
// 2'b01 : occ_cnt_ns = occ_cnt_r - 5'b1;
// 2'b10 : occ_cnt_ns = occ_cnt_r + 5'b1;
// endcase // case ({wr_data_end, rd_data_upd_indx_r})
//end
//always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;
//assign wdf_rdy_ns = !(rst || ~ram_init_done_r || occ_cnt_ns[4]);
//always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
//assign app_wdf_rdy = app_wdf_rdy_r;
reg [15:0] occ_cnt;
always @(posedge clk) begin
if ( rst )
occ_cnt <= #TCQ 16'h0000;
else case ({wr_data_end, rd_data_upd_indx_r})
2'b01 : occ_cnt <= #TCQ {1'b0,occ_cnt[15:1]};
2'b10 : occ_cnt <= #TCQ {occ_cnt[14:0],1'b1};
endcase // case ({wr_data_end, rd_data_upd_indx_r})
end
assign wdf_rdy_ns = !(rst || ~ram_init_done_r || (occ_cnt[14] && wr_data_end && ~rd_data_upd_indx_r) || (occ_cnt[15] && ~rd_data_upd_indx_r));
always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
assign app_wdf_rdy = app_wdf_rdy_r;
`ifdef MC_SVA
wr_data_buffer_full: cover property (@(posedge clk)
(~rst && ~app_wdf_rdy_r));
// wr_data_buffer_inc_dec_15: cover property (@(posedge clk)
// (~rst && wr_data_end && rd_data_upd_indx_r && (occ_cnt_r == 5'hf)));
// wr_data_underflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f))));
// wr_data_overflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11))));
`endif
end // block: occupied_counter
endgenerate
// Keep track of how many write requests are in the memory controller. We
// must limit this to 16 because we only have that many data_buf_addrs to
// hand out. Since the memory controller queue and the write data buffer
// queue are distinct, the number of valid entries can be different.
// Throttle request acceptance once there are sixteen write requests in
// the memory controller. Note that there is still a requirement
// for a write reqeusts corresponding write data to be written into the
// write data queue with two states of the request.
output wire wr_req_16;
generate begin : wr_req_counter
reg [4:0] wr_req_cnt_ns;
reg [4:0] wr_req_cnt_r;
always @(/*AS*/rd_data_upd_indx_r or rst or wr_accepted
or wr_req_cnt_r) begin
wr_req_cnt_ns = wr_req_cnt_r;
if (rst) wr_req_cnt_ns = 5'b0;
else case ({wr_accepted, rd_data_upd_indx_r})
2'b01 : wr_req_cnt_ns = wr_req_cnt_r - 5'b1;
2'b10 : wr_req_cnt_ns = wr_req_cnt_r + 5'b1;
endcase // case ({wr_accepted, rd_data_upd_indx_r})
end
always @(posedge clk) wr_req_cnt_r <= #TCQ wr_req_cnt_ns;
assign wr_req_16 = (wr_req_cnt_ns == 5'h10);
`ifdef MC_SVA
wr_req_mc_full: cover property (@(posedge clk) (~rst && wr_req_16));
wr_req_mc_full_inc_dec_15: cover property (@(posedge clk)
(~rst && wr_accepted && rd_data_upd_indx_r && (wr_req_cnt_r == 5'hf)));
wr_req_underflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'b0) && (wr_req_cnt_ns == 5'h1f))));
wr_req_overflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'h10) && (wr_req_cnt_ns == 5'h11))));
`endif
end // block: wr_req_counter
endgenerate
// Instantiate pointer RAM. Made up of RAM32M in single write, two read
// port mode, 2 bit wide mode.
input [3:0] ram_init_addr;
output wire [3:0] wr_data_buf_addr;
localparam PNTR_RAM_CNT = 2;
generate begin : pointer_ram
wire pointer_we = new_rd_data || ~ram_init_done_r;
wire [3:0] pointer_wr_data = ram_init_done_r
? wr_data_addr_r
: ram_init_addr;
wire [3:0] pointer_wr_addr = ram_init_done_r
? rd_data_indx_r
: ram_init_addr;
genvar i;
for (i=0; i<PNTR_RAM_CNT; i=i+1) begin : rams
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(),
.DOB(wr_data_buf_addr[i*2+:2]),
.DOC(wr_data_pntr[i*2+:2]),
.DOD(),
.DIA(2'b0),
.DIB(pointer_wr_data[i*2+:2]),
.DIC(pointer_wr_data[i*2+:2]),
.DID(2'b0),
.ADDRA(5'b0),
.ADDRB({1'b0, data_buf_addr_cnt_r}),
.ADDRC({1'b0, wr_data_indx_r}),
.ADDRD({1'b0, pointer_wr_addr}),
.WE(pointer_we),
.WCLK(clk)
);
end // block : rams
end // block: pointer_ram
endgenerate
// Instantiate write data buffer. Depending on width of DQ bus and
// DRAM CK to fabric ratio, number of RAM32Ms is variable. RAM32Ms are
// used in single write, single read, 6 bit wide mode.
localparam WR_BUF_WIDTH =
APP_DATA_WIDTH + APP_MASK_WIDTH + (ECC_TEST == "OFF" ? 0 : 2*nCK_PER_CLK);
localparam FULL_RAM_CNT = (WR_BUF_WIDTH/6);
localparam REMAINDER = WR_BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] wr_buf_out_data_w;
reg [RAM_WIDTH-1:0] wr_buf_out_data;
generate
begin : write_buffer
wire [RAM_WIDTH-1:0] wr_buf_in_data;
if (REMAINDER == 0)
if (ECC_TEST == "OFF")
assign wr_buf_in_data = {app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data =
{app_raw_not_ecc_r1, app_wdf_mask_ns1, app_wdf_data_ns1};
else
if (ECC_TEST == "OFF")
assign wr_buf_in_data =
{{6-REMAINDER{1'b0}}, app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data = {{6-REMAINDER{1'b0}}, app_raw_not_ecc_r1,//app_raw_not_ecc_r1 is not ff
app_wdf_mask_ns1, app_wdf_data_ns1};
wire [4:0] rd_addr_w;
assign rd_addr_w = {wr_data_addr, wr_data_offset};
always @(posedge clk) wr_buf_out_data <= #TCQ wr_buf_out_data_w;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : wr_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(wr_buf_out_data_w[((i*6)+4)+:2]),
.DOB(wr_buf_out_data_w[((i*6)+2)+:2]),
.DOC(wr_buf_out_data_w[((i*6)+0)+:2]),
.DOD(),
.DIA(wr_buf_in_data[((i*6)+4)+:2]),
.DIB(wr_buf_in_data[((i*6)+2)+:2]),
.DIC(wr_buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(rd_addr_w),
.ADDRB(rd_addr_w),
.ADDRC(rd_addr_w),
.ADDRD(wb_wr_data_addr_w),
.WE(wdf_rdy_ns),
.WCLK(clk)
);
end // block: wr_buffer_ram
end
endgenerate
output [APP_DATA_WIDTH-1:0] wr_data;
output [APP_MASK_WIDTH-1:0] wr_data_mask;
assign {wr_data_mask, wr_data} = wr_buf_out_data[WR_BUF_WIDTH-1:0];
output [2*nCK_PER_CLK-1:0] raw_not_ecc;
generate
if (ECC_TEST == "OFF") assign raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
else assign raw_not_ecc = wr_buf_out_data[WR_BUF_WIDTH-1-:(2*nCK_PER_CLK)];
endgenerate
endmodule // ui_wr_data
// Local Variables:
// verilog-library-directories:(".")
// End:
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_wr_data.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// User interface write data buffer. Consists of four counters,
// a pointer RAM and the write data storage RAM.
//
// All RAMs are implemented with distributed RAM.
//
// Whe ordering is set to STRICT or NORM, data moves through
// the write data buffer in strictly FIFO order. In RELAXED
// mode, data may be retired from the write data RAM in any
// order relative to the input order. This implementation
// supports all ordering modes.
//
// The pointer RAM stores a list of pointers to the write data storage RAM.
// This is a list of vacant entries. As data is written into the RAM, a
// pointer is pulled from the pointer RAM and used to index the write
// operation. In a semi autonomously manner, pointers are also pulled, in
// the same order, and provided to the command port as the data_buf_addr.
//
// When the MC reads data from the write data buffer, it uses the
// data_buf_addr provided with the command to extract the data from the
// write data buffer. It also writes this pointer into the end
// of the pointer RAM.
//
// The occupancy counter keeps track of how many entries are valid
// in the write data storage RAM. app_wdf_rdy and app_rdy will be
// de-asserted when there is no more storage in the write data buffer.
//
// Three sequentially incrementing counters/indexes are used to maintain
// and use the contents of the pointer RAM.
//
// The write buffer write data address index generates the pointer
// used to extract the write data address from the pointer RAM. It
// is incremented with each buffer write. The counter is actually one
// ahead of the current write address so that the actual data buffer
// write address can be registered to give a full state to propagate to
// the write data distributed RAMs.
//
// The data_buf_addr counter is used to extract the data_buf_addr for
// the command port. It is incremented as each command is written
// into the MC.
//
// The read data index points to the end of the list of free
// buffers. When the MC fetches data from the write data buffer, it
// provides the buffer address. The buffer address is used to fetch
// the data, but is also written into the pointer at the location indicated
// by the read data index.
//
// Enter and exiting a buffer full condition generates corner cases. Upon
// entering a full condition, incrementing the write buffer write data
// address index must be inhibited. When exiting the full condition,
// the just arrived pointer must propagate through the pointer RAM, then
// indexed by the current value of the write buffer write data
// address counter, the value is registered in the write buffer write
// data address register, then the counter can be advanced.
//
// The pointer RAM must be initialized with valid data after reset. This is
// accomplished by stepping through each pointer RAM entry and writing
// the locations address into the pointer RAM. For the FIFO modes, this means
// that buffer address will always proceed in a sequential order. In the
// RELAXED mode, the original write traversal will be in sequential
// order, but once the MC begins to retire out of order, the entries in
// the pointer RAM will become randomized. The ui_rd_data module provides
// the control information for the initialization process.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ui_wr_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter ECC = "OFF",
parameter nCK_PER_CLK = 2 ,
parameter ECC_TEST = "OFF",
parameter CWL = 5
)
(/*AUTOARG*/
// Outputs
app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask,
raw_not_ecc,
// Inputs
rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren,
app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted,
ram_init_done_r, ram_init_addr
);
input rst;
input clk;
input [APP_DATA_WIDTH-1:0] app_wdf_data;
input [APP_MASK_WIDTH-1:0] app_wdf_mask;
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc;
input app_wdf_wren;
input app_wdf_end;
reg [APP_DATA_WIDTH-1:0] app_wdf_data_r1;
reg [APP_MASK_WIDTH-1:0] app_wdf_mask_r1;
reg [2*nCK_PER_CLK-1:0] app_raw_not_ecc_r1 = 4'b0;
reg app_wdf_wren_r1;
reg app_wdf_end_r1;
reg app_wdf_rdy_r;
//Adding few copies of the app_wdf_rdy_r signal in order to meet
//timing. This is signal has a very high fanout. So grouped into
//few functional groups and alloted one copy per group.
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy1;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy2;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy3;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy4;
wire [APP_DATA_WIDTH-1:0] app_wdf_data_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_data_r1 : app_wdf_data;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_mask_r1 : app_wdf_mask;
wire app_wdf_wren_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_wren_r1 : app_wdf_wren);
wire app_wdf_end_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_end_r1 : app_wdf_end);
generate
if (ECC_TEST != "OFF") begin : ecc_on
always @(app_raw_not_ecc) app_raw_not_ecc_r1 = app_raw_not_ecc;
end
endgenerate
// Be explicit about the latch enable on these registers.
always @(posedge clk) begin
app_wdf_data_r1 <= #TCQ app_wdf_data_ns1;
app_wdf_mask_r1 <= #TCQ app_wdf_mask_ns1;
app_wdf_wren_r1 <= #TCQ app_wdf_wren_ns1;
app_wdf_end_r1 <= #TCQ app_wdf_end_ns1;
end
// The signals wr_data_addr and wr_data_offset come at different
// times depending on ECC and the value of CWL. The data portion
// always needs to look a the raw wires, the control portion needs
// to look at a delayed version when ECC is on and CWL != 8. The
// currently supported write data delays do not require this
// functionality, but preserve for future use.
input wr_data_offset;
input [3:0] wr_data_addr;
reg wr_data_offset_r;
reg [3:0] wr_data_addr_r;
generate
if (ECC == "OFF" || CWL >= 0) begin : pass_wr_addr
always @(wr_data_offset) wr_data_offset_r = wr_data_offset;
always @(wr_data_addr) wr_data_addr_r = wr_data_addr;
end
else begin : delay_wr_addr
always @(posedge clk) wr_data_offset_r <= #TCQ wr_data_offset;
always @(posedge clk) wr_data_addr_r <= #TCQ wr_data_addr;
end
endgenerate
// rd_data_cnt is the pointer RAM index for data read from the write data
// buffer. Ie, its the data on its way out to the DRAM.
input wr_data_en;
wire new_rd_data = wr_data_en && ~wr_data_offset_r;
reg [3:0] rd_data_indx_r;
reg rd_data_upd_indx_r;
generate begin : read_data_indx
reg [3:0] rd_data_indx_ns;
always @(/*AS*/new_rd_data or rd_data_indx_r or rst) begin
rd_data_indx_ns = rd_data_indx_r;
if (rst) rd_data_indx_ns = 5'b0;
else if (new_rd_data) rd_data_indx_ns = rd_data_indx_r + 5'h1;
end
always @(posedge clk) rd_data_indx_r <= #TCQ rd_data_indx_ns;
always @(posedge clk) rd_data_upd_indx_r <= #TCQ new_rd_data;
end
endgenerate
// data_buf_addr_cnt generates the pointer for the pointer RAM on behalf
// of data buf address that comes with the wr_data_en.
// The data buf address is written into the memory
// controller along with the command and address.
input wr_accepted;
reg [3:0] data_buf_addr_cnt_r;
generate begin : data_buf_address_counter
reg [3:0] data_buf_addr_cnt_ns;
always @(/*AS*/data_buf_addr_cnt_r or rst or wr_accepted) begin
data_buf_addr_cnt_ns = data_buf_addr_cnt_r;
if (rst) data_buf_addr_cnt_ns = 4'b0;
else if (wr_accepted) data_buf_addr_cnt_ns =
data_buf_addr_cnt_r + 4'h1;
end
always @(posedge clk) data_buf_addr_cnt_r <= #TCQ data_buf_addr_cnt_ns;
end
endgenerate
// Control writing data into the write data buffer.
wire wdf_rdy_ns;
always @( posedge clk ) begin
app_wdf_rdy_r_copy1 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy2 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy3 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy4 <= #TCQ wdf_rdy_ns;
end
wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1;
wire [3:0] wr_data_pntr;
wire [4:0] wb_wr_data_addr;
wire [4:0] wb_wr_data_addr_w;
reg [3:0] wr_data_indx_r;
generate begin : write_data_control
wire wr_data_addr_le = (wr_data_end && wdf_rdy_ns) ||
(rd_data_upd_indx_r && ~app_wdf_rdy_r_copy1);
// For pointer RAM. Initialize to one since this is one ahead of
// what's being registered in wb_wr_data_addr. Assumes pointer RAM
// has been initialized such that address equals contents.
reg [3:0] wr_data_indx_ns;
always @(/*AS*/rst or wr_data_addr_le or wr_data_indx_r) begin
wr_data_indx_ns = wr_data_indx_r;
if (rst) wr_data_indx_ns = 4'b1;
else if (wr_data_addr_le) wr_data_indx_ns = wr_data_indx_r + 4'h1;
end
always @(posedge clk) wr_data_indx_r <= #TCQ wr_data_indx_ns;
// Take pointer from pointer RAM and set into the write data address.
// Needs to be split into zeroth bit and everything else because synthesis
// tools don't always allow assigning bit vectors seperately. Bit zero of the
// address is computed via an entirely different algorithm.
reg [4:1] wb_wr_data_addr_ns;
reg [4:1] wb_wr_data_addr_r;
always @(/*AS*/rst or wb_wr_data_addr_r or wr_data_addr_le
or wr_data_pntr) begin
wb_wr_data_addr_ns = wb_wr_data_addr_r;
if (rst) wb_wr_data_addr_ns = 4'b0;
else if (wr_data_addr_le) wb_wr_data_addr_ns = wr_data_pntr;
end
always @(posedge clk) wb_wr_data_addr_r <= #TCQ wb_wr_data_addr_ns;
// If we see the first getting accepted, then
// second half is unconditionally accepted.
reg wb_wr_data_addr0_r;
wire wb_wr_data_addr0_ns = ~rst &&
((app_wdf_rdy_r_copy3 && app_wdf_wren_r1 && ~app_wdf_end_r1) ||
(wb_wr_data_addr0_r && ~app_wdf_wren_r1));
always @(posedge clk) wb_wr_data_addr0_r <= #TCQ wb_wr_data_addr0_ns;
assign wb_wr_data_addr = {wb_wr_data_addr_r, wb_wr_data_addr0_r};
assign wb_wr_data_addr_w = {wb_wr_data_addr_ns, wb_wr_data_addr0_ns};
end
endgenerate
// Keep track of how many entries in the queue hold data.
input ram_init_done_r;
output wire app_wdf_rdy;
generate begin : occupied_counter
//reg [4:0] occ_cnt_ns;
//reg [4:0] occ_cnt_r;
//always @(/*AS*/occ_cnt_r or rd_data_upd_indx_r or rst
// or wr_data_end) begin
// occ_cnt_ns = occ_cnt_r;
// if (rst) occ_cnt_ns = 5'b0;
// else case ({wr_data_end, rd_data_upd_indx_r})
// 2'b01 : occ_cnt_ns = occ_cnt_r - 5'b1;
// 2'b10 : occ_cnt_ns = occ_cnt_r + 5'b1;
// endcase // case ({wr_data_end, rd_data_upd_indx_r})
//end
//always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;
//assign wdf_rdy_ns = !(rst || ~ram_init_done_r || occ_cnt_ns[4]);
//always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
//assign app_wdf_rdy = app_wdf_rdy_r;
reg [15:0] occ_cnt;
always @(posedge clk) begin
if ( rst )
occ_cnt <= #TCQ 16'h0000;
else case ({wr_data_end, rd_data_upd_indx_r})
2'b01 : occ_cnt <= #TCQ {1'b0,occ_cnt[15:1]};
2'b10 : occ_cnt <= #TCQ {occ_cnt[14:0],1'b1};
endcase // case ({wr_data_end, rd_data_upd_indx_r})
end
assign wdf_rdy_ns = !(rst || ~ram_init_done_r || (occ_cnt[14] && wr_data_end && ~rd_data_upd_indx_r) || (occ_cnt[15] && ~rd_data_upd_indx_r));
always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
assign app_wdf_rdy = app_wdf_rdy_r;
`ifdef MC_SVA
wr_data_buffer_full: cover property (@(posedge clk)
(~rst && ~app_wdf_rdy_r));
// wr_data_buffer_inc_dec_15: cover property (@(posedge clk)
// (~rst && wr_data_end && rd_data_upd_indx_r && (occ_cnt_r == 5'hf)));
// wr_data_underflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f))));
// wr_data_overflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11))));
`endif
end // block: occupied_counter
endgenerate
// Keep track of how many write requests are in the memory controller. We
// must limit this to 16 because we only have that many data_buf_addrs to
// hand out. Since the memory controller queue and the write data buffer
// queue are distinct, the number of valid entries can be different.
// Throttle request acceptance once there are sixteen write requests in
// the memory controller. Note that there is still a requirement
// for a write reqeusts corresponding write data to be written into the
// write data queue with two states of the request.
output wire wr_req_16;
generate begin : wr_req_counter
reg [4:0] wr_req_cnt_ns;
reg [4:0] wr_req_cnt_r;
always @(/*AS*/rd_data_upd_indx_r or rst or wr_accepted
or wr_req_cnt_r) begin
wr_req_cnt_ns = wr_req_cnt_r;
if (rst) wr_req_cnt_ns = 5'b0;
else case ({wr_accepted, rd_data_upd_indx_r})
2'b01 : wr_req_cnt_ns = wr_req_cnt_r - 5'b1;
2'b10 : wr_req_cnt_ns = wr_req_cnt_r + 5'b1;
endcase // case ({wr_accepted, rd_data_upd_indx_r})
end
always @(posedge clk) wr_req_cnt_r <= #TCQ wr_req_cnt_ns;
assign wr_req_16 = (wr_req_cnt_ns == 5'h10);
`ifdef MC_SVA
wr_req_mc_full: cover property (@(posedge clk) (~rst && wr_req_16));
wr_req_mc_full_inc_dec_15: cover property (@(posedge clk)
(~rst && wr_accepted && rd_data_upd_indx_r && (wr_req_cnt_r == 5'hf)));
wr_req_underflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'b0) && (wr_req_cnt_ns == 5'h1f))));
wr_req_overflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'h10) && (wr_req_cnt_ns == 5'h11))));
`endif
end // block: wr_req_counter
endgenerate
// Instantiate pointer RAM. Made up of RAM32M in single write, two read
// port mode, 2 bit wide mode.
input [3:0] ram_init_addr;
output wire [3:0] wr_data_buf_addr;
localparam PNTR_RAM_CNT = 2;
generate begin : pointer_ram
wire pointer_we = new_rd_data || ~ram_init_done_r;
wire [3:0] pointer_wr_data = ram_init_done_r
? wr_data_addr_r
: ram_init_addr;
wire [3:0] pointer_wr_addr = ram_init_done_r
? rd_data_indx_r
: ram_init_addr;
genvar i;
for (i=0; i<PNTR_RAM_CNT; i=i+1) begin : rams
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(),
.DOB(wr_data_buf_addr[i*2+:2]),
.DOC(wr_data_pntr[i*2+:2]),
.DOD(),
.DIA(2'b0),
.DIB(pointer_wr_data[i*2+:2]),
.DIC(pointer_wr_data[i*2+:2]),
.DID(2'b0),
.ADDRA(5'b0),
.ADDRB({1'b0, data_buf_addr_cnt_r}),
.ADDRC({1'b0, wr_data_indx_r}),
.ADDRD({1'b0, pointer_wr_addr}),
.WE(pointer_we),
.WCLK(clk)
);
end // block : rams
end // block: pointer_ram
endgenerate
// Instantiate write data buffer. Depending on width of DQ bus and
// DRAM CK to fabric ratio, number of RAM32Ms is variable. RAM32Ms are
// used in single write, single read, 6 bit wide mode.
localparam WR_BUF_WIDTH =
APP_DATA_WIDTH + APP_MASK_WIDTH + (ECC_TEST == "OFF" ? 0 : 2*nCK_PER_CLK);
localparam FULL_RAM_CNT = (WR_BUF_WIDTH/6);
localparam REMAINDER = WR_BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] wr_buf_out_data_w;
reg [RAM_WIDTH-1:0] wr_buf_out_data;
generate
begin : write_buffer
wire [RAM_WIDTH-1:0] wr_buf_in_data;
if (REMAINDER == 0)
if (ECC_TEST == "OFF")
assign wr_buf_in_data = {app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data =
{app_raw_not_ecc_r1, app_wdf_mask_ns1, app_wdf_data_ns1};
else
if (ECC_TEST == "OFF")
assign wr_buf_in_data =
{{6-REMAINDER{1'b0}}, app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data = {{6-REMAINDER{1'b0}}, app_raw_not_ecc_r1,//app_raw_not_ecc_r1 is not ff
app_wdf_mask_ns1, app_wdf_data_ns1};
wire [4:0] rd_addr_w;
assign rd_addr_w = {wr_data_addr, wr_data_offset};
always @(posedge clk) wr_buf_out_data <= #TCQ wr_buf_out_data_w;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : wr_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(wr_buf_out_data_w[((i*6)+4)+:2]),
.DOB(wr_buf_out_data_w[((i*6)+2)+:2]),
.DOC(wr_buf_out_data_w[((i*6)+0)+:2]),
.DOD(),
.DIA(wr_buf_in_data[((i*6)+4)+:2]),
.DIB(wr_buf_in_data[((i*6)+2)+:2]),
.DIC(wr_buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(rd_addr_w),
.ADDRB(rd_addr_w),
.ADDRC(rd_addr_w),
.ADDRD(wb_wr_data_addr_w),
.WE(wdf_rdy_ns),
.WCLK(clk)
);
end // block: wr_buffer_ram
end
endgenerate
output [APP_DATA_WIDTH-1:0] wr_data;
output [APP_MASK_WIDTH-1:0] wr_data_mask;
assign {wr_data_mask, wr_data} = wr_buf_out_data[WR_BUF_WIDTH-1:0];
output [2*nCK_PER_CLK-1:0] raw_not_ecc;
generate
if (ECC_TEST == "OFF") assign raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
else assign raw_not_ecc = wr_buf_out_data[WR_BUF_WIDTH-1-:(2*nCK_PER_CLK)];
endgenerate
endmodule // ui_wr_data
// Local Variables:
// verilog-library-directories:(".")
// End:
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
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// reasonably foreseeable or Xilinx had been advised of the
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// Xilinx products are not designed or intended to be fail-
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// (individually and collectively, "Critical
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v2_3_phy_ocd_samp.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Controls the number of samples and generates an aggregate
//sampling result.
//
// The following shows the nesting of the sampling loop. Nominally built
// to accomodate the "complex" sampling protocol. Adapted for use with
// "simple" samplng.
//
// simple complex
//
// samples OCAL_SIMPLE_SCAN_SAMPS 1 or 50 Depends on SIM_CAL_OPTION
// rd_victim_sel 0 0 to 7
// data_cnt 1 157
//
// First it collects comparison results provided on the
// two bit "match" bus. A particular phaser tap setting may be recorded one
// or many times depending on various parameter settings.
// The two bit match bus corresponds to comparisons for the
// zero or rising phase, and the oneeighty or falling phase. The "aggregate"
// starts out as NULL and then begins collecting comparison results
// when phy_rddata_en_1 is high. The first result is always set into
// the aggregate result. Subsequent results that match aggregate, don't
// make any change. Subsequent compare results that don't match cause the aggregate
// to turn to FUZZ.
//
// A "sample" is defined as a single DRAM burst for the simple step, and
// an entire 157 DRAM data bursts across the 8 victim bits for complex.
//
// Once all samples have been taken, the samp_result is computed by
// comparing the number of successful compares against the threshold.
//
// The second function is to track and control the number of samples. For
// "simple" data, the number of samples is set by OCAL_SIMPLE_SCAN_SAMPS.
// For "complex" data, nominally
// the complex data pattern consists of a sequence of 157 DRAM chunks. This
// sequence is run with each bit in the byte designated as the "victim". This sequence
// is repeated 50 times, although when SIM_CAL_OPTION is set to none "NONE", it is only
// repeated once.
//
// This block generates oclk_calib_resume. For the simple pattern, a single DRAM
// burst is returned For complex its 157 which indicates the start of the 157*50
// sequence for a bit. samp_done is pulsed.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_ocd_samp #
(parameter nCK_PER_CLK = 4,
parameter OCAL_SIMPLE_SCAN_SAMPS = 2,
parameter SCAN_PCT_SAMPS_SOLID = 95,
parameter TCQ = 100,
parameter SIM_CAL_OPTION = "NONE")
(/*AUTOARG*/
// Outputs
samp_done, oclk_calib_resume, rd_victim_sel, samp_result,
// Inputs
complex_oclkdelay_calib_start, clk, rst, reset_scan,
ocal_num_samples_inc, match, phy_rddata_en_1, taps_set
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam ONE = 1;
localparam CMPLX_DATA_CNT = nCK_PER_CLK == 2 ? 157 * 2 : 157;
localparam SIMP_DATA_CNT = nCK_PER_CLK == 2 ? 2 : 1;
localparam DATA_CNT_WIDTH = nCK_PER_CLK == 2 ? 9 : 8;
localparam CMPLX_SAMPS = SIM_CAL_OPTION == "NONE" ? 50 : 1;
// Plus one because were counting in natural numbers.
localparam SAMP_CNT_WIDTH = clogb2(OCAL_SIMPLE_SCAN_SAMPS > CMPLX_SAMPS
? OCAL_SIMPLE_SCAN_SAMPS : CMPLX_SAMPS) + 1;
// Remember SAMPLES is natural number counting. One corresponds to one sample.
localparam integer SIMP_SAMPS_SOLID_THRESH = OCAL_SIMPLE_SCAN_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01;
localparam integer CMPLX_SAMPS_SOLID_THRESH = CMPLX_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01;
input complex_oclkdelay_calib_start;
wire [SAMP_CNT_WIDTH-1:0] samples = complex_oclkdelay_calib_start
? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0]
: OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0];
localparam [1:0] NULL = 2'b11,
FUZZ = 2'b00,
ONEEIGHTY = 2'b10,
ZERO = 2'b01;
input clk;
input rst;
input reset_scan;
// Given the need to count phy_data_en, this is not useful.
input ocal_num_samples_inc;
input [1:0] match;
input phy_rddata_en_1;
input taps_set;
reg samp_done_ns, samp_done_r;
always @(posedge clk) samp_done_r <= #TCQ samp_done_ns;
output samp_done;
assign samp_done = samp_done_r;
reg [1:0] agg_samp_ns, agg_samp_r;
always @(posedge clk) agg_samp_r <= #TCQ agg_samp_ns;
reg oclk_calib_resume_ns, oclk_calib_resume_r;
always @(posedge clk) oclk_calib_resume_r <= #TCQ oclk_calib_resume_ns;
output oclk_calib_resume;
assign oclk_calib_resume = oclk_calib_resume_r;
// Complex data counting.
// Inner most loop. 157 phy_data_en.
reg [DATA_CNT_WIDTH-1:0] data_cnt_ns, data_cnt_r;
always @(posedge clk) data_cnt_r <= #TCQ data_cnt_ns;
// Nominally, 50 samples of the above 157 phy_data_en.
reg [SAMP_CNT_WIDTH-1:0] samps_ns, samps_r;
always @(posedge clk) samps_r <= #TCQ samps_ns;
// Step through the 8 bits in the byte.
reg [2:0] rd_victim_sel_ns, rd_victim_sel_r;
always @(posedge clk) rd_victim_sel_r <= #TCQ rd_victim_sel_ns;
output [2:0] rd_victim_sel;
assign rd_victim_sel = rd_victim_sel_r;
reg [SAMP_CNT_WIDTH-1:0] zero_ns, zero_r, oneeighty_ns, oneeighty_r;
always @(posedge clk) zero_r <= #TCQ zero_ns;
always @(posedge clk) oneeighty_r <= #TCQ oneeighty_ns;
output [1:0] samp_result;
assign samp_result[0] = zero_r >= (complex_oclkdelay_calib_start
? CMPLX_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]
: SIMP_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]);
assign samp_result[1] = oneeighty_r >= (complex_oclkdelay_calib_start
? CMPLX_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]
: SIMP_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]);
reg [0:0] sm_ns, sm_r;
always @(posedge clk) sm_r <= #TCQ sm_ns;
wire [DATA_CNT_WIDTH-1:0] data_cnt = complex_oclkdelay_calib_start
? CMPLX_DATA_CNT[DATA_CNT_WIDTH-1:0]
: SIMP_DATA_CNT[DATA_CNT_WIDTH-1:0];
wire [2:0] rd_victim_end = complex_oclkdelay_calib_start ? 3'h7 : 3'h0;
wire data_end = data_cnt_r == ONE[DATA_CNT_WIDTH-1:0];
wire samp_end = samps_r == ONE[SAMP_CNT_WIDTH-1:0];
// Primary state machine.
always @(*) begin
// Default next state assignments.
agg_samp_ns = agg_samp_r;
data_cnt_ns = data_cnt_r;
oclk_calib_resume_ns = 1'b0;
oneeighty_ns = oneeighty_r;
rd_victim_sel_ns = rd_victim_sel_r;
samp_done_ns = samp_done_r;
samps_ns = samps_r;
sm_ns = sm_r;
zero_ns = zero_r;
if (rst == 1'b1) begin
// RESET next states
sm_ns = /*AK("READY")*/1'd0;
end else
// State based actions and next states.
case (sm_r)
/*AL("READY")*/1'd0:begin
agg_samp_ns = NULL;
data_cnt_ns = data_cnt;
oneeighty_ns = {SAMP_CNT_WIDTH{1'b0}};
rd_victim_sel_ns = 3'b0;
samps_ns = complex_oclkdelay_calib_start ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0]
: OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0];
zero_ns = {SAMP_CNT_WIDTH{1'b0}};
if (taps_set) begin
samp_done_ns = 1'b0;
sm_ns = /*AK("AWAITING_DATA")*/1'd1;
oclk_calib_resume_ns = 1'b1;
end
end
/*AL("AWAITING_DATA")*/1'd1:begin
if (phy_rddata_en_1) begin
case (agg_samp_r)
NULL : if (~&match) agg_samp_ns = match;
ZERO, ONEEIGHTY : if (~(agg_samp_r == match || &match)) agg_samp_ns = FUZZ;
FUZZ : ;
endcase // case (agg_samp_r)
if (~data_end) data_cnt_ns = data_cnt_r - ONE[DATA_CNT_WIDTH-1:0];
else begin
data_cnt_ns = data_cnt;
if (rd_victim_end != rd_victim_sel_r) rd_victim_sel_ns = rd_victim_sel_r + 3'h1;
else begin
rd_victim_sel_ns = 3'h0;
if (agg_samp_ns == ZERO) zero_ns = zero_r + ONE[SAMP_CNT_WIDTH-1:0];
if (agg_samp_ns == ONEEIGHTY) oneeighty_ns = oneeighty_r + ONE[SAMP_CNT_WIDTH-1:0];
agg_samp_ns = NULL;
if (~samp_end) samps_ns = samps_r - ONE[SAMP_CNT_WIDTH-1:0];
else samp_done_ns = 1'b1;
end
end
if (samp_done_ns) sm_ns = /*AK("READY")*/1'd0;
else oclk_calib_resume_ns = ~complex_oclkdelay_calib_start && data_end;
end
end
endcase // case (sm_r)
end // always @ begin
endmodule // mig_7series_v2_3_ddr_phy_ocd_samp
// Local Variables:
// verilog-autolabel-prefix: "1'd"
// End:
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : col_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// The column machine manages the dq bus. Since there is a single DQ
// bus, and the column part of the DRAM is tightly coupled to this DQ
// bus, conceptually, the DQ bus and all of the column hardware in
// a multi rank DRAM array are managed as a single unit.
//
//
// The column machine does not "enforce" the column timing directly.
// It generates information and sends it to the bank machines. If the
// bank machines incorrectly make a request, the column machine will
// simply overwrite the existing request with the new request even
// if this would result in a timing or protocol violation.
//
// The column machine
// hosts the block that controls read and write data transfer
// to and from the dq bus.
//
// And if configured, there is provision for tracking the address
// of a command as it moves through the column pipeline. This
// address will be logged for detected ECC errors.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_col_mach #
(
parameter TCQ = 100,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DELAY_WR_DATA_CNTRL = 0,
parameter DQS_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nCK_PER_CLK = 2,
parameter nPHY_WRLAT = 0,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16
)
(/*AUTOARG*/
// Outputs
dq_busy_data, wr_data_offset, mc_wrdata_en, wr_data_en,
wr_data_addr, rd_rmw, ecc_err_addr, ecc_status_valid, wr_ecc_buf, rd_data_end,
rd_data_addr, rd_data_offset, rd_data_en, col_read_fifo_empty,
// Inputs
clk, rst, sent_col, col_size, col_wr_data_buf_addr,
phy_rddata_valid, col_periodic_rd, col_data_buf_addr, col_rmw,
col_rd_wr, col_ra, col_ba, col_row, col_a
);
input clk;
input rst;
input sent_col;
input col_rd_wr;
output reg dq_busy_data = 1'b0;
// The following generates a column command disable based mostly on the type
// of DRAM and the fabric to DRAM CK ratio.
generate
if ((nCK_PER_CLK == 1) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
begin : three_bumps
reg [1:0] granted_col_d_r;
wire [1:0] granted_col_d_ns = {sent_col, granted_col_d_r[1]};
always @(posedge clk) granted_col_d_r <= #TCQ granted_col_d_ns;
always @(/*AS*/granted_col_d_r or sent_col)
dq_busy_data = sent_col || |granted_col_d_r;
end
if (((nCK_PER_CLK == 2) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
|| ((nCK_PER_CLK == 1) && ((BURST_MODE == "4") || (DRAM_TYPE == "DDR2"))))
begin : one_bump
always @(/*AS*/sent_col) dq_busy_data = sent_col;
end
endgenerate
// This generates a data offset based on fabric clock to DRAM CK ratio and
// the size bit. Note that this is different that the dq_busy_data signal
// generated above.
reg [1:0] offset_r = 2'b0;
reg [1:0] offset_ns = 2'b0;
input col_size;
wire data_end;
generate
if(nCK_PER_CLK == 4) begin : data_valid_4_1
// For 4:1 mode all data is transfered in a single beat so the default
// values of 0 for offset_r/offset_ns suffice - just tie off data_end
assign data_end = 1'b1;
end
else begin
if(DATA_BUF_OFFSET_WIDTH == 2) begin : data_valid_1_1
always @(col_size or offset_r or rst or sent_col) begin
if (rst) offset_ns = 2'b0;
else begin
offset_ns = offset_r;
if (sent_col) offset_ns = 2'b1;
else if (|offset_r && (offset_r != {col_size, 1'b1}))
offset_ns = offset_r + 2'b1;
else offset_ns = 2'b0;
end
end
always @(posedge clk) offset_r <= #TCQ offset_ns;
assign data_end = col_size ? (offset_r == 2'b11) : offset_r[0];
end
else begin : data_valid_2_1
always @(col_size or rst or sent_col)
offset_ns[0] = rst ? 1'b0 : sent_col && col_size;
always @(posedge clk) offset_r[0] <= #TCQ offset_ns[0];
assign data_end = col_size ? offset_r[0] : 1'b1;
end
end
endgenerate
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r1 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r2 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg col_rd_wr_r1;
reg col_rd_wr_r2;
generate
if ((nPHY_WRLAT >= 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0
always @(posedge clk) offset_r1 <=
#TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr;
end
if(nPHY_WRLAT == 2) begin : offset_pipe_1
always @(posedge clk) offset_r2 <=
#TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1;
end
endgenerate
output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1)
? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]
: (EARLY_WR_DATA_ADDR == "OFF")
? offset_r[DATA_BUF_OFFSET_WIDTH-1:0]
: offset_ns[DATA_BUF_OFFSET_WIDTH-1:0];
reg sent_col_r1;
reg sent_col_r2;
always @(posedge clk) sent_col_r1 <= #TCQ sent_col;
always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1;
wire wrdata_en = (nPHY_WRLAT == 0) ?
(sent_col || |offset_r) & ~col_rd_wr :
(nPHY_WRLAT == 1) ?
(sent_col_r1 || |offset_r1) & ~col_rd_wr_r1 :
//(nPHY_WRLAT >= 2) ?
(sent_col_r2 || |offset_r2) & ~col_rd_wr_r2;
output wire mc_wrdata_en;
assign mc_wrdata_en = wrdata_en;
output wire wr_data_en;
assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1)
? ((sent_col_r1 || |offset_r1) && ~col_rd_wr_r1)
: ((sent_col || |offset_r) && ~col_rd_wr);
input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
generate
if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr;
assign wr_data_addr = col_wr_data_buf_addr_r;
end
else begin : delay_wr_data_cntrl_ne_1
assign wr_data_addr = col_wr_data_buf_addr;
end
endgenerate
// CAS-RD to mc_rddata_en
wire read_data_valid = (sent_col || |offset_r) && col_rd_wr;
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
// Implement FIFO that records reads as they are sent to the DRAM.
// When phy_rddata_valid is returned some unknown time later, the
// FIFO output is used to control how the data is interpreted.
input phy_rddata_valid;
output wire rd_rmw;
output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
output reg ecc_status_valid;
output reg wr_ecc_buf;
output reg rd_data_end;
output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
output reg rd_data_en /* synthesis syn_maxfan = 10 */;
output col_read_fifo_empty;
input col_periodic_rd;
input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
input col_rmw;
input [RANK_WIDTH-1:0] col_ra;
input [BANK_WIDTH-1:0] col_ba;
input [ROW_WIDTH-1:0] col_row;
input [ROW_WIDTH-1:0] col_a;
// Real column address (skip A10/AP and A12/BC#). The maximum width is 12;
// the width will be tailored for the target DRAM downstream.
wire [11:0] col_a_full;
// Minimum row width is 12; take remaining 11 bits after omitting A10/AP
assign col_a_full[10:0] = {col_a[11], col_a[9:0]};
// Get the 12th bit when row address width accommodates it; omit A12/BC#
generate
if (ROW_WIDTH >= 14) begin : COL_A_FULL_11_1
assign col_a_full[11] = col_a[13];
end else begin : COL_A_FULL_11_0
assign col_a_full[11] = 0;
end
endgenerate
// Extract only the width of the target DRAM
wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0];
localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH;
localparam FIFO_WIDTH = 1 /*data_end*/ +
1 /*periodic_rd*/ +
DATA_BUF_ADDR_WIDTH +
DATA_BUF_OFFSET_WIDTH +
((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH);
localparam FULL_RAM_CNT = (FIFO_WIDTH/6);
localparam REMAINDER = FIFO_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
begin : read_fifo
wire [MC_ERR_LINE_WIDTH:0] ecc_line;
if (CS_WIDTH == 1)
assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted};
else
assign ecc_line = {col_rmw,
col_ra,
col_ba,
col_row,
col_a_extracted};
wire [FIFO_WIDTH-1:0] real_fifo_data;
if (ECC == "OFF")
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0]};
else
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0],
ecc_line};
wire [RAM_WIDTH-1:0] fifo_in_data;
if (REMAINDER == 0)
assign fifo_in_data = real_fifo_data;
else
assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data};
wire [RAM_WIDTH-1:0] fifo_out_data_ns;
reg [4:0] head_r;
wire [4:0] head_ns = rst ? 5'b0 : read_data_valid
? (head_r + 5'b1)
: head_r;
always @(posedge clk) head_r <= #TCQ head_ns;
reg [4:0] tail_r;
wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid
? (tail_r + 5'b1)
: tail_r;
always @(posedge clk) tail_r <= #TCQ tail_ns;
assign col_read_fifo_empty = head_r == tail_r ? 1'b1 : 1'b0;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : fifo_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(fifo_out_data_ns[((i*6)+4)+:2]),
.DOB(fifo_out_data_ns[((i*6)+2)+:2]),
.DOC(fifo_out_data_ns[((i*6)+0)+:2]),
.DOD(),
.DIA(fifo_in_data[((i*6)+4)+:2]),
.DIB(fifo_in_data[((i*6)+2)+:2]),
.DIC(fifo_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(tail_ns),
.ADDRB(tail_ns),
.ADDRC(tail_ns),
.ADDRD(head_r),
.WE(1'b1),
.WCLK(clk)
);
end // block: fifo_ram
reg [RAM_WIDTH-1:0] fifo_out_data_r;
always @(posedge clk) fifo_out_data_r <= #TCQ fifo_out_data_ns;
// When ECC is ON, most of the FIFO output is delayed
// by one state.
if (ECC == "OFF") begin
reg periodic_rd;
always @(/*AS*/phy_rddata_valid or fifo_out_data_r) begin
{rd_data_end,
periodic_rd,
rd_data_addr,
rd_data_offset} = fifo_out_data_r[FIFO_WIDTH-1:0];
ecc_err_addr = {MC_ERR_ADDR_WIDTH{1'b0}};
rd_data_en = phy_rddata_valid && ~periodic_rd;
ecc_status_valid = 1'b0;
wr_ecc_buf = 1'b0;
end
assign rd_rmw = 1'b0;
end
else begin
wire rd_data_end_ns;
wire periodic_rd;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset_ns;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr_ns;
assign {rd_data_end_ns,
periodic_rd,
rd_data_addr_ns,
rd_data_offset_ns,
rd_rmw,
ecc_err_addr_ns[DATA_BUF_OFFSET_WIDTH+:MC_ERR_LINE_WIDTH]} =
{fifo_out_data_r[FIFO_WIDTH-1:0]};
assign ecc_err_addr_ns[0+:DATA_BUF_OFFSET_WIDTH] = rd_data_offset_ns;
always @(posedge clk) rd_data_end <= #TCQ rd_data_end_ns;
always @(posedge clk) rd_data_addr <= #TCQ rd_data_addr_ns;
always @(posedge clk) rd_data_offset <= #TCQ rd_data_offset_ns;
always @(posedge clk) ecc_err_addr <= #TCQ ecc_err_addr_ns;
wire rd_data_en_ns = phy_rddata_valid && ~(periodic_rd || rd_rmw);
always @(posedge clk) rd_data_en <= rd_data_en_ns;
wire ecc_status_valid_ns = phy_rddata_valid && ~periodic_rd;
always @(posedge clk) ecc_status_valid <= #TCQ ecc_status_valid_ns;
wire wr_ecc_buf_ns = phy_rddata_valid && ~periodic_rd && rd_rmw;
always @(posedge clk) wr_ecc_buf <= #TCQ wr_ecc_buf_ns;
end
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : col_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// The column machine manages the dq bus. Since there is a single DQ
// bus, and the column part of the DRAM is tightly coupled to this DQ
// bus, conceptually, the DQ bus and all of the column hardware in
// a multi rank DRAM array are managed as a single unit.
//
//
// The column machine does not "enforce" the column timing directly.
// It generates information and sends it to the bank machines. If the
// bank machines incorrectly make a request, the column machine will
// simply overwrite the existing request with the new request even
// if this would result in a timing or protocol violation.
//
// The column machine
// hosts the block that controls read and write data transfer
// to and from the dq bus.
//
// And if configured, there is provision for tracking the address
// of a command as it moves through the column pipeline. This
// address will be logged for detected ECC errors.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_col_mach #
(
parameter TCQ = 100,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DELAY_WR_DATA_CNTRL = 0,
parameter DQS_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nCK_PER_CLK = 2,
parameter nPHY_WRLAT = 0,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16
)
(/*AUTOARG*/
// Outputs
dq_busy_data, wr_data_offset, mc_wrdata_en, wr_data_en,
wr_data_addr, rd_rmw, ecc_err_addr, ecc_status_valid, wr_ecc_buf, rd_data_end,
rd_data_addr, rd_data_offset, rd_data_en, col_read_fifo_empty,
// Inputs
clk, rst, sent_col, col_size, col_wr_data_buf_addr,
phy_rddata_valid, col_periodic_rd, col_data_buf_addr, col_rmw,
col_rd_wr, col_ra, col_ba, col_row, col_a
);
input clk;
input rst;
input sent_col;
input col_rd_wr;
output reg dq_busy_data = 1'b0;
// The following generates a column command disable based mostly on the type
// of DRAM and the fabric to DRAM CK ratio.
generate
if ((nCK_PER_CLK == 1) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
begin : three_bumps
reg [1:0] granted_col_d_r;
wire [1:0] granted_col_d_ns = {sent_col, granted_col_d_r[1]};
always @(posedge clk) granted_col_d_r <= #TCQ granted_col_d_ns;
always @(/*AS*/granted_col_d_r or sent_col)
dq_busy_data = sent_col || |granted_col_d_r;
end
if (((nCK_PER_CLK == 2) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
|| ((nCK_PER_CLK == 1) && ((BURST_MODE == "4") || (DRAM_TYPE == "DDR2"))))
begin : one_bump
always @(/*AS*/sent_col) dq_busy_data = sent_col;
end
endgenerate
// This generates a data offset based on fabric clock to DRAM CK ratio and
// the size bit. Note that this is different that the dq_busy_data signal
// generated above.
reg [1:0] offset_r = 2'b0;
reg [1:0] offset_ns = 2'b0;
input col_size;
wire data_end;
generate
if(nCK_PER_CLK == 4) begin : data_valid_4_1
// For 4:1 mode all data is transfered in a single beat so the default
// values of 0 for offset_r/offset_ns suffice - just tie off data_end
assign data_end = 1'b1;
end
else begin
if(DATA_BUF_OFFSET_WIDTH == 2) begin : data_valid_1_1
always @(col_size or offset_r or rst or sent_col) begin
if (rst) offset_ns = 2'b0;
else begin
offset_ns = offset_r;
if (sent_col) offset_ns = 2'b1;
else if (|offset_r && (offset_r != {col_size, 1'b1}))
offset_ns = offset_r + 2'b1;
else offset_ns = 2'b0;
end
end
always @(posedge clk) offset_r <= #TCQ offset_ns;
assign data_end = col_size ? (offset_r == 2'b11) : offset_r[0];
end
else begin : data_valid_2_1
always @(col_size or rst or sent_col)
offset_ns[0] = rst ? 1'b0 : sent_col && col_size;
always @(posedge clk) offset_r[0] <= #TCQ offset_ns[0];
assign data_end = col_size ? offset_r[0] : 1'b1;
end
end
endgenerate
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r1 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r2 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg col_rd_wr_r1;
reg col_rd_wr_r2;
generate
if ((nPHY_WRLAT >= 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0
always @(posedge clk) offset_r1 <=
#TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr;
end
if(nPHY_WRLAT == 2) begin : offset_pipe_1
always @(posedge clk) offset_r2 <=
#TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1;
end
endgenerate
output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1)
? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]
: (EARLY_WR_DATA_ADDR == "OFF")
? offset_r[DATA_BUF_OFFSET_WIDTH-1:0]
: offset_ns[DATA_BUF_OFFSET_WIDTH-1:0];
reg sent_col_r1;
reg sent_col_r2;
always @(posedge clk) sent_col_r1 <= #TCQ sent_col;
always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1;
wire wrdata_en = (nPHY_WRLAT == 0) ?
(sent_col || |offset_r) & ~col_rd_wr :
(nPHY_WRLAT == 1) ?
(sent_col_r1 || |offset_r1) & ~col_rd_wr_r1 :
//(nPHY_WRLAT >= 2) ?
(sent_col_r2 || |offset_r2) & ~col_rd_wr_r2;
output wire mc_wrdata_en;
assign mc_wrdata_en = wrdata_en;
output wire wr_data_en;
assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1)
? ((sent_col_r1 || |offset_r1) && ~col_rd_wr_r1)
: ((sent_col || |offset_r) && ~col_rd_wr);
input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
generate
if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr;
assign wr_data_addr = col_wr_data_buf_addr_r;
end
else begin : delay_wr_data_cntrl_ne_1
assign wr_data_addr = col_wr_data_buf_addr;
end
endgenerate
// CAS-RD to mc_rddata_en
wire read_data_valid = (sent_col || |offset_r) && col_rd_wr;
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
// Implement FIFO that records reads as they are sent to the DRAM.
// When phy_rddata_valid is returned some unknown time later, the
// FIFO output is used to control how the data is interpreted.
input phy_rddata_valid;
output wire rd_rmw;
output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
output reg ecc_status_valid;
output reg wr_ecc_buf;
output reg rd_data_end;
output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
output reg rd_data_en /* synthesis syn_maxfan = 10 */;
output col_read_fifo_empty;
input col_periodic_rd;
input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
input col_rmw;
input [RANK_WIDTH-1:0] col_ra;
input [BANK_WIDTH-1:0] col_ba;
input [ROW_WIDTH-1:0] col_row;
input [ROW_WIDTH-1:0] col_a;
// Real column address (skip A10/AP and A12/BC#). The maximum width is 12;
// the width will be tailored for the target DRAM downstream.
wire [11:0] col_a_full;
// Minimum row width is 12; take remaining 11 bits after omitting A10/AP
assign col_a_full[10:0] = {col_a[11], col_a[9:0]};
// Get the 12th bit when row address width accommodates it; omit A12/BC#
generate
if (ROW_WIDTH >= 14) begin : COL_A_FULL_11_1
assign col_a_full[11] = col_a[13];
end else begin : COL_A_FULL_11_0
assign col_a_full[11] = 0;
end
endgenerate
// Extract only the width of the target DRAM
wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0];
localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH;
localparam FIFO_WIDTH = 1 /*data_end*/ +
1 /*periodic_rd*/ +
DATA_BUF_ADDR_WIDTH +
DATA_BUF_OFFSET_WIDTH +
((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH);
localparam FULL_RAM_CNT = (FIFO_WIDTH/6);
localparam REMAINDER = FIFO_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
begin : read_fifo
wire [MC_ERR_LINE_WIDTH:0] ecc_line;
if (CS_WIDTH == 1)
assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted};
else
assign ecc_line = {col_rmw,
col_ra,
col_ba,
col_row,
col_a_extracted};
wire [FIFO_WIDTH-1:0] real_fifo_data;
if (ECC == "OFF")
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0]};
else
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0],
ecc_line};
wire [RAM_WIDTH-1:0] fifo_in_data;
if (REMAINDER == 0)
assign fifo_in_data = real_fifo_data;
else
assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data};
wire [RAM_WIDTH-1:0] fifo_out_data_ns;
reg [4:0] head_r;
wire [4:0] head_ns = rst ? 5'b0 : read_data_valid
? (head_r + 5'b1)
: head_r;
always @(posedge clk) head_r <= #TCQ head_ns;
reg [4:0] tail_r;
wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid
? (tail_r + 5'b1)
: tail_r;
always @(posedge clk) tail_r <= #TCQ tail_ns;
assign col_read_fifo_empty = head_r == tail_r ? 1'b1 : 1'b0;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : fifo_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(fifo_out_data_ns[((i*6)+4)+:2]),
.DOB(fifo_out_data_ns[((i*6)+2)+:2]),
.DOC(fifo_out_data_ns[((i*6)+0)+:2]),
.DOD(),
.DIA(fifo_in_data[((i*6)+4)+:2]),
.DIB(fifo_in_data[((i*6)+2)+:2]),
.DIC(fifo_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(tail_ns),
.ADDRB(tail_ns),
.ADDRC(tail_ns),
.ADDRD(head_r),
.WE(1'b1),
.WCLK(clk)
);
end // block: fifo_ram
reg [RAM_WIDTH-1:0] fifo_out_data_r;
always @(posedge clk) fifo_out_data_r <= #TCQ fifo_out_data_ns;
// When ECC is ON, most of the FIFO output is delayed
// by one state.
if (ECC == "OFF") begin
reg periodic_rd;
always @(/*AS*/phy_rddata_valid or fifo_out_data_r) begin
{rd_data_end,
periodic_rd,
rd_data_addr,
rd_data_offset} = fifo_out_data_r[FIFO_WIDTH-1:0];
ecc_err_addr = {MC_ERR_ADDR_WIDTH{1'b0}};
rd_data_en = phy_rddata_valid && ~periodic_rd;
ecc_status_valid = 1'b0;
wr_ecc_buf = 1'b0;
end
assign rd_rmw = 1'b0;
end
else begin
wire rd_data_end_ns;
wire periodic_rd;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset_ns;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr_ns;
assign {rd_data_end_ns,
periodic_rd,
rd_data_addr_ns,
rd_data_offset_ns,
rd_rmw,
ecc_err_addr_ns[DATA_BUF_OFFSET_WIDTH+:MC_ERR_LINE_WIDTH]} =
{fifo_out_data_r[FIFO_WIDTH-1:0]};
assign ecc_err_addr_ns[0+:DATA_BUF_OFFSET_WIDTH] = rd_data_offset_ns;
always @(posedge clk) rd_data_end <= #TCQ rd_data_end_ns;
always @(posedge clk) rd_data_addr <= #TCQ rd_data_addr_ns;
always @(posedge clk) rd_data_offset <= #TCQ rd_data_offset_ns;
always @(posedge clk) ecc_err_addr <= #TCQ ecc_err_addr_ns;
wire rd_data_en_ns = phy_rddata_valid && ~(periodic_rd || rd_rmw);
always @(posedge clk) rd_data_en <= rd_data_en_ns;
wire ecc_status_valid_ns = phy_rddata_valid && ~periodic_rd;
always @(posedge clk) ecc_status_valid <= #TCQ ecc_status_valid_ns;
wire wr_ecc_buf_ns = phy_rddata_valid && ~periodic_rd && rd_rmw;
always @(posedge clk) wr_ecc_buf <= #TCQ wr_ecc_buf_ns;
end
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : col_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// The column machine manages the dq bus. Since there is a single DQ
// bus, and the column part of the DRAM is tightly coupled to this DQ
// bus, conceptually, the DQ bus and all of the column hardware in
// a multi rank DRAM array are managed as a single unit.
//
//
// The column machine does not "enforce" the column timing directly.
// It generates information and sends it to the bank machines. If the
// bank machines incorrectly make a request, the column machine will
// simply overwrite the existing request with the new request even
// if this would result in a timing or protocol violation.
//
// The column machine
// hosts the block that controls read and write data transfer
// to and from the dq bus.
//
// And if configured, there is provision for tracking the address
// of a command as it moves through the column pipeline. This
// address will be logged for detected ECC errors.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_col_mach #
(
parameter TCQ = 100,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DELAY_WR_DATA_CNTRL = 0,
parameter DQS_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nCK_PER_CLK = 2,
parameter nPHY_WRLAT = 0,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16
)
(/*AUTOARG*/
// Outputs
dq_busy_data, wr_data_offset, mc_wrdata_en, wr_data_en,
wr_data_addr, rd_rmw, ecc_err_addr, ecc_status_valid, wr_ecc_buf, rd_data_end,
rd_data_addr, rd_data_offset, rd_data_en, col_read_fifo_empty,
// Inputs
clk, rst, sent_col, col_size, col_wr_data_buf_addr,
phy_rddata_valid, col_periodic_rd, col_data_buf_addr, col_rmw,
col_rd_wr, col_ra, col_ba, col_row, col_a
);
input clk;
input rst;
input sent_col;
input col_rd_wr;
output reg dq_busy_data = 1'b0;
// The following generates a column command disable based mostly on the type
// of DRAM and the fabric to DRAM CK ratio.
generate
if ((nCK_PER_CLK == 1) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
begin : three_bumps
reg [1:0] granted_col_d_r;
wire [1:0] granted_col_d_ns = {sent_col, granted_col_d_r[1]};
always @(posedge clk) granted_col_d_r <= #TCQ granted_col_d_ns;
always @(/*AS*/granted_col_d_r or sent_col)
dq_busy_data = sent_col || |granted_col_d_r;
end
if (((nCK_PER_CLK == 2) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
|| ((nCK_PER_CLK == 1) && ((BURST_MODE == "4") || (DRAM_TYPE == "DDR2"))))
begin : one_bump
always @(/*AS*/sent_col) dq_busy_data = sent_col;
end
endgenerate
// This generates a data offset based on fabric clock to DRAM CK ratio and
// the size bit. Note that this is different that the dq_busy_data signal
// generated above.
reg [1:0] offset_r = 2'b0;
reg [1:0] offset_ns = 2'b0;
input col_size;
wire data_end;
generate
if(nCK_PER_CLK == 4) begin : data_valid_4_1
// For 4:1 mode all data is transfered in a single beat so the default
// values of 0 for offset_r/offset_ns suffice - just tie off data_end
assign data_end = 1'b1;
end
else begin
if(DATA_BUF_OFFSET_WIDTH == 2) begin : data_valid_1_1
always @(col_size or offset_r or rst or sent_col) begin
if (rst) offset_ns = 2'b0;
else begin
offset_ns = offset_r;
if (sent_col) offset_ns = 2'b1;
else if (|offset_r && (offset_r != {col_size, 1'b1}))
offset_ns = offset_r + 2'b1;
else offset_ns = 2'b0;
end
end
always @(posedge clk) offset_r <= #TCQ offset_ns;
assign data_end = col_size ? (offset_r == 2'b11) : offset_r[0];
end
else begin : data_valid_2_1
always @(col_size or rst or sent_col)
offset_ns[0] = rst ? 1'b0 : sent_col && col_size;
always @(posedge clk) offset_r[0] <= #TCQ offset_ns[0];
assign data_end = col_size ? offset_r[0] : 1'b1;
end
end
endgenerate
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r1 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r2 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg col_rd_wr_r1;
reg col_rd_wr_r2;
generate
if ((nPHY_WRLAT >= 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0
always @(posedge clk) offset_r1 <=
#TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr;
end
if(nPHY_WRLAT == 2) begin : offset_pipe_1
always @(posedge clk) offset_r2 <=
#TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1;
end
endgenerate
output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1)
? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]
: (EARLY_WR_DATA_ADDR == "OFF")
? offset_r[DATA_BUF_OFFSET_WIDTH-1:0]
: offset_ns[DATA_BUF_OFFSET_WIDTH-1:0];
reg sent_col_r1;
reg sent_col_r2;
always @(posedge clk) sent_col_r1 <= #TCQ sent_col;
always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1;
wire wrdata_en = (nPHY_WRLAT == 0) ?
(sent_col || |offset_r) & ~col_rd_wr :
(nPHY_WRLAT == 1) ?
(sent_col_r1 || |offset_r1) & ~col_rd_wr_r1 :
//(nPHY_WRLAT >= 2) ?
(sent_col_r2 || |offset_r2) & ~col_rd_wr_r2;
output wire mc_wrdata_en;
assign mc_wrdata_en = wrdata_en;
output wire wr_data_en;
assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1)
? ((sent_col_r1 || |offset_r1) && ~col_rd_wr_r1)
: ((sent_col || |offset_r) && ~col_rd_wr);
input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
generate
if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr;
assign wr_data_addr = col_wr_data_buf_addr_r;
end
else begin : delay_wr_data_cntrl_ne_1
assign wr_data_addr = col_wr_data_buf_addr;
end
endgenerate
// CAS-RD to mc_rddata_en
wire read_data_valid = (sent_col || |offset_r) && col_rd_wr;
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
// Implement FIFO that records reads as they are sent to the DRAM.
// When phy_rddata_valid is returned some unknown time later, the
// FIFO output is used to control how the data is interpreted.
input phy_rddata_valid;
output wire rd_rmw;
output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
output reg ecc_status_valid;
output reg wr_ecc_buf;
output reg rd_data_end;
output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
output reg rd_data_en /* synthesis syn_maxfan = 10 */;
output col_read_fifo_empty;
input col_periodic_rd;
input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
input col_rmw;
input [RANK_WIDTH-1:0] col_ra;
input [BANK_WIDTH-1:0] col_ba;
input [ROW_WIDTH-1:0] col_row;
input [ROW_WIDTH-1:0] col_a;
// Real column address (skip A10/AP and A12/BC#). The maximum width is 12;
// the width will be tailored for the target DRAM downstream.
wire [11:0] col_a_full;
// Minimum row width is 12; take remaining 11 bits after omitting A10/AP
assign col_a_full[10:0] = {col_a[11], col_a[9:0]};
// Get the 12th bit when row address width accommodates it; omit A12/BC#
generate
if (ROW_WIDTH >= 14) begin : COL_A_FULL_11_1
assign col_a_full[11] = col_a[13];
end else begin : COL_A_FULL_11_0
assign col_a_full[11] = 0;
end
endgenerate
// Extract only the width of the target DRAM
wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0];
localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH;
localparam FIFO_WIDTH = 1 /*data_end*/ +
1 /*periodic_rd*/ +
DATA_BUF_ADDR_WIDTH +
DATA_BUF_OFFSET_WIDTH +
((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH);
localparam FULL_RAM_CNT = (FIFO_WIDTH/6);
localparam REMAINDER = FIFO_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
begin : read_fifo
wire [MC_ERR_LINE_WIDTH:0] ecc_line;
if (CS_WIDTH == 1)
assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted};
else
assign ecc_line = {col_rmw,
col_ra,
col_ba,
col_row,
col_a_extracted};
wire [FIFO_WIDTH-1:0] real_fifo_data;
if (ECC == "OFF")
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0]};
else
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0],
ecc_line};
wire [RAM_WIDTH-1:0] fifo_in_data;
if (REMAINDER == 0)
assign fifo_in_data = real_fifo_data;
else
assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data};
wire [RAM_WIDTH-1:0] fifo_out_data_ns;
reg [4:0] head_r;
wire [4:0] head_ns = rst ? 5'b0 : read_data_valid
? (head_r + 5'b1)
: head_r;
always @(posedge clk) head_r <= #TCQ head_ns;
reg [4:0] tail_r;
wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid
? (tail_r + 5'b1)
: tail_r;
always @(posedge clk) tail_r <= #TCQ tail_ns;
assign col_read_fifo_empty = head_r == tail_r ? 1'b1 : 1'b0;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : fifo_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(fifo_out_data_ns[((i*6)+4)+:2]),
.DOB(fifo_out_data_ns[((i*6)+2)+:2]),
.DOC(fifo_out_data_ns[((i*6)+0)+:2]),
.DOD(),
.DIA(fifo_in_data[((i*6)+4)+:2]),
.DIB(fifo_in_data[((i*6)+2)+:2]),
.DIC(fifo_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(tail_ns),
.ADDRB(tail_ns),
.ADDRC(tail_ns),
.ADDRD(head_r),
.WE(1'b1),
.WCLK(clk)
);
end // block: fifo_ram
reg [RAM_WIDTH-1:0] fifo_out_data_r;
always @(posedge clk) fifo_out_data_r <= #TCQ fifo_out_data_ns;
// When ECC is ON, most of the FIFO output is delayed
// by one state.
if (ECC == "OFF") begin
reg periodic_rd;
always @(/*AS*/phy_rddata_valid or fifo_out_data_r) begin
{rd_data_end,
periodic_rd,
rd_data_addr,
rd_data_offset} = fifo_out_data_r[FIFO_WIDTH-1:0];
ecc_err_addr = {MC_ERR_ADDR_WIDTH{1'b0}};
rd_data_en = phy_rddata_valid && ~periodic_rd;
ecc_status_valid = 1'b0;
wr_ecc_buf = 1'b0;
end
assign rd_rmw = 1'b0;
end
else begin
wire rd_data_end_ns;
wire periodic_rd;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset_ns;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr_ns;
assign {rd_data_end_ns,
periodic_rd,
rd_data_addr_ns,
rd_data_offset_ns,
rd_rmw,
ecc_err_addr_ns[DATA_BUF_OFFSET_WIDTH+:MC_ERR_LINE_WIDTH]} =
{fifo_out_data_r[FIFO_WIDTH-1:0]};
assign ecc_err_addr_ns[0+:DATA_BUF_OFFSET_WIDTH] = rd_data_offset_ns;
always @(posedge clk) rd_data_end <= #TCQ rd_data_end_ns;
always @(posedge clk) rd_data_addr <= #TCQ rd_data_addr_ns;
always @(posedge clk) rd_data_offset <= #TCQ rd_data_offset_ns;
always @(posedge clk) ecc_err_addr <= #TCQ ecc_err_addr_ns;
wire rd_data_en_ns = phy_rddata_valid && ~(periodic_rd || rd_rmw);
always @(posedge clk) rd_data_en <= rd_data_en_ns;
wire ecc_status_valid_ns = phy_rddata_valid && ~periodic_rd;
always @(posedge clk) ecc_status_valid <= #TCQ ecc_status_valid_ns;
wire wr_ecc_buf_ns = phy_rddata_valid && ~periodic_rd && rd_rmw;
always @(posedge clk) wr_ecc_buf <= #TCQ wr_ecc_buf_ns;
end
end
endgenerate
endmodule
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