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shailja
/
fine-tuned-codegen-16B-Verilog
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15
Text Generation
Transformers
PyTorch
shailja/Verilog_GitHub
codegen
code
Eval Results
arxiv:
2212.11140
License:
bigcode-openrail-m
Model card
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fine-tuned-codegen-16B-Verilog
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2 contributors
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2 commits
shailja-thakur
uploading 16B Verilog LLM
af0f1d3
over 2 years ago
.gitattributes
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initial commit
over 2 years ago
README.md
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over 2 years ago
fine-tuned-codegen-16B-4gpu.tar.zst
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LFS
uploading 16B Verilog LLM
over 2 years ago
