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4,870 | data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v | 112,176,817 | FP_to_Posit_tb.v | v | 54 | 55 | [] | [] | [] | null | Syntax Error | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #101 in = 32\'h0080ffff;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #325150 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n ^\n%Error: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v:24: Cannot find file containing module: \'FP_to_posit\'\nFP_to_posit #(.N(N), .E(E), .es(es)) d1 (\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/FP_to_posit\n data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/FP_to_posit.v\n data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/FP_to_posit.sv\n FP_to_posit\n FP_to_posit.v\n FP_to_posit.sv\n obj_dir/FP_to_posit\n obj_dir/FP_to_posit.v\n obj_dir/FP_to_posit.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,274 | module | module FP_to_posit_tb_v;
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N=32;
parameter E=8;
parameter Bs=log2(N);
parameter es = 4;
reg [N-1:0] in;
reg clk;
wire [N-1:0] out;
FP_to_posit #(.N(N), .E(E), .es(es)) d1 (
.in(in),
.out(out)
);
initial begin
clk = 1;
#101 in = 32'h0080ffff;
#325150
$fclose(outfile);
$finish;
end
always #5 clk=~clk;
always @(posedge clk) begin
if (in < 32'h7f7fffff)
in <= in + 65535;
end
integer outfile;
initial outfile = $fopen("FP_to_posit_out.txt", "wb");
always @(negedge clk) begin
$fwrite(outfile, "%h\t%h\n",in,out);
end
endmodule | module FP_to_posit_tb_v; |
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N=32;
parameter E=8;
parameter Bs=log2(N);
parameter es = 4;
reg [N-1:0] in;
reg clk;
wire [N-1:0] out;
FP_to_posit #(.N(N), .E(E), .es(es)) d1 (
.in(in),
.out(out)
);
initial begin
clk = 1;
#101 in = 32'h0080ffff;
#325150
$fclose(outfile);
$finish;
end
always #5 clk=~clk;
always @(posedge clk) begin
if (in < 32'h7f7fffff)
in <= in + 65535;
end
integer outfile;
initial outfile = $fopen("FP_to_posit_out.txt", "wb");
always @(negedge clk) begin
$fwrite(outfile, "%h\t%h\n",in,out);
end
endmodule | 36 |
4,871 | data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v | 112,176,817 | FP_to_Posit_tb.v | v | 54 | 55 | [] | [] | [] | null | Syntax Error | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #101 in = 32\'h0080ffff;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #325150 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n ^\n%Error: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v:24: Cannot find file containing module: \'FP_to_posit\'\nFP_to_posit #(.N(N), .E(E), .es(es)) d1 (\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/FP_to_posit\n data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/FP_to_posit.v\n data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/FP_to_posit.sv\n FP_to_posit\n FP_to_posit.v\n FP_to_posit.sv\n obj_dir/FP_to_posit\n obj_dir/FP_to_posit.v\n obj_dir/FP_to_posit.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,274 | function | function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | function [31:0] log2; |
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | 36 |
4,875 | data/full_repos/permissive/112176817/Posit-Adder/LZD_N.v | 112,176,817 | LZD_N.v | v | 61 | 54 | [] | [] | [] | null | Syntax Error | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Adder/LZD_N.v:47: Logical Operator GENIF expects 1 bit on the If, but If\'s AND generates 32 or 7 bits.\n : ... In instance LZD_N.l1\n else if (N & (N-1))\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Adder/LZD_N.v:47: Logical Operator GENIF expects 1 bit on the If, but If\'s AND generates 32 bits.\n : ... In instance LZD_N.l1.genblk2.genblk2.h\n else if (N & (N-1))\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 3,282 | module | module LZD_N (in, out);
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N = 64;
parameter S = log2(N);
input [N-1:0] in;
output [S-1:0] out;
wire vld;
LZD #(.N(N)) l1 (in, out, vld);
endmodule | module LZD_N (in, out); |
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N = 64;
parameter S = log2(N);
input [N-1:0] in;
output [S-1:0] out;
wire vld;
LZD #(.N(N)) l1 (in, out, vld);
endmodule | 36 |
4,876 | data/full_repos/permissive/112176817/Posit-Adder/LZD_N.v | 112,176,817 | LZD_N.v | v | 61 | 54 | [] | [] | [] | null | Syntax Error | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Adder/LZD_N.v:47: Logical Operator GENIF expects 1 bit on the If, but If\'s AND generates 32 or 7 bits.\n : ... In instance LZD_N.l1\n else if (N & (N-1))\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Adder/LZD_N.v:47: Logical Operator GENIF expects 1 bit on the If, but If\'s AND generates 32 bits.\n : ... In instance LZD_N.l1.genblk2.genblk2.h\n else if (N & (N-1))\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 3,282 | module | module LZD (in, out, vld);
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N = 64;
parameter S = log2(N);
input [N-1:0] in;
output [S-1:0] out;
output vld;
generate
if (N == 2)
begin
assign vld = ~∈
assign out = in[1] & ~in[0];
end
else if (N & (N-1))
LZD #(1<<S) LZD ({1<<S {1'b0}} | in,out,vld);
else
begin
wire [S-2:0] out_l;
wire [S-2:0] out_h;
wire out_vl, out_vh;
LZD #(N>>1) l(in[(N>>1)-1:0],out_l,out_vl);
LZD #(N>>1) h(in[N-1:N>>1],out_h,out_vh);
assign vld = out_vl | out_vh;
assign out = out_vh ? {1'b0,out_h} : {out_vl,out_l};
end
endgenerate
endmodule | module LZD (in, out, vld); |
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N = 64;
parameter S = log2(N);
input [N-1:0] in;
output [S-1:0] out;
output vld;
generate
if (N == 2)
begin
assign vld = ~∈
assign out = in[1] & ~in[0];
end
else if (N & (N-1))
LZD #(1<<S) LZD ({1<<S {1'b0}} | in,out,vld);
else
begin
wire [S-2:0] out_l;
wire [S-2:0] out_h;
wire out_vl, out_vh;
LZD #(N>>1) l(in[(N>>1)-1:0],out_l,out_vl);
LZD #(N>>1) h(in[N-1:N>>1],out_h,out_vh);
assign vld = out_vl | out_vh;
assign out = out_vh ? {1'b0,out_h} : {out_vl,out_l};
end
endgenerate
endmodule | 36 |
4,877 | data/full_repos/permissive/112176817/Posit-Adder/LZD_N.v | 112,176,817 | LZD_N.v | v | 61 | 54 | [] | [] | [] | null | Syntax Error | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Adder/LZD_N.v:47: Logical Operator GENIF expects 1 bit on the If, but If\'s AND generates 32 or 7 bits.\n : ... In instance LZD_N.l1\n else if (N & (N-1))\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Adder/LZD_N.v:47: Logical Operator GENIF expects 1 bit on the If, but If\'s AND generates 32 bits.\n : ... In instance LZD_N.l1.genblk2.genblk2.h\n else if (N & (N-1))\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 3,282 | function | function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | function [31:0] log2; |
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | 36 |
4,881 | data/full_repos/permissive/112176817/Posit-Adder/sub_N.v | 112,176,817 | sub_N.v | v | 9 | 32 | [] | [] | [] | [(1, 6)] | null | data/verilator_xmls/f3cb5b5f-8076-42eb-9901-5cce9a94d406.xml | null | 3,285 | module | module sub_N (a,b,c);
parameter N=10;
input [N-1:0] a,b;
output [N:0] c;
assign c = {1'b0,a} - {1'b0,b};
endmodule | module sub_N (a,b,c); |
parameter N=10;
input [N-1:0] a,b;
output [N:0] c;
assign c = {1'b0,a} - {1'b0,b};
endmodule | 36 |
4,882 | data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v | 112,176,817 | posit_mult.v | v | 81 | 125 | [] | [] | [] | null | Syntax Error | null | 1: b'%Error: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:43: Cannot find file containing module: \'data_extract\'\ndata_extract #(.N(N),.es(es)) uut_de1(.in(xin1), .rc(rc1), .regime(regime1), .exp(e1), .mant(mant1), .Lshift(Lshift1));\n^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112176817/Posit-Multiplier,data/full_repos/permissive/112176817/data_extract\n data/full_repos/permissive/112176817/Posit-Multiplier,data/full_repos/permissive/112176817/data_extract.v\n data/full_repos/permissive/112176817/Posit-Multiplier,data/full_repos/permissive/112176817/data_extract.sv\n data_extract\n data_extract.v\n data_extract.sv\n obj_dir/data_extract\n obj_dir/data_extract.v\n obj_dir/data_extract.sv\n%Error: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:44: Cannot find file containing module: \'data_extract\'\ndata_extract #(.N(N),.es(es)) uut_de2(.in(xin2), .rc(rc2), .regime(regime2), .exp(e2), .mant(mant2), .Lshift(Lshift2));\n^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:56: Operator NEGATE expects 6 bits on the LHS, but LHS\'s VARREF \'regime1\' generates 4 bits.\n : ... In instance posit_mult\nwire [Bs+1:0] r1 = rc1 ? {2\'b0,regime1} : -regime1;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:57: Operator NEGATE expects 6 bits on the LHS, but LHS\'s VARREF \'regime2\' generates 4 bits.\n : ... In instance posit_mult\nwire [Bs+1:0] r2 = rc2 ? {2\'b0,regime2} : -regime2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:58: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'mult_m_ovf\' generates 1 bits.\n : ... In instance posit_mult\nwire [Bs+es+1:0] mult_e = {r1, e1} + {r2, e2} + mult_m_ovf;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:61: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 9 bits.\n : ... In instance posit_mult\nwire [es+Bs:0] mult_eN = mult_e[es+Bs+1] ? -mult_e : mult_e;\n ^\n%Error: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:71: Cannot find file containing module: \'DSR_right_N_S\'\nDSR_right_N_S #(.N(2*N), .S(Bs+1)) dsr2 (.a(tmp_o), .b(r_o[Bs] ? {Bs{1\'b1}} : r_o), .c(tmp1_o));\n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n' | 3,291 | module | module posit_mult (in1, in2, start, out, inf, zero, done);
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N = 16;
parameter Bs = log2(N);
parameter es = 3;
input [N-1:0] in1, in2;
input start;
output [N-1:0] out;
output inf, zero;
output done;
wire start0= start;
wire s1 = in1[N-1];
wire s2 = in2[N-1];
wire zero_tmp1 = |in1[N-2:0];
wire zero_tmp2 = |in2[N-2:0];
wire inf1 = in1[N-1] & (~zero_tmp1),
inf2 = in2[N-1] & (~zero_tmp2);
wire zero1 = ~(in1[N-1] | zero_tmp1),
zero2 = ~(in2[N-1] | zero_tmp2);
assign inf = inf1 | inf2,
zero = zero1 & zero2;
wire rc1, rc2;
wire [Bs-1:0] regime1, regime2, Lshift1, Lshift2;
wire [es-1:0] e1, e2;
wire [N-es-1:0] mant1, mant2;
wire [N-1:0] xin1 = s1 ? -in1 : in1;
wire [N-1:0] xin2 = s2 ? -in2 : in2;
data_extract #(.N(N),.es(es)) uut_de1(.in(xin1), .rc(rc1), .regime(regime1), .exp(e1), .mant(mant1), .Lshift(Lshift1));
data_extract #(.N(N),.es(es)) uut_de2(.in(xin2), .rc(rc2), .regime(regime2), .exp(e2), .mant(mant2), .Lshift(Lshift2));
wire [N-es:0] m1 = {zero_tmp1,mant1},
m2 = {zero_tmp2,mant2};
wire mult_s = s1 ^ s2;
wire [2*(N-es)+1:0] mult_m = m1*m2;
wire mult_m_ovf = mult_m[2*(N-es)+1];
wire [2*(N-es)+1:0] mult_mN = ~mult_m_ovf ? mult_m << 1'b1 : mult_m;
wire [Bs+1:0] r1 = rc1 ? {2'b0,regime1} : -regime1;
wire [Bs+1:0] r2 = rc2 ? {2'b0,regime2} : -regime2;
wire [Bs+es+1:0] mult_e = {r1, e1} + {r2, e2} + mult_m_ovf;
wire [es+Bs:0] mult_eN = mult_e[es+Bs+1] ? -mult_e : mult_e;
wire [es-1:0] e_o = (mult_e[es+Bs+1] & |mult_eN[es-1:0]) ? mult_e[es-1:0] : mult_eN[es-1:0];
wire [Bs:0] r_o = (~mult_e[es+Bs+1] || (mult_e[es+Bs+1] & |mult_eN[es-1:0])) ? mult_eN[es+Bs:es] + 1'b1 : mult_eN[es+Bs:es];
wire [2*N-1:0]tmp_o = {{N{~mult_e[es+Bs+1]}},mult_e[es+Bs+1],e_o,mult_mN[2*(N-es):N-es+2]};
wire [2*N-1:0] tmp1_o;
DSR_right_N_S #(.N(2*N), .S(Bs+1)) dsr2 (.a(tmp_o), .b(r_o[Bs] ? {Bs{1'b1}} : r_o), .c(tmp1_o));
wire [2*N-1:0] tmp1_oN = mult_s ? -tmp1_o : tmp1_o;
assign out = inf|zero|(~mult_mN[2*(N-es)+1]) ? {inf,{N-1{1'b0}}} : {mult_s, tmp1_oN[N-1:1]},
done = start0;
endmodule | module posit_mult (in1, in2, start, out, inf, zero, done); |
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N = 16;
parameter Bs = log2(N);
parameter es = 3;
input [N-1:0] in1, in2;
input start;
output [N-1:0] out;
output inf, zero;
output done;
wire start0= start;
wire s1 = in1[N-1];
wire s2 = in2[N-1];
wire zero_tmp1 = |in1[N-2:0];
wire zero_tmp2 = |in2[N-2:0];
wire inf1 = in1[N-1] & (~zero_tmp1),
inf2 = in2[N-1] & (~zero_tmp2);
wire zero1 = ~(in1[N-1] | zero_tmp1),
zero2 = ~(in2[N-1] | zero_tmp2);
assign inf = inf1 | inf2,
zero = zero1 & zero2;
wire rc1, rc2;
wire [Bs-1:0] regime1, regime2, Lshift1, Lshift2;
wire [es-1:0] e1, e2;
wire [N-es-1:0] mant1, mant2;
wire [N-1:0] xin1 = s1 ? -in1 : in1;
wire [N-1:0] xin2 = s2 ? -in2 : in2;
data_extract #(.N(N),.es(es)) uut_de1(.in(xin1), .rc(rc1), .regime(regime1), .exp(e1), .mant(mant1), .Lshift(Lshift1));
data_extract #(.N(N),.es(es)) uut_de2(.in(xin2), .rc(rc2), .regime(regime2), .exp(e2), .mant(mant2), .Lshift(Lshift2));
wire [N-es:0] m1 = {zero_tmp1,mant1},
m2 = {zero_tmp2,mant2};
wire mult_s = s1 ^ s2;
wire [2*(N-es)+1:0] mult_m = m1*m2;
wire mult_m_ovf = mult_m[2*(N-es)+1];
wire [2*(N-es)+1:0] mult_mN = ~mult_m_ovf ? mult_m << 1'b1 : mult_m;
wire [Bs+1:0] r1 = rc1 ? {2'b0,regime1} : -regime1;
wire [Bs+1:0] r2 = rc2 ? {2'b0,regime2} : -regime2;
wire [Bs+es+1:0] mult_e = {r1, e1} + {r2, e2} + mult_m_ovf;
wire [es+Bs:0] mult_eN = mult_e[es+Bs+1] ? -mult_e : mult_e;
wire [es-1:0] e_o = (mult_e[es+Bs+1] & |mult_eN[es-1:0]) ? mult_e[es-1:0] : mult_eN[es-1:0];
wire [Bs:0] r_o = (~mult_e[es+Bs+1] || (mult_e[es+Bs+1] & |mult_eN[es-1:0])) ? mult_eN[es+Bs:es] + 1'b1 : mult_eN[es+Bs:es];
wire [2*N-1:0]tmp_o = {{N{~mult_e[es+Bs+1]}},mult_e[es+Bs+1],e_o,mult_mN[2*(N-es):N-es+2]};
wire [2*N-1:0] tmp1_o;
DSR_right_N_S #(.N(2*N), .S(Bs+1)) dsr2 (.a(tmp_o), .b(r_o[Bs] ? {Bs{1'b1}} : r_o), .c(tmp1_o));
wire [2*N-1:0] tmp1_oN = mult_s ? -tmp1_o : tmp1_o;
assign out = inf|zero|(~mult_mN[2*(N-es)+1]) ? {inf,{N-1{1'b0}}} : {mult_s, tmp1_oN[N-1:1]},
done = start0;
endmodule | 36 |
4,883 | data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v | 112,176,817 | posit_mult.v | v | 81 | 125 | [] | [] | [] | null | Syntax Error | null | 1: b'%Error: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:43: Cannot find file containing module: \'data_extract\'\ndata_extract #(.N(N),.es(es)) uut_de1(.in(xin1), .rc(rc1), .regime(regime1), .exp(e1), .mant(mant1), .Lshift(Lshift1));\n^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112176817/Posit-Multiplier,data/full_repos/permissive/112176817/data_extract\n data/full_repos/permissive/112176817/Posit-Multiplier,data/full_repos/permissive/112176817/data_extract.v\n data/full_repos/permissive/112176817/Posit-Multiplier,data/full_repos/permissive/112176817/data_extract.sv\n data_extract\n data_extract.v\n data_extract.sv\n obj_dir/data_extract\n obj_dir/data_extract.v\n obj_dir/data_extract.sv\n%Error: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:44: Cannot find file containing module: \'data_extract\'\ndata_extract #(.N(N),.es(es)) uut_de2(.in(xin2), .rc(rc2), .regime(regime2), .exp(e2), .mant(mant2), .Lshift(Lshift2));\n^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:56: Operator NEGATE expects 6 bits on the LHS, but LHS\'s VARREF \'regime1\' generates 4 bits.\n : ... In instance posit_mult\nwire [Bs+1:0] r1 = rc1 ? {2\'b0,regime1} : -regime1;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:57: Operator NEGATE expects 6 bits on the LHS, but LHS\'s VARREF \'regime2\' generates 4 bits.\n : ... In instance posit_mult\nwire [Bs+1:0] r2 = rc2 ? {2\'b0,regime2} : -regime2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:58: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'mult_m_ovf\' generates 1 bits.\n : ... In instance posit_mult\nwire [Bs+es+1:0] mult_e = {r1, e1} + {r2, e2} + mult_m_ovf;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:61: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 9 bits.\n : ... In instance posit_mult\nwire [es+Bs:0] mult_eN = mult_e[es+Bs+1] ? -mult_e : mult_e;\n ^\n%Error: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:71: Cannot find file containing module: \'DSR_right_N_S\'\nDSR_right_N_S #(.N(2*N), .S(Bs+1)) dsr2 (.a(tmp_o), .b(r_o[Bs] ? {Bs{1\'b1}} : r_o), .c(tmp1_o));\n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n' | 3,291 | function | function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | function [31:0] log2; |
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | 36 |
4,886 | data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor/Posit_to_FP_tb.v | 112,176,817 | Posit_to_FP_tb.v | v | 56 | 55 | [] | [] | [] | null | Syntax Error | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor/Posit_to_FP_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #101 in = 65535;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor/Posit_to_FP_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #655360\n ^\n%Warning-STMTDLY: data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor/Posit_to_FP_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n ^\n%Error: data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor/Posit_to_FP_tb.v:24: Cannot find file containing module: \'Posit_to_FP\'\nPosit_to_FP #(.N(N), .E(E), .es(es)) d1 (\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor,data/full_repos/permissive/112176817/Posit_to_FP\n data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor,data/full_repos/permissive/112176817/Posit_to_FP.v\n data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor,data/full_repos/permissive/112176817/Posit_to_FP.sv\n Posit_to_FP\n Posit_to_FP.v\n Posit_to_FP.sv\n obj_dir/Posit_to_FP\n obj_dir/Posit_to_FP.v\n obj_dir/Posit_to_FP.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,299 | module | module Posit_to_FP_tb_v;
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N=32;
parameter E=8;
parameter Bs=log2(N);
parameter es = 3;
reg [N-1:0] in;
reg clk;
wire [N-1:0] out;
Posit_to_FP #(.N(N), .E(E), .es(es)) d1 (
.in(in),
.out(out)
);
initial begin
clk = 1;
#101 in = 65535;
#655360
$fclose(outfile);
$finish;
end
always #5 clk=~clk;
always @(posedge clk) begin
if (in < 32'hffffffff)
in <= in + 65535;
end
integer outfile;
initial outfile = $fopen("Posit_to_FP_out.txt", "wb");
always @(negedge clk) begin
$fwrite(outfile, "%h\t%h\n",in,out);
end
endmodule | module Posit_to_FP_tb_v; |
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N=32;
parameter E=8;
parameter Bs=log2(N);
parameter es = 3;
reg [N-1:0] in;
reg clk;
wire [N-1:0] out;
Posit_to_FP #(.N(N), .E(E), .es(es)) d1 (
.in(in),
.out(out)
);
initial begin
clk = 1;
#101 in = 65535;
#655360
$fclose(outfile);
$finish;
end
always #5 clk=~clk;
always @(posedge clk) begin
if (in < 32'hffffffff)
in <= in + 65535;
end
integer outfile;
initial outfile = $fopen("Posit_to_FP_out.txt", "wb");
always @(negedge clk) begin
$fwrite(outfile, "%h\t%h\n",in,out);
end
endmodule | 36 |
4,887 | data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor/Posit_to_FP_tb.v | 112,176,817 | Posit_to_FP_tb.v | v | 56 | 55 | [] | [] | [] | null | Syntax Error | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor/Posit_to_FP_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #101 in = 65535;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor/Posit_to_FP_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #655360\n ^\n%Warning-STMTDLY: data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor/Posit_to_FP_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n ^\n%Error: data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor/Posit_to_FP_tb.v:24: Cannot find file containing module: \'Posit_to_FP\'\nPosit_to_FP #(.N(N), .E(E), .es(es)) d1 (\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor,data/full_repos/permissive/112176817/Posit_to_FP\n data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor,data/full_repos/permissive/112176817/Posit_to_FP.v\n data/full_repos/permissive/112176817/Posit_to_Floating-Point_Convertor,data/full_repos/permissive/112176817/Posit_to_FP.sv\n Posit_to_FP\n Posit_to_FP.v\n Posit_to_FP.sv\n obj_dir/Posit_to_FP\n obj_dir/Posit_to_FP.v\n obj_dir/Posit_to_FP.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,299 | function | function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | function [31:0] log2; |
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | 36 |
4,888 | data/full_repos/permissive/112219256/alu.v | 112,219,256 | alu.v | v | 131 | 85 | [] | [] | [] | [(14, 130)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/112219256/alu.v:84: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'temp\' generates 1 bits.\n : ... In instance ALU\n Result = temp; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 3,300 | module | module ALU(
input wire [`DATA_WIDTH - 1:0] A,
input wire [`DATA_WIDTH - 1:0] B,
input wire [ 3:0] ALUop,
input wire is_signed,
output reg Overflow,
output reg CarryOut,
output reg Zero,
output reg [`DATA_WIDTH - 1:0] Result
);
reg temp;
parameter [3:0]
AND = 4'b0000,
OR = 4'b0001,
ADD = 4'b0010,
LF_16 = 4'b0011,
UNSIGNED_SLT = 4'b0100,
SLL = 4'b0101,
SUB = 4'b0110,
SIGNED_SLT = 4'b0111,
NOR = 4'b1001,
XOR = 4'b1010,
SRA = 4'b1011,
SRL = 4'b1100;
always @(*) begin
case(ALUop)
AND: begin
Result = A & B;
{Overflow,CarryOut,Zero,temp} = 'd0;
end
OR: begin
Result = A | B;
{Overflow,CarryOut,Zero,temp} = 'd0;
end
ADD: begin
{CarryOut,Result} = {A[31],A} + {B[31],B};
if((CarryOut != Result[31]) && (is_signed == 1))
Overflow = 1'b1;
else
Overflow = 1'b0;
{CarryOut,Zero,temp} = 'd0;
end
SUB: begin
{CarryOut,Result} = {A[31],A} - {B[31],B};
if((CarryOut != Result[31]) && (is_signed == 1))
Overflow = 1'b1;
else
Overflow = 1'b0;
{CarryOut,Zero,temp} = 'd0;
end
SIGNED_SLT : begin
if (A[`DATA_WIDTH - 2:0] < B[`DATA_WIDTH - 2:0])
temp = 1;
else
temp = 0;
if(~A[`DATA_WIDTH - 1] && B[`DATA_WIDTH - 1])
Result = 0;
else begin
if(A[`DATA_WIDTH - 1] && ~B[`DATA_WIDTH - 1])
Result = 1;
else
Result = temp;
end
{CarryOut,Zero,Overflow,temp} = 0;
end
LF_16 : begin
Result = {B[15:0],16'd0};
{Overflow,CarryOut,Zero,temp} = 'd0;
end
UNSIGNED_SLT : begin
Result = A < B ? 32'd1 : 32'd0;
{Overflow,CarryOut,Zero,temp} = 'd0;
end
SLL : begin
Result = B << (A[4:0]);
{Overflow,CarryOut,Zero,temp} = 'd0;
end
NOR : begin
Result = ~(A | B);
{Overflow,CarryOut,Zero,temp} = 'd0;
end
XOR : begin
Result = A ^ B;
{Overflow,CarryOut,Zero,temp} = 'd0;
end
SRA : begin
Result = $signed(B) >>> A[4:0];
{Overflow,CarryOut,Zero,temp} = 'd0;
end
SRL : begin
Result = B >> A[4:0];
{Overflow,CarryOut,Zero,temp} = 'd0;
end
default : begin
{Overflow,CarryOut,Zero,temp,Result} = 'd0;
end
endcase
end
endmodule | module ALU(
input wire [`DATA_WIDTH - 1:0] A,
input wire [`DATA_WIDTH - 1:0] B,
input wire [ 3:0] ALUop,
input wire is_signed,
output reg Overflow,
output reg CarryOut,
output reg Zero,
output reg [`DATA_WIDTH - 1:0] Result
); |
reg temp;
parameter [3:0]
AND = 4'b0000,
OR = 4'b0001,
ADD = 4'b0010,
LF_16 = 4'b0011,
UNSIGNED_SLT = 4'b0100,
SLL = 4'b0101,
SUB = 4'b0110,
SIGNED_SLT = 4'b0111,
NOR = 4'b1001,
XOR = 4'b1010,
SRA = 4'b1011,
SRL = 4'b1100;
always @(*) begin
case(ALUop)
AND: begin
Result = A & B;
{Overflow,CarryOut,Zero,temp} = 'd0;
end
OR: begin
Result = A | B;
{Overflow,CarryOut,Zero,temp} = 'd0;
end
ADD: begin
{CarryOut,Result} = {A[31],A} + {B[31],B};
if((CarryOut != Result[31]) && (is_signed == 1))
Overflow = 1'b1;
else
Overflow = 1'b0;
{CarryOut,Zero,temp} = 'd0;
end
SUB: begin
{CarryOut,Result} = {A[31],A} - {B[31],B};
if((CarryOut != Result[31]) && (is_signed == 1))
Overflow = 1'b1;
else
Overflow = 1'b0;
{CarryOut,Zero,temp} = 'd0;
end
SIGNED_SLT : begin
if (A[`DATA_WIDTH - 2:0] < B[`DATA_WIDTH - 2:0])
temp = 1;
else
temp = 0;
if(~A[`DATA_WIDTH - 1] && B[`DATA_WIDTH - 1])
Result = 0;
else begin
if(A[`DATA_WIDTH - 1] && ~B[`DATA_WIDTH - 1])
Result = 1;
else
Result = temp;
end
{CarryOut,Zero,Overflow,temp} = 0;
end
LF_16 : begin
Result = {B[15:0],16'd0};
{Overflow,CarryOut,Zero,temp} = 'd0;
end
UNSIGNED_SLT : begin
Result = A < B ? 32'd1 : 32'd0;
{Overflow,CarryOut,Zero,temp} = 'd0;
end
SLL : begin
Result = B << (A[4:0]);
{Overflow,CarryOut,Zero,temp} = 'd0;
end
NOR : begin
Result = ~(A | B);
{Overflow,CarryOut,Zero,temp} = 'd0;
end
XOR : begin
Result = A ^ B;
{Overflow,CarryOut,Zero,temp} = 'd0;
end
SRA : begin
Result = $signed(B) >>> A[4:0];
{Overflow,CarryOut,Zero,temp} = 'd0;
end
SRL : begin
Result = B >> A[4:0];
{Overflow,CarryOut,Zero,temp} = 'd0;
end
default : begin
{Overflow,CarryOut,Zero,temp,Result} = 'd0;
end
endcase
end
endmodule | 0 |
4,889 | data/full_repos/permissive/112219256/Bypass_Unit.v | 112,219,256 | Bypass_Unit.v | v | 89 | 153 | [] | [] | [] | [(11, 88)] | null | data/verilator_xmls/fb2647bc-d027-4aab-a43a-e7f2b030fa81.xml | null | 3,301 | module | module Bypass_Unit(
input wire clk,
input wire rst,
input wire is_rs_read,
input wire is_rt_read,
input wire MemToReg_ID_EXE,
input wire MemToReg_EXE_MEM,
input wire MemToReg_MEM_WB,
input wire [ 4:0] RegWaddr_EXE_MEM,
input wire [ 4:0] RegWaddr_MEM_WB,
input wire [ 4:0] RegWaddr_ID_EXE,
input wire [ 3:0] RegWrite_ID_EXE,
input wire [ 3:0] RegWrite_EXE_MEM,
input wire [ 3:0] RegWrite_MEM_WB,
input wire [ 4:0] rs_ID,
input wire [ 4:0] rt_ID,
input wire DIV_Busy,
input wire DIV,
input wire ex_int_handle,
output wire PCWrite,
output wire IRWrite,
output wire ID_EXE_Stall,
output wire [ 1:0] RegRdata1_src,
output wire [ 1:0] RegRdata2_src,
input is_j_or_b,
input de_valid,
input wb_valid,
input exe_valid,
input mem_valid
);
wire [ 4:0] rs_read, rt_read;
assign rs_read = (is_rs_read) ? rs_ID : 5'd0;
assign rt_read = (is_rt_read) ? rt_ID : 5'd0;
wire Haz_ID_EXE_rs, Haz_ID_EXE_rt,
Haz_ID_MEM_rs, Haz_ID_MEM_rt,
Haz_ID_WB_rs, Haz_ID_WB_rt;
assign Haz_ID_EXE_rs = (((|RegWaddr_ID_EXE) & (|rs_read)) & ((&(rs_read^~RegWaddr_ID_EXE)) & (|RegWrite_ID_EXE))) & exe_valid&(de_valid|is_j_or_b) ;
assign Haz_ID_EXE_rt = (((|RegWaddr_ID_EXE) & (|rt_read)) & ((&(rt_read^~RegWaddr_ID_EXE)) & (|RegWrite_ID_EXE))) & exe_valid&(de_valid|is_j_or_b);
assign Haz_ID_MEM_rs = ((|RegWaddr_EXE_MEM) & (|rs_read)) & ((&(rs_read^~RegWaddr_EXE_MEM)) & (|RegWrite_EXE_MEM)) & mem_valid&(de_valid|is_j_or_b);
assign Haz_ID_MEM_rt = ((|RegWaddr_EXE_MEM) & (|rt_read)) & ((&(rt_read^~RegWaddr_EXE_MEM)) & (|RegWrite_EXE_MEM)) & mem_valid&(de_valid|is_j_or_b);
assign Haz_ID_WB_rs = ((|RegWaddr_MEM_WB) & (|rs_read)) & ((&(rs_read^~RegWaddr_MEM_WB)) & (|RegWrite_MEM_WB)) & wb_valid&(de_valid|is_j_or_b);
assign Haz_ID_WB_rt = ((|RegWaddr_MEM_WB) & (|rt_read)) & ((&(rt_read^~RegWaddr_MEM_WB)) & (|RegWrite_MEM_WB)) & wb_valid&(de_valid|is_j_or_b);
assign RegRdata1_src = Haz_ID_EXE_rs ? 2'b01 :
(Haz_ID_MEM_rs ? 2'b10 :
(Haz_ID_WB_rs ? 2'b11 : 2'b00));
assign RegRdata2_src = Haz_ID_EXE_rt ? 2'b01 :
(Haz_ID_MEM_rt ? 2'b10 :
(Haz_ID_WB_rt ? 2'b11 : 2'b00));
assign ID_EXE_Stall = ( (Haz_ID_EXE_rt | Haz_ID_EXE_rs) & MemToReg_ID_EXE |
(Haz_ID_MEM_rt & ~Haz_ID_EXE_rt | Haz_ID_MEM_rs & ~Haz_ID_EXE_rs) & MemToReg_EXE_MEM |
(Haz_ID_WB_rt & ~Haz_ID_EXE_rt & ~Haz_ID_MEM_rt | Haz_ID_WB_rs & ~Haz_ID_EXE_rs & ~Haz_ID_MEM_rs) & MemToReg_MEM_WB |
DIV_Busy & DIV)
& (~ex_int_handle & ~rst);
assign PCWrite = ~ID_EXE_Stall;
assign IRWrite = ~(ID_EXE_Stall);
endmodule | module Bypass_Unit(
input wire clk,
input wire rst,
input wire is_rs_read,
input wire is_rt_read,
input wire MemToReg_ID_EXE,
input wire MemToReg_EXE_MEM,
input wire MemToReg_MEM_WB,
input wire [ 4:0] RegWaddr_EXE_MEM,
input wire [ 4:0] RegWaddr_MEM_WB,
input wire [ 4:0] RegWaddr_ID_EXE,
input wire [ 3:0] RegWrite_ID_EXE,
input wire [ 3:0] RegWrite_EXE_MEM,
input wire [ 3:0] RegWrite_MEM_WB,
input wire [ 4:0] rs_ID,
input wire [ 4:0] rt_ID,
input wire DIV_Busy,
input wire DIV,
input wire ex_int_handle,
output wire PCWrite,
output wire IRWrite,
output wire ID_EXE_Stall,
output wire [ 1:0] RegRdata1_src,
output wire [ 1:0] RegRdata2_src,
input is_j_or_b,
input de_valid,
input wb_valid,
input exe_valid,
input mem_valid
); |
wire [ 4:0] rs_read, rt_read;
assign rs_read = (is_rs_read) ? rs_ID : 5'd0;
assign rt_read = (is_rt_read) ? rt_ID : 5'd0;
wire Haz_ID_EXE_rs, Haz_ID_EXE_rt,
Haz_ID_MEM_rs, Haz_ID_MEM_rt,
Haz_ID_WB_rs, Haz_ID_WB_rt;
assign Haz_ID_EXE_rs = (((|RegWaddr_ID_EXE) & (|rs_read)) & ((&(rs_read^~RegWaddr_ID_EXE)) & (|RegWrite_ID_EXE))) & exe_valid&(de_valid|is_j_or_b) ;
assign Haz_ID_EXE_rt = (((|RegWaddr_ID_EXE) & (|rt_read)) & ((&(rt_read^~RegWaddr_ID_EXE)) & (|RegWrite_ID_EXE))) & exe_valid&(de_valid|is_j_or_b);
assign Haz_ID_MEM_rs = ((|RegWaddr_EXE_MEM) & (|rs_read)) & ((&(rs_read^~RegWaddr_EXE_MEM)) & (|RegWrite_EXE_MEM)) & mem_valid&(de_valid|is_j_or_b);
assign Haz_ID_MEM_rt = ((|RegWaddr_EXE_MEM) & (|rt_read)) & ((&(rt_read^~RegWaddr_EXE_MEM)) & (|RegWrite_EXE_MEM)) & mem_valid&(de_valid|is_j_or_b);
assign Haz_ID_WB_rs = ((|RegWaddr_MEM_WB) & (|rs_read)) & ((&(rs_read^~RegWaddr_MEM_WB)) & (|RegWrite_MEM_WB)) & wb_valid&(de_valid|is_j_or_b);
assign Haz_ID_WB_rt = ((|RegWaddr_MEM_WB) & (|rt_read)) & ((&(rt_read^~RegWaddr_MEM_WB)) & (|RegWrite_MEM_WB)) & wb_valid&(de_valid|is_j_or_b);
assign RegRdata1_src = Haz_ID_EXE_rs ? 2'b01 :
(Haz_ID_MEM_rs ? 2'b10 :
(Haz_ID_WB_rs ? 2'b11 : 2'b00));
assign RegRdata2_src = Haz_ID_EXE_rt ? 2'b01 :
(Haz_ID_MEM_rt ? 2'b10 :
(Haz_ID_WB_rt ? 2'b11 : 2'b00));
assign ID_EXE_Stall = ( (Haz_ID_EXE_rt | Haz_ID_EXE_rs) & MemToReg_ID_EXE |
(Haz_ID_MEM_rt & ~Haz_ID_EXE_rt | Haz_ID_MEM_rs & ~Haz_ID_EXE_rs) & MemToReg_EXE_MEM |
(Haz_ID_WB_rt & ~Haz_ID_EXE_rt & ~Haz_ID_MEM_rt | Haz_ID_WB_rs & ~Haz_ID_EXE_rs & ~Haz_ID_MEM_rs) & MemToReg_MEM_WB |
DIV_Busy & DIV)
& (~ex_int_handle & ~rst);
assign PCWrite = ~ID_EXE_Stall;
assign IRWrite = ~(ID_EXE_Stall);
endmodule | 0 |
4,890 | data/full_repos/permissive/112219256/Control_Unit.v | 112,219,256 | Control_Unit.v | v | 294 | 83 | [] | [] | [] | [(19, 293)] | null | data/verilator_xmls/21645610-a48e-42af-9c56-465df66ebd30.xml | null | 3,302 | module | module Control_Unit(
input wire rst,
input wire BranchCond,
input wire [4:0] rt,
input wire [4:0] rs,
input wire [5:0] op,
input wire [5:0] func,
output wire MemEn,
output wire JSrc,
output wire MemToReg,
output wire is_rs_read,
output wire is_rt_read,
output wire LB,
output wire LBU,
output wire LH,
output wire LHU,
output wire [1:0] PCSrc,
output wire [1:0] RegDst,
output wire [1:0] ALUSrcA,
output wire [1:0] ALUSrcB,
output wire [3:0] ALUop,
output wire [3:0] RegWrite,
output wire [3:0] MemWrite,
output wire [5:0] B_Type,
output wire [1:0] MULT,
output wire [1:0] DIV,
output wire [1:0] MFHL,
output wire [1:0] MTHL,
output wire [1:0] LW,
output wire [1:0] SW,
output wire SB,
output wire SH,
output wire trap,
output wire eret,
output wire cp0_Write,
output wire mfc0,
output wire is_signed,
output wire is_j_or_br,
output wire ri,
output wire sys,
output wire bp
);
wire inst_lw = (op == 6'b100011);
wire inst_sw = (op == 6'b101011);
wire inst_addiu = (op == 6'b001001);
wire inst_beq = (op == 6'b000100);
wire inst_bne = (op == 6'b000101);
wire inst_j = (op == 6'b000010);
wire inst_jal = (op == 6'b000011);
wire inst_slti = (op == 6'b001010);
wire inst_sltiu = (op == 6'b001011);
wire inst_lui = (op == 6'b001111);
wire inst_jr = (op == 6'b000000) && (func == 6'b001000);
wire inst_sll = (op == 6'b000000) && (func == 6'b000000);
wire inst_or = (op == 6'b000000) && (func == 6'b100101);
wire inst_slt = (op == 6'b000000) && (func == 6'b101010);
wire inst_addu = (op == 6'b000000) && (func == 6'b100001);
wire inst_addi = (op == 6'b001000);
wire inst_andi = (op == 6'b001100);
wire inst_ori = (op == 6'b001101);
wire inst_xori = (op == 6'b001110);
wire inst_add = (op == 6'b000000) && (func == 6'b100000);
wire inst_sub = (op == 6'b000000) && (func == 6'b100010);
wire inst_subu = (op == 6'b000000) && (func == 6'b100011);
wire inst_sltu = (op == 6'b000000) && (func == 6'b101011);
wire inst_and = (op == 6'b000000) && (func == 6'b100100);
wire inst_nor = (op == 6'b000000) && (func == 6'b100111);
wire inst_xor = (op == 6'b000000) && (func == 6'b100110);
wire inst_sllv = (op == 6'b000000) && (func == 6'b000100);
wire inst_sra = (op == 6'b000000) && (func == 6'b000011);
wire inst_srav = (op == 6'b000000) && (func == 6'b000111);
wire inst_srl = (op == 6'b000000) && (func == 6'b000010);
wire inst_srlv = (op == 6'b000000) && (func == 6'b000110);
wire inst_div = (op == 6'b000000) && (func == 6'b011010);
wire inst_divu = (op == 6'b000000) && (func == 6'b011011);
wire inst_mult = (op == 6'b000000) && (func == 6'b011000);
wire inst_multu = (op == 6'b000000) && (func == 6'b011001);
wire inst_mfhi = (op == 6'b000000) && (func == 6'b010000);
wire inst_mflo = (op == 6'b000000) && (func == 6'b010010);
wire inst_mthi = (op == 6'b000000) && (func == 6'b010001);
wire inst_mtlo = (op == 6'b000000) && (func == 6'b010011);
wire inst_jalr = (op == 6'b000000) && (func == 6'b001001);
wire inst_bgtz = (op == 6'b000111) && (rt == 5'd0);
wire inst_blez = (op == 6'b000110) && (rt == 5'd0);
wire inst_bltz = (op == 6'b000001) && (rt == 5'd0);
wire inst_bgez = (op == 6'b000001) && (rt == 5'b00001);
wire inst_bltzal = (op == 6'b000001) && (rt == 5'b10000);
wire inst_bgezal = (op == 6'b000001) && (rt == 5'b10001);
wire inst_lb = (op == 6'b100000);
wire inst_lbu = (op == 6'b100100);
wire inst_lh = (op == 6'b100001);
wire inst_lhu = (op == 6'b100101);
wire inst_lwl = (op == 6'b100010);
wire inst_lwr = (op == 6'b100110);
wire inst_sb = (op == 6'b101000);
wire inst_sh = (op == 6'b101001);
wire inst_swl = (op == 6'b101010);
wire inst_swr = (op == 6'b101110);
wire inst_mtc0 = (op == 6'b010000) && (rs == 5'b00100);
wire inst_mfc0 = (op == 6'b010000) && (rs == 5'b00000);
wire inst_syscall = (op == 6'b000000) && (func == 6'b001100);
wire inst_eret = (op == 6'b010000) && (func == 6'b011000);
wire inst_break = (op == 6'b000000) && (func == 6'b001101);
wire is_branch;
assign MemToReg = ~rst & (inst_lw | inst_lb | inst_lbu | inst_lh |
inst_lhu | inst_lwl | inst_lwr );
assign JSrc = ~rst & (inst_jr | inst_jalr );
assign MemEn = ~rst & (inst_sw | inst_lw | inst_lb | inst_lbu |
inst_lh | inst_lhu | inst_lwl | inst_lwr |
inst_sb | inst_sh | inst_swl | inst_swr );
assign is_rs_read = ~rst & ~(inst_j | inst_jal );
assign is_rt_read = ~rst & ~(inst_addi | inst_addiu | inst_slti | inst_sltiu |
inst_andi | inst_lui | inst_ori | inst_xori |
inst_j | inst_jal | inst_lw | inst_jalr |
inst_lb | inst_lbu | inst_lh | inst_lhu |
inst_lwl | inst_lwr );
assign is_branch = ~rst & (inst_bne | inst_blez | inst_bgez | inst_bgezal |
inst_beq | inst_bltz | inst_bgtz | inst_bltzal );
assign PCSrc[1] = ~rst & (is_branch & BranchCond );
assign PCSrc[0] = ~rst & (inst_jal | inst_j | inst_jr | inst_jalr );
assign ALUSrcA[1] = ~rst & (inst_sll | inst_sra | inst_srl );
assign ALUSrcA[0] = ~rst & (inst_jal | inst_jalr | inst_bltzal|
inst_bgezal );
assign ALUSrcB[1] = ~rst & (inst_jal | inst_ori | inst_xori |
inst_andi | inst_jalr | inst_bgezal |
inst_bltzal );
assign ALUSrcB[0] = ~rst & (inst_lw | inst_sw | inst_addiu |
inst_slti | inst_sltiu | inst_lui |
inst_addi | inst_andi | inst_ori |
inst_xori | inst_lb | inst_lbu |
inst_lh | inst_lhu | inst_sb |
inst_sh | inst_swl | inst_swr |
inst_lwl | inst_lwr );
assign RegDst[1] = ~rst & (inst_jal | inst_bgezal | inst_bltzal );
assign RegDst[0] = ~rst & (inst_addu | inst_or | inst_slt |
inst_sll | inst_add | inst_sub |
inst_subu | inst_sltu | inst_and |
inst_nor | inst_xor | inst_sllv |
inst_sra | inst_srav | inst_srl |
inst_srlv | inst_jalr | inst_mult |
inst_multu | inst_div | inst_divu |
inst_mfhi | inst_mflo );
assign RegWrite = {4{~rst & (inst_lw | inst_addiu | inst_slti |
inst_sltiu | inst_lui | inst_addu |
inst_or | inst_slt | inst_sll |
inst_jal | inst_addi | inst_andi |
inst_ori | inst_xori | inst_add |
inst_sub | inst_subu | inst_sltu |
inst_and | inst_nor | inst_xor |
inst_sllv | inst_sra | inst_srav |
inst_srl | inst_srlv | inst_jalr |
inst_bltzal | inst_bgezal | inst_mfhi |
inst_mflo | inst_lb | inst_lbu |
inst_lh | inst_lhu | inst_lwl |
inst_lwr | inst_mfc0 )}};
assign MemWrite[3] = ~rst & (inst_sw | inst_swl | inst_swr);
assign MemWrite[2] = ~rst & (inst_sw | inst_swl | inst_swr);
assign MemWrite[1] = ~rst & (inst_sw | inst_sh | inst_swl | inst_swr);
assign MemWrite[0] = ~rst & (inst_sw | inst_sb | inst_sh | inst_swl | inst_swr);
assign ALUop[3] = ~rst & (inst_xori | inst_nor | inst_xor |
inst_sra | inst_srav | inst_srl |
inst_srlv );
assign ALUop[2] = ~rst & (inst_slti | inst_slt | inst_sltiu |
inst_sll | inst_sub | inst_sltu |
inst_sllv | inst_srl | inst_srlv |
inst_subu );
assign ALUop[1] = ~rst & (inst_lw | inst_sw | inst_addiu |
inst_slti | inst_slt | inst_lui |
inst_jal | inst_addu | inst_addi |
inst_xori | inst_add | inst_sub |
inst_xor | inst_sra | inst_srav |
inst_subu | inst_jalr | inst_bgezal |
inst_bltzal | inst_lb | inst_lbu |
inst_lh | inst_lhu | inst_lwl |
inst_lwr | inst_sb | inst_sh |
inst_swl | inst_swr );
assign ALUop[0] = ~rst & (inst_slti | inst_slt | inst_or |
inst_lui | inst_sll | inst_ori |
inst_nor | inst_sllv | inst_sra |
inst_srav );
assign B_Type[5] = ~rst & (inst_bltz | inst_bltzal);
assign B_Type[4] = ~rst & (inst_blez);
assign B_Type[3] = ~rst & (inst_bgtz);
assign B_Type[2] = ~rst & (inst_bgez | inst_bgezal);
assign B_Type[1] = ~rst & (inst_beq );
assign B_Type[0] = ~rst & (inst_bne );
assign MULT[1] = ~rst & inst_multu;
assign MULT[0] = ~rst & inst_mult;
assign DIV[1] = ~rst & inst_divu;
assign DIV[0] = ~rst & inst_div;
assign MFHL[1] = ~rst & inst_mfhi;
assign MFHL[0] = ~rst & inst_mflo;
assign MTHL[1] = ~rst & inst_mthi;
assign MTHL[0] = ~rst & inst_mtlo;
assign LB = ~rst & inst_lb;
assign LBU = ~rst & inst_lbu;
assign LH = ~rst & inst_lh;
assign LHU = ~rst & inst_lhu;
assign LW[1] = ~rst & (inst_lwl | inst_lw);
assign LW[0] = ~rst & (inst_lwr | inst_lw);
assign SW[1] = ~rst & (inst_swl | inst_sw);
assign SW[0] = ~rst & (inst_swr | inst_sw);
assign SB = ~rst & inst_sb;
assign SH = ~rst & inst_sh;
assign mfc0 = ~rst & inst_mfc0;
assign eret = ~rst & inst_eret;
assign trap = ~rst & (inst_syscall | inst_break);
assign sys = ~rst & inst_syscall ;
assign bp = ~rst & inst_break ;
assign cp0_Write = ~rst & (inst_mtc0);
assign is_signed = ~rst & (inst_add | inst_sub | inst_addi );
wire in_inst_set = rst | inst_lw |
inst_sw | inst_addiu | inst_beq | inst_bne |
inst_sltiu | inst_lui | inst_jr | inst_sll |
inst_or | inst_slt | inst_addu | inst_addi |
inst_andi | inst_ori | inst_xori | inst_add |
inst_sub | inst_subu | inst_sltu | inst_and |
inst_nor | inst_xor | inst_sllv | inst_sra |
inst_srav | inst_srl | inst_srlv | inst_div |
inst_divu | inst_mult | inst_multu | inst_mfhi |
inst_mflo | inst_mthi | inst_mtlo | inst_jalr |
inst_bgtz | inst_blez | inst_bltz | inst_bgez |
inst_bltzal | inst_bgezal | inst_lb | inst_lbu |
inst_lh | inst_lhu | inst_lwl | inst_lwr |
inst_sb | inst_sh | inst_swl | inst_swr |
inst_mtc0 | inst_mfc0 | inst_syscall | inst_eret |
inst_j | inst_jal | inst_slti | inst_break ;
assign ri = ~in_inst_set;
assign is_j_or_br = ~rst & (inst_bne | inst_blez | inst_bgez | inst_bgezal |
inst_beq | inst_bltz | inst_bgtz | inst_bltzal |
inst_j | inst_jal | inst_jalr | inst_jr );
endmodule | module Control_Unit(
input wire rst,
input wire BranchCond,
input wire [4:0] rt,
input wire [4:0] rs,
input wire [5:0] op,
input wire [5:0] func,
output wire MemEn,
output wire JSrc,
output wire MemToReg,
output wire is_rs_read,
output wire is_rt_read,
output wire LB,
output wire LBU,
output wire LH,
output wire LHU,
output wire [1:0] PCSrc,
output wire [1:0] RegDst,
output wire [1:0] ALUSrcA,
output wire [1:0] ALUSrcB,
output wire [3:0] ALUop,
output wire [3:0] RegWrite,
output wire [3:0] MemWrite,
output wire [5:0] B_Type,
output wire [1:0] MULT,
output wire [1:0] DIV,
output wire [1:0] MFHL,
output wire [1:0] MTHL,
output wire [1:0] LW,
output wire [1:0] SW,
output wire SB,
output wire SH,
output wire trap,
output wire eret,
output wire cp0_Write,
output wire mfc0,
output wire is_signed,
output wire is_j_or_br,
output wire ri,
output wire sys,
output wire bp
); |
wire inst_lw = (op == 6'b100011);
wire inst_sw = (op == 6'b101011);
wire inst_addiu = (op == 6'b001001);
wire inst_beq = (op == 6'b000100);
wire inst_bne = (op == 6'b000101);
wire inst_j = (op == 6'b000010);
wire inst_jal = (op == 6'b000011);
wire inst_slti = (op == 6'b001010);
wire inst_sltiu = (op == 6'b001011);
wire inst_lui = (op == 6'b001111);
wire inst_jr = (op == 6'b000000) && (func == 6'b001000);
wire inst_sll = (op == 6'b000000) && (func == 6'b000000);
wire inst_or = (op == 6'b000000) && (func == 6'b100101);
wire inst_slt = (op == 6'b000000) && (func == 6'b101010);
wire inst_addu = (op == 6'b000000) && (func == 6'b100001);
wire inst_addi = (op == 6'b001000);
wire inst_andi = (op == 6'b001100);
wire inst_ori = (op == 6'b001101);
wire inst_xori = (op == 6'b001110);
wire inst_add = (op == 6'b000000) && (func == 6'b100000);
wire inst_sub = (op == 6'b000000) && (func == 6'b100010);
wire inst_subu = (op == 6'b000000) && (func == 6'b100011);
wire inst_sltu = (op == 6'b000000) && (func == 6'b101011);
wire inst_and = (op == 6'b000000) && (func == 6'b100100);
wire inst_nor = (op == 6'b000000) && (func == 6'b100111);
wire inst_xor = (op == 6'b000000) && (func == 6'b100110);
wire inst_sllv = (op == 6'b000000) && (func == 6'b000100);
wire inst_sra = (op == 6'b000000) && (func == 6'b000011);
wire inst_srav = (op == 6'b000000) && (func == 6'b000111);
wire inst_srl = (op == 6'b000000) && (func == 6'b000010);
wire inst_srlv = (op == 6'b000000) && (func == 6'b000110);
wire inst_div = (op == 6'b000000) && (func == 6'b011010);
wire inst_divu = (op == 6'b000000) && (func == 6'b011011);
wire inst_mult = (op == 6'b000000) && (func == 6'b011000);
wire inst_multu = (op == 6'b000000) && (func == 6'b011001);
wire inst_mfhi = (op == 6'b000000) && (func == 6'b010000);
wire inst_mflo = (op == 6'b000000) && (func == 6'b010010);
wire inst_mthi = (op == 6'b000000) && (func == 6'b010001);
wire inst_mtlo = (op == 6'b000000) && (func == 6'b010011);
wire inst_jalr = (op == 6'b000000) && (func == 6'b001001);
wire inst_bgtz = (op == 6'b000111) && (rt == 5'd0);
wire inst_blez = (op == 6'b000110) && (rt == 5'd0);
wire inst_bltz = (op == 6'b000001) && (rt == 5'd0);
wire inst_bgez = (op == 6'b000001) && (rt == 5'b00001);
wire inst_bltzal = (op == 6'b000001) && (rt == 5'b10000);
wire inst_bgezal = (op == 6'b000001) && (rt == 5'b10001);
wire inst_lb = (op == 6'b100000);
wire inst_lbu = (op == 6'b100100);
wire inst_lh = (op == 6'b100001);
wire inst_lhu = (op == 6'b100101);
wire inst_lwl = (op == 6'b100010);
wire inst_lwr = (op == 6'b100110);
wire inst_sb = (op == 6'b101000);
wire inst_sh = (op == 6'b101001);
wire inst_swl = (op == 6'b101010);
wire inst_swr = (op == 6'b101110);
wire inst_mtc0 = (op == 6'b010000) && (rs == 5'b00100);
wire inst_mfc0 = (op == 6'b010000) && (rs == 5'b00000);
wire inst_syscall = (op == 6'b000000) && (func == 6'b001100);
wire inst_eret = (op == 6'b010000) && (func == 6'b011000);
wire inst_break = (op == 6'b000000) && (func == 6'b001101);
wire is_branch;
assign MemToReg = ~rst & (inst_lw | inst_lb | inst_lbu | inst_lh |
inst_lhu | inst_lwl | inst_lwr );
assign JSrc = ~rst & (inst_jr | inst_jalr );
assign MemEn = ~rst & (inst_sw | inst_lw | inst_lb | inst_lbu |
inst_lh | inst_lhu | inst_lwl | inst_lwr |
inst_sb | inst_sh | inst_swl | inst_swr );
assign is_rs_read = ~rst & ~(inst_j | inst_jal );
assign is_rt_read = ~rst & ~(inst_addi | inst_addiu | inst_slti | inst_sltiu |
inst_andi | inst_lui | inst_ori | inst_xori |
inst_j | inst_jal | inst_lw | inst_jalr |
inst_lb | inst_lbu | inst_lh | inst_lhu |
inst_lwl | inst_lwr );
assign is_branch = ~rst & (inst_bne | inst_blez | inst_bgez | inst_bgezal |
inst_beq | inst_bltz | inst_bgtz | inst_bltzal );
assign PCSrc[1] = ~rst & (is_branch & BranchCond );
assign PCSrc[0] = ~rst & (inst_jal | inst_j | inst_jr | inst_jalr );
assign ALUSrcA[1] = ~rst & (inst_sll | inst_sra | inst_srl );
assign ALUSrcA[0] = ~rst & (inst_jal | inst_jalr | inst_bltzal|
inst_bgezal );
assign ALUSrcB[1] = ~rst & (inst_jal | inst_ori | inst_xori |
inst_andi | inst_jalr | inst_bgezal |
inst_bltzal );
assign ALUSrcB[0] = ~rst & (inst_lw | inst_sw | inst_addiu |
inst_slti | inst_sltiu | inst_lui |
inst_addi | inst_andi | inst_ori |
inst_xori | inst_lb | inst_lbu |
inst_lh | inst_lhu | inst_sb |
inst_sh | inst_swl | inst_swr |
inst_lwl | inst_lwr );
assign RegDst[1] = ~rst & (inst_jal | inst_bgezal | inst_bltzal );
assign RegDst[0] = ~rst & (inst_addu | inst_or | inst_slt |
inst_sll | inst_add | inst_sub |
inst_subu | inst_sltu | inst_and |
inst_nor | inst_xor | inst_sllv |
inst_sra | inst_srav | inst_srl |
inst_srlv | inst_jalr | inst_mult |
inst_multu | inst_div | inst_divu |
inst_mfhi | inst_mflo );
assign RegWrite = {4{~rst & (inst_lw | inst_addiu | inst_slti |
inst_sltiu | inst_lui | inst_addu |
inst_or | inst_slt | inst_sll |
inst_jal | inst_addi | inst_andi |
inst_ori | inst_xori | inst_add |
inst_sub | inst_subu | inst_sltu |
inst_and | inst_nor | inst_xor |
inst_sllv | inst_sra | inst_srav |
inst_srl | inst_srlv | inst_jalr |
inst_bltzal | inst_bgezal | inst_mfhi |
inst_mflo | inst_lb | inst_lbu |
inst_lh | inst_lhu | inst_lwl |
inst_lwr | inst_mfc0 )}};
assign MemWrite[3] = ~rst & (inst_sw | inst_swl | inst_swr);
assign MemWrite[2] = ~rst & (inst_sw | inst_swl | inst_swr);
assign MemWrite[1] = ~rst & (inst_sw | inst_sh | inst_swl | inst_swr);
assign MemWrite[0] = ~rst & (inst_sw | inst_sb | inst_sh | inst_swl | inst_swr);
assign ALUop[3] = ~rst & (inst_xori | inst_nor | inst_xor |
inst_sra | inst_srav | inst_srl |
inst_srlv );
assign ALUop[2] = ~rst & (inst_slti | inst_slt | inst_sltiu |
inst_sll | inst_sub | inst_sltu |
inst_sllv | inst_srl | inst_srlv |
inst_subu );
assign ALUop[1] = ~rst & (inst_lw | inst_sw | inst_addiu |
inst_slti | inst_slt | inst_lui |
inst_jal | inst_addu | inst_addi |
inst_xori | inst_add | inst_sub |
inst_xor | inst_sra | inst_srav |
inst_subu | inst_jalr | inst_bgezal |
inst_bltzal | inst_lb | inst_lbu |
inst_lh | inst_lhu | inst_lwl |
inst_lwr | inst_sb | inst_sh |
inst_swl | inst_swr );
assign ALUop[0] = ~rst & (inst_slti | inst_slt | inst_or |
inst_lui | inst_sll | inst_ori |
inst_nor | inst_sllv | inst_sra |
inst_srav );
assign B_Type[5] = ~rst & (inst_bltz | inst_bltzal);
assign B_Type[4] = ~rst & (inst_blez);
assign B_Type[3] = ~rst & (inst_bgtz);
assign B_Type[2] = ~rst & (inst_bgez | inst_bgezal);
assign B_Type[1] = ~rst & (inst_beq );
assign B_Type[0] = ~rst & (inst_bne );
assign MULT[1] = ~rst & inst_multu;
assign MULT[0] = ~rst & inst_mult;
assign DIV[1] = ~rst & inst_divu;
assign DIV[0] = ~rst & inst_div;
assign MFHL[1] = ~rst & inst_mfhi;
assign MFHL[0] = ~rst & inst_mflo;
assign MTHL[1] = ~rst & inst_mthi;
assign MTHL[0] = ~rst & inst_mtlo;
assign LB = ~rst & inst_lb;
assign LBU = ~rst & inst_lbu;
assign LH = ~rst & inst_lh;
assign LHU = ~rst & inst_lhu;
assign LW[1] = ~rst & (inst_lwl | inst_lw);
assign LW[0] = ~rst & (inst_lwr | inst_lw);
assign SW[1] = ~rst & (inst_swl | inst_sw);
assign SW[0] = ~rst & (inst_swr | inst_sw);
assign SB = ~rst & inst_sb;
assign SH = ~rst & inst_sh;
assign mfc0 = ~rst & inst_mfc0;
assign eret = ~rst & inst_eret;
assign trap = ~rst & (inst_syscall | inst_break);
assign sys = ~rst & inst_syscall ;
assign bp = ~rst & inst_break ;
assign cp0_Write = ~rst & (inst_mtc0);
assign is_signed = ~rst & (inst_add | inst_sub | inst_addi );
wire in_inst_set = rst | inst_lw |
inst_sw | inst_addiu | inst_beq | inst_bne |
inst_sltiu | inst_lui | inst_jr | inst_sll |
inst_or | inst_slt | inst_addu | inst_addi |
inst_andi | inst_ori | inst_xori | inst_add |
inst_sub | inst_subu | inst_sltu | inst_and |
inst_nor | inst_xor | inst_sllv | inst_sra |
inst_srav | inst_srl | inst_srlv | inst_div |
inst_divu | inst_mult | inst_multu | inst_mfhi |
inst_mflo | inst_mthi | inst_mtlo | inst_jalr |
inst_bgtz | inst_blez | inst_bltz | inst_bgez |
inst_bltzal | inst_bgezal | inst_lb | inst_lbu |
inst_lh | inst_lhu | inst_lwl | inst_lwr |
inst_sb | inst_sh | inst_swl | inst_swr |
inst_mtc0 | inst_mfc0 | inst_syscall | inst_eret |
inst_j | inst_jal | inst_slti | inst_break ;
assign ri = ~in_inst_set;
assign is_j_or_br = ~rst & (inst_bne | inst_blez | inst_bgez | inst_bgezal |
inst_beq | inst_bltz | inst_bgtz | inst_bltzal |
inst_j | inst_jal | inst_jalr | inst_jr );
endmodule | 0 |
4,891 | data/full_repos/permissive/112219256/cp0reg.v | 112,219,256 | cp0reg.v | v | 302 | 88 | [] | [] | [] | null | line:302: before: "/" | null | 1: b"%Error: data/full_repos/permissive/112219256/cp0reg.v:21: syntax error, unexpected int, expecting IDENTIFIER or '[' or do or final\n input [ 5:0] int,\n ^~~\n%Error: data/full_repos/permissive/112219256/cp0reg.v:39: syntax error, unexpected assign\n assign badvaddr_value = badvaddr;\n ^~~~~~\n%Error: data/full_repos/permissive/112219256/cp0reg.v:44: syntax error, unexpected assign\n assign count_value = count;\n ^~~~~~\n%Error: data/full_repos/permissive/112219256/cp0reg.v:48: syntax error, unexpected assign\n assign compare_value = compare;\n ^~~~~~\n%Error: data/full_repos/permissive/112219256/cp0reg.v:79: syntax error, unexpected assign\n assign status_value = {status_CU3, status_CU2, status_CU1, status_CU0,\n ^~~~~~\n%Error: data/full_repos/permissive/112219256/cp0reg.v:107: syntax error, unexpected assign\n assign cause_value = {cause_BD, cause_TI, 14'd0, cause_IP7, cause_IP6, \n ^~~~~~\n%Error: data/full_repos/permissive/112219256/cp0reg.v:120: syntax error, unexpected assign\n assign epc_value = epc;\n ^~~~~~\n%Error: data/full_repos/permissive/112219256/cp0reg.v:135: syntax error, unexpected assign\n assign ex_int_handle = ~status_EXL & (int_pending | exc_pending);\n ^~~~~~\n%Error: data/full_repos/permissive/112219256/cp0reg.v:142: syntax error, unexpected always\n always @(posedge clk) begin\n ^~~~~~\n%Error: Exiting due to 9 error(s)\n" | 3,303 | module | module cp0reg(
input clk,
input rst,
input wen,
input eret,
input Exc_BD,
input [ 5:0] int,
input [ 6:0] Exc_Vec,
input [`ADDR_WIDTH - 1:0] waddr,
input [`ADDR_WIDTH - 1:0] raddr,
input [`DATA_WIDTH - 1:0] wdata,
input [`DATA_WIDTH - 1:0] epc_in,
input [`DATA_WIDTH - 1:0] Exc_BadVaddr,
output [`DATA_WIDTH - 1:0] rdata,
output [`DATA_WIDTH - 1:0] epc_value,
output ex_int_handle,
output eret_handle,
input exe_ready_go,
input exe_refresh
);
reg [31:0] badvaddr;
wire [31:0] badvaddr_value;
assign badvaddr_value = badvaddr;
reg cycle;
reg [31:0] count;
wire [31:0] count_value;
assign count_value = count;
reg [31:0] compare;
wire [31:0] compare_value;
assign compare_value = compare;
wire count_cmp_eq = (count_value == compare_value) ? 1'b1 : 1'b0;
wire status_CU3 = 1'b0;
wire status_CU2 = 1'b0;
wire status_CU1 = 1'b0;
wire status_CU0 = 1'b0;
wire status_RP = 1'b0;
wire status_FR = 1'b0;
wire status_RE = 1'b0;
wire status_MX = 1'b0;
wire status_BEV = 1'b1;
wire status_TS = 1'b0;
wire status_SR = 1'b0;
wire status_NMI = 1'b0;
wire status_ASE = 1'b0;
reg status_IM7;
reg status_IM6;
reg status_IM5;
reg status_IM4;
reg status_IM3;
reg status_IM2;
reg status_IM1;
reg status_IM0;
wire [ 1:0] status_KSU = 2'b00;
wire status_ERL = 1'b0;
reg status_EXL;
reg status_IE;
wire [31:0] status_value;
assign status_value = {status_CU3, status_CU2, status_CU1, status_CU0,
status_RP, status_FR, status_RE, status_MX,
1'b0, status_BEV, status_TS, status_SR, status_NMI, status_ASE,
2'd0, status_IM7, status_IM6, status_IM5, status_IM4, status_IM3,
status_IM2, status_IM1, status_IM0, 3'd0, status_KSU,
status_ERL, status_EXL, status_IE };
reg cause_BD;
reg cause_TI;
reg cause_IP7;
reg cause_IP6;
reg cause_IP5;
reg cause_IP4;
reg cause_IP3;
reg cause_IP2;
reg cause_IP1;
reg cause_IP0;
reg [4:0] cause_ExcCode;
wire [31:0] cause_value;
wire [ 4:0]ExcCode;
assign cause_value = {cause_BD, cause_TI, 14'd0, cause_IP7, cause_IP6,
cause_IP5, cause_IP4, cause_IP3, cause_IP2,
cause_IP1, cause_IP0, 1'b0, cause_ExcCode, 2'd0};
assign ExcCode = (Exc_Vec[6]) ? 5'h4 :
(Exc_Vec[5]) ? 5'ha :
(Exc_Vec[4]) ? 5'hc :
(Exc_Vec[3]) ? 5'h8 :
(Exc_Vec[2]) ? 5'h9 :
(Exc_Vec[1]) ? 5'h4 :
(Exc_Vec[0]) ? 5'h5 : 5'hf;
reg [31:0] epc;
assign epc_value = epc;
wire [7:0] int_vec;
wire int_pending = |int_vec & status_IE;
wire exc_pending = |Exc_Vec;
wire int_handle;
wire ex_handle;
assign ex_int_handle = ~status_EXL & (int_pending | exc_pending);
assign int_handle = ~status_EXL & int_pending;
assign ex_handle = ~status_EXL & exc_pending;
reg wait_for_epc;
reg wait_for_epc_r;
always @(posedge clk) begin
if (~status_EXL) begin
if (|int_vec && status_IE) begin
cause_ExcCode <= 5'd0;
end
else if (|Exc_Vec) begin
cause_ExcCode <= ExcCode;
cause_BD <= Exc_BD;
if (Exc_Vec[6] | Exc_Vec[1] | Exc_Vec[0])
badvaddr <= Exc_BadVaddr;
end
end
if(rst) begin
badvaddr <= 32'd0;
end
if(rst) begin
cycle <= 1'b0;
count <= 32'd0;
end
else if(wen && waddr==5'd9) begin
count <= wdata;
cycle <= 1'b0;
end
else begin
cycle <= ~cycle;
if(cycle)
count <= count + 1'b1;
end
if (rst)
compare <= 32'h0;
else if (wen && waddr == 5'd11)
compare <= wdata[31:0];
if (rst) begin
status_IM7 <= 1'b0;
status_IM6 <= 1'b0;
status_IM5 <= 1'b0;
status_IM4 <= 1'b0;
status_IM3 <= 1'b0;
status_IM2 <= 1'b0;
status_IM1 <= 1'b0;
status_IM0 <= 1'b0;
status_EXL <= 1'b0;
status_IE <= 1'b0;
end
else begin
if (eret && exe_ready_go)
status_EXL <= 1'b0;
else if ((exc_pending || int_pending) && exe_ready_go)
status_EXL <= 1'b1;
else if (wen && waddr == 5'd12)
status_EXL <= wdata[1];
if (wen && waddr == 5'd12) begin
status_IM7 <= wdata[ 15];
status_IM6 <= wdata[ 14];
status_IM5 <= wdata[ 13];
status_IM4 <= wdata[ 12];
status_IM3 <= wdata[ 11];
status_IM2 <= wdata[ 10];
status_IM1 <= wdata[ 9];
status_IM0 <= wdata[ 8];
status_IE <= wdata[ 0];
end
end
if (rst) begin
cause_TI <= 1'b0;
end
else if (wen && waddr==5'd11) begin
cause_TI <= 1'b0;
end
else if (count_cmp_eq) begin
cause_TI <= 1'b1;
end
if (rst) begin
cause_BD <= 1'b0;
cause_IP7 <= 1'b0;
cause_IP6 <= 1'b0;
cause_IP5 <= 1'b0;
cause_IP4 <= 1'b0;
cause_IP3 <= 1'b0;
cause_IP2 <= 1'b0;
cause_IP1 <= 1'b0;
cause_IP0 <= 1'b0;
cause_ExcCode <= 5'h1f;
end
else begin
if (wen && waddr == 5'd13) begin
cause_IP1 <= wdata[ 9];
cause_IP0 <= wdata[ 8];
end
cause_IP7 <= int[5] | cause_TI;
cause_IP6 <= int[4];
cause_IP5 <= int[3];
cause_IP4 <= int[2];
cause_IP3 <= int[1];
cause_IP2 <= int[0];
end
if (rst) begin
epc <= 32'd0;
end
else begin
if (wait_for_epc_neg || ex_handle&&exe_ready_go) begin
epc <= epc_in;
end
else if (wen && waddr == 5'd14)
epc <= wdata[31:0];
end
end
always @ (posedge clk) begin
if (rst) begin
wait_for_epc <= 1'b0;
end
else begin
if (int_handle)
wait_for_epc <= 1'b1;
else if (wait_for_epc&&exe_refresh)
wait_for_epc <= 1'b0;
end
end
always @ (posedge clk) begin
if (rst) begin
wait_for_epc_r <= 1'b0;
end
else begin
wait_for_epc_r <= wait_for_epc;
end
end
assign wait_for_epc_neg = ~wait_for_epc & wait_for_epc_r;
assign rdata = {32{&(~(raddr ^ 5'b01000))}} & badvaddr_value |
{32{&(~(raddr ^ 5'b01001))}} & count_value |
{32{&(~(raddr ^ 5'b01011))}} & compare_value |
{32{&(~(raddr ^ 5'b01100))}} & status_value |
{32{&(~(raddr ^ 5'b01101))}} & cause_value |
{32{&(~(raddr ^ 5'b01110))}} & epc_value ;
assign int_vec = {(int[5] | cause_TI) & status_IM7,
int[4] & status_IM6,
int[3] & status_IM5,
int[2] & status_IM4,
int[1] & status_IM3,
int[0] & status_IM2,
cause_IP1 & status_IM1,
cause_IP0 & status_IM0};
assign eret_handle = eret;
endmodule | module cp0reg(
input clk,
input rst,
input wen,
input eret,
input Exc_BD,
input [ 5:0] int,
input [ 6:0] Exc_Vec,
input [`ADDR_WIDTH - 1:0] waddr,
input [`ADDR_WIDTH - 1:0] raddr,
input [`DATA_WIDTH - 1:0] wdata,
input [`DATA_WIDTH - 1:0] epc_in,
input [`DATA_WIDTH - 1:0] Exc_BadVaddr,
output [`DATA_WIDTH - 1:0] rdata,
output [`DATA_WIDTH - 1:0] epc_value,
output ex_int_handle,
output eret_handle,
input exe_ready_go,
input exe_refresh
); |
reg [31:0] badvaddr;
wire [31:0] badvaddr_value;
assign badvaddr_value = badvaddr;
reg cycle;
reg [31:0] count;
wire [31:0] count_value;
assign count_value = count;
reg [31:0] compare;
wire [31:0] compare_value;
assign compare_value = compare;
wire count_cmp_eq = (count_value == compare_value) ? 1'b1 : 1'b0;
wire status_CU3 = 1'b0;
wire status_CU2 = 1'b0;
wire status_CU1 = 1'b0;
wire status_CU0 = 1'b0;
wire status_RP = 1'b0;
wire status_FR = 1'b0;
wire status_RE = 1'b0;
wire status_MX = 1'b0;
wire status_BEV = 1'b1;
wire status_TS = 1'b0;
wire status_SR = 1'b0;
wire status_NMI = 1'b0;
wire status_ASE = 1'b0;
reg status_IM7;
reg status_IM6;
reg status_IM5;
reg status_IM4;
reg status_IM3;
reg status_IM2;
reg status_IM1;
reg status_IM0;
wire [ 1:0] status_KSU = 2'b00;
wire status_ERL = 1'b0;
reg status_EXL;
reg status_IE;
wire [31:0] status_value;
assign status_value = {status_CU3, status_CU2, status_CU1, status_CU0,
status_RP, status_FR, status_RE, status_MX,
1'b0, status_BEV, status_TS, status_SR, status_NMI, status_ASE,
2'd0, status_IM7, status_IM6, status_IM5, status_IM4, status_IM3,
status_IM2, status_IM1, status_IM0, 3'd0, status_KSU,
status_ERL, status_EXL, status_IE };
reg cause_BD;
reg cause_TI;
reg cause_IP7;
reg cause_IP6;
reg cause_IP5;
reg cause_IP4;
reg cause_IP3;
reg cause_IP2;
reg cause_IP1;
reg cause_IP0;
reg [4:0] cause_ExcCode;
wire [31:0] cause_value;
wire [ 4:0]ExcCode;
assign cause_value = {cause_BD, cause_TI, 14'd0, cause_IP7, cause_IP6,
cause_IP5, cause_IP4, cause_IP3, cause_IP2,
cause_IP1, cause_IP0, 1'b0, cause_ExcCode, 2'd0};
assign ExcCode = (Exc_Vec[6]) ? 5'h4 :
(Exc_Vec[5]) ? 5'ha :
(Exc_Vec[4]) ? 5'hc :
(Exc_Vec[3]) ? 5'h8 :
(Exc_Vec[2]) ? 5'h9 :
(Exc_Vec[1]) ? 5'h4 :
(Exc_Vec[0]) ? 5'h5 : 5'hf;
reg [31:0] epc;
assign epc_value = epc;
wire [7:0] int_vec;
wire int_pending = |int_vec & status_IE;
wire exc_pending = |Exc_Vec;
wire int_handle;
wire ex_handle;
assign ex_int_handle = ~status_EXL & (int_pending | exc_pending);
assign int_handle = ~status_EXL & int_pending;
assign ex_handle = ~status_EXL & exc_pending;
reg wait_for_epc;
reg wait_for_epc_r;
always @(posedge clk) begin
if (~status_EXL) begin
if (|int_vec && status_IE) begin
cause_ExcCode <= 5'd0;
end
else if (|Exc_Vec) begin
cause_ExcCode <= ExcCode;
cause_BD <= Exc_BD;
if (Exc_Vec[6] | Exc_Vec[1] | Exc_Vec[0])
badvaddr <= Exc_BadVaddr;
end
end
if(rst) begin
badvaddr <= 32'd0;
end
if(rst) begin
cycle <= 1'b0;
count <= 32'd0;
end
else if(wen && waddr==5'd9) begin
count <= wdata;
cycle <= 1'b0;
end
else begin
cycle <= ~cycle;
if(cycle)
count <= count + 1'b1;
end
if (rst)
compare <= 32'h0;
else if (wen && waddr == 5'd11)
compare <= wdata[31:0];
if (rst) begin
status_IM7 <= 1'b0;
status_IM6 <= 1'b0;
status_IM5 <= 1'b0;
status_IM4 <= 1'b0;
status_IM3 <= 1'b0;
status_IM2 <= 1'b0;
status_IM1 <= 1'b0;
status_IM0 <= 1'b0;
status_EXL <= 1'b0;
status_IE <= 1'b0;
end
else begin
if (eret && exe_ready_go)
status_EXL <= 1'b0;
else if ((exc_pending || int_pending) && exe_ready_go)
status_EXL <= 1'b1;
else if (wen && waddr == 5'd12)
status_EXL <= wdata[1];
if (wen && waddr == 5'd12) begin
status_IM7 <= wdata[ 15];
status_IM6 <= wdata[ 14];
status_IM5 <= wdata[ 13];
status_IM4 <= wdata[ 12];
status_IM3 <= wdata[ 11];
status_IM2 <= wdata[ 10];
status_IM1 <= wdata[ 9];
status_IM0 <= wdata[ 8];
status_IE <= wdata[ 0];
end
end
if (rst) begin
cause_TI <= 1'b0;
end
else if (wen && waddr==5'd11) begin
cause_TI <= 1'b0;
end
else if (count_cmp_eq) begin
cause_TI <= 1'b1;
end
if (rst) begin
cause_BD <= 1'b0;
cause_IP7 <= 1'b0;
cause_IP6 <= 1'b0;
cause_IP5 <= 1'b0;
cause_IP4 <= 1'b0;
cause_IP3 <= 1'b0;
cause_IP2 <= 1'b0;
cause_IP1 <= 1'b0;
cause_IP0 <= 1'b0;
cause_ExcCode <= 5'h1f;
end
else begin
if (wen && waddr == 5'd13) begin
cause_IP1 <= wdata[ 9];
cause_IP0 <= wdata[ 8];
end
cause_IP7 <= int[5] | cause_TI;
cause_IP6 <= int[4];
cause_IP5 <= int[3];
cause_IP4 <= int[2];
cause_IP3 <= int[1];
cause_IP2 <= int[0];
end
if (rst) begin
epc <= 32'd0;
end
else begin
if (wait_for_epc_neg || ex_handle&&exe_ready_go) begin
epc <= epc_in;
end
else if (wen && waddr == 5'd14)
epc <= wdata[31:0];
end
end
always @ (posedge clk) begin
if (rst) begin
wait_for_epc <= 1'b0;
end
else begin
if (int_handle)
wait_for_epc <= 1'b1;
else if (wait_for_epc&&exe_refresh)
wait_for_epc <= 1'b0;
end
end
always @ (posedge clk) begin
if (rst) begin
wait_for_epc_r <= 1'b0;
end
else begin
wait_for_epc_r <= wait_for_epc;
end
end
assign wait_for_epc_neg = ~wait_for_epc & wait_for_epc_r;
assign rdata = {32{&(~(raddr ^ 5'b01000))}} & badvaddr_value |
{32{&(~(raddr ^ 5'b01001))}} & count_value |
{32{&(~(raddr ^ 5'b01011))}} & compare_value |
{32{&(~(raddr ^ 5'b01100))}} & status_value |
{32{&(~(raddr ^ 5'b01101))}} & cause_value |
{32{&(~(raddr ^ 5'b01110))}} & epc_value ;
assign int_vec = {(int[5] | cause_TI) & status_IM7,
int[4] & status_IM6,
int[3] & status_IM5,
int[2] & status_IM4,
int[1] & status_IM3,
int[0] & status_IM2,
cause_IP1 & status_IM1,
cause_IP0 & status_IM0};
assign eret_handle = eret;
endmodule | 0 |
4,892 | data/full_repos/permissive/112219256/cpu_axi_interface.v | 112,219,256 | cpu_axi_interface.v | v | 281 | 158 | [] | [] | [] | [(1, 279)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/112219256/cpu_axi_interface.v:123: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance cpu_axi_interface\n do_arsize <= !resetn ? 3\'d0 :\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112219256/cpu_axi_interface.v:124: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_size\' generates 2 bits.\n : ... In instance cpu_axi_interface\n r_addr_rcv_pos ? (do_req_raddr_or ? data_size : inst_size) : do_arsize;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/cpu_axi_interface.v:124: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'inst_size\' generates 2 bits.\n : ... In instance cpu_axi_interface\n r_addr_rcv_pos ? (do_req_raddr_or ? data_size : inst_size) : do_arsize;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/cpu_axi_interface.v:217: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'do_arsize\' generates 32 bits.\n : ... In instance cpu_axi_interface\n assign arsize = do_arsize;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/cpu_axi_interface.v:229: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s VARREF \'do_dsize_r\' generates 2 bits.\n : ... In instance cpu_axi_interface\n assign awsize = do_req_waddr ? do_dsize_r : 3\'hx;\n ^\n%Error: Exiting due to 5 warning(s)\n' | 3,304 | module | module cpu_axi_interface(
input clk,
input resetn,
input inst_req,
input inst_wr,
input [ 1:0] inst_size,
input [31:0] inst_addr,
input [31:0] inst_wdata,
output [31:0] inst_rdata,
output inst_addr_ok,
output inst_data_ok,
input data_req,
input data_wr,
input [ 1:0] data_size,
input [31:0] data_addr,
input [31:0] data_wdata,
output [31:0] data_rdata,
output data_addr_ok,
output data_data_ok,
output [ 3:0] arid,
output [31:0] araddr,
output [ 7:0] arlen,
output [ 2:0] arsize,
output [ 1:0] arburst,
output [ 1:0] arlock,
output [ 3:0] arcache,
output [ 2:0] arprot,
output reg arvalid,
input arready,
input [ 3:0] rid,
input [31:0] rdata,
input [ 1:0] rresp,
input rlast,
input rvalid,
output reg rready,
output [ 3:0] awid,
output [31:0] awaddr,
output [ 7:0] awlen,
output [ 2:0] awsize,
output [ 1:0] awburst,
output [ 1:0] awlock,
output [ 3:0] awcache,
output [ 2:0] awprot,
output reg awvalid,
input awready,
output [ 3:0] wid,
output [31:0] wdata,
output [ 3:0] wstrb,
output wlast,
output reg wvalid,
input wready,
input [ 3:0] bid,
input [ 1:0] bresp,
input bvalid,
output reg bready
);
reg do_req_raddr_or;
reg [ 3:0] do_arid;
reg [31:0] do_araddr;
reg [31:0] do_arsize;
reg r_addr_rcv;
reg r_addr_rcv_r;
wire r_data_back;
wire r_addr_rcv_pos;
reg do_req_waddr;
reg do_req_waddr_r;
wire do_req_waddr_pos;
reg do_req_wdata;
reg do_req_wdata_r;
wire do_req_wdata_pos;
reg w_addr_rcv;
reg w_data_rcv;
wire w_data_back;
reg [31:0] do_wdata_r;
reg [32:0] do_waddr_r;
reg [ 1:0] do_dsize_r;
reg [ 1:0] data_in_ready;
reg [ 1:0] data_in_ready_r;
wire data_in_ready_pos;
reg w_addr_rcv_r;
reg w_data_rcv_r;
wire w_addr_rcv_pos;
wire w_data_rcv_pos;
assign inst_addr_ok = arvalid&&arready && !do_req_raddr_or;
assign data_addr_ok = arvalid&&arready && do_req_raddr_or ||
data_in_ready==2'b01 && wvalid&&wready && do_waddr_r[32] ||
data_in_ready==2'b10 && awvalid&&awready && do_waddr_r[32] ;
always @ (posedge clk) begin
do_req_raddr_or <= !resetn ? 1'b0 :
arready&&arvalid ? (data_req&&!data_wr) : do_req_raddr_or;
do_arid <= !resetn ? 4'd0 :
r_addr_rcv_pos ? (do_req_raddr_or ? 4'd1 : 4'd0) : do_arid;
do_araddr <= !resetn ? 32'd0 :
r_addr_rcv_pos ? (do_req_raddr_or ? data_addr : inst_addr) : do_araddr;
do_arsize <= !resetn ? 3'd0 :
r_addr_rcv_pos ? (do_req_raddr_or ? data_size : inst_size) : do_arsize;
arvalid <= !resetn ? 1'b0 :
r_addr_rcv_pos&&(inst_req||data_req&&!data_wr) ? 1'b1 :
arready ? 1'b0 : 1'b1;
end
always @(posedge clk) begin
r_addr_rcv <= !resetn ? 1'b0 :
arvalid&&arready ? 1'b1 :
r_data_back ? 1'b0 : r_addr_rcv;
rready <= !resetn ? 1'b0 :
r_addr_rcv_pos ? 1'b1 :
r_data_back ? 1'b0 : rready;
end
assign r_data_back = r_addr_rcv && (rvalid && rready);
always @ (posedge clk) begin
do_req_waddr <= !resetn ? 1'b0 :
data_req&&data_wr && !do_req_waddr ? 1'b1 :
w_data_back ? 1'b0 : do_req_waddr;
do_req_wdata <= !resetn ? 1'b0 :
data_req&&data_wr && !do_req_wdata ? 1'b1 :
w_data_back ? 1'b0 : do_req_wdata;
do_waddr_r <= !resetn ? 33'd0 :
data_in_ready_pos ? {1'b1,data_addr} : do_waddr_r;
do_wdata_r <= data_in_ready_pos ? data_wdata : do_wdata_r;
do_dsize_r <= data_in_ready_pos ? data_size : do_dsize_r;
data_in_ready <= !resetn ? 2'b00 :
w_addr_rcv_pos&&w_data_rcv_pos ? 2'b11 :
w_addr_rcv_pos ? data_in_ready + 2'b01 :
w_data_rcv_pos ? data_in_ready + 2'b10 :
w_data_back ? 2'b00 : data_in_ready;
awvalid <= !resetn ? 1'b0 :
do_req_waddr_pos ? 1'b1 :
awready ? 1'b0 : awvalid;
wvalid <= !resetn ? 1'b0 :
do_req_wdata_pos ? 1'b1 :
wready ? 1'b0 : wvalid;
end
always @ (posedge clk) begin
w_addr_rcv <= !resetn ? 1'b0 :
awvalid&&awready ? 1'b1 :
w_data_back ? 1'b0 : w_addr_rcv;
w_data_rcv <= !resetn ? 1'b0 :
wvalid&&wready ? 1'b1 :
w_data_back ? 1'b0 : w_data_rcv;
bready <= !resetn ? 1'b0 :
w_addr_rcv&&w_data_rcv ? 1'b1 :
w_data_back ? 1'b0 : bready;
end
assign w_data_back = (w_addr_rcv&&w_data_rcv) && (bvalid && bready);
assign arid = do_arid;
assign araddr = do_araddr;
assign arsize = do_arsize;
assign arlen = 8'd0;
assign arburst = 2'b01;
assign arlock = 2'd0;
assign arcache = 4'd0;
assign arprot = 3'd0;
assign awaddr = do_req_waddr ? do_waddr_r[31:0] : 32'hxxxxxxxx;
assign awsize = do_req_waddr ? do_dsize_r : 3'hx;
assign awid = 4'd0;
assign awlen = 8'd0;
assign awburst = 2'b01;
assign awlock = 2'd0;
assign awcache = 4'd0;
assign awprot = 3'd0;
assign wdata = do_wdata_r;
assign wstrb = do_dsize_r==2'd0 ? 4'b0001<<do_waddr_r[1:0] :
do_dsize_r==2'd1 ? 4'b0011<<do_waddr_r[1:0] : 4'b1111;
assign wid = 4'd0;
assign wlast = 1'b1;
assign inst_data_ok = r_data_back && rid==4'd0;
assign data_data_ok = (r_data_back && rid==4'd1) || w_data_back;
assign inst_rdata = rid==4'd0 ? rdata : 32'hxxxxxxxx;
assign data_rdata = rid==4'd1 ? rdata : 32'hxxxxxxxx;
always @ (posedge clk) begin
r_addr_rcv_r <= !resetn ? 1'b0 : r_addr_rcv;
data_in_ready_r <= !resetn ? 2'd0 : data_in_ready;
w_addr_rcv_r <= !resetn ? 1'b0 : w_addr_rcv;
w_data_rcv_r <= !resetn ? 1'b0 : w_data_rcv;
do_req_waddr_r <= !resetn ? 1'b0 : do_req_waddr;
do_req_wdata_r <= !resetn ? 1'b0 : do_req_wdata;
end
assign r_addr_rcv_pos = r_addr_rcv & ~r_addr_rcv_r;
assign data_in_ready_pos = data_in_ready==2'd3 & data_in_ready_r!=2'd3;
assign w_addr_rcv_pos = w_addr_rcv & ~w_addr_rcv_r;
assign w_data_rcv_pos = w_data_rcv & ~w_data_rcv_r;
assign do_req_waddr_pos = do_req_waddr & ~do_req_waddr_r;
assign do_req_wdata_pos = do_req_wdata & ~do_req_wdata_r;
integer wr_cnt;
always @ (posedge clk) begin
if(!resetn) wr_cnt <= 'd0;
else if(bvalid&&bready)
wr_cnt <= wr_cnt + 'd1;
end
endmodule | module cpu_axi_interface(
input clk,
input resetn,
input inst_req,
input inst_wr,
input [ 1:0] inst_size,
input [31:0] inst_addr,
input [31:0] inst_wdata,
output [31:0] inst_rdata,
output inst_addr_ok,
output inst_data_ok,
input data_req,
input data_wr,
input [ 1:0] data_size,
input [31:0] data_addr,
input [31:0] data_wdata,
output [31:0] data_rdata,
output data_addr_ok,
output data_data_ok,
output [ 3:0] arid,
output [31:0] araddr,
output [ 7:0] arlen,
output [ 2:0] arsize,
output [ 1:0] arburst,
output [ 1:0] arlock,
output [ 3:0] arcache,
output [ 2:0] arprot,
output reg arvalid,
input arready,
input [ 3:0] rid,
input [31:0] rdata,
input [ 1:0] rresp,
input rlast,
input rvalid,
output reg rready,
output [ 3:0] awid,
output [31:0] awaddr,
output [ 7:0] awlen,
output [ 2:0] awsize,
output [ 1:0] awburst,
output [ 1:0] awlock,
output [ 3:0] awcache,
output [ 2:0] awprot,
output reg awvalid,
input awready,
output [ 3:0] wid,
output [31:0] wdata,
output [ 3:0] wstrb,
output wlast,
output reg wvalid,
input wready,
input [ 3:0] bid,
input [ 1:0] bresp,
input bvalid,
output reg bready
); |
reg do_req_raddr_or;
reg [ 3:0] do_arid;
reg [31:0] do_araddr;
reg [31:0] do_arsize;
reg r_addr_rcv;
reg r_addr_rcv_r;
wire r_data_back;
wire r_addr_rcv_pos;
reg do_req_waddr;
reg do_req_waddr_r;
wire do_req_waddr_pos;
reg do_req_wdata;
reg do_req_wdata_r;
wire do_req_wdata_pos;
reg w_addr_rcv;
reg w_data_rcv;
wire w_data_back;
reg [31:0] do_wdata_r;
reg [32:0] do_waddr_r;
reg [ 1:0] do_dsize_r;
reg [ 1:0] data_in_ready;
reg [ 1:0] data_in_ready_r;
wire data_in_ready_pos;
reg w_addr_rcv_r;
reg w_data_rcv_r;
wire w_addr_rcv_pos;
wire w_data_rcv_pos;
assign inst_addr_ok = arvalid&&arready && !do_req_raddr_or;
assign data_addr_ok = arvalid&&arready && do_req_raddr_or ||
data_in_ready==2'b01 && wvalid&&wready && do_waddr_r[32] ||
data_in_ready==2'b10 && awvalid&&awready && do_waddr_r[32] ;
always @ (posedge clk) begin
do_req_raddr_or <= !resetn ? 1'b0 :
arready&&arvalid ? (data_req&&!data_wr) : do_req_raddr_or;
do_arid <= !resetn ? 4'd0 :
r_addr_rcv_pos ? (do_req_raddr_or ? 4'd1 : 4'd0) : do_arid;
do_araddr <= !resetn ? 32'd0 :
r_addr_rcv_pos ? (do_req_raddr_or ? data_addr : inst_addr) : do_araddr;
do_arsize <= !resetn ? 3'd0 :
r_addr_rcv_pos ? (do_req_raddr_or ? data_size : inst_size) : do_arsize;
arvalid <= !resetn ? 1'b0 :
r_addr_rcv_pos&&(inst_req||data_req&&!data_wr) ? 1'b1 :
arready ? 1'b0 : 1'b1;
end
always @(posedge clk) begin
r_addr_rcv <= !resetn ? 1'b0 :
arvalid&&arready ? 1'b1 :
r_data_back ? 1'b0 : r_addr_rcv;
rready <= !resetn ? 1'b0 :
r_addr_rcv_pos ? 1'b1 :
r_data_back ? 1'b0 : rready;
end
assign r_data_back = r_addr_rcv && (rvalid && rready);
always @ (posedge clk) begin
do_req_waddr <= !resetn ? 1'b0 :
data_req&&data_wr && !do_req_waddr ? 1'b1 :
w_data_back ? 1'b0 : do_req_waddr;
do_req_wdata <= !resetn ? 1'b0 :
data_req&&data_wr && !do_req_wdata ? 1'b1 :
w_data_back ? 1'b0 : do_req_wdata;
do_waddr_r <= !resetn ? 33'd0 :
data_in_ready_pos ? {1'b1,data_addr} : do_waddr_r;
do_wdata_r <= data_in_ready_pos ? data_wdata : do_wdata_r;
do_dsize_r <= data_in_ready_pos ? data_size : do_dsize_r;
data_in_ready <= !resetn ? 2'b00 :
w_addr_rcv_pos&&w_data_rcv_pos ? 2'b11 :
w_addr_rcv_pos ? data_in_ready + 2'b01 :
w_data_rcv_pos ? data_in_ready + 2'b10 :
w_data_back ? 2'b00 : data_in_ready;
awvalid <= !resetn ? 1'b0 :
do_req_waddr_pos ? 1'b1 :
awready ? 1'b0 : awvalid;
wvalid <= !resetn ? 1'b0 :
do_req_wdata_pos ? 1'b1 :
wready ? 1'b0 : wvalid;
end
always @ (posedge clk) begin
w_addr_rcv <= !resetn ? 1'b0 :
awvalid&&awready ? 1'b1 :
w_data_back ? 1'b0 : w_addr_rcv;
w_data_rcv <= !resetn ? 1'b0 :
wvalid&&wready ? 1'b1 :
w_data_back ? 1'b0 : w_data_rcv;
bready <= !resetn ? 1'b0 :
w_addr_rcv&&w_data_rcv ? 1'b1 :
w_data_back ? 1'b0 : bready;
end
assign w_data_back = (w_addr_rcv&&w_data_rcv) && (bvalid && bready);
assign arid = do_arid;
assign araddr = do_araddr;
assign arsize = do_arsize;
assign arlen = 8'd0;
assign arburst = 2'b01;
assign arlock = 2'd0;
assign arcache = 4'd0;
assign arprot = 3'd0;
assign awaddr = do_req_waddr ? do_waddr_r[31:0] : 32'hxxxxxxxx;
assign awsize = do_req_waddr ? do_dsize_r : 3'hx;
assign awid = 4'd0;
assign awlen = 8'd0;
assign awburst = 2'b01;
assign awlock = 2'd0;
assign awcache = 4'd0;
assign awprot = 3'd0;
assign wdata = do_wdata_r;
assign wstrb = do_dsize_r==2'd0 ? 4'b0001<<do_waddr_r[1:0] :
do_dsize_r==2'd1 ? 4'b0011<<do_waddr_r[1:0] : 4'b1111;
assign wid = 4'd0;
assign wlast = 1'b1;
assign inst_data_ok = r_data_back && rid==4'd0;
assign data_data_ok = (r_data_back && rid==4'd1) || w_data_back;
assign inst_rdata = rid==4'd0 ? rdata : 32'hxxxxxxxx;
assign data_rdata = rid==4'd1 ? rdata : 32'hxxxxxxxx;
always @ (posedge clk) begin
r_addr_rcv_r <= !resetn ? 1'b0 : r_addr_rcv;
data_in_ready_r <= !resetn ? 2'd0 : data_in_ready;
w_addr_rcv_r <= !resetn ? 1'b0 : w_addr_rcv;
w_data_rcv_r <= !resetn ? 1'b0 : w_data_rcv;
do_req_waddr_r <= !resetn ? 1'b0 : do_req_waddr;
do_req_wdata_r <= !resetn ? 1'b0 : do_req_wdata;
end
assign r_addr_rcv_pos = r_addr_rcv & ~r_addr_rcv_r;
assign data_in_ready_pos = data_in_ready==2'd3 & data_in_ready_r!=2'd3;
assign w_addr_rcv_pos = w_addr_rcv & ~w_addr_rcv_r;
assign w_data_rcv_pos = w_data_rcv & ~w_data_rcv_r;
assign do_req_waddr_pos = do_req_waddr & ~do_req_waddr_r;
assign do_req_wdata_pos = do_req_wdata & ~do_req_wdata_r;
integer wr_cnt;
always @ (posedge clk) begin
if(!resetn) wr_cnt <= 'd0;
else if(bvalid&&bready)
wr_cnt <= wr_cnt + 'd1;
end
endmodule | 0 |
4,893 | data/full_repos/permissive/112219256/decode_stage.v | 112,219,256 | decode_stage.v | v | 371 | 95 | [] | [] | [] | [(11, 350), (352, 369)] | null | null | 1: b'%Error: data/full_repos/permissive/112219256/decode_stage.v:272: Cannot find file containing module: \'Control_Unit\'\n Control_Unit Control(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/Control_Unit\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/Control_Unit.v\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/Control_Unit.sv\n Control_Unit\n Control_Unit.v\n Control_Unit.sv\n obj_dir/Control_Unit\n obj_dir/Control_Unit.v\n obj_dir/Control_Unit.sv\n%Error: data/full_repos/permissive/112219256/decode_stage.v:314: Cannot find file containing module: \'MUX_4_32\'\n MUX_4_32 RegRdata1_MUX(\n ^~~~~~~~\n%Error: data/full_repos/permissive/112219256/decode_stage.v:322: Cannot find file containing module: \'MUX_4_32\'\n MUX_4_32 RegRdata2_MUX(\n ^~~~~~~~\n%Error: data/full_repos/permissive/112219256/decode_stage.v:330: Cannot find file containing module: \'MUX_3_5\'\n MUX_3_5 RegWaddr_MUX(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112219256/decode_stage.v:346: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'MULT_EXE_MEM\' generates 2 bits.\n : ... In instance decode_stage\n assign ID_EXE_data = |MFHL_ID_EXE ? (MULT_EXE_MEM ? MULT_HI_LO : EXE_HI_LO) : Bypass_EXE;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 3,305 | module | module decode_stage(
input wire clk,
input wire rst,
input wire [31:0] Inst_IF_ID,
input wire [31:0] PC_IF_ID,
input wire [31:0] PC_add_4_IF_ID,
input wire PC_AdEL_IF_ID,
input wire DSI_IF_ID,
output wire [ 4:0] RegRaddr1_ID,
output wire [ 4:0] RegRaddr2_ID,
input wire [31:0] RegRdata1_ID,
input wire [31:0] RegRdata2_ID,
input wire ex_int_handle_ID,
input wire [31:0] Bypass_EXE,
input wire [31:0] Bypass_MEM,
input wire [31:0] RegWdata_WB,
input wire [63:0] MULT_Result,
input wire [31:0] HI,
input wire [31:0] LO,
input wire [ 1:0] MFHL_ID_EXE_1,
input wire [ 1:0] MFHL_EXE_MEM,
input wire [ 1:0] MFHL_MEM_WB,
input wire [ 1:0] MULT_EXE_MEM,
input wire [ 1:0] RegRdata1_src,
input wire [ 1:0] RegRdata2_src,
input wire ID_EXE_Stall,
input wire DIV_Complete,
output wire JSrc,
output wire [ 1:0] PCSrc,
output wire [31:0] J_target_ID,
output wire [31:0] JR_target_ID,
output wire [31:0] Br_target_ID,
output reg [ 1:0] ALUSrcA_ID_EXE,
output reg [ 1:0] ALUSrcB_ID_EXE,
output reg [ 3:0] ALUop_ID_EXE,
output reg [ 3:0] RegWrite_ID_EXE,
output reg [ 3:0] MemWrite_ID_EXE,
output reg MemEn_ID_EXE,
output reg MemToReg_ID_EXE,
output reg [ 1:0] MULT_ID_EXE,
output reg [ 1:0] DIV_ID_EXE,
output reg [ 1:0] MFHL_ID_EXE,
output reg [ 1:0] MTHL_ID_EXE,
output reg LB_ID_EXE,
output reg LBU_ID_EXE,
output reg LH_ID_EXE,
output reg LHU_ID_EXE,
output reg [ 1:0] LW_ID_EXE,
output reg [ 1:0] SW_ID_EXE,
output reg SB_ID_EXE,
output reg SH_ID_EXE,
output reg mfc0_ID_EXE,
output reg cp0_Write_ID_EXE,
output reg is_signed_ID_EXE,
output reg DSI_ID_EXE,
output reg eret_ID_EXE,
output reg [ 3:0] Exc_vec_ID_EXE,
output reg [ 4:0] Rd_ID_EXE,
output reg [ 4:0] RegWaddr_ID_EXE,
output reg [31:0] PC_add_4_ID_EXE,
output reg [31:0] PC_ID_EXE,
output reg [31:0] RegRdata1_ID_EXE,
output reg [31:0] RegRdata2_ID_EXE,
output reg [31:0] Sa_ID_EXE,
output reg [31:0] SgnExtend_ID_EXE,
output reg [31:0] ZExtend_ID_EXE,
output is_j_or_br_ID,
output is_rs_read_ID,
output is_rt_read_ID,
input ex_int_handling,
input eret_handling,
output de_to_exe_valid,
output decode_allowin,
input exe_allowin,
input fe_to_de_valid,
output exe_refresh,
output decode_stage_valid
);
reg decode_valid;
wire decode_ready_go;
assign decode_ready_go = !ID_EXE_Stall;
assign decode_allowin = !decode_valid || exe_allowin && decode_ready_go;
assign de_to_exe_valid = decode_valid&&decode_ready_go;
always @ (posedge clk) begin
if (rst) begin
decode_valid <= 1'b0;
end
else if (decode_allowin) begin
decode_valid <= fe_to_de_valid;
end
end
assign decode_stage_valid = decode_valid;
assign exe_refresh = de_to_exe_valid&&exe_allowin;
wire eret_ID;
wire cp0_Write;
wire BranchCond_ID;
wire MemToReg_ID;
wire JSrc_ID;
wire MemEn_ID;
wire [ 1:0] ALUSrcA_ID;
wire [ 1:0] ALUSrcB_ID;
wire [ 1:0] RegDst_ID;
wire [ 1:0] PCSrc_ID;
wire [ 3:0] ALUop_ID;
wire [ 3:0] MemWrite_ID;
wire [ 3:0] RegWrite_ID;
wire [31:0] SgnExtend_ID;
wire [31:0] ZExtend_ID;
wire [31:0] SgnExtend_LF2_ID;
wire [31:0] PC_add_4_ID;
wire [31:0] Sa_ID;
wire [31:0] PC_ID;
wire [ 4:0] RegWaddr_ID;
wire [ 5:0] B_Type_ID;
wire [ 1:0] MULT_ID;
wire [ 1:0] DIV_ID;
wire [ 1:0] MFHL_ID;
wire [ 1:0] MTHL_ID;
wire LB_ID;
wire LBU_ID;
wire LH_ID;
wire LHU_ID;
wire [ 1:0] LW_ID;
wire [ 1:0] SW_ID;
wire SB_ID;
wire SH_ID;
wire mfc0_ID;
wire is_signed_ID;
wire RI_ID;
wire sys_ID;
wire bp_ID;
wire [31:0] RegRdata1_Final_ID;
wire [31:0] RegRdata2_Final_ID;
wire [ 3:0] Exc_vec_ID;
wire [ 4:0] rs,rt,sa,rd;
wire [31:0] ID_EXE_data;
wire [31:0] EXE_MEM_data;
wire [31:0] MEM_WB_data;
assign Exc_vec_ID = {PC_AdEL_IF_ID,RI_ID,sys_ID,bp_ID};
assign rs = Inst_IF_ID[25:21];
assign rt = Inst_IF_ID[20:16];
assign rd = Inst_IF_ID[15:11];
assign sa = Inst_IF_ID[10: 6];
assign RegRaddr1_ID = Inst_IF_ID[25:21];
assign RegRaddr2_ID = Inst_IF_ID[20:16];
assign SgnExtend_ID = {{16{Inst_IF_ID[15]}},Inst_IF_ID[15:0]};
assign ZExtend_ID = {{16'd0},Inst_IF_ID[15:0]};
assign Sa_ID = {{27{1'b0}}, Inst_IF_ID[10: 6]};
assign SgnExtend_LF2_ID = SgnExtend_ID << 2;
assign JSrc = JSrc_ID & ~(ex_int_handling|eret_handling);
assign PCSrc = PCSrc_ID & {2{~(ex_int_handling|eret_handling)}};
assign J_target_ID = {{PC_IF_ID[31:28]},{Inst_IF_ID[25:0]},{2'b00}};
assign JR_target_ID = RegRdata1_Final_ID;
assign Br_target_ID = PC_add_4_ID + SgnExtend_LF2_ID;
assign PC_ID = PC_IF_ID;
assign PC_add_4_ID = PC_add_4_IF_ID;
always @ (posedge clk) begin
if (rst) begin
{
MemEn_ID_EXE, MemToReg_ID_EXE, ALUop_ID_EXE, RegWrite_ID_EXE,
MemWrite_ID_EXE, ALUSrcA_ID_EXE, ALUSrcB_ID_EXE, MULT_ID_EXE,
DIV_ID_EXE, MFHL_ID_EXE, MTHL_ID_EXE, LB_ID_EXE,
LBU_ID_EXE, LH_ID_EXE, LHU_ID_EXE, LW_ID_EXE,
SW_ID_EXE, SB_ID_EXE, SH_ID_EXE, mfc0_ID_EXE,
RegWaddr_ID_EXE, Sa_ID_EXE, PC_ID_EXE, PC_add_4_ID_EXE,
RegRdata1_ID_EXE, RegRdata2_ID_EXE, SgnExtend_ID_EXE, ZExtend_ID_EXE,
is_signed_ID_EXE, DSI_ID_EXE, Exc_vec_ID_EXE, eret_ID_EXE,
Rd_ID_EXE, cp0_Write_ID_EXE
} <= 'd0;
end
else begin
if (de_to_exe_valid&&exe_allowin) begin
MemEn_ID_EXE <= MemEn_ID;
MemToReg_ID_EXE <= MemToReg_ID;
ALUop_ID_EXE <= ALUop_ID;
RegWrite_ID_EXE <= RegWrite_ID;
MemWrite_ID_EXE <= MemWrite_ID;
ALUSrcA_ID_EXE <= ALUSrcA_ID;
ALUSrcB_ID_EXE <= ALUSrcB_ID;
MULT_ID_EXE <= MULT_ID;
DIV_ID_EXE <= DIV_ID;
MFHL_ID_EXE <= MFHL_ID;
MTHL_ID_EXE <= MTHL_ID;
LB_ID_EXE <= LB_ID;
LBU_ID_EXE <= LBU_ID;
LH_ID_EXE <= LH_ID;
LHU_ID_EXE <= LHU_ID;
LW_ID_EXE <= LW_ID;
SW_ID_EXE <= SW_ID;
SB_ID_EXE <= SB_ID;
SH_ID_EXE <= SH_ID;
mfc0_ID_EXE <= mfc0_ID;
is_signed_ID_EXE <= is_signed_ID;
Exc_vec_ID_EXE <= Exc_vec_ID;
cp0_Write_ID_EXE <= cp0_Write;
DSI_ID_EXE <= DSI_IF_ID;
eret_ID_EXE <= eret_ID;
Rd_ID_EXE <= rd;
RegWaddr_ID_EXE <= RegWaddr_ID;
Sa_ID_EXE <= Sa_ID;
PC_ID_EXE <= PC_IF_ID;
PC_add_4_ID_EXE <= PC_add_4_IF_ID;
RegRdata1_ID_EXE <= RegRdata1_Final_ID;
RegRdata2_ID_EXE <= RegRdata2_Final_ID;
SgnExtend_ID_EXE <= SgnExtend_ID;
ZExtend_ID_EXE <= ZExtend_ID;
end
end
end
Branch_Cond Branch_Cond(
.A ( RegRdata1_Final_ID),
.B ( RegRdata2_Final_ID),
.B_Type ( B_Type_ID),
.Cond ( BranchCond_ID)
);
Control_Unit Control(
.rst ( rst),
.BranchCond ( BranchCond_ID),
.op ( Inst_IF_ID[31:26]),
.func ( Inst_IF_ID[ 5: 0]),
.rs ( Inst_IF_ID[25:21]),
.rt ( rt),
.MemEn ( MemEn_ID),
.JSrc ( JSrc_ID),
.MemToReg ( MemToReg_ID),
.ALUop ( ALUop_ID),
.PCSrc ( PCSrc_ID),
.RegDst ( RegDst_ID),
.RegWrite ( RegWrite_ID),
.MemWrite ( MemWrite_ID),
.ALUSrcA ( ALUSrcA_ID),
.ALUSrcB ( ALUSrcB_ID),
.is_rs_read ( is_rs_read_ID),
.is_rt_read ( is_rt_read_ID),
.B_Type ( B_Type_ID),
.MULT ( MULT_ID),
.DIV ( DIV_ID),
.MFHL ( MFHL_ID),
.MTHL ( MTHL_ID),
.LB ( LB_ID),
.LBU ( LBU_ID),
.LH ( LH_ID),
.LHU ( LHU_ID),
.LW ( LW_ID),
.SW ( SW_ID),
.SB ( SB_ID),
.SH ( SH_ID),
.mfc0 ( mfc0_ID),
.eret ( eret_ID),
.cp0_Write ( cp0_Write),
.is_signed ( is_signed_ID),
.ri ( RI_ID),
.is_j_or_br ( is_j_or_br_ID),
.sys ( sys_ID),
.bp ( bp_ID)
);
MUX_4_32 RegRdata1_MUX(
.Src1 ( RegRdata1_ID),
.Src2 ( ID_EXE_data),
.Src3 ( EXE_MEM_data),
.Src4 ( MEM_WB_data),
.op ( RegRdata1_src),
.Result ( RegRdata1_Final_ID)
);
MUX_4_32 RegRdata2_MUX(
.Src1 ( RegRdata2_ID),
.Src2 ( ID_EXE_data),
.Src3 ( EXE_MEM_data),
.Src4 ( MEM_WB_data),
.op ( RegRdata2_src),
.Result ( RegRdata2_Final_ID)
);
MUX_3_5 RegWaddr_MUX(
.Src1 ( rt),
.Src2 ( rd),
.Src3 ( 5'b11111),
.op ( RegDst_ID),
.Result ( RegWaddr_ID)
);
wire [31:0] MULT_HI_LO = {32{MFHL_ID_EXE_1[1]}} & MULT_Result[63:32] |
{32{MFHL_ID_EXE_1[0]}} & MULT_Result[31: 0] ;
wire [31:0] EXE_HI_LO = {32{MFHL_ID_EXE_1[1]}} & HI |
{32{MFHL_ID_EXE_1[0]}} & LO ;
wire [31:0] MEM_HI_LO = {32{MFHL_EXE_MEM[1]}} & HI |
{32{MFHL_EXE_MEM[0]}} & LO ;
wire [31:0] WB_HI_LO = {32{MFHL_MEM_WB[1]}} & HI |
{32{MFHL_MEM_WB[0]}} & LO ;
assign ID_EXE_data = |MFHL_ID_EXE ? (MULT_EXE_MEM ? MULT_HI_LO : EXE_HI_LO) : Bypass_EXE;
assign EXE_MEM_data = |MFHL_EXE_MEM ? MEM_HI_LO : Bypass_MEM;
assign MEM_WB_data = |MFHL_MEM_WB ? WB_HI_LO : RegWdata_WB;
endmodule | module decode_stage(
input wire clk,
input wire rst,
input wire [31:0] Inst_IF_ID,
input wire [31:0] PC_IF_ID,
input wire [31:0] PC_add_4_IF_ID,
input wire PC_AdEL_IF_ID,
input wire DSI_IF_ID,
output wire [ 4:0] RegRaddr1_ID,
output wire [ 4:0] RegRaddr2_ID,
input wire [31:0] RegRdata1_ID,
input wire [31:0] RegRdata2_ID,
input wire ex_int_handle_ID,
input wire [31:0] Bypass_EXE,
input wire [31:0] Bypass_MEM,
input wire [31:0] RegWdata_WB,
input wire [63:0] MULT_Result,
input wire [31:0] HI,
input wire [31:0] LO,
input wire [ 1:0] MFHL_ID_EXE_1,
input wire [ 1:0] MFHL_EXE_MEM,
input wire [ 1:0] MFHL_MEM_WB,
input wire [ 1:0] MULT_EXE_MEM,
input wire [ 1:0] RegRdata1_src,
input wire [ 1:0] RegRdata2_src,
input wire ID_EXE_Stall,
input wire DIV_Complete,
output wire JSrc,
output wire [ 1:0] PCSrc,
output wire [31:0] J_target_ID,
output wire [31:0] JR_target_ID,
output wire [31:0] Br_target_ID,
output reg [ 1:0] ALUSrcA_ID_EXE,
output reg [ 1:0] ALUSrcB_ID_EXE,
output reg [ 3:0] ALUop_ID_EXE,
output reg [ 3:0] RegWrite_ID_EXE,
output reg [ 3:0] MemWrite_ID_EXE,
output reg MemEn_ID_EXE,
output reg MemToReg_ID_EXE,
output reg [ 1:0] MULT_ID_EXE,
output reg [ 1:0] DIV_ID_EXE,
output reg [ 1:0] MFHL_ID_EXE,
output reg [ 1:0] MTHL_ID_EXE,
output reg LB_ID_EXE,
output reg LBU_ID_EXE,
output reg LH_ID_EXE,
output reg LHU_ID_EXE,
output reg [ 1:0] LW_ID_EXE,
output reg [ 1:0] SW_ID_EXE,
output reg SB_ID_EXE,
output reg SH_ID_EXE,
output reg mfc0_ID_EXE,
output reg cp0_Write_ID_EXE,
output reg is_signed_ID_EXE,
output reg DSI_ID_EXE,
output reg eret_ID_EXE,
output reg [ 3:0] Exc_vec_ID_EXE,
output reg [ 4:0] Rd_ID_EXE,
output reg [ 4:0] RegWaddr_ID_EXE,
output reg [31:0] PC_add_4_ID_EXE,
output reg [31:0] PC_ID_EXE,
output reg [31:0] RegRdata1_ID_EXE,
output reg [31:0] RegRdata2_ID_EXE,
output reg [31:0] Sa_ID_EXE,
output reg [31:0] SgnExtend_ID_EXE,
output reg [31:0] ZExtend_ID_EXE,
output is_j_or_br_ID,
output is_rs_read_ID,
output is_rt_read_ID,
input ex_int_handling,
input eret_handling,
output de_to_exe_valid,
output decode_allowin,
input exe_allowin,
input fe_to_de_valid,
output exe_refresh,
output decode_stage_valid
); |
reg decode_valid;
wire decode_ready_go;
assign decode_ready_go = !ID_EXE_Stall;
assign decode_allowin = !decode_valid || exe_allowin && decode_ready_go;
assign de_to_exe_valid = decode_valid&&decode_ready_go;
always @ (posedge clk) begin
if (rst) begin
decode_valid <= 1'b0;
end
else if (decode_allowin) begin
decode_valid <= fe_to_de_valid;
end
end
assign decode_stage_valid = decode_valid;
assign exe_refresh = de_to_exe_valid&&exe_allowin;
wire eret_ID;
wire cp0_Write;
wire BranchCond_ID;
wire MemToReg_ID;
wire JSrc_ID;
wire MemEn_ID;
wire [ 1:0] ALUSrcA_ID;
wire [ 1:0] ALUSrcB_ID;
wire [ 1:0] RegDst_ID;
wire [ 1:0] PCSrc_ID;
wire [ 3:0] ALUop_ID;
wire [ 3:0] MemWrite_ID;
wire [ 3:0] RegWrite_ID;
wire [31:0] SgnExtend_ID;
wire [31:0] ZExtend_ID;
wire [31:0] SgnExtend_LF2_ID;
wire [31:0] PC_add_4_ID;
wire [31:0] Sa_ID;
wire [31:0] PC_ID;
wire [ 4:0] RegWaddr_ID;
wire [ 5:0] B_Type_ID;
wire [ 1:0] MULT_ID;
wire [ 1:0] DIV_ID;
wire [ 1:0] MFHL_ID;
wire [ 1:0] MTHL_ID;
wire LB_ID;
wire LBU_ID;
wire LH_ID;
wire LHU_ID;
wire [ 1:0] LW_ID;
wire [ 1:0] SW_ID;
wire SB_ID;
wire SH_ID;
wire mfc0_ID;
wire is_signed_ID;
wire RI_ID;
wire sys_ID;
wire bp_ID;
wire [31:0] RegRdata1_Final_ID;
wire [31:0] RegRdata2_Final_ID;
wire [ 3:0] Exc_vec_ID;
wire [ 4:0] rs,rt,sa,rd;
wire [31:0] ID_EXE_data;
wire [31:0] EXE_MEM_data;
wire [31:0] MEM_WB_data;
assign Exc_vec_ID = {PC_AdEL_IF_ID,RI_ID,sys_ID,bp_ID};
assign rs = Inst_IF_ID[25:21];
assign rt = Inst_IF_ID[20:16];
assign rd = Inst_IF_ID[15:11];
assign sa = Inst_IF_ID[10: 6];
assign RegRaddr1_ID = Inst_IF_ID[25:21];
assign RegRaddr2_ID = Inst_IF_ID[20:16];
assign SgnExtend_ID = {{16{Inst_IF_ID[15]}},Inst_IF_ID[15:0]};
assign ZExtend_ID = {{16'd0},Inst_IF_ID[15:0]};
assign Sa_ID = {{27{1'b0}}, Inst_IF_ID[10: 6]};
assign SgnExtend_LF2_ID = SgnExtend_ID << 2;
assign JSrc = JSrc_ID & ~(ex_int_handling|eret_handling);
assign PCSrc = PCSrc_ID & {2{~(ex_int_handling|eret_handling)}};
assign J_target_ID = {{PC_IF_ID[31:28]},{Inst_IF_ID[25:0]},{2'b00}};
assign JR_target_ID = RegRdata1_Final_ID;
assign Br_target_ID = PC_add_4_ID + SgnExtend_LF2_ID;
assign PC_ID = PC_IF_ID;
assign PC_add_4_ID = PC_add_4_IF_ID;
always @ (posedge clk) begin
if (rst) begin
{
MemEn_ID_EXE, MemToReg_ID_EXE, ALUop_ID_EXE, RegWrite_ID_EXE,
MemWrite_ID_EXE, ALUSrcA_ID_EXE, ALUSrcB_ID_EXE, MULT_ID_EXE,
DIV_ID_EXE, MFHL_ID_EXE, MTHL_ID_EXE, LB_ID_EXE,
LBU_ID_EXE, LH_ID_EXE, LHU_ID_EXE, LW_ID_EXE,
SW_ID_EXE, SB_ID_EXE, SH_ID_EXE, mfc0_ID_EXE,
RegWaddr_ID_EXE, Sa_ID_EXE, PC_ID_EXE, PC_add_4_ID_EXE,
RegRdata1_ID_EXE, RegRdata2_ID_EXE, SgnExtend_ID_EXE, ZExtend_ID_EXE,
is_signed_ID_EXE, DSI_ID_EXE, Exc_vec_ID_EXE, eret_ID_EXE,
Rd_ID_EXE, cp0_Write_ID_EXE
} <= 'd0;
end
else begin
if (de_to_exe_valid&&exe_allowin) begin
MemEn_ID_EXE <= MemEn_ID;
MemToReg_ID_EXE <= MemToReg_ID;
ALUop_ID_EXE <= ALUop_ID;
RegWrite_ID_EXE <= RegWrite_ID;
MemWrite_ID_EXE <= MemWrite_ID;
ALUSrcA_ID_EXE <= ALUSrcA_ID;
ALUSrcB_ID_EXE <= ALUSrcB_ID;
MULT_ID_EXE <= MULT_ID;
DIV_ID_EXE <= DIV_ID;
MFHL_ID_EXE <= MFHL_ID;
MTHL_ID_EXE <= MTHL_ID;
LB_ID_EXE <= LB_ID;
LBU_ID_EXE <= LBU_ID;
LH_ID_EXE <= LH_ID;
LHU_ID_EXE <= LHU_ID;
LW_ID_EXE <= LW_ID;
SW_ID_EXE <= SW_ID;
SB_ID_EXE <= SB_ID;
SH_ID_EXE <= SH_ID;
mfc0_ID_EXE <= mfc0_ID;
is_signed_ID_EXE <= is_signed_ID;
Exc_vec_ID_EXE <= Exc_vec_ID;
cp0_Write_ID_EXE <= cp0_Write;
DSI_ID_EXE <= DSI_IF_ID;
eret_ID_EXE <= eret_ID;
Rd_ID_EXE <= rd;
RegWaddr_ID_EXE <= RegWaddr_ID;
Sa_ID_EXE <= Sa_ID;
PC_ID_EXE <= PC_IF_ID;
PC_add_4_ID_EXE <= PC_add_4_IF_ID;
RegRdata1_ID_EXE <= RegRdata1_Final_ID;
RegRdata2_ID_EXE <= RegRdata2_Final_ID;
SgnExtend_ID_EXE <= SgnExtend_ID;
ZExtend_ID_EXE <= ZExtend_ID;
end
end
end
Branch_Cond Branch_Cond(
.A ( RegRdata1_Final_ID),
.B ( RegRdata2_Final_ID),
.B_Type ( B_Type_ID),
.Cond ( BranchCond_ID)
);
Control_Unit Control(
.rst ( rst),
.BranchCond ( BranchCond_ID),
.op ( Inst_IF_ID[31:26]),
.func ( Inst_IF_ID[ 5: 0]),
.rs ( Inst_IF_ID[25:21]),
.rt ( rt),
.MemEn ( MemEn_ID),
.JSrc ( JSrc_ID),
.MemToReg ( MemToReg_ID),
.ALUop ( ALUop_ID),
.PCSrc ( PCSrc_ID),
.RegDst ( RegDst_ID),
.RegWrite ( RegWrite_ID),
.MemWrite ( MemWrite_ID),
.ALUSrcA ( ALUSrcA_ID),
.ALUSrcB ( ALUSrcB_ID),
.is_rs_read ( is_rs_read_ID),
.is_rt_read ( is_rt_read_ID),
.B_Type ( B_Type_ID),
.MULT ( MULT_ID),
.DIV ( DIV_ID),
.MFHL ( MFHL_ID),
.MTHL ( MTHL_ID),
.LB ( LB_ID),
.LBU ( LBU_ID),
.LH ( LH_ID),
.LHU ( LHU_ID),
.LW ( LW_ID),
.SW ( SW_ID),
.SB ( SB_ID),
.SH ( SH_ID),
.mfc0 ( mfc0_ID),
.eret ( eret_ID),
.cp0_Write ( cp0_Write),
.is_signed ( is_signed_ID),
.ri ( RI_ID),
.is_j_or_br ( is_j_or_br_ID),
.sys ( sys_ID),
.bp ( bp_ID)
);
MUX_4_32 RegRdata1_MUX(
.Src1 ( RegRdata1_ID),
.Src2 ( ID_EXE_data),
.Src3 ( EXE_MEM_data),
.Src4 ( MEM_WB_data),
.op ( RegRdata1_src),
.Result ( RegRdata1_Final_ID)
);
MUX_4_32 RegRdata2_MUX(
.Src1 ( RegRdata2_ID),
.Src2 ( ID_EXE_data),
.Src3 ( EXE_MEM_data),
.Src4 ( MEM_WB_data),
.op ( RegRdata2_src),
.Result ( RegRdata2_Final_ID)
);
MUX_3_5 RegWaddr_MUX(
.Src1 ( rt),
.Src2 ( rd),
.Src3 ( 5'b11111),
.op ( RegDst_ID),
.Result ( RegWaddr_ID)
);
wire [31:0] MULT_HI_LO = {32{MFHL_ID_EXE_1[1]}} & MULT_Result[63:32] |
{32{MFHL_ID_EXE_1[0]}} & MULT_Result[31: 0] ;
wire [31:0] EXE_HI_LO = {32{MFHL_ID_EXE_1[1]}} & HI |
{32{MFHL_ID_EXE_1[0]}} & LO ;
wire [31:0] MEM_HI_LO = {32{MFHL_EXE_MEM[1]}} & HI |
{32{MFHL_EXE_MEM[0]}} & LO ;
wire [31:0] WB_HI_LO = {32{MFHL_MEM_WB[1]}} & HI |
{32{MFHL_MEM_WB[0]}} & LO ;
assign ID_EXE_data = |MFHL_ID_EXE ? (MULT_EXE_MEM ? MULT_HI_LO : EXE_HI_LO) : Bypass_EXE;
assign EXE_MEM_data = |MFHL_EXE_MEM ? MEM_HI_LO : Bypass_MEM;
assign MEM_WB_data = |MFHL_MEM_WB ? WB_HI_LO : RegWdata_WB;
endmodule | 0 |
4,894 | data/full_repos/permissive/112219256/decode_stage.v | 112,219,256 | decode_stage.v | v | 371 | 95 | [] | [] | [] | [(11, 350), (352, 369)] | null | null | 1: b'%Error: data/full_repos/permissive/112219256/decode_stage.v:272: Cannot find file containing module: \'Control_Unit\'\n Control_Unit Control(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/Control_Unit\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/Control_Unit.v\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/Control_Unit.sv\n Control_Unit\n Control_Unit.v\n Control_Unit.sv\n obj_dir/Control_Unit\n obj_dir/Control_Unit.v\n obj_dir/Control_Unit.sv\n%Error: data/full_repos/permissive/112219256/decode_stage.v:314: Cannot find file containing module: \'MUX_4_32\'\n MUX_4_32 RegRdata1_MUX(\n ^~~~~~~~\n%Error: data/full_repos/permissive/112219256/decode_stage.v:322: Cannot find file containing module: \'MUX_4_32\'\n MUX_4_32 RegRdata2_MUX(\n ^~~~~~~~\n%Error: data/full_repos/permissive/112219256/decode_stage.v:330: Cannot find file containing module: \'MUX_3_5\'\n MUX_3_5 RegWaddr_MUX(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112219256/decode_stage.v:346: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'MULT_EXE_MEM\' generates 2 bits.\n : ... In instance decode_stage\n assign ID_EXE_data = |MFHL_ID_EXE ? (MULT_EXE_MEM ? MULT_HI_LO : EXE_HI_LO) : Bypass_EXE;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 3,305 | module | module Branch_Cond(
input [31:0] A,
input [31:0] B,
input [ 5:0] B_Type,
output Cond
);
wire zero, ge, gt, le, lt;
assign zero = ~(|(A - B));
assign ge = ~A[31];
assign gt = ~A[31] & |A[30:0];
assign le = A[31] | (&(~A[31:0]));
assign lt = A[31];
assign Cond = ((B_Type[0] & ~zero | B_Type[1] & zero) |
(B_Type[2] & ge | B_Type[3] & gt )) |
(B_Type[4] & le | B_Type[5] & lt );
endmodule | module Branch_Cond(
input [31:0] A,
input [31:0] B,
input [ 5:0] B_Type,
output Cond
); |
wire zero, ge, gt, le, lt;
assign zero = ~(|(A - B));
assign ge = ~A[31];
assign gt = ~A[31] & |A[30:0];
assign le = A[31] | (&(~A[31:0]));
assign lt = A[31];
assign Cond = ((B_Type[0] & ~zero | B_Type[1] & zero) |
(B_Type[2] & ge | B_Type[3] & gt )) |
(B_Type[4] & le | B_Type[5] & lt );
endmodule | 0 |
4,895 | data/full_repos/permissive/112219256/div.v | 112,219,256 | div.v | v | 80 | 75 | [] | [] | [] | [(11, 79)] | null | data/verilator_xmls/6141e8cd-7a79-4c2b-ae24-aa8f103e3321.xml | null | 3,306 | module | module divider(
input wire div_clk,
input wire rst,
input wire div,
input wire div_signed,
input wire [31:0] x,
input wire [31:0] y,
output wire [31:0] s,
output wire [31:0] r,
output wire busy,
output wire complete
);
reg [5:0] count;
wire sign_x;
wire sign_y;
wire [31:0] abs_x;
wire [31:0] abs_y;
assign sign_x = div_signed & x[31];
assign sign_y = div_signed & y[31];
assign abs_x = sign_x ? ~x+1 : x;
assign abs_y = sign_y ? ~y+1 : y;
wire [63:0] abs_x_63;
wire [63:0] abs_y_63;
assign abs_x_63 = {32'd0, abs_x};
assign abs_y_63 = {1'b0, abs_y, 31'd0};
reg [63:0] rmdr;
reg [31:0] q;
wire [63:0] next_rmdr;
wire [31:0] next_q;
always @(posedge div_clk) begin
if (rst || complete) begin
rmdr <= 64'd0;
count <= 6'd0;
q <= 32'd0;
end
else if (div==1 && count== 0) begin
rmdr <= abs_x_63;
count <= count + 1;
q <= q;
end
else if(div==1 ) begin
rmdr <= next_rmdr;
count <= count + 1;
q <= next_q;
end
end
wire [63:0] diff;
wire [63:0] r_64;
assign diff = rmdr - abs_y_63;
assign next_rmdr = diff[63] ? ({rmdr[62:0], 1'b0}) : ({diff[62:0], 1'b0});
assign r_64 = diff[63] ? (rmdr[63:0]) : (diff[63:0]) ;
assign next_q = {q[30:0], ~diff[63]};
assign complete = (count == 6'd32);
assign busy = ~complete÷
assign s = {32{ ~sign_x & ~sign_y | sign_x&sign_y }} & next_q
|{32{ sign_x & ~sign_y | ~sign_x & sign_y }} & (~next_q + 1);
assign r = {32{ ~sign_x }} & r_64[62:31]
|{32{ sign_x }} & (~r_64[62:31] + 1);
endmodule | module divider(
input wire div_clk,
input wire rst,
input wire div,
input wire div_signed,
input wire [31:0] x,
input wire [31:0] y,
output wire [31:0] s,
output wire [31:0] r,
output wire busy,
output wire complete
); |
reg [5:0] count;
wire sign_x;
wire sign_y;
wire [31:0] abs_x;
wire [31:0] abs_y;
assign sign_x = div_signed & x[31];
assign sign_y = div_signed & y[31];
assign abs_x = sign_x ? ~x+1 : x;
assign abs_y = sign_y ? ~y+1 : y;
wire [63:0] abs_x_63;
wire [63:0] abs_y_63;
assign abs_x_63 = {32'd0, abs_x};
assign abs_y_63 = {1'b0, abs_y, 31'd0};
reg [63:0] rmdr;
reg [31:0] q;
wire [63:0] next_rmdr;
wire [31:0] next_q;
always @(posedge div_clk) begin
if (rst || complete) begin
rmdr <= 64'd0;
count <= 6'd0;
q <= 32'd0;
end
else if (div==1 && count== 0) begin
rmdr <= abs_x_63;
count <= count + 1;
q <= q;
end
else if(div==1 ) begin
rmdr <= next_rmdr;
count <= count + 1;
q <= next_q;
end
end
wire [63:0] diff;
wire [63:0] r_64;
assign diff = rmdr - abs_y_63;
assign next_rmdr = diff[63] ? ({rmdr[62:0], 1'b0}) : ({diff[62:0], 1'b0});
assign r_64 = diff[63] ? (rmdr[63:0]) : (diff[63:0]) ;
assign next_q = {q[30:0], ~diff[63]};
assign complete = (count == 6'd32);
assign busy = ~complete÷
assign s = {32{ ~sign_x & ~sign_y | sign_x&sign_y }} & next_q
|{32{ sign_x & ~sign_y | ~sign_x & sign_y }} & (~next_q + 1);
assign r = {32{ ~sign_x }} & r_64[62:31]
|{32{ sign_x }} & (~r_64[62:31] + 1);
endmodule | 0 |
4,896 | data/full_repos/permissive/112219256/execute_stage.v | 112,219,256 | execute_stage.v | v | 460 | 111 | [] | [] | [] | [(11, 300), (305, 323), (325, 362), (364, 438), (440, 459)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/112219256/execute_stage.v:305: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'execute_stage\'\nmodule execute_stage(\n ^~~~~~~~~~~~~\n : ... Top module \'MUX_3_5\'\nmodule MUX_3_5(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112219256/execute_stage.v:409: Operator NOT expects 3 bits on the LHS, but LHS\'s VARREF \'vaddr\' generates 2 bits.\n : ... In instance execute_stage.Store\n assign size_r = &(~vaddr) ? 3\'b010 : ~vaddr; \n ^\n%Error: data/full_repos/permissive/112219256/execute_stage.v:241: Cannot find file containing module: \'MUX_4_32\'\n MUX_4_32 ALUA_MUX(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.v\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.sv\n MUX_4_32\n MUX_4_32.v\n MUX_4_32.sv\n obj_dir/MUX_4_32\n obj_dir/MUX_4_32.v\n obj_dir/MUX_4_32.sv\n%Error: data/full_repos/permissive/112219256/execute_stage.v:250: Cannot find file containing module: \'MUX_4_32\'\n MUX_4_32 ALUB_MUX(\n ^~~~~~~~\n%Error: data/full_repos/permissive/112219256/execute_stage.v:259: Cannot find file containing module: \'ALU\'\n ALU ALU(\n ^~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n' | 3,307 | module | module execute_stage(
input wire clk,
input wire rst,
input wire [31:0] PC_add_4_ID_EXE,
input wire [31:0] PC_ID_EXE,
input wire [31:0] RegRdata1_ID_EXE,
input wire [31:0] RegRdata2_ID_EXE,
input wire [31:0] Sa_ID_EXE,
input wire [31:0] SgnExtend_ID_EXE,
input wire [31:0] ZExtend_ID_EXE,
input wire [ 4:0] RegWaddr_ID_EXE,
input wire DSI_ID_EXE,
input wire [ 3:0] Exc_vec_ID_EXE,
input wire cp0_Write_ID_EXE,
input eret_ID_EXE,
input wire MemEn_ID_EXE,
input wire is_signed_ID_EXE,
input wire MemToReg_ID_EXE,
input wire [ 1:0] ALUSrcA_ID_EXE,
input wire [ 1:0] ALUSrcB_ID_EXE,
input wire [ 3:0] ALUop_ID_EXE,
input wire [ 3:0] MemWrite_ID_EXE,
input wire [ 3:0] RegWrite_ID_EXE,
input wire [ 1:0] MULT_ID_EXE,
input [ 1:0] DIV_ID_EXE,
input wire [ 1:0] MFHL_ID_EXE,
input wire [ 1:0] MTHL_ID_EXE,
input wire LB_ID_EXE,
input wire LBU_ID_EXE,
input wire LH_ID_EXE,
input wire LHU_ID_EXE,
input wire [ 1:0] LW_ID_EXE,
input wire [ 1:0] SW_ID_EXE,
input wire SB_ID_EXE,
input wire SH_ID_EXE,
output [ 1:0] DIV_EXE,
output [ 1:0] MULT_EXE,
output reg MemEn_EXE_MEM,
output reg MemToReg_EXE_MEM,
output reg [ 3:0] MemWrite_EXE_MEM,
output reg [ 3:0] RegWrite_EXE_MEM,
output reg [ 1:0] MULT_EXE_MEM,
output reg [ 1:0] MFHL_EXE_MEM,
output reg [ 1:0] MTHL_EXE_MEM,
output reg LB_EXE_MEM,
output reg LBU_EXE_MEM,
output reg LH_EXE_MEM,
output reg LHU_EXE_MEM,
output reg [ 1:0] LW_EXE_MEM,
output reg [ 4:0] RegWaddr_EXE_MEM,
output reg [31:0] ALUResult_EXE_MEM,
output reg [31:0] MemWdata_EXE_MEM,
output reg [31:0] PC_EXE_MEM,
output reg [31:0] RegRdata1_EXE_MEM,
output reg [31:0] RegRdata2_EXE_MEM,
output reg [ 1:0] s_vaddr_EXE_MEM,
output reg [ 2:0] s_size_EXE_MEM,
output wire [31:0] Bypass_EXE,
input wire [ 4:0] Rd_ID_EXE,
input wire mfc0_ID_EXE,
output reg [31:0] cp0Rdata_EXE_MEM,
output reg mfc0_EXE_MEM,
output cp0_Write_EXE,
output wire [31:0] Exc_BadVaddr,
output wire [31:0] Exc_EPC ,
output wire Exc_BD,
output wire [ 6:0] Exc_Vec,
input wire [31:0] cp0Rdata_EXE,
input wire ex_int_handle,
output reg ex_int_handling,
output reg eret_handling,
input mem_allowin,
input de_to_exe_valid,
output exe_allowin,
output exe_to_mem_valid,
output exe_stage_valid,
input ID_EXE_Stall,
output exe_ready_go,
input [31:0] epc_value,
input [31:0] PC
);
reg exe_valid;
assign exe_ready_go = !(ex_int_handle&&PC!=32'hbfc00380);
assign exe_allowin = !exe_valid || exe_ready_go && mem_allowin;
assign exe_to_mem_valid = exe_valid && exe_ready_go;
always @ (posedge clk) begin
if (rst) begin
exe_valid <= 1'b0;
end
else if (exe_allowin) begin
exe_valid <= de_to_exe_valid;
end
end
assign exe_stage_valid = exe_valid;
wire AdEL_EXE,AdES_EXE;
wire ACarryOut,AOverflow,AZero;
wire [31:0] ALUA,ALUB;
wire [ 4:0] RegWaddr_EXE;
wire [31:0] ALUResult_EXE,BadVaddr_EXE;
wire [ 3:0] MemWrite_Final;
wire [31:0] MemWdata;
wire [ 1:0] vaddr_final;
wire [ 2:0] s_size;
assign cp0_Write_EXE = cp0_Write_ID_EXE & ~(ex_int_handling|eret_handling);
assign MULT_EXE = MULT_ID_EXE & {2{~(ex_int_handling|eret_handling)}};
assign DIV_EXE = DIV_ID_EXE & {2{~(ex_int_handling|eret_handling)}};
assign BadVaddr_EXE = ALUResult_EXE & {32{AdEL_EXE|AdES_EXE}};
assign Exc_BadVaddr = Exc_vec_ID_EXE[3] ? PC_ID_EXE : BadVaddr_EXE;
assign Exc_EPC = DSI_ID_EXE ? PC_ID_EXE - 32'd4: PC_ID_EXE;
assign Exc_Vec = {Exc_vec_ID_EXE[3:2], AOverflow,
Exc_vec_ID_EXE[1:0], AdEL_EXE,AdES_EXE};
assign RegWaddr_EXE = RegWaddr_ID_EXE;
assign Bypass_EXE = mfc0_ID_EXE ? cp0Rdata_EXE : ALUResult_EXE;
assign Exc_BD = DSI_ID_EXE;
always @ (posedge clk) begin
if (rst) begin
ex_int_handling <= 1'b0;
eret_handling <= 1'b0;
end
else begin
if (PC_ID_EXE==32'hbfc00380) begin
ex_int_handling <= 1'b0;
end
else if (ex_int_handle) begin
ex_int_handling <= 1'b1;
end
if (PC_ID_EXE==epc_value) begin
eret_handling <= 1'b0;
end
else if (eret_ID_EXE) begin
eret_handling <= 1'b1;
end
end
end
wire exe_control_invalid;
assign exe_control_invalid = ex_int_handling&PC_ID_EXE!=32'hbfc00380 | eret_handling&PC_ID_EXE!=epc_value;
always @ (posedge clk) begin
if (rst) begin
{ MemEn_EXE_MEM, MemToReg_EXE_MEM, MemWrite_EXE_MEM, RegWrite_EXE_MEM,
RegWaddr_EXE_MEM, MULT_EXE_MEM, MFHL_EXE_MEM, MTHL_EXE_MEM,
LB_EXE_MEM, LBU_EXE_MEM, LH_EXE_MEM, LHU_EXE_MEM,
LW_EXE_MEM, mfc0_EXE_MEM, ALUResult_EXE_MEM, MemWdata_EXE_MEM,
PC_EXE_MEM, RegRdata1_EXE_MEM, RegRdata2_EXE_MEM, cp0Rdata_EXE_MEM,
s_vaddr_EXE_MEM, s_size_EXE_MEM
} <= 'd0;
end
else if (exe_to_mem_valid && mem_allowin) begin
MemWrite_EXE_MEM <= MemWrite_Final & {4{~(exe_control_invalid)}};
MemEn_EXE_MEM <= MemEn_ID_EXE & ~(exe_control_invalid);
MemToReg_EXE_MEM <= MemToReg_ID_EXE & ~(exe_control_invalid);
RegWrite_EXE_MEM <= RegWrite_ID_EXE & {4{~(exe_control_invalid)}};
MULT_EXE_MEM <= MULT_ID_EXE & {2{~(exe_control_invalid)}};
MFHL_EXE_MEM <= MFHL_ID_EXE & {2{~(exe_control_invalid)}};
MTHL_EXE_MEM <= MTHL_ID_EXE & {2{~(exe_control_invalid)}};
LB_EXE_MEM <= LB_ID_EXE & ~(exe_control_invalid);
LBU_EXE_MEM <= LBU_ID_EXE & ~(exe_control_invalid);
LH_EXE_MEM <= LH_ID_EXE & ~(exe_control_invalid);
LHU_EXE_MEM <= LHU_ID_EXE & ~(exe_control_invalid);
LW_EXE_MEM <= LW_ID_EXE & {2{~(exe_control_invalid)}};
mfc0_EXE_MEM <= mfc0_ID_EXE & ~(exe_control_invalid);
RegWaddr_EXE_MEM <= RegWaddr_EXE;
ALUResult_EXE_MEM <= ALUResult_EXE;
MemWdata_EXE_MEM <= MemWdata;
PC_EXE_MEM <= PC_ID_EXE;
RegRdata1_EXE_MEM <= RegRdata1_ID_EXE;
RegRdata2_EXE_MEM <= RegRdata2_ID_EXE;
cp0Rdata_EXE_MEM <= cp0Rdata_EXE;
s_vaddr_EXE_MEM <= vaddr_final;
s_size_EXE_MEM <= s_size;
end
end
MUX_4_32 ALUA_MUX(
.Src1 (RegRdata1_ID_EXE),
.Src2 ( PC_add_4_ID_EXE),
.Src3 ( Sa_ID_EXE),
.Src4 ( 32'd0),
.op ( ALUSrcA_ID_EXE),
.Result ( ALUA)
);
MUX_4_32 ALUB_MUX(
.Src1 (RegRdata2_ID_EXE),
.Src2 (SgnExtend_ID_EXE),
.Src3 ( 32'd4),
.Src4 ( ZExtend_ID_EXE),
.op ( ALUSrcB_ID_EXE),
.Result ( ALUB)
);
ALU ALU(
.A ( ALUA),
.B ( ALUB),
.is_signed (is_signed_ID_EXE),
.ALUop ( ALUop_ID_EXE),
.Overflow ( AOverflow),
.CarryOut ( ACarryOut),
.Zero ( AZero),
.Result ( ALUResult_EXE)
);
MemWrite_Sel MemW (
.MemWrite_ID_EXE ( MemWrite_ID_EXE),
.SB_ID_EXE ( SB_ID_EXE),
.SH_ID_EXE ( SH_ID_EXE),
.SW_ID_EXE ( SW_ID_EXE),
.vaddr ( ALUResult_EXE[1:0]),
.MemWrite ( MemWrite_Final)
);
Store_sel Store (
.vaddr ( ALUResult_EXE[1:0]),
.SW ( SW_ID_EXE),
.SB ( SB_ID_EXE),
.SH ( SH_ID_EXE),
.Rt_read_data ( RegRdata2_ID_EXE),
.MemWdata ( MemWdata),
.vaddr_final ( vaddr_final),
.s_size ( s_size)
);
Addr_error ADELS(
.is_lh (LH_ID_EXE|LHU_ID_EXE),
.is_lw ( &LW_ID_EXE),
.is_sh ( SH_ID_EXE),
.is_sw ( &SW_ID_EXE),
.address ( ALUResult_EXE[1:0]),
.AdEL_EXE ( AdEL_EXE),
.AdES_EXE ( AdES_EXE)
);
endmodule | module execute_stage(
input wire clk,
input wire rst,
input wire [31:0] PC_add_4_ID_EXE,
input wire [31:0] PC_ID_EXE,
input wire [31:0] RegRdata1_ID_EXE,
input wire [31:0] RegRdata2_ID_EXE,
input wire [31:0] Sa_ID_EXE,
input wire [31:0] SgnExtend_ID_EXE,
input wire [31:0] ZExtend_ID_EXE,
input wire [ 4:0] RegWaddr_ID_EXE,
input wire DSI_ID_EXE,
input wire [ 3:0] Exc_vec_ID_EXE,
input wire cp0_Write_ID_EXE,
input eret_ID_EXE,
input wire MemEn_ID_EXE,
input wire is_signed_ID_EXE,
input wire MemToReg_ID_EXE,
input wire [ 1:0] ALUSrcA_ID_EXE,
input wire [ 1:0] ALUSrcB_ID_EXE,
input wire [ 3:0] ALUop_ID_EXE,
input wire [ 3:0] MemWrite_ID_EXE,
input wire [ 3:0] RegWrite_ID_EXE,
input wire [ 1:0] MULT_ID_EXE,
input [ 1:0] DIV_ID_EXE,
input wire [ 1:0] MFHL_ID_EXE,
input wire [ 1:0] MTHL_ID_EXE,
input wire LB_ID_EXE,
input wire LBU_ID_EXE,
input wire LH_ID_EXE,
input wire LHU_ID_EXE,
input wire [ 1:0] LW_ID_EXE,
input wire [ 1:0] SW_ID_EXE,
input wire SB_ID_EXE,
input wire SH_ID_EXE,
output [ 1:0] DIV_EXE,
output [ 1:0] MULT_EXE,
output reg MemEn_EXE_MEM,
output reg MemToReg_EXE_MEM,
output reg [ 3:0] MemWrite_EXE_MEM,
output reg [ 3:0] RegWrite_EXE_MEM,
output reg [ 1:0] MULT_EXE_MEM,
output reg [ 1:0] MFHL_EXE_MEM,
output reg [ 1:0] MTHL_EXE_MEM,
output reg LB_EXE_MEM,
output reg LBU_EXE_MEM,
output reg LH_EXE_MEM,
output reg LHU_EXE_MEM,
output reg [ 1:0] LW_EXE_MEM,
output reg [ 4:0] RegWaddr_EXE_MEM,
output reg [31:0] ALUResult_EXE_MEM,
output reg [31:0] MemWdata_EXE_MEM,
output reg [31:0] PC_EXE_MEM,
output reg [31:0] RegRdata1_EXE_MEM,
output reg [31:0] RegRdata2_EXE_MEM,
output reg [ 1:0] s_vaddr_EXE_MEM,
output reg [ 2:0] s_size_EXE_MEM,
output wire [31:0] Bypass_EXE,
input wire [ 4:0] Rd_ID_EXE,
input wire mfc0_ID_EXE,
output reg [31:0] cp0Rdata_EXE_MEM,
output reg mfc0_EXE_MEM,
output cp0_Write_EXE,
output wire [31:0] Exc_BadVaddr,
output wire [31:0] Exc_EPC ,
output wire Exc_BD,
output wire [ 6:0] Exc_Vec,
input wire [31:0] cp0Rdata_EXE,
input wire ex_int_handle,
output reg ex_int_handling,
output reg eret_handling,
input mem_allowin,
input de_to_exe_valid,
output exe_allowin,
output exe_to_mem_valid,
output exe_stage_valid,
input ID_EXE_Stall,
output exe_ready_go,
input [31:0] epc_value,
input [31:0] PC
); |
reg exe_valid;
assign exe_ready_go = !(ex_int_handle&&PC!=32'hbfc00380);
assign exe_allowin = !exe_valid || exe_ready_go && mem_allowin;
assign exe_to_mem_valid = exe_valid && exe_ready_go;
always @ (posedge clk) begin
if (rst) begin
exe_valid <= 1'b0;
end
else if (exe_allowin) begin
exe_valid <= de_to_exe_valid;
end
end
assign exe_stage_valid = exe_valid;
wire AdEL_EXE,AdES_EXE;
wire ACarryOut,AOverflow,AZero;
wire [31:0] ALUA,ALUB;
wire [ 4:0] RegWaddr_EXE;
wire [31:0] ALUResult_EXE,BadVaddr_EXE;
wire [ 3:0] MemWrite_Final;
wire [31:0] MemWdata;
wire [ 1:0] vaddr_final;
wire [ 2:0] s_size;
assign cp0_Write_EXE = cp0_Write_ID_EXE & ~(ex_int_handling|eret_handling);
assign MULT_EXE = MULT_ID_EXE & {2{~(ex_int_handling|eret_handling)}};
assign DIV_EXE = DIV_ID_EXE & {2{~(ex_int_handling|eret_handling)}};
assign BadVaddr_EXE = ALUResult_EXE & {32{AdEL_EXE|AdES_EXE}};
assign Exc_BadVaddr = Exc_vec_ID_EXE[3] ? PC_ID_EXE : BadVaddr_EXE;
assign Exc_EPC = DSI_ID_EXE ? PC_ID_EXE - 32'd4: PC_ID_EXE;
assign Exc_Vec = {Exc_vec_ID_EXE[3:2], AOverflow,
Exc_vec_ID_EXE[1:0], AdEL_EXE,AdES_EXE};
assign RegWaddr_EXE = RegWaddr_ID_EXE;
assign Bypass_EXE = mfc0_ID_EXE ? cp0Rdata_EXE : ALUResult_EXE;
assign Exc_BD = DSI_ID_EXE;
always @ (posedge clk) begin
if (rst) begin
ex_int_handling <= 1'b0;
eret_handling <= 1'b0;
end
else begin
if (PC_ID_EXE==32'hbfc00380) begin
ex_int_handling <= 1'b0;
end
else if (ex_int_handle) begin
ex_int_handling <= 1'b1;
end
if (PC_ID_EXE==epc_value) begin
eret_handling <= 1'b0;
end
else if (eret_ID_EXE) begin
eret_handling <= 1'b1;
end
end
end
wire exe_control_invalid;
assign exe_control_invalid = ex_int_handling&PC_ID_EXE!=32'hbfc00380 | eret_handling&PC_ID_EXE!=epc_value;
always @ (posedge clk) begin
if (rst) begin
{ MemEn_EXE_MEM, MemToReg_EXE_MEM, MemWrite_EXE_MEM, RegWrite_EXE_MEM,
RegWaddr_EXE_MEM, MULT_EXE_MEM, MFHL_EXE_MEM, MTHL_EXE_MEM,
LB_EXE_MEM, LBU_EXE_MEM, LH_EXE_MEM, LHU_EXE_MEM,
LW_EXE_MEM, mfc0_EXE_MEM, ALUResult_EXE_MEM, MemWdata_EXE_MEM,
PC_EXE_MEM, RegRdata1_EXE_MEM, RegRdata2_EXE_MEM, cp0Rdata_EXE_MEM,
s_vaddr_EXE_MEM, s_size_EXE_MEM
} <= 'd0;
end
else if (exe_to_mem_valid && mem_allowin) begin
MemWrite_EXE_MEM <= MemWrite_Final & {4{~(exe_control_invalid)}};
MemEn_EXE_MEM <= MemEn_ID_EXE & ~(exe_control_invalid);
MemToReg_EXE_MEM <= MemToReg_ID_EXE & ~(exe_control_invalid);
RegWrite_EXE_MEM <= RegWrite_ID_EXE & {4{~(exe_control_invalid)}};
MULT_EXE_MEM <= MULT_ID_EXE & {2{~(exe_control_invalid)}};
MFHL_EXE_MEM <= MFHL_ID_EXE & {2{~(exe_control_invalid)}};
MTHL_EXE_MEM <= MTHL_ID_EXE & {2{~(exe_control_invalid)}};
LB_EXE_MEM <= LB_ID_EXE & ~(exe_control_invalid);
LBU_EXE_MEM <= LBU_ID_EXE & ~(exe_control_invalid);
LH_EXE_MEM <= LH_ID_EXE & ~(exe_control_invalid);
LHU_EXE_MEM <= LHU_ID_EXE & ~(exe_control_invalid);
LW_EXE_MEM <= LW_ID_EXE & {2{~(exe_control_invalid)}};
mfc0_EXE_MEM <= mfc0_ID_EXE & ~(exe_control_invalid);
RegWaddr_EXE_MEM <= RegWaddr_EXE;
ALUResult_EXE_MEM <= ALUResult_EXE;
MemWdata_EXE_MEM <= MemWdata;
PC_EXE_MEM <= PC_ID_EXE;
RegRdata1_EXE_MEM <= RegRdata1_ID_EXE;
RegRdata2_EXE_MEM <= RegRdata2_ID_EXE;
cp0Rdata_EXE_MEM <= cp0Rdata_EXE;
s_vaddr_EXE_MEM <= vaddr_final;
s_size_EXE_MEM <= s_size;
end
end
MUX_4_32 ALUA_MUX(
.Src1 (RegRdata1_ID_EXE),
.Src2 ( PC_add_4_ID_EXE),
.Src3 ( Sa_ID_EXE),
.Src4 ( 32'd0),
.op ( ALUSrcA_ID_EXE),
.Result ( ALUA)
);
MUX_4_32 ALUB_MUX(
.Src1 (RegRdata2_ID_EXE),
.Src2 (SgnExtend_ID_EXE),
.Src3 ( 32'd4),
.Src4 ( ZExtend_ID_EXE),
.op ( ALUSrcB_ID_EXE),
.Result ( ALUB)
);
ALU ALU(
.A ( ALUA),
.B ( ALUB),
.is_signed (is_signed_ID_EXE),
.ALUop ( ALUop_ID_EXE),
.Overflow ( AOverflow),
.CarryOut ( ACarryOut),
.Zero ( AZero),
.Result ( ALUResult_EXE)
);
MemWrite_Sel MemW (
.MemWrite_ID_EXE ( MemWrite_ID_EXE),
.SB_ID_EXE ( SB_ID_EXE),
.SH_ID_EXE ( SH_ID_EXE),
.SW_ID_EXE ( SW_ID_EXE),
.vaddr ( ALUResult_EXE[1:0]),
.MemWrite ( MemWrite_Final)
);
Store_sel Store (
.vaddr ( ALUResult_EXE[1:0]),
.SW ( SW_ID_EXE),
.SB ( SB_ID_EXE),
.SH ( SH_ID_EXE),
.Rt_read_data ( RegRdata2_ID_EXE),
.MemWdata ( MemWdata),
.vaddr_final ( vaddr_final),
.s_size ( s_size)
);
Addr_error ADELS(
.is_lh (LH_ID_EXE|LHU_ID_EXE),
.is_lw ( &LW_ID_EXE),
.is_sh ( SH_ID_EXE),
.is_sw ( &SW_ID_EXE),
.address ( ALUResult_EXE[1:0]),
.AdEL_EXE ( AdEL_EXE),
.AdES_EXE ( AdES_EXE)
);
endmodule | 0 |
4,897 | data/full_repos/permissive/112219256/execute_stage.v | 112,219,256 | execute_stage.v | v | 460 | 111 | [] | [] | [] | [(11, 300), (305, 323), (325, 362), (364, 438), (440, 459)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/112219256/execute_stage.v:305: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'execute_stage\'\nmodule execute_stage(\n ^~~~~~~~~~~~~\n : ... Top module \'MUX_3_5\'\nmodule MUX_3_5(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112219256/execute_stage.v:409: Operator NOT expects 3 bits on the LHS, but LHS\'s VARREF \'vaddr\' generates 2 bits.\n : ... In instance execute_stage.Store\n assign size_r = &(~vaddr) ? 3\'b010 : ~vaddr; \n ^\n%Error: data/full_repos/permissive/112219256/execute_stage.v:241: Cannot find file containing module: \'MUX_4_32\'\n MUX_4_32 ALUA_MUX(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.v\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.sv\n MUX_4_32\n MUX_4_32.v\n MUX_4_32.sv\n obj_dir/MUX_4_32\n obj_dir/MUX_4_32.v\n obj_dir/MUX_4_32.sv\n%Error: data/full_repos/permissive/112219256/execute_stage.v:250: Cannot find file containing module: \'MUX_4_32\'\n MUX_4_32 ALUB_MUX(\n ^~~~~~~~\n%Error: data/full_repos/permissive/112219256/execute_stage.v:259: Cannot find file containing module: \'ALU\'\n ALU ALU(\n ^~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n' | 3,307 | module | module MUX_3_5(
input [4:0] Src1,
input [4:0] Src2,
input [4:0] Src3,
input [1:0] op,
output [4:0] Result
);
wire [4:0] and1, and2, and3, op1, op1x, op0, op0x;
assign op1 = {5{ op[1]}};
assign op1x = {5{~op[1]}};
assign op0 = {5{ op[0]}};
assign op0x = {5{~op[0]}};
assign and1 = Src1 & op1x & op0x;
assign and2 = Src2 & op1x & op0;
assign and3 = Src3 & op1 & op0x;
assign Result = and1 | and2 | and3;
endmodule | module MUX_3_5(
input [4:0] Src1,
input [4:0] Src2,
input [4:0] Src3,
input [1:0] op,
output [4:0] Result
); |
wire [4:0] and1, and2, and3, op1, op1x, op0, op0x;
assign op1 = {5{ op[1]}};
assign op1x = {5{~op[1]}};
assign op0 = {5{ op[0]}};
assign op0x = {5{~op[0]}};
assign and1 = Src1 & op1x & op0x;
assign and2 = Src2 & op1x & op0;
assign and3 = Src3 & op1 & op0x;
assign Result = and1 | and2 | and3;
endmodule | 0 |
4,898 | data/full_repos/permissive/112219256/execute_stage.v | 112,219,256 | execute_stage.v | v | 460 | 111 | [] | [] | [] | [(11, 300), (305, 323), (325, 362), (364, 438), (440, 459)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/112219256/execute_stage.v:305: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'execute_stage\'\nmodule execute_stage(\n ^~~~~~~~~~~~~\n : ... Top module \'MUX_3_5\'\nmodule MUX_3_5(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112219256/execute_stage.v:409: Operator NOT expects 3 bits on the LHS, but LHS\'s VARREF \'vaddr\' generates 2 bits.\n : ... In instance execute_stage.Store\n assign size_r = &(~vaddr) ? 3\'b010 : ~vaddr; \n ^\n%Error: data/full_repos/permissive/112219256/execute_stage.v:241: Cannot find file containing module: \'MUX_4_32\'\n MUX_4_32 ALUA_MUX(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.v\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.sv\n MUX_4_32\n MUX_4_32.v\n MUX_4_32.sv\n obj_dir/MUX_4_32\n obj_dir/MUX_4_32.v\n obj_dir/MUX_4_32.sv\n%Error: data/full_repos/permissive/112219256/execute_stage.v:250: Cannot find file containing module: \'MUX_4_32\'\n MUX_4_32 ALUB_MUX(\n ^~~~~~~~\n%Error: data/full_repos/permissive/112219256/execute_stage.v:259: Cannot find file containing module: \'ALU\'\n ALU ALU(\n ^~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n' | 3,307 | module | module MemWrite_Sel(
input [3:0] MemWrite_ID_EXE,
input [1:0] SW_ID_EXE,
input SB_ID_EXE,
input SH_ID_EXE,
input [1:0] vaddr,
output [3:0] MemWrite
);
wire [3:0] MemW_L, MemW_R, MemW_SB, MemW_SH;
wire [3:0] v;
assign MemW_L[3] = &vaddr;
assign MemW_L[2] = vaddr[1];
assign MemW_L[1] = |vaddr;
assign MemW_L[0] = 1'b1;
assign MemW_R[3] = 1'b1;
assign MemW_R[2] = ~(&vaddr);
assign MemW_R[1] = ~vaddr[1];
assign MemW_R[0] = ~(|vaddr);
assign v[3] = vaddr[1] & vaddr[0];
assign v[2] = vaddr[1] & ~vaddr[0];
assign v[1] = ~vaddr[1] & vaddr[0];
assign v[0] = ~vaddr[1] & ~vaddr[0];
assign MemW_SB = ({4{v[0]}} & 4'b0001 | {4{v[1]}} & 4'b0010) |
({4{v[2]}} & 4'b0100 | {4{v[3]}} & 4'b1000) ;
assign MemW_SH = ({4{v[0]}} & 4'b0011) | ({4{v[2]}} & 4'b1100);
assign MemWrite = ( SW_ID_EXE[1] &~SW_ID_EXE[0]) ? MemW_L :
(~SW_ID_EXE[1] & SW_ID_EXE[0]) ? MemW_R :
( SW_ID_EXE[1] & SW_ID_EXE[0]) ? MemWrite_ID_EXE :
SB_ID_EXE ? MemW_SB :
SH_ID_EXE ? MemW_SH : MemWrite_ID_EXE;
endmodule | module MemWrite_Sel(
input [3:0] MemWrite_ID_EXE,
input [1:0] SW_ID_EXE,
input SB_ID_EXE,
input SH_ID_EXE,
input [1:0] vaddr,
output [3:0] MemWrite
); |
wire [3:0] MemW_L, MemW_R, MemW_SB, MemW_SH;
wire [3:0] v;
assign MemW_L[3] = &vaddr;
assign MemW_L[2] = vaddr[1];
assign MemW_L[1] = |vaddr;
assign MemW_L[0] = 1'b1;
assign MemW_R[3] = 1'b1;
assign MemW_R[2] = ~(&vaddr);
assign MemW_R[1] = ~vaddr[1];
assign MemW_R[0] = ~(|vaddr);
assign v[3] = vaddr[1] & vaddr[0];
assign v[2] = vaddr[1] & ~vaddr[0];
assign v[1] = ~vaddr[1] & vaddr[0];
assign v[0] = ~vaddr[1] & ~vaddr[0];
assign MemW_SB = ({4{v[0]}} & 4'b0001 | {4{v[1]}} & 4'b0010) |
({4{v[2]}} & 4'b0100 | {4{v[3]}} & 4'b1000) ;
assign MemW_SH = ({4{v[0]}} & 4'b0011) | ({4{v[2]}} & 4'b1100);
assign MemWrite = ( SW_ID_EXE[1] &~SW_ID_EXE[0]) ? MemW_L :
(~SW_ID_EXE[1] & SW_ID_EXE[0]) ? MemW_R :
( SW_ID_EXE[1] & SW_ID_EXE[0]) ? MemWrite_ID_EXE :
SB_ID_EXE ? MemW_SB :
SH_ID_EXE ? MemW_SH : MemWrite_ID_EXE;
endmodule | 0 |
4,899 | data/full_repos/permissive/112219256/execute_stage.v | 112,219,256 | execute_stage.v | v | 460 | 111 | [] | [] | [] | [(11, 300), (305, 323), (325, 362), (364, 438), (440, 459)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/112219256/execute_stage.v:305: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'execute_stage\'\nmodule execute_stage(\n ^~~~~~~~~~~~~\n : ... Top module \'MUX_3_5\'\nmodule MUX_3_5(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112219256/execute_stage.v:409: Operator NOT expects 3 bits on the LHS, but LHS\'s VARREF \'vaddr\' generates 2 bits.\n : ... In instance execute_stage.Store\n assign size_r = &(~vaddr) ? 3\'b010 : ~vaddr; \n ^\n%Error: data/full_repos/permissive/112219256/execute_stage.v:241: Cannot find file containing module: \'MUX_4_32\'\n MUX_4_32 ALUA_MUX(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.v\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.sv\n MUX_4_32\n MUX_4_32.v\n MUX_4_32.sv\n obj_dir/MUX_4_32\n obj_dir/MUX_4_32.v\n obj_dir/MUX_4_32.sv\n%Error: data/full_repos/permissive/112219256/execute_stage.v:250: Cannot find file containing module: \'MUX_4_32\'\n MUX_4_32 ALUB_MUX(\n ^~~~~~~~\n%Error: data/full_repos/permissive/112219256/execute_stage.v:259: Cannot find file containing module: \'ALU\'\n ALU ALU(\n ^~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n' | 3,307 | module | module Store_sel(
input wire [ 1:0] vaddr,
input wire [ 1:0] SW,
input wire SB,
input wire SH,
input wire [31:0] Rt_read_data,
output wire [31:0] MemWdata,
output wire [ 1:0] vaddr_final,
output wire [ 2:0] s_size
);
wire swr = SW[0] & ~SW[1];
wire swl = SW[1] & ~SW[0];
wire sw = &SW;
wire [3:0] v;
wire [1:0] swl_vaddr, swr_vaddr;
wire [2:0] size_l, size_r;
wire [31:0] swr_1,swr_2,swr_3,swr_4,swr_data;
wire [31:0] swl_1,swl_2,swl_3,swl_4,swl_data;
wire [31:0] sb_data, sh_data;
assign v[3] = vaddr[1] & vaddr[0];
assign v[2] = vaddr[1] & ~vaddr[0];
assign v[1] = ~vaddr[1] & vaddr[0];
assign v[0] = ~vaddr[1] & ~vaddr[0];
assign swl_1 = {24'd0,Rt_read_data[31:24]};
assign swl_2 = {16'd0,Rt_read_data[31:16]};
assign swl_3 = { 8'd0,Rt_read_data[31: 8]};
assign swl_4 = Rt_read_data;
assign swl_vaddr = 2'b00;
assign size_l = |vaddr ? {1'b0,vaddr} : 3'b010;
assign swl_data = (({32{v[0]}} & swl_1) | ({32{v[1]}} & swl_2)) |
(({32{v[2]}} & swl_3) | ({32{v[3]}} & swl_4)) ;
assign swr_1 = Rt_read_data;
assign swr_2 = {Rt_read_data[23:0], 8'd0};
assign swr_3 = {Rt_read_data[15:0],16'd0};
assign swr_4 = {Rt_read_data[ 7:0],24'd0};
assign swr_vaddr = v[1] ? 2'b00 : vaddr;
assign size_r = &(~vaddr) ? 3'b010 : ~vaddr;
assign swr_data = (({32{v[0]}} & swr_1) | ({32{v[1]}} & swr_2)) |
(({32{v[2]}} & swr_3) | ({32{v[3]}} & swr_4)) ;
assign sb_data = ({32{v[0]}} & {24'd0,Rt_read_data[7:0] } |
{32{v[1]}} & {16'd0,Rt_read_data[7:0], 8'd0} )
|
({32{v[2]}} & { 8'd0,Rt_read_data[7:0],16'd0} |
{32{v[3]}} & { Rt_read_data[7:0],24'd0} ) ;
assign sh_data = {32{v[0]}} & {16'd0,Rt_read_data[15:0] } |
{32{v[2]}} & { Rt_read_data[15:0],16'd0} ;
assign MemWdata = (({32{sw }} & Rt_read_data) |
({32{swl}} & swl_data )) |
(({32{swr}} & swr_data ) |
({32{SB }} & sb_data )) |
({32{SH }} & sh_data ) ;
assign vaddr_final = {2{sw }} & vaddr |
{2{SH }} & vaddr |
{2{SB }} & vaddr |
{2{swl}} & swl_vaddr |
{2{swr}} & swr_vaddr ;
assign s_size = {3{sw }} & 3'b010 |
{3{SB }} & 3'b000 |
{3{SH }} & 3'b001 |
{3{swl}} & size_l |
{3{swr}} & size_r ;
endmodule | module Store_sel(
input wire [ 1:0] vaddr,
input wire [ 1:0] SW,
input wire SB,
input wire SH,
input wire [31:0] Rt_read_data,
output wire [31:0] MemWdata,
output wire [ 1:0] vaddr_final,
output wire [ 2:0] s_size
); |
wire swr = SW[0] & ~SW[1];
wire swl = SW[1] & ~SW[0];
wire sw = &SW;
wire [3:0] v;
wire [1:0] swl_vaddr, swr_vaddr;
wire [2:0] size_l, size_r;
wire [31:0] swr_1,swr_2,swr_3,swr_4,swr_data;
wire [31:0] swl_1,swl_2,swl_3,swl_4,swl_data;
wire [31:0] sb_data, sh_data;
assign v[3] = vaddr[1] & vaddr[0];
assign v[2] = vaddr[1] & ~vaddr[0];
assign v[1] = ~vaddr[1] & vaddr[0];
assign v[0] = ~vaddr[1] & ~vaddr[0];
assign swl_1 = {24'd0,Rt_read_data[31:24]};
assign swl_2 = {16'd0,Rt_read_data[31:16]};
assign swl_3 = { 8'd0,Rt_read_data[31: 8]};
assign swl_4 = Rt_read_data;
assign swl_vaddr = 2'b00;
assign size_l = |vaddr ? {1'b0,vaddr} : 3'b010;
assign swl_data = (({32{v[0]}} & swl_1) | ({32{v[1]}} & swl_2)) |
(({32{v[2]}} & swl_3) | ({32{v[3]}} & swl_4)) ;
assign swr_1 = Rt_read_data;
assign swr_2 = {Rt_read_data[23:0], 8'd0};
assign swr_3 = {Rt_read_data[15:0],16'd0};
assign swr_4 = {Rt_read_data[ 7:0],24'd0};
assign swr_vaddr = v[1] ? 2'b00 : vaddr;
assign size_r = &(~vaddr) ? 3'b010 : ~vaddr;
assign swr_data = (({32{v[0]}} & swr_1) | ({32{v[1]}} & swr_2)) |
(({32{v[2]}} & swr_3) | ({32{v[3]}} & swr_4)) ;
assign sb_data = ({32{v[0]}} & {24'd0,Rt_read_data[7:0] } |
{32{v[1]}} & {16'd0,Rt_read_data[7:0], 8'd0} )
|
({32{v[2]}} & { 8'd0,Rt_read_data[7:0],16'd0} |
{32{v[3]}} & { Rt_read_data[7:0],24'd0} ) ;
assign sh_data = {32{v[0]}} & {16'd0,Rt_read_data[15:0] } |
{32{v[2]}} & { Rt_read_data[15:0],16'd0} ;
assign MemWdata = (({32{sw }} & Rt_read_data) |
({32{swl}} & swl_data )) |
(({32{swr}} & swr_data ) |
({32{SB }} & sb_data )) |
({32{SH }} & sh_data ) ;
assign vaddr_final = {2{sw }} & vaddr |
{2{SH }} & vaddr |
{2{SB }} & vaddr |
{2{swl}} & swl_vaddr |
{2{swr}} & swr_vaddr ;
assign s_size = {3{sw }} & 3'b010 |
{3{SB }} & 3'b000 |
{3{SH }} & 3'b001 |
{3{swl}} & size_l |
{3{swr}} & size_r ;
endmodule | 0 |
4,900 | data/full_repos/permissive/112219256/execute_stage.v | 112,219,256 | execute_stage.v | v | 460 | 111 | [] | [] | [] | [(11, 300), (305, 323), (325, 362), (364, 438), (440, 459)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/112219256/execute_stage.v:305: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'execute_stage\'\nmodule execute_stage(\n ^~~~~~~~~~~~~\n : ... Top module \'MUX_3_5\'\nmodule MUX_3_5(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112219256/execute_stage.v:409: Operator NOT expects 3 bits on the LHS, but LHS\'s VARREF \'vaddr\' generates 2 bits.\n : ... In instance execute_stage.Store\n assign size_r = &(~vaddr) ? 3\'b010 : ~vaddr; \n ^\n%Error: data/full_repos/permissive/112219256/execute_stage.v:241: Cannot find file containing module: \'MUX_4_32\'\n MUX_4_32 ALUA_MUX(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.v\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.sv\n MUX_4_32\n MUX_4_32.v\n MUX_4_32.sv\n obj_dir/MUX_4_32\n obj_dir/MUX_4_32.v\n obj_dir/MUX_4_32.sv\n%Error: data/full_repos/permissive/112219256/execute_stage.v:250: Cannot find file containing module: \'MUX_4_32\'\n MUX_4_32 ALUB_MUX(\n ^~~~~~~~\n%Error: data/full_repos/permissive/112219256/execute_stage.v:259: Cannot find file containing module: \'ALU\'\n ALU ALU(\n ^~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n' | 3,307 | module | module Addr_error(
input wire is_lh ,
input wire is_lw ,
input wire is_sh ,
input wire is_sw ,
input wire [ 1:0] address ,
output wire AdEL_EXE,
output wire AdES_EXE
);
wire AdEL_LH, AdEL_LW, AdES_SH, AdES_SW;
assign AdEL_LH = address[0] & is_lh;
assign AdEL_LW = (|address) & is_lw;
assign AdES_SH = address[0] & is_sh;
assign AdES_SW = (|address) & is_sw;
assign AdEL_EXE = AdEL_LH | AdEL_LW;
assign AdES_EXE = AdES_SH | AdES_SW;
endmodule | module Addr_error(
input wire is_lh ,
input wire is_lw ,
input wire is_sh ,
input wire is_sw ,
input wire [ 1:0] address ,
output wire AdEL_EXE,
output wire AdES_EXE
); |
wire AdEL_LH, AdEL_LW, AdES_SH, AdES_SW;
assign AdEL_LH = address[0] & is_lh;
assign AdEL_LW = (|address) & is_lw;
assign AdES_SH = address[0] & is_sh;
assign AdES_SW = (|address) & is_sw;
assign AdEL_EXE = AdEL_LH | AdEL_LW;
assign AdES_EXE = AdES_SH | AdES_SW;
endmodule | 0 |
4,901 | data/full_repos/permissive/112219256/fetch_stage.v | 112,219,256 | fetch_stage.v | v | 117 | 113 | [] | [] | [] | [(12, 115)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/112219256/fetch_stage.v:104: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'IR_buffer\' generates 33 bits.\n : ... In instance fetch_stage\n IR <= IR_buffer;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 3,308 | module | module fetch_stage(
input wire clk,
input wire rst,
input wire DSI_ID,
input wire IRWrite,
input wire PC_AdEL,
input [31:0] PC_buffer,
output reg [31:0] PC_IF_ID,
output reg [31:0] PC_add_4_IF_ID,
output [31:0] IR_IF_ID,
output reg PC_AdEL_IF_ID,
output reg DSI_IF_ID,
input [ 1:0] data_r_req,
output fetch_axi_rready ,
input fetch_axi_rvalid ,
input [31:0] fetch_axi_rdata ,
input [ 3:0] fetch_axi_rid ,
input fetch_axi_arready,
input decode_allowin,
output fe_to_de_valid,
output IR_buffer_valid
);
parameter reset_addr = 32'hbfc00000;
reg [32:0] IR_buffer;
reg [31:0] IR;
wire fetch_allowin;
wire fetch_ready_go;
assign IR_IF_ID = IR;
assign fetch_axi_rready = decode_allowin || data_r_req!=2'd0;
wire fetch_valid;
assign IR_buffer_valid = IR_buffer[32];
assign fetch_valid = fetch_ready_go;
assign fetch_ready_go = fetch_axi_rvalid && fetch_axi_rid==4'd0 && data_r_req==2'd0 || IR_buffer_valid;
assign fe_to_de_valid = fetch_valid && fetch_ready_go;
always @(posedge clk) begin
if (rst) begin
IR <= 32'd0;
IR_buffer <= 33'd0;
PC_IF_ID <= 32'd0;
PC_add_4_IF_ID <= 32'd0;
PC_AdEL_IF_ID <= 1'd0;
DSI_IF_ID <= 1'd0;
end
else if (!IR_buffer_valid) begin
if (fetch_axi_rready&&fetch_axi_rvalid) begin
if (data_r_req==2'd0) begin
if (fetch_axi_rid==4'd0) begin
IR <= fetch_axi_rdata;
PC_IF_ID <= PC_buffer;
PC_add_4_IF_ID <= PC_buffer + 32'd4;
PC_AdEL_IF_ID <= PC_AdEL;
DSI_IF_ID <= DSI_ID;
end
end
else begin
if (fetch_axi_rid==4'd0) begin
IR_buffer <= {1'b1,fetch_axi_rdata};
end
end
end
end
else begin
if (decode_allowin&&IRWrite) begin
IR <= IR_buffer;
IR_buffer <= 33'd0;
PC_IF_ID <= PC_buffer;
PC_add_4_IF_ID <= PC_buffer + 32'd4;
PC_AdEL_IF_ID <= PC_AdEL;
DSI_IF_ID <= DSI_ID;
end
end
end
endmodule | module fetch_stage(
input wire clk,
input wire rst,
input wire DSI_ID,
input wire IRWrite,
input wire PC_AdEL,
input [31:0] PC_buffer,
output reg [31:0] PC_IF_ID,
output reg [31:0] PC_add_4_IF_ID,
output [31:0] IR_IF_ID,
output reg PC_AdEL_IF_ID,
output reg DSI_IF_ID,
input [ 1:0] data_r_req,
output fetch_axi_rready ,
input fetch_axi_rvalid ,
input [31:0] fetch_axi_rdata ,
input [ 3:0] fetch_axi_rid ,
input fetch_axi_arready,
input decode_allowin,
output fe_to_de_valid,
output IR_buffer_valid
); |
parameter reset_addr = 32'hbfc00000;
reg [32:0] IR_buffer;
reg [31:0] IR;
wire fetch_allowin;
wire fetch_ready_go;
assign IR_IF_ID = IR;
assign fetch_axi_rready = decode_allowin || data_r_req!=2'd0;
wire fetch_valid;
assign IR_buffer_valid = IR_buffer[32];
assign fetch_valid = fetch_ready_go;
assign fetch_ready_go = fetch_axi_rvalid && fetch_axi_rid==4'd0 && data_r_req==2'd0 || IR_buffer_valid;
assign fe_to_de_valid = fetch_valid && fetch_ready_go;
always @(posedge clk) begin
if (rst) begin
IR <= 32'd0;
IR_buffer <= 33'd0;
PC_IF_ID <= 32'd0;
PC_add_4_IF_ID <= 32'd0;
PC_AdEL_IF_ID <= 1'd0;
DSI_IF_ID <= 1'd0;
end
else if (!IR_buffer_valid) begin
if (fetch_axi_rready&&fetch_axi_rvalid) begin
if (data_r_req==2'd0) begin
if (fetch_axi_rid==4'd0) begin
IR <= fetch_axi_rdata;
PC_IF_ID <= PC_buffer;
PC_add_4_IF_ID <= PC_buffer + 32'd4;
PC_AdEL_IF_ID <= PC_AdEL;
DSI_IF_ID <= DSI_ID;
end
end
else begin
if (fetch_axi_rid==4'd0) begin
IR_buffer <= {1'b1,fetch_axi_rdata};
end
end
end
end
else begin
if (decode_allowin&&IRWrite) begin
IR <= IR_buffer;
IR_buffer <= 33'd0;
PC_IF_ID <= PC_buffer;
PC_add_4_IF_ID <= PC_buffer + 32'd4;
PC_AdEL_IF_ID <= PC_AdEL;
DSI_IF_ID <= DSI_ID;
end
end
end
endmodule | 0 |
4,902 | data/full_repos/permissive/112219256/HILO.v | 112,219,256 | HILO.v | v | 39 | 69 | [] | [] | [] | [(11, 38)] | null | data/verilator_xmls/bdf0417e-aa23-420e-a9fd-3a072ba48af1.xml | null | 3,309 | module | module HILO(
input clk,
input rst,
input [31:0] HI_in,
input [31:0] LO_in,
input [ 1:0] HILO_Write,
output [31:0] HI_out,
output [31:0] LO_out
);
reg [31:0] HI;
reg [31:0] LO;
always @ (posedge clk) begin
begin
if (HILO_Write[1]) HI <= HI_in;
else HI <= HI;
if (HILO_Write[0]) LO <= LO_in;
else LO <= LO;
end
end
assign HI_out = HI;
assign LO_out = LO;
endmodule | module HILO(
input clk,
input rst,
input [31:0] HI_in,
input [31:0] LO_in,
input [ 1:0] HILO_Write,
output [31:0] HI_out,
output [31:0] LO_out
); |
reg [31:0] HI;
reg [31:0] LO;
always @ (posedge clk) begin
begin
if (HILO_Write[1]) HI <= HI_in;
else HI <= HI;
if (HILO_Write[0]) LO <= LO_in;
else LO <= LO;
end
end
assign HI_out = HI;
assign LO_out = LO;
endmodule | 0 |
4,903 | data/full_repos/permissive/112219256/memory_stage.v | 112,219,256 | memory_stage.v | v | 643 | 126 | [] | [] | [] | [(11, 642)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/112219256/memory_stage.v:141: Little bit endian vector: MSB < LSB of bit range: 0:3\n reg [0:3] do_req_waddr;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/112219256/memory_stage.v:142: Little bit endian vector: MSB < LSB of bit range: 0:3\n reg [0:3] do_req_wdata;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/112219256/memory_stage.v:143: Little bit endian vector: MSB < LSB of bit range: 0:3\n wire [0:3] do_req_waddr_pos; \n ^\n%Warning-LITENDIAN: data/full_repos/permissive/112219256/memory_stage.v:144: Little bit endian vector: MSB < LSB of bit range: 0:3\n wire [0:3] do_req_wdata_pos; \n ^\n%Warning-LITENDIAN: data/full_repos/permissive/112219256/memory_stage.v:148: Little bit endian vector: MSB < LSB of bit range: 0:3\n reg [0:3] w_addr_rcv;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/112219256/memory_stage.v:149: Little bit endian vector: MSB < LSB of bit range: 0:3\n reg [0:3] w_data_rcv;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/112219256/memory_stage.v:155: Little bit endian vector: MSB < LSB of bit range: 0:3\n wire [0:3] w_data_back;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/112219256/memory_stage.v:167: Little bit endian vector: MSB < LSB of bit range: 0:3\n wire [0:3] data_in_ready_pos; \n ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:172: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'cpu_arid\' generates 4 bits.\n : ... In instance memory_stage\n assign arid = cpu_arid;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:193: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance memory_stage\n assign write_id_n = do_waddr_r[0][32]==1\'b0 ? 4\'d0 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:194: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance memory_stage\n do_waddr_r[1][32]==1\'b0 ? 4\'d1 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:195: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s CONST \'4\'h2\' generates 4 bits.\n : ... In instance memory_stage\n do_waddr_r[2][32]==1\'b0 ? 4\'d2 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:196: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s CONST \'4\'h3\' generates 4 bits.\n : ... In instance memory_stage\n do_waddr_r[3][32]==1\'b0 ? 4\'d3 : 4\'d4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:196: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'4\'h4\' generates 4 bits.\n : ... In instance memory_stage\n do_waddr_r[3][32]==1\'b0 ? 4\'d3 : 4\'d4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:204: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'write_id_n\' generates 5 bits.\n : ... In instance memory_stage\n do_write_id <= write_id_n;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:220: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'do_write_id\' generates 3 bits.\n : ... In instance memory_stage\n assign mem_axi_wid = do_write_id;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:226: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'do_write_id\' generates 3 bits.\n : ... In instance memory_stage\n assign mem_axi_awid = do_write_id;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:300: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h4\' generates 4 bits.\n : ... In instance memory_stage\n (write_id_n!=4\'d4 ? 2\'d2 : 2\'d1) \n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:303: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h4\' generates 4 bits.\n : ... In instance memory_stage\n (write_id_n!=4\'d4 ? 2\'d2 : data_w_req)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:328: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance memory_stage\n do_dsize_r[0] <= 3\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:329: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance memory_stage\n do_dsize_r[1] <= 3\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:330: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance memory_stage\n do_dsize_r[2] <= 3\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:331: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance memory_stage\n do_dsize_r[3] <= 3\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:342: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'mem_axi_awsize\' generates 3 bits.\n : ... In instance memory_stage\n do_dsize_r[0] <= mem_axi_awsize;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:335: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance memory_stage\n if (write_id_n==4\'d0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:351: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'mem_axi_awsize\' generates 3 bits.\n : ... In instance memory_stage\n do_dsize_r[1] <= mem_axi_awsize;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:344: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance memory_stage\n if (write_id_n==4\'d1) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:360: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'mem_axi_awsize\' generates 3 bits.\n : ... In instance memory_stage\n do_dsize_r[2] <= mem_axi_awsize;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:353: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n : ... In instance memory_stage\n if (write_id_n==4\'d2) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:369: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'mem_axi_awsize\' generates 3 bits.\n : ... In instance memory_stage\n do_dsize_r[3] <= mem_axi_awsize;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:362: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h3\' generates 4 bits.\n : ... In instance memory_stage\n if (write_id_n==4\'d3) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:388: Operator EQ expects 4 bits on the LHS, but LHS\'s VARREF \'arid\' generates 1 bits.\n : ... In instance memory_stage\n arvalid&&arready&&arid==4\'d1 ? 1\'b1 :\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:422: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance memory_stage\n if (write_id_n==3\'d0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:426: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n : ... In instance memory_stage\n if (write_id_n==3\'d1) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:430: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n : ... In instance memory_stage\n if (write_id_n==3\'d2) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:434: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n : ... In instance memory_stage\n if (write_id_n==3\'d3) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:608: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h4\' generates 4 bits.\n : ... In instance memory_stage\n assign data_w_req_pos = data_w_req==2\'d0 && write_req && write_id_n!=4\'d4 ||\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:609: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h4\' generates 4 bits.\n : ... In instance memory_stage\n data_w_req==2\'d1 && write_id_n!=4\'d4;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:613: Operator EQ expects 4 bits on the LHS, but LHS\'s VARREF \'arid\' generates 1 bits.\n : ... In instance memory_stage\n assign r_addr_rcv_pos = !r_addr_rcv && arvalid&&arready&&arid==4\'d1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:630: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance memory_stage\n assign do_req_waddr_pos[0] = !do_req_waddr[0] && data_w_req_pos && write_id_n==3\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:631: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n : ... In instance memory_stage\n assign do_req_waddr_pos[1] = !do_req_waddr[1] && data_w_req_pos && write_id_n==3\'d1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:632: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n : ... In instance memory_stage\n assign do_req_waddr_pos[2] = !do_req_waddr[2] && data_w_req_pos && write_id_n==3\'d2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:633: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n : ... In instance memory_stage\n assign do_req_waddr_pos[3] = !do_req_waddr[3] && data_w_req_pos && write_id_n==3\'d3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:635: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance memory_stage\n assign do_req_wdata_pos[0] = !do_req_wdata[0] && data_w_req_pos && write_id_n==3\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:636: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n : ... In instance memory_stage\n assign do_req_wdata_pos[1] = !do_req_wdata[1] && data_w_req_pos && write_id_n==3\'d1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:637: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n : ... In instance memory_stage\n assign do_req_wdata_pos[2] = !do_req_wdata[2] && data_w_req_pos && write_id_n==3\'d2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112219256/memory_stage.v:638: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n : ... In instance memory_stage\n assign do_req_wdata_pos[3] = !do_req_wdata[3] && data_w_req_pos && write_id_n==3\'d3;\n ^~\n%Error: Exiting due to 47 warning(s)\n' | 3,310 | module | module memory_stage(
input wire clk,
input wire rst,
input wire MemEn_EXE_MEM,
input wire MemToReg_EXE_MEM,
input wire [ 3:0] MemWrite_EXE_MEM,
input wire [ 3:0] RegWrite_EXE_MEM,
input wire [ 1:0] MFHL_EXE_MEM,
input wire LB_EXE_MEM,
input wire LBU_EXE_MEM,
input wire LH_EXE_MEM,
input wire LHU_EXE_MEM,
input wire [ 1:0] LW_EXE_MEM,
input wire [ 4:0] RegWaddr_EXE_MEM,
input wire [31:0] ALUResult_EXE_MEM,
input wire [31:0] MemWdata_EXE_MEM,
input wire [31:0] RegRdata2_EXE_MEM,
input wire [31:0] PC_EXE_MEM,
input wire [ 1:0] s_vaddr_EXE_MEM,
input wire [ 2:0] s_size_EXE_MEM,
input [ 1:0] MULT_EXE_MEM,
input [ 1:0] MTHL_EXE_MEM,
output [ 1:0] MULT_MEM,
output [ 1:0] MTHL_MEM,
output reg MemToReg_MEM_WB,
output reg [ 3:0] RegWrite_MEM_WB,
output reg [ 1:0] MFHL_MEM_WB,
output reg LB_MEM_WB,
output reg LBU_MEM_WB,
output reg LH_MEM_WB,
output reg LHU_MEM_WB,
output reg [ 1:0] LW_MEM_WB,
output reg [ 4:0] RegWaddr_MEM_WB,
output reg [31:0] ALUResult_MEM_WB,
output reg [31:0] RegRdata2_MEM_WB,
output reg [31:0] PC_MEM_WB,
output reg [31:0] MemRdata_MEM_WB,
output wire [31:0] Bypass_MEM,
input wire [31:0] cp0Rdata_EXE_MEM,
input wire mfc0_EXE_MEM,
output reg [31:0] cp0Rdata_MEM_WB,
output reg mfc0_MEM_WB,
input wb_allowin,
input exe_to_mem_valid,
output mem_allowin,
output mem_to_wb_valid,
output reg [ 1:0] data_r_req,
output reg do_req_raddr,
input [31:0] mem_axi_rdata,
input mem_axi_rvalid,
input [ 3:0] mem_axi_rid,
output mem_axi_rready,
output [ 3:0] mem_axi_arid,
output [31:0] mem_axi_araddr,
output [ 2:0] mem_axi_arsize,
input mem_axi_arready,
output mem_axi_arvalid,
output [ 3:0] mem_axi_awid,
output [31:0] mem_axi_awaddr,
output [ 2:0] mem_axi_awsize,
output mem_axi_awvalid,
input mem_axi_awready,
output [ 3:0] mem_axi_wid,
output [31:0] mem_axi_wdata,
output [ 3:0] mem_axi_wstrb,
output mem_axi_wvalid,
input mem_axi_wready,
output mem_axi_bready,
input [ 3:0] mem_axi_bid,
input mem_axi_bvalid,
input [ 3:0] cpu_arid,
output mem_read_req,
output mem_stage_valid
);
wire mem_ready_go;
reg mem_valid;
wire read_req;
wire write_req;
wire arvalid;
wire arready;
wire [3:0] rid;
reg rready;
wire rvalid;
reg awvalid;
wire awready;
reg wvalid;
wire wready;
wire bvalid;
wire bready;
wire [3:0] bid;
reg [1:0] data_w_req;
reg [0:3] do_req_waddr;
reg [0:3] do_req_wdata;
wire [0:3] do_req_waddr_pos;
wire [0:3] do_req_wdata_pos;
reg r_addr_rcv;
reg [0:3] w_addr_rcv;
reg [0:3] w_data_rcv;
reg [1:0] data_in_ready [0:3];
wire r_data_back;
wire [0:3] w_data_back;
reg [32:0] do_waddr_r [0:3];
reg [ 3:0] do_dsize_r [0:3];
wire [4:0] write_id_n;
wire pot_hazard;
wire data_w_req_pos;
wire data_r_req_pos;
wire r_addr_rcv_pos;
wire [0:3] data_in_ready_pos;
reg [2:0] do_write_id;
wire arid;
assign arid = cpu_arid;
assign mem_ready_go = (data_r_req==2'd0&&!read_req&&data_w_req==2'd0&&!write_req) ||
(data_r_req==2'd2&&r_data_back) ||
(data_w_req==2'd2&&(|data_in_ready_pos));
assign mem_allowin = !mem_valid || mem_ready_go && wb_allowin;
assign mem_to_wb_valid = mem_valid && mem_ready_go;
always @ (posedge clk) begin
if (rst) begin
mem_valid <= 1'b0;
end
else if (mem_allowin) begin
mem_valid <= exe_to_mem_valid;
end
end
assign mem_stage_valid = mem_valid;
assign write_id_n = do_waddr_r[0][32]==1'b0 ? 4'd0 :
do_waddr_r[1][32]==1'b0 ? 4'd1 :
do_waddr_r[2][32]==1'b0 ? 4'd2 :
do_waddr_r[3][32]==1'b0 ? 4'd3 : 4'd4;
always @ (posedge clk) begin
if (rst) begin
do_write_id <= 3'd0;
end
else
if (data_w_req_pos) begin
do_write_id <= write_id_n;
end
end
assign pot_hazard = mem_axi_araddr==(do_waddr_r[0][31:0]&32'hfffffffc) && do_waddr_r[0][32] ||
mem_axi_araddr==(do_waddr_r[1][31:0]&32'hfffffffc) && do_waddr_r[1][32] ||
mem_axi_araddr==(do_waddr_r[2][31:0]&32'hfffffffc) && do_waddr_r[2][32] ||
mem_axi_araddr==(do_waddr_r[3][31:0]&32'hfffffffc) && do_waddr_r[3][32] ;
assign Bypass_MEM = mfc0_EXE_MEM ?
cp0Rdata_EXE_MEM : ALUResult_EXE_MEM;
assign mem_axi_wid = do_write_id;
assign mem_axi_wstrb = MemWrite_EXE_MEM;
assign mem_axi_wdata = MemWdata_EXE_MEM;
assign mem_axi_wvalid = wvalid && mem_valid;
assign wready = mem_axi_wready;
assign mem_axi_awid = do_write_id;
assign mem_axi_awvalid = awvalid && mem_valid;
assign mem_axi_awaddr = {ALUResult_EXE_MEM[31:2],s_vaddr_EXE_MEM};
assign mem_axi_awsize = s_size_EXE_MEM;
assign awready = mem_axi_awready;
assign mem_axi_arid = 4'd1;
assign mem_axi_araddr = {ALUResult_EXE_MEM[31:2],2'b00};
assign mem_axi_arsize = (|LW_EXE_MEM)|
LH_EXE_MEM | LHU_EXE_MEM |
LB_EXE_MEM | LBU_EXE_MEM ? 3'b010 : 3'b00;
assign mem_axi_arvalid = arvalid && mem_valid;
assign arready = mem_axi_arready;
assign arvalid = do_req_raddr;
assign rvalid = mem_axi_rvalid;
assign rid = mem_axi_rid;
assign mem_axi_rready = rready;
assign bid = mem_axi_bid;
assign bvalid = mem_axi_bvalid;
assign mem_axi_bready = bready;
always @ (posedge clk) begin
if (rst) begin
{
PC_MEM_WB, RegWaddr_MEM_WB, MemToReg_MEM_WB, RegWrite_MEM_WB,
ALUResult_MEM_WB, RegRdata2_MEM_WB, cp0Rdata_MEM_WB, MFHL_MEM_WB,
LB_MEM_WB, LBU_MEM_WB, LH_MEM_WB, LHU_MEM_WB,
LW_MEM_WB, mfc0_MEM_WB, MemRdata_MEM_WB
} <= 'd0;
end
else if (mem_to_wb_valid && wb_allowin) begin
PC_MEM_WB <= PC_EXE_MEM;
RegWaddr_MEM_WB <= RegWaddr_EXE_MEM;
MemToReg_MEM_WB <= MemToReg_EXE_MEM;
RegWrite_MEM_WB <= RegWrite_EXE_MEM;
ALUResult_MEM_WB <= ALUResult_EXE_MEM;
RegRdata2_MEM_WB <= RegRdata2_EXE_MEM;
cp0Rdata_MEM_WB <= cp0Rdata_EXE_MEM;
MFHL_MEM_WB <= MFHL_EXE_MEM;
LB_MEM_WB <= LB_EXE_MEM;
LBU_MEM_WB <= LBU_EXE_MEM;
LH_MEM_WB <= LH_EXE_MEM;
LHU_MEM_WB <= LHU_EXE_MEM;
LW_MEM_WB <= LW_EXE_MEM;
mfc0_MEM_WB <= mfc0_EXE_MEM;
MemRdata_MEM_WB <= mem_axi_rdata;
end
end
assign MULT_MEM = MULT_EXE_MEM & {2{mem_valid}};
assign MTHL_MEM = MTHL_EXE_MEM & {2{mem_valid}};
assign mem_read_req = read_req;
assign write_req = |MemWrite_EXE_MEM && mem_valid;
assign read_req = MemEn_EXE_MEM && ~(|MemWrite_EXE_MEM) && mem_valid;
always @(posedge clk)
begin
data_w_req <= rst ? 2'd0 :
data_w_req==2'd0 ?
(write_req ?
(write_id_n!=4'd4 ? 2'd2 : 2'd1)
: data_w_req)
: (data_w_req==2'd1 ?
(write_id_n!=4'd4 ? 2'd2 : data_w_req)
: (|data_in_ready_pos ? 2'd0 : data_w_req));
data_r_req <= rst ? 2'd0 :
data_r_req==2'd0 ?
read_req ?
!pot_hazard ? 2'd2 : 2'd1
: data_r_req
:data_r_req==2'd1 ?
!pot_hazard ? 2'd2 : data_r_req
:r_data_back ? 2'd0 : data_r_req;
end
always @ (posedge clk) begin
end
always @ (posedge clk) begin
if (rst) begin
do_waddr_r[0] <= 33'd0;
do_waddr_r[1] <= 33'd0;
do_waddr_r[2] <= 33'd0;
do_waddr_r[3] <= 33'd0;
do_dsize_r[0] <= 3'd0;
do_dsize_r[1] <= 3'd0;
do_dsize_r[2] <= 3'd0;
do_dsize_r[3] <= 3'd0;
end
else
if (data_w_req_pos) begin
if (write_id_n==4'd0) begin
if (bvalid&&bready) begin
if (bid==4'd1) do_waddr_r[1] <= 33'd0;
if (bid==4'd2) do_waddr_r[2] <= 33'd0;
if (bid==4'd3) do_waddr_r[3] <= 33'd0;
end
do_waddr_r[0] <= {1'b1,mem_axi_awaddr};
do_dsize_r[0] <= mem_axi_awsize;
end
if (write_id_n==4'd1) begin
if (bvalid&&bready) begin
if (bid==4'd0) do_waddr_r[0] <= 33'd0;
if (bid==4'd2) do_waddr_r[2] <= 33'd0;
if (bid==4'd3) do_waddr_r[3] <= 33'd0;
end
do_waddr_r[1] <= {1'b1,mem_axi_awaddr};
do_dsize_r[1] <= mem_axi_awsize;
end
if (write_id_n==4'd2) begin
if (bvalid&&bready) begin
if (bid==4'd0) do_waddr_r[0] <= 33'd0;
if (bid==4'd1) do_waddr_r[1] <= 33'd0;
if (bid==4'd3) do_waddr_r[3] <= 33'd0;
end
do_waddr_r[2] <= {1'b1,mem_axi_awaddr};
do_dsize_r[2] <= mem_axi_awsize;
end
if (write_id_n==4'd3) begin
if (bvalid&&bready) begin
if (bid==4'd0) do_waddr_r[0] <= 33'd0;
if (bid==4'd1) do_waddr_r[1] <= 33'd0;
if (bid==4'd2) do_waddr_r[2] <= 33'd0;
end
do_waddr_r[3] <= {1'b1,mem_axi_awaddr};
do_dsize_r[3] <= mem_axi_awsize;
end
end
else if (bvalid&&bready) begin
if (bid==4'd0) do_waddr_r[0] <= 33'd0;
if (bid==4'd1) do_waddr_r[1] <= 33'd0;
if (bid==4'd2) do_waddr_r[2] <= 33'd0;
if (bid==4'd3) do_waddr_r[3] <= 33'd0;
end
end
always @ (posedge clk) begin
do_req_raddr <= rst ? 1'b0 :
data_r_req_pos ? 1'b1 :
r_addr_rcv_pos ? 1'b0 : do_req_raddr;
end
always @(posedge clk) begin
r_addr_rcv <= rst ? 1'b0 :
arvalid&&arready&&arid==4'd1 ? 1'b1 :
r_data_back ? 1'b0 : r_addr_rcv;
rready <= rst ? 1'b0 :
r_addr_rcv_pos ? 1'b1 :
r_data_back ? 1'b0 : rready;
end
assign r_data_back = r_addr_rcv && (rvalid && rready && rid==4'd1);
assign w_data_back[0] = (w_addr_rcv[0]&&w_data_rcv[0]) && (bvalid && bready && bid==4'd0);
assign w_data_back[1] = (w_addr_rcv[1]&&w_data_rcv[1]) && (bvalid && bready && bid==4'd1);
assign w_data_back[2] = (w_addr_rcv[2]&&w_data_rcv[2]) && (bvalid && bready && bid==4'd2);
assign w_data_back[3] = (w_addr_rcv[3]&&w_data_rcv[3]) && (bvalid && bready && bid==4'd3);
always @ (posedge clk) begin
if (rst) begin
do_req_waddr[0] <= 1'b0;
do_req_waddr[1] <= 1'b0;
do_req_waddr[2] <= 1'b0;
do_req_waddr[3] <= 1'b0;
do_req_wdata[0] <= 1'b0;
do_req_wdata[1] <= 1'b0;
do_req_wdata[2] <= 1'b0;
do_req_wdata[3] <= 1'b0;
data_in_ready[0] <= 2'b00;
data_in_ready[1] <= 2'b00;
data_in_ready[2] <= 2'b00;
data_in_ready[3] <= 2'b00;
end
else begin
if (data_w_req_pos) begin
if (write_id_n==3'd0) begin
do_req_waddr[0] <= 1'b1;
do_req_wdata[0] <= 1'b1;
end
if (write_id_n==3'd1) begin
do_req_waddr[1] <= 1'b1;
do_req_wdata[1] <= 1'b1;
end
if (write_id_n==3'd2) begin
do_req_waddr[2] <= 1'b1;
do_req_wdata[2] <= 1'b1;
end
if (write_id_n==3'd3) begin
do_req_waddr[3] <= 1'b1;
do_req_wdata[3] <= 1'b1;
end
end
else begin
if (data_in_ready_pos[0]) begin
do_req_waddr[0] <= 1'b0;
do_req_wdata[0] <= 1'b0;
end
if (data_in_ready_pos[1]) begin
do_req_waddr[1] <= 1'b0;
do_req_wdata[1] <= 1'b0;
end
if (data_in_ready_pos[2]) begin
do_req_waddr[2] <= 1'b0;
do_req_wdata[2] <= 1'b0;
end
if (data_in_ready_pos[3]) begin
do_req_waddr[3] <= 1'b0;
do_req_wdata[3] <= 1'b0;
end
end
if (do_write_id==3'd0) begin
if (awvalid&&awready && wvalid&&wready) begin
data_in_ready[0] <= 2'b11;
end
else if (awvalid&&awready) begin
data_in_ready[0] <= data_in_ready[0] + 2'b01;
end
else if (wvalid&&wready) begin
data_in_ready[0] <= data_in_ready[0] + 2'b10;
end
end
if (w_data_back[0]) begin
data_in_ready[0] <= 2'b00;
end
if (do_write_id==3'd1) begin
if (awvalid&&awready && wvalid&&wready) begin
data_in_ready[1] <= 2'b11;
end
else if (awvalid&&awready) begin
data_in_ready[1] <= data_in_ready[1] + 2'b01;
end
else if (wvalid&&wready) begin
data_in_ready[1] <= data_in_ready[1] + 2'b10;
end
end
if (w_data_back[1]) begin
data_in_ready[1] <= 2'b00;
end
if (do_write_id==3'd2) begin
if (awvalid&&awready && wvalid&&wready) begin
data_in_ready[2] <= 2'b11;
end
else if (awvalid&&awready) begin
data_in_ready[2] <= data_in_ready[2] + 2'b01;
end
else if (wvalid&&wready) begin
data_in_ready[2] <= data_in_ready[2] + 2'b10;
end
end
if (w_data_back[2]) begin
data_in_ready[2] <= 2'b00;
end
if (do_write_id==3'd3) begin
if (awvalid&&awready && wvalid&&wready) begin
data_in_ready[3] <= 2'b11;
end
else if (awvalid&&awready) begin
data_in_ready[3] <= data_in_ready[3] + 2'b01;
end
else if (wvalid&&wready) begin
data_in_ready[3] <= data_in_ready[3] + 2'b10;
end
end
if (w_data_back[3]) begin
data_in_ready[3] <= 2'b00;
end
end
end
always @ (posedge clk) begin
if (rst) begin
awvalid <= 1'b0;
wvalid <= 1'b0;
end
else begin
if (|do_req_waddr_pos) begin
awvalid <= 1'b1;
end
else if (awready) begin
awvalid <= 1'b0;
end
if (|do_req_wdata_pos) begin
wvalid <= 1'b1;
end
else if (wready) begin
wvalid <= 1'b0;
end
end
end
always @ (posedge clk) begin
if (rst) begin
w_addr_rcv[0] <= 1'b0;
w_addr_rcv[1] <= 1'b0;
w_addr_rcv[2] <= 1'b0;
w_addr_rcv[3] <= 1'b0;
w_data_rcv[0] <= 1'b0;
w_data_rcv[1] <= 1'b0;
w_data_rcv[2] <= 1'b0;
w_data_rcv[3] <= 1'b0;
end
else begin
if (awvalid&&awready) begin
if (do_write_id==3'd0) begin
w_addr_rcv[0] <= 1'b1;
end
if (do_write_id==3'd1) begin
w_addr_rcv[1] <= 1'b1;
end
if (do_write_id==3'd2) begin
w_addr_rcv[2] <= 1'b1;
end
if (do_write_id==3'd3) begin
w_addr_rcv[3] <= 1'b1;
end
end
if (wvalid&&wready) begin
if (do_write_id==3'd0) begin
w_data_rcv[0] <= 1'b1;
end
if (do_write_id==3'd1) begin
w_data_rcv[1] <= 1'b1;
end
if (do_write_id==3'd2) begin
w_data_rcv[2] <= 1'b1;
end
if (do_write_id==3'd3) begin
w_data_rcv[3] <= 1'b1;
end
end
if (w_data_back[0]) begin
w_addr_rcv[0] <= 1'b0;
w_data_rcv[0] <= 1'b0;
end
if (w_data_back[1]) begin
w_addr_rcv[1] <= 1'b0;
w_data_rcv[1] <= 1'b0;
end
if (w_data_back[2]) begin
w_addr_rcv[2] <= 1'b0;
w_data_rcv[2] <= 1'b0;
end
if (w_data_back[3]) begin
w_addr_rcv[3] <= 1'b0;
w_data_rcv[3] <= 1'b0;
end
end
end
assign bready = 1'b1;
assign data_w_req_pos = data_w_req==2'd0 && write_req && write_id_n!=4'd4 ||
data_w_req==2'd1 && write_id_n!=4'd4;
assign data_r_req_pos = data_r_req==2'd0 && read_req && !pot_hazard ||
data_r_req==2'd1 && !pot_hazard;
assign r_addr_rcv_pos = !r_addr_rcv && arvalid&&arready&&arid==4'd1;
assign data_in_ready_pos[0] = data_in_ready[0]==2'd1 && wvalid&&wready ||
data_in_ready[0]==2'd2 && awvalid&&awready ||
data_in_ready[0]==2'd0 && awvalid&&awready && wvalid&&wready;
assign data_in_ready_pos[1] = data_in_ready[1]==2'd1 && wvalid&&wready ||
data_in_ready[1]==2'd2 && awvalid&&awready ||
data_in_ready[1]==2'd0 && awvalid&&awready && wvalid&&wready;
assign data_in_ready_pos[2] = data_in_ready[2]==2'd1 && wvalid&&wready ||
data_in_ready[2]==2'd2 && awvalid&&awready ||
data_in_ready[2]==2'd0 && awvalid&&awready && wvalid&&wready;
assign data_in_ready_pos[3] = data_in_ready[3]==2'd1 && wvalid&&wready ||
data_in_ready[3]==2'd2 && awvalid&&awready ||
data_in_ready[3]==2'd0 && awvalid&&awready && wvalid&&wready;
assign do_req_waddr_pos[0] = !do_req_waddr[0] && data_w_req_pos && write_id_n==3'd0;
assign do_req_waddr_pos[1] = !do_req_waddr[1] && data_w_req_pos && write_id_n==3'd1;
assign do_req_waddr_pos[2] = !do_req_waddr[2] && data_w_req_pos && write_id_n==3'd2;
assign do_req_waddr_pos[3] = !do_req_waddr[3] && data_w_req_pos && write_id_n==3'd3;
assign do_req_wdata_pos[0] = !do_req_wdata[0] && data_w_req_pos && write_id_n==3'd0;
assign do_req_wdata_pos[1] = !do_req_wdata[1] && data_w_req_pos && write_id_n==3'd1;
assign do_req_wdata_pos[2] = !do_req_wdata[2] && data_w_req_pos && write_id_n==3'd2;
assign do_req_wdata_pos[3] = !do_req_wdata[3] && data_w_req_pos && write_id_n==3'd3;
endmodule | module memory_stage(
input wire clk,
input wire rst,
input wire MemEn_EXE_MEM,
input wire MemToReg_EXE_MEM,
input wire [ 3:0] MemWrite_EXE_MEM,
input wire [ 3:0] RegWrite_EXE_MEM,
input wire [ 1:0] MFHL_EXE_MEM,
input wire LB_EXE_MEM,
input wire LBU_EXE_MEM,
input wire LH_EXE_MEM,
input wire LHU_EXE_MEM,
input wire [ 1:0] LW_EXE_MEM,
input wire [ 4:0] RegWaddr_EXE_MEM,
input wire [31:0] ALUResult_EXE_MEM,
input wire [31:0] MemWdata_EXE_MEM,
input wire [31:0] RegRdata2_EXE_MEM,
input wire [31:0] PC_EXE_MEM,
input wire [ 1:0] s_vaddr_EXE_MEM,
input wire [ 2:0] s_size_EXE_MEM,
input [ 1:0] MULT_EXE_MEM,
input [ 1:0] MTHL_EXE_MEM,
output [ 1:0] MULT_MEM,
output [ 1:0] MTHL_MEM,
output reg MemToReg_MEM_WB,
output reg [ 3:0] RegWrite_MEM_WB,
output reg [ 1:0] MFHL_MEM_WB,
output reg LB_MEM_WB,
output reg LBU_MEM_WB,
output reg LH_MEM_WB,
output reg LHU_MEM_WB,
output reg [ 1:0] LW_MEM_WB,
output reg [ 4:0] RegWaddr_MEM_WB,
output reg [31:0] ALUResult_MEM_WB,
output reg [31:0] RegRdata2_MEM_WB,
output reg [31:0] PC_MEM_WB,
output reg [31:0] MemRdata_MEM_WB,
output wire [31:0] Bypass_MEM,
input wire [31:0] cp0Rdata_EXE_MEM,
input wire mfc0_EXE_MEM,
output reg [31:0] cp0Rdata_MEM_WB,
output reg mfc0_MEM_WB,
input wb_allowin,
input exe_to_mem_valid,
output mem_allowin,
output mem_to_wb_valid,
output reg [ 1:0] data_r_req,
output reg do_req_raddr,
input [31:0] mem_axi_rdata,
input mem_axi_rvalid,
input [ 3:0] mem_axi_rid,
output mem_axi_rready,
output [ 3:0] mem_axi_arid,
output [31:0] mem_axi_araddr,
output [ 2:0] mem_axi_arsize,
input mem_axi_arready,
output mem_axi_arvalid,
output [ 3:0] mem_axi_awid,
output [31:0] mem_axi_awaddr,
output [ 2:0] mem_axi_awsize,
output mem_axi_awvalid,
input mem_axi_awready,
output [ 3:0] mem_axi_wid,
output [31:0] mem_axi_wdata,
output [ 3:0] mem_axi_wstrb,
output mem_axi_wvalid,
input mem_axi_wready,
output mem_axi_bready,
input [ 3:0] mem_axi_bid,
input mem_axi_bvalid,
input [ 3:0] cpu_arid,
output mem_read_req,
output mem_stage_valid
); |
wire mem_ready_go;
reg mem_valid;
wire read_req;
wire write_req;
wire arvalid;
wire arready;
wire [3:0] rid;
reg rready;
wire rvalid;
reg awvalid;
wire awready;
reg wvalid;
wire wready;
wire bvalid;
wire bready;
wire [3:0] bid;
reg [1:0] data_w_req;
reg [0:3] do_req_waddr;
reg [0:3] do_req_wdata;
wire [0:3] do_req_waddr_pos;
wire [0:3] do_req_wdata_pos;
reg r_addr_rcv;
reg [0:3] w_addr_rcv;
reg [0:3] w_data_rcv;
reg [1:0] data_in_ready [0:3];
wire r_data_back;
wire [0:3] w_data_back;
reg [32:0] do_waddr_r [0:3];
reg [ 3:0] do_dsize_r [0:3];
wire [4:0] write_id_n;
wire pot_hazard;
wire data_w_req_pos;
wire data_r_req_pos;
wire r_addr_rcv_pos;
wire [0:3] data_in_ready_pos;
reg [2:0] do_write_id;
wire arid;
assign arid = cpu_arid;
assign mem_ready_go = (data_r_req==2'd0&&!read_req&&data_w_req==2'd0&&!write_req) ||
(data_r_req==2'd2&&r_data_back) ||
(data_w_req==2'd2&&(|data_in_ready_pos));
assign mem_allowin = !mem_valid || mem_ready_go && wb_allowin;
assign mem_to_wb_valid = mem_valid && mem_ready_go;
always @ (posedge clk) begin
if (rst) begin
mem_valid <= 1'b0;
end
else if (mem_allowin) begin
mem_valid <= exe_to_mem_valid;
end
end
assign mem_stage_valid = mem_valid;
assign write_id_n = do_waddr_r[0][32]==1'b0 ? 4'd0 :
do_waddr_r[1][32]==1'b0 ? 4'd1 :
do_waddr_r[2][32]==1'b0 ? 4'd2 :
do_waddr_r[3][32]==1'b0 ? 4'd3 : 4'd4;
always @ (posedge clk) begin
if (rst) begin
do_write_id <= 3'd0;
end
else
if (data_w_req_pos) begin
do_write_id <= write_id_n;
end
end
assign pot_hazard = mem_axi_araddr==(do_waddr_r[0][31:0]&32'hfffffffc) && do_waddr_r[0][32] ||
mem_axi_araddr==(do_waddr_r[1][31:0]&32'hfffffffc) && do_waddr_r[1][32] ||
mem_axi_araddr==(do_waddr_r[2][31:0]&32'hfffffffc) && do_waddr_r[2][32] ||
mem_axi_araddr==(do_waddr_r[3][31:0]&32'hfffffffc) && do_waddr_r[3][32] ;
assign Bypass_MEM = mfc0_EXE_MEM ?
cp0Rdata_EXE_MEM : ALUResult_EXE_MEM;
assign mem_axi_wid = do_write_id;
assign mem_axi_wstrb = MemWrite_EXE_MEM;
assign mem_axi_wdata = MemWdata_EXE_MEM;
assign mem_axi_wvalid = wvalid && mem_valid;
assign wready = mem_axi_wready;
assign mem_axi_awid = do_write_id;
assign mem_axi_awvalid = awvalid && mem_valid;
assign mem_axi_awaddr = {ALUResult_EXE_MEM[31:2],s_vaddr_EXE_MEM};
assign mem_axi_awsize = s_size_EXE_MEM;
assign awready = mem_axi_awready;
assign mem_axi_arid = 4'd1;
assign mem_axi_araddr = {ALUResult_EXE_MEM[31:2],2'b00};
assign mem_axi_arsize = (|LW_EXE_MEM)|
LH_EXE_MEM | LHU_EXE_MEM |
LB_EXE_MEM | LBU_EXE_MEM ? 3'b010 : 3'b00;
assign mem_axi_arvalid = arvalid && mem_valid;
assign arready = mem_axi_arready;
assign arvalid = do_req_raddr;
assign rvalid = mem_axi_rvalid;
assign rid = mem_axi_rid;
assign mem_axi_rready = rready;
assign bid = mem_axi_bid;
assign bvalid = mem_axi_bvalid;
assign mem_axi_bready = bready;
always @ (posedge clk) begin
if (rst) begin
{
PC_MEM_WB, RegWaddr_MEM_WB, MemToReg_MEM_WB, RegWrite_MEM_WB,
ALUResult_MEM_WB, RegRdata2_MEM_WB, cp0Rdata_MEM_WB, MFHL_MEM_WB,
LB_MEM_WB, LBU_MEM_WB, LH_MEM_WB, LHU_MEM_WB,
LW_MEM_WB, mfc0_MEM_WB, MemRdata_MEM_WB
} <= 'd0;
end
else if (mem_to_wb_valid && wb_allowin) begin
PC_MEM_WB <= PC_EXE_MEM;
RegWaddr_MEM_WB <= RegWaddr_EXE_MEM;
MemToReg_MEM_WB <= MemToReg_EXE_MEM;
RegWrite_MEM_WB <= RegWrite_EXE_MEM;
ALUResult_MEM_WB <= ALUResult_EXE_MEM;
RegRdata2_MEM_WB <= RegRdata2_EXE_MEM;
cp0Rdata_MEM_WB <= cp0Rdata_EXE_MEM;
MFHL_MEM_WB <= MFHL_EXE_MEM;
LB_MEM_WB <= LB_EXE_MEM;
LBU_MEM_WB <= LBU_EXE_MEM;
LH_MEM_WB <= LH_EXE_MEM;
LHU_MEM_WB <= LHU_EXE_MEM;
LW_MEM_WB <= LW_EXE_MEM;
mfc0_MEM_WB <= mfc0_EXE_MEM;
MemRdata_MEM_WB <= mem_axi_rdata;
end
end
assign MULT_MEM = MULT_EXE_MEM & {2{mem_valid}};
assign MTHL_MEM = MTHL_EXE_MEM & {2{mem_valid}};
assign mem_read_req = read_req;
assign write_req = |MemWrite_EXE_MEM && mem_valid;
assign read_req = MemEn_EXE_MEM && ~(|MemWrite_EXE_MEM) && mem_valid;
always @(posedge clk)
begin
data_w_req <= rst ? 2'd0 :
data_w_req==2'd0 ?
(write_req ?
(write_id_n!=4'd4 ? 2'd2 : 2'd1)
: data_w_req)
: (data_w_req==2'd1 ?
(write_id_n!=4'd4 ? 2'd2 : data_w_req)
: (|data_in_ready_pos ? 2'd0 : data_w_req));
data_r_req <= rst ? 2'd0 :
data_r_req==2'd0 ?
read_req ?
!pot_hazard ? 2'd2 : 2'd1
: data_r_req
:data_r_req==2'd1 ?
!pot_hazard ? 2'd2 : data_r_req
:r_data_back ? 2'd0 : data_r_req;
end
always @ (posedge clk) begin
end
always @ (posedge clk) begin
if (rst) begin
do_waddr_r[0] <= 33'd0;
do_waddr_r[1] <= 33'd0;
do_waddr_r[2] <= 33'd0;
do_waddr_r[3] <= 33'd0;
do_dsize_r[0] <= 3'd0;
do_dsize_r[1] <= 3'd0;
do_dsize_r[2] <= 3'd0;
do_dsize_r[3] <= 3'd0;
end
else
if (data_w_req_pos) begin
if (write_id_n==4'd0) begin
if (bvalid&&bready) begin
if (bid==4'd1) do_waddr_r[1] <= 33'd0;
if (bid==4'd2) do_waddr_r[2] <= 33'd0;
if (bid==4'd3) do_waddr_r[3] <= 33'd0;
end
do_waddr_r[0] <= {1'b1,mem_axi_awaddr};
do_dsize_r[0] <= mem_axi_awsize;
end
if (write_id_n==4'd1) begin
if (bvalid&&bready) begin
if (bid==4'd0) do_waddr_r[0] <= 33'd0;
if (bid==4'd2) do_waddr_r[2] <= 33'd0;
if (bid==4'd3) do_waddr_r[3] <= 33'd0;
end
do_waddr_r[1] <= {1'b1,mem_axi_awaddr};
do_dsize_r[1] <= mem_axi_awsize;
end
if (write_id_n==4'd2) begin
if (bvalid&&bready) begin
if (bid==4'd0) do_waddr_r[0] <= 33'd0;
if (bid==4'd1) do_waddr_r[1] <= 33'd0;
if (bid==4'd3) do_waddr_r[3] <= 33'd0;
end
do_waddr_r[2] <= {1'b1,mem_axi_awaddr};
do_dsize_r[2] <= mem_axi_awsize;
end
if (write_id_n==4'd3) begin
if (bvalid&&bready) begin
if (bid==4'd0) do_waddr_r[0] <= 33'd0;
if (bid==4'd1) do_waddr_r[1] <= 33'd0;
if (bid==4'd2) do_waddr_r[2] <= 33'd0;
end
do_waddr_r[3] <= {1'b1,mem_axi_awaddr};
do_dsize_r[3] <= mem_axi_awsize;
end
end
else if (bvalid&&bready) begin
if (bid==4'd0) do_waddr_r[0] <= 33'd0;
if (bid==4'd1) do_waddr_r[1] <= 33'd0;
if (bid==4'd2) do_waddr_r[2] <= 33'd0;
if (bid==4'd3) do_waddr_r[3] <= 33'd0;
end
end
always @ (posedge clk) begin
do_req_raddr <= rst ? 1'b0 :
data_r_req_pos ? 1'b1 :
r_addr_rcv_pos ? 1'b0 : do_req_raddr;
end
always @(posedge clk) begin
r_addr_rcv <= rst ? 1'b0 :
arvalid&&arready&&arid==4'd1 ? 1'b1 :
r_data_back ? 1'b0 : r_addr_rcv;
rready <= rst ? 1'b0 :
r_addr_rcv_pos ? 1'b1 :
r_data_back ? 1'b0 : rready;
end
assign r_data_back = r_addr_rcv && (rvalid && rready && rid==4'd1);
assign w_data_back[0] = (w_addr_rcv[0]&&w_data_rcv[0]) && (bvalid && bready && bid==4'd0);
assign w_data_back[1] = (w_addr_rcv[1]&&w_data_rcv[1]) && (bvalid && bready && bid==4'd1);
assign w_data_back[2] = (w_addr_rcv[2]&&w_data_rcv[2]) && (bvalid && bready && bid==4'd2);
assign w_data_back[3] = (w_addr_rcv[3]&&w_data_rcv[3]) && (bvalid && bready && bid==4'd3);
always @ (posedge clk) begin
if (rst) begin
do_req_waddr[0] <= 1'b0;
do_req_waddr[1] <= 1'b0;
do_req_waddr[2] <= 1'b0;
do_req_waddr[3] <= 1'b0;
do_req_wdata[0] <= 1'b0;
do_req_wdata[1] <= 1'b0;
do_req_wdata[2] <= 1'b0;
do_req_wdata[3] <= 1'b0;
data_in_ready[0] <= 2'b00;
data_in_ready[1] <= 2'b00;
data_in_ready[2] <= 2'b00;
data_in_ready[3] <= 2'b00;
end
else begin
if (data_w_req_pos) begin
if (write_id_n==3'd0) begin
do_req_waddr[0] <= 1'b1;
do_req_wdata[0] <= 1'b1;
end
if (write_id_n==3'd1) begin
do_req_waddr[1] <= 1'b1;
do_req_wdata[1] <= 1'b1;
end
if (write_id_n==3'd2) begin
do_req_waddr[2] <= 1'b1;
do_req_wdata[2] <= 1'b1;
end
if (write_id_n==3'd3) begin
do_req_waddr[3] <= 1'b1;
do_req_wdata[3] <= 1'b1;
end
end
else begin
if (data_in_ready_pos[0]) begin
do_req_waddr[0] <= 1'b0;
do_req_wdata[0] <= 1'b0;
end
if (data_in_ready_pos[1]) begin
do_req_waddr[1] <= 1'b0;
do_req_wdata[1] <= 1'b0;
end
if (data_in_ready_pos[2]) begin
do_req_waddr[2] <= 1'b0;
do_req_wdata[2] <= 1'b0;
end
if (data_in_ready_pos[3]) begin
do_req_waddr[3] <= 1'b0;
do_req_wdata[3] <= 1'b0;
end
end
if (do_write_id==3'd0) begin
if (awvalid&&awready && wvalid&&wready) begin
data_in_ready[0] <= 2'b11;
end
else if (awvalid&&awready) begin
data_in_ready[0] <= data_in_ready[0] + 2'b01;
end
else if (wvalid&&wready) begin
data_in_ready[0] <= data_in_ready[0] + 2'b10;
end
end
if (w_data_back[0]) begin
data_in_ready[0] <= 2'b00;
end
if (do_write_id==3'd1) begin
if (awvalid&&awready && wvalid&&wready) begin
data_in_ready[1] <= 2'b11;
end
else if (awvalid&&awready) begin
data_in_ready[1] <= data_in_ready[1] + 2'b01;
end
else if (wvalid&&wready) begin
data_in_ready[1] <= data_in_ready[1] + 2'b10;
end
end
if (w_data_back[1]) begin
data_in_ready[1] <= 2'b00;
end
if (do_write_id==3'd2) begin
if (awvalid&&awready && wvalid&&wready) begin
data_in_ready[2] <= 2'b11;
end
else if (awvalid&&awready) begin
data_in_ready[2] <= data_in_ready[2] + 2'b01;
end
else if (wvalid&&wready) begin
data_in_ready[2] <= data_in_ready[2] + 2'b10;
end
end
if (w_data_back[2]) begin
data_in_ready[2] <= 2'b00;
end
if (do_write_id==3'd3) begin
if (awvalid&&awready && wvalid&&wready) begin
data_in_ready[3] <= 2'b11;
end
else if (awvalid&&awready) begin
data_in_ready[3] <= data_in_ready[3] + 2'b01;
end
else if (wvalid&&wready) begin
data_in_ready[3] <= data_in_ready[3] + 2'b10;
end
end
if (w_data_back[3]) begin
data_in_ready[3] <= 2'b00;
end
end
end
always @ (posedge clk) begin
if (rst) begin
awvalid <= 1'b0;
wvalid <= 1'b0;
end
else begin
if (|do_req_waddr_pos) begin
awvalid <= 1'b1;
end
else if (awready) begin
awvalid <= 1'b0;
end
if (|do_req_wdata_pos) begin
wvalid <= 1'b1;
end
else if (wready) begin
wvalid <= 1'b0;
end
end
end
always @ (posedge clk) begin
if (rst) begin
w_addr_rcv[0] <= 1'b0;
w_addr_rcv[1] <= 1'b0;
w_addr_rcv[2] <= 1'b0;
w_addr_rcv[3] <= 1'b0;
w_data_rcv[0] <= 1'b0;
w_data_rcv[1] <= 1'b0;
w_data_rcv[2] <= 1'b0;
w_data_rcv[3] <= 1'b0;
end
else begin
if (awvalid&&awready) begin
if (do_write_id==3'd0) begin
w_addr_rcv[0] <= 1'b1;
end
if (do_write_id==3'd1) begin
w_addr_rcv[1] <= 1'b1;
end
if (do_write_id==3'd2) begin
w_addr_rcv[2] <= 1'b1;
end
if (do_write_id==3'd3) begin
w_addr_rcv[3] <= 1'b1;
end
end
if (wvalid&&wready) begin
if (do_write_id==3'd0) begin
w_data_rcv[0] <= 1'b1;
end
if (do_write_id==3'd1) begin
w_data_rcv[1] <= 1'b1;
end
if (do_write_id==3'd2) begin
w_data_rcv[2] <= 1'b1;
end
if (do_write_id==3'd3) begin
w_data_rcv[3] <= 1'b1;
end
end
if (w_data_back[0]) begin
w_addr_rcv[0] <= 1'b0;
w_data_rcv[0] <= 1'b0;
end
if (w_data_back[1]) begin
w_addr_rcv[1] <= 1'b0;
w_data_rcv[1] <= 1'b0;
end
if (w_data_back[2]) begin
w_addr_rcv[2] <= 1'b0;
w_data_rcv[2] <= 1'b0;
end
if (w_data_back[3]) begin
w_addr_rcv[3] <= 1'b0;
w_data_rcv[3] <= 1'b0;
end
end
end
assign bready = 1'b1;
assign data_w_req_pos = data_w_req==2'd0 && write_req && write_id_n!=4'd4 ||
data_w_req==2'd1 && write_id_n!=4'd4;
assign data_r_req_pos = data_r_req==2'd0 && read_req && !pot_hazard ||
data_r_req==2'd1 && !pot_hazard;
assign r_addr_rcv_pos = !r_addr_rcv && arvalid&&arready&&arid==4'd1;
assign data_in_ready_pos[0] = data_in_ready[0]==2'd1 && wvalid&&wready ||
data_in_ready[0]==2'd2 && awvalid&&awready ||
data_in_ready[0]==2'd0 && awvalid&&awready && wvalid&&wready;
assign data_in_ready_pos[1] = data_in_ready[1]==2'd1 && wvalid&&wready ||
data_in_ready[1]==2'd2 && awvalid&&awready ||
data_in_ready[1]==2'd0 && awvalid&&awready && wvalid&&wready;
assign data_in_ready_pos[2] = data_in_ready[2]==2'd1 && wvalid&&wready ||
data_in_ready[2]==2'd2 && awvalid&&awready ||
data_in_ready[2]==2'd0 && awvalid&&awready && wvalid&&wready;
assign data_in_ready_pos[3] = data_in_ready[3]==2'd1 && wvalid&&wready ||
data_in_ready[3]==2'd2 && awvalid&&awready ||
data_in_ready[3]==2'd0 && awvalid&&awready && wvalid&&wready;
assign do_req_waddr_pos[0] = !do_req_waddr[0] && data_w_req_pos && write_id_n==3'd0;
assign do_req_waddr_pos[1] = !do_req_waddr[1] && data_w_req_pos && write_id_n==3'd1;
assign do_req_waddr_pos[2] = !do_req_waddr[2] && data_w_req_pos && write_id_n==3'd2;
assign do_req_waddr_pos[3] = !do_req_waddr[3] && data_w_req_pos && write_id_n==3'd3;
assign do_req_wdata_pos[0] = !do_req_wdata[0] && data_w_req_pos && write_id_n==3'd0;
assign do_req_wdata_pos[1] = !do_req_wdata[1] && data_w_req_pos && write_id_n==3'd1;
assign do_req_wdata_pos[2] = !do_req_wdata[2] && data_w_req_pos && write_id_n==3'd2;
assign do_req_wdata_pos[3] = !do_req_wdata[3] && data_w_req_pos && write_id_n==3'd3;
endmodule | 0 |
4,904 | data/full_repos/permissive/112219256/mul.v | 112,219,256 | mul.v | v | 42 | 69 | [] | [] | [] | [(11, 41)] | null | null | 1: b"%Error: data/full_repos/permissive/112219256/mul.v:32: Cannot find file containing module: 'mult_signed'\n mult_signed Signed_Muliplier(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/mult_signed\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/mult_signed.v\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/mult_signed.sv\n mult_signed\n mult_signed.v\n mult_signed.sv\n obj_dir/mult_signed\n obj_dir/mult_signed.v\n obj_dir/mult_signed.sv\n%Error: Exiting due to 1 error(s)\n" | 3,311 | module | module multiplyer(
input [31:0] x,
input [31:0] y,
input mul_clk,
input resetn,
input clken,
input mul_signed,
output [63:0] result
);
wire rst = ~resetn;
wire clk = mul_clk;
wire [65:0] temp_signed_r, temp_unsigned_r;
reg temp_sign_r;
wire [32:0] x_r = mul_signed ? {x[31],x} : {{1'b0}, x};
wire [32:0] y_r = mul_signed ? {y[31],y} : {{1'b0}, y};
mult_signed Signed_Muliplier(
.CLK (clk),
.A (x_r),
.B (y_r),
.P (temp_signed_r)
);
assign result = temp_signed_r[63:0];
endmodule | module multiplyer(
input [31:0] x,
input [31:0] y,
input mul_clk,
input resetn,
input clken,
input mul_signed,
output [63:0] result
); |
wire rst = ~resetn;
wire clk = mul_clk;
wire [65:0] temp_signed_r, temp_unsigned_r;
reg temp_sign_r;
wire [32:0] x_r = mul_signed ? {x[31],x} : {{1'b0}, x};
wire [32:0] y_r = mul_signed ? {y[31],y} : {{1'b0}, y};
mult_signed Signed_Muliplier(
.CLK (clk),
.A (x_r),
.B (y_r),
.P (temp_signed_r)
);
assign result = temp_signed_r[63:0];
endmodule | 0 |
4,905 | data/full_repos/permissive/112219256/MUX_4_32.v | 112,219,256 | MUX_4_32.v | v | 33 | 69 | [] | [] | [] | [(11, 32)] | null | data/verilator_xmls/aa203c72-602d-4258-8471-d95113cf663e.xml | null | 3,312 | module | module MUX_4_32(
input [31:0] Src1,
input [31:0] Src2,
input [31:0] Src3,
input [31:0] Src4,
input [ 1:0] op,
output [31:0] Result
);
wire [31:0] and1, and2, and3, and4, op1, op1x, op0, op0x;
assign op1 = {32{ op[1]}};
assign op1x = {32{~op[1]}};
assign op0 = {32{ op[0]}};
assign op0x = {32{~op[0]}};
assign and1 = Src1 & op1x & op0x;
assign and2 = Src2 & op1x & op0;
assign and3 = Src3 & op1 & op0x;
assign and4 = Src4 & op1 & op0;
assign Result = (and1 | and2) | (and3 | and4);
endmodule | module MUX_4_32(
input [31:0] Src1,
input [31:0] Src2,
input [31:0] Src3,
input [31:0] Src4,
input [ 1:0] op,
output [31:0] Result
); |
wire [31:0] and1, and2, and3, and4, op1, op1x, op0, op0x;
assign op1 = {32{ op[1]}};
assign op1x = {32{~op[1]}};
assign op0 = {32{ op[0]}};
assign op0x = {32{~op[0]}};
assign and1 = Src1 & op1x & op0x;
assign and2 = Src2 & op1x & op0;
assign and3 = Src3 & op1 & op0x;
assign and4 = Src4 & op1 & op0;
assign Result = (and1 | and2) | (and3 | and4);
endmodule | 0 |
4,906 | data/full_repos/permissive/112219256/mycpu.v | 112,219,256 | mycpu.v | v | 593 | 86 | [] | [] | [] | [(13, 592)] | null | null | 1: b'%Error: data/full_repos/permissive/112219256/mycpu.v:520: syntax error, unexpected int\n .int ( int_i), \n ^~~\n%Error: Exiting due to 1 error(s)\n' | 3,313 | module | module mycpu(
input clk,
input resetn,
input [ 5:0] int_i,
output inst_req,
output [ 1:0] inst_size,
output [31:0] inst_addr,
input [31:0] inst_rdata,
input inst_addr_ok,
input inst_data_ok,
output data_req,
output data_wr,
output [ 1:0] data_rsize,
output [31:0] data_raddr,
input [31:0] data_rdata,
input data_raddr_ok,
input data_rdata_ok,
output [ 1:0] data_wsize,
output [31:0] data_waddr,
input [31:0] data_wdata,
input data_waddr_ok,
input data_wdata_ok
`ifdef SIMU_DEBUG
,output [31:0] debug_wb_pc,
output [ 3:0] debug_wb_rf_wen,
output [ 4:0] debug_wb_rf_wnum,
output [31:0] debug_wb_rf_wdata
`endif
);
wire rst = ~resetn;
wire JSrc;
wire [ 1:0] PCSrc;
wire [ 4:0] RegRaddr1;
wire [ 4:0] RegRaddr2;
wire [31:0] RegRdata1;
wire [31:0] RegRdata2;
wire DSI_ID;
wire DSI_IF_ID;
wire [31:0] PC_next;
wire [31:0] PC_IF_ID;
wire [31:0] PC_add_4_IF_ID;
wire PC_AdEL_IF_ID;
wire PC_AdEL;
wire [31:0] Inst_IF_ID;
wire PCWrite;
wire IRWrite;
wire [31:0] J_target_ID;
wire [31:0] JR_target_ID;
wire [31:0] Br_target_ID;
wire [31:0] PC_add_4_ID;
wire [ 1:0] RegRdata1_src;
wire [ 1:0] RegRdata2_src;
wire is_rs_read;
wire is_rt_read;
wire ID_EXE_Stall;
wire [31:0] PC_ID_EXE;
wire [31:0] PC_add_4_ID_EXE;
wire [ 1:0] RegDst_ID_EXE;
wire [ 1:0] ALUSrcA_ID_EXE;
wire [ 1:0] ALUSrcB_ID_EXE;
wire [ 3:0] ALUop_ID_EXE;
wire [ 3:0] RegWrite_ID_EXE;
wire [ 3:0] MemWrite_ID_EXE;
wire is_signed_ID_EXE;
wire MemEn_ID_EXE;
wire MemToReg_ID_EXE;
wire [ 1:0] MULT_ID_EXE;
wire [ 1:0] DIV_ID_EXE;
wire [ 1:0] MFHL_ID_EXE;
wire [ 1:0] MTHL_ID_EXE;
wire LB_ID_EXE;
wire LBU_ID_EXE;
wire LH_ID_EXE;
wire LHU_ID_EXE;
wire [ 1:0] LW_ID_EXE;
wire [ 1:0] SW_ID_EXE;
wire SB_ID_EXE;
wire SH_ID_EXE;
wire [ 4:0] RegWaddr_ID_EXE;
wire [31:0] ALUResult_EXE;
wire [31:0] ALUResult_MEM;
wire [31:0] RegRdata1_ID_EXE;
wire [31:0] RegRdata2_ID_EXE;
wire [31:0] Sa_ID_EXE;
wire [31:0] SgnExtend_ID_EXE;
wire [31:0] ZExtend_ID_EXE;
wire MemEn_EXE_MEM;
wire MemToReg_EXE_MEM;
wire [ 3:0] MemWrite_EXE_MEM;
wire [ 3:0] RegWrite_EXE_MEM;
wire [ 3:0] RegWrite_EXE;
wire [ 4:0] RegWaddr_EXE_MEM;
wire [ 1:0] MULT_EXE_MEM;
wire [ 1:0] MFHL_EXE_MEM;
wire [ 1:0] MTHL_EXE_MEM;
wire LB_EXE_MEM;
wire LBU_EXE_MEM;
wire LH_EXE_MEM;
wire LHU_EXE_MEM;
wire [ 1:0] LW_EXE_MEM;
wire [31:0] ALUResult_EXE_MEM;
wire [31:0] MemWdata_EXE_MEM;
wire [31:0] PC_EXE_MEM;
wire [31:0] RegRdata1_EXE_MEM;
wire [31:0] RegRdata2_EXE_MEM;
wire MemToReg_MEM_WB;
wire [ 3:0] RegWrite_MEM_WB;
wire [ 4:0] RegWaddr_MEM_WB;
wire [ 1:0] MFHL_MEM_WB;
wire LB_MEM_WB;
wire LBU_MEM_WB;
wire LH_MEM_WB;
wire LHU_MEM_WB;
wire [ 1:0] LW_MEM_WB;
wire [31:0] ALUResult_MEM_WB;
wire [31:0] RegRdata2_MEM_WB;
wire [31:0] PC_MEM_WB;
wire [31:0] PC_WB;
wire [31:0] RegWdata_WB;
wire [ 4:0] RegWaddr_WB;
wire [ 3:0] RegWrite_WB;
wire [31:0] RegWdata_Bypass_WB;
wire [63:0] MULT_Result;
wire [31:0] DIV_quotient;
wire [31:0] DIV_remainder;
wire DIV_Busy;
wire DIV_Complete;
wire [31:0] HI_in;
wire [31:0] LO_in;
wire [ 1:0] HILO_Write;
wire [31:0] HI_out;
wire [31:0] LO_out;
wire [31:0] CP0Raddr;
wire [31:0] CP0Rdata;
wire [31:0] CP0Waddr;
wire [31:0] CP0Wdata;
wire [ 3:0] CP0Write;
wire [31:0] epc;
wire [ 4:0] rd;
wire [31:0] RegRdata2_Final;
wire [31:0] cp0Rdata_EXE_MEM;
wire [31:0] cp0Rdata_MEM_WB;
wire mfc0_ID_EXE;
wire mfc0_EXE_MEM;
wire mfc0_MEM_WB;
wire [31:0] Bypass_EXE;
wire [31:0] Bypass_MEM;
wire [31:0] Exc_BadVaddr;
wire [31:0] Exc_EPC;
wire [ 5:0] Exc_Cause;
wire ex_int_handle;
wire eret_handle;
wire [ 6:0] Exc_Vec;
wire DSI_ID_EXE,eret_ID_EXE,cp0_Write_ID_EXE,Exc_BD;
wire [ 4:0] Rd_ID_EXE;
wire [ 3:0] Exc_vec_ID_EXE;
wire PC_abnormal;
nextpc_gen nextpc_gen(
.clk ( clk),
.rst ( rst),
.PCWrite ( PCWrite),
.JSrc ( JSrc),
.PCSrc ( PCSrc),
.eret ( eret_handle),
.epc ( epc),
.JR_target ( JR_target_ID),
.J_target ( J_target_ID),
.Br_addr ( Br_target_ID),
.inst_sram_addr ( inst_sram_addr),
.PC_next ( PC_next),
.PC_AdEL ( PC_AdEL),
.ex_int_handle ( ex_int_handle),
.PC_abnormal ( PC_abnormal)
);
fetch_stage fe_stage(
.clk ( clk),
.rst ( rst),
.DSI_ID ( DSI_ID),
.IRWrite ( IRWrite),
.PC_AdEL ( PC_AdEL),
.PC_next ( PC_next),
.PC_abnormal ( PC_abnormal),
.inst_sram_en ( inst_sram_en),
.inst_sram_rdata ( inst_sram_rdata),
.PC_IF_ID ( PC_IF_ID),
.PC_add_4_IF_ID ( PC_add_4_IF_ID),
.Inst_IF_ID ( Inst_IF_ID),
.PC_AdEL_IF_ID ( PC_AdEL_IF_ID),
.DSI_IF_ID ( DSI_IF_ID)
);
decode_stage de_stage(
.clk ( clk),
.rst ( rst),
.Inst_IF_ID ( Inst_IF_ID),
.PC_IF_ID ( PC_IF_ID),
.PC_add_4_IF_ID ( PC_add_4_IF_ID),
.DSI_IF_ID ( DSI_IF_ID),
.PC_AdEL_IF_ID ( PC_AdEL_IF_ID),
.ex_int_handle_ID ( ex_int_handle),
.RegRaddr1_ID ( RegRaddr1),
.RegRaddr2_ID ( RegRaddr2),
.RegRdata1_ID ( RegRdata1),
.RegRdata2_ID ( RegRdata2),
.Bypass_EXE ( Bypass_EXE),
.Bypass_MEM ( Bypass_MEM),
.RegWdata_WB (RegWdata_Bypass_WB),
.MULT_Result ( MULT_Result),
.HI ( HI_out),
.LO ( LO_out),
.MFHL_ID_EXE_1 ( MFHL_ID_EXE),
.MFHL_EXE_MEM ( MFHL_EXE_MEM),
.MFHL_MEM_WB ( MFHL_MEM_WB),
.MULT_EXE_MEM ( MULT_EXE_MEM),
.RegRdata1_src ( RegRdata1_src),
.RegRdata2_src ( RegRdata2_src),
.ID_EXE_Stall ( ID_EXE_Stall),
.DIV_Complete ( DIV_Complete),
.JSrc ( JSrc),
.PCSrc ( PCSrc),
.J_target_ID ( J_target_ID),
.JR_target_ID ( JR_target_ID),
.Br_target_ID ( Br_target_ID),
.ALUSrcA_ID_EXE ( ALUSrcA_ID_EXE),
.ALUSrcB_ID_EXE ( ALUSrcB_ID_EXE),
.ALUop_ID_EXE ( ALUop_ID_EXE),
.RegWrite_ID_EXE ( RegWrite_ID_EXE),
.MemWrite_ID_EXE ( MemWrite_ID_EXE),
.MemEn_ID_EXE ( MemEn_ID_EXE),
.MemToReg_ID_EXE ( MemToReg_ID_EXE),
.is_signed_ID_EXE ( is_signed_ID_EXE),
.MULT_ID_EXE ( MULT_ID_EXE),
.DIV_ID_EXE ( DIV_ID_EXE),
.MFHL_ID_EXE ( MFHL_ID_EXE),
.MTHL_ID_EXE ( MTHL_ID_EXE),
.LB_ID_EXE ( LB_ID_EXE),
.LBU_ID_EXE ( LBU_ID_EXE),
.LH_ID_EXE ( LH_ID_EXE),
.LHU_ID_EXE ( LHU_ID_EXE),
.LW_ID_EXE ( LW_ID_EXE),
.SW_ID_EXE ( SW_ID_EXE),
.SB_ID_EXE ( SB_ID_EXE),
.SH_ID_EXE ( SH_ID_EXE),
.DSI_ID_EXE ( DSI_ID_EXE),
.eret_ID_EXE ( eret_ID_EXE),
.Rd_ID_EXE ( Rd_ID_EXE),
.Exc_vec_ID_EXE ( Exc_vec_ID_EXE),
.RegWaddr_ID_EXE ( RegWaddr_ID_EXE),
.PC_add_4_ID_EXE ( PC_add_4_ID_EXE),
.PC_ID_EXE ( PC_ID_EXE),
.RegRdata1_ID_EXE ( RegRdata1_ID_EXE),
.RegRdata2_ID_EXE ( RegRdata2_ID_EXE),
.Sa_ID_EXE ( Sa_ID_EXE),
.SgnExtend_ID_EXE ( SgnExtend_ID_EXE),
.ZExtend_ID_EXE ( ZExtend_ID_EXE),
.cp0_Write_ID_EXE ( cp0_Write_ID_EXE),
.mfc0_ID_EXE ( mfc0_ID_EXE),
.is_rs_read_ID ( is_rs_read),
.is_rt_read_ID ( is_rt_read),
.is_j_or_br_ID ( DSI_ID)
);
execute_stage exe_stage(
.clk ( clk),
.rst ( rst),
.PC_add_4_ID_EXE ( PC_add_4_ID_EXE),
.cp0_Write_ID_EXE ( cp0_Write_ID_EXE),
.PC_ID_EXE ( PC_ID_EXE),
.RegRdata1_ID_EXE ( RegRdata1_ID_EXE),
.RegRdata2_ID_EXE ( RegRdata2_ID_EXE),
.Sa_ID_EXE ( Sa_ID_EXE),
.SgnExtend_ID_EXE ( SgnExtend_ID_EXE),
.ZExtend_ID_EXE ( ZExtend_ID_EXE),
.RegWaddr_ID_EXE ( RegWaddr_ID_EXE),
.MemEn_ID_EXE ( MemEn_ID_EXE),
.MemToReg_ID_EXE ( MemToReg_ID_EXE),
.is_signed_ID_EXE ( is_signed_ID_EXE),
.DSI_ID_EXE ( DSI_ID_EXE),
.Rd_ID_EXE ( Rd_ID_EXE),
.Exc_vec_ID_EXE ( Exc_vec_ID_EXE),
.ALUSrcA_ID_EXE ( ALUSrcA_ID_EXE),
.ALUSrcB_ID_EXE ( ALUSrcB_ID_EXE),
.ALUop_ID_EXE ( ALUop_ID_EXE),
.MemWrite_ID_EXE ( MemWrite_ID_EXE),
.RegWrite_ID_EXE ( RegWrite_ID_EXE),
.MULT_ID_EXE ( MULT_ID_EXE),
.MFHL_ID_EXE ( MFHL_ID_EXE),
.MTHL_ID_EXE ( MTHL_ID_EXE),
.LB_ID_EXE ( LB_ID_EXE),
.LBU_ID_EXE ( LBU_ID_EXE),
.LH_ID_EXE ( LH_ID_EXE),
.LHU_ID_EXE ( LHU_ID_EXE),
.LW_ID_EXE ( LW_ID_EXE),
.SW_ID_EXE ( SW_ID_EXE),
.SB_ID_EXE ( SB_ID_EXE),
.SH_ID_EXE ( SH_ID_EXE),
.MemEn_EXE_MEM ( MemEn_EXE_MEM),
.MemToReg_EXE_MEM ( MemToReg_EXE_MEM),
.MemWrite_EXE_MEM ( MemWrite_EXE_MEM),
.RegWrite_EXE_MEM ( RegWrite_EXE_MEM),
.MULT_EXE_MEM ( MULT_EXE_MEM),
.MFHL_EXE_MEM ( MFHL_EXE_MEM),
.MTHL_EXE_MEM ( MTHL_EXE_MEM),
.LB_EXE_MEM ( LB_EXE_MEM),
.LBU_EXE_MEM ( LBU_EXE_MEM),
.LH_EXE_MEM ( LH_EXE_MEM),
.LHU_EXE_MEM ( LHU_EXE_MEM),
.LW_EXE_MEM ( LW_EXE_MEM),
.RegWaddr_EXE_MEM ( RegWaddr_EXE_MEM),
.ALUResult_EXE_MEM (ALUResult_EXE_MEM),
.MemWdata_EXE_MEM ( MemWdata_EXE_MEM),
.PC_EXE_MEM ( PC_EXE_MEM),
.RegRdata1_EXE_MEM (RegRdata1_EXE_MEM),
.RegRdata2_EXE_MEM (RegRdata2_EXE_MEM),
.Bypass_EXE ( Bypass_EXE),
.cp0Rdata_EXE ( CP0Rdata),
.mfc0_ID_EXE ( mfc0_ID_EXE),
.mfc0_EXE_MEM ( mfc0_EXE_MEM),
.cp0Rdata_EXE_MEM ( cp0Rdata_EXE_MEM),
.Exc_BadVaddr ( Exc_BadVaddr),
.Exc_EPC ( Exc_EPC),
.Exc_Vec ( Exc_Vec),
.Exc_BD ( Exc_BD ),
.ex_int_handle ( ex_int_handle)
);
memory_stage mem_stage(
.clk ( clk),
.rst ( rst),
.MemEn_EXE_MEM ( MemEn_EXE_MEM),
.MemToReg_EXE_MEM ( MemToReg_EXE_MEM),
.MemWrite_EXE_MEM ( MemWrite_EXE_MEM),
.RegWrite_EXE_MEM ( RegWrite_EXE_MEM),
.RegWaddr_EXE_MEM ( RegWaddr_EXE_MEM),
.ALUResult_EXE_MEM (ALUResult_EXE_MEM),
.MemWdata_EXE_MEM ( MemWdata_EXE_MEM),
.RegRdata2_EXE_MEM (RegRdata2_EXE_MEM),
.PC_EXE_MEM ( PC_EXE_MEM),
.MFHL_EXE_MEM ( MFHL_EXE_MEM),
.LB_EXE_MEM ( LB_EXE_MEM),
.LBU_EXE_MEM ( LBU_EXE_MEM),
.LH_EXE_MEM ( LH_EXE_MEM),
.LHU_EXE_MEM ( LHU_EXE_MEM),
.LW_EXE_MEM ( LW_EXE_MEM),
.MemEn_MEM ( data_sram_en),
.MemWrite_MEM ( data_sram_wen),
.data_sram_addr ( data_sram_addr),
.MemWdata_MEM ( data_sram_wdata),
.MemToReg_MEM_WB ( MemToReg_MEM_WB),
.RegWrite_MEM_WB ( RegWrite_MEM_WB),
.LB_MEM_WB ( LB_MEM_WB),
.LBU_MEM_WB ( LBU_MEM_WB),
.LH_MEM_WB ( LH_MEM_WB),
.LHU_MEM_WB ( LHU_MEM_WB),
.LW_MEM_WB ( LW_MEM_WB),
.RegWaddr_MEM_WB ( RegWaddr_MEM_WB),
.ALUResult_MEM_WB ( ALUResult_MEM_WB),
.RegRdata2_MEM_WB ( RegRdata2_MEM_WB),
.PC_MEM_WB ( PC_MEM_WB),
.MFHL_MEM_WB ( MFHL_MEM_WB),
.Bypass_MEM ( Bypass_MEM),
.cp0Rdata_MEM_WB ( cp0Rdata_MEM_WB),
.mfc0_MEM_WB ( mfc0_MEM_WB),
.mfc0_EXE_MEM ( mfc0_EXE_MEM),
.cp0Rdata_EXE_MEM ( cp0Rdata_EXE_MEM)
);
writeback_stage wb_stage(
.clk ( clk),
.rst ( rst),
.MemToReg_MEM_WB ( MemToReg_MEM_WB),
.RegWrite_MEM_WB ( RegWrite_MEM_WB),
.MFHL_MEM_WB ( MFHL_MEM_WB),
.LB_MEM_WB ( LB_MEM_WB),
.LBU_MEM_WB ( LBU_MEM_WB),
.LH_MEM_WB ( LH_MEM_WB),
.LHU_MEM_WB ( LHU_MEM_WB),
.LW_MEM_WB ( LW_MEM_WB),
.RegWaddr_MEM_WB ( RegWaddr_MEM_WB),
.ALUResult_MEM_WB ( ALUResult_MEM_WB),
.RegRdata2_MEM_WB ( RegRdata2_MEM_WB),
.MemRdata_MEM_WB ( data_sram_rdata),
.PC_MEM_WB ( PC_MEM_WB),
.HI_MEM_WB ( HI_out),
.LO_MEM_WB ( LO_out),
.RegWdata_WB ( RegWdata_WB),
.RegWdata_Bypass_WB(RegWdata_Bypass_WB),
.RegWaddr_WB ( RegWaddr_WB),
.RegWrite_WB ( RegWrite_WB),
.PC_WB ( PC_WB),
.cp0Rdata_MEM_WB ( cp0Rdata_MEM_WB),
.mfc0_MEM_WB ( mfc0_MEM_WB)
);
Bypass_Unit bypass_unit(
.clk ( clk),
.rst ( rst),
.is_rs_read ( is_rs_read),
.is_rt_read ( is_rt_read),
.MemToReg_ID_EXE ( MemToReg_ID_EXE),
.MemToReg_EXE_MEM ( MemToReg_EXE_MEM),
.MemToReg_MEM_WB ( MemToReg_MEM_WB),
.RegWaddr_EXE_MEM ( RegWaddr_EXE_MEM),
.RegWaddr_MEM_WB ( RegWaddr_MEM_WB),
.RegWaddr_ID_EXE ( RegWaddr_ID_EXE),
.rs_ID (Inst_IF_ID[25:21]),
.rt_ID (Inst_IF_ID[20:16]),
.RegWrite_ID_EXE ( RegWrite_ID_EXE),
.RegWrite_EXE_MEM ( RegWrite_EXE_MEM),
.RegWrite_MEM_WB ( RegWrite_MEM_WB),
.DIV_Busy ( DIV_Busy),
.DIV ( |DIV_ID_EXE),
.ex_int_handle ( ex_int_handle),
.PCWrite ( PCWrite),
.IRWrite ( IRWrite),
.ID_EXE_Stall ( ID_EXE_Stall),
.RegRdata1_src ( RegRdata1_src),
.RegRdata2_src ( RegRdata2_src)
);
reg_file RegFile(
.clk ( clk),
.rst ( rst),
.waddr ( RegWaddr_WB),
.raddr1 ( RegRaddr1),
.raddr2 ( RegRaddr2),
.wen ( RegWrite_WB),
.wdata ( RegWdata_WB),
.rdata1 ( RegRdata1),
.rdata2 ( RegRdata2)
);
cp0reg cp0(
.clk ( clk),
.rst ( rst),
.eret ( eret_ID_EXE),
.int ( int_i),
.Exc_BD ( Exc_BD),
.Exc_Vec ( Exc_Vec),
.waddr ( CP0Waddr),
.raddr ( CP0Raddr),
.wen ( cp0_Write_ID_EXE),
.wdata ( CP0Wdata),
.epc_in ( Exc_EPC),
.Exc_BadVaddr ( Exc_BadVaddr),
.rdata ( CP0Rdata),
.epc_value ( epc),
.ex_int_handle ( ex_int_handle),
.eret_handle ( eret_handle)
);
multiplyer mul(
.x ( RegRdata1_ID_EXE),
.y ( RegRdata2_ID_EXE),
.mul_clk ( clk),
.resetn ( resetn),
.clken ( |MULT_ID_EXE),
.mul_signed (MULT_ID_EXE[0]&~MULT_ID_EXE[1]),
.result ( MULT_Result)
);
divider div(
.div_clk ( clk),
.rst ( rst),
.x ( RegRdata1_ID_EXE),
.y ( RegRdata2_ID_EXE),
.div ( |DIV_ID_EXE),
.div_signed ( DIV_ID_EXE[0]&~DIV_ID_EXE[1]),
.s ( DIV_quotient),
.r ( DIV_remainder),
.busy ( DIV_Busy),
.complete ( DIV_Complete)
);
HILO HILO(
.clk ( clk),
.rst ( rst),
.HI_in ( HI_in),
.LO_in ( LO_in),
.HILO_Write ( HILO_Write),
.HI_out ( HI_out),
.LO_out ( LO_out)
);
assign HI_in = |MULT_EXE_MEM ? MULT_Result[63:32] :
MTHL_EXE_MEM[1] ? RegRdata1_EXE_MEM :
DIV_Complete ? DIV_remainder : 'd0;
assign LO_in = |MULT_EXE_MEM ? MULT_Result[31: 0] :
MTHL_EXE_MEM[0] ? RegRdata1_EXE_MEM :
DIV_Complete ? DIV_quotient : 'd0;
assign HILO_Write[1] = |MULT_EXE_MEM | DIV_Complete | MTHL_EXE_MEM[1];
assign HILO_Write[0] = |MULT_EXE_MEM | DIV_Complete | MTHL_EXE_MEM[0];
assign CP0Waddr = Rd_ID_EXE;
assign CP0Wdata = RegRdata2_ID_EXE;
assign CP0Raddr = Rd_ID_EXE;
`ifdef SIMU_DEBUG
assign debug_wb_pc = PC_WB;
assign debug_wb_rf_wen = RegWrite_WB;
assign debug_wb_rf_wnum = RegWaddr_WB;
assign debug_wb_rf_wdata = RegWdata_WB;
`endif
endmodule | module mycpu(
input clk,
input resetn,
input [ 5:0] int_i,
output inst_req,
output [ 1:0] inst_size,
output [31:0] inst_addr,
input [31:0] inst_rdata,
input inst_addr_ok,
input inst_data_ok,
output data_req,
output data_wr,
output [ 1:0] data_rsize,
output [31:0] data_raddr,
input [31:0] data_rdata,
input data_raddr_ok,
input data_rdata_ok,
output [ 1:0] data_wsize,
output [31:0] data_waddr,
input [31:0] data_wdata,
input data_waddr_ok,
input data_wdata_ok
`ifdef SIMU_DEBUG
,output [31:0] debug_wb_pc,
output [ 3:0] debug_wb_rf_wen,
output [ 4:0] debug_wb_rf_wnum,
output [31:0] debug_wb_rf_wdata
`endif
); |
wire rst = ~resetn;
wire JSrc;
wire [ 1:0] PCSrc;
wire [ 4:0] RegRaddr1;
wire [ 4:0] RegRaddr2;
wire [31:0] RegRdata1;
wire [31:0] RegRdata2;
wire DSI_ID;
wire DSI_IF_ID;
wire [31:0] PC_next;
wire [31:0] PC_IF_ID;
wire [31:0] PC_add_4_IF_ID;
wire PC_AdEL_IF_ID;
wire PC_AdEL;
wire [31:0] Inst_IF_ID;
wire PCWrite;
wire IRWrite;
wire [31:0] J_target_ID;
wire [31:0] JR_target_ID;
wire [31:0] Br_target_ID;
wire [31:0] PC_add_4_ID;
wire [ 1:0] RegRdata1_src;
wire [ 1:0] RegRdata2_src;
wire is_rs_read;
wire is_rt_read;
wire ID_EXE_Stall;
wire [31:0] PC_ID_EXE;
wire [31:0] PC_add_4_ID_EXE;
wire [ 1:0] RegDst_ID_EXE;
wire [ 1:0] ALUSrcA_ID_EXE;
wire [ 1:0] ALUSrcB_ID_EXE;
wire [ 3:0] ALUop_ID_EXE;
wire [ 3:0] RegWrite_ID_EXE;
wire [ 3:0] MemWrite_ID_EXE;
wire is_signed_ID_EXE;
wire MemEn_ID_EXE;
wire MemToReg_ID_EXE;
wire [ 1:0] MULT_ID_EXE;
wire [ 1:0] DIV_ID_EXE;
wire [ 1:0] MFHL_ID_EXE;
wire [ 1:0] MTHL_ID_EXE;
wire LB_ID_EXE;
wire LBU_ID_EXE;
wire LH_ID_EXE;
wire LHU_ID_EXE;
wire [ 1:0] LW_ID_EXE;
wire [ 1:0] SW_ID_EXE;
wire SB_ID_EXE;
wire SH_ID_EXE;
wire [ 4:0] RegWaddr_ID_EXE;
wire [31:0] ALUResult_EXE;
wire [31:0] ALUResult_MEM;
wire [31:0] RegRdata1_ID_EXE;
wire [31:0] RegRdata2_ID_EXE;
wire [31:0] Sa_ID_EXE;
wire [31:0] SgnExtend_ID_EXE;
wire [31:0] ZExtend_ID_EXE;
wire MemEn_EXE_MEM;
wire MemToReg_EXE_MEM;
wire [ 3:0] MemWrite_EXE_MEM;
wire [ 3:0] RegWrite_EXE_MEM;
wire [ 3:0] RegWrite_EXE;
wire [ 4:0] RegWaddr_EXE_MEM;
wire [ 1:0] MULT_EXE_MEM;
wire [ 1:0] MFHL_EXE_MEM;
wire [ 1:0] MTHL_EXE_MEM;
wire LB_EXE_MEM;
wire LBU_EXE_MEM;
wire LH_EXE_MEM;
wire LHU_EXE_MEM;
wire [ 1:0] LW_EXE_MEM;
wire [31:0] ALUResult_EXE_MEM;
wire [31:0] MemWdata_EXE_MEM;
wire [31:0] PC_EXE_MEM;
wire [31:0] RegRdata1_EXE_MEM;
wire [31:0] RegRdata2_EXE_MEM;
wire MemToReg_MEM_WB;
wire [ 3:0] RegWrite_MEM_WB;
wire [ 4:0] RegWaddr_MEM_WB;
wire [ 1:0] MFHL_MEM_WB;
wire LB_MEM_WB;
wire LBU_MEM_WB;
wire LH_MEM_WB;
wire LHU_MEM_WB;
wire [ 1:0] LW_MEM_WB;
wire [31:0] ALUResult_MEM_WB;
wire [31:0] RegRdata2_MEM_WB;
wire [31:0] PC_MEM_WB;
wire [31:0] PC_WB;
wire [31:0] RegWdata_WB;
wire [ 4:0] RegWaddr_WB;
wire [ 3:0] RegWrite_WB;
wire [31:0] RegWdata_Bypass_WB;
wire [63:0] MULT_Result;
wire [31:0] DIV_quotient;
wire [31:0] DIV_remainder;
wire DIV_Busy;
wire DIV_Complete;
wire [31:0] HI_in;
wire [31:0] LO_in;
wire [ 1:0] HILO_Write;
wire [31:0] HI_out;
wire [31:0] LO_out;
wire [31:0] CP0Raddr;
wire [31:0] CP0Rdata;
wire [31:0] CP0Waddr;
wire [31:0] CP0Wdata;
wire [ 3:0] CP0Write;
wire [31:0] epc;
wire [ 4:0] rd;
wire [31:0] RegRdata2_Final;
wire [31:0] cp0Rdata_EXE_MEM;
wire [31:0] cp0Rdata_MEM_WB;
wire mfc0_ID_EXE;
wire mfc0_EXE_MEM;
wire mfc0_MEM_WB;
wire [31:0] Bypass_EXE;
wire [31:0] Bypass_MEM;
wire [31:0] Exc_BadVaddr;
wire [31:0] Exc_EPC;
wire [ 5:0] Exc_Cause;
wire ex_int_handle;
wire eret_handle;
wire [ 6:0] Exc_Vec;
wire DSI_ID_EXE,eret_ID_EXE,cp0_Write_ID_EXE,Exc_BD;
wire [ 4:0] Rd_ID_EXE;
wire [ 3:0] Exc_vec_ID_EXE;
wire PC_abnormal;
nextpc_gen nextpc_gen(
.clk ( clk),
.rst ( rst),
.PCWrite ( PCWrite),
.JSrc ( JSrc),
.PCSrc ( PCSrc),
.eret ( eret_handle),
.epc ( epc),
.JR_target ( JR_target_ID),
.J_target ( J_target_ID),
.Br_addr ( Br_target_ID),
.inst_sram_addr ( inst_sram_addr),
.PC_next ( PC_next),
.PC_AdEL ( PC_AdEL),
.ex_int_handle ( ex_int_handle),
.PC_abnormal ( PC_abnormal)
);
fetch_stage fe_stage(
.clk ( clk),
.rst ( rst),
.DSI_ID ( DSI_ID),
.IRWrite ( IRWrite),
.PC_AdEL ( PC_AdEL),
.PC_next ( PC_next),
.PC_abnormal ( PC_abnormal),
.inst_sram_en ( inst_sram_en),
.inst_sram_rdata ( inst_sram_rdata),
.PC_IF_ID ( PC_IF_ID),
.PC_add_4_IF_ID ( PC_add_4_IF_ID),
.Inst_IF_ID ( Inst_IF_ID),
.PC_AdEL_IF_ID ( PC_AdEL_IF_ID),
.DSI_IF_ID ( DSI_IF_ID)
);
decode_stage de_stage(
.clk ( clk),
.rst ( rst),
.Inst_IF_ID ( Inst_IF_ID),
.PC_IF_ID ( PC_IF_ID),
.PC_add_4_IF_ID ( PC_add_4_IF_ID),
.DSI_IF_ID ( DSI_IF_ID),
.PC_AdEL_IF_ID ( PC_AdEL_IF_ID),
.ex_int_handle_ID ( ex_int_handle),
.RegRaddr1_ID ( RegRaddr1),
.RegRaddr2_ID ( RegRaddr2),
.RegRdata1_ID ( RegRdata1),
.RegRdata2_ID ( RegRdata2),
.Bypass_EXE ( Bypass_EXE),
.Bypass_MEM ( Bypass_MEM),
.RegWdata_WB (RegWdata_Bypass_WB),
.MULT_Result ( MULT_Result),
.HI ( HI_out),
.LO ( LO_out),
.MFHL_ID_EXE_1 ( MFHL_ID_EXE),
.MFHL_EXE_MEM ( MFHL_EXE_MEM),
.MFHL_MEM_WB ( MFHL_MEM_WB),
.MULT_EXE_MEM ( MULT_EXE_MEM),
.RegRdata1_src ( RegRdata1_src),
.RegRdata2_src ( RegRdata2_src),
.ID_EXE_Stall ( ID_EXE_Stall),
.DIV_Complete ( DIV_Complete),
.JSrc ( JSrc),
.PCSrc ( PCSrc),
.J_target_ID ( J_target_ID),
.JR_target_ID ( JR_target_ID),
.Br_target_ID ( Br_target_ID),
.ALUSrcA_ID_EXE ( ALUSrcA_ID_EXE),
.ALUSrcB_ID_EXE ( ALUSrcB_ID_EXE),
.ALUop_ID_EXE ( ALUop_ID_EXE),
.RegWrite_ID_EXE ( RegWrite_ID_EXE),
.MemWrite_ID_EXE ( MemWrite_ID_EXE),
.MemEn_ID_EXE ( MemEn_ID_EXE),
.MemToReg_ID_EXE ( MemToReg_ID_EXE),
.is_signed_ID_EXE ( is_signed_ID_EXE),
.MULT_ID_EXE ( MULT_ID_EXE),
.DIV_ID_EXE ( DIV_ID_EXE),
.MFHL_ID_EXE ( MFHL_ID_EXE),
.MTHL_ID_EXE ( MTHL_ID_EXE),
.LB_ID_EXE ( LB_ID_EXE),
.LBU_ID_EXE ( LBU_ID_EXE),
.LH_ID_EXE ( LH_ID_EXE),
.LHU_ID_EXE ( LHU_ID_EXE),
.LW_ID_EXE ( LW_ID_EXE),
.SW_ID_EXE ( SW_ID_EXE),
.SB_ID_EXE ( SB_ID_EXE),
.SH_ID_EXE ( SH_ID_EXE),
.DSI_ID_EXE ( DSI_ID_EXE),
.eret_ID_EXE ( eret_ID_EXE),
.Rd_ID_EXE ( Rd_ID_EXE),
.Exc_vec_ID_EXE ( Exc_vec_ID_EXE),
.RegWaddr_ID_EXE ( RegWaddr_ID_EXE),
.PC_add_4_ID_EXE ( PC_add_4_ID_EXE),
.PC_ID_EXE ( PC_ID_EXE),
.RegRdata1_ID_EXE ( RegRdata1_ID_EXE),
.RegRdata2_ID_EXE ( RegRdata2_ID_EXE),
.Sa_ID_EXE ( Sa_ID_EXE),
.SgnExtend_ID_EXE ( SgnExtend_ID_EXE),
.ZExtend_ID_EXE ( ZExtend_ID_EXE),
.cp0_Write_ID_EXE ( cp0_Write_ID_EXE),
.mfc0_ID_EXE ( mfc0_ID_EXE),
.is_rs_read_ID ( is_rs_read),
.is_rt_read_ID ( is_rt_read),
.is_j_or_br_ID ( DSI_ID)
);
execute_stage exe_stage(
.clk ( clk),
.rst ( rst),
.PC_add_4_ID_EXE ( PC_add_4_ID_EXE),
.cp0_Write_ID_EXE ( cp0_Write_ID_EXE),
.PC_ID_EXE ( PC_ID_EXE),
.RegRdata1_ID_EXE ( RegRdata1_ID_EXE),
.RegRdata2_ID_EXE ( RegRdata2_ID_EXE),
.Sa_ID_EXE ( Sa_ID_EXE),
.SgnExtend_ID_EXE ( SgnExtend_ID_EXE),
.ZExtend_ID_EXE ( ZExtend_ID_EXE),
.RegWaddr_ID_EXE ( RegWaddr_ID_EXE),
.MemEn_ID_EXE ( MemEn_ID_EXE),
.MemToReg_ID_EXE ( MemToReg_ID_EXE),
.is_signed_ID_EXE ( is_signed_ID_EXE),
.DSI_ID_EXE ( DSI_ID_EXE),
.Rd_ID_EXE ( Rd_ID_EXE),
.Exc_vec_ID_EXE ( Exc_vec_ID_EXE),
.ALUSrcA_ID_EXE ( ALUSrcA_ID_EXE),
.ALUSrcB_ID_EXE ( ALUSrcB_ID_EXE),
.ALUop_ID_EXE ( ALUop_ID_EXE),
.MemWrite_ID_EXE ( MemWrite_ID_EXE),
.RegWrite_ID_EXE ( RegWrite_ID_EXE),
.MULT_ID_EXE ( MULT_ID_EXE),
.MFHL_ID_EXE ( MFHL_ID_EXE),
.MTHL_ID_EXE ( MTHL_ID_EXE),
.LB_ID_EXE ( LB_ID_EXE),
.LBU_ID_EXE ( LBU_ID_EXE),
.LH_ID_EXE ( LH_ID_EXE),
.LHU_ID_EXE ( LHU_ID_EXE),
.LW_ID_EXE ( LW_ID_EXE),
.SW_ID_EXE ( SW_ID_EXE),
.SB_ID_EXE ( SB_ID_EXE),
.SH_ID_EXE ( SH_ID_EXE),
.MemEn_EXE_MEM ( MemEn_EXE_MEM),
.MemToReg_EXE_MEM ( MemToReg_EXE_MEM),
.MemWrite_EXE_MEM ( MemWrite_EXE_MEM),
.RegWrite_EXE_MEM ( RegWrite_EXE_MEM),
.MULT_EXE_MEM ( MULT_EXE_MEM),
.MFHL_EXE_MEM ( MFHL_EXE_MEM),
.MTHL_EXE_MEM ( MTHL_EXE_MEM),
.LB_EXE_MEM ( LB_EXE_MEM),
.LBU_EXE_MEM ( LBU_EXE_MEM),
.LH_EXE_MEM ( LH_EXE_MEM),
.LHU_EXE_MEM ( LHU_EXE_MEM),
.LW_EXE_MEM ( LW_EXE_MEM),
.RegWaddr_EXE_MEM ( RegWaddr_EXE_MEM),
.ALUResult_EXE_MEM (ALUResult_EXE_MEM),
.MemWdata_EXE_MEM ( MemWdata_EXE_MEM),
.PC_EXE_MEM ( PC_EXE_MEM),
.RegRdata1_EXE_MEM (RegRdata1_EXE_MEM),
.RegRdata2_EXE_MEM (RegRdata2_EXE_MEM),
.Bypass_EXE ( Bypass_EXE),
.cp0Rdata_EXE ( CP0Rdata),
.mfc0_ID_EXE ( mfc0_ID_EXE),
.mfc0_EXE_MEM ( mfc0_EXE_MEM),
.cp0Rdata_EXE_MEM ( cp0Rdata_EXE_MEM),
.Exc_BadVaddr ( Exc_BadVaddr),
.Exc_EPC ( Exc_EPC),
.Exc_Vec ( Exc_Vec),
.Exc_BD ( Exc_BD ),
.ex_int_handle ( ex_int_handle)
);
memory_stage mem_stage(
.clk ( clk),
.rst ( rst),
.MemEn_EXE_MEM ( MemEn_EXE_MEM),
.MemToReg_EXE_MEM ( MemToReg_EXE_MEM),
.MemWrite_EXE_MEM ( MemWrite_EXE_MEM),
.RegWrite_EXE_MEM ( RegWrite_EXE_MEM),
.RegWaddr_EXE_MEM ( RegWaddr_EXE_MEM),
.ALUResult_EXE_MEM (ALUResult_EXE_MEM),
.MemWdata_EXE_MEM ( MemWdata_EXE_MEM),
.RegRdata2_EXE_MEM (RegRdata2_EXE_MEM),
.PC_EXE_MEM ( PC_EXE_MEM),
.MFHL_EXE_MEM ( MFHL_EXE_MEM),
.LB_EXE_MEM ( LB_EXE_MEM),
.LBU_EXE_MEM ( LBU_EXE_MEM),
.LH_EXE_MEM ( LH_EXE_MEM),
.LHU_EXE_MEM ( LHU_EXE_MEM),
.LW_EXE_MEM ( LW_EXE_MEM),
.MemEn_MEM ( data_sram_en),
.MemWrite_MEM ( data_sram_wen),
.data_sram_addr ( data_sram_addr),
.MemWdata_MEM ( data_sram_wdata),
.MemToReg_MEM_WB ( MemToReg_MEM_WB),
.RegWrite_MEM_WB ( RegWrite_MEM_WB),
.LB_MEM_WB ( LB_MEM_WB),
.LBU_MEM_WB ( LBU_MEM_WB),
.LH_MEM_WB ( LH_MEM_WB),
.LHU_MEM_WB ( LHU_MEM_WB),
.LW_MEM_WB ( LW_MEM_WB),
.RegWaddr_MEM_WB ( RegWaddr_MEM_WB),
.ALUResult_MEM_WB ( ALUResult_MEM_WB),
.RegRdata2_MEM_WB ( RegRdata2_MEM_WB),
.PC_MEM_WB ( PC_MEM_WB),
.MFHL_MEM_WB ( MFHL_MEM_WB),
.Bypass_MEM ( Bypass_MEM),
.cp0Rdata_MEM_WB ( cp0Rdata_MEM_WB),
.mfc0_MEM_WB ( mfc0_MEM_WB),
.mfc0_EXE_MEM ( mfc0_EXE_MEM),
.cp0Rdata_EXE_MEM ( cp0Rdata_EXE_MEM)
);
writeback_stage wb_stage(
.clk ( clk),
.rst ( rst),
.MemToReg_MEM_WB ( MemToReg_MEM_WB),
.RegWrite_MEM_WB ( RegWrite_MEM_WB),
.MFHL_MEM_WB ( MFHL_MEM_WB),
.LB_MEM_WB ( LB_MEM_WB),
.LBU_MEM_WB ( LBU_MEM_WB),
.LH_MEM_WB ( LH_MEM_WB),
.LHU_MEM_WB ( LHU_MEM_WB),
.LW_MEM_WB ( LW_MEM_WB),
.RegWaddr_MEM_WB ( RegWaddr_MEM_WB),
.ALUResult_MEM_WB ( ALUResult_MEM_WB),
.RegRdata2_MEM_WB ( RegRdata2_MEM_WB),
.MemRdata_MEM_WB ( data_sram_rdata),
.PC_MEM_WB ( PC_MEM_WB),
.HI_MEM_WB ( HI_out),
.LO_MEM_WB ( LO_out),
.RegWdata_WB ( RegWdata_WB),
.RegWdata_Bypass_WB(RegWdata_Bypass_WB),
.RegWaddr_WB ( RegWaddr_WB),
.RegWrite_WB ( RegWrite_WB),
.PC_WB ( PC_WB),
.cp0Rdata_MEM_WB ( cp0Rdata_MEM_WB),
.mfc0_MEM_WB ( mfc0_MEM_WB)
);
Bypass_Unit bypass_unit(
.clk ( clk),
.rst ( rst),
.is_rs_read ( is_rs_read),
.is_rt_read ( is_rt_read),
.MemToReg_ID_EXE ( MemToReg_ID_EXE),
.MemToReg_EXE_MEM ( MemToReg_EXE_MEM),
.MemToReg_MEM_WB ( MemToReg_MEM_WB),
.RegWaddr_EXE_MEM ( RegWaddr_EXE_MEM),
.RegWaddr_MEM_WB ( RegWaddr_MEM_WB),
.RegWaddr_ID_EXE ( RegWaddr_ID_EXE),
.rs_ID (Inst_IF_ID[25:21]),
.rt_ID (Inst_IF_ID[20:16]),
.RegWrite_ID_EXE ( RegWrite_ID_EXE),
.RegWrite_EXE_MEM ( RegWrite_EXE_MEM),
.RegWrite_MEM_WB ( RegWrite_MEM_WB),
.DIV_Busy ( DIV_Busy),
.DIV ( |DIV_ID_EXE),
.ex_int_handle ( ex_int_handle),
.PCWrite ( PCWrite),
.IRWrite ( IRWrite),
.ID_EXE_Stall ( ID_EXE_Stall),
.RegRdata1_src ( RegRdata1_src),
.RegRdata2_src ( RegRdata2_src)
);
reg_file RegFile(
.clk ( clk),
.rst ( rst),
.waddr ( RegWaddr_WB),
.raddr1 ( RegRaddr1),
.raddr2 ( RegRaddr2),
.wen ( RegWrite_WB),
.wdata ( RegWdata_WB),
.rdata1 ( RegRdata1),
.rdata2 ( RegRdata2)
);
cp0reg cp0(
.clk ( clk),
.rst ( rst),
.eret ( eret_ID_EXE),
.int ( int_i),
.Exc_BD ( Exc_BD),
.Exc_Vec ( Exc_Vec),
.waddr ( CP0Waddr),
.raddr ( CP0Raddr),
.wen ( cp0_Write_ID_EXE),
.wdata ( CP0Wdata),
.epc_in ( Exc_EPC),
.Exc_BadVaddr ( Exc_BadVaddr),
.rdata ( CP0Rdata),
.epc_value ( epc),
.ex_int_handle ( ex_int_handle),
.eret_handle ( eret_handle)
);
multiplyer mul(
.x ( RegRdata1_ID_EXE),
.y ( RegRdata2_ID_EXE),
.mul_clk ( clk),
.resetn ( resetn),
.clken ( |MULT_ID_EXE),
.mul_signed (MULT_ID_EXE[0]&~MULT_ID_EXE[1]),
.result ( MULT_Result)
);
divider div(
.div_clk ( clk),
.rst ( rst),
.x ( RegRdata1_ID_EXE),
.y ( RegRdata2_ID_EXE),
.div ( |DIV_ID_EXE),
.div_signed ( DIV_ID_EXE[0]&~DIV_ID_EXE[1]),
.s ( DIV_quotient),
.r ( DIV_remainder),
.busy ( DIV_Busy),
.complete ( DIV_Complete)
);
HILO HILO(
.clk ( clk),
.rst ( rst),
.HI_in ( HI_in),
.LO_in ( LO_in),
.HILO_Write ( HILO_Write),
.HI_out ( HI_out),
.LO_out ( LO_out)
);
assign HI_in = |MULT_EXE_MEM ? MULT_Result[63:32] :
MTHL_EXE_MEM[1] ? RegRdata1_EXE_MEM :
DIV_Complete ? DIV_remainder : 'd0;
assign LO_in = |MULT_EXE_MEM ? MULT_Result[31: 0] :
MTHL_EXE_MEM[0] ? RegRdata1_EXE_MEM :
DIV_Complete ? DIV_quotient : 'd0;
assign HILO_Write[1] = |MULT_EXE_MEM | DIV_Complete | MTHL_EXE_MEM[1];
assign HILO_Write[0] = |MULT_EXE_MEM | DIV_Complete | MTHL_EXE_MEM[0];
assign CP0Waddr = Rd_ID_EXE;
assign CP0Wdata = RegRdata2_ID_EXE;
assign CP0Raddr = Rd_ID_EXE;
`ifdef SIMU_DEBUG
assign debug_wb_pc = PC_WB;
assign debug_wb_rf_wen = RegWrite_WB;
assign debug_wb_rf_wnum = RegWaddr_WB;
assign debug_wb_rf_wdata = RegWdata_WB;
`endif
endmodule | 0 |
4,907 | data/full_repos/permissive/112219256/mycpu_top.v | 112,219,256 | mycpu_top.v | v | 919 | 127 | [] | [] | [] | [(15, 918)] | null | null | 1: b'%Error: data/full_repos/permissive/112219256/mycpu_top.v:710: syntax error, unexpected int\n .int ( int_i), \n ^~~\n%Error: Exiting due to 1 error(s)\n' | 3,314 | module | module mycpu_top(
input clk,
input resetn,
input [ 5:0] int_i,
output [ 3:0] cpu_arid,
output [31:0] cpu_araddr,
output [ 7:0] cpu_arlen,
output [ 2:0] cpu_arsize,
output [ 1:0] cpu_arburst,
output [ 1:0] cpu_arlock,
output [ 3:0] cpu_arcache,
output [ 2:0] cpu_arprot,
output cpu_arvalid,
input cpu_arready,
input [ 3:0] cpu_rid,
input [31:0] cpu_rdata,
input [ 1:0] cpu_rresp,
input cpu_rlast,
input cpu_rvalid,
output cpu_rready,
output [ 3:0] cpu_awid,
output [31:0] cpu_awaddr,
output [ 7:0] cpu_awlen,
output [ 2:0] cpu_awsize,
output [ 1:0] cpu_awburst,
output [ 1:0] cpu_awlock,
output [ 3:0] cpu_awcache,
output [ 2:0] cpu_awprot,
output cpu_awvalid,
input cpu_awready,
output [ 3:0] cpu_wid,
output [31:0] cpu_wdata,
output [ 3:0] cpu_wstrb,
output cpu_wlast,
output cpu_wvalid,
input cpu_wready,
input [ 3:0] cpu_bid,
input [ 1:0] cpu_bresp,
input cpu_bvalid,
output cpu_bready
`ifdef SIMU_DEBUG
,output wire [31:0] debug_wb_pc,
output wire [ 3:0] debug_wb_rf_wen,
output wire [ 4:0] debug_wb_rf_wnum,
output wire [31:0] debug_wb_rf_wdata
`endif
);
wire rst = ~resetn;
wire JSrc;
wire [ 1:0] PCSrc;
wire [ 4:0] RegRaddr1;
wire [ 4:0] RegRaddr2;
wire [31:0] RegRdata1;
wire [31:0] RegRdata2;
wire DSI_ID;
wire DSI_IF_ID;
wire [31:0] PC_next;
wire [31:0] PC_IF_ID;
wire [31:0] PC_add_4_IF_ID;
wire PC_AdEL_IF_ID;
wire PC_AdEL;
wire [31:0] IR_IF_ID;
wire PCWrite;
wire IRWrite;
wire [31:0] J_target_ID;
wire [31:0] JR_target_ID;
wire [31:0] Br_target_ID;
wire [31:0] PC_add_4_ID;
wire [ 1:0] RegRdata1_src;
wire [ 1:0] RegRdata2_src;
wire is_rs_read;
wire is_rt_read;
wire ID_EXE_Stall;
wire [31:0] PC_ID_EXE;
wire [31:0] PC_add_4_ID_EXE;
wire [ 1:0] RegDst_ID_EXE;
wire [ 1:0] ALUSrcA_ID_EXE;
wire [ 1:0] ALUSrcB_ID_EXE;
wire [ 3:0] ALUop_ID_EXE;
wire [ 3:0] RegWrite_ID_EXE;
wire [ 3:0] MemWrite_ID_EXE;
wire is_signed_ID_EXE;
wire MemEn_ID_EXE;
wire MemToReg_ID_EXE;
wire [ 1:0] MULT_ID_EXE;
wire [ 1:0] DIV_ID_EXE;
wire [ 1:0] MFHL_ID_EXE;
wire [ 1:0] MTHL_ID_EXE;
wire LB_ID_EXE;
wire LBU_ID_EXE;
wire LH_ID_EXE;
wire LHU_ID_EXE;
wire [ 1:0] LW_ID_EXE;
wire [ 1:0] SW_ID_EXE;
wire SB_ID_EXE;
wire SH_ID_EXE;
wire [ 4:0] RegWaddr_ID_EXE;
wire [31:0] ALUResult_EXE;
wire [31:0] ALUResult_MEM;
wire [ 1:0] DIV_EXE;
wire [ 1:0] MULT_EXE;
wire [31:0] RegRdata1_ID_EXE;
wire [31:0] RegRdata2_ID_EXE;
wire [31:0] Sa_ID_EXE;
wire [31:0] SgnExtend_ID_EXE;
wire [31:0] ZExtend_ID_EXE;
wire MemEn_EXE_MEM;
wire MemToReg_EXE_MEM;
wire [ 3:0] MemWrite_EXE_MEM;
wire [ 3:0] RegWrite_EXE_MEM;
wire [ 3:0] RegWrite_EXE;
wire [ 4:0] RegWaddr_EXE_MEM;
wire [ 1:0] MULT_EXE_MEM;
wire [ 1:0] MFHL_EXE_MEM;
wire [ 1:0] MTHL_EXE_MEM;
wire LB_EXE_MEM;
wire LBU_EXE_MEM;
wire LH_EXE_MEM;
wire LHU_EXE_MEM;
wire [ 1:0] LW_EXE_MEM;
wire [31:0] ALUResult_EXE_MEM;
wire [31:0] MemWdata_EXE_MEM;
wire [31:0] PC_EXE_MEM;
wire [31:0] RegRdata1_EXE_MEM;
wire [31:0] RegRdata2_EXE_MEM;
wire [ 1:0] s_vaddr_EXE_MEM;
wire [ 2:0] s_size_EXE_MEM;
wire [ 1:0] MULT_MEM;
wire [ 1:0] MTHL_MEM;
wire MemToReg_MEM_WB;
wire [ 3:0] RegWrite_MEM_WB;
wire [ 4:0] RegWaddr_MEM_WB;
wire [ 1:0] MFHL_MEM_WB;
wire LB_MEM_WB;
wire LBU_MEM_WB;
wire LH_MEM_WB;
wire LHU_MEM_WB;
wire [ 1:0] LW_MEM_WB;
wire [31:0] ALUResult_MEM_WB;
wire [31:0] RegRdata2_MEM_WB;
wire [31:0] PC_MEM_WB;
wire [31:0] PC_WB;
wire [31:0] RegWdata_WB;
wire [ 4:0] RegWaddr_WB;
wire [ 3:0] RegWrite_WB;
wire [31:0] MemRdata_MEM_WB;
wire [31:0] RegWdata_Bypass_WB;
wire [63:0] MULT_Result ;
wire [31:0] DIV_quotient ;
wire [31:0] DIV_remainder ;
wire DIV_Busy ;
wire DIV_Complete ;
wire [31:0] HI_in ;
wire [31:0] LO_in ;
wire [ 1:0] HILO_Write ;
wire [31:0] HI_out ;
wire [31:0] LO_out ;
wire [ 4:0] CP0Raddr ;
wire [31:0] CP0Rdata ;
wire [ 4:0] CP0Waddr ;
wire [31:0] CP0Wdata ;
wire CP0Write ;
wire [31:0] epc ;
wire [ 4:0] rd ;
wire [31:0] RegRdata2_Final ;
wire [31:0] cp0Rdata_EXE_MEM ;
wire [31:0] cp0Rdata_MEM_WB ;
wire mfc0_ID_EXE ;
wire mfc0_EXE_MEM ;
wire mfc0_MEM_WB ;
wire [31:0] Bypass_EXE ;
wire [31:0] Bypass_MEM ;
wire [31:0] Exc_BadVaddr ;
wire [31:0] Exc_EPC ;
wire [ 5:0] Exc_Cause ;
wire ex_int_handle ;
wire ex_int_handling ;
wire eret_handle ;
wire eret_handling ;
wire DSI_ID_EXE ;
wire eret_ID_EXE ;
wire cp0_Write_ID_EXE ;
wire Exc_BD ;
wire [ 6:0] Exc_Vec ;
wire [ 4:0] Rd_ID_EXE ;
wire [ 3:0] Exc_vec_ID_EXE ;
wire [31:0] PC_buffer ;
wire PC_refresh ;
wire [ 1:0] data_r_req ;
wire do_req_raddr ;
wire mem_read_req;
wire [31:0] PC ;
wire [31:0] mem_axi_rdata ;
wire mem_axi_rvalid ;
wire [ 3:0] mem_axi_rid ;
wire mem_axi_rready ;
wire [ 3:0] mem_axi_arid ;
wire [31:0] mem_axi_araddr ;
wire [ 2:0] mem_axi_arsize ;
wire mem_axi_arready ;
wire mem_axi_arvalid ;
wire [ 3:0] mem_axi_awid ;
wire [31:0] mem_axi_awaddr ;
wire [ 2:0] mem_axi_awsize ;
wire mem_axi_awvalid ;
wire mem_axi_awready ;
wire [ 3:0] mem_axi_wid ;
wire [31:0] mem_axi_wdata ;
wire [ 3:0] mem_axi_wstrb ;
wire mem_axi_wvalid ;
wire mem_axi_wready ;
wire mem_axi_bready ;
wire [ 3:0] mem_axi_bid ;
wire mem_axi_bvalid ;
wire [ 1:0] mem_axi_bresp ;
wire fetch_axi_rready ;
wire fetch_axi_rvalid ;
wire fetch_axi_rdata ;
wire [ 3:0] fetch_axi_rid ;
wire fetch_axi_arready;
wire fetch_axi_arvalid;
wire [ 2:0] fetch_axi_arsize ;
wire fetch_axi_arid ;
wire decode_allowin ;
wire exe_allowin;
wire mem_allowin;
wire wb_allowin;
wire fe_to_de_valid;
wire de_to_exe_valid;
wire exe_to_mem_valid;
wire mem_to_wb_valid;
wire de_valid;
wire exe_valid;
wire mem_valid;
wire wb_valid;
wire exe_refresh;
wire exe_ready_go;
wire IR_buffer_valid;
wire j_or_b_ID;
nextpc_gen nextpc_gen(
.clk ( clk),
.rst ( rst),
.PCWrite ( PCWrite),
.JSrc ( JSrc),
.PCSrc ( PCSrc),
.eret ( eret_handle),
.epc ( epc),
.JR_target ( JR_target_ID),
.J_target ( J_target_ID),
.Br_addr ( Br_target_ID),
.PC_AdEL ( PC_AdEL),
.ex_int_handle ( ex_int_handle),
.PC ( PC),
.PC_buffer ( PC_buffer),
.PC_refresh ( PC_refresh)
);
fetch_stage fe_stage(
.clk ( clk),
.rst ( rst),
.DSI_ID ( DSI_ID),
.IRWrite ( IRWrite),
.PC_AdEL ( PC_AdEL),
.PC_IF_ID ( PC_IF_ID),
.PC_add_4_IF_ID ( PC_add_4_IF_ID),
.IR_IF_ID ( IR_IF_ID),
.PC_buffer ( PC_buffer),
.PC_AdEL_IF_ID ( PC_AdEL_IF_ID),
.DSI_IF_ID ( DSI_IF_ID),
.data_r_req ( data_r_req),
.fetch_axi_rready (fetch_axi_rready ),
.fetch_axi_rvalid ( cpu_rvalid ),
.fetch_axi_rdata ( cpu_rdata ),
.fetch_axi_rid ( cpu_rid ),
.fetch_axi_arready ( cpu_arready),
.fe_to_de_valid ( fe_to_de_valid),
.decode_allowin (decode_allowin ),
.IR_buffer_valid ( IR_buffer_valid)
);
decode_stage de_stage(
.clk ( clk),
.rst ( rst),
.Inst_IF_ID ( IR_IF_ID),
.PC_IF_ID ( PC_IF_ID),
.PC_add_4_IF_ID ( PC_add_4_IF_ID),
.DSI_IF_ID ( DSI_IF_ID),
.PC_AdEL_IF_ID ( PC_AdEL_IF_ID),
.ex_int_handle_ID ( ex_int_handle),
.RegRaddr1_ID ( RegRaddr1),
.RegRaddr2_ID ( RegRaddr2),
.RegRdata1_ID ( RegRdata1),
.RegRdata2_ID ( RegRdata2),
.Bypass_EXE ( Bypass_EXE),
.Bypass_MEM ( Bypass_MEM),
.RegWdata_WB (RegWdata_Bypass_WB),
.MULT_Result ( MULT_Result),
.HI ( HI_out),
.LO ( LO_out),
.MFHL_ID_EXE_1 ( MFHL_ID_EXE),
.MFHL_EXE_MEM ( MFHL_EXE_MEM),
.MFHL_MEM_WB ( MFHL_MEM_WB),
.MULT_EXE_MEM ( MULT_EXE_MEM),
.RegRdata1_src ( RegRdata1_src),
.RegRdata2_src ( RegRdata2_src),
.ID_EXE_Stall ( ID_EXE_Stall),
.DIV_Complete ( DIV_Complete),
.JSrc ( JSrc),
.PCSrc ( PCSrc),
.J_target_ID ( J_target_ID),
.JR_target_ID ( JR_target_ID),
.Br_target_ID ( Br_target_ID),
.ALUSrcA_ID_EXE ( ALUSrcA_ID_EXE),
.ALUSrcB_ID_EXE ( ALUSrcB_ID_EXE),
.ALUop_ID_EXE ( ALUop_ID_EXE),
.RegWrite_ID_EXE ( RegWrite_ID_EXE),
.MemWrite_ID_EXE ( MemWrite_ID_EXE),
.MemEn_ID_EXE ( MemEn_ID_EXE),
.MemToReg_ID_EXE ( MemToReg_ID_EXE),
.is_signed_ID_EXE ( is_signed_ID_EXE),
.MULT_ID_EXE ( MULT_ID_EXE),
.DIV_ID_EXE ( DIV_ID_EXE),
.MFHL_ID_EXE ( MFHL_ID_EXE),
.MTHL_ID_EXE ( MTHL_ID_EXE),
.LB_ID_EXE ( LB_ID_EXE),
.LBU_ID_EXE ( LBU_ID_EXE),
.LH_ID_EXE ( LH_ID_EXE),
.LHU_ID_EXE ( LHU_ID_EXE),
.LW_ID_EXE ( LW_ID_EXE),
.SW_ID_EXE ( SW_ID_EXE),
.SB_ID_EXE ( SB_ID_EXE),
.SH_ID_EXE ( SH_ID_EXE),
.DSI_ID_EXE ( DSI_ID_EXE),
.eret_ID_EXE ( eret_ID_EXE),
.Rd_ID_EXE ( Rd_ID_EXE),
.Exc_vec_ID_EXE ( Exc_vec_ID_EXE),
.RegWaddr_ID_EXE ( RegWaddr_ID_EXE),
.PC_add_4_ID_EXE ( PC_add_4_ID_EXE),
.PC_ID_EXE ( PC_ID_EXE),
.RegRdata1_ID_EXE ( RegRdata1_ID_EXE),
.RegRdata2_ID_EXE ( RegRdata2_ID_EXE),
.Sa_ID_EXE ( Sa_ID_EXE),
.SgnExtend_ID_EXE ( SgnExtend_ID_EXE),
.ZExtend_ID_EXE ( ZExtend_ID_EXE),
.cp0_Write_ID_EXE ( cp0_Write_ID_EXE),
.mfc0_ID_EXE ( mfc0_ID_EXE),
.is_rs_read_ID ( is_rs_read),
.is_rt_read_ID ( is_rt_read),
.is_j_or_br_ID ( DSI_ID),
.ex_int_handling ( ex_int_handling),
.eret_handling ( eret_handling),
.de_to_exe_valid ( de_to_exe_valid),
.decode_allowin ( decode_allowin),
.fe_to_de_valid ( fe_to_de_valid),
.exe_allowin ( exe_allowin),
.exe_refresh ( exe_refresh),
.decode_stage_valid( de_valid)
);
execute_stage exe_stage
(
.clk (clk),
.rst (rst),
.PC_add_4_ID_EXE (PC_add_4_ID_EXE),
.PC_ID_EXE (PC_ID_EXE),
.RegRdata1_ID_EXE (RegRdata1_ID_EXE),
.RegRdata2_ID_EXE (RegRdata2_ID_EXE),
.Sa_ID_EXE (Sa_ID_EXE),
.SgnExtend_ID_EXE (SgnExtend_ID_EXE),
.ZExtend_ID_EXE (ZExtend_ID_EXE),
.RegWaddr_ID_EXE (RegWaddr_ID_EXE),
.DSI_ID_EXE (DSI_ID_EXE),
.Exc_vec_ID_EXE (Exc_vec_ID_EXE),
.cp0_Write_ID_EXE (cp0_Write_ID_EXE),
.MemEn_ID_EXE (MemEn_ID_EXE),
.is_signed_ID_EXE (is_signed_ID_EXE),
.MemToReg_ID_EXE (MemToReg_ID_EXE),
.ALUSrcA_ID_EXE (ALUSrcA_ID_EXE),
.ALUSrcB_ID_EXE (ALUSrcB_ID_EXE),
.ALUop_ID_EXE (ALUop_ID_EXE),
.MemWrite_ID_EXE (MemWrite_ID_EXE),
.RegWrite_ID_EXE (RegWrite_ID_EXE),
.DIV_ID_EXE (DIV_ID_EXE),
.MULT_ID_EXE (MULT_ID_EXE),
.MFHL_ID_EXE (MFHL_ID_EXE),
.MTHL_ID_EXE (MTHL_ID_EXE),
.LB_ID_EXE (LB_ID_EXE),
.LBU_ID_EXE (LBU_ID_EXE),
.LH_ID_EXE (LH_ID_EXE),
.LHU_ID_EXE (LHU_ID_EXE),
.LW_ID_EXE (LW_ID_EXE),
.SW_ID_EXE (SW_ID_EXE),
.SB_ID_EXE (SB_ID_EXE),
.SH_ID_EXE (SH_ID_EXE),
.MemEn_EXE_MEM (MemEn_EXE_MEM),
.MemToReg_EXE_MEM (MemToReg_EXE_MEM),
.MemWrite_EXE_MEM (MemWrite_EXE_MEM),
.RegWrite_EXE_MEM (RegWrite_EXE_MEM),
.MULT_EXE_MEM (MULT_EXE_MEM),
.MFHL_EXE_MEM (MFHL_EXE_MEM),
.MTHL_EXE_MEM (MTHL_EXE_MEM),
.LB_EXE_MEM (LB_EXE_MEM),
.LBU_EXE_MEM (LBU_EXE_MEM),
.LH_EXE_MEM (LH_EXE_MEM),
.LHU_EXE_MEM (LHU_EXE_MEM),
.LW_EXE_MEM (LW_EXE_MEM),
.RegWaddr_EXE_MEM (RegWaddr_EXE_MEM),
.ALUResult_EXE_MEM (ALUResult_EXE_MEM),
.MemWdata_EXE_MEM (MemWdata_EXE_MEM),
.PC_EXE_MEM (PC_EXE_MEM),
.RegRdata1_EXE_MEM (RegRdata1_EXE_MEM),
.RegRdata2_EXE_MEM (RegRdata2_EXE_MEM),
.s_vaddr_EXE_MEM (s_vaddr_EXE_MEM),
.s_size_EXE_MEM (s_size_EXE_MEM),
.Bypass_EXE (Bypass_EXE),
.Rd_ID_EXE (Rd_ID_EXE),
.mfc0_ID_EXE (mfc0_ID_EXE),
.cp0Rdata_EXE_MEM (cp0Rdata_EXE_MEM),
.mfc0_EXE_MEM (mfc0_EXE_MEM),
.Exc_BadVaddr (Exc_BadVaddr),
.Exc_EPC (Exc_EPC),
.Exc_BD (Exc_BD),
.Exc_Vec (Exc_Vec),
.cp0Rdata_EXE (CP0Rdata),
.ex_int_handle (ex_int_handle),
.ex_int_handling (ex_int_handling),
.eret_handling (eret_handling),
.mem_allowin (mem_allowin),
.de_to_exe_valid (de_to_exe_valid),
.exe_allowin (exe_allowin),
.exe_to_mem_valid (exe_to_mem_valid),
.cp0_Write_EXE (CP0Write),
.exe_ready_go (exe_ready_go),
.exe_stage_valid (exe_valid),
.ID_EXE_Stall (ID_EXE_Stall),
.DIV_EXE (DIV_EXE),
.MULT_EXE (MULT_EXE),
.eret_ID_EXE (eret_ID_EXE),
.epc_value (epc),
.PC (PC)
);
memory_stage mem_stage
(
.clk (clk),
.rst (rst),
.MemEn_EXE_MEM (MemEn_EXE_MEM),
.MemToReg_EXE_MEM (MemToReg_EXE_MEM),
.MemWrite_EXE_MEM (MemWrite_EXE_MEM),
.RegWrite_EXE_MEM (RegWrite_EXE_MEM),
.MFHL_EXE_MEM (MFHL_EXE_MEM),
.LB_EXE_MEM (LB_EXE_MEM),
.LBU_EXE_MEM (LBU_EXE_MEM),
.LH_EXE_MEM (LH_EXE_MEM),
.LHU_EXE_MEM (LHU_EXE_MEM),
.LW_EXE_MEM (LW_EXE_MEM),
.RegWaddr_EXE_MEM (RegWaddr_EXE_MEM),
.ALUResult_EXE_MEM (ALUResult_EXE_MEM),
.MemWdata_EXE_MEM (MemWdata_EXE_MEM),
.RegRdata2_EXE_MEM (RegRdata2_EXE_MEM),
.PC_EXE_MEM (PC_EXE_MEM),
.s_vaddr_EXE_MEM (s_vaddr_EXE_MEM),
.s_size_EXE_MEM (s_size_EXE_MEM),
.MULT_EXE_MEM (MULT_EXE_MEM),
.MTHL_EXE_MEM (MTHL_EXE_MEM),
.MULT_MEM (MULT_MEM),
.MTHL_MEM (MTHL_MEM),
.MemToReg_MEM_WB (MemToReg_MEM_WB),
.RegWrite_MEM_WB (RegWrite_MEM_WB),
.MFHL_MEM_WB (MFHL_MEM_WB),
.LB_MEM_WB (LB_MEM_WB),
.LBU_MEM_WB (LBU_MEM_WB),
.LH_MEM_WB (LH_MEM_WB),
.LHU_MEM_WB (LHU_MEM_WB),
.LW_MEM_WB (LW_MEM_WB),
.RegWaddr_MEM_WB (RegWaddr_MEM_WB),
.ALUResult_MEM_WB (ALUResult_MEM_WB),
.RegRdata2_MEM_WB (RegRdata2_MEM_WB),
.PC_MEM_WB (PC_MEM_WB),
.MemRdata_MEM_WB (MemRdata_MEM_WB),
.Bypass_MEM (Bypass_MEM),
.cp0Rdata_EXE_MEM (cp0Rdata_EXE_MEM),
.mfc0_EXE_MEM (mfc0_EXE_MEM),
.cp0Rdata_MEM_WB (cp0Rdata_MEM_WB),
.mfc0_MEM_WB (mfc0_MEM_WB),
.wb_allowin (wb_allowin),
.exe_to_mem_valid (exe_to_mem_valid),
.mem_allowin (mem_allowin),
.mem_to_wb_valid (mem_to_wb_valid),
.data_r_req (data_r_req),
.do_req_raddr (do_req_raddr),
.mem_axi_rdata (mem_axi_rdata),
.mem_axi_rvalid (mem_axi_rvalid),
.mem_axi_rid (mem_axi_rid),
.mem_axi_rready (mem_axi_rready),
.mem_axi_arid (mem_axi_arid),
.mem_axi_araddr (mem_axi_araddr),
.mem_axi_arsize (mem_axi_arsize),
.mem_axi_arready (mem_axi_arready),
.mem_axi_arvalid (mem_axi_arvalid),
.mem_axi_awid (mem_axi_awid),
.mem_axi_awaddr (mem_axi_awaddr),
.mem_axi_awsize (mem_axi_awsize),
.mem_axi_awvalid (mem_axi_awvalid),
.mem_axi_awready (mem_axi_awready),
.mem_axi_wid (mem_axi_wid),
.mem_axi_wdata (mem_axi_wdata),
.mem_axi_wstrb (mem_axi_wstrb),
.mem_axi_wvalid (mem_axi_wvalid),
.mem_axi_wready (mem_axi_wready),
.mem_axi_bready (mem_axi_bready),
.mem_axi_bid (mem_axi_bid),
.mem_axi_bvalid (mem_axi_bvalid),
.cpu_arid (cpu_arid),
.mem_read_req (mem_read_req),
.mem_stage_valid (mem_valid)
);
writeback_stage wb_stage(
.clk ( clk),
.rst ( rst),
.MemToReg_MEM_WB ( MemToReg_MEM_WB),
.RegWrite_MEM_WB ( RegWrite_MEM_WB),
.MFHL_MEM_WB ( MFHL_MEM_WB),
.LB_MEM_WB ( LB_MEM_WB),
.LBU_MEM_WB ( LBU_MEM_WB),
.LH_MEM_WB ( LH_MEM_WB),
.LHU_MEM_WB ( LHU_MEM_WB),
.LW_MEM_WB ( LW_MEM_WB),
.RegWaddr_MEM_WB ( RegWaddr_MEM_WB),
.ALUResult_MEM_WB ( ALUResult_MEM_WB),
.RegRdata2_MEM_WB ( RegRdata2_MEM_WB),
.MemRdata_MEM_WB ( MemRdata_MEM_WB),
.PC_MEM_WB ( PC_MEM_WB),
.HI_MEM_WB ( HI_out),
.LO_MEM_WB ( LO_out),
.RegWdata_WB ( RegWdata_WB),
.RegWdata_Bypass_WB(RegWdata_Bypass_WB),
.RegWaddr_WB ( RegWaddr_WB),
.RegWrite_WB ( RegWrite_WB),
.PC_WB ( PC_WB),
.cp0Rdata_MEM_WB ( cp0Rdata_MEM_WB),
.mfc0_MEM_WB ( mfc0_MEM_WB),
.mem_to_wb_valid ( mem_to_wb_valid),
.wb_allowin ( wb_allowin),
.wb_stage_valid ( wb_valid)
);
Bypass_Unit bypass_unit(
.clk ( clk),
.rst ( rst),
.is_rs_read ( is_rs_read),
.is_rt_read ( is_rt_read),
.MemToReg_ID_EXE ( MemToReg_ID_EXE),
.MemToReg_EXE_MEM ( MemToReg_EXE_MEM),
.MemToReg_MEM_WB ( MemToReg_MEM_WB),
.RegWaddr_EXE_MEM ( RegWaddr_EXE_MEM),
.RegWaddr_MEM_WB ( RegWaddr_MEM_WB),
.RegWaddr_ID_EXE ( RegWaddr_ID_EXE),
.rs_ID ( IR_IF_ID[25:21]),
.rt_ID ( IR_IF_ID[20:16]),
.RegWrite_ID_EXE ( RegWrite_ID_EXE),
.RegWrite_EXE_MEM ( RegWrite_EXE_MEM),
.RegWrite_MEM_WB ( RegWrite_MEM_WB),
.DIV_Busy ( DIV_Busy),
.DIV ( |DIV_ID_EXE),
.ex_int_handle ( ex_int_handle),
.PCWrite ( PCWrite),
.IRWrite ( IRWrite),
.ID_EXE_Stall ( ID_EXE_Stall),
.RegRdata1_src ( RegRdata1_src),
.RegRdata2_src ( RegRdata2_src),
.de_valid ( de_valid),
.wb_valid ( wb_valid),
.exe_valid ( exe_valid),
.mem_valid ( mem_valid),
.is_j_or_b ( DSI_ID)
);
reg_file RegFile(
.clk ( clk),
.rst ( rst),
.waddr ( RegWaddr_WB),
.raddr1 ( RegRaddr1),
.raddr2 ( RegRaddr2),
.wen ( RegWrite_WB),
.wdata ( RegWdata_WB),
.rdata1 ( RegRdata1),
.rdata2 ( RegRdata2)
);
cp0reg cp0(
.clk ( clk),
.rst ( rst),
.eret ( eret_ID_EXE),
.int ( int_i),
.Exc_BD ( Exc_BD),
.Exc_Vec ( Exc_Vec),
.waddr ( CP0Waddr),
.raddr ( CP0Raddr),
.wen ( CP0Write),
.wdata ( CP0Wdata),
.epc_in ( Exc_EPC),
.Exc_BadVaddr ( Exc_BadVaddr),
.rdata ( CP0Rdata),
.epc_value ( epc),
.ex_int_handle ( ex_int_handle),
.eret_handle ( eret_handle),
.exe_ready_go ( exe_ready_go),
.exe_refresh ( exe_refresh)
);
multiplyer mul(
.x ( RegRdata1_ID_EXE),
.y ( RegRdata2_ID_EXE),
.mul_clk ( clk),
.resetn ( resetn),
.clken ( |MULT_EXE),
.mul_signed ( MULT_EXE[0]&~MULT_EXE[1]),
.result ( MULT_Result)
);
divider div(
.div_clk ( clk),
.rst ( rst),
.x ( RegRdata1_ID_EXE),
.y ( RegRdata2_ID_EXE),
.div ( |DIV_EXE),
.div_signed ( DIV_EXE[0]&~DIV_EXE[1]),
.s ( DIV_quotient),
.r ( DIV_remainder),
.busy ( DIV_Busy),
.complete ( DIV_Complete)
);
HILO HILO(
.clk ( clk),
.rst ( rst),
.HI_in ( HI_in),
.LO_in ( LO_in),
.HILO_Write ( HILO_Write),
.HI_out ( HI_out),
.LO_out ( LO_out)
);
assign HI_in = |MULT_MEM ? MULT_Result[63:32] :
MTHL_MEM[1] ? RegRdata1_EXE_MEM :
DIV_Complete ? DIV_remainder : 'd0;
assign LO_in = |MULT_MEM ? MULT_Result[31: 0] :
MTHL_MEM[0] ? RegRdata1_EXE_MEM :
DIV_Complete ? DIV_quotient : 'd0;
assign HILO_Write[1] = |MULT_MEM | DIV_Complete | MTHL_MEM[1];
assign HILO_Write[0] = |MULT_MEM | DIV_Complete | MTHL_MEM[0];
assign CP0Waddr = Rd_ID_EXE;
assign CP0Wdata = RegRdata2_ID_EXE;
assign CP0Raddr = Rd_ID_EXE;
`ifdef SIMU_DEBUG
assign debug_wb_pc = PC_WB;
assign debug_wb_rf_wen = RegWrite_WB;
assign debug_wb_rf_wnum = RegWaddr_WB;
assign debug_wb_rf_wdata = RegWdata_WB;
`endif
reg arvalid_r;
reg first_fetch;
reg [31:0] do_araddr;
reg [ 3:0] do_arid;
reg [ 2:0] do_arsize;
reg [ 1:0] do_r_req;
wire [ 3:0] do_r_req_pos;
assign cpu_arid = do_arid;
assign cpu_araddr = do_araddr;
assign cpu_arlen = 8'd0;
assign cpu_arsize = do_arsize;
assign cpu_arburst = 2'd1;
assign cpu_arlock = 2'd0;
assign cpu_arcache = 4'd0;
assign cpu_arprot = 3'd0;
assign cpu_arvalid = |do_r_req;
assign mem_axi_arready = cpu_arready;
assign fetch_axi_arready = cpu_arready;
assign mem_axi_rid = cpu_rid;
assign fetch_axi_rid = cpu_rid;
assign mem_axi_rdata = cpu_rdata;
assign fetch_axi_rdata = cpu_rdata;
assign mem_axi_rvalid = cpu_rvalid;
assign fetch_axi_rvalid = cpu_rvalid;
assign cpu_rready = fetch_axi_rready || mem_axi_rready;
assign cpu_awid = mem_axi_awid;
assign cpu_awaddr = mem_axi_awaddr;
assign cpu_awlen = 8'd0;
assign cpu_awsize = mem_axi_awsize;
assign cpu_awburst = 2'd1;
assign cpu_awlock = 2'd0;
assign cpu_awcache = 2'd0;
assign cpu_awprot = 4'd0;
assign cpu_awvalid = mem_axi_awvalid;
assign mem_axi_awready = cpu_awready;
assign cpu_wid = mem_axi_wid;
assign cpu_wdata = mem_axi_wdata;
assign cpu_wstrb = mem_axi_wstrb;
assign cpu_wlast = 1'd1;
assign cpu_wvalid = mem_axi_wvalid;
assign mem_axi_wready = cpu_wready;
assign mem_axi_bid = cpu_bid;
assign mem_axi_bresp = cpu_bresp;
assign mem_axi_bvalid = cpu_bvalid;
assign cpu_bready = mem_axi_bready;
assign PC_refresh = cpu_arvalid && cpu_arready && cpu_arid==4'd0;
always @(posedge clk) begin
if (rst) begin
arvalid_r <= 1'b0;
first_fetch <= 1'b1;
end
else if (cpu_arready&&cpu_arvalid&&cpu_arid==4'd0) begin
arvalid_r <= 1'b0;
first_fetch <= 1'b0;
end
else if (cpu_rready&&cpu_rvalid&&cpu_rid==4'd0) begin
arvalid_r <= 1'b1;
first_fetch <= 1'b0;
end
end
always @ (posedge clk) begin
if (rst) begin
do_r_req <= 2'd0;
end
else begin
if (do_r_req==2'd0) begin
if (first_fetch) begin
do_r_req <= 2'd1;
end
else if (do_req_raddr) begin
do_r_req <= 2'd3;
end
else if (arvalid_r&&(data_r_req!=2'd2||data_r_req!=2'd1)&&!IR_buffer_valid&&!ID_EXE_Stall) begin
do_r_req <= 2'd2;
end
end
else begin
if (do_r_req==2'd1||do_r_req==2'd2) begin
if (cpu_arready&&cpu_arid==4'd0) begin
do_r_req <= 2'd0;
end
end
if (do_r_req==2'd3) begin
if (cpu_arready&&cpu_arid==4'd1) begin
do_r_req <= 2'd0;
end
end
end
end
end
assign do_r_req_pos[0] = 1'b0;
assign do_r_req_pos[1] = do_r_req==2'd0 && first_fetch;
assign do_r_req_pos[2] = do_r_req==2'd0 && !ID_EXE_Stall && arvalid_r&&(data_r_req!=2'd2||data_r_req!=2'd1)&&!IR_buffer_valid;
assign do_r_req_pos[3] = do_r_req==2'd0 && do_req_raddr;
always @ (posedge clk) begin
if (rst) begin
do_arid <= 'd0;
do_arsize <= 'd0;
do_araddr <= 'd0;
end
else begin
if (do_r_req_pos[1]||do_r_req_pos[2]) begin
do_arid <= `INST_ARID;
do_arsize <= 3'd2;
do_araddr <= {PC[31:2],2'd0};
end
if (do_r_req_pos[3]) begin
do_arid <= `MEM_ARID;
do_arsize <= mem_axi_arsize;
do_araddr <= mem_axi_araddr;
end
end
end
endmodule | module mycpu_top(
input clk,
input resetn,
input [ 5:0] int_i,
output [ 3:0] cpu_arid,
output [31:0] cpu_araddr,
output [ 7:0] cpu_arlen,
output [ 2:0] cpu_arsize,
output [ 1:0] cpu_arburst,
output [ 1:0] cpu_arlock,
output [ 3:0] cpu_arcache,
output [ 2:0] cpu_arprot,
output cpu_arvalid,
input cpu_arready,
input [ 3:0] cpu_rid,
input [31:0] cpu_rdata,
input [ 1:0] cpu_rresp,
input cpu_rlast,
input cpu_rvalid,
output cpu_rready,
output [ 3:0] cpu_awid,
output [31:0] cpu_awaddr,
output [ 7:0] cpu_awlen,
output [ 2:0] cpu_awsize,
output [ 1:0] cpu_awburst,
output [ 1:0] cpu_awlock,
output [ 3:0] cpu_awcache,
output [ 2:0] cpu_awprot,
output cpu_awvalid,
input cpu_awready,
output [ 3:0] cpu_wid,
output [31:0] cpu_wdata,
output [ 3:0] cpu_wstrb,
output cpu_wlast,
output cpu_wvalid,
input cpu_wready,
input [ 3:0] cpu_bid,
input [ 1:0] cpu_bresp,
input cpu_bvalid,
output cpu_bready
`ifdef SIMU_DEBUG
,output wire [31:0] debug_wb_pc,
output wire [ 3:0] debug_wb_rf_wen,
output wire [ 4:0] debug_wb_rf_wnum,
output wire [31:0] debug_wb_rf_wdata
`endif
); |
wire rst = ~resetn;
wire JSrc;
wire [ 1:0] PCSrc;
wire [ 4:0] RegRaddr1;
wire [ 4:0] RegRaddr2;
wire [31:0] RegRdata1;
wire [31:0] RegRdata2;
wire DSI_ID;
wire DSI_IF_ID;
wire [31:0] PC_next;
wire [31:0] PC_IF_ID;
wire [31:0] PC_add_4_IF_ID;
wire PC_AdEL_IF_ID;
wire PC_AdEL;
wire [31:0] IR_IF_ID;
wire PCWrite;
wire IRWrite;
wire [31:0] J_target_ID;
wire [31:0] JR_target_ID;
wire [31:0] Br_target_ID;
wire [31:0] PC_add_4_ID;
wire [ 1:0] RegRdata1_src;
wire [ 1:0] RegRdata2_src;
wire is_rs_read;
wire is_rt_read;
wire ID_EXE_Stall;
wire [31:0] PC_ID_EXE;
wire [31:0] PC_add_4_ID_EXE;
wire [ 1:0] RegDst_ID_EXE;
wire [ 1:0] ALUSrcA_ID_EXE;
wire [ 1:0] ALUSrcB_ID_EXE;
wire [ 3:0] ALUop_ID_EXE;
wire [ 3:0] RegWrite_ID_EXE;
wire [ 3:0] MemWrite_ID_EXE;
wire is_signed_ID_EXE;
wire MemEn_ID_EXE;
wire MemToReg_ID_EXE;
wire [ 1:0] MULT_ID_EXE;
wire [ 1:0] DIV_ID_EXE;
wire [ 1:0] MFHL_ID_EXE;
wire [ 1:0] MTHL_ID_EXE;
wire LB_ID_EXE;
wire LBU_ID_EXE;
wire LH_ID_EXE;
wire LHU_ID_EXE;
wire [ 1:0] LW_ID_EXE;
wire [ 1:0] SW_ID_EXE;
wire SB_ID_EXE;
wire SH_ID_EXE;
wire [ 4:0] RegWaddr_ID_EXE;
wire [31:0] ALUResult_EXE;
wire [31:0] ALUResult_MEM;
wire [ 1:0] DIV_EXE;
wire [ 1:0] MULT_EXE;
wire [31:0] RegRdata1_ID_EXE;
wire [31:0] RegRdata2_ID_EXE;
wire [31:0] Sa_ID_EXE;
wire [31:0] SgnExtend_ID_EXE;
wire [31:0] ZExtend_ID_EXE;
wire MemEn_EXE_MEM;
wire MemToReg_EXE_MEM;
wire [ 3:0] MemWrite_EXE_MEM;
wire [ 3:0] RegWrite_EXE_MEM;
wire [ 3:0] RegWrite_EXE;
wire [ 4:0] RegWaddr_EXE_MEM;
wire [ 1:0] MULT_EXE_MEM;
wire [ 1:0] MFHL_EXE_MEM;
wire [ 1:0] MTHL_EXE_MEM;
wire LB_EXE_MEM;
wire LBU_EXE_MEM;
wire LH_EXE_MEM;
wire LHU_EXE_MEM;
wire [ 1:0] LW_EXE_MEM;
wire [31:0] ALUResult_EXE_MEM;
wire [31:0] MemWdata_EXE_MEM;
wire [31:0] PC_EXE_MEM;
wire [31:0] RegRdata1_EXE_MEM;
wire [31:0] RegRdata2_EXE_MEM;
wire [ 1:0] s_vaddr_EXE_MEM;
wire [ 2:0] s_size_EXE_MEM;
wire [ 1:0] MULT_MEM;
wire [ 1:0] MTHL_MEM;
wire MemToReg_MEM_WB;
wire [ 3:0] RegWrite_MEM_WB;
wire [ 4:0] RegWaddr_MEM_WB;
wire [ 1:0] MFHL_MEM_WB;
wire LB_MEM_WB;
wire LBU_MEM_WB;
wire LH_MEM_WB;
wire LHU_MEM_WB;
wire [ 1:0] LW_MEM_WB;
wire [31:0] ALUResult_MEM_WB;
wire [31:0] RegRdata2_MEM_WB;
wire [31:0] PC_MEM_WB;
wire [31:0] PC_WB;
wire [31:0] RegWdata_WB;
wire [ 4:0] RegWaddr_WB;
wire [ 3:0] RegWrite_WB;
wire [31:0] MemRdata_MEM_WB;
wire [31:0] RegWdata_Bypass_WB;
wire [63:0] MULT_Result ;
wire [31:0] DIV_quotient ;
wire [31:0] DIV_remainder ;
wire DIV_Busy ;
wire DIV_Complete ;
wire [31:0] HI_in ;
wire [31:0] LO_in ;
wire [ 1:0] HILO_Write ;
wire [31:0] HI_out ;
wire [31:0] LO_out ;
wire [ 4:0] CP0Raddr ;
wire [31:0] CP0Rdata ;
wire [ 4:0] CP0Waddr ;
wire [31:0] CP0Wdata ;
wire CP0Write ;
wire [31:0] epc ;
wire [ 4:0] rd ;
wire [31:0] RegRdata2_Final ;
wire [31:0] cp0Rdata_EXE_MEM ;
wire [31:0] cp0Rdata_MEM_WB ;
wire mfc0_ID_EXE ;
wire mfc0_EXE_MEM ;
wire mfc0_MEM_WB ;
wire [31:0] Bypass_EXE ;
wire [31:0] Bypass_MEM ;
wire [31:0] Exc_BadVaddr ;
wire [31:0] Exc_EPC ;
wire [ 5:0] Exc_Cause ;
wire ex_int_handle ;
wire ex_int_handling ;
wire eret_handle ;
wire eret_handling ;
wire DSI_ID_EXE ;
wire eret_ID_EXE ;
wire cp0_Write_ID_EXE ;
wire Exc_BD ;
wire [ 6:0] Exc_Vec ;
wire [ 4:0] Rd_ID_EXE ;
wire [ 3:0] Exc_vec_ID_EXE ;
wire [31:0] PC_buffer ;
wire PC_refresh ;
wire [ 1:0] data_r_req ;
wire do_req_raddr ;
wire mem_read_req;
wire [31:0] PC ;
wire [31:0] mem_axi_rdata ;
wire mem_axi_rvalid ;
wire [ 3:0] mem_axi_rid ;
wire mem_axi_rready ;
wire [ 3:0] mem_axi_arid ;
wire [31:0] mem_axi_araddr ;
wire [ 2:0] mem_axi_arsize ;
wire mem_axi_arready ;
wire mem_axi_arvalid ;
wire [ 3:0] mem_axi_awid ;
wire [31:0] mem_axi_awaddr ;
wire [ 2:0] mem_axi_awsize ;
wire mem_axi_awvalid ;
wire mem_axi_awready ;
wire [ 3:0] mem_axi_wid ;
wire [31:0] mem_axi_wdata ;
wire [ 3:0] mem_axi_wstrb ;
wire mem_axi_wvalid ;
wire mem_axi_wready ;
wire mem_axi_bready ;
wire [ 3:0] mem_axi_bid ;
wire mem_axi_bvalid ;
wire [ 1:0] mem_axi_bresp ;
wire fetch_axi_rready ;
wire fetch_axi_rvalid ;
wire fetch_axi_rdata ;
wire [ 3:0] fetch_axi_rid ;
wire fetch_axi_arready;
wire fetch_axi_arvalid;
wire [ 2:0] fetch_axi_arsize ;
wire fetch_axi_arid ;
wire decode_allowin ;
wire exe_allowin;
wire mem_allowin;
wire wb_allowin;
wire fe_to_de_valid;
wire de_to_exe_valid;
wire exe_to_mem_valid;
wire mem_to_wb_valid;
wire de_valid;
wire exe_valid;
wire mem_valid;
wire wb_valid;
wire exe_refresh;
wire exe_ready_go;
wire IR_buffer_valid;
wire j_or_b_ID;
nextpc_gen nextpc_gen(
.clk ( clk),
.rst ( rst),
.PCWrite ( PCWrite),
.JSrc ( JSrc),
.PCSrc ( PCSrc),
.eret ( eret_handle),
.epc ( epc),
.JR_target ( JR_target_ID),
.J_target ( J_target_ID),
.Br_addr ( Br_target_ID),
.PC_AdEL ( PC_AdEL),
.ex_int_handle ( ex_int_handle),
.PC ( PC),
.PC_buffer ( PC_buffer),
.PC_refresh ( PC_refresh)
);
fetch_stage fe_stage(
.clk ( clk),
.rst ( rst),
.DSI_ID ( DSI_ID),
.IRWrite ( IRWrite),
.PC_AdEL ( PC_AdEL),
.PC_IF_ID ( PC_IF_ID),
.PC_add_4_IF_ID ( PC_add_4_IF_ID),
.IR_IF_ID ( IR_IF_ID),
.PC_buffer ( PC_buffer),
.PC_AdEL_IF_ID ( PC_AdEL_IF_ID),
.DSI_IF_ID ( DSI_IF_ID),
.data_r_req ( data_r_req),
.fetch_axi_rready (fetch_axi_rready ),
.fetch_axi_rvalid ( cpu_rvalid ),
.fetch_axi_rdata ( cpu_rdata ),
.fetch_axi_rid ( cpu_rid ),
.fetch_axi_arready ( cpu_arready),
.fe_to_de_valid ( fe_to_de_valid),
.decode_allowin (decode_allowin ),
.IR_buffer_valid ( IR_buffer_valid)
);
decode_stage de_stage(
.clk ( clk),
.rst ( rst),
.Inst_IF_ID ( IR_IF_ID),
.PC_IF_ID ( PC_IF_ID),
.PC_add_4_IF_ID ( PC_add_4_IF_ID),
.DSI_IF_ID ( DSI_IF_ID),
.PC_AdEL_IF_ID ( PC_AdEL_IF_ID),
.ex_int_handle_ID ( ex_int_handle),
.RegRaddr1_ID ( RegRaddr1),
.RegRaddr2_ID ( RegRaddr2),
.RegRdata1_ID ( RegRdata1),
.RegRdata2_ID ( RegRdata2),
.Bypass_EXE ( Bypass_EXE),
.Bypass_MEM ( Bypass_MEM),
.RegWdata_WB (RegWdata_Bypass_WB),
.MULT_Result ( MULT_Result),
.HI ( HI_out),
.LO ( LO_out),
.MFHL_ID_EXE_1 ( MFHL_ID_EXE),
.MFHL_EXE_MEM ( MFHL_EXE_MEM),
.MFHL_MEM_WB ( MFHL_MEM_WB),
.MULT_EXE_MEM ( MULT_EXE_MEM),
.RegRdata1_src ( RegRdata1_src),
.RegRdata2_src ( RegRdata2_src),
.ID_EXE_Stall ( ID_EXE_Stall),
.DIV_Complete ( DIV_Complete),
.JSrc ( JSrc),
.PCSrc ( PCSrc),
.J_target_ID ( J_target_ID),
.JR_target_ID ( JR_target_ID),
.Br_target_ID ( Br_target_ID),
.ALUSrcA_ID_EXE ( ALUSrcA_ID_EXE),
.ALUSrcB_ID_EXE ( ALUSrcB_ID_EXE),
.ALUop_ID_EXE ( ALUop_ID_EXE),
.RegWrite_ID_EXE ( RegWrite_ID_EXE),
.MemWrite_ID_EXE ( MemWrite_ID_EXE),
.MemEn_ID_EXE ( MemEn_ID_EXE),
.MemToReg_ID_EXE ( MemToReg_ID_EXE),
.is_signed_ID_EXE ( is_signed_ID_EXE),
.MULT_ID_EXE ( MULT_ID_EXE),
.DIV_ID_EXE ( DIV_ID_EXE),
.MFHL_ID_EXE ( MFHL_ID_EXE),
.MTHL_ID_EXE ( MTHL_ID_EXE),
.LB_ID_EXE ( LB_ID_EXE),
.LBU_ID_EXE ( LBU_ID_EXE),
.LH_ID_EXE ( LH_ID_EXE),
.LHU_ID_EXE ( LHU_ID_EXE),
.LW_ID_EXE ( LW_ID_EXE),
.SW_ID_EXE ( SW_ID_EXE),
.SB_ID_EXE ( SB_ID_EXE),
.SH_ID_EXE ( SH_ID_EXE),
.DSI_ID_EXE ( DSI_ID_EXE),
.eret_ID_EXE ( eret_ID_EXE),
.Rd_ID_EXE ( Rd_ID_EXE),
.Exc_vec_ID_EXE ( Exc_vec_ID_EXE),
.RegWaddr_ID_EXE ( RegWaddr_ID_EXE),
.PC_add_4_ID_EXE ( PC_add_4_ID_EXE),
.PC_ID_EXE ( PC_ID_EXE),
.RegRdata1_ID_EXE ( RegRdata1_ID_EXE),
.RegRdata2_ID_EXE ( RegRdata2_ID_EXE),
.Sa_ID_EXE ( Sa_ID_EXE),
.SgnExtend_ID_EXE ( SgnExtend_ID_EXE),
.ZExtend_ID_EXE ( ZExtend_ID_EXE),
.cp0_Write_ID_EXE ( cp0_Write_ID_EXE),
.mfc0_ID_EXE ( mfc0_ID_EXE),
.is_rs_read_ID ( is_rs_read),
.is_rt_read_ID ( is_rt_read),
.is_j_or_br_ID ( DSI_ID),
.ex_int_handling ( ex_int_handling),
.eret_handling ( eret_handling),
.de_to_exe_valid ( de_to_exe_valid),
.decode_allowin ( decode_allowin),
.fe_to_de_valid ( fe_to_de_valid),
.exe_allowin ( exe_allowin),
.exe_refresh ( exe_refresh),
.decode_stage_valid( de_valid)
);
execute_stage exe_stage
(
.clk (clk),
.rst (rst),
.PC_add_4_ID_EXE (PC_add_4_ID_EXE),
.PC_ID_EXE (PC_ID_EXE),
.RegRdata1_ID_EXE (RegRdata1_ID_EXE),
.RegRdata2_ID_EXE (RegRdata2_ID_EXE),
.Sa_ID_EXE (Sa_ID_EXE),
.SgnExtend_ID_EXE (SgnExtend_ID_EXE),
.ZExtend_ID_EXE (ZExtend_ID_EXE),
.RegWaddr_ID_EXE (RegWaddr_ID_EXE),
.DSI_ID_EXE (DSI_ID_EXE),
.Exc_vec_ID_EXE (Exc_vec_ID_EXE),
.cp0_Write_ID_EXE (cp0_Write_ID_EXE),
.MemEn_ID_EXE (MemEn_ID_EXE),
.is_signed_ID_EXE (is_signed_ID_EXE),
.MemToReg_ID_EXE (MemToReg_ID_EXE),
.ALUSrcA_ID_EXE (ALUSrcA_ID_EXE),
.ALUSrcB_ID_EXE (ALUSrcB_ID_EXE),
.ALUop_ID_EXE (ALUop_ID_EXE),
.MemWrite_ID_EXE (MemWrite_ID_EXE),
.RegWrite_ID_EXE (RegWrite_ID_EXE),
.DIV_ID_EXE (DIV_ID_EXE),
.MULT_ID_EXE (MULT_ID_EXE),
.MFHL_ID_EXE (MFHL_ID_EXE),
.MTHL_ID_EXE (MTHL_ID_EXE),
.LB_ID_EXE (LB_ID_EXE),
.LBU_ID_EXE (LBU_ID_EXE),
.LH_ID_EXE (LH_ID_EXE),
.LHU_ID_EXE (LHU_ID_EXE),
.LW_ID_EXE (LW_ID_EXE),
.SW_ID_EXE (SW_ID_EXE),
.SB_ID_EXE (SB_ID_EXE),
.SH_ID_EXE (SH_ID_EXE),
.MemEn_EXE_MEM (MemEn_EXE_MEM),
.MemToReg_EXE_MEM (MemToReg_EXE_MEM),
.MemWrite_EXE_MEM (MemWrite_EXE_MEM),
.RegWrite_EXE_MEM (RegWrite_EXE_MEM),
.MULT_EXE_MEM (MULT_EXE_MEM),
.MFHL_EXE_MEM (MFHL_EXE_MEM),
.MTHL_EXE_MEM (MTHL_EXE_MEM),
.LB_EXE_MEM (LB_EXE_MEM),
.LBU_EXE_MEM (LBU_EXE_MEM),
.LH_EXE_MEM (LH_EXE_MEM),
.LHU_EXE_MEM (LHU_EXE_MEM),
.LW_EXE_MEM (LW_EXE_MEM),
.RegWaddr_EXE_MEM (RegWaddr_EXE_MEM),
.ALUResult_EXE_MEM (ALUResult_EXE_MEM),
.MemWdata_EXE_MEM (MemWdata_EXE_MEM),
.PC_EXE_MEM (PC_EXE_MEM),
.RegRdata1_EXE_MEM (RegRdata1_EXE_MEM),
.RegRdata2_EXE_MEM (RegRdata2_EXE_MEM),
.s_vaddr_EXE_MEM (s_vaddr_EXE_MEM),
.s_size_EXE_MEM (s_size_EXE_MEM),
.Bypass_EXE (Bypass_EXE),
.Rd_ID_EXE (Rd_ID_EXE),
.mfc0_ID_EXE (mfc0_ID_EXE),
.cp0Rdata_EXE_MEM (cp0Rdata_EXE_MEM),
.mfc0_EXE_MEM (mfc0_EXE_MEM),
.Exc_BadVaddr (Exc_BadVaddr),
.Exc_EPC (Exc_EPC),
.Exc_BD (Exc_BD),
.Exc_Vec (Exc_Vec),
.cp0Rdata_EXE (CP0Rdata),
.ex_int_handle (ex_int_handle),
.ex_int_handling (ex_int_handling),
.eret_handling (eret_handling),
.mem_allowin (mem_allowin),
.de_to_exe_valid (de_to_exe_valid),
.exe_allowin (exe_allowin),
.exe_to_mem_valid (exe_to_mem_valid),
.cp0_Write_EXE (CP0Write),
.exe_ready_go (exe_ready_go),
.exe_stage_valid (exe_valid),
.ID_EXE_Stall (ID_EXE_Stall),
.DIV_EXE (DIV_EXE),
.MULT_EXE (MULT_EXE),
.eret_ID_EXE (eret_ID_EXE),
.epc_value (epc),
.PC (PC)
);
memory_stage mem_stage
(
.clk (clk),
.rst (rst),
.MemEn_EXE_MEM (MemEn_EXE_MEM),
.MemToReg_EXE_MEM (MemToReg_EXE_MEM),
.MemWrite_EXE_MEM (MemWrite_EXE_MEM),
.RegWrite_EXE_MEM (RegWrite_EXE_MEM),
.MFHL_EXE_MEM (MFHL_EXE_MEM),
.LB_EXE_MEM (LB_EXE_MEM),
.LBU_EXE_MEM (LBU_EXE_MEM),
.LH_EXE_MEM (LH_EXE_MEM),
.LHU_EXE_MEM (LHU_EXE_MEM),
.LW_EXE_MEM (LW_EXE_MEM),
.RegWaddr_EXE_MEM (RegWaddr_EXE_MEM),
.ALUResult_EXE_MEM (ALUResult_EXE_MEM),
.MemWdata_EXE_MEM (MemWdata_EXE_MEM),
.RegRdata2_EXE_MEM (RegRdata2_EXE_MEM),
.PC_EXE_MEM (PC_EXE_MEM),
.s_vaddr_EXE_MEM (s_vaddr_EXE_MEM),
.s_size_EXE_MEM (s_size_EXE_MEM),
.MULT_EXE_MEM (MULT_EXE_MEM),
.MTHL_EXE_MEM (MTHL_EXE_MEM),
.MULT_MEM (MULT_MEM),
.MTHL_MEM (MTHL_MEM),
.MemToReg_MEM_WB (MemToReg_MEM_WB),
.RegWrite_MEM_WB (RegWrite_MEM_WB),
.MFHL_MEM_WB (MFHL_MEM_WB),
.LB_MEM_WB (LB_MEM_WB),
.LBU_MEM_WB (LBU_MEM_WB),
.LH_MEM_WB (LH_MEM_WB),
.LHU_MEM_WB (LHU_MEM_WB),
.LW_MEM_WB (LW_MEM_WB),
.RegWaddr_MEM_WB (RegWaddr_MEM_WB),
.ALUResult_MEM_WB (ALUResult_MEM_WB),
.RegRdata2_MEM_WB (RegRdata2_MEM_WB),
.PC_MEM_WB (PC_MEM_WB),
.MemRdata_MEM_WB (MemRdata_MEM_WB),
.Bypass_MEM (Bypass_MEM),
.cp0Rdata_EXE_MEM (cp0Rdata_EXE_MEM),
.mfc0_EXE_MEM (mfc0_EXE_MEM),
.cp0Rdata_MEM_WB (cp0Rdata_MEM_WB),
.mfc0_MEM_WB (mfc0_MEM_WB),
.wb_allowin (wb_allowin),
.exe_to_mem_valid (exe_to_mem_valid),
.mem_allowin (mem_allowin),
.mem_to_wb_valid (mem_to_wb_valid),
.data_r_req (data_r_req),
.do_req_raddr (do_req_raddr),
.mem_axi_rdata (mem_axi_rdata),
.mem_axi_rvalid (mem_axi_rvalid),
.mem_axi_rid (mem_axi_rid),
.mem_axi_rready (mem_axi_rready),
.mem_axi_arid (mem_axi_arid),
.mem_axi_araddr (mem_axi_araddr),
.mem_axi_arsize (mem_axi_arsize),
.mem_axi_arready (mem_axi_arready),
.mem_axi_arvalid (mem_axi_arvalid),
.mem_axi_awid (mem_axi_awid),
.mem_axi_awaddr (mem_axi_awaddr),
.mem_axi_awsize (mem_axi_awsize),
.mem_axi_awvalid (mem_axi_awvalid),
.mem_axi_awready (mem_axi_awready),
.mem_axi_wid (mem_axi_wid),
.mem_axi_wdata (mem_axi_wdata),
.mem_axi_wstrb (mem_axi_wstrb),
.mem_axi_wvalid (mem_axi_wvalid),
.mem_axi_wready (mem_axi_wready),
.mem_axi_bready (mem_axi_bready),
.mem_axi_bid (mem_axi_bid),
.mem_axi_bvalid (mem_axi_bvalid),
.cpu_arid (cpu_arid),
.mem_read_req (mem_read_req),
.mem_stage_valid (mem_valid)
);
writeback_stage wb_stage(
.clk ( clk),
.rst ( rst),
.MemToReg_MEM_WB ( MemToReg_MEM_WB),
.RegWrite_MEM_WB ( RegWrite_MEM_WB),
.MFHL_MEM_WB ( MFHL_MEM_WB),
.LB_MEM_WB ( LB_MEM_WB),
.LBU_MEM_WB ( LBU_MEM_WB),
.LH_MEM_WB ( LH_MEM_WB),
.LHU_MEM_WB ( LHU_MEM_WB),
.LW_MEM_WB ( LW_MEM_WB),
.RegWaddr_MEM_WB ( RegWaddr_MEM_WB),
.ALUResult_MEM_WB ( ALUResult_MEM_WB),
.RegRdata2_MEM_WB ( RegRdata2_MEM_WB),
.MemRdata_MEM_WB ( MemRdata_MEM_WB),
.PC_MEM_WB ( PC_MEM_WB),
.HI_MEM_WB ( HI_out),
.LO_MEM_WB ( LO_out),
.RegWdata_WB ( RegWdata_WB),
.RegWdata_Bypass_WB(RegWdata_Bypass_WB),
.RegWaddr_WB ( RegWaddr_WB),
.RegWrite_WB ( RegWrite_WB),
.PC_WB ( PC_WB),
.cp0Rdata_MEM_WB ( cp0Rdata_MEM_WB),
.mfc0_MEM_WB ( mfc0_MEM_WB),
.mem_to_wb_valid ( mem_to_wb_valid),
.wb_allowin ( wb_allowin),
.wb_stage_valid ( wb_valid)
);
Bypass_Unit bypass_unit(
.clk ( clk),
.rst ( rst),
.is_rs_read ( is_rs_read),
.is_rt_read ( is_rt_read),
.MemToReg_ID_EXE ( MemToReg_ID_EXE),
.MemToReg_EXE_MEM ( MemToReg_EXE_MEM),
.MemToReg_MEM_WB ( MemToReg_MEM_WB),
.RegWaddr_EXE_MEM ( RegWaddr_EXE_MEM),
.RegWaddr_MEM_WB ( RegWaddr_MEM_WB),
.RegWaddr_ID_EXE ( RegWaddr_ID_EXE),
.rs_ID ( IR_IF_ID[25:21]),
.rt_ID ( IR_IF_ID[20:16]),
.RegWrite_ID_EXE ( RegWrite_ID_EXE),
.RegWrite_EXE_MEM ( RegWrite_EXE_MEM),
.RegWrite_MEM_WB ( RegWrite_MEM_WB),
.DIV_Busy ( DIV_Busy),
.DIV ( |DIV_ID_EXE),
.ex_int_handle ( ex_int_handle),
.PCWrite ( PCWrite),
.IRWrite ( IRWrite),
.ID_EXE_Stall ( ID_EXE_Stall),
.RegRdata1_src ( RegRdata1_src),
.RegRdata2_src ( RegRdata2_src),
.de_valid ( de_valid),
.wb_valid ( wb_valid),
.exe_valid ( exe_valid),
.mem_valid ( mem_valid),
.is_j_or_b ( DSI_ID)
);
reg_file RegFile(
.clk ( clk),
.rst ( rst),
.waddr ( RegWaddr_WB),
.raddr1 ( RegRaddr1),
.raddr2 ( RegRaddr2),
.wen ( RegWrite_WB),
.wdata ( RegWdata_WB),
.rdata1 ( RegRdata1),
.rdata2 ( RegRdata2)
);
cp0reg cp0(
.clk ( clk),
.rst ( rst),
.eret ( eret_ID_EXE),
.int ( int_i),
.Exc_BD ( Exc_BD),
.Exc_Vec ( Exc_Vec),
.waddr ( CP0Waddr),
.raddr ( CP0Raddr),
.wen ( CP0Write),
.wdata ( CP0Wdata),
.epc_in ( Exc_EPC),
.Exc_BadVaddr ( Exc_BadVaddr),
.rdata ( CP0Rdata),
.epc_value ( epc),
.ex_int_handle ( ex_int_handle),
.eret_handle ( eret_handle),
.exe_ready_go ( exe_ready_go),
.exe_refresh ( exe_refresh)
);
multiplyer mul(
.x ( RegRdata1_ID_EXE),
.y ( RegRdata2_ID_EXE),
.mul_clk ( clk),
.resetn ( resetn),
.clken ( |MULT_EXE),
.mul_signed ( MULT_EXE[0]&~MULT_EXE[1]),
.result ( MULT_Result)
);
divider div(
.div_clk ( clk),
.rst ( rst),
.x ( RegRdata1_ID_EXE),
.y ( RegRdata2_ID_EXE),
.div ( |DIV_EXE),
.div_signed ( DIV_EXE[0]&~DIV_EXE[1]),
.s ( DIV_quotient),
.r ( DIV_remainder),
.busy ( DIV_Busy),
.complete ( DIV_Complete)
);
HILO HILO(
.clk ( clk),
.rst ( rst),
.HI_in ( HI_in),
.LO_in ( LO_in),
.HILO_Write ( HILO_Write),
.HI_out ( HI_out),
.LO_out ( LO_out)
);
assign HI_in = |MULT_MEM ? MULT_Result[63:32] :
MTHL_MEM[1] ? RegRdata1_EXE_MEM :
DIV_Complete ? DIV_remainder : 'd0;
assign LO_in = |MULT_MEM ? MULT_Result[31: 0] :
MTHL_MEM[0] ? RegRdata1_EXE_MEM :
DIV_Complete ? DIV_quotient : 'd0;
assign HILO_Write[1] = |MULT_MEM | DIV_Complete | MTHL_MEM[1];
assign HILO_Write[0] = |MULT_MEM | DIV_Complete | MTHL_MEM[0];
assign CP0Waddr = Rd_ID_EXE;
assign CP0Wdata = RegRdata2_ID_EXE;
assign CP0Raddr = Rd_ID_EXE;
`ifdef SIMU_DEBUG
assign debug_wb_pc = PC_WB;
assign debug_wb_rf_wen = RegWrite_WB;
assign debug_wb_rf_wnum = RegWaddr_WB;
assign debug_wb_rf_wdata = RegWdata_WB;
`endif
reg arvalid_r;
reg first_fetch;
reg [31:0] do_araddr;
reg [ 3:0] do_arid;
reg [ 2:0] do_arsize;
reg [ 1:0] do_r_req;
wire [ 3:0] do_r_req_pos;
assign cpu_arid = do_arid;
assign cpu_araddr = do_araddr;
assign cpu_arlen = 8'd0;
assign cpu_arsize = do_arsize;
assign cpu_arburst = 2'd1;
assign cpu_arlock = 2'd0;
assign cpu_arcache = 4'd0;
assign cpu_arprot = 3'd0;
assign cpu_arvalid = |do_r_req;
assign mem_axi_arready = cpu_arready;
assign fetch_axi_arready = cpu_arready;
assign mem_axi_rid = cpu_rid;
assign fetch_axi_rid = cpu_rid;
assign mem_axi_rdata = cpu_rdata;
assign fetch_axi_rdata = cpu_rdata;
assign mem_axi_rvalid = cpu_rvalid;
assign fetch_axi_rvalid = cpu_rvalid;
assign cpu_rready = fetch_axi_rready || mem_axi_rready;
assign cpu_awid = mem_axi_awid;
assign cpu_awaddr = mem_axi_awaddr;
assign cpu_awlen = 8'd0;
assign cpu_awsize = mem_axi_awsize;
assign cpu_awburst = 2'd1;
assign cpu_awlock = 2'd0;
assign cpu_awcache = 2'd0;
assign cpu_awprot = 4'd0;
assign cpu_awvalid = mem_axi_awvalid;
assign mem_axi_awready = cpu_awready;
assign cpu_wid = mem_axi_wid;
assign cpu_wdata = mem_axi_wdata;
assign cpu_wstrb = mem_axi_wstrb;
assign cpu_wlast = 1'd1;
assign cpu_wvalid = mem_axi_wvalid;
assign mem_axi_wready = cpu_wready;
assign mem_axi_bid = cpu_bid;
assign mem_axi_bresp = cpu_bresp;
assign mem_axi_bvalid = cpu_bvalid;
assign cpu_bready = mem_axi_bready;
assign PC_refresh = cpu_arvalid && cpu_arready && cpu_arid==4'd0;
always @(posedge clk) begin
if (rst) begin
arvalid_r <= 1'b0;
first_fetch <= 1'b1;
end
else if (cpu_arready&&cpu_arvalid&&cpu_arid==4'd0) begin
arvalid_r <= 1'b0;
first_fetch <= 1'b0;
end
else if (cpu_rready&&cpu_rvalid&&cpu_rid==4'd0) begin
arvalid_r <= 1'b1;
first_fetch <= 1'b0;
end
end
always @ (posedge clk) begin
if (rst) begin
do_r_req <= 2'd0;
end
else begin
if (do_r_req==2'd0) begin
if (first_fetch) begin
do_r_req <= 2'd1;
end
else if (do_req_raddr) begin
do_r_req <= 2'd3;
end
else if (arvalid_r&&(data_r_req!=2'd2||data_r_req!=2'd1)&&!IR_buffer_valid&&!ID_EXE_Stall) begin
do_r_req <= 2'd2;
end
end
else begin
if (do_r_req==2'd1||do_r_req==2'd2) begin
if (cpu_arready&&cpu_arid==4'd0) begin
do_r_req <= 2'd0;
end
end
if (do_r_req==2'd3) begin
if (cpu_arready&&cpu_arid==4'd1) begin
do_r_req <= 2'd0;
end
end
end
end
end
assign do_r_req_pos[0] = 1'b0;
assign do_r_req_pos[1] = do_r_req==2'd0 && first_fetch;
assign do_r_req_pos[2] = do_r_req==2'd0 && !ID_EXE_Stall && arvalid_r&&(data_r_req!=2'd2||data_r_req!=2'd1)&&!IR_buffer_valid;
assign do_r_req_pos[3] = do_r_req==2'd0 && do_req_raddr;
always @ (posedge clk) begin
if (rst) begin
do_arid <= 'd0;
do_arsize <= 'd0;
do_araddr <= 'd0;
end
else begin
if (do_r_req_pos[1]||do_r_req_pos[2]) begin
do_arid <= `INST_ARID;
do_arsize <= 3'd2;
do_araddr <= {PC[31:2],2'd0};
end
if (do_r_req_pos[3]) begin
do_arid <= `MEM_ARID;
do_arsize <= mem_axi_arsize;
do_araddr <= mem_axi_araddr;
end
end
end
endmodule | 0 |
4,908 | data/full_repos/permissive/112219256/nextpc_gen.v | 112,219,256 | nextpc_gen.v | v | 73 | 115 | [] | [] | [] | [(11, 72)] | null | null | 1: b"%Error: data/full_repos/permissive/112219256/nextpc_gen.v:63: Cannot find file containing module: 'MUX_4_32'\n MUX_4_32 PCS_MUX(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.v\n data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.sv\n MUX_4_32\n MUX_4_32.v\n MUX_4_32.sv\n obj_dir/MUX_4_32\n obj_dir/MUX_4_32.v\n obj_dir/MUX_4_32.sv\n%Error: Exiting due to 1 error(s)\n" | 3,315 | module | module nextpc_gen(
input clk ,
input rst ,
input PCWrite ,
input JSrc ,
input eret ,
input ex_int_handle ,
input [ 1:0] PCSrc ,
input [31:0] JR_target ,
input [31:0] J_target ,
input [31:0] Br_addr ,
input [31:0] epc ,
output reg PC_AdEL ,
output reg [31:0] PC ,
output reg [31:0] PC_buffer ,
input PC_refresh
);
parameter reset_addr = 32'hbfc00000;
parameter except_addr = 32'hbfc00380;
reg [31:0] PC_next;
wire [31:0] Jump_addr, inst_addr, PC_mux;
assign Jump_addr = JSrc ? JR_target : J_target;
assign inst_addr = ex_int_handle ? except_addr :
eret ? epc : PC_mux;
always @(posedge clk) begin
if (rst) begin
PC <= reset_addr;
PC_next <= reset_addr + 32'd4;
PC_buffer <= 'd0;
PC_AdEL <= 'd0;
end
else if (PC_refresh) begin
PC <= inst_addr;
PC_next <= inst_addr + 32'd4;
PC_buffer <= PC;
PC_AdEL <= |PC[1:0] ? 1'b1 : 1'b0;
end
else begin
PC_next <= PC_next;
PC <= PC;
PC_buffer <= PC_buffer;
PC_AdEL <= PC_AdEL ;
end
end
MUX_4_32 PCS_MUX(
.Src1 ( PC_next),
.Src2 ( Jump_addr),
.Src3 ( Br_addr),
.Src4 ( 32'd0),
.op ( PCSrc),
.Result ( PC_mux)
);
endmodule | module nextpc_gen(
input clk ,
input rst ,
input PCWrite ,
input JSrc ,
input eret ,
input ex_int_handle ,
input [ 1:0] PCSrc ,
input [31:0] JR_target ,
input [31:0] J_target ,
input [31:0] Br_addr ,
input [31:0] epc ,
output reg PC_AdEL ,
output reg [31:0] PC ,
output reg [31:0] PC_buffer ,
input PC_refresh
); |
parameter reset_addr = 32'hbfc00000;
parameter except_addr = 32'hbfc00380;
reg [31:0] PC_next;
wire [31:0] Jump_addr, inst_addr, PC_mux;
assign Jump_addr = JSrc ? JR_target : J_target;
assign inst_addr = ex_int_handle ? except_addr :
eret ? epc : PC_mux;
always @(posedge clk) begin
if (rst) begin
PC <= reset_addr;
PC_next <= reset_addr + 32'd4;
PC_buffer <= 'd0;
PC_AdEL <= 'd0;
end
else if (PC_refresh) begin
PC <= inst_addr;
PC_next <= inst_addr + 32'd4;
PC_buffer <= PC;
PC_AdEL <= |PC[1:0] ? 1'b1 : 1'b0;
end
else begin
PC_next <= PC_next;
PC <= PC;
PC_buffer <= PC_buffer;
PC_AdEL <= PC_AdEL ;
end
end
MUX_4_32 PCS_MUX(
.Src1 ( PC_next),
.Src2 ( Jump_addr),
.Src3 ( Br_addr),
.Src4 ( 32'd0),
.op ( PCSrc),
.Result ( PC_mux)
);
endmodule | 0 |
4,909 | data/full_repos/permissive/112219256/reg_file.v | 112,219,256 | reg_file.v | v | 47 | 69 | [] | [] | [] | [(14, 46)] | null | data/verilator_xmls/4154b2cf-3bec-4f85-ae0e-188b5f859c9f.xml | null | 3,316 | module | module reg_file(
input clk,
input rst,
input [`ADDR_WIDTH - 1:0] waddr,
input [`ADDR_WIDTH - 1:0] raddr1,
input [`ADDR_WIDTH - 1:0] raddr2,
input [ 3:0] wen,
input [`DATA_WIDTH - 1:0] wdata,
output [`DATA_WIDTH - 1:0] rdata1,
output [`DATA_WIDTH - 1:0] rdata2
);
reg [`DATA_WIDTH - 1:0] mem [0:(1 << `ADDR_WIDTH )- 1];
integer i;
always @ (posedge clk)
begin
if (rst == 1)
begin
for (i = 0; i < 1 << `ADDR_WIDTH ; i = i + 1)
mem[i] <= `DATA_WIDTH'd0;
end
else if (wen != 4'd0 && waddr != 5'd0) begin
mem[waddr][31:24] <= {8{wen[3]}} & wdata[31:24];
mem[waddr][23:16] <= {8{wen[2]}} & wdata[23:16];
mem[waddr][15: 8] <= {8{wen[1]}} & wdata[15: 8];
mem[waddr][ 7: 0] <= {8{wen[0]}} & wdata[ 7: 0];
end
end
assign rdata1 = mem[raddr1];
assign rdata2 = mem[raddr2];
endmodule | module reg_file(
input clk,
input rst,
input [`ADDR_WIDTH - 1:0] waddr,
input [`ADDR_WIDTH - 1:0] raddr1,
input [`ADDR_WIDTH - 1:0] raddr2,
input [ 3:0] wen,
input [`DATA_WIDTH - 1:0] wdata,
output [`DATA_WIDTH - 1:0] rdata1,
output [`DATA_WIDTH - 1:0] rdata2
); |
reg [`DATA_WIDTH - 1:0] mem [0:(1 << `ADDR_WIDTH )- 1];
integer i;
always @ (posedge clk)
begin
if (rst == 1)
begin
for (i = 0; i < 1 << `ADDR_WIDTH ; i = i + 1)
mem[i] <= `DATA_WIDTH'd0;
end
else if (wen != 4'd0 && waddr != 5'd0) begin
mem[waddr][31:24] <= {8{wen[3]}} & wdata[31:24];
mem[waddr][23:16] <= {8{wen[2]}} & wdata[23:16];
mem[waddr][15: 8] <= {8{wen[1]}} & wdata[15: 8];
mem[waddr][ 7: 0] <= {8{wen[0]}} & wdata[ 7: 0];
end
end
assign rdata1 = mem[raddr1];
assign rdata2 = mem[raddr2];
endmodule | 0 |
4,910 | data/full_repos/permissive/112219256/writeback_stage.v | 112,219,256 | writeback_stage.v | v | 148 | 167 | [] | [] | [] | null | line:148: before: "/" | data/verilator_xmls/781c91e0-9370-4e82-b910-61f2ea1a8046.xml | null | 3,317 | module | module writeback_stage(
input wire clk,
input wire rst,
input wire MemToReg_MEM_WB,
input wire [ 3:0] RegWrite_MEM_WB,
input wire [ 1:0] MFHL_MEM_WB,
input wire LB_MEM_WB,
input wire LBU_MEM_WB,
input wire LH_MEM_WB,
input wire LHU_MEM_WB,
input wire [ 1:0] LW_MEM_WB,
input wire [ 1:0] MFHL_ID_EXE,
input wire [ 4:0] RegWaddr_MEM_WB,
input wire [31:0] ALUResult_MEM_WB,
input wire [31:0] RegRdata2_MEM_WB,
input wire [31:0] PC_MEM_WB,
input wire [31:0] MemRdata_MEM_WB,
input wire [31:0] HI_MEM_WB,
input wire [31:0] LO_MEM_WB,
output wire [ 4:0] RegWaddr_WB,
output wire [31:0] RegWdata_WB,
output wire [31:0] RegWdata_Bypass_WB,
output wire [ 3:0] RegWrite_WB,
output wire [31:0] PC_WB,
input wire [31:0] cp0Rdata_MEM_WB,
input wire mfc0_MEM_WB,
output wb_allowin,
input mem_to_wb_valid,
output wb_stage_valid
);
reg wb_valid;
wire wb_ready_go;
assign wb_ready_go = 1'b1;
assign wb_allowin = !wb_valid || wb_ready_go;
always @ (posedge clk) begin
if (rst) begin
wb_valid <= 1'b0;
end
else if (wb_allowin) begin
wb_valid <= mem_to_wb_valid;
end
end
assign wb_stage_valid = wb_valid;
wire MemToReg_WB;
wire [31:0] HI_LO_out;
wire [31:0] MemRdata_Final;
assign HI_LO_out = { 32{wb_valid}} &
({32{MFHL_MEM_WB[1]}} & HI_MEM_WB |
{32{MFHL_MEM_WB[0]}} & LO_MEM_WB );
assign PC_WB = PC_MEM_WB;
assign RegWaddr_WB = RegWaddr_MEM_WB & { 5{wb_valid}};
assign MemToReg_WB = MemToReg_MEM_WB & wb_valid ;
assign RegWrite_WB = RegWrite_MEM_WB & { 4{wb_valid}};
assign RegWdata_WB = {32{wb_valid}} &
(|MFHL_MEM_WB ? HI_LO_out :
(MemToReg_WB ? MemRdata_Final :
(mfc0_MEM_WB ? cp0Rdata_MEM_WB : ALUResult_MEM_WB)));
assign RegWdata_Bypass_WB =
(|MFHL_MEM_WB ? HI_LO_out :
(MemToReg_WB ? MemRdata_Final :
(mfc0_MEM_WB ? cp0Rdata_MEM_WB :ALUResult_MEM_WB)));
RegWdata_Sel RegWdata (
.MemRdata ( MemRdata_MEM_WB),
.Rt_data ( RegRdata2_MEM_WB),
.LW ( LW_MEM_WB),
.vaddr ( ALUResult_MEM_WB[1:0]),
.LB ( LB_MEM_WB),
.LBU ( LBU_MEM_WB),
.LH ( LH_MEM_WB),
.LHU ( LHU_MEM_WB),
.RegWdata ( MemRdata_Final)
);
endmodule | module writeback_stage(
input wire clk,
input wire rst,
input wire MemToReg_MEM_WB,
input wire [ 3:0] RegWrite_MEM_WB,
input wire [ 1:0] MFHL_MEM_WB,
input wire LB_MEM_WB,
input wire LBU_MEM_WB,
input wire LH_MEM_WB,
input wire LHU_MEM_WB,
input wire [ 1:0] LW_MEM_WB,
input wire [ 1:0] MFHL_ID_EXE,
input wire [ 4:0] RegWaddr_MEM_WB,
input wire [31:0] ALUResult_MEM_WB,
input wire [31:0] RegRdata2_MEM_WB,
input wire [31:0] PC_MEM_WB,
input wire [31:0] MemRdata_MEM_WB,
input wire [31:0] HI_MEM_WB,
input wire [31:0] LO_MEM_WB,
output wire [ 4:0] RegWaddr_WB,
output wire [31:0] RegWdata_WB,
output wire [31:0] RegWdata_Bypass_WB,
output wire [ 3:0] RegWrite_WB,
output wire [31:0] PC_WB,
input wire [31:0] cp0Rdata_MEM_WB,
input wire mfc0_MEM_WB,
output wb_allowin,
input mem_to_wb_valid,
output wb_stage_valid
); |
reg wb_valid;
wire wb_ready_go;
assign wb_ready_go = 1'b1;
assign wb_allowin = !wb_valid || wb_ready_go;
always @ (posedge clk) begin
if (rst) begin
wb_valid <= 1'b0;
end
else if (wb_allowin) begin
wb_valid <= mem_to_wb_valid;
end
end
assign wb_stage_valid = wb_valid;
wire MemToReg_WB;
wire [31:0] HI_LO_out;
wire [31:0] MemRdata_Final;
assign HI_LO_out = { 32{wb_valid}} &
({32{MFHL_MEM_WB[1]}} & HI_MEM_WB |
{32{MFHL_MEM_WB[0]}} & LO_MEM_WB );
assign PC_WB = PC_MEM_WB;
assign RegWaddr_WB = RegWaddr_MEM_WB & { 5{wb_valid}};
assign MemToReg_WB = MemToReg_MEM_WB & wb_valid ;
assign RegWrite_WB = RegWrite_MEM_WB & { 4{wb_valid}};
assign RegWdata_WB = {32{wb_valid}} &
(|MFHL_MEM_WB ? HI_LO_out :
(MemToReg_WB ? MemRdata_Final :
(mfc0_MEM_WB ? cp0Rdata_MEM_WB : ALUResult_MEM_WB)));
assign RegWdata_Bypass_WB =
(|MFHL_MEM_WB ? HI_LO_out :
(MemToReg_WB ? MemRdata_Final :
(mfc0_MEM_WB ? cp0Rdata_MEM_WB :ALUResult_MEM_WB)));
RegWdata_Sel RegWdata (
.MemRdata ( MemRdata_MEM_WB),
.Rt_data ( RegRdata2_MEM_WB),
.LW ( LW_MEM_WB),
.vaddr ( ALUResult_MEM_WB[1:0]),
.LB ( LB_MEM_WB),
.LBU ( LBU_MEM_WB),
.LH ( LH_MEM_WB),
.LHU ( LHU_MEM_WB),
.RegWdata ( MemRdata_Final)
);
endmodule | 0 |
4,911 | data/full_repos/permissive/112219256/writeback_stage.v | 112,219,256 | writeback_stage.v | v | 148 | 167 | [] | [] | [] | null | line:148: before: "/" | data/verilator_xmls/781c91e0-9370-4e82-b910-61f2ea1a8046.xml | null | 3,317 | module | module RegWdata_Sel(
input [31:0] MemRdata,
input [31:0] Rt_data,
input [ 1:0] LW,
input [ 1:0] vaddr,
input LB,
input LBU,
input LH,
input LHU,
output [31:0] RegWdata
);
wire [31:0] LWL_data, LWR_data;
wire [3:0] v;
wire LWL, LWR;
wire [7:0] LB_data;
wire [15:0] LH_data;
assign LWL = LW[1] & ~LW[0];
assign LWR = ~LW[1] & LW[0];
assign v[3] = vaddr[1] & vaddr[0];
assign v[2] = vaddr[1] & ~vaddr[0];
assign v[1] = ~vaddr[1] & vaddr[0];
assign v[0] = ~vaddr[1] & ~vaddr[0];
assign LWL_data = ({32{v[0]}} & {MemRdata[ 7:0],Rt_data[23:0]} | {32{v[1]}} & {MemRdata[15:0],Rt_data[15:0]}) |
({32{v[2]}} & {MemRdata[23:0],Rt_data[ 7:0]} | {32{v[3]}} & MemRdata);
assign LWR_data = ({32{v[3]}} & {Rt_data[31: 8],MemRdata[31:24]} | {32{v[2]}} & {Rt_data[31:16],MemRdata[31:16]}) |
({32{v[1]}} & {Rt_data[31:24],MemRdata[31: 8]} | {32{v[0]}} & MemRdata);
assign LB_data = ({8{v[0]}} & MemRdata[ 7: 0] | {8{v[1]}} & MemRdata[15: 8]) |
({8{v[2]}} & MemRdata[23:16] | {8{v[3]}} & MemRdata[31:24]) ;
assign LH_data = {16{v[0]}} & MemRdata[15: 0] |
{16{v[2]}} & MemRdata[31:16] ;
assign RegWdata = (({32{&LW}} & MemRdata | {32{ LB}} & {{24{LB_data[7]}}, LB_data}) | ({32{LBU}} & {24'd0,LB_data} | {32{ LH}} & {{16{LH_data[15]}}, LH_data})) |
(({32{LHU}} & {16'd0,LH_data} | {32{LWL}} & LWL_data) | {32{LWR}} & LWR_data) ;
endmodule | module RegWdata_Sel(
input [31:0] MemRdata,
input [31:0] Rt_data,
input [ 1:0] LW,
input [ 1:0] vaddr,
input LB,
input LBU,
input LH,
input LHU,
output [31:0] RegWdata
); |
wire [31:0] LWL_data, LWR_data;
wire [3:0] v;
wire LWL, LWR;
wire [7:0] LB_data;
wire [15:0] LH_data;
assign LWL = LW[1] & ~LW[0];
assign LWR = ~LW[1] & LW[0];
assign v[3] = vaddr[1] & vaddr[0];
assign v[2] = vaddr[1] & ~vaddr[0];
assign v[1] = ~vaddr[1] & vaddr[0];
assign v[0] = ~vaddr[1] & ~vaddr[0];
assign LWL_data = ({32{v[0]}} & {MemRdata[ 7:0],Rt_data[23:0]} | {32{v[1]}} & {MemRdata[15:0],Rt_data[15:0]}) |
({32{v[2]}} & {MemRdata[23:0],Rt_data[ 7:0]} | {32{v[3]}} & MemRdata);
assign LWR_data = ({32{v[3]}} & {Rt_data[31: 8],MemRdata[31:24]} | {32{v[2]}} & {Rt_data[31:16],MemRdata[31:16]}) |
({32{v[1]}} & {Rt_data[31:24],MemRdata[31: 8]} | {32{v[0]}} & MemRdata);
assign LB_data = ({8{v[0]}} & MemRdata[ 7: 0] | {8{v[1]}} & MemRdata[15: 8]) |
({8{v[2]}} & MemRdata[23:16] | {8{v[3]}} & MemRdata[31:24]) ;
assign LH_data = {16{v[0]}} & MemRdata[15: 0] |
{16{v[2]}} & MemRdata[31:16] ;
assign RegWdata = (({32{&LW}} & MemRdata | {32{ LB}} & {{24{LB_data[7]}}, LB_data}) | ({32{LBU}} & {24'd0,LB_data} | {32{ LH}} & {{16{LH_data[15]}}, LH_data})) |
(({32{LHU}} & {16'd0,LH_data} | {32{LWL}} & LWL_data) | {32{LWR}} & LWR_data) ;
endmodule | 0 |
4,918 | data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v | 1,122,957 | alt_mem_ddrx_burst_gen.v | v | 1,435 | 161 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:4: Cannot find include file: alt_mem_ddrx_define.iv\n`include "alt_mem_ddrx_define.iv" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy,data/full_repos/permissive/1122957/alt_mem_ddrx_define.iv\n data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy,data/full_repos/permissive/1122957/alt_mem_ddrx_define.iv.v\n data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy,data/full_repos/permissive/1122957/alt_mem_ddrx_define.iv.sv\n alt_mem_ddrx_define.iv\n alt_mem_ddrx_define.iv.v\n alt_mem_ddrx_define.iv.sv\n obj_dir/alt_mem_ddrx_define.iv\n obj_dir/alt_mem_ddrx_define.iv.v\n obj_dir/alt_mem_ddrx_define.iv.sv\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:557: Define or directive not defined: \'`MMR_TYPE_DDR3\'\n if (cfg_type == `MMR_TYPE_DDR3 && do_burst_chop) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:557: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n if (cfg_type == `MMR_TYPE_DDR3 && do_burst_chop) \n ^~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:957: Define or directive not defined: \'`MMR_TYPE_DDR3\'\n if (do_burst_chop && cfg_type == `MMR_TYPE_DDR3)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:957: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (do_burst_chop && cfg_type == `MMR_TYPE_DDR3)\n ^\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1059: Define or directive not defined: \'`MMR_TYPE_DDR3\'\n if (cfg_type == `MMR_TYPE_DDR3) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1170: Define or directive not defined: \'`MMR_TYPE_LPDDR1\'\n if (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2) \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1170: Define or directive not defined: \'`MMR_TYPE_LPDDR2\'\n if (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2) \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1184: syntax error, unexpected <=, expecting IDENTIFIER\n int_do_burst_terminate <= 1\'b1;\n ^~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1186: syntax error, unexpected <=, expecting IDENTIFIER\n int_do_burst_terminate <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1193: syntax error, unexpected <=, expecting IDENTIFIER\n int_do_burst_terminate <= 1\'b1;\n ^~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1195: syntax error, unexpected <=, expecting IDENTIFIER\n int_do_burst_terminate <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1215: syntax error, unexpected <=, expecting IDENTIFIER\n int_do_burst_terminate <= 1\'b1;\n ^~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1217: syntax error, unexpected <=, expecting IDENTIFIER\n int_do_burst_terminate <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1237: syntax error, unexpected <=, expecting IDENTIFIER\n int_do_burst_terminate <= 1\'b1;\n ^~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1239: syntax error, unexpected <=, expecting IDENTIFIER\n int_do_burst_terminate <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1331: syntax error, unexpected \'[\', expecting IDENTIFIER\n do_burst_terminate [AFI_INTF_HIGH_PHASE] = 0;\n ^\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1333: syntax error, unexpected \'[\', expecting IDENTIFIER\n do_burst_terminate [AFI_INTF_HIGH_PHASE] = int_do_burst_terminate;\n ^\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1343: syntax error, unexpected \'[\', expecting IDENTIFIER\n do_burst_terminate [AFI_INTF_LOW_PHASE] = 0;\n ^\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v:1345: syntax error, unexpected \'[\', expecting IDENTIFIER\n do_burst_terminate [AFI_INTF_LOW_PHASE] = int_do_burst_terminate;\n ^\n%Error: Cannot continue\n' | 3,325 | module | module alt_mem_ddrx_burst_gen #
( parameter
CFG_DWIDTH_RATIO = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_REG_GRANT = 0,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_ENABLE_BURST_INTERRUPT = 0,
CFG_ENABLE_BURST_TERMINATE = 0,
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_TCCD = 4,
CFG_ENABLE_BURST_GEN_OUTPUT_REG = 0
)
(
ctl_clk,
ctl_reset_n,
cfg_type,
cfg_burst_length,
cfg_tccd,
arb_do_write,
arb_do_read,
arb_do_burst_chop,
arb_do_burst_terminate,
arb_do_auto_precharge,
arb_do_rmw_correct,
arb_do_rmw_partial,
arb_do_activate,
arb_do_precharge,
arb_do_precharge_all,
arb_do_refresh,
arb_do_self_refresh,
arb_do_power_down,
arb_do_deep_pdown,
arb_do_zq_cal,
arb_do_lmr,
arb_to_chipsel,
arb_to_chip,
arb_to_bank,
arb_to_row,
arb_to_col,
arb_localid,
arb_dataid,
arb_size,
bg_do_write_combi,
bg_do_read_combi,
bg_do_burst_chop_combi,
bg_do_burst_terminate_combi,
bg_do_activate_combi,
bg_do_precharge_combi,
bg_to_chip_combi,
bg_effective_size_combi,
bg_interrupt_ready_combi,
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_auto_precharge,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_deep_pdown,
bg_do_zq_cal,
bg_do_lmr,
bg_to_chipsel,
bg_to_chip,
bg_to_bank,
bg_to_row,
bg_to_col,
bg_doing_write,
bg_doing_read,
bg_rdwr_data_valid,
bg_interrupt_ready,
bg_localid,
bg_dataid,
bg_size,
bg_effective_size
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
input [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
input [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
output bg_interrupt_ready_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
output bg_doing_write;
output bg_doing_read;
output bg_rdwr_data_valid;
output bg_interrupt_ready;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
output [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
reg bg_doing_write;
reg bg_doing_read;
reg bg_rdwr_data_valid;
reg bg_interrupt_ready;
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_size;
reg [CFG_DATA_ID_WIDTH - 1 : 0] int_dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] int_to_col;
reg [2 : 0] int_col_address;
reg [2 : 0] int_address_left;
reg int_do_row_req;
reg int_do_col_req;
reg int_do_rd_req;
reg int_do_wr_req;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_rmw_partial;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] size;
reg [CFG_DATA_ID_WIDTH - 1 : 0] dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] to_col;
reg [2 : 0] col_address;
reg [2 : 0] address_left;
reg do_row_req;
reg do_col_req;
reg do_rd_req;
reg do_wr_req;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_rmw_partial;
reg [3 : 0] max_local_burst_size;
reg [3 : 0] max_local_burst_size_divide_2;
reg [3 : 0] max_local_burst_size_minus_2;
reg [3 : 0] max_local_burst_size_divide_2_and_minus_2;
reg [3 : 0] burst_left;
reg current_valid;
reg delayed_valid;
reg combined_valid;
reg [3 : 0] max_burst_left;
reg delayed_doing;
reg last_is_write;
reg last_is_read;
reg [CFG_PORT_WIDTH_TCCD - 2 : 0] n_prefetch;
reg int_allow_interrupt;
reg int_interrupt_ready;
reg int_interrupt_gate;
reg int_allow_terminate;
reg int_do_burst_terminate;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
reg int_do_req;
reg doing_burst_terminate;
reg terminate_doing;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_partial;
reg [CFG_DATA_ID_WIDTH - 1 : 0] delayed_dataid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] combined_dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] modified_to_col;
wire zero = 1'b0;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
reg bg_interrupt_ready_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_burst_terminate;
reg doing_write;
reg doing_read;
reg rdwr_data_valid;
reg interrupt_ready;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] effective_size;
generate
if (CFG_ENABLE_BURST_GEN_OUTPUT_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (! ctl_reset_n)
begin
bg_do_write <= 0;
bg_do_read <= 0;
bg_do_auto_precharge <= 0;
bg_do_rmw_correct <= 0;
bg_do_rmw_partial <= 0;
bg_do_activate <= 0;
bg_do_precharge <= 0;
bg_do_precharge_all <= 0;
bg_do_refresh <= 0;
bg_do_self_refresh <= 0;
bg_do_power_down <= 0;
bg_do_deep_pdown <= 0;
bg_do_zq_cal <= 0;
bg_do_lmr <= 0;
bg_to_chip <= 0;
bg_to_chipsel <= 0;
bg_to_bank <= 0;
bg_to_row <= 0;
bg_localid <= 0;
bg_size <= 0;
bg_to_col <= 0;
bg_dataid <= 0;
bg_do_burst_chop <= 0;
bg_do_burst_terminate <= 0;
bg_doing_write <= 0;
bg_doing_read <= 0;
bg_rdwr_data_valid <= 0;
bg_interrupt_ready <= 0;
bg_effective_size <= 0;
end
else
begin
bg_do_write <= arb_do_write;
bg_do_read <= arb_do_read;
bg_do_auto_precharge <= arb_do_auto_precharge;
bg_do_rmw_correct <= combined_do_rmw_correct;
bg_do_rmw_partial <= combined_do_rmw_partial;
bg_do_activate <= arb_do_activate;
bg_do_precharge <= arb_do_precharge;
bg_do_precharge_all <= arb_do_precharge_all;
bg_do_refresh <= arb_do_refresh;
bg_do_self_refresh <= arb_do_self_refresh;
bg_do_power_down <= arb_do_power_down;
bg_do_deep_pdown <= arb_do_deep_pdown;
bg_do_zq_cal <= arb_do_zq_cal;
bg_do_lmr <= arb_do_lmr;
bg_to_chip <= arb_to_chip;
bg_to_chipsel <= arb_to_chipsel;
bg_to_bank <= arb_to_bank;
bg_to_row <= arb_to_row;
bg_localid <= arb_localid;
bg_size <= arb_size;
bg_to_col <= modified_to_col;
bg_dataid <= combined_dataid;
bg_do_burst_chop <= do_burst_chop;
bg_do_burst_terminate <= do_burst_terminate;
bg_doing_write <= doing_write;
bg_doing_read <= doing_read;
bg_rdwr_data_valid <= rdwr_data_valid;
bg_interrupt_ready <= interrupt_ready;
bg_effective_size <= effective_size;
end
end
end
else
begin
always @ (*)
begin
bg_do_write = arb_do_write;
bg_do_read = arb_do_read;
bg_do_auto_precharge = arb_do_auto_precharge;
bg_do_activate = arb_do_activate;
bg_do_precharge = arb_do_precharge;
bg_do_precharge_all = arb_do_precharge_all;
bg_do_refresh = arb_do_refresh;
bg_do_self_refresh = arb_do_self_refresh;
bg_do_power_down = arb_do_power_down;
bg_do_deep_pdown = arb_do_deep_pdown;
bg_do_zq_cal = arb_do_zq_cal;
bg_do_lmr = arb_do_lmr;
bg_to_chip = arb_to_chip;
bg_to_chipsel = arb_to_chipsel;
bg_to_bank = arb_to_bank;
bg_to_row = arb_to_row;
bg_localid = arb_localid;
bg_size = arb_size;
bg_do_burst_chop = do_burst_chop;
bg_do_burst_terminate = do_burst_terminate;
bg_doing_write = doing_write;
bg_doing_read = doing_read;
bg_rdwr_data_valid = rdwr_data_valid;
bg_interrupt_ready = interrupt_ready;
bg_effective_size = effective_size;
end
always @ (*)
begin
bg_to_col = modified_to_col;
end
always @ (*)
begin
bg_do_rmw_correct = combined_do_rmw_correct;
bg_do_rmw_partial = combined_do_rmw_partial;
end
always @ (*)
begin
bg_dataid = combined_dataid;
end
end
endgenerate
always @ (*)
begin
bg_do_write_combi = arb_do_write;
bg_do_read_combi = arb_do_read;
bg_do_burst_chop_combi = do_burst_chop;
bg_do_burst_terminate_combi = do_burst_terminate;
bg_do_activate_combi = arb_do_activate;
bg_do_precharge_combi = arb_do_precharge;
bg_to_chip_combi = arb_to_chip;
bg_effective_size_combi = effective_size;
bg_interrupt_ready_combi = interrupt_ready;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size <= 0;
end
else
begin
max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size_divide_2 <= 0;
max_local_burst_size_minus_2 <= 0;
max_local_burst_size_divide_2_and_minus_2 <= 0;
end
else
begin
max_local_burst_size_divide_2 <= max_local_burst_size / 2;
max_local_burst_size_minus_2 <= max_local_burst_size - 2'd2;
max_local_burst_size_divide_2_and_minus_2 <= (max_local_burst_size / 2) - 2'd2;
end
end
always @ (*)
begin
int_col_address = 0;
if (cfg_type == `MMR_TYPE_DDR3 && do_burst_chop)
begin
if (max_local_burst_size [2])
int_col_address [0 ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
else
int_col_address = 0;
end
else if (max_local_burst_size [0])
int_col_address = 0;
else if (max_local_burst_size [1])
int_col_address [0 ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
else if (max_local_burst_size [2])
int_col_address [1 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 1 : (CFG_DWIDTH_RATIO / 2)];
else if (max_local_burst_size [3])
int_col_address [2 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 2 : (CFG_DWIDTH_RATIO / 2)];
end
always @ (*)
begin
col_address = int_col_address;
end
always @ (*)
begin
int_to_col = arb_to_col;
end
always @ (*)
begin
int_do_row_req = (|arb_do_activate) | (|arb_do_precharge);
end
always @ (*)
begin
int_do_col_req = (|arb_do_write) | (|arb_do_read);
end
always @ (*)
begin
int_do_rd_req = |arb_do_read;
int_do_wr_req = |arb_do_write;
end
always @ (*)
begin
int_do_burst_chop = arb_do_burst_chop;
end
always @ (*)
begin
int_do_rmw_correct = arb_do_rmw_correct;
int_do_rmw_partial = arb_do_rmw_partial;
end
always @ (*)
begin
int_size = arb_size;
int_dataid = arb_dataid;
end
always @ (*)
begin
size = int_size;
dataid = int_dataid;
to_col = int_to_col;
do_row_req = int_do_row_req;
do_col_req = int_do_col_req;
do_rd_req = int_do_rd_req;
do_wr_req = int_do_wr_req;
do_burst_chop = int_do_burst_chop;
do_rmw_correct = int_do_rmw_correct;
do_rmw_partial = int_do_rmw_partial;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
address_left <= 0;
end
else
begin
if (do_col_req)
begin
if (col_address > 1'b1)
address_left <= col_address - 2'd2;
else
address_left <= 0;
end
else if (address_left != 0)
address_left <= address_left - 1'b1;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
burst_left <= 0;
end
else
begin
if (do_col_req)
begin
if (col_address == 0)
begin
if (size > 1'b1)
burst_left <= size - 2'd2;
else
burst_left <= 0;
end
else if (col_address == 1'b1)
begin
burst_left <= size - 1'b1;
end
else
begin
burst_left <= size;
end
end
else if (address_left == 0 && burst_left != 0)
burst_left <= burst_left - 1'b1;
end
end
always @ (*)
begin
if (do_col_req && col_address == 0)
current_valid = 1'b1;
else
current_valid = 1'b0;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_valid <= 0;
end
else
begin
if (do_col_req && ((col_address == 0 && size > 1) || col_address == 1'b1))
delayed_valid <= 1'b1;
else if (address_left == 0 && burst_left > 0)
delayed_valid <= 1'b1;
else
delayed_valid <= 1'b0;
end
end
always @ (*)
begin
combined_valid = current_valid | delayed_valid;
end
always @ (*)
begin
rdwr_data_valid = combined_valid;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_burst_left <= 0;
end
else
begin
if (do_col_req)
begin
if (do_burst_chop)
begin
if (max_local_burst_size_divide_2 <= 2)
max_burst_left <= 0;
else
max_burst_left <= max_local_burst_size_divide_2_and_minus_2;
end
else
begin
if (max_local_burst_size <= 2)
max_burst_left <= 0;
else
max_burst_left <= max_local_burst_size_minus_2;
end
end
else if (max_burst_left != 0)
max_burst_left <= max_burst_left - 1'b1;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_doing <= 0;
end
else
begin
if (do_col_req)
begin
if (max_local_burst_size <= 1'b1)
delayed_doing <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 2'd2)
delayed_doing <= 1'b0;
else
delayed_doing <= 1'b1;
end
else if (max_burst_left > 0)
delayed_doing <= 1'b1;
else
delayed_doing <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last_is_write <= 1'b0;
last_is_read <= 1'b0;
end
else
begin
if (do_wr_req)
begin
last_is_write <= 1'b1;
last_is_read <= 1'b0;
end
else if (do_rd_req)
begin
last_is_write <= 1'b0;
last_is_read <= 1'b1;
end
end
end
always @ (*)
begin
if (do_rd_req)
doing_write = 1'b0;
else if (do_wr_req)
doing_write = ~terminate_doing;
else if (last_is_write)
doing_write = delayed_doing & ~terminate_doing;
else
doing_write = 1'b0;
end
always @ (*)
begin
if (do_wr_req)
doing_read = 1'b0;
else if (do_rd_req)
doing_read = ~terminate_doing;
else if (last_is_read)
doing_read = delayed_doing & ~terminate_doing;
else
doing_read = 1'b0;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_do_rmw_correct <= 0;
delayed_do_rmw_partial <= 0;
end
else
begin
if (do_col_req)
begin
delayed_do_rmw_correct <= do_rmw_correct;
delayed_do_rmw_partial <= do_rmw_partial;
end
end
end
always @ (*)
begin
if (do_col_req)
begin
combined_do_rmw_correct = do_rmw_correct;
combined_do_rmw_partial = do_rmw_partial;
end
else if (delayed_doing)
begin
combined_do_rmw_correct = delayed_do_rmw_correct;
combined_do_rmw_partial = delayed_do_rmw_partial;
end
else
begin
combined_do_rmw_correct = 0;
combined_do_rmw_partial = 0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_dataid <= 0;
end
else
begin
if (do_col_req)
delayed_dataid <= dataid;
end
end
always @ (*)
begin
if (do_col_req)
combined_dataid = dataid;
else if (delayed_doing)
combined_dataid = delayed_dataid;
else
combined_dataid = 0;
end
always @ (*)
begin
modified_to_col = to_col;
if (do_burst_chop && cfg_type == `MMR_TYPE_DDR3)
begin
if (max_local_burst_size [1])
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 0 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [2])
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 1 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
end
end
else
begin
if (max_local_burst_size [0])
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 0 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [1])
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 1 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [2])
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 2 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 2 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [3])
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 3 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 3 : CFG_MEM_IF_COL_WIDTH] = 0;
end
end
end
generate
begin
if (CFG_ENABLE_BURST_INTERRUPT || CFG_ENABLE_BURST_TERMINATE)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
n_prefetch <= 0;
end
else
begin
n_prefetch <= cfg_tccd / (CFG_DWIDTH_RATIO / 2);
end
end
end
end
endgenerate
generate
begin
if (CFG_ENABLE_BURST_INTERRUPT)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_allow_interrupt <= 1'b1;
end
else
begin
if (cfg_type == `MMR_TYPE_DDR3)
int_allow_interrupt <= 1'b1;
else
begin
if (n_prefetch <= 1)
begin
if (do_col_req && ((col_address == 0 && size > 1) || col_address != 0))
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0)
int_allow_interrupt <= 1'b1;
end
else if (n_prefetch == 2)
begin
if (do_col_req)
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0 && max_burst_left [0] == 0)
int_allow_interrupt <= 1'b1;
end
else if (n_prefetch == 4)
begin
if (do_col_req)
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0 && max_burst_left [1 : 0] == 0)
int_allow_interrupt <= 1'b1;
end
end
end
end
always @ (*)
begin
int_interrupt_ready = int_allow_interrupt;
end
end
else
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_interrupt_ready <= 0;
end
else
begin
if (do_col_req)
begin
if (CFG_REG_GRANT)
begin
if (max_local_burst_size <= 2'd2)
int_interrupt_ready <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 3'd4)
int_interrupt_ready <= 1'b0;
else
int_interrupt_ready <= 1'b1;
end
else
begin
if (max_local_burst_size <= 1'b1)
int_interrupt_ready <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 2'd2)
int_interrupt_ready <= 1'b0;
else
int_interrupt_ready <= 1'b1;
end
end
else if (!CFG_REG_GRANT && max_burst_left > 0)
int_interrupt_ready <= 1'b1;
else if ( CFG_REG_GRANT && max_burst_left > 1'b1)
int_interrupt_ready <= 1'b1;
else
int_interrupt_ready <= 1'b0;
end
end
end
end
endgenerate
always @ (*)
begin
interrupt_ready = ~int_interrupt_ready;
end
generate
begin
if (CFG_ENABLE_BURST_TERMINATE)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else
begin
if (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2)
begin
if (n_prefetch <= 1)
begin
if (do_col_req && col_address != 0)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (do_col_req && col_address == 0 && size == 1'b1)
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0)
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
else if (n_prefetch == 2)
begin
if (do_col_req)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && (max_burst_left [0] == 0 || int_allow_terminate == 1'b1))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
else if (n_prefetch == 4)
begin
if (do_col_req)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && (max_burst_left [1 : 0] == 0 || int_allow_terminate == 1'b1))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
end
else
begin
int_allow_terminate <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_effective_size <= 0;
end
else
begin
if (do_col_req)
int_effective_size <= 1'b1;
else if (int_effective_size != {CFG_INT_SIZE_WIDTH{1'b1}})
int_effective_size <= int_effective_size + 1'b1;
end
end
end
else
begin
always @ (*)
begin
int_do_burst_terminate = zero;
end
always @ (*)
begin
int_effective_size = {CFG_INT_SIZE_WIDTH{zero}};
end
end
end
endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_terminate <= 1'b0;
end
else
begin
if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && ((|do_burst_terminate) == 1'b1 || doing_burst_terminate == 1'b1))
doing_burst_terminate <= 1'b1;
else
doing_burst_terminate <= 1'b0;
end
end
always @ (*)
begin
terminate_doing = (|do_burst_terminate) | doing_burst_terminate;
end
always @ (*)
begin
if (CFG_DWIDTH_RATIO == 2)
int_do_req = do_col_req | do_row_req;
else
int_do_req = do_col_req;
end
generate
begin
if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
always @ (*)
begin
do_burst_terminate = 0;
if (int_do_req)
do_burst_terminate [AFI_INTF_HIGH_PHASE] = 0;
else
do_burst_terminate [AFI_INTF_HIGH_PHASE] = int_do_burst_terminate;
end
end
else if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
always @ (*)
begin
do_burst_terminate = 0;
if (int_do_req)
do_burst_terminate [AFI_INTF_LOW_PHASE] = 0;
else
do_burst_terminate [AFI_INTF_LOW_PHASE] = int_do_burst_terminate;
end
end
end
endgenerate
always @ (*)
begin
effective_size = int_effective_size;
end
endmodule | module alt_mem_ddrx_burst_gen #
( parameter
CFG_DWIDTH_RATIO = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_REG_GRANT = 0,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_ENABLE_BURST_INTERRUPT = 0,
CFG_ENABLE_BURST_TERMINATE = 0,
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_TCCD = 4,
CFG_ENABLE_BURST_GEN_OUTPUT_REG = 0
)
(
ctl_clk,
ctl_reset_n,
cfg_type,
cfg_burst_length,
cfg_tccd,
arb_do_write,
arb_do_read,
arb_do_burst_chop,
arb_do_burst_terminate,
arb_do_auto_precharge,
arb_do_rmw_correct,
arb_do_rmw_partial,
arb_do_activate,
arb_do_precharge,
arb_do_precharge_all,
arb_do_refresh,
arb_do_self_refresh,
arb_do_power_down,
arb_do_deep_pdown,
arb_do_zq_cal,
arb_do_lmr,
arb_to_chipsel,
arb_to_chip,
arb_to_bank,
arb_to_row,
arb_to_col,
arb_localid,
arb_dataid,
arb_size,
bg_do_write_combi,
bg_do_read_combi,
bg_do_burst_chop_combi,
bg_do_burst_terminate_combi,
bg_do_activate_combi,
bg_do_precharge_combi,
bg_to_chip_combi,
bg_effective_size_combi,
bg_interrupt_ready_combi,
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_auto_precharge,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_deep_pdown,
bg_do_zq_cal,
bg_do_lmr,
bg_to_chipsel,
bg_to_chip,
bg_to_bank,
bg_to_row,
bg_to_col,
bg_doing_write,
bg_doing_read,
bg_rdwr_data_valid,
bg_interrupt_ready,
bg_localid,
bg_dataid,
bg_size,
bg_effective_size
); |
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
input [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
input [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
output bg_interrupt_ready_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
output bg_doing_write;
output bg_doing_read;
output bg_rdwr_data_valid;
output bg_interrupt_ready;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
output [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
reg bg_doing_write;
reg bg_doing_read;
reg bg_rdwr_data_valid;
reg bg_interrupt_ready;
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_size;
reg [CFG_DATA_ID_WIDTH - 1 : 0] int_dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] int_to_col;
reg [2 : 0] int_col_address;
reg [2 : 0] int_address_left;
reg int_do_row_req;
reg int_do_col_req;
reg int_do_rd_req;
reg int_do_wr_req;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_rmw_partial;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] size;
reg [CFG_DATA_ID_WIDTH - 1 : 0] dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] to_col;
reg [2 : 0] col_address;
reg [2 : 0] address_left;
reg do_row_req;
reg do_col_req;
reg do_rd_req;
reg do_wr_req;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_rmw_partial;
reg [3 : 0] max_local_burst_size;
reg [3 : 0] max_local_burst_size_divide_2;
reg [3 : 0] max_local_burst_size_minus_2;
reg [3 : 0] max_local_burst_size_divide_2_and_minus_2;
reg [3 : 0] burst_left;
reg current_valid;
reg delayed_valid;
reg combined_valid;
reg [3 : 0] max_burst_left;
reg delayed_doing;
reg last_is_write;
reg last_is_read;
reg [CFG_PORT_WIDTH_TCCD - 2 : 0] n_prefetch;
reg int_allow_interrupt;
reg int_interrupt_ready;
reg int_interrupt_gate;
reg int_allow_terminate;
reg int_do_burst_terminate;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
reg int_do_req;
reg doing_burst_terminate;
reg terminate_doing;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_partial;
reg [CFG_DATA_ID_WIDTH - 1 : 0] delayed_dataid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] combined_dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] modified_to_col;
wire zero = 1'b0;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
reg bg_interrupt_ready_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_burst_terminate;
reg doing_write;
reg doing_read;
reg rdwr_data_valid;
reg interrupt_ready;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] effective_size;
generate
if (CFG_ENABLE_BURST_GEN_OUTPUT_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (! ctl_reset_n)
begin
bg_do_write <= 0;
bg_do_read <= 0;
bg_do_auto_precharge <= 0;
bg_do_rmw_correct <= 0;
bg_do_rmw_partial <= 0;
bg_do_activate <= 0;
bg_do_precharge <= 0;
bg_do_precharge_all <= 0;
bg_do_refresh <= 0;
bg_do_self_refresh <= 0;
bg_do_power_down <= 0;
bg_do_deep_pdown <= 0;
bg_do_zq_cal <= 0;
bg_do_lmr <= 0;
bg_to_chip <= 0;
bg_to_chipsel <= 0;
bg_to_bank <= 0;
bg_to_row <= 0;
bg_localid <= 0;
bg_size <= 0;
bg_to_col <= 0;
bg_dataid <= 0;
bg_do_burst_chop <= 0;
bg_do_burst_terminate <= 0;
bg_doing_write <= 0;
bg_doing_read <= 0;
bg_rdwr_data_valid <= 0;
bg_interrupt_ready <= 0;
bg_effective_size <= 0;
end
else
begin
bg_do_write <= arb_do_write;
bg_do_read <= arb_do_read;
bg_do_auto_precharge <= arb_do_auto_precharge;
bg_do_rmw_correct <= combined_do_rmw_correct;
bg_do_rmw_partial <= combined_do_rmw_partial;
bg_do_activate <= arb_do_activate;
bg_do_precharge <= arb_do_precharge;
bg_do_precharge_all <= arb_do_precharge_all;
bg_do_refresh <= arb_do_refresh;
bg_do_self_refresh <= arb_do_self_refresh;
bg_do_power_down <= arb_do_power_down;
bg_do_deep_pdown <= arb_do_deep_pdown;
bg_do_zq_cal <= arb_do_zq_cal;
bg_do_lmr <= arb_do_lmr;
bg_to_chip <= arb_to_chip;
bg_to_chipsel <= arb_to_chipsel;
bg_to_bank <= arb_to_bank;
bg_to_row <= arb_to_row;
bg_localid <= arb_localid;
bg_size <= arb_size;
bg_to_col <= modified_to_col;
bg_dataid <= combined_dataid;
bg_do_burst_chop <= do_burst_chop;
bg_do_burst_terminate <= do_burst_terminate;
bg_doing_write <= doing_write;
bg_doing_read <= doing_read;
bg_rdwr_data_valid <= rdwr_data_valid;
bg_interrupt_ready <= interrupt_ready;
bg_effective_size <= effective_size;
end
end
end
else
begin
always @ (*)
begin
bg_do_write = arb_do_write;
bg_do_read = arb_do_read;
bg_do_auto_precharge = arb_do_auto_precharge;
bg_do_activate = arb_do_activate;
bg_do_precharge = arb_do_precharge;
bg_do_precharge_all = arb_do_precharge_all;
bg_do_refresh = arb_do_refresh;
bg_do_self_refresh = arb_do_self_refresh;
bg_do_power_down = arb_do_power_down;
bg_do_deep_pdown = arb_do_deep_pdown;
bg_do_zq_cal = arb_do_zq_cal;
bg_do_lmr = arb_do_lmr;
bg_to_chip = arb_to_chip;
bg_to_chipsel = arb_to_chipsel;
bg_to_bank = arb_to_bank;
bg_to_row = arb_to_row;
bg_localid = arb_localid;
bg_size = arb_size;
bg_do_burst_chop = do_burst_chop;
bg_do_burst_terminate = do_burst_terminate;
bg_doing_write = doing_write;
bg_doing_read = doing_read;
bg_rdwr_data_valid = rdwr_data_valid;
bg_interrupt_ready = interrupt_ready;
bg_effective_size = effective_size;
end
always @ (*)
begin
bg_to_col = modified_to_col;
end
always @ (*)
begin
bg_do_rmw_correct = combined_do_rmw_correct;
bg_do_rmw_partial = combined_do_rmw_partial;
end
always @ (*)
begin
bg_dataid = combined_dataid;
end
end
endgenerate
always @ (*)
begin
bg_do_write_combi = arb_do_write;
bg_do_read_combi = arb_do_read;
bg_do_burst_chop_combi = do_burst_chop;
bg_do_burst_terminate_combi = do_burst_terminate;
bg_do_activate_combi = arb_do_activate;
bg_do_precharge_combi = arb_do_precharge;
bg_to_chip_combi = arb_to_chip;
bg_effective_size_combi = effective_size;
bg_interrupt_ready_combi = interrupt_ready;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size <= 0;
end
else
begin
max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size_divide_2 <= 0;
max_local_burst_size_minus_2 <= 0;
max_local_burst_size_divide_2_and_minus_2 <= 0;
end
else
begin
max_local_burst_size_divide_2 <= max_local_burst_size / 2;
max_local_burst_size_minus_2 <= max_local_burst_size - 2'd2;
max_local_burst_size_divide_2_and_minus_2 <= (max_local_burst_size / 2) - 2'd2;
end
end
always @ (*)
begin
int_col_address = 0;
if (cfg_type == `MMR_TYPE_DDR3 && do_burst_chop)
begin
if (max_local_burst_size [2])
int_col_address [0 ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
else
int_col_address = 0;
end
else if (max_local_burst_size [0])
int_col_address = 0;
else if (max_local_burst_size [1])
int_col_address [0 ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
else if (max_local_burst_size [2])
int_col_address [1 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 1 : (CFG_DWIDTH_RATIO / 2)];
else if (max_local_burst_size [3])
int_col_address [2 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 2 : (CFG_DWIDTH_RATIO / 2)];
end
always @ (*)
begin
col_address = int_col_address;
end
always @ (*)
begin
int_to_col = arb_to_col;
end
always @ (*)
begin
int_do_row_req = (|arb_do_activate) | (|arb_do_precharge);
end
always @ (*)
begin
int_do_col_req = (|arb_do_write) | (|arb_do_read);
end
always @ (*)
begin
int_do_rd_req = |arb_do_read;
int_do_wr_req = |arb_do_write;
end
always @ (*)
begin
int_do_burst_chop = arb_do_burst_chop;
end
always @ (*)
begin
int_do_rmw_correct = arb_do_rmw_correct;
int_do_rmw_partial = arb_do_rmw_partial;
end
always @ (*)
begin
int_size = arb_size;
int_dataid = arb_dataid;
end
always @ (*)
begin
size = int_size;
dataid = int_dataid;
to_col = int_to_col;
do_row_req = int_do_row_req;
do_col_req = int_do_col_req;
do_rd_req = int_do_rd_req;
do_wr_req = int_do_wr_req;
do_burst_chop = int_do_burst_chop;
do_rmw_correct = int_do_rmw_correct;
do_rmw_partial = int_do_rmw_partial;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
address_left <= 0;
end
else
begin
if (do_col_req)
begin
if (col_address > 1'b1)
address_left <= col_address - 2'd2;
else
address_left <= 0;
end
else if (address_left != 0)
address_left <= address_left - 1'b1;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
burst_left <= 0;
end
else
begin
if (do_col_req)
begin
if (col_address == 0)
begin
if (size > 1'b1)
burst_left <= size - 2'd2;
else
burst_left <= 0;
end
else if (col_address == 1'b1)
begin
burst_left <= size - 1'b1;
end
else
begin
burst_left <= size;
end
end
else if (address_left == 0 && burst_left != 0)
burst_left <= burst_left - 1'b1;
end
end
always @ (*)
begin
if (do_col_req && col_address == 0)
current_valid = 1'b1;
else
current_valid = 1'b0;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_valid <= 0;
end
else
begin
if (do_col_req && ((col_address == 0 && size > 1) || col_address == 1'b1))
delayed_valid <= 1'b1;
else if (address_left == 0 && burst_left > 0)
delayed_valid <= 1'b1;
else
delayed_valid <= 1'b0;
end
end
always @ (*)
begin
combined_valid = current_valid | delayed_valid;
end
always @ (*)
begin
rdwr_data_valid = combined_valid;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_burst_left <= 0;
end
else
begin
if (do_col_req)
begin
if (do_burst_chop)
begin
if (max_local_burst_size_divide_2 <= 2)
max_burst_left <= 0;
else
max_burst_left <= max_local_burst_size_divide_2_and_minus_2;
end
else
begin
if (max_local_burst_size <= 2)
max_burst_left <= 0;
else
max_burst_left <= max_local_burst_size_minus_2;
end
end
else if (max_burst_left != 0)
max_burst_left <= max_burst_left - 1'b1;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_doing <= 0;
end
else
begin
if (do_col_req)
begin
if (max_local_burst_size <= 1'b1)
delayed_doing <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 2'd2)
delayed_doing <= 1'b0;
else
delayed_doing <= 1'b1;
end
else if (max_burst_left > 0)
delayed_doing <= 1'b1;
else
delayed_doing <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last_is_write <= 1'b0;
last_is_read <= 1'b0;
end
else
begin
if (do_wr_req)
begin
last_is_write <= 1'b1;
last_is_read <= 1'b0;
end
else if (do_rd_req)
begin
last_is_write <= 1'b0;
last_is_read <= 1'b1;
end
end
end
always @ (*)
begin
if (do_rd_req)
doing_write = 1'b0;
else if (do_wr_req)
doing_write = ~terminate_doing;
else if (last_is_write)
doing_write = delayed_doing & ~terminate_doing;
else
doing_write = 1'b0;
end
always @ (*)
begin
if (do_wr_req)
doing_read = 1'b0;
else if (do_rd_req)
doing_read = ~terminate_doing;
else if (last_is_read)
doing_read = delayed_doing & ~terminate_doing;
else
doing_read = 1'b0;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_do_rmw_correct <= 0;
delayed_do_rmw_partial <= 0;
end
else
begin
if (do_col_req)
begin
delayed_do_rmw_correct <= do_rmw_correct;
delayed_do_rmw_partial <= do_rmw_partial;
end
end
end
always @ (*)
begin
if (do_col_req)
begin
combined_do_rmw_correct = do_rmw_correct;
combined_do_rmw_partial = do_rmw_partial;
end
else if (delayed_doing)
begin
combined_do_rmw_correct = delayed_do_rmw_correct;
combined_do_rmw_partial = delayed_do_rmw_partial;
end
else
begin
combined_do_rmw_correct = 0;
combined_do_rmw_partial = 0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_dataid <= 0;
end
else
begin
if (do_col_req)
delayed_dataid <= dataid;
end
end
always @ (*)
begin
if (do_col_req)
combined_dataid = dataid;
else if (delayed_doing)
combined_dataid = delayed_dataid;
else
combined_dataid = 0;
end
always @ (*)
begin
modified_to_col = to_col;
if (do_burst_chop && cfg_type == `MMR_TYPE_DDR3)
begin
if (max_local_burst_size [1])
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 0 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [2])
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 1 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
end
end
else
begin
if (max_local_burst_size [0])
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 0 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [1])
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 1 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [2])
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 2 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 2 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [3])
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 3 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 3 : CFG_MEM_IF_COL_WIDTH] = 0;
end
end
end
generate
begin
if (CFG_ENABLE_BURST_INTERRUPT || CFG_ENABLE_BURST_TERMINATE)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
n_prefetch <= 0;
end
else
begin
n_prefetch <= cfg_tccd / (CFG_DWIDTH_RATIO / 2);
end
end
end
end
endgenerate
generate
begin
if (CFG_ENABLE_BURST_INTERRUPT)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_allow_interrupt <= 1'b1;
end
else
begin
if (cfg_type == `MMR_TYPE_DDR3)
int_allow_interrupt <= 1'b1;
else
begin
if (n_prefetch <= 1)
begin
if (do_col_req && ((col_address == 0 && size > 1) || col_address != 0))
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0)
int_allow_interrupt <= 1'b1;
end
else if (n_prefetch == 2)
begin
if (do_col_req)
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0 && max_burst_left [0] == 0)
int_allow_interrupt <= 1'b1;
end
else if (n_prefetch == 4)
begin
if (do_col_req)
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0 && max_burst_left [1 : 0] == 0)
int_allow_interrupt <= 1'b1;
end
end
end
end
always @ (*)
begin
int_interrupt_ready = int_allow_interrupt;
end
end
else
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_interrupt_ready <= 0;
end
else
begin
if (do_col_req)
begin
if (CFG_REG_GRANT)
begin
if (max_local_burst_size <= 2'd2)
int_interrupt_ready <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 3'd4)
int_interrupt_ready <= 1'b0;
else
int_interrupt_ready <= 1'b1;
end
else
begin
if (max_local_burst_size <= 1'b1)
int_interrupt_ready <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 2'd2)
int_interrupt_ready <= 1'b0;
else
int_interrupt_ready <= 1'b1;
end
end
else if (!CFG_REG_GRANT && max_burst_left > 0)
int_interrupt_ready <= 1'b1;
else if ( CFG_REG_GRANT && max_burst_left > 1'b1)
int_interrupt_ready <= 1'b1;
else
int_interrupt_ready <= 1'b0;
end
end
end
end
endgenerate
always @ (*)
begin
interrupt_ready = ~int_interrupt_ready;
end
generate
begin
if (CFG_ENABLE_BURST_TERMINATE)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else
begin
if (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2)
begin
if (n_prefetch <= 1)
begin
if (do_col_req && col_address != 0)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (do_col_req && col_address == 0 && size == 1'b1)
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0)
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
else if (n_prefetch == 2)
begin
if (do_col_req)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && (max_burst_left [0] == 0 || int_allow_terminate == 1'b1))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
else if (n_prefetch == 4)
begin
if (do_col_req)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && (max_burst_left [1 : 0] == 0 || int_allow_terminate == 1'b1))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
end
else
begin
int_allow_terminate <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_effective_size <= 0;
end
else
begin
if (do_col_req)
int_effective_size <= 1'b1;
else if (int_effective_size != {CFG_INT_SIZE_WIDTH{1'b1}})
int_effective_size <= int_effective_size + 1'b1;
end
end
end
else
begin
always @ (*)
begin
int_do_burst_terminate = zero;
end
always @ (*)
begin
int_effective_size = {CFG_INT_SIZE_WIDTH{zero}};
end
end
end
endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_terminate <= 1'b0;
end
else
begin
if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && ((|do_burst_terminate) == 1'b1 || doing_burst_terminate == 1'b1))
doing_burst_terminate <= 1'b1;
else
doing_burst_terminate <= 1'b0;
end
end
always @ (*)
begin
terminate_doing = (|do_burst_terminate) | doing_burst_terminate;
end
always @ (*)
begin
if (CFG_DWIDTH_RATIO == 2)
int_do_req = do_col_req | do_row_req;
else
int_do_req = do_col_req;
end
generate
begin
if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
always @ (*)
begin
do_burst_terminate = 0;
if (int_do_req)
do_burst_terminate [AFI_INTF_HIGH_PHASE] = 0;
else
do_burst_terminate [AFI_INTF_HIGH_PHASE] = int_do_burst_terminate;
end
end
else if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
always @ (*)
begin
do_burst_terminate = 0;
if (int_do_req)
do_burst_terminate [AFI_INTF_LOW_PHASE] = 0;
else
do_burst_terminate [AFI_INTF_LOW_PHASE] = int_do_burst_terminate;
end
end
end
endgenerate
always @ (*)
begin
effective_size = int_effective_size;
end
endmodule | 25 |
4,919 | data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_tracking.v | 1,122,957 | alt_mem_ddrx_burst_tracking.v | v | 126 | 83 | [] | [] | [] | [(4, 125)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_tracking.v:95: Operator SUB expects 32 or 7 bits on the RHS, but RHS\'s VARREF \'burst_counsumed_burstcount\' generates 4 bits.\n : ... In instance alt_mem_ddrx_burst_tracking\n burst_counter_next = burst_counter + 1 - burst_counsumed_burstcount;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_tracking.v:103: Operator SUB expects 7 bits on the RHS, but RHS\'s VARREF \'burst_counsumed_burstcount\' generates 4 bits.\n : ... In instance alt_mem_ddrx_burst_tracking\n burst_counter_next = burst_counter - burst_counsumed_burstcount;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 3,326 | module | module alt_mem_ddrx_burst_tracking
# (
parameter
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 4
)
(
ctl_clk,
ctl_reset_n,
burst_ready,
burst_valid,
burst_pending_burstcount,
burst_next_pending_burstcount,
burst_consumed_valid,
burst_counsumed_burstcount
);
input ctl_clk;
input ctl_reset_n;
input burst_ready;
input burst_valid;
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
input burst_consumed_valid;
input [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
wire ctl_clk;
wire ctl_reset_n;
wire burst_ready;
wire burst_valid;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
wire burst_consumed_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter_next;
wire burst_accepted;
assign burst_pending_burstcount = burst_counter;
assign burst_next_pending_burstcount = burst_counter_next;
assign burst_accepted = burst_ready & burst_valid;
always @ (*)
begin
if (burst_accepted & burst_consumed_valid)
begin
burst_counter_next = burst_counter + 1 - burst_counsumed_burstcount;
end
else if (burst_accepted)
begin
burst_counter_next = burst_counter + 1;
end
else if (burst_consumed_valid)
begin
burst_counter_next = burst_counter - burst_counsumed_burstcount;
end
else
begin
burst_counter_next = burst_counter;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
burst_counter <= 0;
end
else
begin
burst_counter <= burst_counter_next;
end
end
endmodule | module alt_mem_ddrx_burst_tracking
# (
parameter
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 4
)
(
ctl_clk,
ctl_reset_n,
burst_ready,
burst_valid,
burst_pending_burstcount,
burst_next_pending_burstcount,
burst_consumed_valid,
burst_counsumed_burstcount
); |
input ctl_clk;
input ctl_reset_n;
input burst_ready;
input burst_valid;
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
input burst_consumed_valid;
input [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
wire ctl_clk;
wire ctl_reset_n;
wire burst_ready;
wire burst_valid;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
wire burst_consumed_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter_next;
wire burst_accepted;
assign burst_pending_burstcount = burst_counter;
assign burst_next_pending_burstcount = burst_counter_next;
assign burst_accepted = burst_ready & burst_valid;
always @ (*)
begin
if (burst_accepted & burst_consumed_valid)
begin
burst_counter_next = burst_counter + 1 - burst_counsumed_burstcount;
end
else if (burst_accepted)
begin
burst_counter_next = burst_counter + 1;
end
else if (burst_consumed_valid)
begin
burst_counter_next = burst_counter - burst_counsumed_burstcount;
end
else
begin
burst_counter_next = burst_counter;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
burst_counter <= 0;
end
else
begin
burst_counter <= burst_counter_next;
end
end
endmodule | 25 |
4,920 | data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_dataid_manager.v | 1,122,957 | alt_mem_ddrx_dataid_manager.v | v | 849 | 206 | [] | [] | [] | null | None: at end of input | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_dataid_manager.v:292: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 256 bits.\n : ... In instance alt_mem_ddrx_dataid_manager\n assign burstcount_list_write_data = {{(CFG_DATAID_ARRAY_DEPTH - CFG_INT_SIZE_WIDTH){1\'b0}}, update_cmd_if_burstcount};\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_dataid_manager.v:297: Cannot find file containing module: \'alt_mem_ddrx_list\'\n alt_mem_ddrx_list\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy,data/full_repos/permissive/1122957/alt_mem_ddrx_list\n data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy,data/full_repos/permissive/1122957/alt_mem_ddrx_list.v\n data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy,data/full_repos/permissive/1122957/alt_mem_ddrx_list.sv\n alt_mem_ddrx_list\n alt_mem_ddrx_list.v\n alt_mem_ddrx_list.sv\n obj_dir/alt_mem_ddrx_list\n obj_dir/alt_mem_ddrx_list.v\n obj_dir/alt_mem_ddrx_list.sv\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_dataid_manager.v:319: Operator GTE expects 7 bits on the RHS, but RHS\'s VARREF \'burstcount_list_read_data\' generates 1 bits.\n : ... In instance alt_mem_ddrx_dataid_manager\n if (burstcount_list_read_data_valid && (update_data_if_burstcount >= burstcount_list_read_data))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_dataid_manager.v:328: Operator EQ expects 7 bits on the RHS, but RHS\'s VARREF \'burstcount_list_read_data\' generates 1 bits.\n : ... In instance alt_mem_ddrx_dataid_manager\n if (burstcount_list_read_data_valid && (update_data_if_burstcount == burstcount_list_read_data))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_dataid_manager.v:569: Operator ADD expects 6 bits on the RHS, but RHS\'s VARREF \'update_cmd_if_burstcount\' generates 1 bits.\n : ... In instance alt_mem_ddrx_dataid_manager\n assign update_cmd_if_nextaddress = update_cmd_if_address + update_cmd_if_burstcount;\n ^\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_dataid_manager.v:620: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'update_cmd_if_burstcount\' generates 1 bits.\n : ... In instance alt_mem_ddrx_dataid_manager\n update_cmd_if_next_unnotified_burstcount = update_cmd_if_unnotified_burstcount + update_cmd_if_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];\n ^\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_dataid_manager.v:620: Operator SUB expects 7 bits on the RHS, but RHS\'s ARRAYSEL generates 1 bits.\n : ... In instance alt_mem_ddrx_dataid_manager\n update_cmd_if_next_unnotified_burstcount = update_cmd_if_unnotified_burstcount + update_cmd_if_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];\n ^\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_dataid_manager.v:624: Operator SUB expects 7 bits on the RHS, but RHS\'s ARRAYSEL generates 1 bits.\n : ... In instance alt_mem_ddrx_dataid_manager\n update_cmd_if_next_unnotified_burstcount = update_cmd_if_unnotified_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];\n ^\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_dataid_manager.v:658: Operator SUB expects 32 or 6 bits on the RHS, but RHS\'s VARREF \'update_cmd_if_burstcount\' generates 1 bits.\n : ... In instance alt_mem_ddrx_dataid_manager\n buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter- update_cmd_if_burstcount + 1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_dataid_manager.v:663: Operator SUB expects 7 bits on the RHS, but RHS\'s VARREF \'update_cmd_if_burstcount\' generates 1 bits.\n : ... In instance alt_mem_ddrx_dataid_manager\n {err_buffer_cmd_unallocated_counter_overflow, buffer_cmd_unallocated_counter} <= buffer_cmd_unallocated_counter - update_cmd_if_burstcount;\n ^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n' | 3,331 | module | module alt_mem_ddrx_dataid_manager
# (
parameter
CFG_DATA_ID_WIDTH = 8,
CFG_DRAM_WLAT_GROUP = 1,
CFG_LOCAL_WLAT_GROUP = 1,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 1,
CFG_TBP_NUM = 4,
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_DWIDTH_RATIO = 2
)
(
ctl_clk,
ctl_reset_n,
cfg_burst_length,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
update_cmd_if_ready,
update_cmd_if_valid,
update_cmd_if_data_id,
update_cmd_if_burstcount,
update_cmd_if_tbp_id,
update_data_if_valid,
update_data_if_data_id,
update_data_if_data_id_vector,
update_data_if_burstcount,
update_data_if_next_burstcount,
notify_data_if_valid,
notify_data_if_burstcount,
notify_tbp_data_ready,
notify_tbp_data_partial_be,
write_data_if_ready,
write_data_if_valid,
write_data_if_accepted,
write_data_if_address,
write_data_if_partial_dm,
read_data_if_valid,
read_data_if_data_id,
read_data_if_data_id_vector,
read_data_if_valid_first,
read_data_if_data_id_first,
read_data_if_data_id_vector_first,
read_data_if_valid_first_vector,
read_data_if_valid_last,
read_data_if_data_id_last,
read_data_if_data_id_vector_last,
read_data_if_address,
read_data_if_datavalid,
read_data_if_done
);
localparam integer CFG_DATAID_ARRAY_DEPTH = (2**CFG_DATA_ID_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input cfg_enable_ecc;
input cfg_enable_auto_corr;
input cfg_enable_no_dm;
output update_cmd_if_ready;
input update_cmd_if_valid;
input [CFG_DATA_ID_WIDTH-1:0] update_cmd_if_data_id;
input [CFG_INT_SIZE_WIDTH-1:0] update_cmd_if_burstcount;
input [CFG_TBP_NUM-1:0] update_cmd_if_tbp_id;
input update_data_if_valid;
input [CFG_DATA_ID_WIDTH-1:0] update_data_if_data_id;
input [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_data_id_vector;
input [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_burstcount;
input [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_next_burstcount;
output notify_data_if_valid;
output [CFG_INT_SIZE_WIDTH-1:0] notify_data_if_burstcount;
output [CFG_TBP_NUM-1:0] notify_tbp_data_ready;
output notify_tbp_data_partial_be;
output write_data_if_ready;
input write_data_if_valid;
output write_data_if_accepted;
output [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_address;
input write_data_if_partial_dm;
input [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid;
input [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id;
input [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector;
input read_data_if_valid_first;
input [CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id_first;
input [CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector_first;
input [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid_first_vector;
input read_data_if_valid_last;
input [CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id_last;
input [CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector_last;
output [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] read_data_if_address;
output [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_datavalid;
output read_data_if_done;
wire ctl_clk;
wire ctl_reset_n;
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire cfg_enable_ecc;
wire cfg_enable_auto_corr;
wire cfg_enable_no_dm;
reg update_cmd_if_ready;
wire update_cmd_if_valid;
wire [CFG_DATA_ID_WIDTH-1:0] update_cmd_if_data_id;
wire [CFG_INT_SIZE_WIDTH-1:0] update_cmd_if_burstcount;
wire [CFG_TBP_NUM-1:0] update_cmd_if_tbp_id;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_address;
wire update_data_if_valid;
wire [CFG_DATA_ID_WIDTH-1:0] update_data_if_data_id;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_data_id_vector;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_next_burstcount;
wire notify_data_if_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] notify_data_if_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_notify_data_if_valid;
reg [CFG_INT_SIZE_WIDTH-1:0] mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_valid;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_data_ready;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] dataid_array_address [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_INT_SIZE_WIDTH-1:0] dataid_array_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_TBP_NUM-1:0] dataid_array_tbp_id [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_dataid_array_done;
wire [CFG_TBP_NUM-1:0] notify_tbp_data_ready;
reg notify_tbp_data_partial_be;
reg [CFG_TBP_NUM-1:0] mux_tbp_data_ready [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_TBP_NUM-1:0] tbp_data_ready_r;
reg write_data_if_ready;
wire write_data_if_valid;
wire write_data_if_accepted;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_address;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_nextaddress;
wire write_data_if_partial_dm;
wire [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector;
reg [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] read_data_if_address;
reg [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_datavalid;
wire [CFG_INT_SIZE_WIDTH-1:0] read_data_if_burstcount;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_INT_SIZE_WIDTH-1:0] mux_read_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
wire read_data_if_done;
reg write_data_if_address_blocked;
reg cfg_enable_partial_be_notification;
reg [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_max_cmd_burstcount;
reg [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_max_cmd_burstcount_2x;
wire update_cmd_if_accepted;
wire update_cmd_if_address_blocked;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_nextaddress;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_nextmaxaddress;
reg update_cmd_if_nextmaxaddress_wrapped;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_cmd_if_unnotified_burstcount;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_cmd_if_next_unnotified_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_write_data_if_address_blocked;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_update_cmd_if_address_blocked;
reg err_dataid_array_overwritten;
reg err_dataid_array_invalidread;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_cmd_unallocated_counter;
reg buffer_valid_counter_full;
reg err_buffer_valid_counter_overflow;
reg err_buffer_cmd_unallocated_counter_overflow;
reg partial_be_detected;
reg partial_be_when_no_cmd_tracked;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_burstcount_greatereq;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_burstcount_same;
wire update_data_bc_gt_update_cmd_unnotified_bc;
wire burstcount_list_read;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] burstcount_list_read_data;
wire burstcount_list_read_data_valid;
wire burstcount_list_write;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] burstcount_list_write_data;
reg update_data_if_burstcount_greatereq_burstcount_list;
reg update_data_if_burstcount_same_burstcount_list;
integer k;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_enable_partial_be_notification <= 1'b0;
end
else
begin
cfg_enable_partial_be_notification <= cfg_enable_ecc | cfg_enable_auto_corr | cfg_enable_no_dm;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_max_cmd_burstcount <= 0;
cfg_max_cmd_burstcount_2x <= 0;
end
else
begin
cfg_max_cmd_burstcount <= cfg_burst_length / CFG_DWIDTH_RATIO;
cfg_max_cmd_burstcount_2x <= 2 * cfg_max_cmd_burstcount;
end
end
assign burstcount_list_write = update_cmd_if_accepted;
assign burstcount_list_write_data = {{(CFG_DATAID_ARRAY_DEPTH - CFG_INT_SIZE_WIDTH){1'b0}}, update_cmd_if_burstcount};
assign burstcount_list_read = notify_data_if_valid;
alt_mem_ddrx_list
# (
.CTL_LIST_WIDTH (CFG_INT_SIZE_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
burstcount_list
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_valid (burstcount_list_read_data_valid),
.list_get_entry_ready (burstcount_list_read),
.list_get_entry_id (burstcount_list_read_data),
.list_get_entry_id_vector (),
.list_put_entry_valid (burstcount_list_write),
.list_put_entry_ready (),
.list_put_entry_id (burstcount_list_write_data)
);
always @ (*)
begin
if (burstcount_list_read_data_valid && (update_data_if_burstcount >= burstcount_list_read_data))
begin
update_data_if_burstcount_greatereq_burstcount_list = 1'b1;
end
else
begin
update_data_if_burstcount_greatereq_burstcount_list = 1'b0;
end
if (burstcount_list_read_data_valid && (update_data_if_burstcount == burstcount_list_read_data))
begin
update_data_if_burstcount_same_burstcount_list = 1'b1;
end
else
begin
update_data_if_burstcount_same_burstcount_list = 1'b0;
end
end
genvar i;
generate
for (i = 0; i < CFG_DATAID_ARRAY_DEPTH; i = i + 1)
begin : gen_dataid_array_management
assign update_data_if_burstcount_greatereq [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_greatereq_burstcount_list;
assign update_data_if_burstcount_same [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_same_burstcount_list;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
dataid_array_address [i] <= 0;
dataid_array_burstcount [i] <= 0;
dataid_array_tbp_id [i] <= 0;
dataid_array_data_ready [i] <= 1'b0;
dataid_array_valid [i] <= 1'b0;
mux_dataid_array_done [i] <= 1'b0;
err_dataid_array_overwritten <= 0;
err_dataid_array_invalidread <= 0;
end
else
begin
if (update_cmd_if_accepted && (update_cmd_if_data_id == i))
begin
dataid_array_address [i] <= update_cmd_if_address;
dataid_array_burstcount [i] <= update_cmd_if_burstcount;
dataid_array_tbp_id [i] <= update_cmd_if_tbp_id;
dataid_array_valid [i] <= 1'b1;
mux_dataid_array_done [i] <= 1'b0;
if (dataid_array_valid[i])
begin
err_dataid_array_overwritten <= 1;
end
end
if (update_data_if_burstcount_greatereq[i])
begin
dataid_array_data_ready [i] <= 1'b1;
end
if (read_data_if_valid_first && (read_data_if_data_id_vector_first[i]))
begin
dataid_array_address [i] <= dataid_array_address [i] + 1;
dataid_array_burstcount [i] <= dataid_array_burstcount [i] - 1;
dataid_array_data_ready [i] <= 0;
if (dataid_array_burstcount [i] == 1'b1)
begin
dataid_array_valid [i] <= 1'b0;
mux_dataid_array_done [i] <= 1'b1;
end
else
begin
mux_dataid_array_done [i] <= 1'b0;
end
if (~dataid_array_valid[i])
begin
err_dataid_array_invalidread <= 1;
end
end
else
begin
mux_dataid_array_done [i] <= 1'b0;
end
end
end
always @ (*)
begin
if (update_data_if_burstcount_greatereq[i])
begin
mux_notify_data_if_valid [i] = 1'b1;
end
else
begin
mux_notify_data_if_valid [i] = 1'b0;
end
end
end
endgenerate
assign notify_data_if_valid = update_data_if_burstcount_greatereq_burstcount_list;
assign notify_data_if_burstcount= burstcount_list_read_data;
assign read_data_if_burstcount = mux_read_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
assign read_data_if_done = |mux_dataid_array_done;
assign update_cmd_if_address_blocked= |mux_update_cmd_if_address_blocked;
generate
if (CFG_DRAM_WLAT_GROUP == 1)
begin
always @ (*)
begin
read_data_if_address = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
end
end
else
begin
wire rdata_address_list_read;
wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_read_data;
wire rdata_address_list_read_data_valid;
wire rdata_address_list_write;
wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_write_data;
assign rdata_address_list_read = read_data_if_valid_last;
assign rdata_address_list_write = read_data_if_valid_first;
assign rdata_address_list_write_data = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
alt_mem_ddrx_list
# (
.CTL_LIST_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CTL_LIST_DEPTH (CFG_DRAM_WLAT_GROUP),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
rdata_address_list
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_valid (rdata_address_list_read_data_valid),
.list_get_entry_ready (rdata_address_list_read),
.list_get_entry_id (rdata_address_list_read_data),
.list_get_entry_id_vector (),
.list_put_entry_valid (rdata_address_list_write),
.list_put_entry_ready (),
.list_put_entry_id (rdata_address_list_write_data)
);
for (i = 0;i < CFG_LOCAL_WLAT_GROUP;i = i + 1)
begin : rdata_if_address_per_dqs_group
always @ (*)
begin
if (read_data_if_valid_first_vector [i])
begin
read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_write_data;
end
else
begin
read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_read_data;
end
end
end
end
endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
write_data_if_address_blocked <= 0;
end
else
begin
write_data_if_address_blocked <= |mux_write_data_if_address_blocked;
end
end
always @ (*)
begin
mux_tbp_data_ready [0] = (mux_notify_data_if_valid [0]) ? dataid_array_tbp_id [0] : {CFG_TBP_NUM{1'b0}};
mux_notify_data_if_burstcount [0] = (mux_notify_data_if_valid [0]) ? dataid_array_burstcount [0] : 0;
mux_read_data_if_address [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_address [0] : 0;
mux_read_data_if_burstcount [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_burstcount [0] : 0;
mux_write_data_if_address_blocked [0] = (dataid_array_data_ready[0] & ( (dataid_array_address[0] == write_data_if_nextaddress) | (dataid_array_address[0] == write_data_if_address) ) );
if (update_cmd_if_nextmaxaddress_wrapped)
begin
mux_update_cmd_if_address_blocked [0] = (dataid_array_valid[0] & ~( (dataid_array_address[0] < update_cmd_if_address) & (dataid_array_address[0] > update_cmd_if_nextmaxaddress) ));
end
else
begin
mux_update_cmd_if_address_blocked [0] = (dataid_array_valid[0] & ( (dataid_array_address[0] >= update_cmd_if_address) & (dataid_array_address[0] <= update_cmd_if_nextmaxaddress) ));
end
end
genvar j;
generate
for (j = 1; j < CFG_DATAID_ARRAY_DEPTH; j = j + 1)
begin : gen_mux_dataid_array_output
always @ (*)
begin
mux_tbp_data_ready [j] = mux_tbp_data_ready [j-1] | ( (mux_notify_data_if_valid [j]) ? dataid_array_tbp_id [j] : {CFG_TBP_NUM{1'b0}} );
mux_notify_data_if_burstcount [j] = mux_notify_data_if_burstcount [j-1] | ( (mux_notify_data_if_valid [j]) ? dataid_array_burstcount [j] : 0 );
mux_read_data_if_address [j] = mux_read_data_if_address [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_address [j] : 0 );
mux_read_data_if_burstcount [j] = mux_read_data_if_burstcount [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_burstcount [j] : 0 );
mux_write_data_if_address_blocked [j] = (dataid_array_data_ready[j] & ( (dataid_array_address[j] == write_data_if_nextaddress) | (dataid_array_address[j] == write_data_if_address) ) );
if (update_cmd_if_nextmaxaddress_wrapped)
begin
mux_update_cmd_if_address_blocked [j] = (dataid_array_valid[j] & ~( (dataid_array_address[j] < update_cmd_if_address) & (dataid_array_address[j] > update_cmd_if_nextmaxaddress) ));
end
else
begin
mux_update_cmd_if_address_blocked [j] = (dataid_array_valid[j] & ( (dataid_array_address[j] >= update_cmd_if_address) & (dataid_array_address[j] <= update_cmd_if_nextmaxaddress) ));
end
end
end
endgenerate
assign notify_tbp_data_ready = mux_tbp_data_ready [CFG_DATAID_ARRAY_DEPTH-1];
assign update_cmd_if_accepted = update_cmd_if_ready & update_cmd_if_valid;
assign update_cmd_if_nextaddress = update_cmd_if_address + update_cmd_if_burstcount;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
update_cmd_if_address <= 0;
update_cmd_if_nextmaxaddress <= 0;
update_cmd_if_nextmaxaddress_wrapped <= 1'b0;
write_data_if_address <= 0;
write_data_if_nextaddress <= 0;
end
else
begin
if (update_cmd_if_accepted)
begin
update_cmd_if_address <= update_cmd_if_nextaddress;
update_cmd_if_nextmaxaddress <= update_cmd_if_nextaddress + cfg_max_cmd_burstcount_2x;
if (update_cmd_if_nextaddress > (update_cmd_if_nextaddress + cfg_max_cmd_burstcount_2x))
begin
update_cmd_if_nextmaxaddress_wrapped <= 1'b1;
end
else
begin
update_cmd_if_nextmaxaddress_wrapped <= 1'b0;
end
end
if (write_data_if_accepted)
begin
write_data_if_address <= write_data_if_address + 1;
write_data_if_nextaddress <= write_data_if_address + 2;
end
else
begin
write_data_if_nextaddress <= write_data_if_address + 1;
end
end
end
always @ (*)
begin
if (update_cmd_if_accepted)
begin
update_cmd_if_next_unnotified_burstcount = update_cmd_if_unnotified_burstcount + update_cmd_if_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
end
else
begin
update_cmd_if_next_unnotified_burstcount = update_cmd_if_unnotified_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
update_cmd_if_unnotified_burstcount <= 0;
end
else
begin
update_cmd_if_unnotified_burstcount <= update_cmd_if_next_unnotified_burstcount;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_cmd_unallocated_counter <= {CFG_BUFFER_ADDR_WIDTH{1'b1}};
err_buffer_cmd_unallocated_counter_overflow <= 0;
end
else
begin
if (update_cmd_if_accepted & read_data_if_valid_last)
begin
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter- update_cmd_if_burstcount + 1;
end
else if (update_cmd_if_accepted)
begin
{err_buffer_cmd_unallocated_counter_overflow, buffer_cmd_unallocated_counter} <= buffer_cmd_unallocated_counter - update_cmd_if_burstcount;
end
else if (read_data_if_valid_last)
begin
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter + 1;
end
else
begin
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
update_cmd_if_ready <= 0;
end
else
begin
update_cmd_if_ready <= ~update_cmd_if_address_blocked;
end
end
assign write_data_if_accepted = write_data_if_ready & write_data_if_valid;
always @ (*)
begin
if (write_data_if_address_blocked)
begin
write_data_if_ready = 1'b0;
end
else
begin
write_data_if_ready = ~buffer_valid_counter_full & ~partial_be_when_no_cmd_tracked;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
read_data_if_datavalid <= 0;
end
else
begin
read_data_if_datavalid <= read_data_if_valid;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
buffer_valid_counter_full <= 1'b0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (write_data_if_accepted & read_data_if_valid_last)
begin
buffer_valid_counter <= buffer_valid_counter;
buffer_valid_counter_full <= buffer_valid_counter_full;
end
else if (write_data_if_accepted)
begin
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
if (buffer_valid_counter == {{(CFG_BUFFER_ADDR_WIDTH - 1){1'b1}}, 1'b0})
begin
buffer_valid_counter_full <= 1'b1;
end
else
begin
buffer_valid_counter_full <= 1'b0;
end
end
else if (read_data_if_valid_last)
begin
buffer_valid_counter <= buffer_valid_counter - 1;
buffer_valid_counter_full <= 1'b0;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
buffer_valid_counter_full <= buffer_valid_counter_full;
end
end
end
always @ (*)
begin
if (partial_be_when_no_cmd_tracked)
begin
notify_tbp_data_partial_be = update_data_if_valid & (|update_data_if_burstcount_same);
end
else
begin
notify_tbp_data_partial_be = partial_be_detected;
end
end
assign update_data_bc_gt_update_cmd_unnotified_bc = ~update_data_if_valid | (update_data_if_burstcount >= update_cmd_if_unnotified_burstcount);
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= 1'b0;
end
else
begin
if (cfg_enable_partial_be_notification)
begin
if (partial_be_when_no_cmd_tracked)
begin
if (update_data_if_valid & ~notify_data_if_valid)
begin
partial_be_when_no_cmd_tracked <= 1'b0;
end
else if (update_data_if_valid & notify_data_if_valid)
begin
if (|update_data_if_burstcount_same)
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= write_data_if_accepted & write_data_if_partial_dm;
end
else
begin
end
end
end
else if (partial_be_detected & ~notify_data_if_valid)
begin
partial_be_detected <= partial_be_detected;
end
else
begin
partial_be_when_no_cmd_tracked <= write_data_if_accepted & write_data_if_partial_dm & update_data_bc_gt_update_cmd_unnotified_bc;
partial_be_detected <= write_data_if_accepted & write_data_if_partial_dm;
end
end
else
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= 1'b0;
end
end
end
endmodule | module alt_mem_ddrx_dataid_manager
# (
parameter
CFG_DATA_ID_WIDTH = 8,
CFG_DRAM_WLAT_GROUP = 1,
CFG_LOCAL_WLAT_GROUP = 1,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 1,
CFG_TBP_NUM = 4,
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_DWIDTH_RATIO = 2
)
(
ctl_clk,
ctl_reset_n,
cfg_burst_length,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
update_cmd_if_ready,
update_cmd_if_valid,
update_cmd_if_data_id,
update_cmd_if_burstcount,
update_cmd_if_tbp_id,
update_data_if_valid,
update_data_if_data_id,
update_data_if_data_id_vector,
update_data_if_burstcount,
update_data_if_next_burstcount,
notify_data_if_valid,
notify_data_if_burstcount,
notify_tbp_data_ready,
notify_tbp_data_partial_be,
write_data_if_ready,
write_data_if_valid,
write_data_if_accepted,
write_data_if_address,
write_data_if_partial_dm,
read_data_if_valid,
read_data_if_data_id,
read_data_if_data_id_vector,
read_data_if_valid_first,
read_data_if_data_id_first,
read_data_if_data_id_vector_first,
read_data_if_valid_first_vector,
read_data_if_valid_last,
read_data_if_data_id_last,
read_data_if_data_id_vector_last,
read_data_if_address,
read_data_if_datavalid,
read_data_if_done
); |
localparam integer CFG_DATAID_ARRAY_DEPTH = (2**CFG_DATA_ID_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input cfg_enable_ecc;
input cfg_enable_auto_corr;
input cfg_enable_no_dm;
output update_cmd_if_ready;
input update_cmd_if_valid;
input [CFG_DATA_ID_WIDTH-1:0] update_cmd_if_data_id;
input [CFG_INT_SIZE_WIDTH-1:0] update_cmd_if_burstcount;
input [CFG_TBP_NUM-1:0] update_cmd_if_tbp_id;
input update_data_if_valid;
input [CFG_DATA_ID_WIDTH-1:0] update_data_if_data_id;
input [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_data_id_vector;
input [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_burstcount;
input [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_next_burstcount;
output notify_data_if_valid;
output [CFG_INT_SIZE_WIDTH-1:0] notify_data_if_burstcount;
output [CFG_TBP_NUM-1:0] notify_tbp_data_ready;
output notify_tbp_data_partial_be;
output write_data_if_ready;
input write_data_if_valid;
output write_data_if_accepted;
output [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_address;
input write_data_if_partial_dm;
input [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid;
input [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id;
input [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector;
input read_data_if_valid_first;
input [CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id_first;
input [CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector_first;
input [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid_first_vector;
input read_data_if_valid_last;
input [CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id_last;
input [CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector_last;
output [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] read_data_if_address;
output [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_datavalid;
output read_data_if_done;
wire ctl_clk;
wire ctl_reset_n;
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire cfg_enable_ecc;
wire cfg_enable_auto_corr;
wire cfg_enable_no_dm;
reg update_cmd_if_ready;
wire update_cmd_if_valid;
wire [CFG_DATA_ID_WIDTH-1:0] update_cmd_if_data_id;
wire [CFG_INT_SIZE_WIDTH-1:0] update_cmd_if_burstcount;
wire [CFG_TBP_NUM-1:0] update_cmd_if_tbp_id;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_address;
wire update_data_if_valid;
wire [CFG_DATA_ID_WIDTH-1:0] update_data_if_data_id;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_data_id_vector;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_next_burstcount;
wire notify_data_if_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] notify_data_if_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_notify_data_if_valid;
reg [CFG_INT_SIZE_WIDTH-1:0] mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_valid;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_data_ready;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] dataid_array_address [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_INT_SIZE_WIDTH-1:0] dataid_array_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_TBP_NUM-1:0] dataid_array_tbp_id [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_dataid_array_done;
wire [CFG_TBP_NUM-1:0] notify_tbp_data_ready;
reg notify_tbp_data_partial_be;
reg [CFG_TBP_NUM-1:0] mux_tbp_data_ready [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_TBP_NUM-1:0] tbp_data_ready_r;
reg write_data_if_ready;
wire write_data_if_valid;
wire write_data_if_accepted;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_address;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_nextaddress;
wire write_data_if_partial_dm;
wire [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector;
reg [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] read_data_if_address;
reg [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_datavalid;
wire [CFG_INT_SIZE_WIDTH-1:0] read_data_if_burstcount;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_INT_SIZE_WIDTH-1:0] mux_read_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
wire read_data_if_done;
reg write_data_if_address_blocked;
reg cfg_enable_partial_be_notification;
reg [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_max_cmd_burstcount;
reg [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_max_cmd_burstcount_2x;
wire update_cmd_if_accepted;
wire update_cmd_if_address_blocked;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_nextaddress;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_nextmaxaddress;
reg update_cmd_if_nextmaxaddress_wrapped;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_cmd_if_unnotified_burstcount;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_cmd_if_next_unnotified_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_write_data_if_address_blocked;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_update_cmd_if_address_blocked;
reg err_dataid_array_overwritten;
reg err_dataid_array_invalidread;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_cmd_unallocated_counter;
reg buffer_valid_counter_full;
reg err_buffer_valid_counter_overflow;
reg err_buffer_cmd_unallocated_counter_overflow;
reg partial_be_detected;
reg partial_be_when_no_cmd_tracked;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_burstcount_greatereq;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_burstcount_same;
wire update_data_bc_gt_update_cmd_unnotified_bc;
wire burstcount_list_read;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] burstcount_list_read_data;
wire burstcount_list_read_data_valid;
wire burstcount_list_write;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] burstcount_list_write_data;
reg update_data_if_burstcount_greatereq_burstcount_list;
reg update_data_if_burstcount_same_burstcount_list;
integer k;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_enable_partial_be_notification <= 1'b0;
end
else
begin
cfg_enable_partial_be_notification <= cfg_enable_ecc | cfg_enable_auto_corr | cfg_enable_no_dm;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_max_cmd_burstcount <= 0;
cfg_max_cmd_burstcount_2x <= 0;
end
else
begin
cfg_max_cmd_burstcount <= cfg_burst_length / CFG_DWIDTH_RATIO;
cfg_max_cmd_burstcount_2x <= 2 * cfg_max_cmd_burstcount;
end
end
assign burstcount_list_write = update_cmd_if_accepted;
assign burstcount_list_write_data = {{(CFG_DATAID_ARRAY_DEPTH - CFG_INT_SIZE_WIDTH){1'b0}}, update_cmd_if_burstcount};
assign burstcount_list_read = notify_data_if_valid;
alt_mem_ddrx_list
# (
.CTL_LIST_WIDTH (CFG_INT_SIZE_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
burstcount_list
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_valid (burstcount_list_read_data_valid),
.list_get_entry_ready (burstcount_list_read),
.list_get_entry_id (burstcount_list_read_data),
.list_get_entry_id_vector (),
.list_put_entry_valid (burstcount_list_write),
.list_put_entry_ready (),
.list_put_entry_id (burstcount_list_write_data)
);
always @ (*)
begin
if (burstcount_list_read_data_valid && (update_data_if_burstcount >= burstcount_list_read_data))
begin
update_data_if_burstcount_greatereq_burstcount_list = 1'b1;
end
else
begin
update_data_if_burstcount_greatereq_burstcount_list = 1'b0;
end
if (burstcount_list_read_data_valid && (update_data_if_burstcount == burstcount_list_read_data))
begin
update_data_if_burstcount_same_burstcount_list = 1'b1;
end
else
begin
update_data_if_burstcount_same_burstcount_list = 1'b0;
end
end
genvar i;
generate
for (i = 0; i < CFG_DATAID_ARRAY_DEPTH; i = i + 1)
begin : gen_dataid_array_management
assign update_data_if_burstcount_greatereq [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_greatereq_burstcount_list;
assign update_data_if_burstcount_same [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_same_burstcount_list;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
dataid_array_address [i] <= 0;
dataid_array_burstcount [i] <= 0;
dataid_array_tbp_id [i] <= 0;
dataid_array_data_ready [i] <= 1'b0;
dataid_array_valid [i] <= 1'b0;
mux_dataid_array_done [i] <= 1'b0;
err_dataid_array_overwritten <= 0;
err_dataid_array_invalidread <= 0;
end
else
begin
if (update_cmd_if_accepted && (update_cmd_if_data_id == i))
begin
dataid_array_address [i] <= update_cmd_if_address;
dataid_array_burstcount [i] <= update_cmd_if_burstcount;
dataid_array_tbp_id [i] <= update_cmd_if_tbp_id;
dataid_array_valid [i] <= 1'b1;
mux_dataid_array_done [i] <= 1'b0;
if (dataid_array_valid[i])
begin
err_dataid_array_overwritten <= 1;
end
end
if (update_data_if_burstcount_greatereq[i])
begin
dataid_array_data_ready [i] <= 1'b1;
end
if (read_data_if_valid_first && (read_data_if_data_id_vector_first[i]))
begin
dataid_array_address [i] <= dataid_array_address [i] + 1;
dataid_array_burstcount [i] <= dataid_array_burstcount [i] - 1;
dataid_array_data_ready [i] <= 0;
if (dataid_array_burstcount [i] == 1'b1)
begin
dataid_array_valid [i] <= 1'b0;
mux_dataid_array_done [i] <= 1'b1;
end
else
begin
mux_dataid_array_done [i] <= 1'b0;
end
if (~dataid_array_valid[i])
begin
err_dataid_array_invalidread <= 1;
end
end
else
begin
mux_dataid_array_done [i] <= 1'b0;
end
end
end
always @ (*)
begin
if (update_data_if_burstcount_greatereq[i])
begin
mux_notify_data_if_valid [i] = 1'b1;
end
else
begin
mux_notify_data_if_valid [i] = 1'b0;
end
end
end
endgenerate
assign notify_data_if_valid = update_data_if_burstcount_greatereq_burstcount_list;
assign notify_data_if_burstcount= burstcount_list_read_data;
assign read_data_if_burstcount = mux_read_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
assign read_data_if_done = |mux_dataid_array_done;
assign update_cmd_if_address_blocked= |mux_update_cmd_if_address_blocked;
generate
if (CFG_DRAM_WLAT_GROUP == 1)
begin
always @ (*)
begin
read_data_if_address = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
end
end
else
begin
wire rdata_address_list_read;
wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_read_data;
wire rdata_address_list_read_data_valid;
wire rdata_address_list_write;
wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_write_data;
assign rdata_address_list_read = read_data_if_valid_last;
assign rdata_address_list_write = read_data_if_valid_first;
assign rdata_address_list_write_data = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
alt_mem_ddrx_list
# (
.CTL_LIST_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CTL_LIST_DEPTH (CFG_DRAM_WLAT_GROUP),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
rdata_address_list
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_valid (rdata_address_list_read_data_valid),
.list_get_entry_ready (rdata_address_list_read),
.list_get_entry_id (rdata_address_list_read_data),
.list_get_entry_id_vector (),
.list_put_entry_valid (rdata_address_list_write),
.list_put_entry_ready (),
.list_put_entry_id (rdata_address_list_write_data)
);
for (i = 0;i < CFG_LOCAL_WLAT_GROUP;i = i + 1)
begin : rdata_if_address_per_dqs_group
always @ (*)
begin
if (read_data_if_valid_first_vector [i])
begin
read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_write_data;
end
else
begin
read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_read_data;
end
end
end
end
endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
write_data_if_address_blocked <= 0;
end
else
begin
write_data_if_address_blocked <= |mux_write_data_if_address_blocked;
end
end
always @ (*)
begin
mux_tbp_data_ready [0] = (mux_notify_data_if_valid [0]) ? dataid_array_tbp_id [0] : {CFG_TBP_NUM{1'b0}};
mux_notify_data_if_burstcount [0] = (mux_notify_data_if_valid [0]) ? dataid_array_burstcount [0] : 0;
mux_read_data_if_address [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_address [0] : 0;
mux_read_data_if_burstcount [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_burstcount [0] : 0;
mux_write_data_if_address_blocked [0] = (dataid_array_data_ready[0] & ( (dataid_array_address[0] == write_data_if_nextaddress) | (dataid_array_address[0] == write_data_if_address) ) );
if (update_cmd_if_nextmaxaddress_wrapped)
begin
mux_update_cmd_if_address_blocked [0] = (dataid_array_valid[0] & ~( (dataid_array_address[0] < update_cmd_if_address) & (dataid_array_address[0] > update_cmd_if_nextmaxaddress) ));
end
else
begin
mux_update_cmd_if_address_blocked [0] = (dataid_array_valid[0] & ( (dataid_array_address[0] >= update_cmd_if_address) & (dataid_array_address[0] <= update_cmd_if_nextmaxaddress) ));
end
end
genvar j;
generate
for (j = 1; j < CFG_DATAID_ARRAY_DEPTH; j = j + 1)
begin : gen_mux_dataid_array_output
always @ (*)
begin
mux_tbp_data_ready [j] = mux_tbp_data_ready [j-1] | ( (mux_notify_data_if_valid [j]) ? dataid_array_tbp_id [j] : {CFG_TBP_NUM{1'b0}} );
mux_notify_data_if_burstcount [j] = mux_notify_data_if_burstcount [j-1] | ( (mux_notify_data_if_valid [j]) ? dataid_array_burstcount [j] : 0 );
mux_read_data_if_address [j] = mux_read_data_if_address [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_address [j] : 0 );
mux_read_data_if_burstcount [j] = mux_read_data_if_burstcount [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_burstcount [j] : 0 );
mux_write_data_if_address_blocked [j] = (dataid_array_data_ready[j] & ( (dataid_array_address[j] == write_data_if_nextaddress) | (dataid_array_address[j] == write_data_if_address) ) );
if (update_cmd_if_nextmaxaddress_wrapped)
begin
mux_update_cmd_if_address_blocked [j] = (dataid_array_valid[j] & ~( (dataid_array_address[j] < update_cmd_if_address) & (dataid_array_address[j] > update_cmd_if_nextmaxaddress) ));
end
else
begin
mux_update_cmd_if_address_blocked [j] = (dataid_array_valid[j] & ( (dataid_array_address[j] >= update_cmd_if_address) & (dataid_array_address[j] <= update_cmd_if_nextmaxaddress) ));
end
end
end
endgenerate
assign notify_tbp_data_ready = mux_tbp_data_ready [CFG_DATAID_ARRAY_DEPTH-1];
assign update_cmd_if_accepted = update_cmd_if_ready & update_cmd_if_valid;
assign update_cmd_if_nextaddress = update_cmd_if_address + update_cmd_if_burstcount;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
update_cmd_if_address <= 0;
update_cmd_if_nextmaxaddress <= 0;
update_cmd_if_nextmaxaddress_wrapped <= 1'b0;
write_data_if_address <= 0;
write_data_if_nextaddress <= 0;
end
else
begin
if (update_cmd_if_accepted)
begin
update_cmd_if_address <= update_cmd_if_nextaddress;
update_cmd_if_nextmaxaddress <= update_cmd_if_nextaddress + cfg_max_cmd_burstcount_2x;
if (update_cmd_if_nextaddress > (update_cmd_if_nextaddress + cfg_max_cmd_burstcount_2x))
begin
update_cmd_if_nextmaxaddress_wrapped <= 1'b1;
end
else
begin
update_cmd_if_nextmaxaddress_wrapped <= 1'b0;
end
end
if (write_data_if_accepted)
begin
write_data_if_address <= write_data_if_address + 1;
write_data_if_nextaddress <= write_data_if_address + 2;
end
else
begin
write_data_if_nextaddress <= write_data_if_address + 1;
end
end
end
always @ (*)
begin
if (update_cmd_if_accepted)
begin
update_cmd_if_next_unnotified_burstcount = update_cmd_if_unnotified_burstcount + update_cmd_if_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
end
else
begin
update_cmd_if_next_unnotified_burstcount = update_cmd_if_unnotified_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
update_cmd_if_unnotified_burstcount <= 0;
end
else
begin
update_cmd_if_unnotified_burstcount <= update_cmd_if_next_unnotified_burstcount;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_cmd_unallocated_counter <= {CFG_BUFFER_ADDR_WIDTH{1'b1}};
err_buffer_cmd_unallocated_counter_overflow <= 0;
end
else
begin
if (update_cmd_if_accepted & read_data_if_valid_last)
begin
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter- update_cmd_if_burstcount + 1;
end
else if (update_cmd_if_accepted)
begin
{err_buffer_cmd_unallocated_counter_overflow, buffer_cmd_unallocated_counter} <= buffer_cmd_unallocated_counter - update_cmd_if_burstcount;
end
else if (read_data_if_valid_last)
begin
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter + 1;
end
else
begin
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
update_cmd_if_ready <= 0;
end
else
begin
update_cmd_if_ready <= ~update_cmd_if_address_blocked;
end
end
assign write_data_if_accepted = write_data_if_ready & write_data_if_valid;
always @ (*)
begin
if (write_data_if_address_blocked)
begin
write_data_if_ready = 1'b0;
end
else
begin
write_data_if_ready = ~buffer_valid_counter_full & ~partial_be_when_no_cmd_tracked;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
read_data_if_datavalid <= 0;
end
else
begin
read_data_if_datavalid <= read_data_if_valid;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
buffer_valid_counter_full <= 1'b0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (write_data_if_accepted & read_data_if_valid_last)
begin
buffer_valid_counter <= buffer_valid_counter;
buffer_valid_counter_full <= buffer_valid_counter_full;
end
else if (write_data_if_accepted)
begin
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
if (buffer_valid_counter == {{(CFG_BUFFER_ADDR_WIDTH - 1){1'b1}}, 1'b0})
begin
buffer_valid_counter_full <= 1'b1;
end
else
begin
buffer_valid_counter_full <= 1'b0;
end
end
else if (read_data_if_valid_last)
begin
buffer_valid_counter <= buffer_valid_counter - 1;
buffer_valid_counter_full <= 1'b0;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
buffer_valid_counter_full <= buffer_valid_counter_full;
end
end
end
always @ (*)
begin
if (partial_be_when_no_cmd_tracked)
begin
notify_tbp_data_partial_be = update_data_if_valid & (|update_data_if_burstcount_same);
end
else
begin
notify_tbp_data_partial_be = partial_be_detected;
end
end
assign update_data_bc_gt_update_cmd_unnotified_bc = ~update_data_if_valid | (update_data_if_burstcount >= update_cmd_if_unnotified_burstcount);
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= 1'b0;
end
else
begin
if (cfg_enable_partial_be_notification)
begin
if (partial_be_when_no_cmd_tracked)
begin
if (update_data_if_valid & ~notify_data_if_valid)
begin
partial_be_when_no_cmd_tracked <= 1'b0;
end
else if (update_data_if_valid & notify_data_if_valid)
begin
if (|update_data_if_burstcount_same)
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= write_data_if_accepted & write_data_if_partial_dm;
end
else
begin
end
end
end
else if (partial_be_detected & ~notify_data_if_valid)
begin
partial_be_detected <= partial_be_detected;
end
else
begin
partial_be_when_no_cmd_tracked <= write_data_if_accepted & write_data_if_partial_dm & update_data_bc_gt_update_cmd_unnotified_bc;
partial_be_detected <= write_data_if_accepted & write_data_if_partial_dm;
end
end
else
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= 1'b0;
end
end
end
endmodule | 25 |
4,921 | data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr2_odt_gen.v | 1,122,957 | alt_mem_ddrx_ddr2_odt_gen.v | v | 446 | 133 | [] | [] | [] | null | line:244 column:15: Illegal character '\x00' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr2_odt_gen.v:107: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'regd_output\' generates 2 bits.\n : ... In instance alt_mem_ddrx_ddr2_odt_gen\n int_tcwl_unreg = cfg_tcl + cfg_add_lat + regd_output - 1\'b1;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr2_odt_gen.v:190: Operator GTE expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'doing_read_count\' generates 4 bits.\n : ... In instance alt_mem_ddrx_ddr2_odt_gen\n else if (doing_read_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr2_odt_gen.v:236: Operator GTE expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'doing_write_count\' generates 4 bits.\n : ... In instance alt_mem_ddrx_ddr2_odt_gen\n else if (doing_write_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr2_odt_gen.v:379: Operator LT expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'doing_write_count\' generates 4 bits.\n : ... In instance alt_mem_ddrx_ddr2_odt_gen\n if (doing_write_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))\n ^\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr2_odt_gen.v:400: Operator LT expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'doing_read_count\' generates 4 bits.\n : ... In instance alt_mem_ddrx_ddr2_odt_gen\n if (doing_read_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))\n ^\n%Error: Exiting due to 5 warning(s)\n' | 3,332 | module | module alt_mem_ddrx_ddr2_odt_gen
# ( parameter
CFG_DWIDTH_RATIO = 2,
CFG_PORT_WIDTH_ADD_LAT = 3,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_TCL = 4
)
(
ctl_clk,
ctl_reset_n,
cfg_tcl,
cfg_add_lat,
cfg_burst_length,
cfg_output_regd,
bg_do_write,
bg_do_read,
int_odt_l,
int_odt_h
);
localparam integer CFG_TCL_PIPE_LENGTH = 2**CFG_PORT_WIDTH_TCL;
localparam CFG_TAOND = 2;
localparam CFG_TAOFD = 2.5;
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TCL-1:0] cfg_tcl;
input [CFG_PORT_WIDTH_ADD_LAT-1:0] cfg_add_lat;
input [4:0] cfg_burst_length;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
input bg_do_write;
input bg_do_read;
output int_odt_l;
output int_odt_h;
wire bg_do_write;
wire bg_do_read;
reg [1:0] regd_output;
reg [CFG_PORT_WIDTH_TCL-1:0] int_tcwl_unreg;
reg [CFG_PORT_WIDTH_TCL-1:0] int_tcwl;
reg int_tcwl_even;
reg int_tcwl_odd;
reg [CFG_PORT_WIDTH_TCL-1:0] write_latency;
reg [CFG_PORT_WIDTH_TCL-1:0] read_latency;
wire int_odt_l;
wire int_odt_h;
reg reg_odt_l;
reg reg_odt_h;
reg combi_odt_l;
reg combi_odt_h;
reg [1:0] offset_code;
reg start_odt_write;
reg start_odt_read;
reg [CFG_TCL_PIPE_LENGTH-1:0] do_write_pipe;
reg [CFG_TCL_PIPE_LENGTH-1:0] do_read_pipe;
reg [3:0] doing_write_count;
reg [3:0] doing_read_count;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
regd_output <= 0;
end
else
begin
if (cfg_output_regd)
regd_output <= (CFG_DWIDTH_RATIO / 2);
else
regd_output <= 2'd0;
end
end
always @ (*)
begin
int_tcwl_unreg = cfg_tcl + cfg_add_lat + regd_output - 1'b1;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_tcwl <= 0;
else
int_tcwl <= int_tcwl_unreg;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_tcwl_even <= 1'b0;
int_tcwl_odd <= 1'b0;
end
else
begin
if (int_tcwl % 2 == 0)
begin
int_tcwl_even <= 1'b1;
int_tcwl_odd <= 1'b0;
end
else
begin
int_tcwl_even <= 1'b0;
int_tcwl_odd <= 1'b1;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
write_latency <= 0;
read_latency <= 0;
end
else
begin
write_latency <= (int_tcwl - 4) / (CFG_DWIDTH_RATIO / 2);
read_latency <= (int_tcwl - 3) / (CFG_DWIDTH_RATIO / 2);
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_read_pipe <= 0;
else
if (bg_do_read)
do_read_pipe <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_read};
else
do_read_pipe <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(*)
begin
if (int_tcwl < 3)
start_odt_read = bg_do_read;
else
start_odt_read = do_read_pipe[read_latency];
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin doing_read_count <= 0; end
else
begin
if (start_odt_read)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
doing_read_count <= 1;
else
doing_read_count <= 0;
end
else if (doing_read_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
doing_read_count <= 0;
end
else if (doing_read_count > 0)
begin
doing_read_count <= doing_read_count + 1'b1;
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_write_pipe <= 0;
else
if (bg_do_write)
do_write_pipe <= {do_write_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_write};
else
do_write_pipe <= {do_write_pipe[CFG_TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(*)
begin
if (int_tcwl < 4)
start_odt_write = bg_do_write;
else
start_odt_write = do_write_pipe[write_latency];
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_write_count <= 0;
else
if (start_odt_write)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
doing_write_count <= 1;
else
doing_write_count <= 0;
end
else if (doing_write_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
doing_write_count <= 0;
end
else if (doing_write_count > 0)
begin
doing_write_count <= doing_write_count + 1'b1;
end
end
always @ (*)
begin
if (CFG_DWIDTH_RATIO == 2)
begin
if (start_odt_write || start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
else
begin
if (int_tcwl_even)
begin
if (start_odt_write)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else if (start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b0;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
else
begin
if (start_odt_write)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b0;
end
else if (start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
else
begin
if (CFG_DWIDTH_RATIO == 2)
begin
if (start_odt_write || start_odt_read)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else if (doing_write_count > 0 || doing_read_count > 0)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
end
else
begin
if (start_odt_write)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_even)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (start_odt_read)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_odd)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (doing_write_count > 0)
begin
if (doing_write_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_even)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (doing_read_count > 0)
begin
if (doing_read_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_odd)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
end
end
end
generate
if (CFG_DWIDTH_RATIO == 2)
begin
assign int_odt_h = combi_odt_h | reg_odt_h;
assign int_odt_l = combi_odt_h | reg_odt_h;
end
else if (CFG_DWIDTH_RATIO == 4)
begin
assign int_odt_h = combi_odt_h | reg_odt_h;
assign int_odt_l = combi_odt_l | reg_odt_l;
end
else if (CFG_DWIDTH_RATIO == 8)
begin
end
endgenerate
endmodule | module alt_mem_ddrx_ddr2_odt_gen
# ( parameter
CFG_DWIDTH_RATIO = 2,
CFG_PORT_WIDTH_ADD_LAT = 3,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_TCL = 4
)
(
ctl_clk,
ctl_reset_n,
cfg_tcl,
cfg_add_lat,
cfg_burst_length,
cfg_output_regd,
bg_do_write,
bg_do_read,
int_odt_l,
int_odt_h
); |
localparam integer CFG_TCL_PIPE_LENGTH = 2**CFG_PORT_WIDTH_TCL;
localparam CFG_TAOND = 2;
localparam CFG_TAOFD = 2.5;
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TCL-1:0] cfg_tcl;
input [CFG_PORT_WIDTH_ADD_LAT-1:0] cfg_add_lat;
input [4:0] cfg_burst_length;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
input bg_do_write;
input bg_do_read;
output int_odt_l;
output int_odt_h;
wire bg_do_write;
wire bg_do_read;
reg [1:0] regd_output;
reg [CFG_PORT_WIDTH_TCL-1:0] int_tcwl_unreg;
reg [CFG_PORT_WIDTH_TCL-1:0] int_tcwl;
reg int_tcwl_even;
reg int_tcwl_odd;
reg [CFG_PORT_WIDTH_TCL-1:0] write_latency;
reg [CFG_PORT_WIDTH_TCL-1:0] read_latency;
wire int_odt_l;
wire int_odt_h;
reg reg_odt_l;
reg reg_odt_h;
reg combi_odt_l;
reg combi_odt_h;
reg [1:0] offset_code;
reg start_odt_write;
reg start_odt_read;
reg [CFG_TCL_PIPE_LENGTH-1:0] do_write_pipe;
reg [CFG_TCL_PIPE_LENGTH-1:0] do_read_pipe;
reg [3:0] doing_write_count;
reg [3:0] doing_read_count;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
regd_output <= 0;
end
else
begin
if (cfg_output_regd)
regd_output <= (CFG_DWIDTH_RATIO / 2);
else
regd_output <= 2'd0;
end
end
always @ (*)
begin
int_tcwl_unreg = cfg_tcl + cfg_add_lat + regd_output - 1'b1;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_tcwl <= 0;
else
int_tcwl <= int_tcwl_unreg;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_tcwl_even <= 1'b0;
int_tcwl_odd <= 1'b0;
end
else
begin
if (int_tcwl % 2 == 0)
begin
int_tcwl_even <= 1'b1;
int_tcwl_odd <= 1'b0;
end
else
begin
int_tcwl_even <= 1'b0;
int_tcwl_odd <= 1'b1;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
write_latency <= 0;
read_latency <= 0;
end
else
begin
write_latency <= (int_tcwl - 4) / (CFG_DWIDTH_RATIO / 2);
read_latency <= (int_tcwl - 3) / (CFG_DWIDTH_RATIO / 2);
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_read_pipe <= 0;
else
if (bg_do_read)
do_read_pipe <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_read};
else
do_read_pipe <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(*)
begin
if (int_tcwl < 3)
start_odt_read = bg_do_read;
else
start_odt_read = do_read_pipe[read_latency];
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin doing_read_count <= 0; end
else
begin
if (start_odt_read)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
doing_read_count <= 1;
else
doing_read_count <= 0;
end
else if (doing_read_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
doing_read_count <= 0;
end
else if (doing_read_count > 0)
begin
doing_read_count <= doing_read_count + 1'b1;
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_write_pipe <= 0;
else
if (bg_do_write)
do_write_pipe <= {do_write_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_write};
else
do_write_pipe <= {do_write_pipe[CFG_TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(*)
begin
if (int_tcwl < 4)
start_odt_write = bg_do_write;
else
start_odt_write = do_write_pipe[write_latency];
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_write_count <= 0;
else
if (start_odt_write)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
doing_write_count <= 1;
else
doing_write_count <= 0;
end
else if (doing_write_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
doing_write_count <= 0;
end
else if (doing_write_count > 0)
begin
doing_write_count <= doing_write_count + 1'b1;
end
end
always @ (*)
begin
if (CFG_DWIDTH_RATIO == 2)
begin
if (start_odt_write || start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
else
begin
if (int_tcwl_even)
begin
if (start_odt_write)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else if (start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b0;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
else
begin
if (start_odt_write)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b0;
end
else if (start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
else
begin
if (CFG_DWIDTH_RATIO == 2)
begin
if (start_odt_write || start_odt_read)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else if (doing_write_count > 0 || doing_read_count > 0)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
end
else
begin
if (start_odt_write)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_even)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (start_odt_read)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_odd)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (doing_write_count > 0)
begin
if (doing_write_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_even)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (doing_read_count > 0)
begin
if (doing_read_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_odd)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
end
end
end
generate
if (CFG_DWIDTH_RATIO == 2)
begin
assign int_odt_h = combi_odt_h | reg_odt_h;
assign int_odt_l = combi_odt_h | reg_odt_h;
end
else if (CFG_DWIDTH_RATIO == 4)
begin
assign int_odt_h = combi_odt_h | reg_odt_h;
assign int_odt_l = combi_odt_l | reg_odt_l;
end
else if (CFG_DWIDTH_RATIO == 8)
begin
end
endgenerate
endmodule | 25 |
4,922 | data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr3_odt_gen.v | 1,122,957 | alt_mem_ddrx_ddr3_odt_gen.v | v | 350 | 162 | [] | [] | [] | [(5, 349)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr3_odt_gen.v:105: Operator MODDIV expects 32 bits on the LHS, but LHS\'s VARREF \'diff\' generates 4 bits.\n : ... In instance alt_mem_ddrx_ddr3_odt_gen\n assign diff_modulo_unreg = (diff % CFG_ODTPIPE_THRESHOLD); \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr3_odt_gen.v:105: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n : ... In instance alt_mem_ddrx_ddr3_odt_gen\n assign diff_modulo_unreg = (diff % CFG_ODTPIPE_THRESHOLD); \n ^\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr3_odt_gen.v:106: Operator DIV expects 32 bits on the LHS, but LHS\'s VARREF \'diff\' generates 4 bits.\n : ... In instance alt_mem_ddrx_ddr3_odt_gen\n assign sel_do_read_pipe_unreg = (diff / CFG_ODTPIPE_THRESHOLD) + diff_modulo;\n ^\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr3_odt_gen.v:106: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'diff_modulo\' generates 4 bits.\n : ... In instance alt_mem_ddrx_ddr3_odt_gen\n assign sel_do_read_pipe_unreg = (diff / CFG_ODTPIPE_THRESHOLD) + diff_modulo;\n ^\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr3_odt_gen.v:106: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance alt_mem_ddrx_ddr3_odt_gen\n assign sel_do_read_pipe_unreg = (diff / CFG_ODTPIPE_THRESHOLD) + diff_modulo;\n ^\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr3_odt_gen.v:129: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'diff\' generates 4 bits.\n : ... In instance alt_mem_ddrx_ddr3_odt_gen\n int_do_read = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_read : do_read_pipe [sel_do_read_pipe] ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr3_odt_gen.v:130: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'diff\' generates 4 bits.\n : ... In instance alt_mem_ddrx_ddr3_odt_gen\n int_do_read_burst_chop_c = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_burst_chop : do_burst_chop_pipe [sel_do_read_pipe] ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr3_odt_gen.v:172: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance alt_mem_ddrx_ddr3_odt_gen\n assign doing_read_count_limit = int_do_read_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);\n ^\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr3_odt_gen.v:221: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance alt_mem_ddrx_ddr3_odt_gen\n assign doing_write_count_limit = int_do_write_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);\n ^\n%Error: Exiting due to 9 warning(s)\n' | 3,333 | module | module alt_mem_ddrx_ddr3_odt_gen
# (parameter
CFG_DWIDTH_RATIO = 2,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_TCL = 4,
CFG_PORT_WIDTH_CAS_WR_LAT = 4
)
(
ctl_clk,
ctl_reset_n,
cfg_tcl,
cfg_cas_wr_lat,
cfg_output_regd,
bg_do_write,
bg_do_read,
bg_do_burst_chop,
int_odt_l,
int_odt_h,
int_odt_i
);
localparam integer CFG_TCL_PIPE_LENGTH = 2**CFG_PORT_WIDTH_TCL;
localparam integer CFG_ODTH8 = 6;
localparam integer CFG_ODTH4 = 4;
localparam integer CFG_ODTPIPE_THRESHOLD = CFG_DWIDTH_RATIO/2;
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TCL-1:0] cfg_tcl;
input [CFG_PORT_WIDTH_CAS_WR_LAT-1:0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
input bg_do_write;
input bg_do_read;
input bg_do_burst_chop;
output int_odt_l;
output int_odt_h;
output int_odt_i;
wire bg_do_write;
reg int_do_read;
reg int_do_write_burst_chop;
reg int_do_read_burst_chop;
reg int_do_read_burst_chop_c;
reg do_read_r;
wire [3:0] diff_unreg;
reg [3:0] diff;
wire [3:0] diff_modulo_unreg;
reg [3:0] diff_modulo;
wire [3:0] sel_do_read_pipe_unreg;
reg [3:0] sel_do_read_pipe;
wire diff_modulo_not_zero;
reg int_odt_l_int;
reg int_odt_l_int_r;
reg premux_odt_h;
reg premux_odt_h_r;
reg int_odt_h_int;
reg int_odt_h_int_r;
reg int_odt_i_int;
reg int_odt_i_int_r;
wire int_odt_l;
wire int_odt_h;
wire int_odt_i;
reg [3:0] doing_write_count;
reg [3:0] doing_read_count;
wire doing_read_count_not_zero;
reg doing_read_count_not_zero_r;
wire [3:0] doing_write_count_limit;
wire [3:0] doing_read_count_limit;
reg [CFG_TCL_PIPE_LENGTH -1:0] do_read_pipe;
reg [CFG_TCL_PIPE_LENGTH -1:0] do_burst_chop_pipe;
assign diff_unreg = cfg_tcl - cfg_cas_wr_lat;
assign diff_modulo_unreg = (diff % CFG_ODTPIPE_THRESHOLD);
assign sel_do_read_pipe_unreg = (diff / CFG_ODTPIPE_THRESHOLD) + diff_modulo;
assign diff_modulo_not_zero = (|diff_modulo);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
diff <= 0;
diff_modulo <= 0;
sel_do_read_pipe <= 0;
end
else
begin
diff <= diff_unreg;
diff_modulo <= diff_modulo_unreg;
sel_do_read_pipe <= sel_do_read_pipe_unreg;
end
end
always @ (*)
begin
int_do_read = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_read : do_read_pipe [sel_do_read_pipe] ;
int_do_read_burst_chop_c = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_burst_chop : do_burst_chop_pipe [sel_do_read_pipe] ;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_do_read_burst_chop <= 1'b0;
end
else
begin
if (int_do_read)
begin
int_do_read_burst_chop <= int_do_read_burst_chop_c;
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_read_pipe <= 0;
end
else
begin
do_read_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_read};
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_burst_chop_pipe <= 0;
end
else
begin
do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_burst_chop};
end
end
assign doing_read_count_limit = int_do_read_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
assign doing_read_count_not_zero = (|doing_read_count);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin doing_read_count <= 0; end
else
begin
if (int_do_read)
begin doing_read_count <= 1; end
else if (doing_read_count >= doing_read_count_limit)
begin doing_read_count <= 0; end
else if (doing_read_count > 0)
begin doing_read_count <= doing_read_count + 1'b1; end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
doing_read_count_not_zero_r <= 1'b0;
end
else
begin
doing_read_count_not_zero_r <= doing_read_count_not_zero;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_do_write_burst_chop <= 1'b0;
end
else
begin
if (bg_do_write)
begin
int_do_write_burst_chop <= bg_do_burst_chop;
end
end
end
assign doing_write_count_limit = int_do_write_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin doing_write_count <= 0; end
else
begin
if (bg_do_write)
begin doing_write_count <= 1; end
else if (doing_write_count >= doing_write_count_limit)
begin doing_write_count <= 0; end
else if (doing_write_count > 0)
begin doing_write_count <= doing_write_count + 1'b1; end
end
end
always @ (*)
begin
if (bg_do_write || int_do_read)
begin premux_odt_h = 1'b1; end
else if (doing_write_count > 0 || doing_read_count > 0)
begin premux_odt_h = 1'b1; end
else
begin premux_odt_h = 1'b0; end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
premux_odt_h_r <= 1'b0;
end
else
begin
premux_odt_h_r <= premux_odt_h;
end
end
always @ (*)
begin
if (diff_modulo_not_zero & (int_do_read|doing_read_count_not_zero_r) )
begin
int_odt_h_int = premux_odt_h_r;
end
else
begin
int_odt_h_int = premux_odt_h;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_l_int <= 1'b0;
end
else
begin
if (bg_do_write || int_do_read)
begin int_odt_l_int <= 1'b1; end
else if (doing_write_count > 0 || doing_read_count > 0)
begin int_odt_l_int <= 1'b1; end
else
begin int_odt_l_int <= 1'b0; end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_i_int <= 1'b0;
end
else
begin
if (bg_do_write || int_do_read)
begin int_odt_i_int <= 1'b1; end
else if (doing_write_count > 1 || doing_read_count > 1)
begin int_odt_i_int <= 1'b1; end
else
begin int_odt_i_int <= 1'b0; end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_h_int_r <= 1'b0;
int_odt_l_int_r <= 1'b0;
int_odt_i_int_r <= 1'b0;
end
else
begin
int_odt_h_int_r <= int_odt_h_int;
int_odt_l_int_r <= int_odt_l_int;
int_odt_i_int_r <= int_odt_i_int;
end
end
generate
if (CFG_DWIDTH_RATIO == 2)
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_i = 1'b0;
end
else if (CFG_DWIDTH_RATIO == 4)
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_l_int_r : int_odt_l_int;
assign int_odt_i = 1'b0;
end
else if (CFG_DWIDTH_RATIO == 8)
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_l_int_r : int_odt_l_int;
assign int_odt_i = (cfg_output_regd) ? int_odt_i_int_r : int_odt_i_int;
end
endgenerate
endmodule | module alt_mem_ddrx_ddr3_odt_gen
# (parameter
CFG_DWIDTH_RATIO = 2,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_TCL = 4,
CFG_PORT_WIDTH_CAS_WR_LAT = 4
)
(
ctl_clk,
ctl_reset_n,
cfg_tcl,
cfg_cas_wr_lat,
cfg_output_regd,
bg_do_write,
bg_do_read,
bg_do_burst_chop,
int_odt_l,
int_odt_h,
int_odt_i
); |
localparam integer CFG_TCL_PIPE_LENGTH = 2**CFG_PORT_WIDTH_TCL;
localparam integer CFG_ODTH8 = 6;
localparam integer CFG_ODTH4 = 4;
localparam integer CFG_ODTPIPE_THRESHOLD = CFG_DWIDTH_RATIO/2;
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TCL-1:0] cfg_tcl;
input [CFG_PORT_WIDTH_CAS_WR_LAT-1:0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
input bg_do_write;
input bg_do_read;
input bg_do_burst_chop;
output int_odt_l;
output int_odt_h;
output int_odt_i;
wire bg_do_write;
reg int_do_read;
reg int_do_write_burst_chop;
reg int_do_read_burst_chop;
reg int_do_read_burst_chop_c;
reg do_read_r;
wire [3:0] diff_unreg;
reg [3:0] diff;
wire [3:0] diff_modulo_unreg;
reg [3:0] diff_modulo;
wire [3:0] sel_do_read_pipe_unreg;
reg [3:0] sel_do_read_pipe;
wire diff_modulo_not_zero;
reg int_odt_l_int;
reg int_odt_l_int_r;
reg premux_odt_h;
reg premux_odt_h_r;
reg int_odt_h_int;
reg int_odt_h_int_r;
reg int_odt_i_int;
reg int_odt_i_int_r;
wire int_odt_l;
wire int_odt_h;
wire int_odt_i;
reg [3:0] doing_write_count;
reg [3:0] doing_read_count;
wire doing_read_count_not_zero;
reg doing_read_count_not_zero_r;
wire [3:0] doing_write_count_limit;
wire [3:0] doing_read_count_limit;
reg [CFG_TCL_PIPE_LENGTH -1:0] do_read_pipe;
reg [CFG_TCL_PIPE_LENGTH -1:0] do_burst_chop_pipe;
assign diff_unreg = cfg_tcl - cfg_cas_wr_lat;
assign diff_modulo_unreg = (diff % CFG_ODTPIPE_THRESHOLD);
assign sel_do_read_pipe_unreg = (diff / CFG_ODTPIPE_THRESHOLD) + diff_modulo;
assign diff_modulo_not_zero = (|diff_modulo);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
diff <= 0;
diff_modulo <= 0;
sel_do_read_pipe <= 0;
end
else
begin
diff <= diff_unreg;
diff_modulo <= diff_modulo_unreg;
sel_do_read_pipe <= sel_do_read_pipe_unreg;
end
end
always @ (*)
begin
int_do_read = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_read : do_read_pipe [sel_do_read_pipe] ;
int_do_read_burst_chop_c = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_burst_chop : do_burst_chop_pipe [sel_do_read_pipe] ;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_do_read_burst_chop <= 1'b0;
end
else
begin
if (int_do_read)
begin
int_do_read_burst_chop <= int_do_read_burst_chop_c;
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_read_pipe <= 0;
end
else
begin
do_read_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_read};
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_burst_chop_pipe <= 0;
end
else
begin
do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_burst_chop};
end
end
assign doing_read_count_limit = int_do_read_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
assign doing_read_count_not_zero = (|doing_read_count);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin doing_read_count <= 0; end
else
begin
if (int_do_read)
begin doing_read_count <= 1; end
else if (doing_read_count >= doing_read_count_limit)
begin doing_read_count <= 0; end
else if (doing_read_count > 0)
begin doing_read_count <= doing_read_count + 1'b1; end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
doing_read_count_not_zero_r <= 1'b0;
end
else
begin
doing_read_count_not_zero_r <= doing_read_count_not_zero;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_do_write_burst_chop <= 1'b0;
end
else
begin
if (bg_do_write)
begin
int_do_write_burst_chop <= bg_do_burst_chop;
end
end
end
assign doing_write_count_limit = int_do_write_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin doing_write_count <= 0; end
else
begin
if (bg_do_write)
begin doing_write_count <= 1; end
else if (doing_write_count >= doing_write_count_limit)
begin doing_write_count <= 0; end
else if (doing_write_count > 0)
begin doing_write_count <= doing_write_count + 1'b1; end
end
end
always @ (*)
begin
if (bg_do_write || int_do_read)
begin premux_odt_h = 1'b1; end
else if (doing_write_count > 0 || doing_read_count > 0)
begin premux_odt_h = 1'b1; end
else
begin premux_odt_h = 1'b0; end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
premux_odt_h_r <= 1'b0;
end
else
begin
premux_odt_h_r <= premux_odt_h;
end
end
always @ (*)
begin
if (diff_modulo_not_zero & (int_do_read|doing_read_count_not_zero_r) )
begin
int_odt_h_int = premux_odt_h_r;
end
else
begin
int_odt_h_int = premux_odt_h;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_l_int <= 1'b0;
end
else
begin
if (bg_do_write || int_do_read)
begin int_odt_l_int <= 1'b1; end
else if (doing_write_count > 0 || doing_read_count > 0)
begin int_odt_l_int <= 1'b1; end
else
begin int_odt_l_int <= 1'b0; end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_i_int <= 1'b0;
end
else
begin
if (bg_do_write || int_do_read)
begin int_odt_i_int <= 1'b1; end
else if (doing_write_count > 1 || doing_read_count > 1)
begin int_odt_i_int <= 1'b1; end
else
begin int_odt_i_int <= 1'b0; end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_h_int_r <= 1'b0;
int_odt_l_int_r <= 1'b0;
int_odt_i_int_r <= 1'b0;
end
else
begin
int_odt_h_int_r <= int_odt_h_int;
int_odt_l_int_r <= int_odt_l_int;
int_odt_i_int_r <= int_odt_i_int;
end
end
generate
if (CFG_DWIDTH_RATIO == 2)
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_i = 1'b0;
end
else if (CFG_DWIDTH_RATIO == 4)
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_l_int_r : int_odt_l_int;
assign int_odt_i = 1'b0;
end
else if (CFG_DWIDTH_RATIO == 8)
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_l_int_r : int_odt_l_int;
assign int_odt_i = (cfg_output_regd) ? int_odt_i_int_r : int_odt_i_int;
end
endgenerate
endmodule | 25 |
4,923 | data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v | 1,122,957 | alt_mem_ddrx_ecc_encoder_decoder_wrapper.v | v | 1,124 | 273 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v:358: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n : ... In instance alt_mem_ddrx_ecc_encoder_decoder_wrapper\n cfg_dram_dm_width <= cfg_dram_data_width / CFG_MEM_IF_DQ_PER_DQS;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v:370: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n : ... In instance alt_mem_ddrx_ecc_encoder_decoder_wrapper\n cfg_local_dm_width <= cfg_local_data_width / CFG_MEM_IF_DQ_PER_DQS;\n ^~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v:653: Cannot find file containing module: \'alt_mem_ddrx_ecc_encoder\'\n alt_mem_ddrx_ecc_encoder #\n ^~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy,data/full_repos/permissive/1122957/alt_mem_ddrx_ecc_encoder\n data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy,data/full_repos/permissive/1122957/alt_mem_ddrx_ecc_encoder.v\n data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy,data/full_repos/permissive/1122957/alt_mem_ddrx_ecc_encoder.sv\n alt_mem_ddrx_ecc_encoder\n alt_mem_ddrx_ecc_encoder.v\n alt_mem_ddrx_ecc_encoder.sv\n obj_dir/alt_mem_ddrx_ecc_encoder\n obj_dir/alt_mem_ddrx_ecc_encoder.v\n obj_dir/alt_mem_ddrx_ecc_encoder.sv\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v:675: Cannot find file containing module: \'alt_mem_ddrx_ecc_encoder\'\n alt_mem_ddrx_ecc_encoder #\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v:697: Cannot find file containing module: \'alt_mem_ddrx_ecc_encoder\'\n alt_mem_ddrx_ecc_encoder #\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v:742: Cannot find file containing module: \'alt_mem_ddrx_ecc_decoder\'\n alt_mem_ddrx_ecc_decoder #\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n' | 3,340 | module | module alt_mem_ddrx_ecc_encoder_decoder_wrapper #
( parameter
CFG_LOCAL_DATA_WIDTH = 80,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_DWIDTH_RATIO = 2,
CFG_MEM_IF_DQ_WIDTH = 40,
CFG_MEM_IF_DQS_WIDTH = 5,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_MULTIPLES = 1,
CFG_ECC_ENC_REG = 0,
CFG_ECC_DEC_REG = 0,
CFG_ECC_RDATA_REG = 0,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_GEN_SBE = 1,
CFG_PORT_WIDTH_GEN_DBE = 1,
CFG_PORT_WIDTH_ENABLE_INTR = 1,
CFG_PORT_WIDTH_MASK_SBE_INTR = 1,
CFG_PORT_WIDTH_MASK_DBE_INTR = 1,
CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1,
CFG_PORT_WIDTH_CLR_INTR = 1,
STS_PORT_WIDTH_SBE_ERROR = 1,
STS_PORT_WIDTH_DBE_ERROR = 1,
STS_PORT_WIDTH_SBE_COUNT = 8,
STS_PORT_WIDTH_DBE_COUNT = 8,
STS_PORT_WIDTH_CORR_DROP_ERROR = 1,
STS_PORT_WIDTH_CORR_DROP_COUNT = 8
)
(
ctl_clk,
ctl_reset_n,
cfg_interface_width,
cfg_enable_ecc,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
wdatap_dm,
wdatap_data,
wdatap_rmw_partial_data,
wdatap_rmw_correct_data,
wdatap_rmw_partial,
wdatap_rmw_correct,
wdatap_ecc_code,
wdatap_ecc_code_overwrite,
rdatap_rcvd_addr,
rdatap_rcvd_cmd,
rdatap_rcvd_corr_dropped,
afi_rdata,
afi_rdata_valid,
ecc_rdata,
ecc_rdata_valid,
ecc_dm,
ecc_wdata,
ecc_sbe,
ecc_dbe,
ecc_code,
ecc_interrupt,
sts_sbe_error,
sts_dbe_error,
sts_sbe_count,
sts_dbe_count,
sts_err_addr,
sts_corr_dropped,
sts_corr_dropped_count,
sts_corr_dropped_addr
);
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_ECC_DATA_WIDTH = CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO;
localparam CFG_LOCAL_DM_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_ECC_DM_WIDTH = CFG_ECC_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_LOCAL_DATA_PER_WORD_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_LOCAL_DM_PER_WORD_WIDTH = CFG_LOCAL_DM_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_ECC_DATA_PER_WORD_WIDTH = CFG_ECC_DATA_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_ECC_DM_PER_WORD_WIDTH = CFG_ECC_DM_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_MMR_DRAM_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_LOCAL_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_DRAM_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2;
localparam CFG_MMR_LOCAL_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2;
localparam CFG_ENCODER_DATA_WIDTH = CFG_ECC_DATA_PER_WORD_WIDTH;
localparam CFG_DECODER_DATA_WIDTH = CFG_ECC_DATA_PER_WORD_WIDTH;
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] cfg_gen_sbe;
input [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] cfg_gen_dbe;
input [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] cfg_enable_intr;
input [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] cfg_mask_sbe_intr;
input [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] cfg_mask_dbe_intr;
input [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] cfg_mask_corr_dropped_intr;
input [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] cfg_clr_intr;
input [CFG_LOCAL_DM_WIDTH - 1 : 0] wdatap_dm;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_data;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_partial_data;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_correct_data;
input wdatap_rmw_partial;
input wdatap_rmw_correct;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
input [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] rdatap_rcvd_addr;
input rdatap_rcvd_cmd;
input rdatap_rcvd_corr_dropped;
input [CFG_ECC_DATA_WIDTH - 1 : 0] afi_rdata;
input [CFG_DWIDTH_RATIO / 2 - 1 : 0] afi_rdata_valid;
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
output ecc_rdata_valid;
output [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
output [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
output [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
output [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
output ecc_interrupt;
output [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
output [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
output [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
output [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
output [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
output [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
reg ecc_rdata_valid;
reg [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
reg [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
reg [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
reg [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
reg ecc_interrupt;
reg [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
reg [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
reg [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
reg [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
reg [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
reg [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
reg [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
reg [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_local_data_width;
reg [CFG_MMR_DRAM_DM_WIDTH - 1 : 0] cfg_dram_dm_width;
reg [CFG_MMR_LOCAL_DM_WIDTH - 1 : 0] cfg_local_dm_width;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_data;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_rmw_partial_data;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_rmw_correct_data;
reg int_encoder_input_rmw_partial;
reg int_encoder_input_rmw_correct;
reg wdatap_rmw_partial_r;
reg wdatap_rmw_correct_r;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg int_decoder_input_data_valid;
reg [CFG_ECC_MULTIPLES - 1 : 0] int_sbe;
reg [CFG_ECC_MULTIPLES - 1 : 0] int_dbe;
reg [CFG_ECC_DM_WIDTH - 1 : 0] int_encoder_output_dm;
reg [CFG_ECC_DM_WIDTH - 1 : 0] int_encoder_output_dm_r;
wire [CFG_ECC_MULTIPLES - 1 : 0] int_decoder_output_data_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_encoder_output_data;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_encoder_output_data_r;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_decoder_output_data;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] int_ecc_code;
reg [1 : 0] inject_data_error;
reg int_sbe_detected;
reg int_dbe_detected;
wire int_be_detected;
reg int_sbe_store;
reg int_dbe_store;
reg int_sbe_valid;
reg int_dbe_valid;
reg int_sbe_valid_r;
reg int_dbe_valid_r;
reg int_ecc_interrupt;
wire int_interruptable_error_detected;
reg [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] int_sbe_error;
reg [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] int_dbe_error;
reg [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] int_sbe_count;
reg [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] int_dbe_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_err_addr ;
reg [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] int_corr_dropped;
reg [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] int_corr_dropped_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_corr_dropped_addr ;
reg int_corr_dropped_detected;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_data_width <= 0;
end
else
begin
cfg_dram_data_width <= cfg_interface_width;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_local_data_width <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
cfg_local_data_width <= cfg_interface_width - CFG_ECC_CODE_WIDTH;
end
else
begin
cfg_local_data_width <= cfg_interface_width;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_dm_width <= 0;
end
else
begin
cfg_dram_dm_width <= cfg_dram_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_local_dm_width <= 0;
end
else
begin
cfg_local_dm_width <= cfg_local_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_rmw_partial_r <= 1'b0;
wdatap_rmw_correct_r <= 1'b0;
end
else
begin
wdatap_rmw_partial_r <= wdatap_rmw_partial;
wdatap_rmw_correct_r <= wdatap_rmw_correct;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_encoder_output_data_r <= 0;
int_encoder_output_dm_r <= 0;
end
else
begin
int_encoder_output_data_r <= int_encoder_output_data;
int_encoder_output_dm_r <= int_encoder_output_dm;
end
end
always @ (*)
begin
int_encoder_input_data = wdatap_data;
int_encoder_input_rmw_partial_data = wdatap_rmw_partial_data;
int_encoder_input_rmw_correct_data = wdatap_rmw_correct_data;
if (CFG_ECC_ENC_REG)
begin
int_encoder_input_rmw_partial = wdatap_rmw_partial_r;
int_encoder_input_rmw_correct = wdatap_rmw_correct_r;
end
else
begin
int_encoder_input_rmw_partial = wdatap_rmw_partial;
int_encoder_input_rmw_correct = wdatap_rmw_correct;
end
end
generate
genvar i_drate;
for (i_drate = 0;i_drate < CFG_ECC_MULTIPLES;i_drate = i_drate + 1)
begin : encoder_input_dm_mux_per_dm_drate
wire [CFG_LOCAL_DM_PER_WORD_WIDTH-1:0] int_encoder_input_dm = wdatap_dm [(i_drate + 1) * CFG_LOCAL_DM_PER_WORD_WIDTH - 1 : i_drate * CFG_LOCAL_DM_PER_WORD_WIDTH];
wire int_encoder_input_dm_all_zeros = ~(|int_encoder_input_dm);
always @ (*)
begin
if (cfg_enable_ecc)
begin
if (int_encoder_input_dm_all_zeros)
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b0}},int_encoder_input_dm};
end
else
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b1}},int_encoder_input_dm};
end
end
else
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b0}},int_encoder_input_dm};
end
end
end
endgenerate
always @ (*)
begin
int_decoder_input_data = afi_rdata;
end
always @ (*)
begin
int_decoder_input_data_valid = afi_rdata_valid [0];
end
always @ (*)
begin
ecc_wdata = int_encoder_output_data;
end
always @ (*)
begin
if (CFG_ECC_ENC_REG)
begin
ecc_dm = int_encoder_output_dm_r;
end
else
begin
ecc_dm = int_encoder_output_dm;
end
end
always @ (*)
begin
ecc_rdata = int_decoder_output_data;
end
always @ (*)
begin
ecc_rdata_valid = |int_decoder_output_data_valid;
end
always @ (*)
begin
if (cfg_enable_ecc)
ecc_sbe = int_sbe;
else
ecc_sbe = 0;
end
always @ (*)
begin
if (cfg_enable_ecc)
ecc_dbe = int_dbe;
else
ecc_dbe = 0;
end
always @ (*)
begin
if (cfg_enable_ecc)
ecc_code = int_ecc_code;
else
ecc_code = 0;
end
always @ (*)
begin
ecc_interrupt = int_ecc_interrupt;
end
always @ (*)
begin
sts_sbe_error = int_sbe_error;
end
always @ (*)
begin
sts_dbe_error = int_dbe_error;
end
always @ (*)
begin
sts_sbe_count = int_sbe_count;
end
always @ (*)
begin
sts_dbe_count = int_dbe_count;
end
always @ (*)
begin
sts_err_addr = int_err_addr;
end
always @ (*)
begin
sts_corr_dropped = int_corr_dropped;
end
always @ (*)
begin
sts_corr_dropped_count = int_corr_dropped_count;
end
always @ (*)
begin
sts_corr_dropped_addr = int_corr_dropped_addr;
end
generate
genvar m_drate;
for (m_drate = 0;m_drate < CFG_ECC_MULTIPLES;m_drate = m_drate + 1)
begin : encoder_inst_per_drate
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_rmw_partial_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_rmw_partial_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_rmw_correct_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_rmw_correct_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code = wdatap_ecc_code [(m_drate + 1) * CFG_ECC_CODE_WIDTH - 1 : m_drate * CFG_ECC_CODE_WIDTH];
wire input_ecc_code_overwrite = wdatap_ecc_code_overwrite [m_drate];
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_data;
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_rmw_partial_data;
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_rmw_correct_data;
always @ (*)
begin
if (int_encoder_input_rmw_partial)
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_rmw_partial_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_rmw_partial_data [1 : 0] ^ inject_data_error [1 : 0])};
end
else if (int_encoder_input_rmw_correct)
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_rmw_correct_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_rmw_correct_data [1 : 0] ^ inject_data_error [1 : 0])};
end
else
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_data [1 : 0] ^ inject_data_error [1 : 0])};
end
end
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (1'b0 ),
.output_data (output_data )
);
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
rmw_partial_encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_rmw_partial_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (1'b0 ),
.output_data (output_rmw_partial_data )
);
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
rmw_correct_encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_rmw_correct_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (input_ecc_code_overwrite ),
.output_data (output_rmw_correct_data )
);
end
endgenerate
generate
genvar n_drate;
for (n_drate = 0;n_drate < CFG_ECC_MULTIPLES;n_drate = n_drate + 1)
begin : decoder_inst_per_drate
wire err_corrected;
wire err_detected;
wire err_fatal;
wire [CFG_DECODER_DATA_WIDTH - 1 : 0] input_data = {{CFG_DECODER_DATA_WIDTH - CFG_ECC_DATA_PER_WORD_WIDTH{1'b0}}, int_decoder_input_data [(n_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : n_drate * CFG_ECC_DATA_PER_WORD_WIDTH]};
wire input_data_valid = int_decoder_input_data_valid;
wire [CFG_DECODER_DATA_WIDTH - 1 : 0] output_data;
wire output_data_valid;
wire [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
assign int_decoder_output_data [(n_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : n_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH] = output_data [CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : 0];
assign int_ecc_code [(n_drate + 1) * CFG_ECC_CODE_WIDTH - 1 : n_drate * CFG_ECC_CODE_WIDTH ] = output_ecc_code;
assign int_decoder_output_data_valid [n_drate] = output_data_valid;
alt_mem_ddrx_ecc_decoder #
(
.CFG_DATA_WIDTH (CFG_DECODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_DEC_REG (CFG_ECC_DEC_REG ),
.CFG_ECC_RDATA_REG (CFG_ECC_RDATA_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
decoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_data ),
.input_data_valid (input_data_valid ),
.output_data (output_data ),
.output_data_valid (output_data_valid ),
.output_ecc_code (output_ecc_code ),
.err_corrected (err_corrected ),
.err_detected (err_detected ),
.err_fatal (err_fatal )
);
always @ (*)
begin
if (err_detected)
begin
if (err_corrected)
begin
int_sbe [n_drate] = 1'b1;
int_dbe [n_drate] = 1'b0;
end
else if (err_fatal)
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b1;
end
else
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b0;
end
end
else
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b0;
end
end
end
endgenerate
always @ (*)
begin
int_sbe_valid = |int_sbe & ecc_rdata_valid;
int_dbe_valid = |int_dbe & ecc_rdata_valid;
int_sbe_detected = ( int_sbe_store | int_sbe_valid_r ) & rdatap_rcvd_cmd;
int_dbe_detected = ( int_dbe_store | int_dbe_valid_r ) & rdatap_rcvd_cmd;
int_corr_dropped_detected = rdatap_rcvd_corr_dropped;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_sbe_valid_r <= 0;
int_dbe_valid_r <= 0;
int_sbe_store <= 0;
int_dbe_store <= 0;
end
else
begin
int_sbe_valid_r <= int_sbe_valid;
int_dbe_valid_r <= int_dbe_valid;
int_sbe_store <= (int_sbe_store | int_sbe_valid_r) & ~rdatap_rcvd_cmd;
int_dbe_store <= (int_dbe_store | int_dbe_valid_r) & ~rdatap_rcvd_cmd;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
inject_data_error <= 0;
end
else
begin
if (cfg_gen_dbe)
inject_data_error <= 2'b11;
else if (cfg_gen_sbe)
inject_data_error <= 2'b01;
else
inject_data_error <= 2'b00;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_sbe_error <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_sbe_detected)
int_sbe_error <= 1'b1;
else if (cfg_clr_intr)
int_sbe_error <= 1'b0;
end
else
begin
int_sbe_error <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_sbe_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_sbe_detected)
int_sbe_count <= 1;
else
int_sbe_count <= 0;
else if (int_sbe_detected)
int_sbe_count <= int_sbe_count + 1'b1;
end
else
begin
int_sbe_count <= {STS_PORT_WIDTH_SBE_COUNT{1'b0}};
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dbe_error <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_dbe_detected)
int_dbe_error <= 1'b1;
else if (cfg_clr_intr)
int_dbe_error <= 1'b0;
end
else
begin
int_dbe_error <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dbe_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_dbe_detected)
int_dbe_count <= 1;
else
int_dbe_count <= 0;
else if (int_dbe_detected)
int_dbe_count <= int_dbe_count + 1'b1;
end
else
begin
int_dbe_count <= {STS_PORT_WIDTH_DBE_COUNT{1'b0}};
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_err_addr <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_be_detected)
int_err_addr <= rdatap_rcvd_addr;
else if (cfg_clr_intr)
int_err_addr <= 0;
end
else
begin
int_err_addr <= {CFG_LOCAL_ADDR_WIDTH{1'b0}};
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_corr_dropped_detected)
int_corr_dropped <= 1'b1;
else if (cfg_clr_intr)
int_corr_dropped <= 1'b0;
end
else
begin
int_corr_dropped <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_corr_dropped_detected)
int_corr_dropped_count <= 1;
else
int_corr_dropped_count <= 0;
else if (int_corr_dropped_detected)
int_corr_dropped_count <= int_corr_dropped_count + 1'b1;
end
else
begin
int_corr_dropped_count <= {STS_PORT_WIDTH_CORR_DROP_COUNT{1'b0}};
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped_addr <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_corr_dropped_detected)
int_corr_dropped_addr <= rdatap_rcvd_addr;
else if (cfg_clr_intr)
int_corr_dropped_addr <= 0;
end
else
begin
int_corr_dropped_addr <= {CFG_LOCAL_ADDR_WIDTH{1'b0}};
end
end
end
assign int_interruptable_error_detected = (int_sbe_detected & ~cfg_mask_sbe_intr) | (int_dbe_detected & ~cfg_mask_dbe_intr) | (int_corr_dropped_detected & ~cfg_mask_corr_dropped_intr);
assign int_be_detected = int_sbe_detected | int_dbe_detected;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_interrupt <= 1'b0;
end
else
begin
if (cfg_enable_ecc && cfg_enable_intr)
begin
if (int_interruptable_error_detected)
int_ecc_interrupt <= 1'b1;
else if (cfg_clr_intr)
int_ecc_interrupt <= 1'b0;
end
else
begin
int_ecc_interrupt <= 1'b0;
end
end
end
endmodule | module alt_mem_ddrx_ecc_encoder_decoder_wrapper #
( parameter
CFG_LOCAL_DATA_WIDTH = 80,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_DWIDTH_RATIO = 2,
CFG_MEM_IF_DQ_WIDTH = 40,
CFG_MEM_IF_DQS_WIDTH = 5,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_MULTIPLES = 1,
CFG_ECC_ENC_REG = 0,
CFG_ECC_DEC_REG = 0,
CFG_ECC_RDATA_REG = 0,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_GEN_SBE = 1,
CFG_PORT_WIDTH_GEN_DBE = 1,
CFG_PORT_WIDTH_ENABLE_INTR = 1,
CFG_PORT_WIDTH_MASK_SBE_INTR = 1,
CFG_PORT_WIDTH_MASK_DBE_INTR = 1,
CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1,
CFG_PORT_WIDTH_CLR_INTR = 1,
STS_PORT_WIDTH_SBE_ERROR = 1,
STS_PORT_WIDTH_DBE_ERROR = 1,
STS_PORT_WIDTH_SBE_COUNT = 8,
STS_PORT_WIDTH_DBE_COUNT = 8,
STS_PORT_WIDTH_CORR_DROP_ERROR = 1,
STS_PORT_WIDTH_CORR_DROP_COUNT = 8
)
(
ctl_clk,
ctl_reset_n,
cfg_interface_width,
cfg_enable_ecc,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
wdatap_dm,
wdatap_data,
wdatap_rmw_partial_data,
wdatap_rmw_correct_data,
wdatap_rmw_partial,
wdatap_rmw_correct,
wdatap_ecc_code,
wdatap_ecc_code_overwrite,
rdatap_rcvd_addr,
rdatap_rcvd_cmd,
rdatap_rcvd_corr_dropped,
afi_rdata,
afi_rdata_valid,
ecc_rdata,
ecc_rdata_valid,
ecc_dm,
ecc_wdata,
ecc_sbe,
ecc_dbe,
ecc_code,
ecc_interrupt,
sts_sbe_error,
sts_dbe_error,
sts_sbe_count,
sts_dbe_count,
sts_err_addr,
sts_corr_dropped,
sts_corr_dropped_count,
sts_corr_dropped_addr
); |
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_ECC_DATA_WIDTH = CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO;
localparam CFG_LOCAL_DM_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_ECC_DM_WIDTH = CFG_ECC_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_LOCAL_DATA_PER_WORD_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_LOCAL_DM_PER_WORD_WIDTH = CFG_LOCAL_DM_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_ECC_DATA_PER_WORD_WIDTH = CFG_ECC_DATA_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_ECC_DM_PER_WORD_WIDTH = CFG_ECC_DM_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_MMR_DRAM_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_LOCAL_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_DRAM_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2;
localparam CFG_MMR_LOCAL_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2;
localparam CFG_ENCODER_DATA_WIDTH = CFG_ECC_DATA_PER_WORD_WIDTH;
localparam CFG_DECODER_DATA_WIDTH = CFG_ECC_DATA_PER_WORD_WIDTH;
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] cfg_gen_sbe;
input [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] cfg_gen_dbe;
input [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] cfg_enable_intr;
input [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] cfg_mask_sbe_intr;
input [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] cfg_mask_dbe_intr;
input [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] cfg_mask_corr_dropped_intr;
input [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] cfg_clr_intr;
input [CFG_LOCAL_DM_WIDTH - 1 : 0] wdatap_dm;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_data;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_partial_data;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_correct_data;
input wdatap_rmw_partial;
input wdatap_rmw_correct;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
input [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] rdatap_rcvd_addr;
input rdatap_rcvd_cmd;
input rdatap_rcvd_corr_dropped;
input [CFG_ECC_DATA_WIDTH - 1 : 0] afi_rdata;
input [CFG_DWIDTH_RATIO / 2 - 1 : 0] afi_rdata_valid;
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
output ecc_rdata_valid;
output [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
output [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
output [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
output [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
output ecc_interrupt;
output [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
output [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
output [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
output [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
output [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
output [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
reg ecc_rdata_valid;
reg [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
reg [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
reg [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
reg [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
reg ecc_interrupt;
reg [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
reg [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
reg [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
reg [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
reg [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
reg [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
reg [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
reg [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_local_data_width;
reg [CFG_MMR_DRAM_DM_WIDTH - 1 : 0] cfg_dram_dm_width;
reg [CFG_MMR_LOCAL_DM_WIDTH - 1 : 0] cfg_local_dm_width;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_data;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_rmw_partial_data;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_rmw_correct_data;
reg int_encoder_input_rmw_partial;
reg int_encoder_input_rmw_correct;
reg wdatap_rmw_partial_r;
reg wdatap_rmw_correct_r;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg int_decoder_input_data_valid;
reg [CFG_ECC_MULTIPLES - 1 : 0] int_sbe;
reg [CFG_ECC_MULTIPLES - 1 : 0] int_dbe;
reg [CFG_ECC_DM_WIDTH - 1 : 0] int_encoder_output_dm;
reg [CFG_ECC_DM_WIDTH - 1 : 0] int_encoder_output_dm_r;
wire [CFG_ECC_MULTIPLES - 1 : 0] int_decoder_output_data_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_encoder_output_data;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_encoder_output_data_r;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_decoder_output_data;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] int_ecc_code;
reg [1 : 0] inject_data_error;
reg int_sbe_detected;
reg int_dbe_detected;
wire int_be_detected;
reg int_sbe_store;
reg int_dbe_store;
reg int_sbe_valid;
reg int_dbe_valid;
reg int_sbe_valid_r;
reg int_dbe_valid_r;
reg int_ecc_interrupt;
wire int_interruptable_error_detected;
reg [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] int_sbe_error;
reg [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] int_dbe_error;
reg [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] int_sbe_count;
reg [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] int_dbe_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_err_addr ;
reg [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] int_corr_dropped;
reg [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] int_corr_dropped_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_corr_dropped_addr ;
reg int_corr_dropped_detected;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_data_width <= 0;
end
else
begin
cfg_dram_data_width <= cfg_interface_width;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_local_data_width <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
cfg_local_data_width <= cfg_interface_width - CFG_ECC_CODE_WIDTH;
end
else
begin
cfg_local_data_width <= cfg_interface_width;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_dm_width <= 0;
end
else
begin
cfg_dram_dm_width <= cfg_dram_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_local_dm_width <= 0;
end
else
begin
cfg_local_dm_width <= cfg_local_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_rmw_partial_r <= 1'b0;
wdatap_rmw_correct_r <= 1'b0;
end
else
begin
wdatap_rmw_partial_r <= wdatap_rmw_partial;
wdatap_rmw_correct_r <= wdatap_rmw_correct;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_encoder_output_data_r <= 0;
int_encoder_output_dm_r <= 0;
end
else
begin
int_encoder_output_data_r <= int_encoder_output_data;
int_encoder_output_dm_r <= int_encoder_output_dm;
end
end
always @ (*)
begin
int_encoder_input_data = wdatap_data;
int_encoder_input_rmw_partial_data = wdatap_rmw_partial_data;
int_encoder_input_rmw_correct_data = wdatap_rmw_correct_data;
if (CFG_ECC_ENC_REG)
begin
int_encoder_input_rmw_partial = wdatap_rmw_partial_r;
int_encoder_input_rmw_correct = wdatap_rmw_correct_r;
end
else
begin
int_encoder_input_rmw_partial = wdatap_rmw_partial;
int_encoder_input_rmw_correct = wdatap_rmw_correct;
end
end
generate
genvar i_drate;
for (i_drate = 0;i_drate < CFG_ECC_MULTIPLES;i_drate = i_drate + 1)
begin : encoder_input_dm_mux_per_dm_drate
wire [CFG_LOCAL_DM_PER_WORD_WIDTH-1:0] int_encoder_input_dm = wdatap_dm [(i_drate + 1) * CFG_LOCAL_DM_PER_WORD_WIDTH - 1 : i_drate * CFG_LOCAL_DM_PER_WORD_WIDTH];
wire int_encoder_input_dm_all_zeros = ~(|int_encoder_input_dm);
always @ (*)
begin
if (cfg_enable_ecc)
begin
if (int_encoder_input_dm_all_zeros)
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b0}},int_encoder_input_dm};
end
else
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b1}},int_encoder_input_dm};
end
end
else
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b0}},int_encoder_input_dm};
end
end
end
endgenerate
always @ (*)
begin
int_decoder_input_data = afi_rdata;
end
always @ (*)
begin
int_decoder_input_data_valid = afi_rdata_valid [0];
end
always @ (*)
begin
ecc_wdata = int_encoder_output_data;
end
always @ (*)
begin
if (CFG_ECC_ENC_REG)
begin
ecc_dm = int_encoder_output_dm_r;
end
else
begin
ecc_dm = int_encoder_output_dm;
end
end
always @ (*)
begin
ecc_rdata = int_decoder_output_data;
end
always @ (*)
begin
ecc_rdata_valid = |int_decoder_output_data_valid;
end
always @ (*)
begin
if (cfg_enable_ecc)
ecc_sbe = int_sbe;
else
ecc_sbe = 0;
end
always @ (*)
begin
if (cfg_enable_ecc)
ecc_dbe = int_dbe;
else
ecc_dbe = 0;
end
always @ (*)
begin
if (cfg_enable_ecc)
ecc_code = int_ecc_code;
else
ecc_code = 0;
end
always @ (*)
begin
ecc_interrupt = int_ecc_interrupt;
end
always @ (*)
begin
sts_sbe_error = int_sbe_error;
end
always @ (*)
begin
sts_dbe_error = int_dbe_error;
end
always @ (*)
begin
sts_sbe_count = int_sbe_count;
end
always @ (*)
begin
sts_dbe_count = int_dbe_count;
end
always @ (*)
begin
sts_err_addr = int_err_addr;
end
always @ (*)
begin
sts_corr_dropped = int_corr_dropped;
end
always @ (*)
begin
sts_corr_dropped_count = int_corr_dropped_count;
end
always @ (*)
begin
sts_corr_dropped_addr = int_corr_dropped_addr;
end
generate
genvar m_drate;
for (m_drate = 0;m_drate < CFG_ECC_MULTIPLES;m_drate = m_drate + 1)
begin : encoder_inst_per_drate
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_rmw_partial_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_rmw_partial_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_rmw_correct_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_rmw_correct_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code = wdatap_ecc_code [(m_drate + 1) * CFG_ECC_CODE_WIDTH - 1 : m_drate * CFG_ECC_CODE_WIDTH];
wire input_ecc_code_overwrite = wdatap_ecc_code_overwrite [m_drate];
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_data;
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_rmw_partial_data;
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_rmw_correct_data;
always @ (*)
begin
if (int_encoder_input_rmw_partial)
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_rmw_partial_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_rmw_partial_data [1 : 0] ^ inject_data_error [1 : 0])};
end
else if (int_encoder_input_rmw_correct)
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_rmw_correct_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_rmw_correct_data [1 : 0] ^ inject_data_error [1 : 0])};
end
else
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_data [1 : 0] ^ inject_data_error [1 : 0])};
end
end
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (1'b0 ),
.output_data (output_data )
);
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
rmw_partial_encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_rmw_partial_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (1'b0 ),
.output_data (output_rmw_partial_data )
);
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
rmw_correct_encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_rmw_correct_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (input_ecc_code_overwrite ),
.output_data (output_rmw_correct_data )
);
end
endgenerate
generate
genvar n_drate;
for (n_drate = 0;n_drate < CFG_ECC_MULTIPLES;n_drate = n_drate + 1)
begin : decoder_inst_per_drate
wire err_corrected;
wire err_detected;
wire err_fatal;
wire [CFG_DECODER_DATA_WIDTH - 1 : 0] input_data = {{CFG_DECODER_DATA_WIDTH - CFG_ECC_DATA_PER_WORD_WIDTH{1'b0}}, int_decoder_input_data [(n_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : n_drate * CFG_ECC_DATA_PER_WORD_WIDTH]};
wire input_data_valid = int_decoder_input_data_valid;
wire [CFG_DECODER_DATA_WIDTH - 1 : 0] output_data;
wire output_data_valid;
wire [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
assign int_decoder_output_data [(n_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : n_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH] = output_data [CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : 0];
assign int_ecc_code [(n_drate + 1) * CFG_ECC_CODE_WIDTH - 1 : n_drate * CFG_ECC_CODE_WIDTH ] = output_ecc_code;
assign int_decoder_output_data_valid [n_drate] = output_data_valid;
alt_mem_ddrx_ecc_decoder #
(
.CFG_DATA_WIDTH (CFG_DECODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_DEC_REG (CFG_ECC_DEC_REG ),
.CFG_ECC_RDATA_REG (CFG_ECC_RDATA_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
decoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_data ),
.input_data_valid (input_data_valid ),
.output_data (output_data ),
.output_data_valid (output_data_valid ),
.output_ecc_code (output_ecc_code ),
.err_corrected (err_corrected ),
.err_detected (err_detected ),
.err_fatal (err_fatal )
);
always @ (*)
begin
if (err_detected)
begin
if (err_corrected)
begin
int_sbe [n_drate] = 1'b1;
int_dbe [n_drate] = 1'b0;
end
else if (err_fatal)
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b1;
end
else
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b0;
end
end
else
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b0;
end
end
end
endgenerate
always @ (*)
begin
int_sbe_valid = |int_sbe & ecc_rdata_valid;
int_dbe_valid = |int_dbe & ecc_rdata_valid;
int_sbe_detected = ( int_sbe_store | int_sbe_valid_r ) & rdatap_rcvd_cmd;
int_dbe_detected = ( int_dbe_store | int_dbe_valid_r ) & rdatap_rcvd_cmd;
int_corr_dropped_detected = rdatap_rcvd_corr_dropped;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_sbe_valid_r <= 0;
int_dbe_valid_r <= 0;
int_sbe_store <= 0;
int_dbe_store <= 0;
end
else
begin
int_sbe_valid_r <= int_sbe_valid;
int_dbe_valid_r <= int_dbe_valid;
int_sbe_store <= (int_sbe_store | int_sbe_valid_r) & ~rdatap_rcvd_cmd;
int_dbe_store <= (int_dbe_store | int_dbe_valid_r) & ~rdatap_rcvd_cmd;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
inject_data_error <= 0;
end
else
begin
if (cfg_gen_dbe)
inject_data_error <= 2'b11;
else if (cfg_gen_sbe)
inject_data_error <= 2'b01;
else
inject_data_error <= 2'b00;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_sbe_error <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_sbe_detected)
int_sbe_error <= 1'b1;
else if (cfg_clr_intr)
int_sbe_error <= 1'b0;
end
else
begin
int_sbe_error <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_sbe_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_sbe_detected)
int_sbe_count <= 1;
else
int_sbe_count <= 0;
else if (int_sbe_detected)
int_sbe_count <= int_sbe_count + 1'b1;
end
else
begin
int_sbe_count <= {STS_PORT_WIDTH_SBE_COUNT{1'b0}};
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dbe_error <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_dbe_detected)
int_dbe_error <= 1'b1;
else if (cfg_clr_intr)
int_dbe_error <= 1'b0;
end
else
begin
int_dbe_error <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dbe_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_dbe_detected)
int_dbe_count <= 1;
else
int_dbe_count <= 0;
else if (int_dbe_detected)
int_dbe_count <= int_dbe_count + 1'b1;
end
else
begin
int_dbe_count <= {STS_PORT_WIDTH_DBE_COUNT{1'b0}};
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_err_addr <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_be_detected)
int_err_addr <= rdatap_rcvd_addr;
else if (cfg_clr_intr)
int_err_addr <= 0;
end
else
begin
int_err_addr <= {CFG_LOCAL_ADDR_WIDTH{1'b0}};
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_corr_dropped_detected)
int_corr_dropped <= 1'b1;
else if (cfg_clr_intr)
int_corr_dropped <= 1'b0;
end
else
begin
int_corr_dropped <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_corr_dropped_detected)
int_corr_dropped_count <= 1;
else
int_corr_dropped_count <= 0;
else if (int_corr_dropped_detected)
int_corr_dropped_count <= int_corr_dropped_count + 1'b1;
end
else
begin
int_corr_dropped_count <= {STS_PORT_WIDTH_CORR_DROP_COUNT{1'b0}};
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped_addr <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_corr_dropped_detected)
int_corr_dropped_addr <= rdatap_rcvd_addr;
else if (cfg_clr_intr)
int_corr_dropped_addr <= 0;
end
else
begin
int_corr_dropped_addr <= {CFG_LOCAL_ADDR_WIDTH{1'b0}};
end
end
end
assign int_interruptable_error_detected = (int_sbe_detected & ~cfg_mask_sbe_intr) | (int_dbe_detected & ~cfg_mask_dbe_intr) | (int_corr_dropped_detected & ~cfg_mask_corr_dropped_intr);
assign int_be_detected = int_sbe_detected | int_dbe_detected;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_interrupt <= 1'b0;
end
else
begin
if (cfg_enable_ecc && cfg_enable_intr)
begin
if (int_interruptable_error_detected)
int_ecc_interrupt <= 1'b1;
else if (cfg_clr_intr)
int_ecc_interrupt <= 1'b0;
end
else
begin
int_ecc_interrupt <= 1'b0;
end
end
end
endmodule | 25 |
4,924 | data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_list.v | 1,122,957 | alt_mem_ddrx_list.v | v | 236 | 108 | [] | [] | [] | null | line:228: before: "integer" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_list.v:99: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n : ... In instance alt_mem_ddrx_list\n list [i] <= i;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_list.v:135: Operator EQ expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 3 bits.\n : ... In instance alt_mem_ddrx_list\n if (i == list [1])\n ^~\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_list.v:168: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'list_put_entry_id\' generates 3 bits.\n : ... In instance alt_mem_ddrx_list\n if (i == list_put_entry_id)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_list.v:199: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'list_put_entry_id\' generates 3 bits.\n : ... In instance alt_mem_ddrx_list\n if (i == list_put_entry_id)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_list.v:210: Operator EQ expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 3 bits.\n : ... In instance alt_mem_ddrx_list\n if (i == list [1])\n ^~\n%Error: Exiting due to 5 warning(s)\n' | 3,343 | module | module alt_mem_ddrx_list
# (
parameter
CTL_LIST_WIDTH = 3,
CTL_LIST_DEPTH = 8,
CTL_LIST_INIT_VALUE_TYPE = "INCR",
CTL_LIST_INIT_VALID = "VALID"
)
(
ctl_clk,
ctl_reset_n,
list_get_entry_valid,
list_get_entry_ready,
list_get_entry_id,
list_get_entry_id_vector,
list_put_entry_valid,
list_put_entry_ready,
list_put_entry_id
);
input ctl_clk;
input ctl_reset_n;
input list_get_entry_ready;
output list_get_entry_valid;
output [CTL_LIST_WIDTH-1:0] list_get_entry_id;
output [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
output list_put_entry_ready;
input list_put_entry_valid;
input [CTL_LIST_WIDTH-1:0] list_put_entry_id;
reg list_get_entry_valid;
wire list_get_entry_ready;
reg [CTL_LIST_WIDTH-1:0] list_get_entry_id;
reg [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
wire list_put_entry_valid;
reg list_put_entry_ready;
wire [CTL_LIST_WIDTH-1:0] list_put_entry_id;
reg [CTL_LIST_WIDTH-1:0] list [CTL_LIST_DEPTH-1:0];
reg list_v [CTL_LIST_DEPTH-1:0];
reg [CTL_LIST_DEPTH-1:0] list_vector;
wire list_get = list_get_entry_valid & list_get_entry_ready;
wire list_put = list_put_entry_valid & list_put_entry_ready;
always @ (*)
begin
list_get_entry_valid = list_v[0];
list_get_entry_id = list[0];
list_get_entry_id_vector = list_vector;
list_put_entry_ready = ~list_v[CTL_LIST_DEPTH-1];
end
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if (CTL_LIST_INIT_VALUE_TYPE == "INCR")
begin
list [i] <= i;
end
else
begin
list [i] <= {CTL_LIST_WIDTH{1'b0}};
end
if (CTL_LIST_INIT_VALID == "VALID")
begin
list_v [i] <= 1'b1;
end
else
begin
list_v [i] <= 1'b0;
end
end
list_vector <= {CTL_LIST_DEPTH{1'b0}};
end
else
begin
if (list_get)
begin
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
list_v [i-1] <= list_v [i];
list [i-1] <= list [i];
end
list_v [CTL_LIST_DEPTH-1] <= 0;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
if (list_put)
begin
if (~list_get)
begin
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if ( list_v[i-1] & ~list_v[i])
begin
list_v [i] <= 1'b1;
list [i] <= list_put_entry_id;
end
end
if (~list_v[0])
begin
list_v [0] <= 1'b1;
list [0] <= list_put_entry_id;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
else
begin
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if (list_v[i-1] & ~list_v[i])
begin
list_v [i-1] <= 1'b1;
list [i-1] <= list_put_entry_id;
end
end
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (list_v[0] & ~list_v[1])
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
else
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
end
end
end
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule | module alt_mem_ddrx_list
# (
parameter
CTL_LIST_WIDTH = 3,
CTL_LIST_DEPTH = 8,
CTL_LIST_INIT_VALUE_TYPE = "INCR",
CTL_LIST_INIT_VALID = "VALID"
)
(
ctl_clk,
ctl_reset_n,
list_get_entry_valid,
list_get_entry_ready,
list_get_entry_id,
list_get_entry_id_vector,
list_put_entry_valid,
list_put_entry_ready,
list_put_entry_id
); |
input ctl_clk;
input ctl_reset_n;
input list_get_entry_ready;
output list_get_entry_valid;
output [CTL_LIST_WIDTH-1:0] list_get_entry_id;
output [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
output list_put_entry_ready;
input list_put_entry_valid;
input [CTL_LIST_WIDTH-1:0] list_put_entry_id;
reg list_get_entry_valid;
wire list_get_entry_ready;
reg [CTL_LIST_WIDTH-1:0] list_get_entry_id;
reg [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
wire list_put_entry_valid;
reg list_put_entry_ready;
wire [CTL_LIST_WIDTH-1:0] list_put_entry_id;
reg [CTL_LIST_WIDTH-1:0] list [CTL_LIST_DEPTH-1:0];
reg list_v [CTL_LIST_DEPTH-1:0];
reg [CTL_LIST_DEPTH-1:0] list_vector;
wire list_get = list_get_entry_valid & list_get_entry_ready;
wire list_put = list_put_entry_valid & list_put_entry_ready;
always @ (*)
begin
list_get_entry_valid = list_v[0];
list_get_entry_id = list[0];
list_get_entry_id_vector = list_vector;
list_put_entry_ready = ~list_v[CTL_LIST_DEPTH-1];
end
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if (CTL_LIST_INIT_VALUE_TYPE == "INCR")
begin
list [i] <= i;
end
else
begin
list [i] <= {CTL_LIST_WIDTH{1'b0}};
end
if (CTL_LIST_INIT_VALID == "VALID")
begin
list_v [i] <= 1'b1;
end
else
begin
list_v [i] <= 1'b0;
end
end
list_vector <= {CTL_LIST_DEPTH{1'b0}};
end
else
begin
if (list_get)
begin
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
list_v [i-1] <= list_v [i];
list [i-1] <= list [i];
end
list_v [CTL_LIST_DEPTH-1] <= 0;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
if (list_put)
begin
if (~list_get)
begin
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if ( list_v[i-1] & ~list_v[i])
begin
list_v [i] <= 1'b1;
list [i] <= list_put_entry_id;
end
end
if (~list_v[0])
begin
list_v [0] <= 1'b1;
list [0] <= list_put_entry_id;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
else
begin
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if (list_v[i-1] & ~list_v[i])
begin
list_v [i-1] <= 1'b1;
list [i-1] <= list_put_entry_id;
end
end
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (list_v[0] & ~list_v[1])
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
else
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
end
end
end
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule | 25 |
4,925 | data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_list.v | 1,122,957 | alt_mem_ddrx_list.v | v | 236 | 108 | [] | [] | [] | null | line:228: before: "integer" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_list.v:99: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n : ... In instance alt_mem_ddrx_list\n list [i] <= i;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_list.v:135: Operator EQ expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 3 bits.\n : ... In instance alt_mem_ddrx_list\n if (i == list [1])\n ^~\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_list.v:168: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'list_put_entry_id\' generates 3 bits.\n : ... In instance alt_mem_ddrx_list\n if (i == list_put_entry_id)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_list.v:199: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'list_put_entry_id\' generates 3 bits.\n : ... In instance alt_mem_ddrx_list\n if (i == list_put_entry_id)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_list.v:210: Operator EQ expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 3 bits.\n : ... In instance alt_mem_ddrx_list\n if (i == list [1])\n ^~\n%Error: Exiting due to 5 warning(s)\n' | 3,343 | function | function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction | function integer two_pow_N; |
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction | 25 |
4,927 | data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_mm_st_converter.v | 1,122,957 | alt_mem_ddrx_mm_st_converter.v | v | 194 | 124 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/1122957/coregen/ddr3_s4_amphy/alt_mem_ddrx_mm_st_converter.v:163: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'itf_rd_data_error\' generates 1 bits.\n : ... In instance alt_mem_ddrx_mm_st_converter\n assign local_rdata_error = itf_rd_data_error;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 3,345 | module | module alt_mem_ddrx_mm_st_converter # (
parameter
AVL_SIZE_WIDTH = 3,
AVL_ADDR_WIDTH = 25,
AVL_DATA_WIDTH = 32,
LOCAL_ID_WIDTH = 8,
CFG_DWIDTH_RATIO = 4
)
(
ctl_clk,
ctl_reset_n,
ctl_half_clk,
ctl_half_clk_reset_n,
avl_ready,
avl_read_req,
avl_write_req,
avl_size,
avl_burstbegin,
avl_addr,
avl_rdata_valid,
avl_rdata,
avl_wdata,
avl_be,
local_rdata_error,
local_multicast,
local_autopch_req,
local_priority,
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id
);
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output avl_ready;
input avl_read_req;
input avl_write_req;
input [AVL_SIZE_WIDTH-1:0] avl_size;
input avl_burstbegin;
input [AVL_ADDR_WIDTH-1:0] avl_addr;
output avl_rdata_valid;
output [3:0] local_rdata_error;
output [AVL_DATA_WIDTH-1:0] avl_rdata;
input [AVL_DATA_WIDTH-1:0] avl_wdata;
input [AVL_DATA_WIDTH/8-1:0] avl_be;
input local_multicast;
input local_autopch_req;
input local_priority;
input itf_cmd_ready;
output itf_cmd_valid;
output itf_cmd;
output [AVL_ADDR_WIDTH-1:0] itf_cmd_address;
output [AVL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
output [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
output itf_cmd_priority;
output itf_cmd_autopercharge;
output itf_cmd_multicast;
input itf_wr_data_ready;
output itf_wr_data_valid;
output [AVL_DATA_WIDTH-1:0] itf_wr_data;
output [AVL_DATA_WIDTH/8-1:0] itf_wr_data_byte_en;
output itf_wr_data_begin;
output itf_wr_data_last;
output [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
output itf_rd_data_ready;
input itf_rd_data_valid;
input [AVL_DATA_WIDTH-1:0] itf_rd_data;
input itf_rd_data_error;
input itf_rd_data_begin;
input itf_rd_data_last;
input [LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
reg [AVL_SIZE_WIDTH-1:0] burst_count;
wire int_ready;
wire itf_cmd;
wire itf_wr_if_ready;
reg data_pass;
reg [AVL_SIZE_WIDTH-1:0] burst_counter;
assign itf_cmd_valid = avl_read_req | itf_wr_if_ready;
assign itf_wr_if_ready = itf_wr_data_ready & avl_write_req & ~data_pass;
assign avl_ready = int_ready;
assign itf_rd_data_ready = 1'b1;
assign itf_cmd_address = avl_addr ;
assign itf_cmd_burstlen = avl_size ;
assign itf_cmd_autopercharge = local_autopch_req ;
assign itf_cmd_priority = local_priority ;
assign itf_cmd_multicast = local_multicast ;
assign itf_cmd = avl_write_req;
assign itf_wr_data_valid = (data_pass) ? avl_write_req : itf_cmd_ready & avl_write_req;
assign itf_wr_data = avl_wdata ;
assign itf_wr_data_byte_en = avl_be ;
assign avl_rdata_valid = itf_rd_data_valid;
assign avl_rdata = itf_rd_data;
assign local_rdata_error = itf_rd_data_error;
assign int_ready = (data_pass) ? itf_wr_data_ready : ((itf_cmd) ? (itf_wr_data_ready & itf_cmd_ready) : itf_cmd_ready);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
burst_counter <= 0;
else
begin
if (itf_wr_if_ready && avl_size > 1 && itf_cmd_ready)
burst_counter <= avl_size - 1;
else if (avl_write_req && itf_wr_data_ready)
burst_counter <= burst_counter - 1;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
data_pass <= 0;
else
begin
if (itf_wr_if_ready && avl_size > 1 && itf_cmd_ready)
data_pass <= 1;
else if (burst_counter == 1 && avl_write_req && itf_wr_data_ready)
data_pass <= 0;
end
end
endmodule | module alt_mem_ddrx_mm_st_converter # (
parameter
AVL_SIZE_WIDTH = 3,
AVL_ADDR_WIDTH = 25,
AVL_DATA_WIDTH = 32,
LOCAL_ID_WIDTH = 8,
CFG_DWIDTH_RATIO = 4
)
(
ctl_clk,
ctl_reset_n,
ctl_half_clk,
ctl_half_clk_reset_n,
avl_ready,
avl_read_req,
avl_write_req,
avl_size,
avl_burstbegin,
avl_addr,
avl_rdata_valid,
avl_rdata,
avl_wdata,
avl_be,
local_rdata_error,
local_multicast,
local_autopch_req,
local_priority,
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id
); |
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output avl_ready;
input avl_read_req;
input avl_write_req;
input [AVL_SIZE_WIDTH-1:0] avl_size;
input avl_burstbegin;
input [AVL_ADDR_WIDTH-1:0] avl_addr;
output avl_rdata_valid;
output [3:0] local_rdata_error;
output [AVL_DATA_WIDTH-1:0] avl_rdata;
input [AVL_DATA_WIDTH-1:0] avl_wdata;
input [AVL_DATA_WIDTH/8-1:0] avl_be;
input local_multicast;
input local_autopch_req;
input local_priority;
input itf_cmd_ready;
output itf_cmd_valid;
output itf_cmd;
output [AVL_ADDR_WIDTH-1:0] itf_cmd_address;
output [AVL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
output [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
output itf_cmd_priority;
output itf_cmd_autopercharge;
output itf_cmd_multicast;
input itf_wr_data_ready;
output itf_wr_data_valid;
output [AVL_DATA_WIDTH-1:0] itf_wr_data;
output [AVL_DATA_WIDTH/8-1:0] itf_wr_data_byte_en;
output itf_wr_data_begin;
output itf_wr_data_last;
output [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
output itf_rd_data_ready;
input itf_rd_data_valid;
input [AVL_DATA_WIDTH-1:0] itf_rd_data;
input itf_rd_data_error;
input itf_rd_data_begin;
input itf_rd_data_last;
input [LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
reg [AVL_SIZE_WIDTH-1:0] burst_count;
wire int_ready;
wire itf_cmd;
wire itf_wr_if_ready;
reg data_pass;
reg [AVL_SIZE_WIDTH-1:0] burst_counter;
assign itf_cmd_valid = avl_read_req | itf_wr_if_ready;
assign itf_wr_if_ready = itf_wr_data_ready & avl_write_req & ~data_pass;
assign avl_ready = int_ready;
assign itf_rd_data_ready = 1'b1;
assign itf_cmd_address = avl_addr ;
assign itf_cmd_burstlen = avl_size ;
assign itf_cmd_autopercharge = local_autopch_req ;
assign itf_cmd_priority = local_priority ;
assign itf_cmd_multicast = local_multicast ;
assign itf_cmd = avl_write_req;
assign itf_wr_data_valid = (data_pass) ? avl_write_req : itf_cmd_ready & avl_write_req;
assign itf_wr_data = avl_wdata ;
assign itf_wr_data_byte_en = avl_be ;
assign avl_rdata_valid = itf_rd_data_valid;
assign avl_rdata = itf_rd_data;
assign local_rdata_error = itf_rd_data_error;
assign int_ready = (data_pass) ? itf_wr_data_ready : ((itf_cmd) ? (itf_wr_data_ready & itf_cmd_ready) : itf_cmd_ready);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
burst_counter <= 0;
else
begin
if (itf_wr_if_ready && avl_size > 1 && itf_cmd_ready)
burst_counter <= avl_size - 1;
else if (avl_write_req && itf_wr_data_ready)
burst_counter <= burst_counter - 1;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
data_pass <= 0;
else
begin
if (itf_wr_if_ready && avl_size > 1 && itf_cmd_ready)
data_pass <= 1;
else if (burst_counter == 1 && avl_write_req && itf_wr_data_ready)
data_pass <= 0;
end
end
endmodule | 25 |
4,929 | data/full_repos/permissive/1122957/coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/simulation/ddr3_s4_uniphy_example_sim_tb.v | 1,122,957 | ddr3_s4_uniphy_example_sim_tb.v | v | 34 | 40 | [] | [] | [] | [(5, 32)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/1122957/coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/simulation/ddr3_s4_uniphy_example_sim_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\nalways #(10000/2) clk <= ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/1122957/coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/simulation/ddr3_s4_uniphy_example_sim_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #(50000) reset_n <= 1;\n ^\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/simulation/ddr3_s4_uniphy_example_sim_tb.v:10: Cannot find file containing module: \'ddr3_s4_uniphy_example_sim\'\nddr3_s4_uniphy_example_sim dut (\n^~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/1122957/coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/simulation,data/full_repos/permissive/1122957/ddr3_s4_uniphy_example_sim\n data/full_repos/permissive/1122957/coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/simulation,data/full_repos/permissive/1122957/ddr3_s4_uniphy_example_sim.v\n data/full_repos/permissive/1122957/coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/simulation,data/full_repos/permissive/1122957/ddr3_s4_uniphy_example_sim.sv\n ddr3_s4_uniphy_example_sim\n ddr3_s4_uniphy_example_sim.v\n ddr3_s4_uniphy_example_sim.sv\n obj_dir/ddr3_s4_uniphy_example_sim\n obj_dir/ddr3_s4_uniphy_example_sim.v\n obj_dir/ddr3_s4_uniphy_example_sim.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,641 | module | module ddr3_s4_uniphy_example_sim_tb();
reg clk;
reg reset_n;
ddr3_s4_uniphy_example_sim dut (
.oct_rdn(),
.oct_rup(),
.pll_ref_clk(clk),
.global_reset_n(reset_n),
.soft_reset_n(1'b1)
);
always #(10000/2) clk <= ~clk;
initial
begin
clk <= 1'b0;
reset_n <= 0;
#(50000) reset_n <= 1;
end
endmodule | module ddr3_s4_uniphy_example_sim_tb(); |
reg clk;
reg reset_n;
ddr3_s4_uniphy_example_sim dut (
.oct_rdn(),
.oct_rup(),
.pll_ref_clk(clk),
.global_reset_n(reset_n),
.soft_reset_n(1'b1)
);
always #(10000/2) clk <= ~clk;
initial
begin
clk <= 1'b0;
reset_n <= 0;
#(50000) reset_n <= 1;
end
endmodule | 25 |
4,938 | data/full_repos/permissive/1122957/coregen/dram_v6_mig37/mig_37/example_design/sim/ddr3_model_parameters.vh | 1,122,957 | ddr3_model_parameters.vh | vh | 1,457 | 156 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n' | 4,189 | function | function valid_cl;
input [3:0] cl;
input [3:0] cwl;
case ({cwl, cl})
`ifdef sg094E
{4'd5, 4'd5 },
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd10},
{4'd8, 4'd11},
{4'd8, 4'd12},
{4'd9, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14},
{4'd10, 4'd13},
{4'd10, 4'd14}: valid_cl = 1;
`else `ifdef sg094
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd10},
{4'd8, 4'd11},
{4'd8, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14},
{4'd10, 4'd14}: valid_cl = 1;
`else `ifdef sg107F
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd11},
{4'd8, 4'd12},
{4'd9, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14}: valid_cl = 1;
`else `ifdef sg107E
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10},
{4'd8, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14}: valid_cl = 1;
`else `ifdef sg107
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10},
{4'd8, 4'd12},
{4'd9, 4'd14}: valid_cl = 1;
`else `ifdef sg125F
{4'd5, 4'd5 },
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd9 },
{4'd8, 4'd10},
{4'd8, 4'd11}: valid_cl = 1;
`else `ifdef sg125E
{4'd5, 4'd5 },
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd10},
{4'd8, 4'd11}: valid_cl = 1;
`else `ifdef sg125
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd11}: valid_cl = 1;
`else `ifdef sg15E
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg15
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg187E
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg187
{4'd5, 4'd6 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg25E
{4'd5, 4'd5 },
{4'd5, 4'd6 }: valid_cl = 1;
`else `ifdef sg25
{4'd5, 4'd6 }: valid_cl = 1;
`endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
default : valid_cl = 0;
endcase
endfunction | function valid_cl; |
input [3:0] cl;
input [3:0] cwl;
case ({cwl, cl})
`ifdef sg094E
{4'd5, 4'd5 },
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd10},
{4'd8, 4'd11},
{4'd8, 4'd12},
{4'd9, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14},
{4'd10, 4'd13},
{4'd10, 4'd14}: valid_cl = 1;
`else `ifdef sg094
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd10},
{4'd8, 4'd11},
{4'd8, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14},
{4'd10, 4'd14}: valid_cl = 1;
`else `ifdef sg107F
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd11},
{4'd8, 4'd12},
{4'd9, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14}: valid_cl = 1;
`else `ifdef sg107E
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10},
{4'd8, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14}: valid_cl = 1;
`else `ifdef sg107
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10},
{4'd8, 4'd12},
{4'd9, 4'd14}: valid_cl = 1;
`else `ifdef sg125F
{4'd5, 4'd5 },
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd9 },
{4'd8, 4'd10},
{4'd8, 4'd11}: valid_cl = 1;
`else `ifdef sg125E
{4'd5, 4'd5 },
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd10},
{4'd8, 4'd11}: valid_cl = 1;
`else `ifdef sg125
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd11}: valid_cl = 1;
`else `ifdef sg15E
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg15
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg187E
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg187
{4'd5, 4'd6 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg25E
{4'd5, 4'd5 },
{4'd5, 4'd6 }: valid_cl = 1;
`else `ifdef sg25
{4'd5, 4'd6 }: valid_cl = 1;
`endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
default : valid_cl = 0;
endcase
endfunction | 25 |
4,939 | data/full_repos/permissive/1122957/coregen/dram_v6_mig37/mig_37/example_design/sim/ddr3_model_parameters.vh | 1,122,957 | ddr3_model_parameters.vh | vh | 1,457 | 156 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n' | 4,189 | function | function [3:0] min_cwl;
input period;
real period;
min_cwl = (period >= 2500.0) ? 5:
(period >= 1875.0) ? 6:
(period >= 1500.0) ? 7:
(period >= 1250.0) ? 8:
(period >= 15e3/14) ? 9:
10;
endfunction | function [3:0] min_cwl; |
input period;
real period;
min_cwl = (period >= 2500.0) ? 5:
(period >= 1875.0) ? 6:
(period >= 1500.0) ? 7:
(period >= 1250.0) ? 8:
(period >= 15e3/14) ? 9:
10;
endfunction | 25 |
4,940 | data/full_repos/permissive/1122957/coregen/dram_v6_mig37/mig_37/example_design/sim/ddr3_model_parameters.vh | 1,122,957 | ddr3_model_parameters.vh | vh | 1,457 | 156 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n' | 4,189 | function | function [3:0] min_cl;
input period;
real period;
reg [3:0] cwl;
reg [3:0] cl;
begin
cwl = min_cwl(period);
for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin
if (valid_cl(cl, cwl)) begin
min_cl = cl;
end
end
end
endfunction | function [3:0] min_cl; |
input period;
real period;
reg [3:0] cwl;
reg [3:0] cl;
begin
cwl = min_cwl(period);
for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin
if (valid_cl(cl, cwl)) begin
min_cl = cl;
end
end
end
endfunction | 25 |
4,941 | data/full_repos/permissive/1122957/coregen/dram_v6_mig37/mig_37/example_design/sim/ddr3_model_parameters.vh | 1,122,957 | ddr3_model_parameters.vh | vh | 1,457 | 156 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n' | 4,189 | function | function valid_cl;
input [3:0] cl;
input [3:0] cwl;
case ({cwl, cl})
`ifdef sg15E
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg15
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg187E
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg187
{4'd5, 4'd6 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg25E
{4'd5, 4'd5 },
{4'd5, 4'd6 }: valid_cl = 1;
`else `ifdef sg25
{4'd5, 4'd6 }: valid_cl = 1;
`endif `endif `endif `endif `endif `endif
default : valid_cl = 0;
endcase
endfunction | function valid_cl; |
input [3:0] cl;
input [3:0] cwl;
case ({cwl, cl})
`ifdef sg15E
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg15
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg187E
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg187
{4'd5, 4'd6 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg25E
{4'd5, 4'd5 },
{4'd5, 4'd6 }: valid_cl = 1;
`else `ifdef sg25
{4'd5, 4'd6 }: valid_cl = 1;
`endif `endif `endif `endif `endif `endif
default : valid_cl = 0;
endcase
endfunction | 25 |
4,942 | data/full_repos/permissive/1122957/coregen/dram_v6_mig37/mig_37/example_design/sim/ddr3_model_parameters.vh | 1,122,957 | ddr3_model_parameters.vh | vh | 1,457 | 156 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n' | 4,189 | function | function [3:0] min_cwl;
input period;
real period;
min_cwl = (period >= 2500.0) ? 5:
(period >= 1875.0) ? 6:
(period >= 1500.0) ? 7:
8;
endfunction | function [3:0] min_cwl; |
input period;
real period;
min_cwl = (period >= 2500.0) ? 5:
(period >= 1875.0) ? 6:
(period >= 1500.0) ? 7:
8;
endfunction | 25 |
4,945 | data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_block_bb.v | 1,122,957 | v6_emac_v1_3_block_bb.v | v | 152 | 80 | [] | [] | [] | [(40, 151)] | null | data/verilator_xmls/69d52cbe-4fed-4fff-9d9a-edb5fc8a9443.xml | null | 5,106 | module | module v6_emac_v1_3_block
(
TX_CLK_OUT,
TX_CLK,
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
PHY_RX_CLK,
GTX_CLK,
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
RESET
);
output TX_CLK_OUT;
input TX_CLK;
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
input PHY_RX_CLK;
input GTX_CLK;
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
input RESET;
endmodule | module v6_emac_v1_3_block
(
TX_CLK_OUT,
TX_CLK,
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
PHY_RX_CLK,
GTX_CLK,
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
RESET
); |
output TX_CLK_OUT;
input TX_CLK;
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
input PHY_RX_CLK;
input GTX_CLK;
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
input RESET;
endmodule | 25 |
4,946 | data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v | 1,122,957 | v6_emac_v1_3_patch.v | v | 935 | 456 | [] | [] | [] | [(39, 291), (327, 638), (655, 934)] | null | null | 1: b"%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:709: Cannot find file containing module: 'ODDR'\n ODDR gmii_tx_clk_oddr (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/1122957/coregen/temac_v6,data/full_repos/permissive/1122957/ODDR\n data/full_repos/permissive/1122957/coregen/temac_v6,data/full_repos/permissive/1122957/ODDR.v\n data/full_repos/permissive/1122957/coregen/temac_v6,data/full_repos/permissive/1122957/ODDR.sv\n ODDR\n ODDR.v\n ODDR.sv\n obj_dir/ODDR\n obj_dir/ODDR.v\n obj_dir/ODDR.sv\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:743: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:760: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:777: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:794: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:811: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:828: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:845: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:862: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:879: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:896: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:459: Cannot find file containing module: 'TEMAC_SINGLE'\n TEMAC_SINGLE #(\n ^~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n" | 5,107 | module | module v6_emac_v1_3_block
(
TX_CLK_OUT,
TX_CLK,
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
PHY_RX_CLK,
GTX_CLK,
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
RESET
);
output TX_CLK_OUT;
input TX_CLK;
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
input PHY_RX_CLK;
input GTX_CLK;
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
input RESET;
wire reset_ibuf_i;
wire reset_i;
wire rx_client_clk_out_i;
wire rx_client_clk_in_i;
wire tx_client_clk_out_i;
wire tx_client_clk_in_i;
wire tx_gmii_mii_clk_out_i;
wire tx_gmii_mii_clk_in_i;
wire gmii_tx_en_i;
wire gmii_tx_er_i;
wire [7:0] gmii_txd_i;
wire gmii_rx_dv_r;
wire gmii_rx_er_r;
wire [7:0] gmii_rxd_r;
wire gmii_rx_clk_i;
wire gtx_clk_ibufg_i;
assign reset_ibuf_i = RESET;
assign reset_i = reset_ibuf_i;
gmii_if gmii (
.RESET (reset_i),
.GMII_TXD (GMII_TXD),
.GMII_TX_EN (GMII_TX_EN),
.GMII_TX_ER (GMII_TX_ER),
.GMII_TX_CLK (GMII_TX_CLK),
.GMII_RXD (GMII_RXD),
.GMII_RX_DV (GMII_RX_DV),
.GMII_RX_ER (GMII_RX_ER),
.TXD_FROM_MAC (gmii_txd_i),
.TX_EN_FROM_MAC (gmii_tx_en_i),
.TX_ER_FROM_MAC (gmii_tx_er_i),
.TX_CLK (tx_gmii_mii_clk_in_i),
.RXD_TO_MAC (gmii_rxd_r),
.RX_DV_TO_MAC (gmii_rx_dv_r),
.RX_ER_TO_MAC (gmii_rx_er_r),
.RX_CLK (GMII_RX_CLK)
);
assign gtx_clk_ibufg_i = GTX_CLK;
assign tx_gmii_mii_clk_in_i = TX_CLK;
assign gmii_rx_clk_i = PHY_RX_CLK;
assign tx_client_clk_in_i = TX_CLK;
assign rx_client_clk_in_i = gmii_rx_clk_i;
assign TX_CLK_OUT = tx_gmii_mii_clk_out_i;
v6_emac_v1_3 v6_emac_v1_3_inst
(
.EMACCLIENTRXCLIENTCLKOUT (rx_client_clk_out_i),
.CLIENTEMACRXCLIENTCLKIN (rx_client_clk_in_i),
.EMACCLIENTRXD (EMACCLIENTRXD),
.EMACCLIENTRXDVLD (EMACCLIENTRXDVLD),
.EMACCLIENTRXDVLDMSW (),
.EMACCLIENTRXGOODFRAME (EMACCLIENTRXGOODFRAME),
.EMACCLIENTRXBADFRAME (EMACCLIENTRXBADFRAME),
.EMACCLIENTRXFRAMEDROP (EMACCLIENTRXFRAMEDROP),
.EMACCLIENTRXSTATS (EMACCLIENTRXSTATS),
.EMACCLIENTRXSTATSVLD (EMACCLIENTRXSTATSVLD),
.EMACCLIENTRXSTATSBYTEVLD (EMACCLIENTRXSTATSBYTEVLD),
.EMACCLIENTTXCLIENTCLKOUT (tx_client_clk_out_i),
.CLIENTEMACTXCLIENTCLKIN (tx_client_clk_in_i),
.CLIENTEMACTXD (CLIENTEMACTXD),
.CLIENTEMACTXDVLD (CLIENTEMACTXDVLD),
.CLIENTEMACTXDVLDMSW (1'b0),
.EMACCLIENTTXACK (EMACCLIENTTXACK),
.CLIENTEMACTXFIRSTBYTE (CLIENTEMACTXFIRSTBYTE),
.CLIENTEMACTXUNDERRUN (CLIENTEMACTXUNDERRUN),
.EMACCLIENTTXCOLLISION (EMACCLIENTTXCOLLISION),
.EMACCLIENTTXRETRANSMIT (EMACCLIENTTXRETRANSMIT),
.CLIENTEMACTXIFGDELAY (CLIENTEMACTXIFGDELAY),
.EMACCLIENTTXSTATS (EMACCLIENTTXSTATS),
.EMACCLIENTTXSTATSVLD (EMACCLIENTTXSTATSVLD),
.EMACCLIENTTXSTATSBYTEVLD (EMACCLIENTTXSTATSBYTEVLD),
.CLIENTEMACPAUSEREQ (CLIENTEMACPAUSEREQ),
.CLIENTEMACPAUSEVAL (CLIENTEMACPAUSEVAL),
.GTX_CLK (gtx_clk_ibufg_i),
.EMACPHYTXGMIIMIICLKOUT (tx_gmii_mii_clk_out_i),
.PHYEMACTXGMIIMIICLKIN (tx_gmii_mii_clk_in_i),
.GMII_TXD (gmii_txd_i),
.GMII_TX_EN (gmii_tx_en_i),
.GMII_TX_ER (gmii_tx_er_i),
.GMII_RXD (gmii_rxd_r),
.GMII_RX_DV (gmii_rx_dv_r),
.GMII_RX_ER (gmii_rx_er_r),
.GMII_RX_CLK (gmii_rx_clk_i),
.MMCM_LOCKED (1'b1),
.RESET (reset_i)
);
endmodule | module v6_emac_v1_3_block
(
TX_CLK_OUT,
TX_CLK,
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
PHY_RX_CLK,
GTX_CLK,
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
RESET
); |
output TX_CLK_OUT;
input TX_CLK;
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
input PHY_RX_CLK;
input GTX_CLK;
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
input RESET;
wire reset_ibuf_i;
wire reset_i;
wire rx_client_clk_out_i;
wire rx_client_clk_in_i;
wire tx_client_clk_out_i;
wire tx_client_clk_in_i;
wire tx_gmii_mii_clk_out_i;
wire tx_gmii_mii_clk_in_i;
wire gmii_tx_en_i;
wire gmii_tx_er_i;
wire [7:0] gmii_txd_i;
wire gmii_rx_dv_r;
wire gmii_rx_er_r;
wire [7:0] gmii_rxd_r;
wire gmii_rx_clk_i;
wire gtx_clk_ibufg_i;
assign reset_ibuf_i = RESET;
assign reset_i = reset_ibuf_i;
gmii_if gmii (
.RESET (reset_i),
.GMII_TXD (GMII_TXD),
.GMII_TX_EN (GMII_TX_EN),
.GMII_TX_ER (GMII_TX_ER),
.GMII_TX_CLK (GMII_TX_CLK),
.GMII_RXD (GMII_RXD),
.GMII_RX_DV (GMII_RX_DV),
.GMII_RX_ER (GMII_RX_ER),
.TXD_FROM_MAC (gmii_txd_i),
.TX_EN_FROM_MAC (gmii_tx_en_i),
.TX_ER_FROM_MAC (gmii_tx_er_i),
.TX_CLK (tx_gmii_mii_clk_in_i),
.RXD_TO_MAC (gmii_rxd_r),
.RX_DV_TO_MAC (gmii_rx_dv_r),
.RX_ER_TO_MAC (gmii_rx_er_r),
.RX_CLK (GMII_RX_CLK)
);
assign gtx_clk_ibufg_i = GTX_CLK;
assign tx_gmii_mii_clk_in_i = TX_CLK;
assign gmii_rx_clk_i = PHY_RX_CLK;
assign tx_client_clk_in_i = TX_CLK;
assign rx_client_clk_in_i = gmii_rx_clk_i;
assign TX_CLK_OUT = tx_gmii_mii_clk_out_i;
v6_emac_v1_3 v6_emac_v1_3_inst
(
.EMACCLIENTRXCLIENTCLKOUT (rx_client_clk_out_i),
.CLIENTEMACRXCLIENTCLKIN (rx_client_clk_in_i),
.EMACCLIENTRXD (EMACCLIENTRXD),
.EMACCLIENTRXDVLD (EMACCLIENTRXDVLD),
.EMACCLIENTRXDVLDMSW (),
.EMACCLIENTRXGOODFRAME (EMACCLIENTRXGOODFRAME),
.EMACCLIENTRXBADFRAME (EMACCLIENTRXBADFRAME),
.EMACCLIENTRXFRAMEDROP (EMACCLIENTRXFRAMEDROP),
.EMACCLIENTRXSTATS (EMACCLIENTRXSTATS),
.EMACCLIENTRXSTATSVLD (EMACCLIENTRXSTATSVLD),
.EMACCLIENTRXSTATSBYTEVLD (EMACCLIENTRXSTATSBYTEVLD),
.EMACCLIENTTXCLIENTCLKOUT (tx_client_clk_out_i),
.CLIENTEMACTXCLIENTCLKIN (tx_client_clk_in_i),
.CLIENTEMACTXD (CLIENTEMACTXD),
.CLIENTEMACTXDVLD (CLIENTEMACTXDVLD),
.CLIENTEMACTXDVLDMSW (1'b0),
.EMACCLIENTTXACK (EMACCLIENTTXACK),
.CLIENTEMACTXFIRSTBYTE (CLIENTEMACTXFIRSTBYTE),
.CLIENTEMACTXUNDERRUN (CLIENTEMACTXUNDERRUN),
.EMACCLIENTTXCOLLISION (EMACCLIENTTXCOLLISION),
.EMACCLIENTTXRETRANSMIT (EMACCLIENTTXRETRANSMIT),
.CLIENTEMACTXIFGDELAY (CLIENTEMACTXIFGDELAY),
.EMACCLIENTTXSTATS (EMACCLIENTTXSTATS),
.EMACCLIENTTXSTATSVLD (EMACCLIENTTXSTATSVLD),
.EMACCLIENTTXSTATSBYTEVLD (EMACCLIENTTXSTATSBYTEVLD),
.CLIENTEMACPAUSEREQ (CLIENTEMACPAUSEREQ),
.CLIENTEMACPAUSEVAL (CLIENTEMACPAUSEVAL),
.GTX_CLK (gtx_clk_ibufg_i),
.EMACPHYTXGMIIMIICLKOUT (tx_gmii_mii_clk_out_i),
.PHYEMACTXGMIIMIICLKIN (tx_gmii_mii_clk_in_i),
.GMII_TXD (gmii_txd_i),
.GMII_TX_EN (gmii_tx_en_i),
.GMII_TX_ER (gmii_tx_er_i),
.GMII_RXD (gmii_rxd_r),
.GMII_RX_DV (gmii_rx_dv_r),
.GMII_RX_ER (gmii_rx_er_r),
.GMII_RX_CLK (gmii_rx_clk_i),
.MMCM_LOCKED (1'b1),
.RESET (reset_i)
);
endmodule | 25 |
4,947 | data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v | 1,122,957 | v6_emac_v1_3_patch.v | v | 935 | 456 | [] | [] | [] | [(39, 291), (327, 638), (655, 934)] | null | null | 1: b"%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:709: Cannot find file containing module: 'ODDR'\n ODDR gmii_tx_clk_oddr (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/1122957/coregen/temac_v6,data/full_repos/permissive/1122957/ODDR\n data/full_repos/permissive/1122957/coregen/temac_v6,data/full_repos/permissive/1122957/ODDR.v\n data/full_repos/permissive/1122957/coregen/temac_v6,data/full_repos/permissive/1122957/ODDR.sv\n ODDR\n ODDR.v\n ODDR.sv\n obj_dir/ODDR\n obj_dir/ODDR.v\n obj_dir/ODDR.sv\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:743: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:760: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:777: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:794: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:811: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:828: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:845: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:862: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:879: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:896: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:459: Cannot find file containing module: 'TEMAC_SINGLE'\n TEMAC_SINGLE #(\n ^~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n" | 5,107 | module | module v6_emac_v1_3
(
EMACCLIENTRXCLIENTCLKOUT,
CLIENTEMACRXCLIENTCLKIN,
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXDVLDMSW,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
EMACCLIENTTXCLIENTCLKOUT,
CLIENTEMACTXCLIENTCLKIN,
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
CLIENTEMACTXDVLDMSW,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
GTX_CLK,
PHYEMACTXGMIIMIICLKIN,
EMACPHYTXGMIIMIICLKOUT,
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
MMCM_LOCKED,
RESET
);
output EMACCLIENTRXCLIENTCLKOUT;
input CLIENTEMACRXCLIENTCLKIN;
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXDVLDMSW;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
output EMACCLIENTTXCLIENTCLKOUT;
input CLIENTEMACTXCLIENTCLKIN;
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
input CLIENTEMACTXDVLDMSW;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
input GTX_CLK;
output EMACPHYTXGMIIMIICLKOUT;
input PHYEMACTXGMIIMIICLKIN;
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
input MMCM_LOCKED;
input RESET;
wire [15:0] client_rx_data_i;
wire [15:0] client_tx_data_i;
assign EMACCLIENTRXD = client_rx_data_i[7:0];
assign #4000 client_tx_data_i = {8'b00000000, CLIENTEMACTXD};
TEMAC_SINGLE #(
.EMAC_PHYINITAUTONEG_ENABLE ("FALSE"),
.EMAC_PHYISOLATE ("FALSE"),
.EMAC_PHYLOOPBACKMSB ("FALSE"),
.EMAC_PHYPOWERDOWN ("FALSE"),
.EMAC_PHYRESET ("TRUE"),
.EMAC_GTLOOPBACK ("FALSE"),
.EMAC_UNIDIRECTION_ENABLE ("FALSE"),
.EMAC_LINKTIMERVAL (9'h000),
.EMAC_MDIO_IGNORE_PHYADZERO ("FALSE"),
.EMAC_MDIO_ENABLE ("FALSE"),
.EMAC_SPEED_LSB ("FALSE"),
.EMAC_SPEED_MSB ("TRUE"),
.EMAC_USECLKEN ("FALSE"),
.EMAC_BYTEPHY ("FALSE"),
.EMAC_RGMII_ENABLE ("FALSE"),
.EMAC_SGMII_ENABLE ("FALSE"),
.EMAC_1000BASEX_ENABLE ("FALSE"),
.EMAC_HOST_ENABLE ("FALSE"),
.EMAC_TX16BITCLIENT_ENABLE ("FALSE"),
.EMAC_RX16BITCLIENT_ENABLE ("FALSE"),
.EMAC_ADDRFILTER_ENABLE ("FALSE"),
.EMAC_LTCHECK_DISABLE ("FALSE"),
.EMAC_CTRLLENCHECK_DISABLE ("FALSE"),
.EMAC_RXFLOWCTRL_ENABLE ("FALSE"),
.EMAC_TXFLOWCTRL_ENABLE ("FALSE"),
.EMAC_TXRESET ("FALSE"),
.EMAC_TXJUMBOFRAME_ENABLE ("FALSE"),
.EMAC_TXINBANDFCS_ENABLE ("FALSE"),
.EMAC_TX_ENABLE ("TRUE"),
.EMAC_TXVLAN_ENABLE ("FALSE"),
.EMAC_TXHALFDUPLEX ("FALSE"),
.EMAC_TXIFGADJUST_ENABLE ("FALSE"),
.EMAC_RXRESET ("FALSE"),
.EMAC_RXJUMBOFRAME_ENABLE ("FALSE"),
.EMAC_RXINBANDFCS_ENABLE ("FALSE"),
.EMAC_RX_ENABLE ("TRUE"),
.EMAC_RXVLAN_ENABLE ("FALSE"),
.EMAC_RXHALFDUPLEX ("FALSE"),
.EMAC_PAUSEADDR (48'hFFEEDDCCBBAA),
.EMAC_UNICASTADDR (48'h000000000000),
.EMAC_DCRBASEADDR (8'h00)
)
v6_emac
(
.RESET (RESET),
.EMACCLIENTRXCLIENTCLKOUT (EMACCLIENTRXCLIENTCLKOUT),
.CLIENTEMACRXCLIENTCLKIN (CLIENTEMACRXCLIENTCLKIN),
.EMACCLIENTRXD (client_rx_data_i),
.EMACCLIENTRXDVLD (EMACCLIENTRXDVLD),
.EMACCLIENTRXDVLDMSW (EMACCLIENTRXDVLDMSW),
.EMACCLIENTRXGOODFRAME (EMACCLIENTRXGOODFRAME),
.EMACCLIENTRXBADFRAME (EMACCLIENTRXBADFRAME),
.EMACCLIENTRXFRAMEDROP (EMACCLIENTRXFRAMEDROP),
.EMACCLIENTRXSTATS (EMACCLIENTRXSTATS),
.EMACCLIENTRXSTATSVLD (EMACCLIENTRXSTATSVLD),
.EMACCLIENTRXSTATSBYTEVLD (EMACCLIENTRXSTATSBYTEVLD),
.EMACCLIENTTXCLIENTCLKOUT (EMACCLIENTTXCLIENTCLKOUT),
.CLIENTEMACTXCLIENTCLKIN (CLIENTEMACTXCLIENTCLKIN),
.CLIENTEMACTXD (client_tx_data_i),
.CLIENTEMACTXDVLD (CLIENTEMACTXDVLD),
.CLIENTEMACTXDVLDMSW (CLIENTEMACTXDVLDMSW),
.EMACCLIENTTXACK (EMACCLIENTTXACK),
.CLIENTEMACTXFIRSTBYTE (CLIENTEMACTXFIRSTBYTE),
.CLIENTEMACTXUNDERRUN (CLIENTEMACTXUNDERRUN),
.EMACCLIENTTXCOLLISION (EMACCLIENTTXCOLLISION),
.EMACCLIENTTXRETRANSMIT (EMACCLIENTTXRETRANSMIT),
.CLIENTEMACTXIFGDELAY (CLIENTEMACTXIFGDELAY),
.EMACCLIENTTXSTATS (EMACCLIENTTXSTATS),
.EMACCLIENTTXSTATSVLD (EMACCLIENTTXSTATSVLD),
.EMACCLIENTTXSTATSBYTEVLD (EMACCLIENTTXSTATSBYTEVLD),
.CLIENTEMACPAUSEREQ (CLIENTEMACPAUSEREQ),
.CLIENTEMACPAUSEVAL (CLIENTEMACPAUSEVAL),
.PHYEMACGTXCLK (GTX_CLK),
.EMACPHYTXGMIIMIICLKOUT (EMACPHYTXGMIIMIICLKOUT),
.PHYEMACTXGMIIMIICLKIN (PHYEMACTXGMIIMIICLKIN),
.PHYEMACRXCLK (GMII_RX_CLK),
.PHYEMACRXD (GMII_RXD),
.PHYEMACRXDV (GMII_RX_DV),
.PHYEMACRXER (GMII_RX_ER),
.EMACPHYTXCLK (),
.EMACPHYTXD (GMII_TXD),
.EMACPHYTXEN (GMII_TX_EN),
.EMACPHYTXER (GMII_TX_ER),
.PHYEMACMIITXCLK (1'b0),
.PHYEMACCOL (1'b0),
.PHYEMACCRS (1'b0),
.CLIENTEMACDCMLOCKED (MMCM_LOCKED),
.EMACCLIENTANINTERRUPT (),
.PHYEMACSIGNALDET (1'b0),
.PHYEMACPHYAD (5'b00000),
.EMACPHYENCOMMAALIGN (),
.EMACPHYLOOPBACKMSB (),
.EMACPHYMGTRXRESET (),
.EMACPHYMGTTXRESET (),
.EMACPHYPOWERDOWN (),
.EMACPHYSYNCACQSTATUS (),
.PHYEMACRXCLKCORCNT (3'b000),
.PHYEMACRXBUFSTATUS (2'b00),
.PHYEMACRXCHARISCOMMA (1'b0),
.PHYEMACRXCHARISK (1'b0),
.PHYEMACRXDISPERR (1'b0),
.PHYEMACRXNOTINTABLE (1'b0),
.PHYEMACRXRUNDISP (1'b0),
.PHYEMACTXBUFERR (1'b0),
.EMACPHYTXCHARDISPMODE (),
.EMACPHYTXCHARDISPVAL (),
.EMACPHYTXCHARISK (),
.EMACPHYMCLKOUT (),
.PHYEMACMCLKIN (1'b0),
.PHYEMACMDIN (1'b1),
.EMACPHYMDOUT (),
.EMACPHYMDTRI (),
.EMACSPEEDIS10100 (),
.HOSTCLK (1'b0),
.HOSTOPCODE (2'b00),
.HOSTREQ (1'b0),
.HOSTMIIMSEL (1'b0),
.HOSTADDR (10'b0000000000),
.HOSTWRDATA (32'h00000000),
.HOSTMIIMRDY (),
.HOSTRDDATA (),
.DCREMACCLK (1'b0),
.DCREMACABUS (10'h000),
.DCREMACREAD (1'b0),
.DCREMACWRITE (1'b0),
.DCREMACDBUS (32'h00000000),
.EMACDCRACK (),
.EMACDCRDBUS (),
.DCREMACENABLE (1'b0),
.DCRHOSTDONEIR ()
);
endmodule | module v6_emac_v1_3
(
EMACCLIENTRXCLIENTCLKOUT,
CLIENTEMACRXCLIENTCLKIN,
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXDVLDMSW,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
EMACCLIENTTXCLIENTCLKOUT,
CLIENTEMACTXCLIENTCLKIN,
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
CLIENTEMACTXDVLDMSW,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
GTX_CLK,
PHYEMACTXGMIIMIICLKIN,
EMACPHYTXGMIIMIICLKOUT,
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
MMCM_LOCKED,
RESET
); |
output EMACCLIENTRXCLIENTCLKOUT;
input CLIENTEMACRXCLIENTCLKIN;
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXDVLDMSW;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
output EMACCLIENTTXCLIENTCLKOUT;
input CLIENTEMACTXCLIENTCLKIN;
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
input CLIENTEMACTXDVLDMSW;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
input GTX_CLK;
output EMACPHYTXGMIIMIICLKOUT;
input PHYEMACTXGMIIMIICLKIN;
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
input MMCM_LOCKED;
input RESET;
wire [15:0] client_rx_data_i;
wire [15:0] client_tx_data_i;
assign EMACCLIENTRXD = client_rx_data_i[7:0];
assign #4000 client_tx_data_i = {8'b00000000, CLIENTEMACTXD};
TEMAC_SINGLE #(
.EMAC_PHYINITAUTONEG_ENABLE ("FALSE"),
.EMAC_PHYISOLATE ("FALSE"),
.EMAC_PHYLOOPBACKMSB ("FALSE"),
.EMAC_PHYPOWERDOWN ("FALSE"),
.EMAC_PHYRESET ("TRUE"),
.EMAC_GTLOOPBACK ("FALSE"),
.EMAC_UNIDIRECTION_ENABLE ("FALSE"),
.EMAC_LINKTIMERVAL (9'h000),
.EMAC_MDIO_IGNORE_PHYADZERO ("FALSE"),
.EMAC_MDIO_ENABLE ("FALSE"),
.EMAC_SPEED_LSB ("FALSE"),
.EMAC_SPEED_MSB ("TRUE"),
.EMAC_USECLKEN ("FALSE"),
.EMAC_BYTEPHY ("FALSE"),
.EMAC_RGMII_ENABLE ("FALSE"),
.EMAC_SGMII_ENABLE ("FALSE"),
.EMAC_1000BASEX_ENABLE ("FALSE"),
.EMAC_HOST_ENABLE ("FALSE"),
.EMAC_TX16BITCLIENT_ENABLE ("FALSE"),
.EMAC_RX16BITCLIENT_ENABLE ("FALSE"),
.EMAC_ADDRFILTER_ENABLE ("FALSE"),
.EMAC_LTCHECK_DISABLE ("FALSE"),
.EMAC_CTRLLENCHECK_DISABLE ("FALSE"),
.EMAC_RXFLOWCTRL_ENABLE ("FALSE"),
.EMAC_TXFLOWCTRL_ENABLE ("FALSE"),
.EMAC_TXRESET ("FALSE"),
.EMAC_TXJUMBOFRAME_ENABLE ("FALSE"),
.EMAC_TXINBANDFCS_ENABLE ("FALSE"),
.EMAC_TX_ENABLE ("TRUE"),
.EMAC_TXVLAN_ENABLE ("FALSE"),
.EMAC_TXHALFDUPLEX ("FALSE"),
.EMAC_TXIFGADJUST_ENABLE ("FALSE"),
.EMAC_RXRESET ("FALSE"),
.EMAC_RXJUMBOFRAME_ENABLE ("FALSE"),
.EMAC_RXINBANDFCS_ENABLE ("FALSE"),
.EMAC_RX_ENABLE ("TRUE"),
.EMAC_RXVLAN_ENABLE ("FALSE"),
.EMAC_RXHALFDUPLEX ("FALSE"),
.EMAC_PAUSEADDR (48'hFFEEDDCCBBAA),
.EMAC_UNICASTADDR (48'h000000000000),
.EMAC_DCRBASEADDR (8'h00)
)
v6_emac
(
.RESET (RESET),
.EMACCLIENTRXCLIENTCLKOUT (EMACCLIENTRXCLIENTCLKOUT),
.CLIENTEMACRXCLIENTCLKIN (CLIENTEMACRXCLIENTCLKIN),
.EMACCLIENTRXD (client_rx_data_i),
.EMACCLIENTRXDVLD (EMACCLIENTRXDVLD),
.EMACCLIENTRXDVLDMSW (EMACCLIENTRXDVLDMSW),
.EMACCLIENTRXGOODFRAME (EMACCLIENTRXGOODFRAME),
.EMACCLIENTRXBADFRAME (EMACCLIENTRXBADFRAME),
.EMACCLIENTRXFRAMEDROP (EMACCLIENTRXFRAMEDROP),
.EMACCLIENTRXSTATS (EMACCLIENTRXSTATS),
.EMACCLIENTRXSTATSVLD (EMACCLIENTRXSTATSVLD),
.EMACCLIENTRXSTATSBYTEVLD (EMACCLIENTRXSTATSBYTEVLD),
.EMACCLIENTTXCLIENTCLKOUT (EMACCLIENTTXCLIENTCLKOUT),
.CLIENTEMACTXCLIENTCLKIN (CLIENTEMACTXCLIENTCLKIN),
.CLIENTEMACTXD (client_tx_data_i),
.CLIENTEMACTXDVLD (CLIENTEMACTXDVLD),
.CLIENTEMACTXDVLDMSW (CLIENTEMACTXDVLDMSW),
.EMACCLIENTTXACK (EMACCLIENTTXACK),
.CLIENTEMACTXFIRSTBYTE (CLIENTEMACTXFIRSTBYTE),
.CLIENTEMACTXUNDERRUN (CLIENTEMACTXUNDERRUN),
.EMACCLIENTTXCOLLISION (EMACCLIENTTXCOLLISION),
.EMACCLIENTTXRETRANSMIT (EMACCLIENTTXRETRANSMIT),
.CLIENTEMACTXIFGDELAY (CLIENTEMACTXIFGDELAY),
.EMACCLIENTTXSTATS (EMACCLIENTTXSTATS),
.EMACCLIENTTXSTATSVLD (EMACCLIENTTXSTATSVLD),
.EMACCLIENTTXSTATSBYTEVLD (EMACCLIENTTXSTATSBYTEVLD),
.CLIENTEMACPAUSEREQ (CLIENTEMACPAUSEREQ),
.CLIENTEMACPAUSEVAL (CLIENTEMACPAUSEVAL),
.PHYEMACGTXCLK (GTX_CLK),
.EMACPHYTXGMIIMIICLKOUT (EMACPHYTXGMIIMIICLKOUT),
.PHYEMACTXGMIIMIICLKIN (PHYEMACTXGMIIMIICLKIN),
.PHYEMACRXCLK (GMII_RX_CLK),
.PHYEMACRXD (GMII_RXD),
.PHYEMACRXDV (GMII_RX_DV),
.PHYEMACRXER (GMII_RX_ER),
.EMACPHYTXCLK (),
.EMACPHYTXD (GMII_TXD),
.EMACPHYTXEN (GMII_TX_EN),
.EMACPHYTXER (GMII_TX_ER),
.PHYEMACMIITXCLK (1'b0),
.PHYEMACCOL (1'b0),
.PHYEMACCRS (1'b0),
.CLIENTEMACDCMLOCKED (MMCM_LOCKED),
.EMACCLIENTANINTERRUPT (),
.PHYEMACSIGNALDET (1'b0),
.PHYEMACPHYAD (5'b00000),
.EMACPHYENCOMMAALIGN (),
.EMACPHYLOOPBACKMSB (),
.EMACPHYMGTRXRESET (),
.EMACPHYMGTTXRESET (),
.EMACPHYPOWERDOWN (),
.EMACPHYSYNCACQSTATUS (),
.PHYEMACRXCLKCORCNT (3'b000),
.PHYEMACRXBUFSTATUS (2'b00),
.PHYEMACRXCHARISCOMMA (1'b0),
.PHYEMACRXCHARISK (1'b0),
.PHYEMACRXDISPERR (1'b0),
.PHYEMACRXNOTINTABLE (1'b0),
.PHYEMACRXRUNDISP (1'b0),
.PHYEMACTXBUFERR (1'b0),
.EMACPHYTXCHARDISPMODE (),
.EMACPHYTXCHARDISPVAL (),
.EMACPHYTXCHARISK (),
.EMACPHYMCLKOUT (),
.PHYEMACMCLKIN (1'b0),
.PHYEMACMDIN (1'b1),
.EMACPHYMDOUT (),
.EMACPHYMDTRI (),
.EMACSPEEDIS10100 (),
.HOSTCLK (1'b0),
.HOSTOPCODE (2'b00),
.HOSTREQ (1'b0),
.HOSTMIIMSEL (1'b0),
.HOSTADDR (10'b0000000000),
.HOSTWRDATA (32'h00000000),
.HOSTMIIMRDY (),
.HOSTRDDATA (),
.DCREMACCLK (1'b0),
.DCREMACABUS (10'h000),
.DCREMACREAD (1'b0),
.DCREMACWRITE (1'b0),
.DCREMACDBUS (32'h00000000),
.EMACDCRACK (),
.EMACDCRDBUS (),
.DCREMACENABLE (1'b0),
.DCRHOSTDONEIR ()
);
endmodule | 25 |
4,948 | data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v | 1,122,957 | v6_emac_v1_3_patch.v | v | 935 | 456 | [] | [] | [] | [(39, 291), (327, 638), (655, 934)] | null | null | 1: b"%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:709: Cannot find file containing module: 'ODDR'\n ODDR gmii_tx_clk_oddr (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/1122957/coregen/temac_v6,data/full_repos/permissive/1122957/ODDR\n data/full_repos/permissive/1122957/coregen/temac_v6,data/full_repos/permissive/1122957/ODDR.v\n data/full_repos/permissive/1122957/coregen/temac_v6,data/full_repos/permissive/1122957/ODDR.sv\n ODDR\n ODDR.v\n ODDR.sv\n obj_dir/ODDR\n obj_dir/ODDR.v\n obj_dir/ODDR.sv\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:743: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:760: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:777: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:794: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:811: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:828: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:845: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:862: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:879: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:896: Cannot find file containing module: 'IODELAY'\n IODELAY #(\n ^~~~~~~\n%Error: data/full_repos/permissive/1122957/coregen/temac_v6/v6_emac_v1_3_patch.v:459: Cannot find file containing module: 'TEMAC_SINGLE'\n TEMAC_SINGLE #(\n ^~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n" | 5,107 | module | module gmii_if (
RESET,
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
TXD_FROM_MAC,
TX_EN_FROM_MAC,
TX_ER_FROM_MAC,
TX_CLK,
RXD_TO_MAC,
RX_DV_TO_MAC,
RX_ER_TO_MAC,
RX_CLK
);
input RESET;
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input [7:0] TXD_FROM_MAC;
input TX_EN_FROM_MAC;
input TX_ER_FROM_MAC;
input TX_CLK;
output [7:0] RXD_TO_MAC;
output RX_DV_TO_MAC;
output RX_ER_TO_MAC;
input RX_CLK;
reg [7:0] RXD_TO_MAC;
reg RX_DV_TO_MAC;
reg RX_ER_TO_MAC;
reg [7:0] GMII_TXD;
reg GMII_TX_EN;
reg GMII_TX_ER;
wire [7:0] GMII_RXD_DLY;
wire GMII_RX_DV_DLY;
wire GMII_RX_ER_DLY;
ODDR gmii_tx_clk_oddr (
.Q (GMII_TX_CLK),
.C (TX_CLK),
.CE (1'b1),
.D1 (1'b0),
.D2 (1'b1),
.R (RESET),
.S (1'b0)
);
always @(posedge TX_CLK, posedge RESET)
begin
if (RESET == 1'b1)
begin
GMII_TX_EN <= 1'b0;
GMII_TX_ER <= 1'b0;
GMII_TXD <= 8'h00;
end
else
begin
GMII_TX_EN <= TX_EN_FROM_MAC;
GMII_TX_ER <= TX_ER_FROM_MAC;
GMII_TXD <= TXD_FROM_MAC;
end
end
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld0 (
.IDATAIN(GMII_RXD[0]),
.DATAOUT(GMII_RXD_DLY[0]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld1 (
.IDATAIN(GMII_RXD[1]),
.DATAOUT(GMII_RXD_DLY[1]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld2 (
.IDATAIN(GMII_RXD[2]),
.DATAOUT(GMII_RXD_DLY[2]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld3 (
.IDATAIN(GMII_RXD[3]),
.DATAOUT(GMII_RXD_DLY[3]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld4 (
.IDATAIN(GMII_RXD[4]),
.DATAOUT(GMII_RXD_DLY[4]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld5 (
.IDATAIN(GMII_RXD[5]),
.DATAOUT(GMII_RXD_DLY[5]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld6 (
.IDATAIN(GMII_RXD[6]),
.DATAOUT(GMII_RXD_DLY[6]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld7 (
.IDATAIN(GMII_RXD[7]),
.DATAOUT(GMII_RXD_DLY[7]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideldv(
.IDATAIN(GMII_RX_DV),
.DATAOUT(GMII_RX_DV_DLY),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideler(
.IDATAIN(GMII_RX_ER),
.DATAOUT(GMII_RX_ER_DLY),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
always @(posedge RX_CLK, posedge RESET)
begin
if (RESET == 1'b1)
begin
RX_DV_TO_MAC <= 1'b0;
RX_ER_TO_MAC <= 1'b0;
RXD_TO_MAC <= 8'h00;
end
else
begin
RX_DV_TO_MAC <= GMII_RX_DV_DLY;
RX_ER_TO_MAC <= GMII_RX_ER_DLY;
RXD_TO_MAC <= GMII_RXD_DLY;
end
end
endmodule | module gmii_if (
RESET,
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
TXD_FROM_MAC,
TX_EN_FROM_MAC,
TX_ER_FROM_MAC,
TX_CLK,
RXD_TO_MAC,
RX_DV_TO_MAC,
RX_ER_TO_MAC,
RX_CLK
); |
input RESET;
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input [7:0] TXD_FROM_MAC;
input TX_EN_FROM_MAC;
input TX_ER_FROM_MAC;
input TX_CLK;
output [7:0] RXD_TO_MAC;
output RX_DV_TO_MAC;
output RX_ER_TO_MAC;
input RX_CLK;
reg [7:0] RXD_TO_MAC;
reg RX_DV_TO_MAC;
reg RX_ER_TO_MAC;
reg [7:0] GMII_TXD;
reg GMII_TX_EN;
reg GMII_TX_ER;
wire [7:0] GMII_RXD_DLY;
wire GMII_RX_DV_DLY;
wire GMII_RX_ER_DLY;
ODDR gmii_tx_clk_oddr (
.Q (GMII_TX_CLK),
.C (TX_CLK),
.CE (1'b1),
.D1 (1'b0),
.D2 (1'b1),
.R (RESET),
.S (1'b0)
);
always @(posedge TX_CLK, posedge RESET)
begin
if (RESET == 1'b1)
begin
GMII_TX_EN <= 1'b0;
GMII_TX_ER <= 1'b0;
GMII_TXD <= 8'h00;
end
else
begin
GMII_TX_EN <= TX_EN_FROM_MAC;
GMII_TX_ER <= TX_ER_FROM_MAC;
GMII_TXD <= TXD_FROM_MAC;
end
end
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld0 (
.IDATAIN(GMII_RXD[0]),
.DATAOUT(GMII_RXD_DLY[0]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld1 (
.IDATAIN(GMII_RXD[1]),
.DATAOUT(GMII_RXD_DLY[1]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld2 (
.IDATAIN(GMII_RXD[2]),
.DATAOUT(GMII_RXD_DLY[2]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld3 (
.IDATAIN(GMII_RXD[3]),
.DATAOUT(GMII_RXD_DLY[3]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld4 (
.IDATAIN(GMII_RXD[4]),
.DATAOUT(GMII_RXD_DLY[4]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld5 (
.IDATAIN(GMII_RXD[5]),
.DATAOUT(GMII_RXD_DLY[5]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld6 (
.IDATAIN(GMII_RXD[6]),
.DATAOUT(GMII_RXD_DLY[6]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld7 (
.IDATAIN(GMII_RXD[7]),
.DATAOUT(GMII_RXD_DLY[7]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideldv(
.IDATAIN(GMII_RX_DV),
.DATAOUT(GMII_RX_DV_DLY),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideler(
.IDATAIN(GMII_RX_ER),
.DATAOUT(GMII_RX_ER_DLY),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
always @(posedge RX_CLK, posedge RESET)
begin
if (RESET == 1'b1)
begin
RX_DV_TO_MAC <= 1'b0;
RX_ER_TO_MAC <= 1'b0;
RXD_TO_MAC <= 8'h00;
end
else
begin
RX_DV_TO_MAC <= GMII_RX_DV_DLY;
RX_ER_TO_MAC <= GMII_RX_ER_DLY;
RXD_TO_MAC <= GMII_RXD_DLY;
end
end
endmodule | 25 |
4,956 | data/full_repos/permissive/1122957/libsrc/hdl/bsv/ResetEither.v | 1,122,957 | ResetEither.v | v | 55 | 122 | [] | [] | [] | [(42, 54)] | null | data/verilator_xmls/4449c480-8939-4109-9081-0f3690153c5a.xml | null | 5,158 | module | module ResetEither(A_RST,
B_RST,
RST_OUT
) ;
input A_RST;
input B_RST;
output RST_OUT;
assign RST_OUT = ((A_RST == `BSV_RESET_VALUE) || (B_RST == `BSV_RESET_VALUE)) ? `BSV_RESET_VALUE : ~ `BSV_RESET_VALUE;
endmodule | module ResetEither(A_RST,
B_RST,
RST_OUT
) ; |
input A_RST;
input B_RST;
output RST_OUT;
assign RST_OUT = ((A_RST == `BSV_RESET_VALUE) || (B_RST == `BSV_RESET_VALUE)) ? `BSV_RESET_VALUE : ~ `BSV_RESET_VALUE;
endmodule | 25 |
4,959 | data/full_repos/permissive/1122957/libsrc/hdl/bsv/bram_patch/BRAM1BE_alt.v | 1,122,957 | BRAM1BE_alt.v | v | 117 | 108 | [] | [] | [] | [(30, 116)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/1122957/libsrc/hdl/bsv/bram_patch/BRAM1BE_alt.v:68: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n : ... In instance BRAM1BE\n RAM[i] = { ((DATA_WIDTH+1)/2) { 2\'b10 } };\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/1122957/libsrc/hdl/bsv/bram_patch/BRAM1BE_alt.v:70: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n : ... In instance BRAM1BE\n ADDR_R = { ((ADDR_WIDTH+1)/2) { 2\'b10 } };\n ^\n%Warning-WIDTH: data/full_repos/permissive/1122957/libsrc/hdl/bsv/bram_patch/BRAM1BE_alt.v:71: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n : ... In instance BRAM1BE\n DO_R = { ((DATA_WIDTH+1)/2) { 2\'b10 } };\n ^\n%Error: Exiting due to 3 warning(s)\n' | 5,171 | module | module BRAM1BE(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter CHUNKSIZE = 1;
parameter WE_WIDTH = 1;
parameter MEMSIZE = 1;
input CLK;
input EN;
input [WE_WIDTH-1:0] WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [ADDR_WIDTH-1:0] ADDR_R;
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DATA;
wire [DATA_WIDTH-1:0] DATAwr;
assign DATAwr = RAM[ADDR] ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
initial
begin : init_block
integer i;
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
ADDR_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } };
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
`endif
`ifdef __ICARUS__
reg [DATA_WIDTH-1:0] MASK, IMASK;
always @(WE or DI or DATAwr) begin : combo1
integer j;
MASK = 0;
IMASK = 0;
for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
if (WE[j]) MASK = (MASK << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
else MASK = (MASK << 8);
end
IMASK = ~MASK;
DATA = (DATAwr & IMASK) | (DI & MASK);
end
`else
always @(WE or DI or DATAwr) begin : combo1
integer j;
for(j = 0; j < WE_WIDTH; j = j + 1) begin
if (WE[j]) DATA[j*CHUNKSIZE +: CHUNKSIZE] = DI[j*CHUNKSIZE +: CHUNKSIZE];
else DATA[j*CHUNKSIZE +: CHUNKSIZE] = DATAwr[j*CHUNKSIZE +: CHUNKSIZE];
end
end
`endif
always @(posedge CLK) begin
if (EN) begin
if (|WE)
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
ADDR_R <= `BSV_ASSIGNMENT_DELAY ADDR;
end
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR_R];
end
assign DO = (PIPELINED) ? DO_R : RAM[ADDR_R];
endmodule | module BRAM1BE(CLK,
EN,
WE,
ADDR,
DI,
DO
); |
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter CHUNKSIZE = 1;
parameter WE_WIDTH = 1;
parameter MEMSIZE = 1;
input CLK;
input EN;
input [WE_WIDTH-1:0] WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [ADDR_WIDTH-1:0] ADDR_R;
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DATA;
wire [DATA_WIDTH-1:0] DATAwr;
assign DATAwr = RAM[ADDR] ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
initial
begin : init_block
integer i;
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
ADDR_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } };
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
`endif
`ifdef __ICARUS__
reg [DATA_WIDTH-1:0] MASK, IMASK;
always @(WE or DI or DATAwr) begin : combo1
integer j;
MASK = 0;
IMASK = 0;
for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
if (WE[j]) MASK = (MASK << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
else MASK = (MASK << 8);
end
IMASK = ~MASK;
DATA = (DATAwr & IMASK) | (DI & MASK);
end
`else
always @(WE or DI or DATAwr) begin : combo1
integer j;
for(j = 0; j < WE_WIDTH; j = j + 1) begin
if (WE[j]) DATA[j*CHUNKSIZE +: CHUNKSIZE] = DI[j*CHUNKSIZE +: CHUNKSIZE];
else DATA[j*CHUNKSIZE +: CHUNKSIZE] = DATAwr[j*CHUNKSIZE +: CHUNKSIZE];
end
end
`endif
always @(posedge CLK) begin
if (EN) begin
if (|WE)
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
ADDR_R <= `BSV_ASSIGNMENT_DELAY ADDR;
end
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR_R];
end
assign DO = (PIPELINED) ? DO_R : RAM[ADDR_R];
endmodule | 25 |
4,960 | data/full_repos/permissive/1122957/libsrc/hdl/mit/timeServer.v | 1,122,957 | timeServer.v | v | 67 | 107 | [] | ['mit license'] | ['all rights reserved'] | [(27, 66)] | null | null | 1: b"%Error: data/full_repos/permissive/1122957/libsrc/hdl/mit/timeServer.v:59: Can't find definition of variable: 'M_AXIS_DEMOD_TDATA_WIDTH'\n : ... Suggested alternative: 'M_AXIS_TIME_TDATA_WIDTH'\n output [M_AXIS_DEMOD_TDATA_WIDTH-1:0] m_axis_time_tdata, \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/1122957/libsrc/hdl/mit/timeServer.v:60: Can't find definition of variable: 'M_AXIS_DEMOD_TUSER_WIDTH'\n : ... Suggested alternative: 'M_AXIS_DEMOD_TDATA_WIDTH'\n output [M_AXIS_DEMOD_TUSER_WIDTH-1:0] m_axis_time_tuser, \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 5,177 | module | module ubbDemodulator #
(
parameter S_AXIS_CONFIG_TDATA_WIDTH = 32,
parameter S_AXIS_RCVR_TDATA_WIDTH = 16,
parameter S_AXIS_RCVR_TUSER_WIDTH = 2,
parameter S_AXIS_NCO_TDATA_WIDTH = 32,
parameter S_AXIS_NCO_TUSER_WIDTH = 2,
parameter M_AXIS_TIME_TDATA_WIDTH = 64,
parameter M_AXIS_TIME_TUSER_WIDTH = 2)
(
input aclk,
input aresetn,
input [S_AXIS_CONFIG_TDATA_WIDTH-1:0] s_axis_config_tdata,
input s_axis_config_tvalid,
output s_axis_config_tready,
input s_axis_config_tlast,
input [S_AXIS_RCVR_TDATA_WIDTH-1:0] s_axis_rcvr_tdata,
input [S_AXIS_RCVR_TUSER_WIDTH-1:0] s_axis_rcvr_tuser,
input s_axis_rcvr_tvalid,
output s_axis_rcvr_tready,
input s_axis_rcvr_tlast,
input [S_AXIS_NCO_TDATA_WIDTH-1:0] s_axis_nco_tdata,
input [S_AXIS_NCO_TUSER_WIDTH-1:0] s_axis_nco_tuser,
input s_axis_nco_tvalid,
output s_axis_nco_tready,
input s_axis_nco_tlast,
output [M_AXIS_DEMOD_TDATA_WIDTH-1:0] m_axis_time_tdata,
output [M_AXIS_DEMOD_TUSER_WIDTH-1:0] m_axis_time_tuser,
output m_axis_time_tvalid,
input m_axis_time_tready,
output m_axis_time_tlast
);
endmodule | module ubbDemodulator #
(
parameter S_AXIS_CONFIG_TDATA_WIDTH = 32,
parameter S_AXIS_RCVR_TDATA_WIDTH = 16,
parameter S_AXIS_RCVR_TUSER_WIDTH = 2,
parameter S_AXIS_NCO_TDATA_WIDTH = 32,
parameter S_AXIS_NCO_TUSER_WIDTH = 2,
parameter M_AXIS_TIME_TDATA_WIDTH = 64,
parameter M_AXIS_TIME_TUSER_WIDTH = 2)
(
input aclk,
input aresetn,
input [S_AXIS_CONFIG_TDATA_WIDTH-1:0] s_axis_config_tdata,
input s_axis_config_tvalid,
output s_axis_config_tready,
input s_axis_config_tlast,
input [S_AXIS_RCVR_TDATA_WIDTH-1:0] s_axis_rcvr_tdata,
input [S_AXIS_RCVR_TUSER_WIDTH-1:0] s_axis_rcvr_tuser,
input s_axis_rcvr_tvalid,
output s_axis_rcvr_tready,
input s_axis_rcvr_tlast,
input [S_AXIS_NCO_TDATA_WIDTH-1:0] s_axis_nco_tdata,
input [S_AXIS_NCO_TUSER_WIDTH-1:0] s_axis_nco_tuser,
input s_axis_nco_tvalid,
output s_axis_nco_tready,
input s_axis_nco_tlast,
output [M_AXIS_DEMOD_TDATA_WIDTH-1:0] m_axis_time_tdata,
output [M_AXIS_DEMOD_TUSER_WIDTH-1:0] m_axis_time_tuser,
output m_axis_time_tvalid,
input m_axis_time_tready,
output m_axis_time_tlast
); |
endmodule | 25 |
4,971 | data/full_repos/permissive/1122957/libsrc/hdl/ocpi/IDELAYCTRL_GRP.v | 1,122,957 | IDELAYCTRL_GRP.v | v | 12 | 57 | [] | [] | [] | [(1, 11)] | null | null | 1: b"%Error: data/full_repos/permissive/1122957/libsrc/hdl/ocpi/IDELAYCTRL_GRP.v:9: Cannot find file containing module: 'IDELAYCTRL'\n IDELAYCTRL idc(.REFCLK(REFCLK), .RST(RST), .RDY(RDY));\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/1122957/libsrc/hdl/ocpi,data/full_repos/permissive/1122957/IDELAYCTRL\n data/full_repos/permissive/1122957/libsrc/hdl/ocpi,data/full_repos/permissive/1122957/IDELAYCTRL.v\n data/full_repos/permissive/1122957/libsrc/hdl/ocpi,data/full_repos/permissive/1122957/IDELAYCTRL.sv\n IDELAYCTRL\n IDELAYCTRL.v\n IDELAYCTRL.sv\n obj_dir/IDELAYCTRL\n obj_dir/IDELAYCTRL.v\n obj_dir/IDELAYCTRL.sv\n%Error: Exiting due to 1 error(s)\n" | 5,214 | module | module IDELAYCTRL_GRP#(
parameter IODELAY_GRP = "IODELAY_XXX")
( input REFCLK,
input RST,
output RDY
);
(* IODELAY_GROUP = IODELAY_GRP *)
IDELAYCTRL idc(.REFCLK(REFCLK), .RST(RST), .RDY(RDY));
endmodule | module IDELAYCTRL_GRP#(
parameter IODELAY_GRP = "IODELAY_XXX")
( input REFCLK,
input RST,
output RDY
); |
(* IODELAY_GROUP = IODELAY_GRP *)
IDELAYCTRL idc(.REFCLK(REFCLK), .RST(RST), .RDY(RDY));
endmodule | 25 |
4,974 | data/full_repos/permissive/1122957/libsrc/hdl/ocpi/opedTop.v | 1,122,957 | opedTop.v | v | 107 | 91 | [] | ['netfpga'] | ['all rights reserved'] | [(7, 106)] | null | null | 1: b"%Error: data/full_repos/permissive/1122957/libsrc/hdl/ocpi/opedTop.v:93: Cannot find file containing module: 'mkOPED'\n mkOPED moped(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/1122957/libsrc/hdl/ocpi,data/full_repos/permissive/1122957/mkOPED\n data/full_repos/permissive/1122957/libsrc/hdl/ocpi,data/full_repos/permissive/1122957/mkOPED.v\n data/full_repos/permissive/1122957/libsrc/hdl/ocpi,data/full_repos/permissive/1122957/mkOPED.sv\n mkOPED\n mkOPED.v\n mkOPED.sv\n obj_dir/mkOPED\n obj_dir/mkOPED.v\n obj_dir/mkOPED.sv\n%Error: Exiting due to 1 error(s)\n" | 5,222 | module | module opedTop(
input wire pcie_clk_p,
input wire pcie_clk_n,
input wire pcie_reset_n,
output wire [7:0] pcie_txp,
output wire [7:0] pcie_txn,
input wire [7:0] pcie_rxp,
input wire [7:0] pcie_rxn,
output wire [31:0] debug
);
wire unused_1;
mkOPED moped(
.pcie_clk_p (pcie_clk_p),
.pcie_clk_n (pcie_clk_n),
.pcie_reset_n (pcie_reset_n),
.pcie_rxp_i (pcie_rxp),
.pcie_rxn_i (pcie_rxn),
.pcie_txp (pcie_txp),
.pcie_txn (pcie_txn),
.debug (debug),
.trnClk (oped_clk125),
.CLK_GATE_trnClk (unused_1)
);
endmodule | module opedTop(
input wire pcie_clk_p,
input wire pcie_clk_n,
input wire pcie_reset_n,
output wire [7:0] pcie_txp,
output wire [7:0] pcie_txn,
input wire [7:0] pcie_rxp,
input wire [7:0] pcie_rxn,
output wire [31:0] debug
); |
wire unused_1;
mkOPED moped(
.pcie_clk_p (pcie_clk_p),
.pcie_clk_n (pcie_clk_n),
.pcie_reset_n (pcie_reset_n),
.pcie_rxp_i (pcie_rxp),
.pcie_rxn_i (pcie_rxn),
.pcie_txp (pcie_txp),
.pcie_txn (pcie_txn),
.debug (debug),
.trnClk (oped_clk125),
.CLK_GATE_trnClk (unused_1)
);
endmodule | 25 |
4,977 | data/full_repos/permissive/1122957/libsrc/hdl/vhd/mkBiasWorker4B.v | 1,122,957 | mkBiasWorker4B.v | v | 76 | 88 | [] | [] | [] | [(4, 75)] | null | null | 1: b"%Error: data/full_repos/permissive/1122957/libsrc/hdl/vhd/mkBiasWorker4B.v:39: Cannot find file containing module: 'bias_vhdl'\n bias_vhdl bias_vi(\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/1122957/libsrc/hdl/vhd,data/full_repos/permissive/1122957/bias_vhdl\n data/full_repos/permissive/1122957/libsrc/hdl/vhd,data/full_repos/permissive/1122957/bias_vhdl.v\n data/full_repos/permissive/1122957/libsrc/hdl/vhd,data/full_repos/permissive/1122957/bias_vhdl.sv\n bias_vhdl\n bias_vhdl.v\n bias_vhdl.sv\n obj_dir/bias_vhdl\n obj_dir/bias_vhdl.v\n obj_dir/bias_vhdl.sv\n%Error: Exiting due to 1 error(s)\n" | 5,237 | module | module mkBiasWorker4B(
input wciS0_Clk,
input wciS0_MReset_n,
input [2 : 0] wciS0_MCmd,
input wciS0_MAddrSpace,
input [3 : 0] wciS0_MByteEn,
input [31 : 0] wciS0_MAddr,
input [31 : 0] wciS0_MData,
output [1 : 0] wciS0_SResp,
output [31 : 0] wciS0_SData,
output wciS0_SThreadBusy,
output [1 : 0] wciS0_SFlag,
input [1 : 0] wciS0_MFlag,
input [2 : 0] wsiS0_MCmd,
input wsiS0_MReqLast,
input wsiS0_MBurstPrecise,
input [11 : 0] wsiS0_MBurstLength,
input [31 : 0] wsiS0_MData,
input [3 : 0] wsiS0_MByteEn,
input [7 : 0] wsiS0_MReqInfo,
output wsiS0_SThreadBusy,
output wsiS0_SReset_n,
input wsiS0_MReset_n,
output [2 : 0] wsiM0_MCmd,
output wsiM0_MReqLast,
output wsiM0_MBurstPrecise,
output [11 : 0] wsiM0_MBurstLength,
output [31 : 0] wsiM0_MData,
output [3 : 0] wsiM0_MByteEn,
output [7 : 0] wsiM0_MReqInfo,
input wsiM0_SThreadBusy,
output wsiM0_MReset_n,
input wsiM0_SReset_n );
bias_vhdl bias_vi(
.ctl_Clk (wciS0_Clk),
.ctl_MAddr (wciS0_MAddr[4:0]),
.ctl_MAddrSpace (wciS0_MAddrSpace),
.ctl_MCmd (wciS0_MCmd),
.ctl_MData (wciS0_MData),
.ctl_MFlag (wciS0_MFlag),
.ctl_MReset_n (wciS0_MReset_n),
.ctl_SData (wciS0_SData),
.ctl_SFlag (wciS0_SFlag),
.ctl_SResp (wciS0_SResp),
.ctl_SThreadBusy (wciS0_SThreadBusy),
.in_MBurstLength (wsiS0_MBurstLength),
.in_MByteEn (wsiS0_MByteEn),
.in_MCmd (wsiS0_MCmd),
.in_MData (wsiS0_MData),
.in_MBurstPrecise (wsiS0_MBurstPrecise),
.in_MReqInfo (wsiS0_MReqInfo),
.in_MReqLast (wsiS0_MReqLast),
.in_MReset_n (wsiS0_MReset_n),
.in_SReset_n (wsiS0_SReset_n),
.in_SThreadBusy (wsiS0_SThreadBusy),
.out_SReset_n (wsiM0_SReset_n),
.out_SThreadBusy (wsiM0_SThreadBusy),
.out_MBurstLength (wsiM0_MBurstLength),
.out_MByteEn (wsiM0_MByteEn),
.out_MCmd (wsiM0_MCmd),
.out_MData (wsiM0_MData),
.out_MBurstPrecise (wsiM0_MBurstPrecise),
.out_MReqInfo (wsiM0_MReqInfo),
.out_MReqLast (wsiM0_MReqLast),
.out_MReset_n (wsiM0_MReset_n)
);
endmodule | module mkBiasWorker4B(
input wciS0_Clk,
input wciS0_MReset_n,
input [2 : 0] wciS0_MCmd,
input wciS0_MAddrSpace,
input [3 : 0] wciS0_MByteEn,
input [31 : 0] wciS0_MAddr,
input [31 : 0] wciS0_MData,
output [1 : 0] wciS0_SResp,
output [31 : 0] wciS0_SData,
output wciS0_SThreadBusy,
output [1 : 0] wciS0_SFlag,
input [1 : 0] wciS0_MFlag,
input [2 : 0] wsiS0_MCmd,
input wsiS0_MReqLast,
input wsiS0_MBurstPrecise,
input [11 : 0] wsiS0_MBurstLength,
input [31 : 0] wsiS0_MData,
input [3 : 0] wsiS0_MByteEn,
input [7 : 0] wsiS0_MReqInfo,
output wsiS0_SThreadBusy,
output wsiS0_SReset_n,
input wsiS0_MReset_n,
output [2 : 0] wsiM0_MCmd,
output wsiM0_MReqLast,
output wsiM0_MBurstPrecise,
output [11 : 0] wsiM0_MBurstLength,
output [31 : 0] wsiM0_MData,
output [3 : 0] wsiM0_MByteEn,
output [7 : 0] wsiM0_MReqInfo,
input wsiM0_SThreadBusy,
output wsiM0_MReset_n,
input wsiM0_SReset_n ); |
bias_vhdl bias_vi(
.ctl_Clk (wciS0_Clk),
.ctl_MAddr (wciS0_MAddr[4:0]),
.ctl_MAddrSpace (wciS0_MAddrSpace),
.ctl_MCmd (wciS0_MCmd),
.ctl_MData (wciS0_MData),
.ctl_MFlag (wciS0_MFlag),
.ctl_MReset_n (wciS0_MReset_n),
.ctl_SData (wciS0_SData),
.ctl_SFlag (wciS0_SFlag),
.ctl_SResp (wciS0_SResp),
.ctl_SThreadBusy (wciS0_SThreadBusy),
.in_MBurstLength (wsiS0_MBurstLength),
.in_MByteEn (wsiS0_MByteEn),
.in_MCmd (wsiS0_MCmd),
.in_MData (wsiS0_MData),
.in_MBurstPrecise (wsiS0_MBurstPrecise),
.in_MReqInfo (wsiS0_MReqInfo),
.in_MReqLast (wsiS0_MReqLast),
.in_MReset_n (wsiS0_MReset_n),
.in_SReset_n (wsiS0_SReset_n),
.in_SThreadBusy (wsiS0_SThreadBusy),
.out_SReset_n (wsiM0_SReset_n),
.out_SThreadBusy (wsiM0_SThreadBusy),
.out_MBurstLength (wsiM0_MBurstLength),
.out_MByteEn (wsiM0_MByteEn),
.out_MCmd (wsiM0_MCmd),
.out_MData (wsiM0_MData),
.out_MBurstPrecise (wsiM0_MBurstPrecise),
.out_MReqInfo (wsiM0_MReqInfo),
.out_MReqLast (wsiM0_MReqLast),
.out_MReset_n (wsiM0_MReset_n)
);
endmodule | 25 |
4,979 | data/full_repos/permissive/112626266/Alu.v | 112,626,266 | Alu.v | v | 106 | 76 | [] | [] | [] | [(3, 29), (31, 83), (87, 105)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/112626266/Alu.v:31: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'alu_control\'\nmodule alu_control(ALUOp,FUNCT,op_code);\n ^~~~~~~~~~~\n : ... Top module \'ALU\'\nmodule ALU(read_data1, read_data2, op_code, result, zero);\n ^~~\n : ... Top module \'two_to_one_mux\'\nmodule two_to_one_mux(read_data2 , sign_extend , ALUSrc , write_data);\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 5,360 | module | module alu_control(ALUOp,FUNCT,op_code);
input [1:0] ALUOp ;
input [5:0] FUNCT ;
output reg [3:0] op_code ;
always @(*)
if(ALUOp == 2'b00)
op_code=4'b0000 ;
else if(ALUOp == 2'b01)
op_code=4'b0001 ;
else
begin
case ( FUNCT )
6'b100000 : op_code=4'b0000 ;
6'b100010 : op_code=4'b0001 ;
6'b100100 : op_code=4'b0010 ;
6'b100101 : op_code=4'b0011 ;
6'b101010 : op_code=4'b0111 ;
6'b000000 : op_code=4'b0100 ;
default : op_code=op_code ;
endcase
end
endmodule | module alu_control(ALUOp,FUNCT,op_code); |
input [1:0] ALUOp ;
input [5:0] FUNCT ;
output reg [3:0] op_code ;
always @(*)
if(ALUOp == 2'b00)
op_code=4'b0000 ;
else if(ALUOp == 2'b01)
op_code=4'b0001 ;
else
begin
case ( FUNCT )
6'b100000 : op_code=4'b0000 ;
6'b100010 : op_code=4'b0001 ;
6'b100100 : op_code=4'b0010 ;
6'b100101 : op_code=4'b0011 ;
6'b101010 : op_code=4'b0111 ;
6'b000000 : op_code=4'b0100 ;
default : op_code=op_code ;
endcase
end
endmodule | 1 |
4,980 | data/full_repos/permissive/112626266/Alu.v | 112,626,266 | Alu.v | v | 106 | 76 | [] | [] | [] | [(3, 29), (31, 83), (87, 105)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/112626266/Alu.v:31: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'alu_control\'\nmodule alu_control(ALUOp,FUNCT,op_code);\n ^~~~~~~~~~~\n : ... Top module \'ALU\'\nmodule ALU(read_data1, read_data2, op_code, result, zero);\n ^~~\n : ... Top module \'two_to_one_mux\'\nmodule two_to_one_mux(read_data2 , sign_extend , ALUSrc , write_data);\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 5,360 | module | module ALU(read_data1, read_data2, op_code, result, zero);
input [31:0] read_data1 , read_data2;
input [3:0] op_code;
output reg [31:0] result;
output reg zero ;
always@(*)
begin
zero=1'b0;
if(op_code == 0)
begin result = read_data1 + read_data2; end
else if(op_code == 1)
begin result = read_data1 - read_data2;
if (result==0)
zero=1'b1;
else
zero=1'b0;
end
else if(op_code == 2)
begin result = read_data1 & read_data2; end
else if(op_code == 3)
begin result = read_data1 | read_data2; end
else if(op_code == 4)
begin result = read_data1 << read_data2; end
else if(op_code == 5)
begin result = read_data1 >> read_data2; end
else if(op_code == 6)
begin result = $signed(read_data1) >>> read_data2; end
else if(op_code == 7)
begin
if(read_data1 > read_data2) begin result = read_data1; end
else begin result = read_data2; end
end
else if(op_code == 8)
begin
if(read_data1 < read_data2) begin result = read_data1; end
else begin result = read_data2; end
end
else begin result = 32'bx; end
end
endmodule | module ALU(read_data1, read_data2, op_code, result, zero); |
input [31:0] read_data1 , read_data2;
input [3:0] op_code;
output reg [31:0] result;
output reg zero ;
always@(*)
begin
zero=1'b0;
if(op_code == 0)
begin result = read_data1 + read_data2; end
else if(op_code == 1)
begin result = read_data1 - read_data2;
if (result==0)
zero=1'b1;
else
zero=1'b0;
end
else if(op_code == 2)
begin result = read_data1 & read_data2; end
else if(op_code == 3)
begin result = read_data1 | read_data2; end
else if(op_code == 4)
begin result = read_data1 << read_data2; end
else if(op_code == 5)
begin result = read_data1 >> read_data2; end
else if(op_code == 6)
begin result = $signed(read_data1) >>> read_data2; end
else if(op_code == 7)
begin
if(read_data1 > read_data2) begin result = read_data1; end
else begin result = read_data2; end
end
else if(op_code == 8)
begin
if(read_data1 < read_data2) begin result = read_data1; end
else begin result = read_data2; end
end
else begin result = 32'bx; end
end
endmodule | 1 |
4,981 | data/full_repos/permissive/112626266/Alu.v | 112,626,266 | Alu.v | v | 106 | 76 | [] | [] | [] | [(3, 29), (31, 83), (87, 105)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/112626266/Alu.v:31: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'alu_control\'\nmodule alu_control(ALUOp,FUNCT,op_code);\n ^~~~~~~~~~~\n : ... Top module \'ALU\'\nmodule ALU(read_data1, read_data2, op_code, result, zero);\n ^~~\n : ... Top module \'two_to_one_mux\'\nmodule two_to_one_mux(read_data2 , sign_extend , ALUSrc , write_data);\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 5,360 | module | module two_to_one_mux(read_data2 , sign_extend , ALUSrc , write_data);
input [31:0]read_data2 ;
input [31:0]sign_extend;
input ALUSrc;
output reg [31:0]write_data;
always@(*)
begin
if(ALUSrc == 0)
begin write_data = read_data2; end
else if(ALUSrc == 1)
begin write_data = sign_extend; end
else
begin write_data = 32'bx; end
end
endmodule | module two_to_one_mux(read_data2 , sign_extend , ALUSrc , write_data); |
input [31:0]read_data2 ;
input [31:0]sign_extend;
input ALUSrc;
output reg [31:0]write_data;
always@(*)
begin
if(ALUSrc == 0)
begin write_data = read_data2; end
else if(ALUSrc == 1)
begin write_data = sign_extend; end
else
begin write_data = 32'bx; end
end
endmodule | 1 |
4,984 | data/full_repos/permissive/112626266/Data_Memory.v | 112,626,266 | Data_Memory.v | v | 67 | 134 | [] | [] | [] | [(1, 27)] | null | data/verilator_xmls/d9c5b3ac-98d7-43f8-8904-e849203c5050.xml | null | 5,363 | module | module Data_Memory(Address , Write_Data , MemWrite , MemRead , Read_Data, Clock);
input wire[31:0] Address;
input wire[31:0] Write_Data;
input MemWrite;
input MemRead;
output reg[31:0] Read_Data;
reg[31:0] D_Memory [0:255];
input wire Clock;
always@(*)
begin
Read_Data <= (MemRead && ~MemWrite)? D_Memory[Address] : Read_Data;
D_Memory[Address] <= (MemWrite && ~MemRead)? Write_Data : D_Memory[Address];
end
initial
begin
D_Memory[3] = 4;
D_Memory[7] = 8;
end
endmodule | module Data_Memory(Address , Write_Data , MemWrite , MemRead , Read_Data, Clock); |
input wire[31:0] Address;
input wire[31:0] Write_Data;
input MemWrite;
input MemRead;
output reg[31:0] Read_Data;
reg[31:0] D_Memory [0:255];
input wire Clock;
always@(*)
begin
Read_Data <= (MemRead && ~MemWrite)? D_Memory[Address] : Read_Data;
D_Memory[Address] <= (MemWrite && ~MemRead)? Write_Data : D_Memory[Address];
end
initial
begin
D_Memory[3] = 4;
D_Memory[7] = 8;
end
endmodule | 1 |
4,988 | data/full_repos/permissive/112626266/new_decode_stage.v | 112,626,266 | new_decode_stage.v | v | 80 | 211 | [] | [] | [] | [(9, 79)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/112626266/new_decode_stage.v:57: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance decode\n DataB <= IDinst[10:6];\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/112626266/new_decode_stage.v:65: Cannot find file containing module: \'HazardUnit\'\n HazardUnit HU(readReg1,readReg2,EXRegRt,ExMemStall,PCWrite,IFIDWrite,HazMuxCon);\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/HazardUnit\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/HazardUnit.v\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/HazardUnit.sv\n HazardUnit\n HazardUnit.v\n HazardUnit.sv\n obj_dir/HazardUnit\n obj_dir/HazardUnit.v\n obj_dir/HazardUnit.sv\n%Error: data/full_repos/permissive/112626266/new_decode_stage.v:67: Cannot find file containing module: \'Control\'\nControl thecontrol(IDinst[31:26],ConOut);\n^~~~~~~\n%Error: data/full_repos/permissive/112626266/new_decode_stage.v:70: Cannot find file containing module: \'RegFile\'\nRegFile rf(DataA,DataB_,readReg1,readReg2,WBRegRd,datatowirte,WBWB[0],clock);\n^~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 5,367 | module | module decode (clock,WBRegRd,WBWB,EXM,EXRegRt,datatowirte,IDpc_plus_4,IDinst,WB,M,EX,IDRegRs,IDRegRt,IDRegRd,DataA,DataB,imm_value,BranchAddr,brunch_taken,brunch_control ,PCWrite,IFIDWrite);
input clock ;
input [31:0] IDpc_plus_4,IDinst;
input [2:0]EXM;
input [4:0]EXRegRt;
input [4:0]WBRegRd;
input [1:0] WBWB;
input [31:0] datatowirte;
output [1:0]WB;
output [2:0]M;
output [3:0]EX;
output [4:0]IDRegRs,IDRegRt,IDRegRd;
output [31:0]DataA,imm_value;
output reg [31:0] DataB;
output [31:0] BranchAddr ;
output brunch_taken,brunch_control,PCWrite,IFIDWrite;
assign IDRegRs[4:0]=IDinst[25:21];
assign IDRegRt[4:0]=IDinst[20:16];
assign IDRegRd[4:0]=IDinst[15:11];
assign imm_value ={IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15:0]};
assign BranchAddr = (imm_value << 2) + IDpc_plus_4;
wire [8:0] IDcontrol,ConOut;
wire HazMuxCon;
assign IDcontrol = HazMuxCon?ConOut:0;
reg [4:0] readReg1, readReg2;
wire signed [31:0] DataB_;
always @(*) begin
if ((IDinst[31:26] == 0) && (IDinst[5:0] == 0)) begin
readReg1 <= IDinst[20:16];
readReg2 <= 0;
DataB <= IDinst[10:6];
end else begin
readReg1 <= IDinst[25:21];
readReg2 <= IDinst[20:16];
DataB <= DataB_;
end
end
wire ExMemStall = EXM[0] | EXM[1];
HazardUnit HU(readReg1,readReg2,EXRegRt,ExMemStall,PCWrite,IFIDWrite,HazMuxCon);
Control thecontrol(IDinst[31:26],ConOut);
RegFile rf(DataA,DataB_,readReg1,readReg2,WBRegRd,datatowirte,WBWB[0],clock);
assign brunch_taken=(DataA==DataB)?1:0;
assign brunch_control=IDcontrol[6];
assign WB=IDcontrol[8:7];
assign M=IDcontrol[6:4];
assign EX=IDcontrol[3:0];
endmodule | module decode (clock,WBRegRd,WBWB,EXM,EXRegRt,datatowirte,IDpc_plus_4,IDinst,WB,M,EX,IDRegRs,IDRegRt,IDRegRd,DataA,DataB,imm_value,BranchAddr,brunch_taken,brunch_control ,PCWrite,IFIDWrite); |
input clock ;
input [31:0] IDpc_plus_4,IDinst;
input [2:0]EXM;
input [4:0]EXRegRt;
input [4:0]WBRegRd;
input [1:0] WBWB;
input [31:0] datatowirte;
output [1:0]WB;
output [2:0]M;
output [3:0]EX;
output [4:0]IDRegRs,IDRegRt,IDRegRd;
output [31:0]DataA,imm_value;
output reg [31:0] DataB;
output [31:0] BranchAddr ;
output brunch_taken,brunch_control,PCWrite,IFIDWrite;
assign IDRegRs[4:0]=IDinst[25:21];
assign IDRegRt[4:0]=IDinst[20:16];
assign IDRegRd[4:0]=IDinst[15:11];
assign imm_value ={IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15:0]};
assign BranchAddr = (imm_value << 2) + IDpc_plus_4;
wire [8:0] IDcontrol,ConOut;
wire HazMuxCon;
assign IDcontrol = HazMuxCon?ConOut:0;
reg [4:0] readReg1, readReg2;
wire signed [31:0] DataB_;
always @(*) begin
if ((IDinst[31:26] == 0) && (IDinst[5:0] == 0)) begin
readReg1 <= IDinst[20:16];
readReg2 <= 0;
DataB <= IDinst[10:6];
end else begin
readReg1 <= IDinst[25:21];
readReg2 <= IDinst[20:16];
DataB <= DataB_;
end
end
wire ExMemStall = EXM[0] | EXM[1];
HazardUnit HU(readReg1,readReg2,EXRegRt,ExMemStall,PCWrite,IFIDWrite,HazMuxCon);
Control thecontrol(IDinst[31:26],ConOut);
RegFile rf(DataA,DataB_,readReg1,readReg2,WBRegRd,datatowirte,WBWB[0],clock);
assign brunch_taken=(DataA==DataB)?1:0;
assign brunch_control=IDcontrol[6];
assign WB=IDcontrol[8:7];
assign M=IDcontrol[6:4];
assign EX=IDcontrol[3:0];
endmodule | 1 |
4,989 | data/full_repos/permissive/112626266/our_top_module.v | 112,626,266 | our_top_module.v | v | 251 | 125 | [] | [] | [] | [(1, 14), (16, 25), (27, 32), (35, 249)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/112626266/our_top_module.v:6: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112626266/our_top_module.v:12: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/112626266/our_top_module.v:75: Cannot find file containing module: \'PC\'\n PC pc1(clk , next_PC , PCWrite , current_PC);\n ^~\n ... Looked in:\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC.v\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC.sv\n PC\n PC.v\n PC.sv\n obj_dir/PC\n obj_dir/PC.v\n obj_dir/PC.sv\n%Error: data/full_repos/permissive/112626266/our_top_module.v:80: Cannot find file containing module: \'Instruction_Memory\'\n Instruction_Memory imem(current_PC , Instruction, addent);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:87: Cannot find file containing module: \'IFID\'\n IFID IFID1(clk , Instruction ,IFIDWrite , PC_from_Adder , Instruction_to_ID , PC_from_Adder_to_ID);\n ^~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:121: Cannot find file containing module: \'decode\'\n decode d1(clk , WBRegRd , WBreg2 , M , EXRegRt , Write_Data , PC_from_Adder_to_ID , Instruction_to_ID ,\n ^~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:176: Cannot find file containing module: \'EXMEM\'\n EXMEM emem1(clk,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);\n ^~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:192: Cannot find file containing module: \'Data_Memory\'\n Data_Memory dm1(.Clock(clk) , .Address(ALUreg) , .Write_Data(WriteDataOut) , .MemWrite(MemWrite) , .MemRead(MemRead) , \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:217: Cannot find file containing module: \'MEMWB\'\n MEMWB mwb(.clock(clk) , .WB(WBreg) , .Memout(Read_Data) , .ALUOut(ALUreg) , .RegRD(RegRDreg) , \n ^~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:223: Cannot find file containing module: \'ExBrunch\'\n ExBrunch EXBranch(.clock(clk),.datatowrite(Write_Data),.MEMALUOut(ALUreg),.DEXWB(DecodeWB) ,.DEXM(DecodeM),.DEXEX(EX),\n ^~~~~~~~\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 5,368 | module | module Clock(clk);
output reg clk;
initial
begin
clk = 0;
#10;
end
always
begin
clk = ~clk;
#1;
end
endmodule | module Clock(clk); |
output reg clk;
initial
begin
clk = 0;
#10;
end
always
begin
clk = ~clk;
#1;
end
endmodule | 1 |
4,990 | data/full_repos/permissive/112626266/our_top_module.v | 112,626,266 | our_top_module.v | v | 251 | 125 | [] | [] | [] | [(1, 14), (16, 25), (27, 32), (35, 249)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/112626266/our_top_module.v:6: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112626266/our_top_module.v:12: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/112626266/our_top_module.v:75: Cannot find file containing module: \'PC\'\n PC pc1(clk , next_PC , PCWrite , current_PC);\n ^~\n ... Looked in:\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC.v\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC.sv\n PC\n PC.v\n PC.sv\n obj_dir/PC\n obj_dir/PC.v\n obj_dir/PC.sv\n%Error: data/full_repos/permissive/112626266/our_top_module.v:80: Cannot find file containing module: \'Instruction_Memory\'\n Instruction_Memory imem(current_PC , Instruction, addent);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:87: Cannot find file containing module: \'IFID\'\n IFID IFID1(clk , Instruction ,IFIDWrite , PC_from_Adder , Instruction_to_ID , PC_from_Adder_to_ID);\n ^~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:121: Cannot find file containing module: \'decode\'\n decode d1(clk , WBRegRd , WBreg2 , M , EXRegRt , Write_Data , PC_from_Adder_to_ID , Instruction_to_ID ,\n ^~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:176: Cannot find file containing module: \'EXMEM\'\n EXMEM emem1(clk,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);\n ^~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:192: Cannot find file containing module: \'Data_Memory\'\n Data_Memory dm1(.Clock(clk) , .Address(ALUreg) , .Write_Data(WriteDataOut) , .MemWrite(MemWrite) , .MemRead(MemRead) , \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:217: Cannot find file containing module: \'MEMWB\'\n MEMWB mwb(.clock(clk) , .WB(WBreg) , .Memout(Read_Data) , .ALUOut(ALUreg) , .RegRD(RegRDreg) , \n ^~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:223: Cannot find file containing module: \'ExBrunch\'\n ExBrunch EXBranch(.clock(clk),.datatowrite(Write_Data),.MEMALUOut(ALUreg),.DEXWB(DecodeWB) ,.DEXM(DecodeM),.DEXEX(EX),\n ^~~~~~~~\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 5,368 | module | module MUX(MemtoReg , Read_Data , ALU_Result , Write_Data);
input MemtoReg;
input[31:0] Read_Data;
input[31:0] ALU_Result;
output[31:0] Write_Data;
assign Write_Data = MemtoReg ? Read_Data : ALU_Result;
endmodule | module MUX(MemtoReg , Read_Data , ALU_Result , Write_Data); |
input MemtoReg;
input[31:0] Read_Data;
input[31:0] ALU_Result;
output[31:0] Write_Data;
assign Write_Data = MemtoReg ? Read_Data : ALU_Result;
endmodule | 1 |
4,991 | data/full_repos/permissive/112626266/our_top_module.v | 112,626,266 | our_top_module.v | v | 251 | 125 | [] | [] | [] | [(1, 14), (16, 25), (27, 32), (35, 249)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/112626266/our_top_module.v:6: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112626266/our_top_module.v:12: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/112626266/our_top_module.v:75: Cannot find file containing module: \'PC\'\n PC pc1(clk , next_PC , PCWrite , current_PC);\n ^~\n ... Looked in:\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC.v\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC.sv\n PC\n PC.v\n PC.sv\n obj_dir/PC\n obj_dir/PC.v\n obj_dir/PC.sv\n%Error: data/full_repos/permissive/112626266/our_top_module.v:80: Cannot find file containing module: \'Instruction_Memory\'\n Instruction_Memory imem(current_PC , Instruction, addent);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:87: Cannot find file containing module: \'IFID\'\n IFID IFID1(clk , Instruction ,IFIDWrite , PC_from_Adder , Instruction_to_ID , PC_from_Adder_to_ID);\n ^~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:121: Cannot find file containing module: \'decode\'\n decode d1(clk , WBRegRd , WBreg2 , M , EXRegRt , Write_Data , PC_from_Adder_to_ID , Instruction_to_ID ,\n ^~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:176: Cannot find file containing module: \'EXMEM\'\n EXMEM emem1(clk,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);\n ^~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:192: Cannot find file containing module: \'Data_Memory\'\n Data_Memory dm1(.Clock(clk) , .Address(ALUreg) , .Write_Data(WriteDataOut) , .MemWrite(MemWrite) , .MemRead(MemRead) , \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:217: Cannot find file containing module: \'MEMWB\'\n MEMWB mwb(.clock(clk) , .WB(WBreg) , .Memout(Read_Data) , .ALUOut(ALUreg) , .RegRD(RegRDreg) , \n ^~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:223: Cannot find file containing module: \'ExBrunch\'\n ExBrunch EXBranch(.clock(clk),.datatowrite(Write_Data),.MEMALUOut(ALUreg),.DEXWB(DecodeWB) ,.DEXM(DecodeM),.DEXEX(EX),\n ^~~~~~~~\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 5,368 | module | module Adder(in1 , in2 , out);
input[31:0] in1;
input[31:0] in2;
output[31:0] out;
assign out = in1 + in2;
endmodule | module Adder(in1 , in2 , out); |
input[31:0] in1;
input[31:0] in2;
output[31:0] out;
assign out = in1 + in2;
endmodule | 1 |
4,992 | data/full_repos/permissive/112626266/our_top_module.v | 112,626,266 | our_top_module.v | v | 251 | 125 | [] | [] | [] | [(1, 14), (16, 25), (27, 32), (35, 249)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/112626266/our_top_module.v:6: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112626266/our_top_module.v:12: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/112626266/our_top_module.v:75: Cannot find file containing module: \'PC\'\n PC pc1(clk , next_PC , PCWrite , current_PC);\n ^~\n ... Looked in:\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC.v\n data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC.sv\n PC\n PC.v\n PC.sv\n obj_dir/PC\n obj_dir/PC.v\n obj_dir/PC.sv\n%Error: data/full_repos/permissive/112626266/our_top_module.v:80: Cannot find file containing module: \'Instruction_Memory\'\n Instruction_Memory imem(current_PC , Instruction, addent);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:87: Cannot find file containing module: \'IFID\'\n IFID IFID1(clk , Instruction ,IFIDWrite , PC_from_Adder , Instruction_to_ID , PC_from_Adder_to_ID);\n ^~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:121: Cannot find file containing module: \'decode\'\n decode d1(clk , WBRegRd , WBreg2 , M , EXRegRt , Write_Data , PC_from_Adder_to_ID , Instruction_to_ID ,\n ^~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:176: Cannot find file containing module: \'EXMEM\'\n EXMEM emem1(clk,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);\n ^~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:192: Cannot find file containing module: \'Data_Memory\'\n Data_Memory dm1(.Clock(clk) , .Address(ALUreg) , .Write_Data(WriteDataOut) , .MemWrite(MemWrite) , .MemRead(MemRead) , \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:217: Cannot find file containing module: \'MEMWB\'\n MEMWB mwb(.clock(clk) , .WB(WBreg) , .Memout(Read_Data) , .ALUOut(ALUreg) , .RegRD(RegRDreg) , \n ^~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:223: Cannot find file containing module: \'ExBrunch\'\n ExBrunch EXBranch(.clock(clk),.datatowrite(Write_Data),.MEMALUOut(ALUreg),.DEXWB(DecodeWB) ,.DEXM(DecodeM),.DEXEX(EX),\n ^~~~~~~~\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 5,368 | module | module top_mod;
wire clk;
Clock c1(clk);
wire Branch_Control;
wire Branch_Taken;
wire PC_selector;
and(PC_selector , Branch_Control , Branch_Taken);
wire[31:0] PC_from_Branch;
wire[31:0] PC_from_Adder;
wire[31:0] next_PC;
MUX pc_mux(PC_selector , PC_from_Branch , PC_from_Adder , next_PC);
wire PCWrite;
wire[31:0] current_PC;
PC pc1(clk , next_PC , PCWrite , current_PC);
wire[31:0] Instruction;
wire [31:0] addent;
Instruction_Memory imem(current_PC , Instruction, addent);
Adder normal_pc_adder(current_PC , addent , PC_from_Adder);
wire IFIDWrite;
wire[31:0] Instruction_to_ID , PC_from_Adder_to_ID;
IFID IFID1(clk , Instruction ,IFIDWrite , PC_from_Adder , Instruction_to_ID , PC_from_Adder_to_ID);
wire [2:0] M;
wire [4:0]EXRegRt;
wire [4:0]WBRegRd;
wire [31:0] Write_Data;
wire [1:0]DecodeWB;
wire [2:0]DecodeM;
wire [3:0]EX;
wire [4:0]IDRegRs,IDRegRt,IDRegRd;
wire [31:0]DataA,DataB,imm_value;
wire [1:0] WBreg2;
decode d1(clk , WBRegRd , WBreg2 , M , EXRegRt , Write_Data , PC_from_Adder_to_ID , Instruction_to_ID ,
DecodeWB , DecodeM , EX , IDRegRs , IDRegRt , IDRegRd , DataA , DataB, imm_value ,
PC_from_Branch , Branch_Taken , Branch_Control , PCWrite , IFIDWrite);
wire [1:0] WB;
wire [4:0] RegRD;
wire [31:0] ALUOut,WriteDataIn;
wire [1:0] WBreg;
wire [2:0] Mreg;
wire [31:0] ALUreg,WriteDataOut;
wire [4:0] RegRDreg;
EXMEM emem1(clk,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);
wire MemWrite; assign MemWrite = Mreg[0:0];
wire MemRead; assign MemRead = Mreg[1:1];
wire[31:0] Read_Data;
Data_Memory dm1(.Clock(clk) , .Address(ALUreg) , .Write_Data(WriteDataOut) , .MemWrite(MemWrite) , .MemRead(MemRead) ,
.Read_Data(Read_Data));
wire [31:0] Memreg2,ALUreg2;
MEMWB mwb(.clock(clk) , .WB(WBreg) , .Memout(Read_Data) , .ALUOut(ALUreg) , .RegRD(RegRDreg) ,
.WBreg(WBreg2) , .Memreg(Memreg2) , .ALUreg(ALUreg2) , .RegRDreg(WBRegRd));
ExBrunch EXBranch(.clock(clk),.datatowrite(Write_Data),.MEMALUOut(ALUreg),.DEXWB(DecodeWB) ,.DEXM(DecodeM),.DEXEX(EX),
.DEXRegRs(IDRegRs),.DEXRegRt(IDRegRt),.DEXRegRd(IDRegRd),.DEXDataA(DataA),.DEXDataB(DataB),
.DEXimm_value(imm_value),.EXMEMRegRd(RegRDreg),.MEMWBRegRd(WBRegRd),.EXMEM_RegWrite(WBreg),.MEMWB_RegWrite(WBreg2),
.EXMWB(WB),.EXMM(M),.EXALUOut(ALUOut),.regtopass(RegRD),.EXMWriteDataIn(WriteDataIn), .RtReg(EXRegRt));
wire MemtoReg; assign MemtoReg = WBreg2[1];
MUX m1(.MemtoReg(MemtoReg) , .Read_Data(Memreg2) , .ALU_Result(ALUreg2) , .Write_Data(Write_Data));
endmodule | module top_mod; |
wire clk;
Clock c1(clk);
wire Branch_Control;
wire Branch_Taken;
wire PC_selector;
and(PC_selector , Branch_Control , Branch_Taken);
wire[31:0] PC_from_Branch;
wire[31:0] PC_from_Adder;
wire[31:0] next_PC;
MUX pc_mux(PC_selector , PC_from_Branch , PC_from_Adder , next_PC);
wire PCWrite;
wire[31:0] current_PC;
PC pc1(clk , next_PC , PCWrite , current_PC);
wire[31:0] Instruction;
wire [31:0] addent;
Instruction_Memory imem(current_PC , Instruction, addent);
Adder normal_pc_adder(current_PC , addent , PC_from_Adder);
wire IFIDWrite;
wire[31:0] Instruction_to_ID , PC_from_Adder_to_ID;
IFID IFID1(clk , Instruction ,IFIDWrite , PC_from_Adder , Instruction_to_ID , PC_from_Adder_to_ID);
wire [2:0] M;
wire [4:0]EXRegRt;
wire [4:0]WBRegRd;
wire [31:0] Write_Data;
wire [1:0]DecodeWB;
wire [2:0]DecodeM;
wire [3:0]EX;
wire [4:0]IDRegRs,IDRegRt,IDRegRd;
wire [31:0]DataA,DataB,imm_value;
wire [1:0] WBreg2;
decode d1(clk , WBRegRd , WBreg2 , M , EXRegRt , Write_Data , PC_from_Adder_to_ID , Instruction_to_ID ,
DecodeWB , DecodeM , EX , IDRegRs , IDRegRt , IDRegRd , DataA , DataB, imm_value ,
PC_from_Branch , Branch_Taken , Branch_Control , PCWrite , IFIDWrite);
wire [1:0] WB;
wire [4:0] RegRD;
wire [31:0] ALUOut,WriteDataIn;
wire [1:0] WBreg;
wire [2:0] Mreg;
wire [31:0] ALUreg,WriteDataOut;
wire [4:0] RegRDreg;
EXMEM emem1(clk,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);
wire MemWrite; assign MemWrite = Mreg[0:0];
wire MemRead; assign MemRead = Mreg[1:1];
wire[31:0] Read_Data;
Data_Memory dm1(.Clock(clk) , .Address(ALUreg) , .Write_Data(WriteDataOut) , .MemWrite(MemWrite) , .MemRead(MemRead) ,
.Read_Data(Read_Data));
wire [31:0] Memreg2,ALUreg2;
MEMWB mwb(.clock(clk) , .WB(WBreg) , .Memout(Read_Data) , .ALUOut(ALUreg) , .RegRD(RegRDreg) ,
.WBreg(WBreg2) , .Memreg(Memreg2) , .ALUreg(ALUreg2) , .RegRDreg(WBRegRd));
ExBrunch EXBranch(.clock(clk),.datatowrite(Write_Data),.MEMALUOut(ALUreg),.DEXWB(DecodeWB) ,.DEXM(DecodeM),.DEXEX(EX),
.DEXRegRs(IDRegRs),.DEXRegRt(IDRegRt),.DEXRegRd(IDRegRd),.DEXDataA(DataA),.DEXDataB(DataB),
.DEXimm_value(imm_value),.EXMEMRegRd(RegRDreg),.MEMWBRegRd(WBRegRd),.EXMEM_RegWrite(WBreg),.MEMWB_RegWrite(WBreg2),
.EXMWB(WB),.EXMM(M),.EXALUOut(ALUOut),.regtopass(RegRD),.EXMWriteDataIn(WriteDataIn), .RtReg(EXRegRt));
wire MemtoReg; assign MemtoReg = WBreg2[1];
MUX m1(.MemtoReg(MemtoReg) , .Read_Data(Memreg2) , .ALU_Result(ALUreg2) , .Write_Data(Write_Data));
endmodule | 1 |
4,993 | data/full_repos/permissive/112626266/PIPELINE.v | 112,626,266 | PIPELINE.v | v | 113 | 98 | [] | [] | [] | [(3, 21), (23, 59), (61, 87), (89, 111)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/112626266/PIPELINE.v:23: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'IFID\'\nmodule IFID(clock,Inst,IFIDWrite ,PcPlusFour,InstReg,PcPlusFourReg);\n ^~~~\n : ... Top module \'IDEX\'\nmodule IDEX(clock,WB,M,EX,DataA,DataB,imm_value,RegRs,RegRt,RegRd,WBreg,Mreg,EXreg,DataAreg,\n ^~~~\n : ... Top module \'EXMEM\'\nmodule EXMEM(clock,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);\n ^~~~~\n : ... Top module \'MEMWB\'\nmodule MEMWB(clock,WB,Memout,ALUOut,RegRD,WBreg,Memreg,ALUreg,RegRDreg);\n ^~~~~\n%Error: Exiting due to 1 warning(s)\n' | 5,369 | module | module IFID(clock,Inst,IFIDWrite ,PcPlusFour,InstReg,PcPlusFourReg);
input clock,IFIDWrite;
input [31:0] PcPlusFour,Inst;
output reg [31:0] InstReg, PcPlusFourReg;
initial
begin
InstReg = 0;
PcPlusFourReg = 0;
end
always@(posedge clock)
begin
if(IFIDWrite)
begin
InstReg <= Inst;
PcPlusFourReg <= PcPlusFour;
end
end
endmodule | module IFID(clock,Inst,IFIDWrite ,PcPlusFour,InstReg,PcPlusFourReg); |
input clock,IFIDWrite;
input [31:0] PcPlusFour,Inst;
output reg [31:0] InstReg, PcPlusFourReg;
initial
begin
InstReg = 0;
PcPlusFourReg = 0;
end
always@(posedge clock)
begin
if(IFIDWrite)
begin
InstReg <= Inst;
PcPlusFourReg <= PcPlusFour;
end
end
endmodule | 1 |
4,994 | data/full_repos/permissive/112626266/PIPELINE.v | 112,626,266 | PIPELINE.v | v | 113 | 98 | [] | [] | [] | [(3, 21), (23, 59), (61, 87), (89, 111)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/112626266/PIPELINE.v:23: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'IFID\'\nmodule IFID(clock,Inst,IFIDWrite ,PcPlusFour,InstReg,PcPlusFourReg);\n ^~~~\n : ... Top module \'IDEX\'\nmodule IDEX(clock,WB,M,EX,DataA,DataB,imm_value,RegRs,RegRt,RegRd,WBreg,Mreg,EXreg,DataAreg,\n ^~~~\n : ... Top module \'EXMEM\'\nmodule EXMEM(clock,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);\n ^~~~~\n : ... Top module \'MEMWB\'\nmodule MEMWB(clock,WB,Memout,ALUOut,RegRD,WBreg,Memreg,ALUreg,RegRDreg);\n ^~~~~\n%Error: Exiting due to 1 warning(s)\n' | 5,369 | module | module IDEX(clock,WB,M,EX,DataA,DataB,imm_value,RegRs,RegRt,RegRd,WBreg,Mreg,EXreg,DataAreg,
DataBreg,imm_valuereg,RegRsreg,RegRtreg,RegRdreg);
input clock;
input [1:0] WB;
input [2:0] M;
input [3:0] EX;
input [4:0] RegRs,RegRt,RegRd;
input [31:0] DataA,DataB,imm_value;
output reg [1:0] WBreg;
output reg [2:0] Mreg;
output reg [3:0] EXreg;
output reg [4:0] RegRsreg,RegRtreg,RegRdreg;
output reg [31:0] DataAreg,DataBreg,imm_valuereg;
initial begin
WBreg = 0;
Mreg = 0;
EXreg = 0;
DataAreg = 0;
DataBreg = 0;
imm_valuereg = 0;
RegRsreg = 0;
RegRtreg = 0;
RegRdreg = 0;
end
always@(posedge clock)
begin
WBreg <= WB;
Mreg <= M;
EXreg <= EX;
DataAreg <= DataA;
DataBreg <= DataB;
imm_valuereg <= imm_value;
RegRsreg <= RegRs;
RegRtreg <= RegRt;
RegRdreg <= RegRd;
end
endmodule | module IDEX(clock,WB,M,EX,DataA,DataB,imm_value,RegRs,RegRt,RegRd,WBreg,Mreg,EXreg,DataAreg,
DataBreg,imm_valuereg,RegRsreg,RegRtreg,RegRdreg); |
input clock;
input [1:0] WB;
input [2:0] M;
input [3:0] EX;
input [4:0] RegRs,RegRt,RegRd;
input [31:0] DataA,DataB,imm_value;
output reg [1:0] WBreg;
output reg [2:0] Mreg;
output reg [3:0] EXreg;
output reg [4:0] RegRsreg,RegRtreg,RegRdreg;
output reg [31:0] DataAreg,DataBreg,imm_valuereg;
initial begin
WBreg = 0;
Mreg = 0;
EXreg = 0;
DataAreg = 0;
DataBreg = 0;
imm_valuereg = 0;
RegRsreg = 0;
RegRtreg = 0;
RegRdreg = 0;
end
always@(posedge clock)
begin
WBreg <= WB;
Mreg <= M;
EXreg <= EX;
DataAreg <= DataA;
DataBreg <= DataB;
imm_valuereg <= imm_value;
RegRsreg <= RegRs;
RegRtreg <= RegRt;
RegRdreg <= RegRd;
end
endmodule | 1 |
4,995 | data/full_repos/permissive/112626266/PIPELINE.v | 112,626,266 | PIPELINE.v | v | 113 | 98 | [] | [] | [] | [(3, 21), (23, 59), (61, 87), (89, 111)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/112626266/PIPELINE.v:23: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'IFID\'\nmodule IFID(clock,Inst,IFIDWrite ,PcPlusFour,InstReg,PcPlusFourReg);\n ^~~~\n : ... Top module \'IDEX\'\nmodule IDEX(clock,WB,M,EX,DataA,DataB,imm_value,RegRs,RegRt,RegRd,WBreg,Mreg,EXreg,DataAreg,\n ^~~~\n : ... Top module \'EXMEM\'\nmodule EXMEM(clock,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);\n ^~~~~\n : ... Top module \'MEMWB\'\nmodule MEMWB(clock,WB,Memout,ALUOut,RegRD,WBreg,Memreg,ALUreg,RegRDreg);\n ^~~~~\n%Error: Exiting due to 1 warning(s)\n' | 5,369 | module | module EXMEM(clock,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);
input clock;
input [1:0] WB;
input [2:0] M;
input [4:0] RegRD;
input [31:0] ALUOut,WriteDataIn;
output reg [1:0] WBreg;
output reg [2:0] Mreg;
output reg [31:0] ALUreg,WriteDataOut;
output reg [4:0] RegRDreg;
initial
begin
WBreg=0;
Mreg=0;
ALUreg=0;
WriteDataOut=0;
RegRDreg=0;
end
always@(posedge clock)
begin
WBreg <= WB;
Mreg <= M;
ALUreg <= ALUOut;
RegRDreg <= RegRD;
WriteDataOut <= WriteDataIn;
end
endmodule | module EXMEM(clock,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut); |
input clock;
input [1:0] WB;
input [2:0] M;
input [4:0] RegRD;
input [31:0] ALUOut,WriteDataIn;
output reg [1:0] WBreg;
output reg [2:0] Mreg;
output reg [31:0] ALUreg,WriteDataOut;
output reg [4:0] RegRDreg;
initial
begin
WBreg=0;
Mreg=0;
ALUreg=0;
WriteDataOut=0;
RegRDreg=0;
end
always@(posedge clock)
begin
WBreg <= WB;
Mreg <= M;
ALUreg <= ALUOut;
RegRDreg <= RegRD;
WriteDataOut <= WriteDataIn;
end
endmodule | 1 |
4,996 | data/full_repos/permissive/112626266/PIPELINE.v | 112,626,266 | PIPELINE.v | v | 113 | 98 | [] | [] | [] | [(3, 21), (23, 59), (61, 87), (89, 111)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/112626266/PIPELINE.v:23: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'IFID\'\nmodule IFID(clock,Inst,IFIDWrite ,PcPlusFour,InstReg,PcPlusFourReg);\n ^~~~\n : ... Top module \'IDEX\'\nmodule IDEX(clock,WB,M,EX,DataA,DataB,imm_value,RegRs,RegRt,RegRd,WBreg,Mreg,EXreg,DataAreg,\n ^~~~\n : ... Top module \'EXMEM\'\nmodule EXMEM(clock,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);\n ^~~~~\n : ... Top module \'MEMWB\'\nmodule MEMWB(clock,WB,Memout,ALUOut,RegRD,WBreg,Memreg,ALUreg,RegRDreg);\n ^~~~~\n%Error: Exiting due to 1 warning(s)\n' | 5,369 | module | module MEMWB(clock,WB,Memout,ALUOut,RegRD,WBreg,Memreg,ALUreg,RegRDreg);
input clock;
input [1:0] WB;
input [4:0] RegRD;
input [31:0] Memout,ALUOut;
output reg [1:0] WBreg;
output reg [31:0] Memreg,ALUreg;
output reg [4:0] RegRDreg;
initial
begin
WBreg = 0;
Memreg = 0;
ALUreg = 0;
RegRDreg = 0;
end
always@(posedge clock)
begin
WBreg <= WB;
Memreg <= Memout;
ALUreg <= ALUOut;
RegRDreg <= RegRD;
end
endmodule | module MEMWB(clock,WB,Memout,ALUOut,RegRD,WBreg,Memreg,ALUreg,RegRDreg); |
input clock;
input [1:0] WB;
input [4:0] RegRD;
input [31:0] Memout,ALUOut;
output reg [1:0] WBreg;
output reg [31:0] Memreg,ALUreg;
output reg [4:0] RegRDreg;
initial
begin
WBreg = 0;
Memreg = 0;
ALUreg = 0;
RegRDreg = 0;
end
always@(posedge clock)
begin
WBreg <= WB;
Memreg <= Memout;
ALUreg <= ALUOut;
RegRDreg <= RegRD;
end
endmodule | 1 |
4,997 | data/full_repos/permissive/112823543/Avalon_LedPanel/LedMemory_Avalon.v | 112,823,543 | LedMemory_Avalon.v | v | 142 | 137 | [] | [] | [] | [(1, 141)] | null | null | 1: b"%Error: data/full_repos/permissive/112823543/Avalon_LedPanel/LedMemory_Avalon.v:116: Cannot find file containing module: 'LedPanel'\n LedPanel #(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112823543/Avalon_LedPanel,data/full_repos/permissive/112823543/LedPanel\n data/full_repos/permissive/112823543/Avalon_LedPanel,data/full_repos/permissive/112823543/LedPanel.v\n data/full_repos/permissive/112823543/Avalon_LedPanel,data/full_repos/permissive/112823543/LedPanel.sv\n LedPanel\n LedPanel.v\n LedPanel.sv\n obj_dir/LedPanel\n obj_dir/LedPanel.v\n obj_dir/LedPanel.sv\n%Error: Exiting due to 1 error(s)\n" | 5,370 | module | module LedPanel_Avalon (
input wire clock200,
input wire reset,
input wire s0_address,
input wire s0_write,
input wire [31:0] s0_writedata,
input wire s0_read,
output reg [31:0] s0_readdata,
output wire irq,
input wire [DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES:0] s1_address,
input wire s1_write,
input wire [31:0] s1_writedata,
output wire [1:0] led_red,
output wire [1:0] led_green,
output wire [1:0] led_blue,
output wire [3:0] led_addr,
output wire led_clock,
output wire led_blank,
output wire led_latch,
input wire debug_clock
);
parameter DISPLAY_ROWS_LINES = 4;
parameter DISPLAY_COLS_LINES = 6;
parameter COLOR_BITS = 8;
reg backbuffer;
reg flip_backbuffer;
wire v_sync;
wire [7:0] reg_stat = {flip_backbuffer, 5'b00000, backbuffer, v_sync};
reg [7:0] reg_irq;
wire irq_ena = reg_irq[7];
wire irq_latch = reg_irq[0];
reg [1:0] v_sync_edge_detect;
reg req_backbuffer_flip;
assign irq = irq_ena && irq_latch;
always @(posedge clock200)
begin
if (reset) begin
backbuffer <= 1'b0;
flip_backbuffer <= 1'b0;
reg_irq <= 8'h00;
v_sync_edge_detect <= 2'b00;
end else begin
v_sync_edge_detect <= {v_sync_edge_detect[0], v_sync};
if (s0_address) begin
if (s0_read) begin
s0_readdata <= {24'b0, reg_irq};
end else if (s0_write) begin
reg_irq[7] <= s0_writedata[7];
reg_irq[0] <= 1'b0;
end
end else begin
if (s0_read) begin
s0_readdata <= {24'b0, reg_stat};
end else if (s0_write) begin
flip_backbuffer <= s0_writedata[7];
end
end
if (v_sync_edge_detect == 2'b01) begin
reg_irq[0] <= 1'b1;
end
if (req_backbuffer_flip) begin
backbuffer <= ~backbuffer;
flip_backbuffer <= 0;
end
end
end
always @(posedge debug_clock)
begin
if (reset) begin
req_backbuffer_flip <= 1'b0;
end else begin
if ((v_sync_edge_detect == 2'b01) && (flip_backbuffer) ) begin
req_backbuffer_flip <= 1'b1;
end else req_backbuffer_flip <= 1'b0;
end
end
LedPanel #(
.COLOR_BITS(COLOR_BITS),
.DISPLAY_ROWS_LINES(DISPLAY_ROWS_LINES),
.DISPLAY_COLS_LINES(DISPLAY_COLS_LINES)
) panel(
.CLK(debug_clock),
.RST(reset),
.RED(led_red),
.GREEN(led_green),
.BLUE(led_blue),
.ADDR(led_addr),
.CLK_LED(led_clock),
.BLANK(led_blank),
.LATCH(led_latch),
.memAddrIn(s1_address),
.memDataIn(s1_writedata[23:0]),
.memWrite(s1_write),
.v_sync(v_sync),
.backbuffer(backbuffer)
);
endmodule | module LedPanel_Avalon (
input wire clock200,
input wire reset,
input wire s0_address,
input wire s0_write,
input wire [31:0] s0_writedata,
input wire s0_read,
output reg [31:0] s0_readdata,
output wire irq,
input wire [DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES:0] s1_address,
input wire s1_write,
input wire [31:0] s1_writedata,
output wire [1:0] led_red,
output wire [1:0] led_green,
output wire [1:0] led_blue,
output wire [3:0] led_addr,
output wire led_clock,
output wire led_blank,
output wire led_latch,
input wire debug_clock
); |
parameter DISPLAY_ROWS_LINES = 4;
parameter DISPLAY_COLS_LINES = 6;
parameter COLOR_BITS = 8;
reg backbuffer;
reg flip_backbuffer;
wire v_sync;
wire [7:0] reg_stat = {flip_backbuffer, 5'b00000, backbuffer, v_sync};
reg [7:0] reg_irq;
wire irq_ena = reg_irq[7];
wire irq_latch = reg_irq[0];
reg [1:0] v_sync_edge_detect;
reg req_backbuffer_flip;
assign irq = irq_ena && irq_latch;
always @(posedge clock200)
begin
if (reset) begin
backbuffer <= 1'b0;
flip_backbuffer <= 1'b0;
reg_irq <= 8'h00;
v_sync_edge_detect <= 2'b00;
end else begin
v_sync_edge_detect <= {v_sync_edge_detect[0], v_sync};
if (s0_address) begin
if (s0_read) begin
s0_readdata <= {24'b0, reg_irq};
end else if (s0_write) begin
reg_irq[7] <= s0_writedata[7];
reg_irq[0] <= 1'b0;
end
end else begin
if (s0_read) begin
s0_readdata <= {24'b0, reg_stat};
end else if (s0_write) begin
flip_backbuffer <= s0_writedata[7];
end
end
if (v_sync_edge_detect == 2'b01) begin
reg_irq[0] <= 1'b1;
end
if (req_backbuffer_flip) begin
backbuffer <= ~backbuffer;
flip_backbuffer <= 0;
end
end
end
always @(posedge debug_clock)
begin
if (reset) begin
req_backbuffer_flip <= 1'b0;
end else begin
if ((v_sync_edge_detect == 2'b01) && (flip_backbuffer) ) begin
req_backbuffer_flip <= 1'b1;
end else req_backbuffer_flip <= 1'b0;
end
end
LedPanel #(
.COLOR_BITS(COLOR_BITS),
.DISPLAY_ROWS_LINES(DISPLAY_ROWS_LINES),
.DISPLAY_COLS_LINES(DISPLAY_COLS_LINES)
) panel(
.CLK(debug_clock),
.RST(reset),
.RED(led_red),
.GREEN(led_green),
.BLUE(led_blue),
.ADDR(led_addr),
.CLK_LED(led_clock),
.BLANK(led_blank),
.LATCH(led_latch),
.memAddrIn(s1_address),
.memDataIn(s1_writedata[23:0]),
.memWrite(s1_write),
.v_sync(v_sync),
.backbuffer(backbuffer)
);
endmodule | 0 |
4,998 | data/full_repos/permissive/112823543/Avalon_LedPanel/LedPanel.v | 112,823,543 | LedPanel.v | v | 261 | 234 | [] | [] | [] | [(23, 260)] | null | null | 1: b"%Error: data/full_repos/permissive/112823543/Avalon_LedPanel/LedPanel.v:97: Cannot find file containing module: 'LedPanelMemory'\n LedPanelMemory #(\n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112823543/Avalon_LedPanel,data/full_repos/permissive/112823543/LedPanelMemory\n data/full_repos/permissive/112823543/Avalon_LedPanel,data/full_repos/permissive/112823543/LedPanelMemory.v\n data/full_repos/permissive/112823543/Avalon_LedPanel,data/full_repos/permissive/112823543/LedPanelMemory.sv\n LedPanelMemory\n LedPanelMemory.v\n LedPanelMemory.sv\n obj_dir/LedPanelMemory\n obj_dir/LedPanelMemory.v\n obj_dir/LedPanelMemory.sv\n%Error: data/full_repos/permissive/112823543/Avalon_LedPanel/LedPanel.v:112: Cannot find file containing module: 'LedPanelMemory'\n LedPanelMemory #(\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 5,371 | module | module LedPanel(
input wire CLK,
input wire RST,
output wire [1:0] RED,
output wire [1:0] GREEN,
output wire [1:0] BLUE,
output reg [3:0] ADDR,
output reg CLK_LED,
output reg BLANK,
output reg LATCH,
input wire[DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES:0] memAddrIn,
input wire [23:0] memDataIn,
input wire memWrite,
output reg v_sync,
input wire backbuffer
);
parameter COLOR_BITS = 8;
parameter DISPLAY_ROWS_LINES = 4;
parameter DISPLAY_COLS_LINES = 6;
reg [1:0] clkReg;
wire CLK_50 = clkReg[1];
reg [DISPLAY_COLS_LINES-1:0] col;
reg [DISPLAY_ROWS_LINES-1:0] row;
reg [2:0] bitplane;
wire [COLOR_BITS-1:0] redUpper, redLower, greenUpper, greenLower, blueUpper, blueLower;
wire [3*COLOR_BITS-1:0] memDataUpper, memDataLower;
wire [DISPLAY_COLS_LINES+DISPLAY_ROWS_LINES-1:0] memAddr;
assign redUpper = memDataUpper[COLOR_BITS-1:0];
assign redLower = memDataLower[COLOR_BITS-1:0];
assign greenUpper = memDataUpper[2*COLOR_BITS-1:COLOR_BITS];
assign greenLower = memDataLower[2*COLOR_BITS-1:COLOR_BITS];
assign blueUpper = memDataUpper[3*COLOR_BITS-1:2*COLOR_BITS];
assign blueLower = memDataLower[3*COLOR_BITS-1:2*COLOR_BITS];
assign RED[0] = redUpper[bitplane];
assign RED[1] = redLower[bitplane];
assign GREEN[0] = greenUpper[bitplane];
assign GREEN[1] = greenLower[bitplane];
assign BLUE[0] = blueUpper[bitplane];
assign BLUE[1] = blueLower[bitplane];
localparam s_00 = 2'b00,
s_01 = 2'b01,
s_10 = 2'b10,
s_11 = 2'b11;
localparam s_UNBLANK = 3'b000,
s_WAIT = 3'b001,
s_BLANK = 3'b010,
s_LATCH = 3'b011,
s_DELATCH = 3'b100;
reg [2:0] state;
reg sig_shifting_ready;
reg shifting_ena;
reg [13:0] display_counter;
reg [DISPLAY_ROWS_LINES-1:0] old_addr;
assign memAddr = {row, col};
wire memUpperCS = (!memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES] && memWrite) ? 1'b1 : 1'b0;
wire memLowerCS = ( memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES] && memWrite) ? 1'b1 : 1'b0;
LedPanelMemory #(
.ADDR_LINES(DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES+1),
.DATA_LINES(3*COLOR_BITS)
) UpperMemory (
.clock(CLK),
.reset(RST),
.Address_a({backbuffer, memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES-1:0]}),
.DataIn_a(memDataIn),
.Write_a(memUpperCS),
.Address_b({!backbuffer, memAddr}),
.DataOut_b(memDataUpper)
);
LedPanelMemory #(
.ADDR_LINES(DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES+1),
.DATA_LINES(3*COLOR_BITS)
) LowerMemory (
.clock(CLK),
.reset(RST),
.Address_a({backbuffer, memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES-1:0]}),
.DataIn_a(memDataIn),
.Write_a(memLowerCS),
.Address_b({!backbuffer, memAddr}),
.DataOut_b(memDataLower)
);
always @(negedge CLK)
begin
case (clkReg)
2'b00: clkReg = 2'b01;
2'b01: clkReg = 2'b10;
2'b10: clkReg = 2'b11;
2'b11: clkReg = 2'b00;
default: clkReg = 2'b00;
endcase
end
always @(posedge CLK_50)
begin
if (RST) begin
col = {DISPLAY_COLS_LINES{1'b0}};
row = {DISPLAY_ROWS_LINES{1'b0}};
CLK_LED <= 0;
bitplane = 3'b000;
sig_shifting_ready <= 0;
v_sync <= 0;
end else begin
CLK_LED <= 0;
v_sync <= 0;
if (state == s_WAIT) begin
if ((shifting_ena == 1) && (sig_shifting_ready == 0) ) begin
if (CLK_LED == 1) begin
col = col + 1;
if (col == 0) begin
sig_shifting_ready <= 1;
bitplane = bitplane + 1;
if (bitplane == 0) begin
row = row + 1;
if (row == 0) begin
v_sync <= 1;
end
end
end
end
CLK_LED <= ~CLK_LED;
end
end else sig_shifting_ready <= 0;
end
end
always @(posedge CLK_50)
begin
if (RST) begin
BLANK <= 0;
ADDR = {DISPLAY_ROWS_LINES{1'b0}};
old_addr = 0;
end else begin
if (state == s_BLANK) begin
BLANK <= 1;
ADDR = old_addr;
old_addr = row;
end else if (state == s_UNBLANK) begin
BLANK <= 0;
end
end
end
always @(posedge CLK_50)
begin
if (RST)
LATCH <= 1'b1;
else begin
if (state == s_LATCH)
LATCH <= 1'b1;
else if (state == s_DELATCH)
LATCH <= 1'b0;
end
end
reg sig_wait_done;
always @(posedge CLK_50)
begin
if (RST) begin
display_counter <= 123;
shifting_ena <= 0;
sig_wait_done <= 0;
end else if (state == s_WAIT) begin
if (display_counter != 0) begin
display_counter <= display_counter - 1;
end else if (sig_shifting_ready) begin
shifting_ena <= 0;
sig_wait_done <= 1;
end
end else if (state == s_UNBLANK) begin
case (bitplane)
0: display_counter = 122 << 7;
1: display_counter = 122 << 0;
2: display_counter = 122 << 1;
3: display_counter = 122 << 2;
4: display_counter = 122 << 3;
5: display_counter = 122 << 4;
6: display_counter = 122 << 5;
7: display_counter = 122 << 6;
default: display_counter = 122 << 0;
endcase
shifting_ena <= 1;
end else sig_wait_done <= 0;
end
always @(posedge CLK_50)
begin
if (RST) begin state <= s_UNBLANK;
end else begin
case (state)
s_UNBLANK: state <= s_WAIT;
s_WAIT: if (sig_wait_done == 1) state <= s_BLANK;
s_BLANK: state <= s_LATCH;
s_LATCH: state <= s_DELATCH;
s_DELATCH: state <= s_UNBLANK;
endcase
end
end
endmodule | module LedPanel(
input wire CLK,
input wire RST,
output wire [1:0] RED,
output wire [1:0] GREEN,
output wire [1:0] BLUE,
output reg [3:0] ADDR,
output reg CLK_LED,
output reg BLANK,
output reg LATCH,
input wire[DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES:0] memAddrIn,
input wire [23:0] memDataIn,
input wire memWrite,
output reg v_sync,
input wire backbuffer
); |
parameter COLOR_BITS = 8;
parameter DISPLAY_ROWS_LINES = 4;
parameter DISPLAY_COLS_LINES = 6;
reg [1:0] clkReg;
wire CLK_50 = clkReg[1];
reg [DISPLAY_COLS_LINES-1:0] col;
reg [DISPLAY_ROWS_LINES-1:0] row;
reg [2:0] bitplane;
wire [COLOR_BITS-1:0] redUpper, redLower, greenUpper, greenLower, blueUpper, blueLower;
wire [3*COLOR_BITS-1:0] memDataUpper, memDataLower;
wire [DISPLAY_COLS_LINES+DISPLAY_ROWS_LINES-1:0] memAddr;
assign redUpper = memDataUpper[COLOR_BITS-1:0];
assign redLower = memDataLower[COLOR_BITS-1:0];
assign greenUpper = memDataUpper[2*COLOR_BITS-1:COLOR_BITS];
assign greenLower = memDataLower[2*COLOR_BITS-1:COLOR_BITS];
assign blueUpper = memDataUpper[3*COLOR_BITS-1:2*COLOR_BITS];
assign blueLower = memDataLower[3*COLOR_BITS-1:2*COLOR_BITS];
assign RED[0] = redUpper[bitplane];
assign RED[1] = redLower[bitplane];
assign GREEN[0] = greenUpper[bitplane];
assign GREEN[1] = greenLower[bitplane];
assign BLUE[0] = blueUpper[bitplane];
assign BLUE[1] = blueLower[bitplane];
localparam s_00 = 2'b00,
s_01 = 2'b01,
s_10 = 2'b10,
s_11 = 2'b11;
localparam s_UNBLANK = 3'b000,
s_WAIT = 3'b001,
s_BLANK = 3'b010,
s_LATCH = 3'b011,
s_DELATCH = 3'b100;
reg [2:0] state;
reg sig_shifting_ready;
reg shifting_ena;
reg [13:0] display_counter;
reg [DISPLAY_ROWS_LINES-1:0] old_addr;
assign memAddr = {row, col};
wire memUpperCS = (!memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES] && memWrite) ? 1'b1 : 1'b0;
wire memLowerCS = ( memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES] && memWrite) ? 1'b1 : 1'b0;
LedPanelMemory #(
.ADDR_LINES(DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES+1),
.DATA_LINES(3*COLOR_BITS)
) UpperMemory (
.clock(CLK),
.reset(RST),
.Address_a({backbuffer, memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES-1:0]}),
.DataIn_a(memDataIn),
.Write_a(memUpperCS),
.Address_b({!backbuffer, memAddr}),
.DataOut_b(memDataUpper)
);
LedPanelMemory #(
.ADDR_LINES(DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES+1),
.DATA_LINES(3*COLOR_BITS)
) LowerMemory (
.clock(CLK),
.reset(RST),
.Address_a({backbuffer, memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES-1:0]}),
.DataIn_a(memDataIn),
.Write_a(memLowerCS),
.Address_b({!backbuffer, memAddr}),
.DataOut_b(memDataLower)
);
always @(negedge CLK)
begin
case (clkReg)
2'b00: clkReg = 2'b01;
2'b01: clkReg = 2'b10;
2'b10: clkReg = 2'b11;
2'b11: clkReg = 2'b00;
default: clkReg = 2'b00;
endcase
end
always @(posedge CLK_50)
begin
if (RST) begin
col = {DISPLAY_COLS_LINES{1'b0}};
row = {DISPLAY_ROWS_LINES{1'b0}};
CLK_LED <= 0;
bitplane = 3'b000;
sig_shifting_ready <= 0;
v_sync <= 0;
end else begin
CLK_LED <= 0;
v_sync <= 0;
if (state == s_WAIT) begin
if ((shifting_ena == 1) && (sig_shifting_ready == 0) ) begin
if (CLK_LED == 1) begin
col = col + 1;
if (col == 0) begin
sig_shifting_ready <= 1;
bitplane = bitplane + 1;
if (bitplane == 0) begin
row = row + 1;
if (row == 0) begin
v_sync <= 1;
end
end
end
end
CLK_LED <= ~CLK_LED;
end
end else sig_shifting_ready <= 0;
end
end
always @(posedge CLK_50)
begin
if (RST) begin
BLANK <= 0;
ADDR = {DISPLAY_ROWS_LINES{1'b0}};
old_addr = 0;
end else begin
if (state == s_BLANK) begin
BLANK <= 1;
ADDR = old_addr;
old_addr = row;
end else if (state == s_UNBLANK) begin
BLANK <= 0;
end
end
end
always @(posedge CLK_50)
begin
if (RST)
LATCH <= 1'b1;
else begin
if (state == s_LATCH)
LATCH <= 1'b1;
else if (state == s_DELATCH)
LATCH <= 1'b0;
end
end
reg sig_wait_done;
always @(posedge CLK_50)
begin
if (RST) begin
display_counter <= 123;
shifting_ena <= 0;
sig_wait_done <= 0;
end else if (state == s_WAIT) begin
if (display_counter != 0) begin
display_counter <= display_counter - 1;
end else if (sig_shifting_ready) begin
shifting_ena <= 0;
sig_wait_done <= 1;
end
end else if (state == s_UNBLANK) begin
case (bitplane)
0: display_counter = 122 << 7;
1: display_counter = 122 << 0;
2: display_counter = 122 << 1;
3: display_counter = 122 << 2;
4: display_counter = 122 << 3;
5: display_counter = 122 << 4;
6: display_counter = 122 << 5;
7: display_counter = 122 << 6;
default: display_counter = 122 << 0;
endcase
shifting_ena <= 1;
end else sig_wait_done <= 0;
end
always @(posedge CLK_50)
begin
if (RST) begin state <= s_UNBLANK;
end else begin
case (state)
s_UNBLANK: state <= s_WAIT;
s_WAIT: if (sig_wait_done == 1) state <= s_BLANK;
s_BLANK: state <= s_LATCH;
s_LATCH: state <= s_DELATCH;
s_DELATCH: state <= s_UNBLANK;
endcase
end
end
endmodule | 0 |
4,999 | data/full_repos/permissive/112823543/Avalon_LedPanel/LedPanelMemory.v | 112,823,543 | LedPanelMemory.v | v | 35 | 52 | [] | [] | [] | [(1, 34)] | null | data/verilator_xmls/41d8dc0c-0a0b-4e4b-8263-4c6e96382513.xml | null | 5,372 | module | module LedPanelMemory(
input wire clock,
input wire reset,
input wire [ADDR_LINES-1:0] Address_a,
input wire [DATA_LINES-1:0] DataIn_a,
input wire Write_a,
input wire [ADDR_LINES-1:0] Address_b,
output reg [DATA_LINES-1:0] DataOut_b
);
parameter ADDR_LINES = 10;
parameter DATA_LINES = 24;
reg [DATA_LINES-1:0] memory[(1<<ADDR_LINES)-1:0];
always @(posedge clock)
begin
if (reset) begin
DataOut_b <= {DATA_LINES{1'bZ}};
end else begin
if (Write_a) begin
memory[Address_a] <= DataIn_a;
end
DataOut_b <= memory[Address_b];
end
end
endmodule | module LedPanelMemory(
input wire clock,
input wire reset,
input wire [ADDR_LINES-1:0] Address_a,
input wire [DATA_LINES-1:0] DataIn_a,
input wire Write_a,
input wire [ADDR_LINES-1:0] Address_b,
output reg [DATA_LINES-1:0] DataOut_b
); |
parameter ADDR_LINES = 10;
parameter DATA_LINES = 24;
reg [DATA_LINES-1:0] memory[(1<<ADDR_LINES)-1:0];
always @(posedge clock)
begin
if (reset) begin
DataOut_b <= {DATA_LINES{1'bZ}};
end else begin
if (Write_a) begin
memory[Address_a] <= DataIn_a;
end
DataOut_b <= memory[Address_b];
end
end
endmodule | 0 |
5,000 | data/full_repos/permissive/112823543/Avalon_LedPanel _Client_Server/LedMemoryClient_Avalon.v | 112,823,543 | LedMemoryClient_Avalon.v | v | 213 | 143 | [] | [] | [] | [(5, 212)] | null | null | 1: b'%Error: Cannot find file containing module: _Client_Server,data/full_repos/permissive/112823543\n ... Looked in:\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.v\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.sv\n _Client_Server,data/full_repos/permissive/112823543\n _Client_Server,data/full_repos/permissive/112823543.v\n _Client_Server,data/full_repos/permissive/112823543.sv\n obj_dir/_Client_Server,data/full_repos/permissive/112823543\n obj_dir/_Client_Server,data/full_repos/permissive/112823543.v\n obj_dir/_Client_Server,data/full_repos/permissive/112823543.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/112823543/Avalon_LedPanel\n%Error: Cannot find file containing module: _Client_Server/LedMemoryClient_Avalon.v\n%Error: Exiting due to 3 error(s)\n' | 5,373 | module | module LedPanelClient_Avalon #(
parameter DISPLAY_ROWS_LINES = 4,
parameter DISPLAY_COLS_LINES = 6,
parameter COLOR_BITS = 8
)
(
input wire clock,
input wire reset,
input wire [DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES:0] s1_address,
input wire s1_write,
input wire [31:0] s1_writedata,
input wire [COLOR_BITS-1:0] s2_address,
input wire s2_write,
input wire [31:0] s2_writedata,
output reg [1:0] led_red,
output reg [1:0] led_green,
output reg [1:0] led_blue,
output reg [3:0] led_addr,
output reg led_clock,
output reg led_blank,
output reg led_latch,
input wire ext_clock200,
input wire [DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES-1:0] memAddrMst,
input wire [2:0] bitplaneMst,
input wire backbufferMst,
input wire [3:0] ADDR_MST,
input wire LATCH_MST,
input wire CLK_LED_MST,
input wire BLANK_MST
);
wire [31:0] rgb_upper, rgb_lower;
wire [COLOR_BITS-1:0] red_upper, red_lower, green_upper, green_lower, blue_upper, blue_lower;
reg [COLOR_BITS-1:0] red_upper_q, red_lower_q, green_upper_q, green_lower_q, blue_upper_q, blue_lower_q;
wire [COLOR_BITS-1:0] red_upper_gamma, red_lower_gamma, green_upper_gamma, green_lower_gamma, blue_upper_gamma, blue_lower_gamma;
wire [1:0] led_red_s, led_green_s, led_blue_s;
wire [3:0] led_addr_s;
wire led_clock_s, led_blank_s, led_latch_s;
reg [1:0] led_red_q, led_green_q, led_blue_q;
reg [3:0] led_addr_q;
reg led_clock_q, led_blank_q, led_latch_q;
wire wren_upper = !s1_address[DISPLAY_COLS_LINES+DISPLAY_ROWS_LINES] & s1_write;
wire wren_lower = s1_address[DISPLAY_COLS_LINES+DISPLAY_ROWS_LINES] & s1_write;
onchipmem #(.ADRESS_WIDTH(11)) upper_memory(
.wrclock(clock),
.wren(wren_upper),
.wraddress({backbufferMst, s1_address[DISPLAY_COLS_LINES+DISPLAY_ROWS_LINES-1:0]}),
.data(s1_writedata),
.rdclock(ext_clock200),
.rdaddress({!backbufferMst,memAddrMst}),
.q(rgb_upper)
);
onchipmem #(.ADRESS_WIDTH(11)) lower_memory(
.wrclock(clock),
.wren(wren_lower),
.wraddress({backbufferMst, s1_address[DISPLAY_COLS_LINES+DISPLAY_ROWS_LINES-1:0]}),
.data(s1_writedata),
.rdclock(ext_clock200),
.rdaddress({!backbufferMst,memAddrMst}),
.q(rgb_lower)
);
assign red_upper = rgb_upper[COLOR_BITS-1:0];
assign red_lower = rgb_lower[COLOR_BITS-1:0];
assign green_upper = rgb_upper[2*COLOR_BITS-1:COLOR_BITS];
assign green_lower = rgb_lower[2*COLOR_BITS-1:COLOR_BITS];
assign blue_upper = rgb_upper[3*COLOR_BITS-1:2*COLOR_BITS];
assign blue_lower = rgb_lower[3*COLOR_BITS-1:2*COLOR_BITS];
onchipmem #(.ADRESS_WIDTH(COLOR_BITS)) gamma_red_upper(
.wrclock(clock),
.wren(s2_write),
.wraddress(s2_address),
.data(s2_writedata[COLOR_BITS-1:0]),
.rdclock(ext_clock200),
.rdaddress(red_upper),
.q(red_upper_gamma)
);
onchipmem #(.ADRESS_WIDTH(COLOR_BITS)) gamma_green_upper(
.wrclock(clock),
.wren(s2_write),
.wraddress(s2_address),
.data(s2_writedata[COLOR_BITS-1:0]),
.rdclock(ext_clock200),
.rdaddress(green_upper),
.q(green_upper_gamma)
);
onchipmem #(.ADRESS_WIDTH(COLOR_BITS)) gamma_blue_upper(
.wrclock(clock),
.wren(s2_write),
.wraddress(s2_address),
.data(s2_writedata[COLOR_BITS-1:0]),
.rdclock(ext_clock200),
.rdaddress(blue_upper),
.q(blue_upper_gamma)
);
onchipmem #(.ADRESS_WIDTH(COLOR_BITS)) gamma_red_lower(
.wrclock(clock),
.wren(s2_write),
.wraddress(s2_address),
.data(s2_writedata[COLOR_BITS-1:0]),
.rdclock(ext_clock200),
.rdaddress(red_lower),
.q(red_lower_gamma)
);
onchipmem #(.ADRESS_WIDTH(COLOR_BITS)) gamma_green_lower(
.wrclock(clock),
.wren(s2_write),
.wraddress(s2_address),
.data(s2_writedata[COLOR_BITS-1:0]),
.rdclock(ext_clock200),
.rdaddress(green_lower),
.q(green_lower_gamma)
);
onchipmem #(.ADRESS_WIDTH(COLOR_BITS)) gamma_blue_lower(
.wrclock(clock),
.wren(s2_write),
.wraddress(s2_address),
.data(s2_writedata[COLOR_BITS-1:0]),
.rdclock(ext_clock200),
.rdaddress(blue_lower),
.q(blue_lower_gamma)
);
always @(posedge CLK_LED_MST)
begin
led_red <= {red_lower_gamma[bitplaneMst], red_upper_gamma[bitplaneMst]};
led_green <= {green_lower_gamma[bitplaneMst], green_upper_gamma[bitplaneMst]};
led_blue <= {blue_lower_gamma[bitplaneMst], blue_upper_gamma[bitplaneMst]};
end
always @(posedge ext_clock200)
begin
if (reset) begin
led_addr <= 4'b0;
led_latch <= 1'b0;
led_blank <= 1'b1;
led_clock <= 1'b0;
led_red_q <= 2'b0;
led_green_q <= 2'b0;
led_blue_q <= 2'b0;
led_latch_q <= 1'b0;
led_clock_q <= 1'b0;
led_blank_q <= 1'b0;
end else begin
led_addr_q <= ADDR_MST;
led_clock_q <= CLK_LED_MST;
led_blank_q <= BLANK_MST;
led_latch_q <= LATCH_MST;
led_addr <= led_addr_q;
led_blank <= led_blank_q;
led_latch <= led_latch_q;
led_clock <= led_clock_q;
end
end
endmodule | module LedPanelClient_Avalon #(
parameter DISPLAY_ROWS_LINES = 4,
parameter DISPLAY_COLS_LINES = 6,
parameter COLOR_BITS = 8
)
(
input wire clock,
input wire reset,
input wire [DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES:0] s1_address,
input wire s1_write,
input wire [31:0] s1_writedata,
input wire [COLOR_BITS-1:0] s2_address,
input wire s2_write,
input wire [31:0] s2_writedata,
output reg [1:0] led_red,
output reg [1:0] led_green,
output reg [1:0] led_blue,
output reg [3:0] led_addr,
output reg led_clock,
output reg led_blank,
output reg led_latch,
input wire ext_clock200,
input wire [DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES-1:0] memAddrMst,
input wire [2:0] bitplaneMst,
input wire backbufferMst,
input wire [3:0] ADDR_MST,
input wire LATCH_MST,
input wire CLK_LED_MST,
input wire BLANK_MST
); |
wire [31:0] rgb_upper, rgb_lower;
wire [COLOR_BITS-1:0] red_upper, red_lower, green_upper, green_lower, blue_upper, blue_lower;
reg [COLOR_BITS-1:0] red_upper_q, red_lower_q, green_upper_q, green_lower_q, blue_upper_q, blue_lower_q;
wire [COLOR_BITS-1:0] red_upper_gamma, red_lower_gamma, green_upper_gamma, green_lower_gamma, blue_upper_gamma, blue_lower_gamma;
wire [1:0] led_red_s, led_green_s, led_blue_s;
wire [3:0] led_addr_s;
wire led_clock_s, led_blank_s, led_latch_s;
reg [1:0] led_red_q, led_green_q, led_blue_q;
reg [3:0] led_addr_q;
reg led_clock_q, led_blank_q, led_latch_q;
wire wren_upper = !s1_address[DISPLAY_COLS_LINES+DISPLAY_ROWS_LINES] & s1_write;
wire wren_lower = s1_address[DISPLAY_COLS_LINES+DISPLAY_ROWS_LINES] & s1_write;
onchipmem #(.ADRESS_WIDTH(11)) upper_memory(
.wrclock(clock),
.wren(wren_upper),
.wraddress({backbufferMst, s1_address[DISPLAY_COLS_LINES+DISPLAY_ROWS_LINES-1:0]}),
.data(s1_writedata),
.rdclock(ext_clock200),
.rdaddress({!backbufferMst,memAddrMst}),
.q(rgb_upper)
);
onchipmem #(.ADRESS_WIDTH(11)) lower_memory(
.wrclock(clock),
.wren(wren_lower),
.wraddress({backbufferMst, s1_address[DISPLAY_COLS_LINES+DISPLAY_ROWS_LINES-1:0]}),
.data(s1_writedata),
.rdclock(ext_clock200),
.rdaddress({!backbufferMst,memAddrMst}),
.q(rgb_lower)
);
assign red_upper = rgb_upper[COLOR_BITS-1:0];
assign red_lower = rgb_lower[COLOR_BITS-1:0];
assign green_upper = rgb_upper[2*COLOR_BITS-1:COLOR_BITS];
assign green_lower = rgb_lower[2*COLOR_BITS-1:COLOR_BITS];
assign blue_upper = rgb_upper[3*COLOR_BITS-1:2*COLOR_BITS];
assign blue_lower = rgb_lower[3*COLOR_BITS-1:2*COLOR_BITS];
onchipmem #(.ADRESS_WIDTH(COLOR_BITS)) gamma_red_upper(
.wrclock(clock),
.wren(s2_write),
.wraddress(s2_address),
.data(s2_writedata[COLOR_BITS-1:0]),
.rdclock(ext_clock200),
.rdaddress(red_upper),
.q(red_upper_gamma)
);
onchipmem #(.ADRESS_WIDTH(COLOR_BITS)) gamma_green_upper(
.wrclock(clock),
.wren(s2_write),
.wraddress(s2_address),
.data(s2_writedata[COLOR_BITS-1:0]),
.rdclock(ext_clock200),
.rdaddress(green_upper),
.q(green_upper_gamma)
);
onchipmem #(.ADRESS_WIDTH(COLOR_BITS)) gamma_blue_upper(
.wrclock(clock),
.wren(s2_write),
.wraddress(s2_address),
.data(s2_writedata[COLOR_BITS-1:0]),
.rdclock(ext_clock200),
.rdaddress(blue_upper),
.q(blue_upper_gamma)
);
onchipmem #(.ADRESS_WIDTH(COLOR_BITS)) gamma_red_lower(
.wrclock(clock),
.wren(s2_write),
.wraddress(s2_address),
.data(s2_writedata[COLOR_BITS-1:0]),
.rdclock(ext_clock200),
.rdaddress(red_lower),
.q(red_lower_gamma)
);
onchipmem #(.ADRESS_WIDTH(COLOR_BITS)) gamma_green_lower(
.wrclock(clock),
.wren(s2_write),
.wraddress(s2_address),
.data(s2_writedata[COLOR_BITS-1:0]),
.rdclock(ext_clock200),
.rdaddress(green_lower),
.q(green_lower_gamma)
);
onchipmem #(.ADRESS_WIDTH(COLOR_BITS)) gamma_blue_lower(
.wrclock(clock),
.wren(s2_write),
.wraddress(s2_address),
.data(s2_writedata[COLOR_BITS-1:0]),
.rdclock(ext_clock200),
.rdaddress(blue_lower),
.q(blue_lower_gamma)
);
always @(posedge CLK_LED_MST)
begin
led_red <= {red_lower_gamma[bitplaneMst], red_upper_gamma[bitplaneMst]};
led_green <= {green_lower_gamma[bitplaneMst], green_upper_gamma[bitplaneMst]};
led_blue <= {blue_lower_gamma[bitplaneMst], blue_upper_gamma[bitplaneMst]};
end
always @(posedge ext_clock200)
begin
if (reset) begin
led_addr <= 4'b0;
led_latch <= 1'b0;
led_blank <= 1'b1;
led_clock <= 1'b0;
led_red_q <= 2'b0;
led_green_q <= 2'b0;
led_blue_q <= 2'b0;
led_latch_q <= 1'b0;
led_clock_q <= 1'b0;
led_blank_q <= 1'b0;
end else begin
led_addr_q <= ADDR_MST;
led_clock_q <= CLK_LED_MST;
led_blank_q <= BLANK_MST;
led_latch_q <= LATCH_MST;
led_addr <= led_addr_q;
led_blank <= led_blank_q;
led_latch <= led_latch_q;
led_clock <= led_clock_q;
end
end
endmodule | 0 |
5,001 | data/full_repos/permissive/112823543/Avalon_LedPanel _Client_Server/LedMemoryClient_Avalon_tb.v | 112,823,543 | LedMemoryClient_Avalon_tb.v | v | 101 | 70 | [] | [] | [] | null | line:92: before: "(" | null | 1: b'%Error: Cannot find file containing module: _Client_Server,data/full_repos/permissive/112823543\n ... Looked in:\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.v\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.sv\n _Client_Server,data/full_repos/permissive/112823543\n _Client_Server,data/full_repos/permissive/112823543.v\n _Client_Server,data/full_repos/permissive/112823543.sv\n obj_dir/_Client_Server,data/full_repos/permissive/112823543\n obj_dir/_Client_Server,data/full_repos/permissive/112823543.v\n obj_dir/_Client_Server,data/full_repos/permissive/112823543.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/112823543/Avalon_LedPanel\n%Error: Cannot find file containing module: _Client_Server/LedMemoryClient_Avalon_tb.v\n%Error: Exiting due to 3 error(s)\n' | 5,374 | module | module LedMemoryClient_Avalon_tb ();
reg clock50, clock200;
reg reset;
reg [10:0] s1_address;
reg [31:0] s1_writedata;
reg s1_write;
wire [1:0] led_red, led_green, led_blue;
wire [3:0] led_addr;
wire led_clock;
wire led_blank;
wire led_latch;
reg [9:0] memAddrMst;
reg [2:0] bitplane;
reg backbuffer;
reg [3:0] ADDR_MST;
reg LATCH_MST;
reg CLK_LED_MST;
reg BLANK_MST;
LedPanelClient_Avalon #(
.DISPLAY_ROWS_LINES(4),
.DISPLAY_COLS_LINES(6),
.COLOR_BITS(8)
) DUT (
.clock(clock50),
.reset(reset),
.ext_clock200(clock200),
.s1_address(s1_address),
.s1_write(s1_write),
.s1_writedata(s1_writedata),
.led_red(led_red),
.led_green(led_green),
.led_blue(led_blue),
.led_addr(led_addr),
.led_clock(led_clock),
.led_blank(led_blank),
.led_latch(led_latch),
.memAddrMst(memAddrMst),
.bitplaneMst(bitplane),
.backbufferMst(backbuffer),
.ADDR_MST(ADDR_MST),
.LATCH_MST(LATCH_MST),
.CLK_LED_MST(CLK_LED_MST),
.BLANK_MST(BLANK_MST)
);
initial begin
clock50 = 0;
clock200 = 0;
reset = 1;
ADDR_MST = 0;
LATCH_MST = 0;
BLANK_MST = 1;
CLK_LED_MST = 0;
memAddrMst = 0;
bitplane = 0;
backbuffer = 0;
s1_address = 0;
s1_write = 0;
s1_writedata = 0;
end
initial forever #2.5 clock200 = ~clock200;
always @(posedge clock200) clock50 = ~clock50;
initial
begin
#10 reset = 0;
repeat (5) @(posedge clock50) ;
memAddrMst[5:0] = 5;
memAddrMst[9:6] = 4;
$stop;
end
endmodule | module LedMemoryClient_Avalon_tb (); |
reg clock50, clock200;
reg reset;
reg [10:0] s1_address;
reg [31:0] s1_writedata;
reg s1_write;
wire [1:0] led_red, led_green, led_blue;
wire [3:0] led_addr;
wire led_clock;
wire led_blank;
wire led_latch;
reg [9:0] memAddrMst;
reg [2:0] bitplane;
reg backbuffer;
reg [3:0] ADDR_MST;
reg LATCH_MST;
reg CLK_LED_MST;
reg BLANK_MST;
LedPanelClient_Avalon #(
.DISPLAY_ROWS_LINES(4),
.DISPLAY_COLS_LINES(6),
.COLOR_BITS(8)
) DUT (
.clock(clock50),
.reset(reset),
.ext_clock200(clock200),
.s1_address(s1_address),
.s1_write(s1_write),
.s1_writedata(s1_writedata),
.led_red(led_red),
.led_green(led_green),
.led_blue(led_blue),
.led_addr(led_addr),
.led_clock(led_clock),
.led_blank(led_blank),
.led_latch(led_latch),
.memAddrMst(memAddrMst),
.bitplaneMst(bitplane),
.backbufferMst(backbuffer),
.ADDR_MST(ADDR_MST),
.LATCH_MST(LATCH_MST),
.CLK_LED_MST(CLK_LED_MST),
.BLANK_MST(BLANK_MST)
);
initial begin
clock50 = 0;
clock200 = 0;
reset = 1;
ADDR_MST = 0;
LATCH_MST = 0;
BLANK_MST = 1;
CLK_LED_MST = 0;
memAddrMst = 0;
bitplane = 0;
backbuffer = 0;
s1_address = 0;
s1_write = 0;
s1_writedata = 0;
end
initial forever #2.5 clock200 = ~clock200;
always @(posedge clock200) clock50 = ~clock50;
initial
begin
#10 reset = 0;
repeat (5) @(posedge clock50) ;
memAddrMst[5:0] = 5;
memAddrMst[9:6] = 4;
$stop;
end
endmodule | 0 |
5,002 | data/full_repos/permissive/112823543/Avalon_LedPanel _Client_Server/LedMemoryServer_Avalon.v | 112,823,543 | LedMemoryServer_Avalon.v | v | 175 | 178 | [] | [] | [] | [(2, 174)] | null | null | 1: b'%Error: Cannot find file containing module: _Client_Server,data/full_repos/permissive/112823543\n ... Looked in:\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.v\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.sv\n _Client_Server,data/full_repos/permissive/112823543\n _Client_Server,data/full_repos/permissive/112823543.v\n _Client_Server,data/full_repos/permissive/112823543.sv\n obj_dir/_Client_Server,data/full_repos/permissive/112823543\n obj_dir/_Client_Server,data/full_repos/permissive/112823543.v\n obj_dir/_Client_Server,data/full_repos/permissive/112823543.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/112823543/Avalon_LedPanel\n%Error: Cannot find file containing module: _Client_Server/LedMemoryServer_Avalon.v\n%Error: Exiting due to 3 error(s)\n' | 5,375 | module | module LedPanelServer_Avalon #(
parameter DISPLAY_ROWS_LINES = 4,
parameter DISPLAY_COLS_LINES = 6,
parameter COLOR_BITS = 8
) (
input wire clock,
input wire reset,
input wire [1:0] s0_address,
input wire s0_write,
input wire [31:0] s0_writedata,
input wire s0_read,
output reg [31:0] s0_readdata,
output wire irq,
input wire ext_clock200,
output wire [DISPLAY_COLS_LINES+DISPLAY_ROWS_LINES-1:0] memAddrMst,
output wire [2:0] bitplaneMst,
output wire backbufferMst,
output wire [3:0] ADDR_MST,
output wire LATCH_MST,
output wire CLK_LED_MST,
output wire BLANK_MST
);
localparam major_version = 1;
localparam minor_version = 5;
reg backbuffer;
reg flip_backbuffer;
wire v_sync;
reg v_sync_q;
wire [7:0] reg_stat = {flip_backbuffer, 5'b00000, backbuffer, v_sync_q};
reg [7:0] reg_irq;
wire irq_ena = reg_irq[7];
wire irq_latch = reg_irq[0];
reg [1:0] v_sync_edge_detect;
reg req_backbuffer_flip;
assign irq = irq_ena && irq_latch;
assign backbufferMst = backbuffer;
always @(posedge clock)
begin
if (reset) begin
backbuffer <= 1'b0;
flip_backbuffer <= 1'b0;
reg_irq <= 8'h00;
end else begin
if (s0_address == 2'b01) begin
if (s0_read) begin
s0_readdata <= {24'b0, reg_irq};
end else if (s0_write) begin
reg_irq[7] <= s0_writedata[7];
reg_irq[0] <= 1'b0;
end
end else if (s0_address == 2'b00) begin
if (s0_read) begin
s0_readdata <= {24'b0, reg_stat};
end else if (s0_write) begin
flip_backbuffer <= s0_writedata[7];
end
end else if (s0_address == 2'b10) begin
if (s0_read) begin
s0_readdata[7:0] <= 2**DISPLAY_COLS_LINES;
s0_readdata[15:8]<= 2**DISPLAY_ROWS_LINES;
s0_readdata[31:16]<= 2**COLOR_BITS;
end
end else begin
if (s0_read) begin
s0_readdata[31:24] <= major_version;
s0_readdata[23:16] <= minor_version;
end
end
if (v_sync_edge_detect == 2'b01) begin
reg_irq[0] <= 1'b1;
end
if (req_backbuffer_flip) begin
backbuffer <= ~backbuffer;
flip_backbuffer <= 0;
end
end
end
always @(posedge ext_clock200)
begin
if (reset) begin
req_backbuffer_flip <= 1'b0;
v_sync_q <= 1'b0;
v_sync_edge_detect <= 2'b00;
end else begin
v_sync_q <= v_sync;
v_sync_edge_detect <= {v_sync_edge_detect[0], v_sync_q};
if ((v_sync_edge_detect == 2'b01) && (flip_backbuffer) ) begin
req_backbuffer_flip <= 1'b1;
end else if (req_backbuffer_flip && !flip_backbuffer) begin
req_backbuffer_flip <= 1'b0;
end
end
end
LedPanelServer #(
.COLOR_BITS(COLOR_BITS),
.DISPLAY_ROWS_LINES(DISPLAY_ROWS_LINES),
.DISPLAY_COLS_LINES(DISPLAY_COLS_LINES)
) panel(
.CLK(ext_clock200),
.RST(reset),
.ADDR_MST(ADDR_MST),
.CLK_LED_MST(CLK_LED_MST),
.BLANK_MST(BLANK_MST),
.LATCH_MST(LATCH_MST),
.v_sync(v_sync),
.memAddrMst(memAddrMst),
.bitplaneMst(bitplaneMst)
);
endmodule | module LedPanelServer_Avalon #(
parameter DISPLAY_ROWS_LINES = 4,
parameter DISPLAY_COLS_LINES = 6,
parameter COLOR_BITS = 8
) (
input wire clock,
input wire reset,
input wire [1:0] s0_address,
input wire s0_write,
input wire [31:0] s0_writedata,
input wire s0_read,
output reg [31:0] s0_readdata,
output wire irq,
input wire ext_clock200,
output wire [DISPLAY_COLS_LINES+DISPLAY_ROWS_LINES-1:0] memAddrMst,
output wire [2:0] bitplaneMst,
output wire backbufferMst,
output wire [3:0] ADDR_MST,
output wire LATCH_MST,
output wire CLK_LED_MST,
output wire BLANK_MST
); |
localparam major_version = 1;
localparam minor_version = 5;
reg backbuffer;
reg flip_backbuffer;
wire v_sync;
reg v_sync_q;
wire [7:0] reg_stat = {flip_backbuffer, 5'b00000, backbuffer, v_sync_q};
reg [7:0] reg_irq;
wire irq_ena = reg_irq[7];
wire irq_latch = reg_irq[0];
reg [1:0] v_sync_edge_detect;
reg req_backbuffer_flip;
assign irq = irq_ena && irq_latch;
assign backbufferMst = backbuffer;
always @(posedge clock)
begin
if (reset) begin
backbuffer <= 1'b0;
flip_backbuffer <= 1'b0;
reg_irq <= 8'h00;
end else begin
if (s0_address == 2'b01) begin
if (s0_read) begin
s0_readdata <= {24'b0, reg_irq};
end else if (s0_write) begin
reg_irq[7] <= s0_writedata[7];
reg_irq[0] <= 1'b0;
end
end else if (s0_address == 2'b00) begin
if (s0_read) begin
s0_readdata <= {24'b0, reg_stat};
end else if (s0_write) begin
flip_backbuffer <= s0_writedata[7];
end
end else if (s0_address == 2'b10) begin
if (s0_read) begin
s0_readdata[7:0] <= 2**DISPLAY_COLS_LINES;
s0_readdata[15:8]<= 2**DISPLAY_ROWS_LINES;
s0_readdata[31:16]<= 2**COLOR_BITS;
end
end else begin
if (s0_read) begin
s0_readdata[31:24] <= major_version;
s0_readdata[23:16] <= minor_version;
end
end
if (v_sync_edge_detect == 2'b01) begin
reg_irq[0] <= 1'b1;
end
if (req_backbuffer_flip) begin
backbuffer <= ~backbuffer;
flip_backbuffer <= 0;
end
end
end
always @(posedge ext_clock200)
begin
if (reset) begin
req_backbuffer_flip <= 1'b0;
v_sync_q <= 1'b0;
v_sync_edge_detect <= 2'b00;
end else begin
v_sync_q <= v_sync;
v_sync_edge_detect <= {v_sync_edge_detect[0], v_sync_q};
if ((v_sync_edge_detect == 2'b01) && (flip_backbuffer) ) begin
req_backbuffer_flip <= 1'b1;
end else if (req_backbuffer_flip && !flip_backbuffer) begin
req_backbuffer_flip <= 1'b0;
end
end
end
LedPanelServer #(
.COLOR_BITS(COLOR_BITS),
.DISPLAY_ROWS_LINES(DISPLAY_ROWS_LINES),
.DISPLAY_COLS_LINES(DISPLAY_COLS_LINES)
) panel(
.CLK(ext_clock200),
.RST(reset),
.ADDR_MST(ADDR_MST),
.CLK_LED_MST(CLK_LED_MST),
.BLANK_MST(BLANK_MST),
.LATCH_MST(LATCH_MST),
.v_sync(v_sync),
.memAddrMst(memAddrMst),
.bitplaneMst(bitplaneMst)
);
endmodule | 0 |
5,003 | data/full_repos/permissive/112823543/Avalon_LedPanel _Client_Server/LedPanelClient.v | 112,823,543 | LedPanelClient.v | v | 127 | 237 | [] | [] | [] | [(23, 126)] | null | null | 1: b'%Error: Cannot find file containing module: _Client_Server,data/full_repos/permissive/112823543\n ... Looked in:\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.v\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.sv\n _Client_Server,data/full_repos/permissive/112823543\n _Client_Server,data/full_repos/permissive/112823543.v\n _Client_Server,data/full_repos/permissive/112823543.sv\n obj_dir/_Client_Server,data/full_repos/permissive/112823543\n obj_dir/_Client_Server,data/full_repos/permissive/112823543.v\n obj_dir/_Client_Server,data/full_repos/permissive/112823543.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/112823543/Avalon_LedPanel\n%Error: Cannot find file containing module: _Client_Server/LedPanelClient.v\n%Error: Exiting due to 3 error(s)\n' | 5,376 | module | module LedPanelClient(
input wire CLK,
input wire RST,
output wire [1:0] RED,
output wire [1:0] GREEN,
output wire [1:0] BLUE,
output wire [3:0] ADDR,
output wire CLK_LED,
output wire BLANK,
output wire LATCH,
input wire [DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES:0] memAddrIn,
input wire [23:0] memDataIn,
input wire memWrite,
input wire [COLOR_BITS-1:0] gammaAddrIn,
input wire [3*COLOR_BITS-1:0] gammaDataIn,
output wire [3*COLOR_BITS-1:0] gammaDataOut,
input wire gammaWrite,
input wire gammaRead,
input wire backbufferMst,
input wire [DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES-1:0] memAddrMst,
input wire [2:0] bitplaneMst,
input wire [3:0] ADDR_MST,
input wire CLK_LED_MST,
input wire BLANK_MST,
input wire LATCH_MST
);
parameter COLOR_BITS = 8;
parameter DISPLAY_ROWS_LINES = 4;
parameter DISPLAY_COLS_LINES = 6;
wire [COLOR_BITS-1:0] redUpper, redLower, greenUpper, greenLower, blueUpper, blueLower;
assign RED[0] = redUpper[bitplaneMst];
assign RED[1] = redLower[bitplaneMst];
assign GREEN[0] = greenUpper[bitplaneMst];
assign GREEN[1] = greenLower[bitplaneMst];
assign BLUE[0] = blueUpper[bitplaneMst];
assign BLUE[1] = blueLower[bitplaneMst];
wire memUpperCS = (!memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES] && memWrite) ? 1'b1 : 1'b0;
wire memLowerCS = ( memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES] && memWrite) ? 1'b1 : 1'b0;
assign ADDR = ADDR_MST;
assign CLK_LED = CLK_LED_MST;
assign BLANK = BLANK_MST;
assign LATCH = LATCH_MST;
LedPanelMemory #(
.ADDR_LINES(DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES+1),
.COLOR_BITS(COLOR_BITS)
) UpperMemory (
.clock(CLK),
.reset(RST),
.Address_a({backbufferMst, memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES-1:0]}),
.DataIn_a(memDataIn),
.Write_a(memUpperCS),
.Address_gamma(gammaAddrIn),
.DataIn_gamma(gammaDataIn),
.DataOut_gamma(gammaDataOut),
.Write_gamma(gammaWrite),
.Read_gamma(gammaRead),
.Address_b({!backbufferMst, memAddrMst}),
.RedOut_b(redUpper),
.GreenOut_b(greenUpper),
.BlueOut_b(blueUpper)
);
LedPanelMemory #(
.ADDR_LINES(DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES+1),
.COLOR_BITS(COLOR_BITS)
) LowerMemory (
.clock(CLK),
.reset(RST),
.Address_a({backbufferMst, memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES-1:0]}),
.DataIn_a(memDataIn),
.Write_a(memLowerCS),
.Address_gamma(gammaAddrIn),
.DataIn_gamma(gammaDataIn),
.DataOut_gamma(),
.Write_gamma(gammaWrite),
.Read_gamma(1'b0),
.Address_b({!backbufferMst, memAddrMst}),
.RedOut_b(redLower),
.GreenOut_b(greenLower),
.BlueOut_b(blueLower)
);
endmodule | module LedPanelClient(
input wire CLK,
input wire RST,
output wire [1:0] RED,
output wire [1:0] GREEN,
output wire [1:0] BLUE,
output wire [3:0] ADDR,
output wire CLK_LED,
output wire BLANK,
output wire LATCH,
input wire [DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES:0] memAddrIn,
input wire [23:0] memDataIn,
input wire memWrite,
input wire [COLOR_BITS-1:0] gammaAddrIn,
input wire [3*COLOR_BITS-1:0] gammaDataIn,
output wire [3*COLOR_BITS-1:0] gammaDataOut,
input wire gammaWrite,
input wire gammaRead,
input wire backbufferMst,
input wire [DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES-1:0] memAddrMst,
input wire [2:0] bitplaneMst,
input wire [3:0] ADDR_MST,
input wire CLK_LED_MST,
input wire BLANK_MST,
input wire LATCH_MST
); |
parameter COLOR_BITS = 8;
parameter DISPLAY_ROWS_LINES = 4;
parameter DISPLAY_COLS_LINES = 6;
wire [COLOR_BITS-1:0] redUpper, redLower, greenUpper, greenLower, blueUpper, blueLower;
assign RED[0] = redUpper[bitplaneMst];
assign RED[1] = redLower[bitplaneMst];
assign GREEN[0] = greenUpper[bitplaneMst];
assign GREEN[1] = greenLower[bitplaneMst];
assign BLUE[0] = blueUpper[bitplaneMst];
assign BLUE[1] = blueLower[bitplaneMst];
wire memUpperCS = (!memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES] && memWrite) ? 1'b1 : 1'b0;
wire memLowerCS = ( memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES] && memWrite) ? 1'b1 : 1'b0;
assign ADDR = ADDR_MST;
assign CLK_LED = CLK_LED_MST;
assign BLANK = BLANK_MST;
assign LATCH = LATCH_MST;
LedPanelMemory #(
.ADDR_LINES(DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES+1),
.COLOR_BITS(COLOR_BITS)
) UpperMemory (
.clock(CLK),
.reset(RST),
.Address_a({backbufferMst, memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES-1:0]}),
.DataIn_a(memDataIn),
.Write_a(memUpperCS),
.Address_gamma(gammaAddrIn),
.DataIn_gamma(gammaDataIn),
.DataOut_gamma(gammaDataOut),
.Write_gamma(gammaWrite),
.Read_gamma(gammaRead),
.Address_b({!backbufferMst, memAddrMst}),
.RedOut_b(redUpper),
.GreenOut_b(greenUpper),
.BlueOut_b(blueUpper)
);
LedPanelMemory #(
.ADDR_LINES(DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES+1),
.COLOR_BITS(COLOR_BITS)
) LowerMemory (
.clock(CLK),
.reset(RST),
.Address_a({backbufferMst, memAddrIn[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES-1:0]}),
.DataIn_a(memDataIn),
.Write_a(memLowerCS),
.Address_gamma(gammaAddrIn),
.DataIn_gamma(gammaDataIn),
.DataOut_gamma(),
.Write_gamma(gammaWrite),
.Read_gamma(1'b0),
.Address_b({!backbufferMst, memAddrMst}),
.RedOut_b(redLower),
.GreenOut_b(greenLower),
.BlueOut_b(blueLower)
);
endmodule | 0 |
5,004 | data/full_repos/permissive/112823543/Avalon_LedPanel _Client_Server/LedPanelServer.v | 112,823,543 | LedPanelServer.v | v | 217 | 241 | [] | [] | [] | [(23, 216)] | null | null | 1: b'%Error: Cannot find file containing module: _Client_Server,data/full_repos/permissive/112823543\n ... Looked in:\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.v\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.sv\n _Client_Server,data/full_repos/permissive/112823543\n _Client_Server,data/full_repos/permissive/112823543.v\n _Client_Server,data/full_repos/permissive/112823543.sv\n obj_dir/_Client_Server,data/full_repos/permissive/112823543\n obj_dir/_Client_Server,data/full_repos/permissive/112823543.v\n obj_dir/_Client_Server,data/full_repos/permissive/112823543.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/112823543/Avalon_LedPanel\n%Error: Cannot find file containing module: _Client_Server/LedPanelServer.v\n%Error: Exiting due to 3 error(s)\n' | 5,377 | module | module LedPanelServer #(
parameter COLOR_BITS = 8,
parameter DISPLAY_ROWS_LINES = 4,
parameter DISPLAY_COLS_LINES = 6
) (
input wire CLK,
input wire RST,
output reg [3:0] ADDR_MST,
output reg CLK_LED_MST,
output reg BLANK_MST,
output reg LATCH_MST,
input wire [DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES:0] memAddrIn,
input wire [23:0] memDataIn,
input wire memWrite,
output reg v_sync,
output wire [DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES-1:0] memAddrMst,
output reg [2:0] bitplaneMst
);
reg [1:0] clkReg_d, clkReg_q;
wire CLK_50 = clkReg_q[1];
reg [DISPLAY_COLS_LINES-1:0] col;
reg [DISPLAY_ROWS_LINES-1:0] row;
localparam s_00 = 2'b00,
s_01 = 2'b01,
s_10 = 2'b10,
s_11 = 2'b11;
localparam s_UNBLANK = 3'b000,
s_WAIT = 3'b001,
s_BLANK = 3'b010,
s_LATCH = 3'b011,
s_DELATCH = 3'b100;
reg [2:0] state;
reg sig_shifting_ready;
reg shifting_ena;
reg [13:0] display_counter;
reg [DISPLAY_ROWS_LINES-1:0] old_addr;
assign memAddrMst = {row, col};
always @(*)
begin
case (clkReg_q)
2'b00: clkReg_d = 2'b01;
2'b01: clkReg_d = 2'b10;
2'b10: clkReg_d = 2'b11;
2'b11: clkReg_d = 2'b00;
default: clkReg_d = 2'b00;
endcase
end
always @(negedge CLK)
begin
clkReg_q <= clkReg_d;
end
always @(posedge CLK_50)
begin
if (RST) begin
col = {DISPLAY_COLS_LINES{1'b0}};
row = {DISPLAY_ROWS_LINES{1'b0}};
CLK_LED_MST <= 0;
bitplaneMst <= 3'b000;
sig_shifting_ready <= 0;
v_sync <= 0;
end else begin
CLK_LED_MST <= 0;
v_sync <= 0;
if (state == s_WAIT) begin
if ((shifting_ena == 1) && (sig_shifting_ready == 0) ) begin
if (CLK_LED_MST == 0) begin
col <= col + 1;
if (col == &1) begin
sig_shifting_ready <= 1;
bitplaneMst <= bitplaneMst + 1;
if (bitplaneMst == &1) begin
row <= row + 1;
if (row == &1) begin
v_sync <= 1;
end
end
end
end
CLK_LED_MST <= ~CLK_LED_MST;
end
end else sig_shifting_ready <= 0;
end
end
always @(posedge CLK_50)
begin
if (RST) begin
BLANK_MST <= 0;
ADDR_MST = {DISPLAY_ROWS_LINES{1'b0}};
old_addr = 0;
end else begin
if (state == s_BLANK) begin
BLANK_MST <= 1;
ADDR_MST = old_addr;
old_addr = row;
end else if (state == s_UNBLANK) begin
BLANK_MST <= 0;
end
end
end
always @(posedge CLK_50)
begin
if (RST)
LATCH_MST <= 1'b1;
else begin
if (state == s_LATCH)
LATCH_MST <= 1'b1;
else if (state == s_DELATCH)
LATCH_MST <= 1'b0;
end
end
reg sig_wait_done;
always @(posedge CLK_50)
begin
if (RST) begin
display_counter <= 14'd123;
shifting_ena <= 0;
sig_wait_done <= 0;
end else if (state == s_WAIT) begin
if (display_counter != 0) begin
display_counter <= display_counter - 14'b1;
end else if (sig_shifting_ready) begin
shifting_ena <= 0;
sig_wait_done <= 1;
end
end else if (state == s_UNBLANK) begin
case (bitplaneMst)
0: display_counter = 122 << 7;
1: display_counter = 122 << 0;
2: display_counter = 122 << 1;
3: display_counter = 122 << 2;
4: display_counter = 122 << 3;
5: display_counter = 122 << 4;
6: display_counter = 122 << 5;
7: display_counter = 122 << 6;
default: display_counter = 122 << 0;
endcase
shifting_ena <= 1;
end else sig_wait_done <= 0;
end
always @(posedge CLK_50)
begin
if (RST) begin state = s_UNBLANK;
end else begin
case (state)
s_UNBLANK: state = s_WAIT;
s_WAIT: if (sig_wait_done == 1) state = s_BLANK;
s_BLANK: state = s_LATCH;
s_LATCH: state = s_DELATCH;
s_DELATCH: state = s_UNBLANK;
endcase
end
end
endmodule | module LedPanelServer #(
parameter COLOR_BITS = 8,
parameter DISPLAY_ROWS_LINES = 4,
parameter DISPLAY_COLS_LINES = 6
) (
input wire CLK,
input wire RST,
output reg [3:0] ADDR_MST,
output reg CLK_LED_MST,
output reg BLANK_MST,
output reg LATCH_MST,
input wire [DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES:0] memAddrIn,
input wire [23:0] memDataIn,
input wire memWrite,
output reg v_sync,
output wire [DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES-1:0] memAddrMst,
output reg [2:0] bitplaneMst
); |
reg [1:0] clkReg_d, clkReg_q;
wire CLK_50 = clkReg_q[1];
reg [DISPLAY_COLS_LINES-1:0] col;
reg [DISPLAY_ROWS_LINES-1:0] row;
localparam s_00 = 2'b00,
s_01 = 2'b01,
s_10 = 2'b10,
s_11 = 2'b11;
localparam s_UNBLANK = 3'b000,
s_WAIT = 3'b001,
s_BLANK = 3'b010,
s_LATCH = 3'b011,
s_DELATCH = 3'b100;
reg [2:0] state;
reg sig_shifting_ready;
reg shifting_ena;
reg [13:0] display_counter;
reg [DISPLAY_ROWS_LINES-1:0] old_addr;
assign memAddrMst = {row, col};
always @(*)
begin
case (clkReg_q)
2'b00: clkReg_d = 2'b01;
2'b01: clkReg_d = 2'b10;
2'b10: clkReg_d = 2'b11;
2'b11: clkReg_d = 2'b00;
default: clkReg_d = 2'b00;
endcase
end
always @(negedge CLK)
begin
clkReg_q <= clkReg_d;
end
always @(posedge CLK_50)
begin
if (RST) begin
col = {DISPLAY_COLS_LINES{1'b0}};
row = {DISPLAY_ROWS_LINES{1'b0}};
CLK_LED_MST <= 0;
bitplaneMst <= 3'b000;
sig_shifting_ready <= 0;
v_sync <= 0;
end else begin
CLK_LED_MST <= 0;
v_sync <= 0;
if (state == s_WAIT) begin
if ((shifting_ena == 1) && (sig_shifting_ready == 0) ) begin
if (CLK_LED_MST == 0) begin
col <= col + 1;
if (col == &1) begin
sig_shifting_ready <= 1;
bitplaneMst <= bitplaneMst + 1;
if (bitplaneMst == &1) begin
row <= row + 1;
if (row == &1) begin
v_sync <= 1;
end
end
end
end
CLK_LED_MST <= ~CLK_LED_MST;
end
end else sig_shifting_ready <= 0;
end
end
always @(posedge CLK_50)
begin
if (RST) begin
BLANK_MST <= 0;
ADDR_MST = {DISPLAY_ROWS_LINES{1'b0}};
old_addr = 0;
end else begin
if (state == s_BLANK) begin
BLANK_MST <= 1;
ADDR_MST = old_addr;
old_addr = row;
end else if (state == s_UNBLANK) begin
BLANK_MST <= 0;
end
end
end
always @(posedge CLK_50)
begin
if (RST)
LATCH_MST <= 1'b1;
else begin
if (state == s_LATCH)
LATCH_MST <= 1'b1;
else if (state == s_DELATCH)
LATCH_MST <= 1'b0;
end
end
reg sig_wait_done;
always @(posedge CLK_50)
begin
if (RST) begin
display_counter <= 14'd123;
shifting_ena <= 0;
sig_wait_done <= 0;
end else if (state == s_WAIT) begin
if (display_counter != 0) begin
display_counter <= display_counter - 14'b1;
end else if (sig_shifting_ready) begin
shifting_ena <= 0;
sig_wait_done <= 1;
end
end else if (state == s_UNBLANK) begin
case (bitplaneMst)
0: display_counter = 122 << 7;
1: display_counter = 122 << 0;
2: display_counter = 122 << 1;
3: display_counter = 122 << 2;
4: display_counter = 122 << 3;
5: display_counter = 122 << 4;
6: display_counter = 122 << 5;
7: display_counter = 122 << 6;
default: display_counter = 122 << 0;
endcase
shifting_ena <= 1;
end else sig_wait_done <= 0;
end
always @(posedge CLK_50)
begin
if (RST) begin state = s_UNBLANK;
end else begin
case (state)
s_UNBLANK: state = s_WAIT;
s_WAIT: if (sig_wait_done == 1) state = s_BLANK;
s_BLANK: state = s_LATCH;
s_LATCH: state = s_DELATCH;
s_DELATCH: state = s_UNBLANK;
endcase
end
end
endmodule | 0 |
5,005 | data/full_repos/permissive/112823543/Avalon_LedPanel _Client_Server/StandardAnimation.v | 112,823,543 | StandardAnimation.v | v | 330 | 178 | [] | [] | [] | null | line:246: before: "0" | null | 1: b'%Error: Cannot find file containing module: _Client_Server,data/full_repos/permissive/112823543\n ... Looked in:\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.v\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.sv\n _Client_Server,data/full_repos/permissive/112823543\n _Client_Server,data/full_repos/permissive/112823543.v\n _Client_Server,data/full_repos/permissive/112823543.sv\n obj_dir/_Client_Server,data/full_repos/permissive/112823543\n obj_dir/_Client_Server,data/full_repos/permissive/112823543.v\n obj_dir/_Client_Server,data/full_repos/permissive/112823543.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/112823543/Avalon_LedPanel\n%Error: Cannot find file containing module: _Client_Server/StandardAnimation.v\n%Error: Exiting due to 3 error(s)\n' | 5,381 | module | module StandardAnimation #(
parameter NUM_REGIONS = 5,
parameter DISPLAY_ROWS_LINES = 4,
parameter DISPLAY_COLS_LINES = 6,
parameter COLOR_BITS = 8
) (
input wire clock_clk,
input wire v_sync,
input wire reset_rst,
input wire [2:0] s0_address,
input wire s0_read,
output reg [31:0] s0_readdata,
input wire s0_write,
input wire [31:0] s0_writedata,
input wire [NUM_REGIONS-1:0] event_trigger,
input wire [DISPLAY_COLS_LINES-1:0] col1,
input wire [DISPLAY_ROWS_LINES-1:0] row1,
input wire [3:0] bitplane1,
output reg red1,
output reg green1,
output reg blue1,
input wire [DISPLAY_COLS_LINES-1:0] col2,
input wire [DISPLAY_ROWS_LINES-1:0] row2,
input wire [3:0] bitplane2,
output reg red2,
output reg green2,
output reg blue2
);
reg [7:0] RegStartColumn, RegEndColumn, RegStartRow, RegEndRow;
reg [7:0] RegLightColorR, RegLightColorG, RegLightColorB;
reg [7:0] RegAnimationType;
reg [31:0] RegParameterSlope;
reg [31:0] RegParameterFrequency;
reg [31:0] RegParameterDirection;
reg [31:0] RegParameterSpeed;
always @(posedge clock_clk)
begin
if (reset_rst) begin
RegStartColumn <= 8'b0;
RegEndColumn <= 8'b0;
RegStartRow <= 8'b0;
RegEndRow <= 8'b0;
RegLightColorB <= 8'b0;
RegLightColorG <= 8'b0;
RegLightColorR <= 8'b0;
RegAnimationType<= 8'b0;
RegParameterSlope <= 32'b0;
RegParameterFrequency <= 32'b0;
RegParameterSpeed <= 32'b0;
RegParameterDirection <= 32'b0;
end else begin
if (s0_write) begin
case (s0_address)
3'd0:
begin
RegStartColumn <= s0_writedata[31:24];
RegEndColumn <= s0_writedata[23:16];
RegStartRow <= s0_writedata[15:8];
RegEndRow <= s0_writedata[7:0];
end
3'd1:
begin
RegLightColorR <= s0_writedata[7:0];
RegLightColorG <= s0_writedata[15:8];
RegLightColorB <= s0_writedata[23:16];
end
3'd2:
begin
RegAnimationType <= s0_writedata[7:0];
end
3'd3:
begin
RegParameterSlope <= s0_writedata;
end
3'd4:
begin
RegParameterFrequency <= s0_writedata;
end
3'd5:
begin
RegParameterDirection <= s0_writedata;
end
3'd6:
begin
RegParameterSpeed <= s0_writedata;
end
endcase
end
end
end
always @(posedge clock_clk)
begin
if (reset_rst) begin
s0_readdata <= 32'b0;
end else begin
s0_readdata <= 32'b0;
if (s0_read) begin
case (s0_address)
3'd0: s0_readdata <= {RegStartColumn, RegEndColumn, RegStartRow, RegEndRow};
3'd1: s0_readdata <= {8'b0, RegLightColorB, RegLightColorG, RegLightColorR};
3'd2: s0_readdata <= {24'b0, RegAnimationType};
3'd3: s0_readdata <= RegParameterSlope;
3'd4: s0_readdata <= RegParameterFrequency;
3'd5: s0_readdata <= RegParameterDirection;
3'd6: s0_readdata <= RegParameterSpeed;
default: s0_readdata <= 32'b0;
endcase
end
end
end
reg [7:0] RegStartColumn_q, RegEndColumn_q, RegStartRow_q, RegEndRow_q;
reg [7:0] RegLightColorR_q, RegLightColorG_q, RegLightColorB_q;
reg [7:0] FrameCount_d, FrameCount_q;
reg [1:0] v_sync_edge_detect_d,v_sync_edge_detect_q;
wire cs_col1, cs_row1;
assign cs_col1 = (col1 >= RegStartColumn_q) && (col1 <= RegEndColumn_q);
assign cs_row1 = (row1 >= RegStartRow_q ) && (row1 <= RegEndRow_q);
wire cs1 = cs_col1 && cs_row1;
wire cs_col2, cs_row2;
assign cs_col2 = (col2 >= RegStartColumn_q) && (col2 <= RegEndColumn_q);
assign cs_row2 = (row2 >= RegStartRow_q ) && (row2 <= RegEndRow_q);
wire cs2 = cs_col2 && cs_row2;
always @(*)
begin
if (reset_rst) begin
v_sync_edge_detect_d <= 2'b0;
end else begin
v_sync_edge_detect_d <= {v_sync_edge_detect_q[0], v_sync};
end
end
always @(posedge clock_clk)
begin
if (reset_rst) begin
v_sync_edge_detect_q <= 2'b0;
end else begin
v_sync_edge_detect_q <= v_sync_edge_detect_d;
end
end
always @(*)
begin
if (reset_rst) begin
FrameCount_d <= 0;
end else begin
FrameCount_d <= FrameCount_q;
if (v_sync_edge_detect_q == 2'b01) begin
if (event_trigger[0]) begin
FrameCount_d <= FrameCount_q + 1;
end else begin
if (FrameCount_q !=0)
FrameCount_d <= FrameCount_q - 1;
end
end
end
end
always @(posedge clock_clk)
begin
if (reset_rst) begin
FrameCount_q <= 0;
end else begin
FrameCount_q <= FrameCount_d;
end
end
always @(posedge clock_clk)
begin
if (reset_rst) begin
end else begin
if (v_sync) begin
RegStartColumn_q <= RegStartColumn;
RegEndColumn_q <= RegEndColumn;
RegStartRow_q <= RegStartRow;
RegEndRow_q <= RegEndRow;
RegLightColorB_q <= RegLightColorB;
RegLightColorG_q <= RegLightColorG;
RegLightColorR_q <= RegLightColorR;
end else begin
end
end
end
`ifdef (0)
always @(posedge clock_clk)
begin
if (reset_rst) begin
red1 <= 0;
green1 <= 0;
blue1 <= 0;
end else begin
red1 <= 0;
green1 <= 0;
blue1 <= 0;
if (cs1) begin
if (event_trigger[0]) begin
red1 <= RegLightColorR_q[bitplane1];
green1 <= RegLightColorG_q[bitplane1];
blue1 <= RegLightColorB_q[bitplane1];
end
end
end
end
always @(posedge clock_clk)
begin
if (reset_rst) begin
red2 <= 0;
green2 <= 0;
blue2 <= 0;
end else begin
red2 <= 0;
green2 <= 0;
blue2 <= 0;
if (cs2) begin
if (event_trigger[0]) begin
red2 <= RegLightColorR_q[bitplane2];
green2 <= RegLightColorG_q[bitplane2];
blue2 <= RegLightColorB_q[bitplane2];
end
end
end
end
`endif
always @(posedge clock_clk)
begin
if (reset_rst) begin
red1 <= 0;
green1 <= 0;
blue1 <= 0;
end else begin
red1 <= 0;
green1 <= 0;
blue1 <= 0;
if (cs1) begin
if (event_trigger[0]) begin
red1 <= RegLightColorR_q[bitplane1];
green1 <= RegLightColorG_q[bitplane1];
blue1 <= RegLightColorB_q[bitplane1];
end
end
end
end
always @(posedge clock_clk)
begin
if (reset_rst) begin
red2 <= 0;
green2 <= 0;
blue2 <= 0;
end else begin
red2 <= 0;
green2 <= 0;
blue2 <= 0;
if (cs2) begin
if (event_trigger[0]) begin
red2 <= RegLightColorR_q[bitplane2];
green2 <= RegLightColorG_q[bitplane2];
blue2 <= RegLightColorB_q[bitplane2];
end
end
end
end
endmodule | module StandardAnimation #(
parameter NUM_REGIONS = 5,
parameter DISPLAY_ROWS_LINES = 4,
parameter DISPLAY_COLS_LINES = 6,
parameter COLOR_BITS = 8
) (
input wire clock_clk,
input wire v_sync,
input wire reset_rst,
input wire [2:0] s0_address,
input wire s0_read,
output reg [31:0] s0_readdata,
input wire s0_write,
input wire [31:0] s0_writedata,
input wire [NUM_REGIONS-1:0] event_trigger,
input wire [DISPLAY_COLS_LINES-1:0] col1,
input wire [DISPLAY_ROWS_LINES-1:0] row1,
input wire [3:0] bitplane1,
output reg red1,
output reg green1,
output reg blue1,
input wire [DISPLAY_COLS_LINES-1:0] col2,
input wire [DISPLAY_ROWS_LINES-1:0] row2,
input wire [3:0] bitplane2,
output reg red2,
output reg green2,
output reg blue2
); |
reg [7:0] RegStartColumn, RegEndColumn, RegStartRow, RegEndRow;
reg [7:0] RegLightColorR, RegLightColorG, RegLightColorB;
reg [7:0] RegAnimationType;
reg [31:0] RegParameterSlope;
reg [31:0] RegParameterFrequency;
reg [31:0] RegParameterDirection;
reg [31:0] RegParameterSpeed;
always @(posedge clock_clk)
begin
if (reset_rst) begin
RegStartColumn <= 8'b0;
RegEndColumn <= 8'b0;
RegStartRow <= 8'b0;
RegEndRow <= 8'b0;
RegLightColorB <= 8'b0;
RegLightColorG <= 8'b0;
RegLightColorR <= 8'b0;
RegAnimationType<= 8'b0;
RegParameterSlope <= 32'b0;
RegParameterFrequency <= 32'b0;
RegParameterSpeed <= 32'b0;
RegParameterDirection <= 32'b0;
end else begin
if (s0_write) begin
case (s0_address)
3'd0:
begin
RegStartColumn <= s0_writedata[31:24];
RegEndColumn <= s0_writedata[23:16];
RegStartRow <= s0_writedata[15:8];
RegEndRow <= s0_writedata[7:0];
end
3'd1:
begin
RegLightColorR <= s0_writedata[7:0];
RegLightColorG <= s0_writedata[15:8];
RegLightColorB <= s0_writedata[23:16];
end
3'd2:
begin
RegAnimationType <= s0_writedata[7:0];
end
3'd3:
begin
RegParameterSlope <= s0_writedata;
end
3'd4:
begin
RegParameterFrequency <= s0_writedata;
end
3'd5:
begin
RegParameterDirection <= s0_writedata;
end
3'd6:
begin
RegParameterSpeed <= s0_writedata;
end
endcase
end
end
end
always @(posedge clock_clk)
begin
if (reset_rst) begin
s0_readdata <= 32'b0;
end else begin
s0_readdata <= 32'b0;
if (s0_read) begin
case (s0_address)
3'd0: s0_readdata <= {RegStartColumn, RegEndColumn, RegStartRow, RegEndRow};
3'd1: s0_readdata <= {8'b0, RegLightColorB, RegLightColorG, RegLightColorR};
3'd2: s0_readdata <= {24'b0, RegAnimationType};
3'd3: s0_readdata <= RegParameterSlope;
3'd4: s0_readdata <= RegParameterFrequency;
3'd5: s0_readdata <= RegParameterDirection;
3'd6: s0_readdata <= RegParameterSpeed;
default: s0_readdata <= 32'b0;
endcase
end
end
end
reg [7:0] RegStartColumn_q, RegEndColumn_q, RegStartRow_q, RegEndRow_q;
reg [7:0] RegLightColorR_q, RegLightColorG_q, RegLightColorB_q;
reg [7:0] FrameCount_d, FrameCount_q;
reg [1:0] v_sync_edge_detect_d,v_sync_edge_detect_q;
wire cs_col1, cs_row1;
assign cs_col1 = (col1 >= RegStartColumn_q) && (col1 <= RegEndColumn_q);
assign cs_row1 = (row1 >= RegStartRow_q ) && (row1 <= RegEndRow_q);
wire cs1 = cs_col1 && cs_row1;
wire cs_col2, cs_row2;
assign cs_col2 = (col2 >= RegStartColumn_q) && (col2 <= RegEndColumn_q);
assign cs_row2 = (row2 >= RegStartRow_q ) && (row2 <= RegEndRow_q);
wire cs2 = cs_col2 && cs_row2;
always @(*)
begin
if (reset_rst) begin
v_sync_edge_detect_d <= 2'b0;
end else begin
v_sync_edge_detect_d <= {v_sync_edge_detect_q[0], v_sync};
end
end
always @(posedge clock_clk)
begin
if (reset_rst) begin
v_sync_edge_detect_q <= 2'b0;
end else begin
v_sync_edge_detect_q <= v_sync_edge_detect_d;
end
end
always @(*)
begin
if (reset_rst) begin
FrameCount_d <= 0;
end else begin
FrameCount_d <= FrameCount_q;
if (v_sync_edge_detect_q == 2'b01) begin
if (event_trigger[0]) begin
FrameCount_d <= FrameCount_q + 1;
end else begin
if (FrameCount_q !=0)
FrameCount_d <= FrameCount_q - 1;
end
end
end
end
always @(posedge clock_clk)
begin
if (reset_rst) begin
FrameCount_q <= 0;
end else begin
FrameCount_q <= FrameCount_d;
end
end
always @(posedge clock_clk)
begin
if (reset_rst) begin
end else begin
if (v_sync) begin
RegStartColumn_q <= RegStartColumn;
RegEndColumn_q <= RegEndColumn;
RegStartRow_q <= RegStartRow;
RegEndRow_q <= RegEndRow;
RegLightColorB_q <= RegLightColorB;
RegLightColorG_q <= RegLightColorG;
RegLightColorR_q <= RegLightColorR;
end else begin
end
end
end
`ifdef (0)
always @(posedge clock_clk)
begin
if (reset_rst) begin
red1 <= 0;
green1 <= 0;
blue1 <= 0;
end else begin
red1 <= 0;
green1 <= 0;
blue1 <= 0;
if (cs1) begin
if (event_trigger[0]) begin
red1 <= RegLightColorR_q[bitplane1];
green1 <= RegLightColorG_q[bitplane1];
blue1 <= RegLightColorB_q[bitplane1];
end
end
end
end
always @(posedge clock_clk)
begin
if (reset_rst) begin
red2 <= 0;
green2 <= 0;
blue2 <= 0;
end else begin
red2 <= 0;
green2 <= 0;
blue2 <= 0;
if (cs2) begin
if (event_trigger[0]) begin
red2 <= RegLightColorR_q[bitplane2];
green2 <= RegLightColorG_q[bitplane2];
blue2 <= RegLightColorB_q[bitplane2];
end
end
end
end
`endif
always @(posedge clock_clk)
begin
if (reset_rst) begin
red1 <= 0;
green1 <= 0;
blue1 <= 0;
end else begin
red1 <= 0;
green1 <= 0;
blue1 <= 0;
if (cs1) begin
if (event_trigger[0]) begin
red1 <= RegLightColorR_q[bitplane1];
green1 <= RegLightColorG_q[bitplane1];
blue1 <= RegLightColorB_q[bitplane1];
end
end
end
end
always @(posedge clock_clk)
begin
if (reset_rst) begin
red2 <= 0;
green2 <= 0;
blue2 <= 0;
end else begin
red2 <= 0;
green2 <= 0;
blue2 <= 0;
if (cs2) begin
if (event_trigger[0]) begin
red2 <= RegLightColorR_q[bitplane2];
green2 <= RegLightColorG_q[bitplane2];
blue2 <= RegLightColorB_q[bitplane2];
end
end
end
end
endmodule | 0 |
5,006 | data/full_repos/permissive/112823543/Avalon_LedPanel _Client_Server/Old/LedPanelMemory.v | 112,823,543 | LedPanelMemory.v | v | 102 | 153 | [] | [] | [] | [(2, 101)] | null | null | 1: b'%Error: Cannot find file containing module: _Client_Server/Old,data/full_repos/permissive/112823543\n ... Looked in:\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server/Old,data/full_repos/permissive/112823543\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server/Old,data/full_repos/permissive/112823543.v\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server/Old,data/full_repos/permissive/112823543.sv\n _Client_Server/Old,data/full_repos/permissive/112823543\n _Client_Server/Old,data/full_repos/permissive/112823543.v\n _Client_Server/Old,data/full_repos/permissive/112823543.sv\n obj_dir/_Client_Server/Old,data/full_repos/permissive/112823543\n obj_dir/_Client_Server/Old,data/full_repos/permissive/112823543.v\n obj_dir/_Client_Server/Old,data/full_repos/permissive/112823543.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/112823543/Avalon_LedPanel\n%Error: Cannot find file containing module: _Client_Server/Old/LedPanelMemory.v\n%Error: Exiting due to 3 error(s)\n' | 5,386 | module | module LedPanelMemory(
input wire clock,
input wire reset,
input wire [ADDR_LINES-1:0] Address_a,
input wire [3*COLOR_BITS-1:0] DataIn_a,
input wire Write_a,
input wire [COLOR_BITS-1:0] Address_gamma,
input wire [3*COLOR_BITS-1:0] DataIn_gamma,
output reg [3*COLOR_BITS-1:0] DataOut_gamma,
input wire Write_gamma,
input wire Read_gamma,
input wire [ADDR_LINES-1:0] Address_b,
output reg [COLOR_BITS-1:0] RedOut_b,
output reg [COLOR_BITS-1:0] GreenOut_b,
output reg [COLOR_BITS-1:0] BlueOut_b
);
parameter ADDR_LINES = 10;
parameter COLOR_BITS = 8;
reg [3*COLOR_BITS-1:0] memory[(1<<ADDR_LINES)-1:0];
reg [COLOR_BITS-1:0] gamma_red [(1<<COLOR_BITS)-1:0];
reg [COLOR_BITS-1:0] gamma_green[(1<<COLOR_BITS)-1:0];
reg [COLOR_BITS-1:0] gamma_blue [(1<<COLOR_BITS)-1:0];
integer k;
initial
begin
for(k=0;k< (1<<ADDR_LINES); k = k + 1)
memory[k] = k;
end
initial
begin
for(k=0; k< (1<<COLOR_BITS); k = k + 1)
begin
gamma_red[k] = k;
gamma_blue[k] = k;
gamma_green[k] = k;
end
end
reg [3*COLOR_BITS-1:0] rgb;
always @(posedge clock)
begin
if (reset) begin
RedOut_b = {COLOR_BITS{1'b0}};
BlueOut_b = {COLOR_BITS{1'b0}};
GreenOut_b = {COLOR_BITS{1'b0}};
end else begin
if (Write_a) begin
memory[Address_a] = DataIn_a;
end
rgb = memory[Address_b];
RedOut_b = gamma_red[rgb[COLOR_BITS-1:0]];
GreenOut_b = gamma_green[rgb[2*COLOR_BITS-1:COLOR_BITS]];
BlueOut_b = gamma_blue[rgb[3*COLOR_BITS-1:2*COLOR_BITS]];
end
end
always @(posedge clock)
begin
if (reset) begin
DataOut_gamma <= {COLOR_BITS{1'bZ}};
end else begin
if (Write_gamma)
begin
gamma_red[Address_gamma[COLOR_BITS-1:0]] <= DataIn_gamma[COLOR_BITS-1:0];
gamma_green[Address_gamma[COLOR_BITS-1:0]] <= DataIn_gamma[(2*COLOR_BITS)-1:COLOR_BITS];
gamma_blue[Address_gamma[COLOR_BITS-1:0]] <= DataIn_gamma[(3*COLOR_BITS)-1:2*COLOR_BITS];
end
if (Read_gamma)
DataOut_gamma <= {gamma_blue[Address_gamma[COLOR_BITS-1:0]], gamma_green[Address_gamma[COLOR_BITS-1:0]], gamma_red[Address_gamma[COLOR_BITS-1:0]]};
else
DataOut_gamma <= {COLOR_BITS{1'bZ}};
end
end
endmodule | module LedPanelMemory(
input wire clock,
input wire reset,
input wire [ADDR_LINES-1:0] Address_a,
input wire [3*COLOR_BITS-1:0] DataIn_a,
input wire Write_a,
input wire [COLOR_BITS-1:0] Address_gamma,
input wire [3*COLOR_BITS-1:0] DataIn_gamma,
output reg [3*COLOR_BITS-1:0] DataOut_gamma,
input wire Write_gamma,
input wire Read_gamma,
input wire [ADDR_LINES-1:0] Address_b,
output reg [COLOR_BITS-1:0] RedOut_b,
output reg [COLOR_BITS-1:0] GreenOut_b,
output reg [COLOR_BITS-1:0] BlueOut_b
); |
parameter ADDR_LINES = 10;
parameter COLOR_BITS = 8;
reg [3*COLOR_BITS-1:0] memory[(1<<ADDR_LINES)-1:0];
reg [COLOR_BITS-1:0] gamma_red [(1<<COLOR_BITS)-1:0];
reg [COLOR_BITS-1:0] gamma_green[(1<<COLOR_BITS)-1:0];
reg [COLOR_BITS-1:0] gamma_blue [(1<<COLOR_BITS)-1:0];
integer k;
initial
begin
for(k=0;k< (1<<ADDR_LINES); k = k + 1)
memory[k] = k;
end
initial
begin
for(k=0; k< (1<<COLOR_BITS); k = k + 1)
begin
gamma_red[k] = k;
gamma_blue[k] = k;
gamma_green[k] = k;
end
end
reg [3*COLOR_BITS-1:0] rgb;
always @(posedge clock)
begin
if (reset) begin
RedOut_b = {COLOR_BITS{1'b0}};
BlueOut_b = {COLOR_BITS{1'b0}};
GreenOut_b = {COLOR_BITS{1'b0}};
end else begin
if (Write_a) begin
memory[Address_a] = DataIn_a;
end
rgb = memory[Address_b];
RedOut_b = gamma_red[rgb[COLOR_BITS-1:0]];
GreenOut_b = gamma_green[rgb[2*COLOR_BITS-1:COLOR_BITS]];
BlueOut_b = gamma_blue[rgb[3*COLOR_BITS-1:2*COLOR_BITS]];
end
end
always @(posedge clock)
begin
if (reset) begin
DataOut_gamma <= {COLOR_BITS{1'bZ}};
end else begin
if (Write_gamma)
begin
gamma_red[Address_gamma[COLOR_BITS-1:0]] <= DataIn_gamma[COLOR_BITS-1:0];
gamma_green[Address_gamma[COLOR_BITS-1:0]] <= DataIn_gamma[(2*COLOR_BITS)-1:COLOR_BITS];
gamma_blue[Address_gamma[COLOR_BITS-1:0]] <= DataIn_gamma[(3*COLOR_BITS)-1:2*COLOR_BITS];
end
if (Read_gamma)
DataOut_gamma <= {gamma_blue[Address_gamma[COLOR_BITS-1:0]], gamma_green[Address_gamma[COLOR_BITS-1:0]], gamma_red[Address_gamma[COLOR_BITS-1:0]]};
else
DataOut_gamma <= {COLOR_BITS{1'bZ}};
end
end
endmodule | 0 |
5,007 | data/full_repos/permissive/112823543/Avalon_LedPanel _Client_Server/Simulation/StandardSimulation_tb.v | 112,823,543 | StandardSimulation_tb.v | v | 154 | 117 | [] | [] | [] | null | line:88: before: "(" | null | 1: b'%Error: Cannot find file containing module: _Client_Server/Simulation,data/full_repos/permissive/112823543\n ... Looked in:\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server/Simulation,data/full_repos/permissive/112823543\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server/Simulation,data/full_repos/permissive/112823543.v\n data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server/Simulation,data/full_repos/permissive/112823543.sv\n _Client_Server/Simulation,data/full_repos/permissive/112823543\n _Client_Server/Simulation,data/full_repos/permissive/112823543.v\n _Client_Server/Simulation,data/full_repos/permissive/112823543.sv\n obj_dir/_Client_Server/Simulation,data/full_repos/permissive/112823543\n obj_dir/_Client_Server/Simulation,data/full_repos/permissive/112823543.v\n obj_dir/_Client_Server/Simulation,data/full_repos/permissive/112823543.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/112823543/Avalon_LedPanel\n%Error: Cannot find file containing module: _Client_Server/Simulation/StandardSimulation_tb.v\n%Error: Exiting due to 3 error(s)\n' | 5,388 | module | module StandardAnimation_tb ();
reg clock_clk;
reg reset_rst;
reg v_sync;
reg [2:0] s0_address;
reg s0_write;
reg s0_read;
wire [31:0] s0_readdata;
reg [31:0] s0_writedata;
reg [1:0] event_trigger;
wire red1, red2, green1, green2, blue1, blue2;
reg [5:0] col1, col2;
reg [3:0] row1, row2;
reg [3:0] bitplane1, bitplane2;
StandardAnimation #(
.NUM_REGIONS(2),
.DISPLAY_ROWS_LINES(4),
.DISPLAY_COLS_LINES(6),
.COLOR_BITS(8)
) DUT(
.clock_clk(clock_clk),
.reset_rst(reset_rst),
.v_sync(v_sync),
.s0_address(s0_address),
.s0_read(s0_read),
.s0_readdata(s0_readdata),
.s0_write(s0_write),
.s0_writedata(s0_writedata),
.event_trigger(event_trigger),
.col1(col1),
.row1(row1),
.bitplane1(bitplane1),
.red1(red1),
.green1(green1),
.blue1(blue1),
.col2(col2),
.row2(row2),
.bitplane2(bitplane2),
.red2(red2),
.green2(green2),
.blue2(blue2)
);
task writeAvalonMM;
input [3:0] addr;
input [31:0] val;
begin
@(negedge clock_clk);
s0_address = addr;
s0_write = 1;
s0_writedata = val;
@(posedge clock_clk);
s0_write = 0;
end
endtask
initial
begin
reset_rst = 1;
clock_clk = 0;
v_sync = 0;
s0_address = 0;
s0_write = 0;
s0_read = 0;
s0_writedata = 0;
event_trigger = 2'b0;
end
initial
begin
forever #2.5 clock_clk = ~clock_clk;
end
initial
begin
repeat (5) @(posedge clock_clk);
reset_rst = 0;
repeat (5) @(posedge clock_clk);
writeAvalonMM(0, {8'd3, 8'd9, 8'd2, 8'd5});
writeAvalonMM(1, {8'd0, 8'h55, 8'haa, 8'd255});
col1 = 0;
col2 = 0;
row1 = 0;
row2 = 3;
bitplane1 = 0;
bitplane2 = 0;
event_trigger[0] = 0;
repeat (5) @(posedge clock_clk);
v_sync = 1;
repeat (2) @(posedge clock_clk);
v_sync = 0;
repeat (5) @(posedge clock_clk);
event_trigger[0] = 1;
repeat (15) @(posedge clock_clk);
v_sync = 1;
repeat (2) @(posedge clock_clk);
v_sync = 0;
repeat (5) @(posedge clock_clk);
v_sync = 1;
repeat (2) @(posedge clock_clk);
v_sync = 0;
repeat (5) @(posedge clock_clk);
event_trigger[0] = 0;
repeat (15) @(posedge clock_clk);
v_sync = 1;
repeat (2) @(posedge clock_clk);
v_sync = 0;
repeat (5) @(posedge clock_clk);
v_sync = 1;
repeat (2) @(posedge clock_clk);
v_sync = 0;
repeat (5) @(posedge clock_clk);
v_sync = 1;
repeat (2) @(posedge clock_clk);
v_sync = 0;
repeat (16) @(posedge clock_clk);
$stop;
end
always @(posedge clock_clk)
begin
if (!v_sync) begin
end
end
endmodule | module StandardAnimation_tb (); |
reg clock_clk;
reg reset_rst;
reg v_sync;
reg [2:0] s0_address;
reg s0_write;
reg s0_read;
wire [31:0] s0_readdata;
reg [31:0] s0_writedata;
reg [1:0] event_trigger;
wire red1, red2, green1, green2, blue1, blue2;
reg [5:0] col1, col2;
reg [3:0] row1, row2;
reg [3:0] bitplane1, bitplane2;
StandardAnimation #(
.NUM_REGIONS(2),
.DISPLAY_ROWS_LINES(4),
.DISPLAY_COLS_LINES(6),
.COLOR_BITS(8)
) DUT(
.clock_clk(clock_clk),
.reset_rst(reset_rst),
.v_sync(v_sync),
.s0_address(s0_address),
.s0_read(s0_read),
.s0_readdata(s0_readdata),
.s0_write(s0_write),
.s0_writedata(s0_writedata),
.event_trigger(event_trigger),
.col1(col1),
.row1(row1),
.bitplane1(bitplane1),
.red1(red1),
.green1(green1),
.blue1(blue1),
.col2(col2),
.row2(row2),
.bitplane2(bitplane2),
.red2(red2),
.green2(green2),
.blue2(blue2)
);
task writeAvalonMM;
input [3:0] addr;
input [31:0] val;
begin
@(negedge clock_clk);
s0_address = addr;
s0_write = 1;
s0_writedata = val;
@(posedge clock_clk);
s0_write = 0;
end
endtask
initial
begin
reset_rst = 1;
clock_clk = 0;
v_sync = 0;
s0_address = 0;
s0_write = 0;
s0_read = 0;
s0_writedata = 0;
event_trigger = 2'b0;
end
initial
begin
forever #2.5 clock_clk = ~clock_clk;
end
initial
begin
repeat (5) @(posedge clock_clk);
reset_rst = 0;
repeat (5) @(posedge clock_clk);
writeAvalonMM(0, {8'd3, 8'd9, 8'd2, 8'd5});
writeAvalonMM(1, {8'd0, 8'h55, 8'haa, 8'd255});
col1 = 0;
col2 = 0;
row1 = 0;
row2 = 3;
bitplane1 = 0;
bitplane2 = 0;
event_trigger[0] = 0;
repeat (5) @(posedge clock_clk);
v_sync = 1;
repeat (2) @(posedge clock_clk);
v_sync = 0;
repeat (5) @(posedge clock_clk);
event_trigger[0] = 1;
repeat (15) @(posedge clock_clk);
v_sync = 1;
repeat (2) @(posedge clock_clk);
v_sync = 0;
repeat (5) @(posedge clock_clk);
v_sync = 1;
repeat (2) @(posedge clock_clk);
v_sync = 0;
repeat (5) @(posedge clock_clk);
event_trigger[0] = 0;
repeat (15) @(posedge clock_clk);
v_sync = 1;
repeat (2) @(posedge clock_clk);
v_sync = 0;
repeat (5) @(posedge clock_clk);
v_sync = 1;
repeat (2) @(posedge clock_clk);
v_sync = 0;
repeat (5) @(posedge clock_clk);
v_sync = 1;
repeat (2) @(posedge clock_clk);
v_sync = 0;
repeat (16) @(posedge clock_clk);
$stop;
end
always @(posedge clock_clk)
begin
if (!v_sync) begin
end
end
endmodule | 0 |
5,008 | data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v | 112,823,543 | PwmOut_Avalon_tb.v | v | 90 | 77 | [] | [] | [] | null | line:77: before: "(" | null | 1: b'%Error: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:34: syntax error, unexpected \'@\'\n @(posedge clock);\n ^\n%Error: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:38: syntax error, unexpected \'@\'\n @(posedge clock);\n ^\n%Error: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:49: syntax error, unexpected \'@\'\n @(posedge clock);\n ^\n%Error: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:53: syntax error, unexpected \'@\'\n @(posedge clock);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n initial forever #2.5 clock = ~clock;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10 reset = 0;\n ^\n%Error: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:75: syntax error, unexpected \'@\'\n @(posedge clock);\n ^\n%Error: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:84: syntax error, unexpected \'@\'\n @(negedge pwm[3]);\n ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n' | 5,390 | module | module PwmOut_Avalon_tb ();
reg clock;
reg reset;
reg [31:0] s0_writedata;
reg [4:0] s0_address;
wire [31:0] s0_readdata;
reg s0_write;
reg s0_read;
wire [3:0] pwm;
PwmOut_Avalon #(.NUMBER_OUTPUTS(3)) DUT(
.clock_clk(clock),
.reset_reset(reset),
.s0_command_address(s0_address),
.s0_command_read(s0_read),
.s0_command_write(s0_write),
.s0_command_readdata(s0_readdata),
.s0_command_writedata(s0_writedata),
.pwm(pwm)
);
task SetPrescaler;
input [31:0] prescaler;
begin
@(posedge clock);
s0_address = 17;
s0_writedata = prescaler;
s0_write = 1;
@(posedge clock);
s0_write = 0;
end
endtask
task SetPwm;
input [3:0] channel;
input [15:0] frequency;
input [15:0] duty_cycle;
begin
@(posedge clock);
s0_address = channel;
s0_writedata = {duty_cycle, frequency};
s0_write = 1;
@(posedge clock);
s0_write = 0;
end
endtask
initial begin
clock = 0;
reset = 0;
end
initial forever #2.5 clock = ~clock;
initial begin
reset = 1;
s0_write = 0;
s0_read = 0;
s0_writedata = 0;
#10 reset = 0;
@(posedge clock);
SetPrescaler(1);
SetPwm(0, 1000, 10);
SetPwm(1, 1000, 20);
SetPwm(2, 1000, 30);
SetPwm(3, 1000, 40);
@(negedge pwm[3]);
$stop;
end
endmodule | module PwmOut_Avalon_tb (); |
reg clock;
reg reset;
reg [31:0] s0_writedata;
reg [4:0] s0_address;
wire [31:0] s0_readdata;
reg s0_write;
reg s0_read;
wire [3:0] pwm;
PwmOut_Avalon #(.NUMBER_OUTPUTS(3)) DUT(
.clock_clk(clock),
.reset_reset(reset),
.s0_command_address(s0_address),
.s0_command_read(s0_read),
.s0_command_write(s0_write),
.s0_command_readdata(s0_readdata),
.s0_command_writedata(s0_writedata),
.pwm(pwm)
);
task SetPrescaler;
input [31:0] prescaler;
begin
@(posedge clock);
s0_address = 17;
s0_writedata = prescaler;
s0_write = 1;
@(posedge clock);
s0_write = 0;
end
endtask
task SetPwm;
input [3:0] channel;
input [15:0] frequency;
input [15:0] duty_cycle;
begin
@(posedge clock);
s0_address = channel;
s0_writedata = {duty_cycle, frequency};
s0_write = 1;
@(posedge clock);
s0_write = 0;
end
endtask
initial begin
clock = 0;
reset = 0;
end
initial forever #2.5 clock = ~clock;
initial begin
reset = 1;
s0_write = 0;
s0_read = 0;
s0_writedata = 0;
#10 reset = 0;
@(posedge clock);
SetPrescaler(1);
SetPwm(0, 1000, 10);
SetPwm(1, 1000, 20);
SetPwm(2, 1000, 30);
SetPwm(3, 1000, 40);
@(negedge pwm[3]);
$stop;
end
endmodule | 0 |
5,010 | data/full_repos/permissive/112861503/src/clkdiv.v | 112,861,503 | clkdiv.v | v | 25 | 51 | [] | [] | [] | [(1, 25)] | null | data/verilator_xmls/93a60712-1a50-4ae4-bec1-75f7795cd057.xml | null | 5,392 | module | module clkdiv #(
parameter c_div = 4
)(
input i_clk,
output o_clk
);
localparam c_div_2 = c_div / 2;
localparam c_div_2_1 = c_div_2 - 1;
localparam c_width = $clog2(c_div_2);
reg [c_width-1:0] r_count = 0;
reg r_clk = 0;
always @(posedge i_clk) begin
if (r_count == c_div_2_1[c_width-1:0]) begin
r_count <= 0;
r_clk <= ~r_clk;
end else begin
r_count <= r_count + 1;
end
end
assign o_clk = r_clk;
endmodule | module clkdiv #(
parameter c_div = 4
)(
input i_clk,
output o_clk
); |
localparam c_div_2 = c_div / 2;
localparam c_div_2_1 = c_div_2 - 1;
localparam c_width = $clog2(c_div_2);
reg [c_width-1:0] r_count = 0;
reg r_clk = 0;
always @(posedge i_clk) begin
if (r_count == c_div_2_1[c_width-1:0]) begin
r_count <= 0;
r_clk <= ~r_clk;
end else begin
r_count <= r_count + 1;
end
end
assign o_clk = r_clk;
endmodule | 1 |
5,011 | data/full_repos/permissive/112861503/src/driver.v | 112,861,503 | driver.v | v | 100 | 63 | [] | [] | [] | [(1, 100)] | null | data/verilator_xmls/52166841-cbad-4dc2-85c3-a0a97c54531b.xml | null | 5,393 | module | module driver #(
parameter c_ledboards = 30,
parameter c_bpc = 12,
parameter c_frame_period = 16666,
parameter c_channels = c_ledboards * 32,
parameter c_addr_w = $clog2(c_channels)
)(
input i_clk,
input [c_bpc-1:0] i_data,
output [c_addr_w-1:0] o_addr,
output o_clk,
output o_dai,
output o_lat
);
localparam c_frame_period_1 = c_frame_period - 1;
localparam c_channels_1 = c_channels - 1;
localparam c_bpc_1 = c_bpc - 1;
localparam c_count_width = $clog2(c_frame_period);
localparam c_bit_count_width = $clog2(c_bpc);
reg [c_count_width-1:0] r_count = 0;
reg [c_addr_w-1:0] r_addr = 0;
reg [c_bit_count_width-1:0] r_bitcount = 0;
localparam s_wait = 3'd0;
localparam s_load = 3'd1;
localparam s_prep = 3'd2;
localparam s_send = 3'd3;
localparam s_latch = 3'd4;
reg [2:0] r_state = s_wait;
reg r_dai = 0;
reg r_lat = 0;
always @(posedge i_clk) begin
if (r_count == c_frame_period_1[c_count_width-1:0]) begin
r_count <= 0;
end else begin
r_count <= r_count + 1;
end
end
always @(negedge i_clk) begin
if (r_state == s_send) begin
r_bitcount <= r_bitcount + 1;
end else begin
r_bitcount <= 0;
end
end
always @(posedge i_clk) begin
case (r_state)
s_wait: begin
if (r_count == 0) begin
r_addr <= 0;
r_state <= s_load;
end
end
s_load: begin
r_state <= s_prep;
end
s_prep: begin
r_state <= s_send;
r_dai <= i_data[c_bpc - 1];
end
s_send: begin
if (r_bitcount == c_bpc[c_bit_count_width-1:0]) begin
if (r_addr == c_channels_1[c_addr_w-1:0]) begin
r_state <= s_latch;
end else begin
r_addr <= r_addr + 1;
r_dai <= 0;
r_state <= s_load;
end
end else begin
r_dai <= i_data[c_bpc - r_bitcount - 1];
end
end
s_latch: begin
if (r_lat == 1) begin
r_lat <= 0;
r_state <= s_wait;
end else begin
r_lat <= 1;
end
end
default: begin
end
endcase
end
assign o_addr = ((r_addr >> 4) << 4) + (15 - (r_addr % 16));
assign o_clk = ~i_clk & (r_state == s_send);
assign o_dai = r_dai;
assign o_lat = r_lat;
endmodule | module driver #(
parameter c_ledboards = 30,
parameter c_bpc = 12,
parameter c_frame_period = 16666,
parameter c_channels = c_ledboards * 32,
parameter c_addr_w = $clog2(c_channels)
)(
input i_clk,
input [c_bpc-1:0] i_data,
output [c_addr_w-1:0] o_addr,
output o_clk,
output o_dai,
output o_lat
); |
localparam c_frame_period_1 = c_frame_period - 1;
localparam c_channels_1 = c_channels - 1;
localparam c_bpc_1 = c_bpc - 1;
localparam c_count_width = $clog2(c_frame_period);
localparam c_bit_count_width = $clog2(c_bpc);
reg [c_count_width-1:0] r_count = 0;
reg [c_addr_w-1:0] r_addr = 0;
reg [c_bit_count_width-1:0] r_bitcount = 0;
localparam s_wait = 3'd0;
localparam s_load = 3'd1;
localparam s_prep = 3'd2;
localparam s_send = 3'd3;
localparam s_latch = 3'd4;
reg [2:0] r_state = s_wait;
reg r_dai = 0;
reg r_lat = 0;
always @(posedge i_clk) begin
if (r_count == c_frame_period_1[c_count_width-1:0]) begin
r_count <= 0;
end else begin
r_count <= r_count + 1;
end
end
always @(negedge i_clk) begin
if (r_state == s_send) begin
r_bitcount <= r_bitcount + 1;
end else begin
r_bitcount <= 0;
end
end
always @(posedge i_clk) begin
case (r_state)
s_wait: begin
if (r_count == 0) begin
r_addr <= 0;
r_state <= s_load;
end
end
s_load: begin
r_state <= s_prep;
end
s_prep: begin
r_state <= s_send;
r_dai <= i_data[c_bpc - 1];
end
s_send: begin
if (r_bitcount == c_bpc[c_bit_count_width-1:0]) begin
if (r_addr == c_channels_1[c_addr_w-1:0]) begin
r_state <= s_latch;
end else begin
r_addr <= r_addr + 1;
r_dai <= 0;
r_state <= s_load;
end
end else begin
r_dai <= i_data[c_bpc - r_bitcount - 1];
end
end
s_latch: begin
if (r_lat == 1) begin
r_lat <= 0;
r_state <= s_wait;
end else begin
r_lat <= 1;
end
end
default: begin
end
endcase
end
assign o_addr = ((r_addr >> 4) << 4) + (15 - (r_addr % 16));
assign o_clk = ~i_clk & (r_state == s_send);
assign o_dai = r_dai;
assign o_lat = r_lat;
endmodule | 1 |
5,014 | data/full_repos/permissive/112861503/src/lamp.v | 112,861,503 | lamp.v | v | 206 | 85 | [] | [] | [] | null | line:25: before: "#" | null | 1: b'%Error: data/full_repos/permissive/112861503/src/lamp.v:1: Cannot find include file: clkdiv.v\n`include "clkdiv.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112861503/src,data/full_repos/permissive/112861503/clkdiv.v\n data/full_repos/permissive/112861503/src,data/full_repos/permissive/112861503/clkdiv.v.v\n data/full_repos/permissive/112861503/src,data/full_repos/permissive/112861503/clkdiv.v.sv\n clkdiv.v\n clkdiv.v.v\n clkdiv.v.sv\n obj_dir/clkdiv.v\n obj_dir/clkdiv.v.v\n obj_dir/clkdiv.v.sv\n%Error: data/full_repos/permissive/112861503/src/lamp.v:2: Cannot find include file: protocol.v\n`include "protocol.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/112861503/src/lamp.v:3: Cannot find include file: framebuffer.v\n`include "framebuffer.v" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/112861503/src/lamp.v:4: Cannot find include file: framemanager.v\n`include "framemanager.v" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/112861503/src/lamp.v:5: Cannot find include file: animator.v\n`include "animator.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/112861503/src/lamp.v:6: Cannot find include file: driver.v\n`include "driver.v" \n ^~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n' | 5,396 | module | module lamp #(
parameter c_freq = 100000000
)(
input i_clk,
input i_dck,
input i_cs,
input i_mosi,
output o_clk,
output o_dai,
output o_lat
);
localparam c_ledboards = 30;
localparam c_framerate = 120;
localparam c_max_time = 1024;
localparam c_max_type = 64;
localparam c_bpc = 12;
localparam c_clock = 2000000;
localparam c_channels = c_ledboards * 32;
localparam c_addr_w = $clog2(c_channels);
localparam c_time_w = $clog2(c_max_time);
localparam c_type_w = $clog2(c_max_type);
wire w_clk;
wire [c_bpc-1:0] w_protocol_data;
wire [c_time_w-1:0] w_protocol_time;
wire [c_type_w-1:0] w_protocol_type;
wire [c_addr_w-1:0] w_protocol_addr;
wire w_protocol_write;
wire w_protocol_ready;
wire [c_bpc-1:0] w_next_data;
wire [c_time_w-1:0] w_next_time;
wire [c_type_w-1:0] w_next_type;
wire [c_addr_w-1:0] w_next_addr;
wire w_next_write;
wire [c_bpc-1:0] w_target_data;
wire [c_time_w-1:0] w_target_time;
wire [c_type_w-1:0] w_target_type;
wire [c_time_w-1:0] w_start_time;
wire [c_bpc-1:0] w_animator_data;
wire [c_addr_w-1:0] w_animator_addr;
wire w_animator_write;
wire w_animator_drq;
wire [c_bpc-1:0] w_current_data;
wire [c_addr_w-1:0] w_current_addr;
wire [c_addr_w-1:0] w_driver_addr;
wire w_driver_clk;
wire w_driver_dai;
wire w_driver_lat;
clkdiv #(
.c_div (c_freq / c_clock)
) clkdiv (
.i_clk (i_clk),
.o_clk (w_clk)
);
protocol #(
.c_ledboards (c_ledboards),
.c_bpc (c_bpc),
.c_max_time (c_max_time),
.c_max_type (c_max_type)
) protocol (
.i_clk (w_clk),
.i_dck (i_dck),
.i_cs (i_cs),
.i_mosi (i_mosi),
.o_wen (w_protocol_write),
.o_addr (w_protocol_addr),
.o_data (w_protocol_data),
.o_time (w_protocol_time),
.o_type (w_protocol_type),
.o_ready (w_protocol_ready)
);
framebuffer #(
.c_ledboards (c_ledboards),
.c_bpc (c_bpc),
.c_max_time (c_max_time),
.c_max_type (c_max_type)
) next (
.i_clk (w_clk),
.i_wen (w_protocol_write),
.i_waddr (w_protocol_addr),
.i_wdata (w_protocol_data),
.i_time (w_protocol_time),
.i_type (w_protocol_type),
.i_raddr (w_next_addr),
.o_rdata (w_next_data),
.o_time (w_next_time),
.o_type (w_next_type)
);
framemanager #(
.c_ledboards (c_ledboards),
.c_max_time (c_max_time)
) manager (
.i_clk (w_clk),
.i_drq (w_animator_drq | w_protocol_ready),
.i_target_time (w_target_time),
.o_addr (w_next_addr),
.o_start_time (w_start_time),
.o_wen (w_next_write),
.o_drq ()
);
framebuffer #(
.c_ledboards (c_ledboards),
.c_bpc (c_bpc),
.c_max_time (c_max_time),
.c_max_type (c_max_type)
) target (
.i_clk (w_clk),
.i_wen (w_next_write),
.i_waddr (w_next_addr),
.i_wdata (w_next_data),
.i_time (w_next_time),
.i_type (w_next_type),
.i_raddr (w_animator_addr),
.o_rdata (w_target_data),
.o_time (w_target_time),
.o_type (w_target_type)
);
animator #(
.c_ledboards (c_ledboards),
.c_bpc (c_bpc),
.c_max_time (c_max_time),
.c_max_type (c_max_type)
) animator (
.i_clk (w_clk),
.i_drq (w_driver_lat),
.i_target_data (w_target_data),
.i_current_data (w_current_data),
.i_type (w_target_type),
.i_target_time (w_target_time),
.i_start_time (w_start_time),
.o_wen (w_animator_write),
.o_addr (w_animator_addr),
.o_data (w_animator_data),
.o_drq (w_animator_drq)
);
framebuffer #(
.c_ledboards (c_ledboards),
.c_bpc (c_bpc),
.c_max_time (c_max_time),
.c_max_type (c_max_type)
) current (
.i_clk (w_clk),
.i_wen (w_animator_write),
.i_waddr (w_animator_addr),
.i_wdata (w_animator_data),
.i_time (), .i_type (),
.i_raddr (w_current_addr),
.o_rdata (w_current_data),
.o_time (), .o_type ()
);
driver #(
.c_ledboards (c_ledboards),
.c_bpc (c_bpc),
.c_frame_period (c_clock / c_framerate)
) driver (
.i_clk (w_clk),
.i_data (w_current_data),
.o_addr (w_driver_addr),
.o_clk (w_driver_clk),
.o_dai (w_driver_dai),
.o_lat (w_driver_lat)
);
assign w_current_addr = w_driver_addr | w_animator_addr;
assign o_clk = w_driver_clk;
assign o_dai = w_driver_dai;
assign o_lat = w_driver_lat;
endmodule | module lamp #(
parameter c_freq = 100000000
)(
input i_clk,
input i_dck,
input i_cs,
input i_mosi,
output o_clk,
output o_dai,
output o_lat
); |
localparam c_ledboards = 30;
localparam c_framerate = 120;
localparam c_max_time = 1024;
localparam c_max_type = 64;
localparam c_bpc = 12;
localparam c_clock = 2000000;
localparam c_channels = c_ledboards * 32;
localparam c_addr_w = $clog2(c_channels);
localparam c_time_w = $clog2(c_max_time);
localparam c_type_w = $clog2(c_max_type);
wire w_clk;
wire [c_bpc-1:0] w_protocol_data;
wire [c_time_w-1:0] w_protocol_time;
wire [c_type_w-1:0] w_protocol_type;
wire [c_addr_w-1:0] w_protocol_addr;
wire w_protocol_write;
wire w_protocol_ready;
wire [c_bpc-1:0] w_next_data;
wire [c_time_w-1:0] w_next_time;
wire [c_type_w-1:0] w_next_type;
wire [c_addr_w-1:0] w_next_addr;
wire w_next_write;
wire [c_bpc-1:0] w_target_data;
wire [c_time_w-1:0] w_target_time;
wire [c_type_w-1:0] w_target_type;
wire [c_time_w-1:0] w_start_time;
wire [c_bpc-1:0] w_animator_data;
wire [c_addr_w-1:0] w_animator_addr;
wire w_animator_write;
wire w_animator_drq;
wire [c_bpc-1:0] w_current_data;
wire [c_addr_w-1:0] w_current_addr;
wire [c_addr_w-1:0] w_driver_addr;
wire w_driver_clk;
wire w_driver_dai;
wire w_driver_lat;
clkdiv #(
.c_div (c_freq / c_clock)
) clkdiv (
.i_clk (i_clk),
.o_clk (w_clk)
);
protocol #(
.c_ledboards (c_ledboards),
.c_bpc (c_bpc),
.c_max_time (c_max_time),
.c_max_type (c_max_type)
) protocol (
.i_clk (w_clk),
.i_dck (i_dck),
.i_cs (i_cs),
.i_mosi (i_mosi),
.o_wen (w_protocol_write),
.o_addr (w_protocol_addr),
.o_data (w_protocol_data),
.o_time (w_protocol_time),
.o_type (w_protocol_type),
.o_ready (w_protocol_ready)
);
framebuffer #(
.c_ledboards (c_ledboards),
.c_bpc (c_bpc),
.c_max_time (c_max_time),
.c_max_type (c_max_type)
) next (
.i_clk (w_clk),
.i_wen (w_protocol_write),
.i_waddr (w_protocol_addr),
.i_wdata (w_protocol_data),
.i_time (w_protocol_time),
.i_type (w_protocol_type),
.i_raddr (w_next_addr),
.o_rdata (w_next_data),
.o_time (w_next_time),
.o_type (w_next_type)
);
framemanager #(
.c_ledboards (c_ledboards),
.c_max_time (c_max_time)
) manager (
.i_clk (w_clk),
.i_drq (w_animator_drq | w_protocol_ready),
.i_target_time (w_target_time),
.o_addr (w_next_addr),
.o_start_time (w_start_time),
.o_wen (w_next_write),
.o_drq ()
);
framebuffer #(
.c_ledboards (c_ledboards),
.c_bpc (c_bpc),
.c_max_time (c_max_time),
.c_max_type (c_max_type)
) target (
.i_clk (w_clk),
.i_wen (w_next_write),
.i_waddr (w_next_addr),
.i_wdata (w_next_data),
.i_time (w_next_time),
.i_type (w_next_type),
.i_raddr (w_animator_addr),
.o_rdata (w_target_data),
.o_time (w_target_time),
.o_type (w_target_type)
);
animator #(
.c_ledboards (c_ledboards),
.c_bpc (c_bpc),
.c_max_time (c_max_time),
.c_max_type (c_max_type)
) animator (
.i_clk (w_clk),
.i_drq (w_driver_lat),
.i_target_data (w_target_data),
.i_current_data (w_current_data),
.i_type (w_target_type),
.i_target_time (w_target_time),
.i_start_time (w_start_time),
.o_wen (w_animator_write),
.o_addr (w_animator_addr),
.o_data (w_animator_data),
.o_drq (w_animator_drq)
);
framebuffer #(
.c_ledboards (c_ledboards),
.c_bpc (c_bpc),
.c_max_time (c_max_time),
.c_max_type (c_max_type)
) current (
.i_clk (w_clk),
.i_wen (w_animator_write),
.i_waddr (w_animator_addr),
.i_wdata (w_animator_data),
.i_time (), .i_type (),
.i_raddr (w_current_addr),
.o_rdata (w_current_data),
.o_time (), .o_type ()
);
driver #(
.c_ledboards (c_ledboards),
.c_bpc (c_bpc),
.c_frame_period (c_clock / c_framerate)
) driver (
.i_clk (w_clk),
.i_data (w_current_data),
.o_addr (w_driver_addr),
.o_clk (w_driver_clk),
.o_dai (w_driver_dai),
.o_lat (w_driver_lat)
);
assign w_current_addr = w_driver_addr | w_animator_addr;
assign o_clk = w_driver_clk;
assign o_dai = w_driver_dai;
assign o_lat = w_driver_lat;
endmodule | 1 |
5,015 | data/full_repos/permissive/112861503/src/protocol.v | 112,861,503 | protocol.v | v | 205 | 95 | [] | [] | [] | null | line:74: before: "(" | data/verilator_xmls/80f326b2-8008-473b-8cd3-9c99afbcb024.xml | null | 5,397 | module | module protocol #(
parameter c_ledboards = 30,
parameter c_bpc = 12,
parameter c_max_time = 1024,
parameter c_max_type = 64,
parameter c_channels = c_ledboards * 32,
parameter c_addr_w = $clog2(c_channels),
parameter c_time_w = $clog2(c_max_time),
parameter c_type_w = $clog2(c_max_type)
)(
input i_clk,
input i_dck,
input i_cs,
input i_mosi,
output o_wen,
output [c_addr_w-1:0] o_addr,
output [c_bpc-1:0] o_data,
output [c_time_w-1:0] o_time,
output [c_type_w-1:0] o_type,
output o_ready
);
reg r_prev_dck = 0;
localparam c_command_bits = 5;
localparam c_length_bits = 11;
localparam c_kf_type_bits = 6;
localparam c_kf_duration_bits = 10;
localparam c_command_bit_w = $clog2(c_command_bits);
localparam c_length_bit_w = $clog2(c_length_bits);
localparam c_kf_type_bit_w = $clog2(c_kf_type_bits);
localparam c_kf_duration_bit_w = $clog2(c_kf_duration_bits);
reg [c_command_bits-1:0] r_command = 0;
reg [c_length_bits-1:0] r_length = 0;
reg [c_kf_type_bits-1:0] r_kf_type = 0;
reg [c_kf_duration_bits-1:0] r_kf_duration = 0;
reg [c_command_bit_w-1:0] r_command_bit = 0;
reg [c_length_bit_w-1:0] r_length_bit = 0;
reg [c_kf_type_bit_w-1:0] r_kf_type_bit = 0;
reg [c_kf_duration_bit_w-1:0] r_kf_duration_bit = 0;
reg r_kf_flag = 0;
reg [2:0] r_bitcount = 0;
reg r_wen = 0;
reg [c_addr_w-1:0] r_addr = 0;
reg [c_bpc-1:0] r_data = 0;
reg [3:0] r_databit = 0;
localparam s_global_wait = 3'd0;
localparam s_global_command = 3'd1;
localparam s_global_length = 3'd2;
localparam s_global_execute = 3'd3;
localparam s_global_ready = 3'd4;
reg [2:0] r_global_state = s_global_wait;
localparam s_keyframe_wait = 2'd0;
localparam s_keyframe_type = 2'd1;
localparam s_keyframe_duration = 2'd2;
localparam s_keyframe_data = 2'd3;
reg [1:0] r_keyframe_state = s_keyframe_wait;
localparam c_command_keyframe = 5'd0;
always @(posedge i_clk) begin
if (i_cs == 0) begin
if (i_dck != r_prev_dck) begin
r_prev_dck = i_dck;
if(i_dck == 1) begin
receiveBit(i_mosi);
end
end
end else begin
r_prev_dck = 0;
r_global_state = s_global_wait;
r_keyframe_state = s_keyframe_wait;
r_command_bit = 0;
r_length_bit = 0;
r_kf_type_bit = 0;
r_kf_duration_bit = 0;
r_kf_flag = 0;
r_bitcount = 0;
r_databit = 0;
r_wen = 0;
r_addr = 0;
r_data = 0;
end
end
task receiveBit;
input i_bit;
begin
case (r_global_state)
s_global_wait: begin
r_global_state = s_global_command;
r_command[c_command_bits - 1] = i_bit;
r_command_bit = 1;
r_keyframe_state = s_keyframe_wait;
end
s_global_command: begin
if (r_command_bit == c_command_bits - 1) begin
r_global_state = s_global_length;
end
r_command[c_command_bits - 1 - r_command_bit] = i_bit;
r_command_bit = r_command_bit + 1;
end
s_global_length: begin
if (r_length_bit == c_length_bits - 1) begin
r_global_state = s_global_execute;
end
r_length[c_length_bits - 1 - r_length_bit] = i_bit;
r_length_bit = r_length_bit + 1;
end
s_global_execute: begin
if (r_length == 1 && r_bitcount == 7) begin
r_global_state = s_global_ready;
end
if (r_bitcount == 7) begin
r_length = r_length - 1;
r_bitcount = 0;
end else begin
r_bitcount = r_bitcount + 1;
end
messagePump(i_bit);
end
s_global_ready: begin
r_global_state = s_global_wait;
end
default: begin
end
endcase
end
endtask
task messagePump;
input i_bit;
case (r_command)
c_command_keyframe: begin
receiveKeyframe(i_bit);
end
default: begin
end
endcase
endtask
task receiveKeyframe;
input i_bit;
begin
case (r_keyframe_state)
s_keyframe_wait: begin
r_keyframe_state = s_keyframe_type;
r_kf_type[c_kf_type_bits - 1] = i_bit;
r_kf_type_bit = 1;
end
s_keyframe_type: begin
if (r_kf_type_bit == c_kf_type_bits - 1) begin
r_keyframe_state = s_keyframe_duration;
end
r_kf_type[c_kf_type_bits - 1 - r_kf_type_bit] = i_bit;
r_kf_type_bit = r_kf_type_bit + 1;
end
s_keyframe_duration: begin
if (r_kf_duration_bit == c_kf_duration_bits - 1) begin
r_keyframe_state = s_keyframe_data;
end
r_kf_duration[c_kf_duration_bits - 1 - r_kf_duration_bit] = i_bit;
r_kf_duration_bit = r_kf_duration_bit + 1;
end
s_keyframe_data: begin
if (r_databit == 0 && r_kf_flag == 1) begin
r_addr = r_addr + 1;
end
if (r_databit == c_bpc - 2) begin
r_wen = 1;
end
if (r_databit == c_bpc - 1) begin
r_databit = 0;
r_wen = 0;
end else begin
if (r_kf_flag == 1) begin
r_databit = r_databit + 1;
end
end
r_data[c_bpc - 1 - r_databit] = i_bit;
r_kf_flag = 1;
end
default: begin
end
endcase
end
endtask
assign o_wen = r_wen;
assign o_addr = r_addr;
assign o_data = r_data;
assign o_time = r_kf_duration;
assign o_type = r_kf_type;
assign o_ready = (r_global_state == s_global_ready);
endmodule | module protocol #(
parameter c_ledboards = 30,
parameter c_bpc = 12,
parameter c_max_time = 1024,
parameter c_max_type = 64,
parameter c_channels = c_ledboards * 32,
parameter c_addr_w = $clog2(c_channels),
parameter c_time_w = $clog2(c_max_time),
parameter c_type_w = $clog2(c_max_type)
)(
input i_clk,
input i_dck,
input i_cs,
input i_mosi,
output o_wen,
output [c_addr_w-1:0] o_addr,
output [c_bpc-1:0] o_data,
output [c_time_w-1:0] o_time,
output [c_type_w-1:0] o_type,
output o_ready
); |
reg r_prev_dck = 0;
localparam c_command_bits = 5;
localparam c_length_bits = 11;
localparam c_kf_type_bits = 6;
localparam c_kf_duration_bits = 10;
localparam c_command_bit_w = $clog2(c_command_bits);
localparam c_length_bit_w = $clog2(c_length_bits);
localparam c_kf_type_bit_w = $clog2(c_kf_type_bits);
localparam c_kf_duration_bit_w = $clog2(c_kf_duration_bits);
reg [c_command_bits-1:0] r_command = 0;
reg [c_length_bits-1:0] r_length = 0;
reg [c_kf_type_bits-1:0] r_kf_type = 0;
reg [c_kf_duration_bits-1:0] r_kf_duration = 0;
reg [c_command_bit_w-1:0] r_command_bit = 0;
reg [c_length_bit_w-1:0] r_length_bit = 0;
reg [c_kf_type_bit_w-1:0] r_kf_type_bit = 0;
reg [c_kf_duration_bit_w-1:0] r_kf_duration_bit = 0;
reg r_kf_flag = 0;
reg [2:0] r_bitcount = 0;
reg r_wen = 0;
reg [c_addr_w-1:0] r_addr = 0;
reg [c_bpc-1:0] r_data = 0;
reg [3:0] r_databit = 0;
localparam s_global_wait = 3'd0;
localparam s_global_command = 3'd1;
localparam s_global_length = 3'd2;
localparam s_global_execute = 3'd3;
localparam s_global_ready = 3'd4;
reg [2:0] r_global_state = s_global_wait;
localparam s_keyframe_wait = 2'd0;
localparam s_keyframe_type = 2'd1;
localparam s_keyframe_duration = 2'd2;
localparam s_keyframe_data = 2'd3;
reg [1:0] r_keyframe_state = s_keyframe_wait;
localparam c_command_keyframe = 5'd0;
always @(posedge i_clk) begin
if (i_cs == 0) begin
if (i_dck != r_prev_dck) begin
r_prev_dck = i_dck;
if(i_dck == 1) begin
receiveBit(i_mosi);
end
end
end else begin
r_prev_dck = 0;
r_global_state = s_global_wait;
r_keyframe_state = s_keyframe_wait;
r_command_bit = 0;
r_length_bit = 0;
r_kf_type_bit = 0;
r_kf_duration_bit = 0;
r_kf_flag = 0;
r_bitcount = 0;
r_databit = 0;
r_wen = 0;
r_addr = 0;
r_data = 0;
end
end
task receiveBit;
input i_bit;
begin
case (r_global_state)
s_global_wait: begin
r_global_state = s_global_command;
r_command[c_command_bits - 1] = i_bit;
r_command_bit = 1;
r_keyframe_state = s_keyframe_wait;
end
s_global_command: begin
if (r_command_bit == c_command_bits - 1) begin
r_global_state = s_global_length;
end
r_command[c_command_bits - 1 - r_command_bit] = i_bit;
r_command_bit = r_command_bit + 1;
end
s_global_length: begin
if (r_length_bit == c_length_bits - 1) begin
r_global_state = s_global_execute;
end
r_length[c_length_bits - 1 - r_length_bit] = i_bit;
r_length_bit = r_length_bit + 1;
end
s_global_execute: begin
if (r_length == 1 && r_bitcount == 7) begin
r_global_state = s_global_ready;
end
if (r_bitcount == 7) begin
r_length = r_length - 1;
r_bitcount = 0;
end else begin
r_bitcount = r_bitcount + 1;
end
messagePump(i_bit);
end
s_global_ready: begin
r_global_state = s_global_wait;
end
default: begin
end
endcase
end
endtask
task messagePump;
input i_bit;
case (r_command)
c_command_keyframe: begin
receiveKeyframe(i_bit);
end
default: begin
end
endcase
endtask
task receiveKeyframe;
input i_bit;
begin
case (r_keyframe_state)
s_keyframe_wait: begin
r_keyframe_state = s_keyframe_type;
r_kf_type[c_kf_type_bits - 1] = i_bit;
r_kf_type_bit = 1;
end
s_keyframe_type: begin
if (r_kf_type_bit == c_kf_type_bits - 1) begin
r_keyframe_state = s_keyframe_duration;
end
r_kf_type[c_kf_type_bits - 1 - r_kf_type_bit] = i_bit;
r_kf_type_bit = r_kf_type_bit + 1;
end
s_keyframe_duration: begin
if (r_kf_duration_bit == c_kf_duration_bits - 1) begin
r_keyframe_state = s_keyframe_data;
end
r_kf_duration[c_kf_duration_bits - 1 - r_kf_duration_bit] = i_bit;
r_kf_duration_bit = r_kf_duration_bit + 1;
end
s_keyframe_data: begin
if (r_databit == 0 && r_kf_flag == 1) begin
r_addr = r_addr + 1;
end
if (r_databit == c_bpc - 2) begin
r_wen = 1;
end
if (r_databit == c_bpc - 1) begin
r_databit = 0;
r_wen = 0;
end else begin
if (r_kf_flag == 1) begin
r_databit = r_databit + 1;
end
end
r_data[c_bpc - 1 - r_databit] = i_bit;
r_kf_flag = 1;
end
default: begin
end
endcase
end
endtask
assign o_wen = r_wen;
assign o_addr = r_addr;
assign o_data = r_data;
assign o_time = r_kf_duration;
assign o_type = r_kf_type;
assign o_ready = (r_global_state == s_global_ready);
endmodule | 1 |
5,016 | data/full_repos/permissive/112861503/test/lamp_tb.v | 112,861,503 | lamp_tb.v | v | 78 | 53 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/112861503/test/lamp_tb.v:2: Cannot find include file: lamp.v\n`include "lamp.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112861503/test,data/full_repos/permissive/112861503/lamp.v\n data/full_repos/permissive/112861503/test,data/full_repos/permissive/112861503/lamp.v.v\n data/full_repos/permissive/112861503/test,data/full_repos/permissive/112861503/lamp.v.sv\n lamp.v\n lamp.v.v\n lamp.v.sv\n obj_dir/lamp.v\n obj_dir/lamp.v.v\n obj_dir/lamp.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0.025 r_clk = !r_clk; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #100000 $display($time, " 100 ms have passed");\n ^\n%Error: data/full_repos/permissive/112861503/test/lamp_tb.v:53: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("lamp.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/112861503/test/lamp_tb.v:54: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, lamp_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #100000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 3 error(s), 8 warning(s)\n' | 5,398 | module | module lamp_tb();
reg r_clk;
reg r_dck;
reg r_cs;
reg r_mosi;
wire w_clk;
wire w_dai;
wire w_lat;
integer i;
lamp #(
.c_freq (20000000)
) lamp (
.i_clk (r_clk),
.i_dck (r_dck),
.i_cs (r_cs),
.i_mosi (r_mosi),
.o_clk (w_clk),
.o_dai (w_dai),
.o_lat (w_lat)
);
initial begin
r_clk = 0;
r_dck = 0;
r_cs = 1;
r_mosi = 0;
end
always begin
#0.025 r_clk = !r_clk;
end
always begin
#100000 $display($time, " 100 ms have passed");
end
initial begin
r_cs = 0;
sendData(128'h000e0078001001001001800800800800);
r_cs = 1;
end
initial begin
$dumpfile("lamp.vcd");
$dumpvars(0, lamp_tb);
#100000 $finish;
end
task sendData;
input [127:0] i_data;
begin
r_cs = 0;
#10;
for(i=0; i<128; i=i+1) begin
#5;
r_dck = 0;
r_mosi = i_data[127 - i];
#5;
r_dck = 1;
end
#5;
r_dck = 0;
r_mosi = 0;
#10;
r_cs = 1;
end
endtask
endmodule | module lamp_tb(); |
reg r_clk;
reg r_dck;
reg r_cs;
reg r_mosi;
wire w_clk;
wire w_dai;
wire w_lat;
integer i;
lamp #(
.c_freq (20000000)
) lamp (
.i_clk (r_clk),
.i_dck (r_dck),
.i_cs (r_cs),
.i_mosi (r_mosi),
.o_clk (w_clk),
.o_dai (w_dai),
.o_lat (w_lat)
);
initial begin
r_clk = 0;
r_dck = 0;
r_cs = 1;
r_mosi = 0;
end
always begin
#0.025 r_clk = !r_clk;
end
always begin
#100000 $display($time, " 100 ms have passed");
end
initial begin
r_cs = 0;
sendData(128'h000e0078001001001001800800800800);
r_cs = 1;
end
initial begin
$dumpfile("lamp.vcd");
$dumpvars(0, lamp_tb);
#100000 $finish;
end
task sendData;
input [127:0] i_data;
begin
r_cs = 0;
#10;
for(i=0; i<128; i=i+1) begin
#5;
r_dck = 0;
r_mosi = i_data[127 - i];
#5;
r_dck = 1;
end
#5;
r_dck = 0;
r_mosi = 0;
#10;
r_cs = 1;
end
endtask
endmodule | 1 |
5,017 | data/full_repos/permissive/112861986/src/examples/1.v | 112,861,986 | 1.v | v | 19 | 42 | [] | [] | [] | [(1, 18)] | null | data/verilator_xmls/66a17145-2ea0-4ce5-849c-e3761eedbef2.xml | null | 5,399 | module | module example_1
(
input i_switch_1,
input i_switch_2,
input i_switch_3,
input i_switch_4,
output o_led_1,
output o_led_2,
output o_led_3,
output o_led_4
);
assign o_led_4 = i_switch_1;
assign o_led_3 = i_switch_2 | i_switch_1;
assign o_led_2 = i_switch_3 | i_switch_1;
assign o_led_1 = i_switch_4 | i_switch_1;
endmodule | module example_1
(
input i_switch_1,
input i_switch_2,
input i_switch_3,
input i_switch_4,
output o_led_1,
output o_led_2,
output o_led_3,
output o_led_4
); |
assign o_led_4 = i_switch_1;
assign o_led_3 = i_switch_2 | i_switch_1;
assign o_led_2 = i_switch_3 | i_switch_1;
assign o_led_1 = i_switch_4 | i_switch_1;
endmodule | 0 |
5,018 | data/full_repos/permissive/112861986/src/examples/2.v | 112,861,986 | 2.v | v | 62 | 59 | [] | [] | [] | [(1, 61)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/112861986/src/examples/2.v:23: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n : ... In instance example_2\nreg [7:0] num = 7\'h00;\n ^~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112861986/src/examples/2.v:35: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n : ... In instance example_2\n num = 7\'h00;\n ^\n%Error: data/full_repos/permissive/112861986/src/examples/2.v:38: Cannot find file containing module: \'bin_to_7seg\'\nbin_to_7seg inst\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112861986/src/examples,data/full_repos/permissive/112861986/bin_to_7seg\n data/full_repos/permissive/112861986/src/examples,data/full_repos/permissive/112861986/bin_to_7seg.v\n data/full_repos/permissive/112861986/src/examples,data/full_repos/permissive/112861986/bin_to_7seg.sv\n bin_to_7seg\n bin_to_7seg.v\n bin_to_7seg.sv\n obj_dir/bin_to_7seg\n obj_dir/bin_to_7seg.v\n obj_dir/bin_to_7seg.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 5,400 | module | module example_2
(
input i_switch_1,
input i_switch_2,
input i_switch_3,
input i_switch_4,
output o_segment1_a,
output o_segment1_b,
output o_segment1_c,
output o_segment1_d,
output o_segment1_e,
output o_segment1_f,
output o_segment1_g,
output o_segment2_a,
output o_segment2_b,
output o_segment2_c,
output o_segment2_d,
output o_segment2_e,
output o_segment2_f,
output o_segment2_g
);
reg [7:0] num = 7'h00;
reg [7:0] seg_1;
reg [7:0] seg_2;
always @(posedge i_switch_1)
begin
num = num + 1;
if (i_switch_2 == 1'b1)
num = num ^ 1;
if (i_switch_3 == 1'b1)
num = num << 1;
if (i_switch_4 == 1'b1)
num = 7'h00;
end
bin_to_7seg inst
(
.in_byte(num),
.out_seg1(seg_1),
.out_seg2(seg_2)
);
assign o_segment1_a = ~seg_2[6];
assign o_segment1_b = ~seg_2[5];
assign o_segment1_c = ~seg_2[4];
assign o_segment1_d = ~seg_2[3];
assign o_segment1_e = ~seg_2[2];
assign o_segment1_f = ~seg_2[1];
assign o_segment1_g = ~seg_2[0];
assign o_segment2_a = ~seg_1[6];
assign o_segment2_b = ~seg_1[5];
assign o_segment2_c = ~seg_1[4];
assign o_segment2_d = ~seg_1[3];
assign o_segment2_e = ~seg_1[2];
assign o_segment2_f = ~seg_1[1];
assign o_segment2_g = ~seg_1[0];
endmodule | module example_2
(
input i_switch_1,
input i_switch_2,
input i_switch_3,
input i_switch_4,
output o_segment1_a,
output o_segment1_b,
output o_segment1_c,
output o_segment1_d,
output o_segment1_e,
output o_segment1_f,
output o_segment1_g,
output o_segment2_a,
output o_segment2_b,
output o_segment2_c,
output o_segment2_d,
output o_segment2_e,
output o_segment2_f,
output o_segment2_g
); |
reg [7:0] num = 7'h00;
reg [7:0] seg_1;
reg [7:0] seg_2;
always @(posedge i_switch_1)
begin
num = num + 1;
if (i_switch_2 == 1'b1)
num = num ^ 1;
if (i_switch_3 == 1'b1)
num = num << 1;
if (i_switch_4 == 1'b1)
num = 7'h00;
end
bin_to_7seg inst
(
.in_byte(num),
.out_seg1(seg_1),
.out_seg2(seg_2)
);
assign o_segment1_a = ~seg_2[6];
assign o_segment1_b = ~seg_2[5];
assign o_segment1_c = ~seg_2[4];
assign o_segment1_d = ~seg_2[3];
assign o_segment1_e = ~seg_2[2];
assign o_segment1_f = ~seg_2[1];
assign o_segment1_g = ~seg_2[0];
assign o_segment2_a = ~seg_1[6];
assign o_segment2_b = ~seg_1[5];
assign o_segment2_c = ~seg_1[4];
assign o_segment2_d = ~seg_1[3];
assign o_segment2_e = ~seg_1[2];
assign o_segment2_f = ~seg_1[1];
assign o_segment2_g = ~seg_1[0];
endmodule | 0 |
5,019 | data/full_repos/permissive/112861986/src/examples/3.v | 112,861,986 | 3.v | v | 62 | 59 | [] | [] | [] | [(1, 61)] | null | null | 1: b"%Error: data/full_repos/permissive/112861986/src/examples/3.v:30: Cannot find file containing module: 'uart_rx'\nuart_rx uart_inst\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/112861986/src/examples,data/full_repos/permissive/112861986/uart_rx\n data/full_repos/permissive/112861986/src/examples,data/full_repos/permissive/112861986/uart_rx.v\n data/full_repos/permissive/112861986/src/examples,data/full_repos/permissive/112861986/uart_rx.sv\n uart_rx\n uart_rx.v\n uart_rx.sv\n obj_dir/uart_rx\n obj_dir/uart_rx.v\n obj_dir/uart_rx.sv\n%Error: data/full_repos/permissive/112861986/src/examples/3.v:38: Cannot find file containing module: 'bin_to_7seg'\nbin_to_7seg inst\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 5,401 | module | module example_3
(
input i_clk,
input i_switch_1,
input i_switch_2,
input i_switch_3,
input i_switch_4,
input i_uart_rx,
output o_uart_tx,
output o_segment1_a,
output o_segment1_b,
output o_segment1_c,
output o_segment1_d,
output o_segment1_e,
output o_segment1_f,
output o_segment1_g,
output o_segment2_a,
output o_segment2_b,
output o_segment2_c,
output o_segment2_d,
output o_segment2_e,
output o_segment2_f,
output o_segment2_g
);
wire [7:0] num;
wire [7:0] seg_1;
wire [7:0] seg_2;
uart_rx uart_inst
(
.i_clock(i_clk),
.i_rx_uart(i_uart_rx),
.o_rx_dv(),
.o_rx_byte(num)
);
bin_to_7seg inst
(
.in_byte(num),
.out_seg1(seg_1),
.out_seg2(seg_2)
);
assign o_segment1_a = ~seg_2[6];
assign o_segment1_b = ~seg_2[5];
assign o_segment1_c = ~seg_2[4];
assign o_segment1_d = ~seg_2[3];
assign o_segment1_e = ~seg_2[2];
assign o_segment1_f = ~seg_2[1];
assign o_segment1_g = ~seg_2[0];
assign o_segment2_a = ~seg_1[6];
assign o_segment2_b = ~seg_1[5];
assign o_segment2_c = ~seg_1[4];
assign o_segment2_d = ~seg_1[3];
assign o_segment2_e = ~seg_1[2];
assign o_segment2_f = ~seg_1[1];
assign o_segment2_g = ~seg_1[0];
endmodule | module example_3
(
input i_clk,
input i_switch_1,
input i_switch_2,
input i_switch_3,
input i_switch_4,
input i_uart_rx,
output o_uart_tx,
output o_segment1_a,
output o_segment1_b,
output o_segment1_c,
output o_segment1_d,
output o_segment1_e,
output o_segment1_f,
output o_segment1_g,
output o_segment2_a,
output o_segment2_b,
output o_segment2_c,
output o_segment2_d,
output o_segment2_e,
output o_segment2_f,
output o_segment2_g
); |
wire [7:0] num;
wire [7:0] seg_1;
wire [7:0] seg_2;
uart_rx uart_inst
(
.i_clock(i_clk),
.i_rx_uart(i_uart_rx),
.o_rx_dv(),
.o_rx_byte(num)
);
bin_to_7seg inst
(
.in_byte(num),
.out_seg1(seg_1),
.out_seg2(seg_2)
);
assign o_segment1_a = ~seg_2[6];
assign o_segment1_b = ~seg_2[5];
assign o_segment1_c = ~seg_2[4];
assign o_segment1_d = ~seg_2[3];
assign o_segment1_e = ~seg_2[2];
assign o_segment1_f = ~seg_2[1];
assign o_segment1_g = ~seg_2[0];
assign o_segment2_a = ~seg_1[6];
assign o_segment2_b = ~seg_1[5];
assign o_segment2_c = ~seg_1[4];
assign o_segment2_d = ~seg_1[3];
assign o_segment2_e = ~seg_1[2];
assign o_segment2_f = ~seg_1[1];
assign o_segment2_g = ~seg_1[0];
endmodule | 0 |
5,020 | data/full_repos/permissive/112861986/src/examples/bin_to_7seg.v | 112,861,986 | bin_to_7seg.v | v | 51 | 29 | [] | [] | [] | [(1, 50)] | null | data/verilator_xmls/bae6394e-450a-496e-b16a-3992631097fb.xml | null | 5,402 | module | module bin_to_7seg
(
input [7:0] in_byte,
output reg [7:0] out_seg1,
output reg [7:0] out_seg2
);
always @(*)
begin
case(in_byte[3:0])
4'h0: out_seg1 = 8'h7E;
4'h1: out_seg1 = 8'h30;
4'h2: out_seg1 = 8'h6D;
4'h3: out_seg1 = 8'h79;
4'h4: out_seg1 = 8'h33;
4'h5: out_seg1 = 8'h5B;
4'h6: out_seg1 = 8'h5F;
4'h7: out_seg1 = 8'h70;
4'h8: out_seg1 = 8'h7F;
4'h9: out_seg1 = 8'h7B;
4'ha: out_seg1 = 8'h77;
4'hb: out_seg1 = 8'h1F;
4'hc: out_seg1 = 8'h4E;
4'hd: out_seg1 = 8'h3D;
4'he: out_seg1 = 8'h4F;
4'hf: out_seg1 = 8'h47;
default: out_seg1 = 8'h00;
endcase
case(in_byte[7:4])
4'h0: out_seg2 = 8'h7E;
4'h1: out_seg2 = 8'h30;
4'h2: out_seg2 = 8'h6D;
4'h3: out_seg2 = 8'h79;
4'h4: out_seg2 = 8'h33;
4'h5: out_seg2 = 8'h5B;
4'h6: out_seg2 = 8'h5F;
4'h7: out_seg2 = 8'h70;
4'h8: out_seg2 = 8'h7F;
4'h9: out_seg2 = 8'h7B;
4'ha: out_seg2 = 8'h77;
4'hb: out_seg2 = 8'h1F;
4'hc: out_seg2 = 8'h4E;
4'hd: out_seg2 = 8'h3D;
4'he: out_seg2 = 8'h4F;
4'hf: out_seg2 = 8'h47;
default: out_seg2 = 8'h00;
endcase
end
endmodule | module bin_to_7seg
(
input [7:0] in_byte,
output reg [7:0] out_seg1,
output reg [7:0] out_seg2
); |
always @(*)
begin
case(in_byte[3:0])
4'h0: out_seg1 = 8'h7E;
4'h1: out_seg1 = 8'h30;
4'h2: out_seg1 = 8'h6D;
4'h3: out_seg1 = 8'h79;
4'h4: out_seg1 = 8'h33;
4'h5: out_seg1 = 8'h5B;
4'h6: out_seg1 = 8'h5F;
4'h7: out_seg1 = 8'h70;
4'h8: out_seg1 = 8'h7F;
4'h9: out_seg1 = 8'h7B;
4'ha: out_seg1 = 8'h77;
4'hb: out_seg1 = 8'h1F;
4'hc: out_seg1 = 8'h4E;
4'hd: out_seg1 = 8'h3D;
4'he: out_seg1 = 8'h4F;
4'hf: out_seg1 = 8'h47;
default: out_seg1 = 8'h00;
endcase
case(in_byte[7:4])
4'h0: out_seg2 = 8'h7E;
4'h1: out_seg2 = 8'h30;
4'h2: out_seg2 = 8'h6D;
4'h3: out_seg2 = 8'h79;
4'h4: out_seg2 = 8'h33;
4'h5: out_seg2 = 8'h5B;
4'h6: out_seg2 = 8'h5F;
4'h7: out_seg2 = 8'h70;
4'h8: out_seg2 = 8'h7F;
4'h9: out_seg2 = 8'h7B;
4'ha: out_seg2 = 8'h77;
4'hb: out_seg2 = 8'h1F;
4'hc: out_seg2 = 8'h4E;
4'hd: out_seg2 = 8'h3D;
4'he: out_seg2 = 8'h4F;
4'hf: out_seg2 = 8'h47;
default: out_seg2 = 8'h00;
endcase
end
endmodule | 0 |
5,021 | data/full_repos/permissive/112861986/src/examples/uart_rx.v | 112,861,986 | uart_rx.v | v | 74 | 74 | [] | [] | [] | [(1, 73)] | null | data/verilator_xmls/61a560f8-769b-4d26-85d0-997092dcbde6.xml | null | 5,403 | module | module uart_rx
#(
parameter clks_per_bit = 217
)
(
input i_clock,
input i_rx_uart,
output o_rx_dv,
output [7:0]o_rx_byte
);
parameter clks_mid_bit = 108;
reg [7:0] r_cycle_count = 8'h00;
reg [2:0] r_index = 3'h0;
reg r_dv = 0;
reg [7:0] r_rx_byte = 8'h00;
reg [2:0] r_state = 0;
always @(posedge i_clock)
begin
case (r_state)
0:
begin
r_dv <= 0;
r_cycle_count <= 0;
r_index <= 0;
if (i_rx_uart == 0)
r_state <= 1;
end
1:
begin
r_cycle_count <= r_cycle_count + 1;
if (r_cycle_count == clks_mid_bit)
begin
if (i_rx_uart == 0)
begin
r_cycle_count <= 0;
r_state <= 2;
end
else
r_state = 0;
end
end
2:
begin
r_cycle_count <= r_cycle_count + 1;
if (r_cycle_count == clks_per_bit)
begin
r_cycle_count <= 0;
r_rx_byte[r_index] <= i_rx_uart;
if (r_index == 7)
r_state = 3;
r_index <= r_index + 1;
end
end
3:
begin
r_cycle_count <= r_cycle_count + 1;
if (r_cycle_count == clks_per_bit)
begin
r_cycle_count <= 0;
r_dv <= 1;
r_state <= 0;
end
end
endcase
end
assign o_rx_dv = r_dv;
assign o_rx_byte = r_rx_byte;
endmodule | module uart_rx
#(
parameter clks_per_bit = 217
)
(
input i_clock,
input i_rx_uart,
output o_rx_dv,
output [7:0]o_rx_byte
); |
parameter clks_mid_bit = 108;
reg [7:0] r_cycle_count = 8'h00;
reg [2:0] r_index = 3'h0;
reg r_dv = 0;
reg [7:0] r_rx_byte = 8'h00;
reg [2:0] r_state = 0;
always @(posedge i_clock)
begin
case (r_state)
0:
begin
r_dv <= 0;
r_cycle_count <= 0;
r_index <= 0;
if (i_rx_uart == 0)
r_state <= 1;
end
1:
begin
r_cycle_count <= r_cycle_count + 1;
if (r_cycle_count == clks_mid_bit)
begin
if (i_rx_uart == 0)
begin
r_cycle_count <= 0;
r_state <= 2;
end
else
r_state = 0;
end
end
2:
begin
r_cycle_count <= r_cycle_count + 1;
if (r_cycle_count == clks_per_bit)
begin
r_cycle_count <= 0;
r_rx_byte[r_index] <= i_rx_uart;
if (r_index == 7)
r_state = 3;
r_index <= r_index + 1;
end
end
3:
begin
r_cycle_count <= r_cycle_count + 1;
if (r_cycle_count == clks_per_bit)
begin
r_cycle_count <= 0;
r_dv <= 1;
r_state <= 0;
end
end
endcase
end
assign o_rx_dv = r_dv;
assign o_rx_byte = r_rx_byte;
endmodule | 0 |
5,022 | data/full_repos/permissive/112861986/src/testbench/3_tb.v | 112,861,986 | 3_tb.v | v | 100 | 71 | [] | [] | [] | null | line:75: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #(c_BIT_PERIOD);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #(c_BIT_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #(c_BIT_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;\n ^\n%Error: data/full_repos/permissive/112861986/src/testbench/3_tb.v:74: syntax error, unexpected \'@\'\n @(posedge r_Clock);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n#10000;\n^\n%Error: data/full_repos/permissive/112861986/src/testbench/3_tb.v:77: syntax error, unexpected \'@\'\n @(posedge r_Clock);\n ^\n%Error: data/full_repos/permissive/112861986/src/testbench/3_tb.v:84: syntax error, unexpected \'@\'\n @(posedge r_Clock);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n#10000;\n^\n%Error: data/full_repos/permissive/112861986/src/testbench/3_tb.v:87: syntax error, unexpected \'@\'\n @(posedge r_Clock);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n#10000;\n^\n%Error: data/full_repos/permissive/112861986/src/testbench/3_tb.v:95: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/112861986/src/testbench/3_tb.v:96: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0);\n ^~~~~~~~~\n%Error: Exiting due to 6 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 5,404 | module | module UART_RX_TB();
parameter c_CLOCK_PERIOD_NS = 40;
parameter c_CLKS_PER_BIT = 217;
parameter c_BIT_PERIOD = 8600;
reg r_Clock = 0;
reg r_RX_Serial = 1;
wire w_TX_Serial;
reg rdv = 0;
wire wdv;
wire [7:0] w_RX_Byte;
reg [7:0] w_TX_Byte = 8'h44;
assign wdv = rdv;
task UART_WRITE_BYTE;
input [7:0] i_Data;
integer ii;
begin
r_RX_Serial <= 1'b0;
#(c_BIT_PERIOD);
#1000;
for (ii=0; ii<8; ii=ii+1)
begin
r_RX_Serial <= i_Data[ii];
#(c_BIT_PERIOD);
end
r_RX_Serial <= 1'b1;
#(c_BIT_PERIOD);
end
endtask
uart_rx #(.clks_per_bit(c_CLKS_PER_BIT)) UART_RX_INST
(.i_clock(r_Clock),
.i_rx_uart(r_RX_Serial),
.o_rx_dv(wdv),
.o_rx_byte(w_RX_Byte)
);
uart_tx #(.clks_per_bit(c_CLKS_PER_BIT)) UART_TX_INST
(.i_clock(r_Clock),
.o_tx_uart(w_TX_Serial),
.i_dv(wdv),
.i_tx_byte(w_TX_Byte)
);
always
#(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;
initial
begin
@(posedge r_Clock);
UART_WRITE_BYTE(8'h14);
#10000;
@(posedge r_Clock);
if (w_RX_Byte == 8'h14)
$display("Test Passed - Correct Byte Received");
else
$display("Test Failed - Incorrect Byte Received");
@(posedge r_Clock);
#10000;
$display(w_TX_Byte);
@(posedge r_Clock);
#10000;
$finish();
end
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule | module UART_RX_TB(); |
parameter c_CLOCK_PERIOD_NS = 40;
parameter c_CLKS_PER_BIT = 217;
parameter c_BIT_PERIOD = 8600;
reg r_Clock = 0;
reg r_RX_Serial = 1;
wire w_TX_Serial;
reg rdv = 0;
wire wdv;
wire [7:0] w_RX_Byte;
reg [7:0] w_TX_Byte = 8'h44;
assign wdv = rdv;
task UART_WRITE_BYTE;
input [7:0] i_Data;
integer ii;
begin
r_RX_Serial <= 1'b0;
#(c_BIT_PERIOD);
#1000;
for (ii=0; ii<8; ii=ii+1)
begin
r_RX_Serial <= i_Data[ii];
#(c_BIT_PERIOD);
end
r_RX_Serial <= 1'b1;
#(c_BIT_PERIOD);
end
endtask
uart_rx #(.clks_per_bit(c_CLKS_PER_BIT)) UART_RX_INST
(.i_clock(r_Clock),
.i_rx_uart(r_RX_Serial),
.o_rx_dv(wdv),
.o_rx_byte(w_RX_Byte)
);
uart_tx #(.clks_per_bit(c_CLKS_PER_BIT)) UART_TX_INST
(.i_clock(r_Clock),
.o_tx_uart(w_TX_Serial),
.i_dv(wdv),
.i_tx_byte(w_TX_Byte)
);
always
#(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;
initial
begin
@(posedge r_Clock);
UART_WRITE_BYTE(8'h14);
#10000;
@(posedge r_Clock);
if (w_RX_Byte == 8'h14)
$display("Test Passed - Correct Byte Received");
else
$display("Test Failed - Incorrect Byte Received");
@(posedge r_Clock);
#10000;
$display(w_TX_Byte);
@(posedge r_Clock);
#10000;
$finish();
end
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule | 0 |
5,023 | data/full_repos/permissive/112978342/max10_adc_firmware/demux1.v | 112,978,342 | demux1.v | v | 30 | 75 | [] | [] | [] | [(2, 29)] | null | data/verilator_xmls/e039bfe7-8578-4bf4-ad72-04e8b9fc45c6.xml | null | 5,406 | module | module demux1to2( Data_in, sel, Data_out_0, Data_out_1 );
input Data_in;
input sel;
output Data_out_0;
output Data_out_1;
reg Data_out_0;
reg Data_out_1;
always @(Data_in or sel)
begin
case (sel)
1'b0 : begin
Data_out_0 = Data_in;
Data_out_1 = 0;
end
1'b1 : begin
Data_out_0 = 0;
Data_out_1 = Data_in;
end
endcase
end
endmodule | module demux1to2( Data_in, sel, Data_out_0, Data_out_1 ); |
input Data_in;
input sel;
output Data_out_0;
output Data_out_1;
reg Data_out_0;
reg Data_out_1;
always @(Data_in or sel)
begin
case (sel)
1'b0 : begin
Data_out_0 = Data_in;
Data_out_1 = 0;
end
1'b1 : begin
Data_out_0 = 0;
Data_out_1 = Data_in;
end
endcase
end
endmodule | 93 |
5,024 | data/full_repos/permissive/112978342/max10_adc_firmware/hvsync_generator.v | 112,978,342 | hvsync_generator.v | v | 43 | 100 | [] | [] | [] | [(1, 42)] | null | data/verilator_xmls/127a5aa1-30f5-4fc3-be0f-46ac9090dad1.xml | null | 5,409 | module | module hvsync_generator(clk, vga_h_sync, vga_v_sync, inDisplayArea, CounterX, CounterY);
input clk;
output vga_h_sync, vga_v_sync;
output inDisplayArea;
output [9:0] CounterX;
output [8:0] CounterY;
reg [9:0] CounterX;
reg CounterXflip;
reg [8:0] CounterY;
wire CounterXmaxed = (CounterX==767);
always @(posedge clk)
if(CounterXmaxed)
CounterX <= 0;
else begin
if (CounterXflip) CounterX <= CounterX + 1;
CounterXflip <= ~CounterXflip;
end
always @(posedge clk)
if(CounterXmaxed) CounterY <= CounterY + 1;
reg vga_HS, vga_VS;
always @(posedge clk)
begin
vga_HS <= (CounterX[9:4]==45);
vga_VS <= (CounterY==498);
end
reg inDisplayArea;
always @(posedge clk)
if(inDisplayArea==0)
inDisplayArea <= (CounterXmaxed) && (CounterY<480);
else
inDisplayArea <= !(CounterX==639);
assign vga_h_sync = ~vga_HS;
assign vga_v_sync = ~vga_VS;
endmodule | module hvsync_generator(clk, vga_h_sync, vga_v_sync, inDisplayArea, CounterX, CounterY); |
input clk;
output vga_h_sync, vga_v_sync;
output inDisplayArea;
output [9:0] CounterX;
output [8:0] CounterY;
reg [9:0] CounterX;
reg CounterXflip;
reg [8:0] CounterY;
wire CounterXmaxed = (CounterX==767);
always @(posedge clk)
if(CounterXmaxed)
CounterX <= 0;
else begin
if (CounterXflip) CounterX <= CounterX + 1;
CounterXflip <= ~CounterXflip;
end
always @(posedge clk)
if(CounterXmaxed) CounterY <= CounterY + 1;
reg vga_HS, vga_VS;
always @(posedge clk)
begin
vga_HS <= (CounterX[9:4]==45);
vga_VS <= (CounterY==498);
end
reg inDisplayArea;
always @(posedge clk)
if(inDisplayArea==0)
inDisplayArea <= (CounterXmaxed) && (CounterY<480);
else
inDisplayArea <= !(CounterX==639);
assign vga_h_sync = ~vga_HS;
assign vga_v_sync = ~vga_VS;
endmodule | 93 |
5,025 | data/full_repos/permissive/112978342/max10_adc_firmware/mball.v | 112,978,342 | mball.v | v | 70 | 158 | [] | [] | [] | null | line:7: before: ";" | null | 1: b"%Error: data/full_repos/permissive/112978342/max10_adc_firmware/mball.v:7: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'startX'\n : ... In instance mball\nparameter [9:0] startX;\n ^~~~~~\n%Error: data/full_repos/permissive/112978342/max10_adc_firmware/mball.v:8: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'startY'\n : ... In instance mball\nparameter [8:0] startY;\n ^~~~~~\n%Error: data/full_repos/permissive/112978342/max10_adc_firmware/mball.v:14: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'pballmass'\n : ... In instance mball\nparameter [8:0] pballmass;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/112978342/max10_adc_firmware/mball.v:15: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'pballspeed'\n : ... In instance mball\nparameter [8:0] pballspeed;\n ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 5,415 | module | module mball(clk, BouncingObject, inotherball, CounterX, CounterY, ballX, ballY, inball, ballspeed, ballmass);
input clk;
input BouncingObject;
input inotherball;
input [9:0] CounterX;
input [8:0] CounterY;
parameter [9:0] startX;
parameter [8:0] startY;
parameter ballsize = 5;
parameter twoballsize = 2*ballsize;
output reg [9:0] ballX;
output reg [8:0] ballY;
output reg [8:0] ballspeed;
parameter [8:0] pballmass;
parameter [8:0] pballspeed;
output [8:0] ballmass = pballmass;
reg ball_inX, ball_inY;
always @(posedge clk)
if(ball_inX==0) ball_inX <= (CounterX==ballX) & ball_inY; else ball_inX <= !(CounterX==ballX+twoballsize);
always @(posedge clk)
if(ball_inY==0) ball_inY <= (CounterY==ballY); else ball_inY <= !(CounterY==ballY+twoballsize);
output inball = ball_inX & ball_inY;
initial begin
ballX<=startX;
ballY<=startY;
ball_dirX <= startX%2;
ball_dirY <= startY%2;
ballspeed<=pballspeed;
end
reg ResetCollision;
always @(posedge clk) ResetCollision <= (CounterY==500) & (CounterX==0);
reg CollisionX1, CollisionX2, CollisionY1, CollisionY2;
always @(posedge clk) if(ResetCollision) CollisionX1<=0; else if(BouncingObject & (CounterX==ballX ) & (CounterY==ballY+ballsize)) CollisionX1<=1;
always @(posedge clk) if(ResetCollision) CollisionX2<=0; else if(BouncingObject & (CounterX==ballX+twoballsize) & (CounterY==ballY+ballsize)) CollisionX2<=1;
always @(posedge clk) if(ResetCollision) CollisionY1<=0; else if(BouncingObject & (CounterX==ballX+ballsize) & (CounterY==ballY )) CollisionY1<=1;
always @(posedge clk) if(ResetCollision) CollisionY2<=0; else if(BouncingObject & (CounterX==ballX+ballsize) & (CounterY==ballY+twoballsize)) CollisionY2<=1;
wire UpdateBallPosition = ResetCollision;
reg ballcollision;
always @(posedge clk) if(ResetCollision) ballcollision<=0; else if (inotherball) ballcollision<=1;
reg ball_dirX, ball_dirY;
always @(posedge clk) begin
if(UpdateBallPosition) begin
if(~(CollisionX1 & CollisionX2))
begin
if (ballcollision) begin
ball_dirX = !ball_dirX;
ballspeed = 1+((ballspeed+1)%2);
end
ballX = ballX + (ball_dirX ? -ballspeed : ballspeed);
if (CollisionX2) ball_dirX <= 1; else if (CollisionX1) ball_dirX <= 0;
end
if(~(CollisionY1 & CollisionY2))
begin
ballY <= ballY + (ball_dirY ? -1 : 1);
if (CollisionY2) ball_dirY <= 1; else if (CollisionY1) ball_dirY <= 0;
end
end
end
endmodule | module mball(clk, BouncingObject, inotherball, CounterX, CounterY, ballX, ballY, inball, ballspeed, ballmass); |
input clk;
input BouncingObject;
input inotherball;
input [9:0] CounterX;
input [8:0] CounterY;
parameter [9:0] startX;
parameter [8:0] startY;
parameter ballsize = 5;
parameter twoballsize = 2*ballsize;
output reg [9:0] ballX;
output reg [8:0] ballY;
output reg [8:0] ballspeed;
parameter [8:0] pballmass;
parameter [8:0] pballspeed;
output [8:0] ballmass = pballmass;
reg ball_inX, ball_inY;
always @(posedge clk)
if(ball_inX==0) ball_inX <= (CounterX==ballX) & ball_inY; else ball_inX <= !(CounterX==ballX+twoballsize);
always @(posedge clk)
if(ball_inY==0) ball_inY <= (CounterY==ballY); else ball_inY <= !(CounterY==ballY+twoballsize);
output inball = ball_inX & ball_inY;
initial begin
ballX<=startX;
ballY<=startY;
ball_dirX <= startX%2;
ball_dirY <= startY%2;
ballspeed<=pballspeed;
end
reg ResetCollision;
always @(posedge clk) ResetCollision <= (CounterY==500) & (CounterX==0);
reg CollisionX1, CollisionX2, CollisionY1, CollisionY2;
always @(posedge clk) if(ResetCollision) CollisionX1<=0; else if(BouncingObject & (CounterX==ballX ) & (CounterY==ballY+ballsize)) CollisionX1<=1;
always @(posedge clk) if(ResetCollision) CollisionX2<=0; else if(BouncingObject & (CounterX==ballX+twoballsize) & (CounterY==ballY+ballsize)) CollisionX2<=1;
always @(posedge clk) if(ResetCollision) CollisionY1<=0; else if(BouncingObject & (CounterX==ballX+ballsize) & (CounterY==ballY )) CollisionY1<=1;
always @(posedge clk) if(ResetCollision) CollisionY2<=0; else if(BouncingObject & (CounterX==ballX+ballsize) & (CounterY==ballY+twoballsize)) CollisionY2<=1;
wire UpdateBallPosition = ResetCollision;
reg ballcollision;
always @(posedge clk) if(ResetCollision) ballcollision<=0; else if (inotherball) ballcollision<=1;
reg ball_dirX, ball_dirY;
always @(posedge clk) begin
if(UpdateBallPosition) begin
if(~(CollisionX1 & CollisionX2))
begin
if (ballcollision) begin
ball_dirX = !ball_dirX;
ballspeed = 1+((ballspeed+1)%2);
end
ballX = ballX + (ball_dirX ? -ballspeed : ballspeed);
if (CollisionX2) ball_dirX <= 1; else if (CollisionX1) ball_dirX <= 0;
end
if(~(CollisionY1 & CollisionY2))
begin
ballY <= ballY + (ball_dirY ? -1 : 1);
if (CollisionY2) ball_dirY <= 1; else if (CollisionY1) ball_dirY <= 0;
end
end
end
endmodule | 93 |
5,026 | data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v | 112,978,342 | oscillo.v | v | 409 | 261 | [] | [] | [] | null | line:208: before: "]" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:157: Operator GT expects 11 bits on the RHS, but RHS\'s SEL generates 10 bits.\n : ... In instance oscillo\n if (Threshold3[i]>triggertot[ram_width-1:0]) begin \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:146: Logical Operator IF expects 1 bit on the If, but If\'s ARRAYSEL generates 11 bits.\n : ... In instance oscillo\n if (Threshold3[i]) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:144: Logical Operator IF expects 1 bit on the If, but If\'s SEL generates 10 bits.\n : ... In instance oscillo\n if (triggertot[ram_width-1:0]) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:183: Operator GT expects 11 bits on the RHS, but RHS\'s SEL generates 10 bits.\n : ... In instance oscillo\n if (Threshold3[i]>triggertot[ram_width-1:0]) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:172: Logical Operator IF expects 1 bit on the If, but If\'s ARRAYSEL generates 11 bits.\n : ... In instance oscillo\n if (Threshold3[i]) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:170: Logical Operator IF expects 1 bit on the If, but If\'s SEL generates 10 bits.\n : ... In instance oscillo\n if (triggertot[ram_width-1:0]) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:203: Bit extraction of var[12:0] requires 4 bit index, not 5 bits.\n : ... In instance oscillo\n ext_trig_in_delayed <= ext_trig_in_delay_bits[ext_trig_delay];\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:274: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'Tcounter_test_countdown\' generates 8 bits.\n : ... In instance oscillo\n if (Tcounter_test_countdown) Tcounter_test_countdown <= Tcounter_test_countdown-1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:280: Logical Operator IF expects 1 bit on the If, but If\'s ARRAYSEL generates 4 bits.\n : ... In instance oscillo\n else if (Tcounter[i]) Tcounter[i]<=Tcounter[i]-1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:309: Bit extraction of var[23:0] requires 5 bit index, not 8 bits.\n : ... In instance oscillo\nassign downsamplego = downsamplecounter[downsample2] || downsample2==0; \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:359: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'data_flash1_reg\' generates 8 bits.\n : ... In instance oscillo\n highres1=highres1+data_flash1_reg;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:360: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'data_flash2_reg\' generates 8 bits.\n : ... In instance oscillo\n highres2=highres2+data_flash2_reg;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:361: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'data_flash3_reg\' generates 8 bits.\n : ... In instance oscillo\n highres3=highres3+data_flash3_reg;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:362: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'data_flash4_reg\' generates 8 bits.\n : ... In instance oscillo\n highres4=highres4+data_flash4_reg;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:366: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout1=highres1>>maxhighres;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:367: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout2=highres2>>maxhighres;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:368: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout3=highres3>>maxhighres;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:369: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout4=highres4>>maxhighres;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:372: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout1=highres1>>downsample2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:373: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout2=highres2>>downsample2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:374: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout3=highres3>>downsample2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo.v:375: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout4=highres4>>downsample2;\n ^\n%Error: Exiting due to 22 warning(s)\n' | 5,419 | module | module oscillo(clk, startTrigger, clk_flash, data_flash1, data_flash2, data_flash3, data_flash4, pwr1, pwr2, shdn_out, spen_out, trig_in, trig_out, rden, rdaddress,
data_ready, wraddress_triggerpoint, imthelast, imthefirst,rollingtrigger,trigDebug,triggerpoint,downsample,
trigthresh,trigchannels,triggertype,triggertot,format_sdin_out,div_sclk_out,outsel_cs_out,clk_spi,SPIsend,SPIsenddata,
wraddress,Acquiring,SPIstate,clk_flash2,trigthreshtwo,dout1,dout2,dout3,dout4,highres,ext_trig_in,use_ext_trig, nsmp, trigout, spareright, spareleft,
delaycounter,ext_trig_delay, noselftrig, nselftrigcoincidentreq, selftrigtempholdtime, allowsamechancoin,
trigratecounter,trigratecountreset);
input clk,clk_spi;
input startTrigger;
input [1:0] trig_in;
output reg [1:0] trig_out;
output reg pwr1=0;
output reg pwr2=0;
output reg shdn_out=0;
output reg spen_out=0;
output reg format_sdin_out=0;
output reg div_sclk_out=0;
output reg outsel_cs_out=1;
input clk_flash, clk_flash2;
input [7:0] data_flash1, data_flash2, data_flash3, data_flash4;
output reg [7:0] dout1, dout2, dout3, dout4;
parameter ram_width=10;
output reg[ram_width-1:0] wraddress_triggerpoint;
reg[ram_width-1:0] wraddress_triggerpoint2;
input wire [ram_width-1:0] rdaddress;
input wire rden;
output reg data_ready=0;
input wire imthelast, imthefirst;
input wire rollingtrigger;
output reg trigDebug=1;
input [7:0] trigthresh, trigthreshtwo;
input [3:0] trigchannels;
input [ram_width-1:0] triggerpoint;
input [7:0] downsample;
reg [7:0] downsample2;
input [3:0] triggertype;
reg [3:0] triggertype2;
input [ram_width:0] triggertot;
input highres;
parameter maxhighres=5;
reg [7+maxhighres:0] highres1, highres2, highres3, highres4;
input ext_trig_in, use_ext_trig;
input [ram_width-1:0] nsmp;
reg [ram_width-1:0] nsmp2;
input [4:0] ext_trig_delay;
input noselftrig;
input [1:0] nselftrigcoincidentreq;
input [7:0] selftrigtempholdtime;
input allowsamechancoin;
output reg [3:0] trigout;
output wire spareright;
input wire spareleft;
reg [31:0] SPIcounter=0;
input [15:0] SPIsenddata;
input SPIsend;
reg [3:0] SPIsendcounter;
localparam SPI0=0, SPI1=1, SPI2=2, SPI3=3;
output reg[3:0] SPIstate=SPI0;
always @(posedge clk_spi) begin
if (!spen_out) begin
SPIcounter=SPIcounter+1;
case (SPIstate)
SPI0: begin
if (SPIsend) begin
SPIcounter=0;
outsel_cs_out=1;
div_sclk_out=1;
SPIsendcounter=4'b1111;
SPIstate=SPI1;
end
end
SPI1: begin
if (SPIcounter[2]) begin
div_sclk_out=0;
outsel_cs_out=0;
format_sdin_out=SPIsenddata[SPIsendcounter];
SPIsendcounter=SPIsendcounter-4'b001;
SPIstate=SPI2;
end
end
SPI2: begin
if (!SPIcounter[2]) begin
div_sclk_out=1;
if (SPIsendcounter==4'b1111) SPIstate=SPI3;
else SPIstate=SPI1;
end
end
SPI3: begin
if (SPIcounter[2]) begin
outsel_cs_out=1;
div_sclk_out=0;
SPIstate=SPI0;
end
end
endcase
end
end
reg Threshold1[3:0], Threshold2[3:0];
reg [ram_width:0] Threshold3[3:0];
reg selftrigtemp[3:0];
reg Trigger;
reg AcquiringAndTriggered=0;
reg HaveFullData=0;
integer i;
initial begin
Threshold3[0]=0;
Threshold3[1]=0;
Threshold3[2]=0;
Threshold3[3]=0;
end
reg [ram_width-1:0] samplecount=0;
output reg [ram_width-1:0] wraddress;
output reg Acquiring;
reg PreOrPostAcquiring;
reg [7:0] data_flash1_reg; always @(posedge clk_flash) data_flash1_reg <= data_flash1;
reg [7:0] data_flash2_reg; always @(posedge clk_flash) data_flash2_reg <= data_flash2;
reg [7:0] data_flash3_reg_temp; always @(posedge clk_flash2) data_flash3_reg_temp <= data_flash3;
reg [7:0] data_flash4_reg_temp; always @(posedge clk_flash2) data_flash4_reg_temp <= data_flash4;
reg [7:0] data_flash3_reg; always @(posedge clk_flash) data_flash3_reg <= data_flash3_reg_temp;
reg [7:0] data_flash4_reg; always @(posedge clk_flash) data_flash4_reg <= data_flash4_reg_temp;
always @(posedge clk_flash) begin
i=0;
while (i<4) begin
if (i==0) Threshold1[i] <= (data_flash1_reg>=trigthresh && data_flash1_reg<=trigthreshtwo);
if (i==1) Threshold1[i] <= (data_flash2_reg>=trigthresh && data_flash2_reg<=trigthreshtwo);
if (i==2) Threshold1[i] <= (data_flash3_reg>=trigthresh && data_flash3_reg<=trigthreshtwo);
if (i==3) Threshold1[i] <= (data_flash4_reg>=trigthresh && data_flash4_reg<=trigthreshtwo);
Threshold2[i] <= Threshold1[i];
if (triggertype2[0]) begin
if (triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 0;
if (Threshold3[i]) begin
if (triggertot[ram_width]) begin
if (downsamplego) begin
if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
end
else begin
if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
if (Threshold3[i]>triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 1;
Threshold3[i] <= 0;
end
end
else if (Threshold1[i] & ~Threshold2[i]) begin
Threshold3[i] <= 1;
end
end
else selftrigtemp[i] <= (Threshold1[i] & ~Threshold2[i]);
end
else begin
if (triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 0;
if (Threshold3[i]) begin
if (triggertot[ram_width]) begin
if (downsamplego) begin
if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
end
else begin
if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
if (Threshold3[i]>triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 1;
Threshold3[i] <= 0;
end
end
else if (~Threshold1[i] & Threshold2[i]) begin
Threshold3[i] <= 1;
end
end
else selftrigtemp[i] <= (~Threshold1[i] & Threshold2[i]);
end
i=i+1;
end
end
reg[12:0] ext_trig_in_delay_bits=0;
reg ext_trig_in_delayed;
always @(posedge clk_flash) begin
ext_trig_in_delayed <= ext_trig_in_delay_bits[ext_trig_delay];
ext_trig_in_delay_bits <= {ext_trig_in_delay_bits[12-1:0], ext_trig_in};
end
reg[31:0] thecounter;
reg[1:0] nselftrigstemp[4];
reg[7:0] selftrigtemphold[4];
always @(posedge clk_flash) begin
if (Trigger) thecounter<=0; else thecounter<=thecounter+1;
i=0;
while (i<4) begin
if (selftrigtemp[i]) selftrigtemphold[i]<=selftrigtempholdtime;
else if (selftrigtemphold[i]>0 && downsamplego) selftrigtemphold[i]<=selftrigtemphold[i]-1;
if (allowsamechancoin) nselftrigstemp[i] <= (trigchannels[(i)%4]&&selftrigtemphold[(i)%4]>0) + (trigchannels[(i+1)%4]&&selftrigtemphold[(i+1)%4]>0) + (trigchannels[(i+2)%4]&&selftrigtemphold[(i+2)%4]>0) + (trigchannels[(i+3)%4]&&selftrigtemphold[(i+3)%4]>0);
else nselftrigstemp[i] <= (trigchannels[(i+1)%4]&&selftrigtemphold[(i+1)%4]>0) + (trigchannels[(i+2)%4]&&selftrigtemphold[(i+2)%4]>0) + (trigchannels[(i+3)%4]&&selftrigtemphold[(i+3)%4]>0);
i=i+1;
end
end
wire selfedgetrig;
assign selfedgetrig = (trigchannels[0]&&selftrigtemp[0]&&nselftrigstemp[0]>=nselftrigcoincidentreq)||
(trigchannels[1]&&selftrigtemp[1]&&nselftrigstemp[1]>=nselftrigcoincidentreq)||
(trigchannels[2]&&selftrigtemp[2]&&nselftrigstemp[2]>=nselftrigcoincidentreq)||
(trigchannels[3]&&selftrigtemp[3]&&nselftrigstemp[3]>=nselftrigcoincidentreq);
wire selftrig;
assign selftrig = selfedgetrig || (rollingtrigger&thecounter>=25000000) || (use_ext_trig&ext_trig_in_delayed);
output reg[31:0] trigratecounter=0;
input trigratecountreset;
reg [7:0] selfedgetrigdeadtime=0;
always @(posedge clk_flash) begin
if (selfedgetrig && selfedgetrigdeadtime==0) begin
trigratecounter = trigratecounter+1;
selfedgetrigdeadtime<=selftrigtempholdtime;
end
if (selfedgetrigdeadtime>0 && downsamplego) selfedgetrigdeadtime<=selfedgetrigdeadtime-1;
if (trigratecountreset) trigratecounter=0;
end
always @(posedge clk_flash)
if (noselftrig) Trigger = trig_in[1];
else if (imthefirst & imthelast) Trigger = selftrig;
else if (imthefirst) Trigger = selftrig||trig_in[1];
else if (imthelast) Trigger = selftrig||trig_in[0];
else Trigger = selftrig||trig_in[0]||trig_in[1];
always @(posedge clk_flash)
if (noselftrig) trig_out[0] = 0;
else if (imthefirst) trig_out[0] = selftrig;
else trig_out[0] = trig_in[0]||selftrig;
always @(posedge clk_flash)
if (noselftrig) trig_out[1] = trig_in[1];
else if (imthelast) trig_out[1] = selftrig;
else trig_out[1] = trig_in[1]||selftrig;
reg Ttrig[4];
reg[3:0] Tcounter[4];
reg[7:0] Tcounter_test_countdown;
output reg[7:0] delaycounter;
reg[7:0] spareleftcounter;
always @(posedge clk_flash) begin
if (spareleft) begin
if (spareleftcounter<205) begin
spareleftcounter<=spareleftcounter+1;
Ttrig[0]<=0; Ttrig[1]<=0; Ttrig[2]<=0; Ttrig[3]<=0;
Tcounter[0]<=0; Tcounter[1]<=0; Tcounter[2]<=0; Tcounter[3]<=0;
end
else begin
Ttrig[0] <= (Tcounter_test_countdown!=0);
if (Tcounter_test_countdown) Tcounter_test_countdown <= Tcounter_test_countdown-1;
end
end
else begin
i=0; while (i<4) begin
if (selftrigtemp[i]) Tcounter[i]<=4;
else if (Tcounter[i]) Tcounter[i]<=Tcounter[i]-1;
Ttrig[i] <= (Tcounter[i]>0);
i=i+1;
end
Tcounter_test_countdown <= 219;
spareleftcounter<=0;
end
end
reg[1:0] Pulsecounter=0;
always @(posedge clk_flash) begin
trigout[0]<=(Ttrig[Pulsecounter]);
Pulsecounter<=Pulsecounter+1;
end
assign spareright = spareleft;
reg startAcquisition;
always @(posedge clk) begin
if(~startAcquisition) startAcquisition <= startTrigger;
else if(AcquiringAndTriggered2) startAcquisition <= 0;
end
reg startAcquisition1; always @(posedge clk_flash) startAcquisition1 <= startAcquisition;
reg startAcquisition2; always @(posedge clk_flash) startAcquisition2 <= startAcquisition1;
localparam INIT=0, PREACQ=1, WAITING=2, POSTACQ=3;
reg[2:0] state=INIT;
reg [23:0] downsamplecounter;
reg [maxhighres:0] highrescounter;
wire downsamplego;
assign downsamplego = downsamplecounter[downsample2] || downsample2==0;
always @(posedge clk_flash) begin
nsmp2<=nsmp;
triggertype2<=triggertype;
downsample2<=downsample;
case (state)
INIT: begin
if (startAcquisition2) begin
samplecount <= 0;
Acquiring <= 1;
HaveFullData <= 0;
PreOrPostAcquiring <= 1;
downsamplecounter=1;
highrescounter=0;
highres1=0;
highres2=0;
highres3=0;
highres4=0;
state=PREACQ;
end
end
PREACQ: begin
if( (samplecount==triggerpoint) ) begin
PreOrPostAcquiring <= 0;
state=WAITING;
end
end
WAITING: begin
if(Trigger) begin
AcquiringAndTriggered <= 1;
PreOrPostAcquiring <= 1;
wraddress_triggerpoint2 <= wraddress;
state=POSTACQ;
end
end
POSTACQ: begin
if(samplecount==nsmp2) begin
Acquiring <= 0;
AcquiringAndTriggered <= 0;
HaveFullData <= 1;
PreOrPostAcquiring <= 0;
state=INIT;
end
end
endcase
downsamplecounter=downsamplecounter+1;
if (highres) begin
highrescounter=highrescounter+1;
highres1=highres1+data_flash1_reg;
highres2=highres2+data_flash2_reg;
highres3=highres3+data_flash3_reg;
highres4=highres4+data_flash4_reg;
if (downsamplego || highrescounter[maxhighres]) begin
highrescounter=0;
if (downsample2>maxhighres) begin
dout1=highres1>>maxhighres;
dout2=highres2>>maxhighres;
dout3=highres3>>maxhighres;
dout4=highres4>>maxhighres;
end
else begin
dout1=highres1>>downsample2;
dout2=highres2>>downsample2;
dout3=highres3>>downsample2;
dout4=highres4>>downsample2;
end
highres1=0;
highres2=0;
highres3=0;
highres4=0;
end
end
else begin
dout1=data_flash1_reg;
dout2=data_flash2_reg;
dout3=data_flash3_reg;
dout4=data_flash4_reg;
end
if (downsamplego) begin
downsamplecounter=1;
if(Acquiring) wraddress <= wraddress + 1;
if(PreOrPostAcquiring) samplecount <= samplecount + 1;
end
end
reg AcquiringAndTriggered1; always @(posedge clk) AcquiringAndTriggered1 <= AcquiringAndTriggered;
reg AcquiringAndTriggered2; always @(posedge clk) AcquiringAndTriggered2 <= AcquiringAndTriggered1;
reg HaveFullData1; always @(posedge clk) HaveFullData1 <= HaveFullData;
reg HaveFullData2; always @(posedge clk) HaveFullData2 <= HaveFullData1;
always @(posedge clk) begin
wraddress_triggerpoint=wraddress_triggerpoint2;
if (startAcquisition) data_ready=0;
else if (HaveFullData2) data_ready=1;
end
endmodule | module oscillo(clk, startTrigger, clk_flash, data_flash1, data_flash2, data_flash3, data_flash4, pwr1, pwr2, shdn_out, spen_out, trig_in, trig_out, rden, rdaddress,
data_ready, wraddress_triggerpoint, imthelast, imthefirst,rollingtrigger,trigDebug,triggerpoint,downsample,
trigthresh,trigchannels,triggertype,triggertot,format_sdin_out,div_sclk_out,outsel_cs_out,clk_spi,SPIsend,SPIsenddata,
wraddress,Acquiring,SPIstate,clk_flash2,trigthreshtwo,dout1,dout2,dout3,dout4,highres,ext_trig_in,use_ext_trig, nsmp, trigout, spareright, spareleft,
delaycounter,ext_trig_delay, noselftrig, nselftrigcoincidentreq, selftrigtempholdtime, allowsamechancoin,
trigratecounter,trigratecountreset); |
input clk,clk_spi;
input startTrigger;
input [1:0] trig_in;
output reg [1:0] trig_out;
output reg pwr1=0;
output reg pwr2=0;
output reg shdn_out=0;
output reg spen_out=0;
output reg format_sdin_out=0;
output reg div_sclk_out=0;
output reg outsel_cs_out=1;
input clk_flash, clk_flash2;
input [7:0] data_flash1, data_flash2, data_flash3, data_flash4;
output reg [7:0] dout1, dout2, dout3, dout4;
parameter ram_width=10;
output reg[ram_width-1:0] wraddress_triggerpoint;
reg[ram_width-1:0] wraddress_triggerpoint2;
input wire [ram_width-1:0] rdaddress;
input wire rden;
output reg data_ready=0;
input wire imthelast, imthefirst;
input wire rollingtrigger;
output reg trigDebug=1;
input [7:0] trigthresh, trigthreshtwo;
input [3:0] trigchannels;
input [ram_width-1:0] triggerpoint;
input [7:0] downsample;
reg [7:0] downsample2;
input [3:0] triggertype;
reg [3:0] triggertype2;
input [ram_width:0] triggertot;
input highres;
parameter maxhighres=5;
reg [7+maxhighres:0] highres1, highres2, highres3, highres4;
input ext_trig_in, use_ext_trig;
input [ram_width-1:0] nsmp;
reg [ram_width-1:0] nsmp2;
input [4:0] ext_trig_delay;
input noselftrig;
input [1:0] nselftrigcoincidentreq;
input [7:0] selftrigtempholdtime;
input allowsamechancoin;
output reg [3:0] trigout;
output wire spareright;
input wire spareleft;
reg [31:0] SPIcounter=0;
input [15:0] SPIsenddata;
input SPIsend;
reg [3:0] SPIsendcounter;
localparam SPI0=0, SPI1=1, SPI2=2, SPI3=3;
output reg[3:0] SPIstate=SPI0;
always @(posedge clk_spi) begin
if (!spen_out) begin
SPIcounter=SPIcounter+1;
case (SPIstate)
SPI0: begin
if (SPIsend) begin
SPIcounter=0;
outsel_cs_out=1;
div_sclk_out=1;
SPIsendcounter=4'b1111;
SPIstate=SPI1;
end
end
SPI1: begin
if (SPIcounter[2]) begin
div_sclk_out=0;
outsel_cs_out=0;
format_sdin_out=SPIsenddata[SPIsendcounter];
SPIsendcounter=SPIsendcounter-4'b001;
SPIstate=SPI2;
end
end
SPI2: begin
if (!SPIcounter[2]) begin
div_sclk_out=1;
if (SPIsendcounter==4'b1111) SPIstate=SPI3;
else SPIstate=SPI1;
end
end
SPI3: begin
if (SPIcounter[2]) begin
outsel_cs_out=1;
div_sclk_out=0;
SPIstate=SPI0;
end
end
endcase
end
end
reg Threshold1[3:0], Threshold2[3:0];
reg [ram_width:0] Threshold3[3:0];
reg selftrigtemp[3:0];
reg Trigger;
reg AcquiringAndTriggered=0;
reg HaveFullData=0;
integer i;
initial begin
Threshold3[0]=0;
Threshold3[1]=0;
Threshold3[2]=0;
Threshold3[3]=0;
end
reg [ram_width-1:0] samplecount=0;
output reg [ram_width-1:0] wraddress;
output reg Acquiring;
reg PreOrPostAcquiring;
reg [7:0] data_flash1_reg; always @(posedge clk_flash) data_flash1_reg <= data_flash1;
reg [7:0] data_flash2_reg; always @(posedge clk_flash) data_flash2_reg <= data_flash2;
reg [7:0] data_flash3_reg_temp; always @(posedge clk_flash2) data_flash3_reg_temp <= data_flash3;
reg [7:0] data_flash4_reg_temp; always @(posedge clk_flash2) data_flash4_reg_temp <= data_flash4;
reg [7:0] data_flash3_reg; always @(posedge clk_flash) data_flash3_reg <= data_flash3_reg_temp;
reg [7:0] data_flash4_reg; always @(posedge clk_flash) data_flash4_reg <= data_flash4_reg_temp;
always @(posedge clk_flash) begin
i=0;
while (i<4) begin
if (i==0) Threshold1[i] <= (data_flash1_reg>=trigthresh && data_flash1_reg<=trigthreshtwo);
if (i==1) Threshold1[i] <= (data_flash2_reg>=trigthresh && data_flash2_reg<=trigthreshtwo);
if (i==2) Threshold1[i] <= (data_flash3_reg>=trigthresh && data_flash3_reg<=trigthreshtwo);
if (i==3) Threshold1[i] <= (data_flash4_reg>=trigthresh && data_flash4_reg<=trigthreshtwo);
Threshold2[i] <= Threshold1[i];
if (triggertype2[0]) begin
if (triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 0;
if (Threshold3[i]) begin
if (triggertot[ram_width]) begin
if (downsamplego) begin
if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
end
else begin
if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
if (Threshold3[i]>triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 1;
Threshold3[i] <= 0;
end
end
else if (Threshold1[i] & ~Threshold2[i]) begin
Threshold3[i] <= 1;
end
end
else selftrigtemp[i] <= (Threshold1[i] & ~Threshold2[i]);
end
else begin
if (triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 0;
if (Threshold3[i]) begin
if (triggertot[ram_width]) begin
if (downsamplego) begin
if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
end
else begin
if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
if (Threshold3[i]>triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 1;
Threshold3[i] <= 0;
end
end
else if (~Threshold1[i] & Threshold2[i]) begin
Threshold3[i] <= 1;
end
end
else selftrigtemp[i] <= (~Threshold1[i] & Threshold2[i]);
end
i=i+1;
end
end
reg[12:0] ext_trig_in_delay_bits=0;
reg ext_trig_in_delayed;
always @(posedge clk_flash) begin
ext_trig_in_delayed <= ext_trig_in_delay_bits[ext_trig_delay];
ext_trig_in_delay_bits <= {ext_trig_in_delay_bits[12-1:0], ext_trig_in};
end
reg[31:0] thecounter;
reg[1:0] nselftrigstemp[4];
reg[7:0] selftrigtemphold[4];
always @(posedge clk_flash) begin
if (Trigger) thecounter<=0; else thecounter<=thecounter+1;
i=0;
while (i<4) begin
if (selftrigtemp[i]) selftrigtemphold[i]<=selftrigtempholdtime;
else if (selftrigtemphold[i]>0 && downsamplego) selftrigtemphold[i]<=selftrigtemphold[i]-1;
if (allowsamechancoin) nselftrigstemp[i] <= (trigchannels[(i)%4]&&selftrigtemphold[(i)%4]>0) + (trigchannels[(i+1)%4]&&selftrigtemphold[(i+1)%4]>0) + (trigchannels[(i+2)%4]&&selftrigtemphold[(i+2)%4]>0) + (trigchannels[(i+3)%4]&&selftrigtemphold[(i+3)%4]>0);
else nselftrigstemp[i] <= (trigchannels[(i+1)%4]&&selftrigtemphold[(i+1)%4]>0) + (trigchannels[(i+2)%4]&&selftrigtemphold[(i+2)%4]>0) + (trigchannels[(i+3)%4]&&selftrigtemphold[(i+3)%4]>0);
i=i+1;
end
end
wire selfedgetrig;
assign selfedgetrig = (trigchannels[0]&&selftrigtemp[0]&&nselftrigstemp[0]>=nselftrigcoincidentreq)||
(trigchannels[1]&&selftrigtemp[1]&&nselftrigstemp[1]>=nselftrigcoincidentreq)||
(trigchannels[2]&&selftrigtemp[2]&&nselftrigstemp[2]>=nselftrigcoincidentreq)||
(trigchannels[3]&&selftrigtemp[3]&&nselftrigstemp[3]>=nselftrigcoincidentreq);
wire selftrig;
assign selftrig = selfedgetrig || (rollingtrigger&thecounter>=25000000) || (use_ext_trig&ext_trig_in_delayed);
output reg[31:0] trigratecounter=0;
input trigratecountreset;
reg [7:0] selfedgetrigdeadtime=0;
always @(posedge clk_flash) begin
if (selfedgetrig && selfedgetrigdeadtime==0) begin
trigratecounter = trigratecounter+1;
selfedgetrigdeadtime<=selftrigtempholdtime;
end
if (selfedgetrigdeadtime>0 && downsamplego) selfedgetrigdeadtime<=selfedgetrigdeadtime-1;
if (trigratecountreset) trigratecounter=0;
end
always @(posedge clk_flash)
if (noselftrig) Trigger = trig_in[1];
else if (imthefirst & imthelast) Trigger = selftrig;
else if (imthefirst) Trigger = selftrig||trig_in[1];
else if (imthelast) Trigger = selftrig||trig_in[0];
else Trigger = selftrig||trig_in[0]||trig_in[1];
always @(posedge clk_flash)
if (noselftrig) trig_out[0] = 0;
else if (imthefirst) trig_out[0] = selftrig;
else trig_out[0] = trig_in[0]||selftrig;
always @(posedge clk_flash)
if (noselftrig) trig_out[1] = trig_in[1];
else if (imthelast) trig_out[1] = selftrig;
else trig_out[1] = trig_in[1]||selftrig;
reg Ttrig[4];
reg[3:0] Tcounter[4];
reg[7:0] Tcounter_test_countdown;
output reg[7:0] delaycounter;
reg[7:0] spareleftcounter;
always @(posedge clk_flash) begin
if (spareleft) begin
if (spareleftcounter<205) begin
spareleftcounter<=spareleftcounter+1;
Ttrig[0]<=0; Ttrig[1]<=0; Ttrig[2]<=0; Ttrig[3]<=0;
Tcounter[0]<=0; Tcounter[1]<=0; Tcounter[2]<=0; Tcounter[3]<=0;
end
else begin
Ttrig[0] <= (Tcounter_test_countdown!=0);
if (Tcounter_test_countdown) Tcounter_test_countdown <= Tcounter_test_countdown-1;
end
end
else begin
i=0; while (i<4) begin
if (selftrigtemp[i]) Tcounter[i]<=4;
else if (Tcounter[i]) Tcounter[i]<=Tcounter[i]-1;
Ttrig[i] <= (Tcounter[i]>0);
i=i+1;
end
Tcounter_test_countdown <= 219;
spareleftcounter<=0;
end
end
reg[1:0] Pulsecounter=0;
always @(posedge clk_flash) begin
trigout[0]<=(Ttrig[Pulsecounter]);
Pulsecounter<=Pulsecounter+1;
end
assign spareright = spareleft;
reg startAcquisition;
always @(posedge clk) begin
if(~startAcquisition) startAcquisition <= startTrigger;
else if(AcquiringAndTriggered2) startAcquisition <= 0;
end
reg startAcquisition1; always @(posedge clk_flash) startAcquisition1 <= startAcquisition;
reg startAcquisition2; always @(posedge clk_flash) startAcquisition2 <= startAcquisition1;
localparam INIT=0, PREACQ=1, WAITING=2, POSTACQ=3;
reg[2:0] state=INIT;
reg [23:0] downsamplecounter;
reg [maxhighres:0] highrescounter;
wire downsamplego;
assign downsamplego = downsamplecounter[downsample2] || downsample2==0;
always @(posedge clk_flash) begin
nsmp2<=nsmp;
triggertype2<=triggertype;
downsample2<=downsample;
case (state)
INIT: begin
if (startAcquisition2) begin
samplecount <= 0;
Acquiring <= 1;
HaveFullData <= 0;
PreOrPostAcquiring <= 1;
downsamplecounter=1;
highrescounter=0;
highres1=0;
highres2=0;
highres3=0;
highres4=0;
state=PREACQ;
end
end
PREACQ: begin
if( (samplecount==triggerpoint) ) begin
PreOrPostAcquiring <= 0;
state=WAITING;
end
end
WAITING: begin
if(Trigger) begin
AcquiringAndTriggered <= 1;
PreOrPostAcquiring <= 1;
wraddress_triggerpoint2 <= wraddress;
state=POSTACQ;
end
end
POSTACQ: begin
if(samplecount==nsmp2) begin
Acquiring <= 0;
AcquiringAndTriggered <= 0;
HaveFullData <= 1;
PreOrPostAcquiring <= 0;
state=INIT;
end
end
endcase
downsamplecounter=downsamplecounter+1;
if (highres) begin
highrescounter=highrescounter+1;
highres1=highres1+data_flash1_reg;
highres2=highres2+data_flash2_reg;
highres3=highres3+data_flash3_reg;
highres4=highres4+data_flash4_reg;
if (downsamplego || highrescounter[maxhighres]) begin
highrescounter=0;
if (downsample2>maxhighres) begin
dout1=highres1>>maxhighres;
dout2=highres2>>maxhighres;
dout3=highres3>>maxhighres;
dout4=highres4>>maxhighres;
end
else begin
dout1=highres1>>downsample2;
dout2=highres2>>downsample2;
dout3=highres3>>downsample2;
dout4=highres4>>downsample2;
end
highres1=0;
highres2=0;
highres3=0;
highres4=0;
end
end
else begin
dout1=data_flash1_reg;
dout2=data_flash2_reg;
dout3=data_flash3_reg;
dout4=data_flash4_reg;
end
if (downsamplego) begin
downsamplecounter=1;
if(Acquiring) wraddress <= wraddress + 1;
if(PreOrPostAcquiring) samplecount <= samplecount + 1;
end
end
reg AcquiringAndTriggered1; always @(posedge clk) AcquiringAndTriggered1 <= AcquiringAndTriggered;
reg AcquiringAndTriggered2; always @(posedge clk) AcquiringAndTriggered2 <= AcquiringAndTriggered1;
reg HaveFullData1; always @(posedge clk) HaveFullData1 <= HaveFullData;
reg HaveFullData2; always @(posedge clk) HaveFullData2 <= HaveFullData1;
always @(posedge clk) begin
wraddress_triggerpoint=wraddress_triggerpoint2;
if (startAcquisition) data_ready=0;
else if (HaveFullData2) data_ready=1;
end
endmodule | 93 |
5,027 | data/full_repos/permissive/112978342/max10_adc_firmware/oscillo_sometrigger.v | 112,978,342 | oscillo_sometrigger.v | v | 55 | 118 | [] | [] | [] | [(1, 54)] | null | null | 1: b"%Error: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo_sometrigger.v:44: Cannot find file containing module: 'async_transmitter'\nasync_transmitter async_txd(.clk(clk), .TxD(TxD), .TxD_start(TxD_start), .TxD_busy(TxD_busy), .TxD_data(ram_output));\n^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112978342/max10_adc_firmware,data/full_repos/permissive/112978342/async_transmitter\n data/full_repos/permissive/112978342/max10_adc_firmware,data/full_repos/permissive/112978342/async_transmitter.v\n data/full_repos/permissive/112978342/max10_adc_firmware,data/full_repos/permissive/112978342/async_transmitter.sv\n async_transmitter\n async_transmitter.v\n async_transmitter.sv\n obj_dir/async_transmitter\n obj_dir/async_transmitter.v\n obj_dir/async_transmitter.sv\n%Error: data/full_repos/permissive/112978342/max10_adc_firmware/oscillo_sometrigger.v:49: Cannot find file containing module: 'LPM_RAM_DP'\nLPM_RAM_DP #(.LPM_WIDTH(8), .LPM_WIDTHAD(9)) ram_flash (\n^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 5,421 | module | module oscillo(clk, RxD, TxD, clk_flash, data_flash);
input clk;
input RxD;
output TxD;
input clk_flash;
input [7:0] data_flash;
reg startAcquisition;
wire AcquisitionStarted;
always @(posedge clk)
if(~startAcquisition) startAcquisition <= RxD;
else if(AcquisitionStarted) startAcquisition <= 0;
reg startAcquisition1; always @(posedge clk_flash) startAcquisition1 <= startAcquisition ;
reg startAcquisition2; always @(posedge clk_flash) startAcquisition2 <= startAcquisition1;
reg Acquiring;
always @(posedge clk_flash)
if(~Acquiring) Acquiring <= startAcquisition2;
else if(&wraddress) Acquiring <= 0;
reg [8:0] wraddress;
always @(posedge clk_flash) if(Acquiring) wraddress <= wraddress + 1;
reg Acquiring1; always @(posedge clk) Acquiring1 <= Acquiring;
reg Acquiring2; always @(posedge clk) Acquiring2 <= Acquiring1;
assign AcquisitionStarted = Acquiring2;
reg [8:0] rdaddress;
reg Sending;
wire TxD_busy;
always @(posedge clk)
if(~Sending) Sending <= AcquisitionStarted;
else if(~TxD_busy) begin
rdaddress <= rdaddress + 1;
if(&rdaddress) Sending <= 0;
end
wire TxD_start = ~TxD_busy & Sending;
wire rden = TxD_start;
wire [7:0] ram_output;
async_transmitter async_txd(.clk(clk), .TxD(TxD), .TxD_start(TxD_start), .TxD_busy(TxD_busy), .TxD_data(ram_output));
reg [7:0] data_flash_reg; always @(posedge clk_flash) data_flash_reg <= data_flash;
LPM_RAM_DP #(.LPM_WIDTH(8), .LPM_WIDTHAD(9)) ram_flash (
.data(data_flash_reg), .wraddress(wraddress), .wren(Acquiring), .wrclock(clk_flash),
.q(ram_output), .rdaddress(rdaddress), .rden(rden), .rdclock(clk)
);
endmodule | module oscillo(clk, RxD, TxD, clk_flash, data_flash); |
input clk;
input RxD;
output TxD;
input clk_flash;
input [7:0] data_flash;
reg startAcquisition;
wire AcquisitionStarted;
always @(posedge clk)
if(~startAcquisition) startAcquisition <= RxD;
else if(AcquisitionStarted) startAcquisition <= 0;
reg startAcquisition1; always @(posedge clk_flash) startAcquisition1 <= startAcquisition ;
reg startAcquisition2; always @(posedge clk_flash) startAcquisition2 <= startAcquisition1;
reg Acquiring;
always @(posedge clk_flash)
if(~Acquiring) Acquiring <= startAcquisition2;
else if(&wraddress) Acquiring <= 0;
reg [8:0] wraddress;
always @(posedge clk_flash) if(Acquiring) wraddress <= wraddress + 1;
reg Acquiring1; always @(posedge clk) Acquiring1 <= Acquiring;
reg Acquiring2; always @(posedge clk) Acquiring2 <= Acquiring1;
assign AcquisitionStarted = Acquiring2;
reg [8:0] rdaddress;
reg Sending;
wire TxD_busy;
always @(posedge clk)
if(~Sending) Sending <= AcquisitionStarted;
else if(~TxD_busy) begin
rdaddress <= rdaddress + 1;
if(&rdaddress) Sending <= 0;
end
wire TxD_start = ~TxD_busy & Sending;
wire rden = TxD_start;
wire [7:0] ram_output;
async_transmitter async_txd(.clk(clk), .TxD(TxD), .TxD_start(TxD_start), .TxD_busy(TxD_busy), .TxD_data(ram_output));
reg [7:0] data_flash_reg; always @(posedge clk_flash) data_flash_reg <= data_flash;
LPM_RAM_DP #(.LPM_WIDTH(8), .LPM_WIDTHAD(9)) ram_flash (
.data(data_flash_reg), .wraddress(wraddress), .wren(Acquiring), .wrclock(clk_flash),
.q(ram_output), .rdaddress(rdaddress), .rden(rden), .rdclock(clk)
);
endmodule | 93 |
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